Order Now Product Folder Support & Community Tools & Software Technical Documents TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 TPS6214x 3-V to 17-V 2-A Step-Down Converter in 3 x 3 QFN Package 1 Features * * * * * * * * * * * * * * 1 * 3 Description TM DCS-Control Topology Input Voltage Range: 3 V to 17 V Up to 2-A Output Current Adjustable Output Voltage from 0.9 V to 6 V Pin-Selectable Output Voltage (Nominal, +5%) Programmable Soft Start and Tracking Seamless Power-Save Mode Transition Quiescent Current of 17 A (Typical) Selectable Operating Frequency Power-Good Output 100% Duty-Cycle Mode Short-Circuit Protection Over Temperature Protection Pin to Pin Compatible with TPS62130 and TPS62150 Available in a 3-mm x 3-mm, VQFN-16 Package 2 Applications * * * * * * * * Standard 12-V Rail Supplies POL Supply From Single or Multiple Li-Ion Battery Solid-State Disk Drives Embedded Systems LDO Replacement Mobile PCs, Tablet, Modems, Cameras Server, Microserver Data Terminal, Point of Sales (ePOS) The TPS6214x family is an easy-to-use synchronous step-down DC-DC converter optimized for applications with high power density. A high switching frequency of typically 2.5 MHz allows the use of small inductors and provides fast transient response by use of the DCS-ControlTM topology. With their wide operating input voltage range of 3 V to 17 V, the devices are ideally suited for systems powered from either a Li-Ion or other batteries, as well as from 12-V intermediate power rails. It supports up to 2 A of continuous output current at output voltages between 0.9 V and 6 V (with 100% duty-cycle mode). The output voltage start-up ramp is controlled by the soft-start pin, which allows operation as either a standalone power supply or in tracking configurations. Power sequencing is also possible by configuring the Enable (EN) and open-drain Power Good (PG) pins. In Power Save Mode, the devices draw quiescent current of about 17 A from VIN. Power Save Mode, entered automatically and seamlessly if the load is small, maintains high efficiency over the entire load range. In Shutdown Mode, the device is turned off and current consumption is less than 2 A. The device, available in adjustable and fixed output voltage versions, is packaged in a 16-pin VQFN package measuring 3 mm x 3 mm (RGT). Device Information(1) PART NUMBER TPS6214x PACKAGE VQFN (16) BODY SIZE (NOM) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Schematic (3 .. 17)V Efficiency vs Output Current 10uF PVIN SW AVIN VOS PG EN 100 1.8V / 2A 2.2 H 90 100k 22uF SS/TR 3.3nF FB DEF AGND FSW PGND Efficiency (%) TPS62141 VIN=5V 80 VIN=12V VIN=17V 70 60 Copyright (c) 2016, Texas Instruments Incorporated 50 40 0.0 VOUT=3.3V fsw=1.25MHz 0.4 0.8 1.2 Output Current (A) 1.6 2.0 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 5 6 7 Detailed Description .............................................. 8 8.1 8.2 8.3 8.4 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Overview ................................................................... 8 Functional Block Diagrams ....................................... 8 Feature Description................................................... 9 Device Functional Modes........................................ 11 Application and Implementation ........................ 13 9.1 Application Information............................................ 13 9.2 Typical Application .................................................. 13 9.3 System Examples ................................................... 25 10 Power Supply Recommendations ..................... 28 11 Layout................................................................... 29 11.1 Layout Guidelines ................................................. 29 11.2 Layout Example .................................................... 29 11.3 Thermal Considerations ........................................ 30 12 Device and Documentation Support ................. 31 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 32 32 32 32 13 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2015) to Revision E Page * Added "Pin to Pin Compatible with TPS62130 and TPS62150" to Features list .................................................................. 1 * Changed the TJ MAX value From: 125C To: 150C in the Absolute Maximum Rating ....................................................... 5 * Changed the Thermal Information values ............................................................................................................................. 5 * Changed (TJ = -40C to 85C) To: (TJ = -40C to 125C) in the Electrical Characteristics conditions ............................... 6 * Added a test condition for IQ at TA = -40C to +85C in the Electrical Characteristics ........................................................ 6 * Added Table 1 and Table 2 ................................................................................................................................................. 10 * Added indicators (C1, C3, and C5) for capacitances to Figure 7......................................................................................... 13 * Added Switching Frequency graphs for 1.0-V, 1.8-V, and 5.0-V applications ( Figure 24 through Figure 31) .................... 20 * Changed Layout Example .................................................................................................................................................... 29 Changes from Revision C (August 2015) to Revision D * Page Changed VTH_PG Falling (%VOUT) specification MAX value from "93%" to "94%" in the Electrical Characteristics ................ 6 Changes from Revision B (June 2013) to Revision C * 2 Page Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 Changes from Revision A (October 2012) to Revision B Page * Added new device version TPS62140A to the data sheet ..................................................................................................... 1 * Added text to Power Good section regarding the TPS62140A function .............................................................................. 10 * Added pin option to the footnote for Pin-Selectable Output (DEF) section. ......................................................................... 10 * Added text to Frequency Selection (FSW) section regarding pin control............................................................................. 11 * Added text to Tracking Function section for clarification. ..................................................................................................... 17 * Added application example with regard to new version TPS62140A................................................................................... 25 Changes from Original (November 2011) to Revision A Page * Changed the description of the AGND pin, and added Note 3. ............................................................................................. 4 * Added values to the Initial output voltage accuracy for TA = -10C to 85C ......................................................................... 6 * Added text to the Power-Save Mode Operation section following Equation 1 ..................................................................... 11 * Changed the Layout Considerations section........................................................................................................................ 29 * Changed Layout Example .................................................................................................................................................... 29 Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 3 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 5 Device Comparison Table PART NUMBER OUTPUT VOLTAGE Power Good Logic Level (EN=Low) TPS62140 adjustable High Impedance TPS62140A adjustable Low TPS62141 1.8 V High Impedance TPS62142 3.3 V High Impedance TPS62143 5.0 V High Impedance 6 Pin Configuration and Functions SW 3 PG 4 PGND VOS EN 13 Exposed Thermal Pad 5 6 7 8 DEF 2 14 FSW SW 15 AGND 1 16 FB SW PGND RGT Package 16-Pin VQFN Top View 12 PVIN 11 PVIN 10 AVIN 9 SS/TR Pin Functions PIN (1) NO. NAME 4 DESCRIPTION 1,2,3 SW O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. 4 PG O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires pull-up resistor) 5 FB I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to connect FB to AGND on fixed output voltage versions for improved thermal performance. 6 AGND 7 FSW I Switching Frequency Select (Low 2.5MHz, High 1.25MHz (2) for typical operation) (3) 8 DEF I Output Voltage Scaling (Low = nominal, High = nominal + 5%) (3) 9 SS/TR I Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing. 10 AVIN I Supply voltage for control circuitry. Connect to same source as PVIN. 11,12 PVIN I Supply voltage for power stage. Connect to same source as AVIN. 13 EN I Enable input (High = enabled, Low = disabled) (3) 14 VOS I Output voltage sense pin and connection for the control loop circuitry. 15,16 (1) (2) (3) I/O Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. PGND Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. Exposed Thermal Pad Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability. For more information about connecting pins, see the Detailed Description and Application and Implementation sections. Connect FSW to VOUT or PG in this case. An internal pull-down resistor keeps the logic level low, if pin is floating. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating junction temperature range (unless otherwise noted) Pin voltage (2) Power-good sink current Temperature (1) (2) MIN MAX AVIN, PVIN -0.3 20 EN, SS/TR -0.3 VIN+0.3 SW -0.3 VIN+0.3 V DEF, FSW, FB, PG, VOS -0.3 7 V 10 mA Operating junction temperature, TJ -40 150 Storage temperature, Tstg -65 150 PG UNIT V C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network ground terminal. 7.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3) 500 UNIT V ESD testing is performed according to the respective JESD22 JEDEC standard. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM Supply voltage, VIN (at AVIN and PVIN) Operating junction temperature, TJ MAX UNIT 3 17 V -40 125 C 7.4 Thermal Information THERMAL METRIC (1) TPS6214x RGT 16 PINS UNIT RJA Junction-to-ambient thermal resistance 45 C/W RJC(top) Junction-to-case(top) thermal resistance 53.6 C/W RJB Junction-to-board thermal resistance 17.4 C/W JT Junction-to-top characterization parameter 1.1 C/W JB Junction-to-board characterization parameter 17.4 C/W RJC(bot) Junction-to-case(bottom) thermal resistance 4.5 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 5 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 7.5 Electrical Characteristics over operating junction temperature (TJ= -40C to 125C), typical values at VIN=12V and TA=25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY Input voltage range (1) VIN IQ ISD VUVLO Operating quiescent current EN = High, IOUT = 0 mA, device not switching Shutdown current (2) EN = Low Undervoltage lockout threshold TSD 3 TA = -40C to +85C TA = -40C to +85C Falling input voltage (PWM mode operation) 2.6 Hysteresis 17 17 30 17 25 1.5 25 1.5 4 2.7 2.8 200 Thermal shutdown temperature A A V mV 160 Thermal shutdown hysteresis V C 20 CONTROL (EN, DEF, FSW, SS/TR, PG) VH High level input threshold voltage (EN, DEF, FSW) VL Low level input threshold voltage (EN, DEF, FSW) ILKG Input leakage current (EN, DEF, FSW) 0.9 0.65 0.45 EN = VIN or GND; DEF, FSW = VOUT or GND V 0.3 V A 0.01 1 Rising (%VOUT) 92% 95% 98% Falling (%VOUT) 87% 90% 94% VTH_PG Power-good threshold voltage VOL_PG Power-good output low voltage IPG= -2 mA 0.07 0.3 V ILKG_PG Input leakage current (PG) VPG = 1.8 V 1 400 nA ISS/TR SS/TR pin source current 2.5 2.7 A VIN 6 V 90 170 VIN = 3 V 120 VIN 6 V 40 VIN = 3 V 50 2.3 POWER SWITCH High-side MOSFET ON-resistance rDS(on) Low-side MOSFET ON-resistance ILIMF High-side MOSFET forward current limit (3) VIN = 12 V, TA = 25C Input leakage current (FB) TPS62140, VFB = 0.8 V Output voltage range (TPS62140) VIN VOUT DEF (output voltage programming) DEF = 0 (GND) VOUT DEF = 1 (VOUT) VOUT + 5% 2.45 70 m m 3 3.5 A 1 100 nA 6.0 V OUTPUT ILKG_FB VOUT (1) (2) (3) (4) (5) 6 Initial output voltage accuracy (4) 0.9 PWM mode operation, VIN VOUT + 1 V 785.6 800 814. 4 PWM mode operation, VIN VOUT +1 V, TA = -10C to 85C 788.0 800 812. 8 Power-save mode operation, COUT=22F 781.6 800 822. 4 mV Load regulation (5) VIN = 12 V, VOUT = 3.3 V, PWM mode operation 0.05 %/A Line regulation (5) 3 V VIN 17 V, VOUT = 3.3 V, IOUT = 1 A, PWM mode operation 0.02 %/V The device is still functional down to undervoltage lockout (see parameter VUVLO). Current into AVIN + PVIN pins This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection section). This is the accuracy provided at the FB pin for the adjustable VOUT version (line and load regulation effects are not included). For the fixed-voltage versions the (internal) resistive divider is included. Line and load regulation depend on external component selection and layout (see Figure 22 and Figure 23). Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 7.6 Typical Characteristics Figure 1. Quiescent Current Figure 2. Shutdown Current 100.0 200.0 160.0 125C RDSon Low-Side (m) RDSon High-Side (m) 180.0 140.0 120.0 85C 100.0 25C 80.0 60.0 -10C -40C 40.0 80.0 125C 60.0 40.0 85C 25C -10C 20.0 -40C 20.0 0.0 0.0 3.0 6.0 9.0 12.0 Input Voltage (V) 15.0 18.0 20.0 Figure 3. High-Side Switch Resistance Copyright (c) 2011-2016, Texas Instruments Incorporated G001 0.0 0.0 3.0 6.0 9.0 12.0 Input Voltage (V) 15.0 18.0 20.0 G001 Figure 4. Low-Side Switch Resistance Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 7 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The TPS6214x synchronous switched-mode power converters are based on DCS-ControlTM (Direct Control with Seamless Transition into Power-Save Mode), an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control including an ac loop directly associated with the output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady-state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors. The DCS-ControlTM topology supports Pulse Width Modulation (PWM) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5 MHz or 1.25MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode, the switching frequency decreases linearly with the load current. Because DCS-ControlTM supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage. Fixed output-voltage versions provide the smallest solution size and lowest current consumption, requiring only 3 external components. An internal current limit supports nominal output currents of up to 2 A. The TPS6214x family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. 8.2 Functional Block Diagrams PG Soft start Thermal Shtdwn UVLO AVIN PVIN PVIN PG control HS lim comp EN* SW SS/TR power control control logic gate drive SW * DEF SW FSW* comp LS lim VOS direct control & compensation ramp _ FB comparator + timer tON error amplifier DCS - ControlTM AGND PGND PGND Copyright (c) 2016, Texas Instruments Incorporated * This pin is connected to a pull down resistor internally (see Feature Description section) Figure 5. TPS62140 and TPS62140A (Adjustable Output Voltage) 8 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 Functional Block Diagrams (continued) PG Soft start Thermal Shtdwn UVLO AVIN PVIN PVIN PG control HS lim comp EN* SW SS/TR power control control logic gate drive SW * DEF SW FSW* comp LS lim VOS direct control & compensation ramp _ FB* comparator + timer tON error amplifier DCS - ControlTM AGND PGND PGND Copyright (c) 2016, Texas Instruments Incorporated * This pin is connected to a pull down resistor internally (see Feature Description section) Figure 6. TPS62141/2/3 (Fixed Output Voltage) space 8.3 Feature Description 8.3.1 Enable / Shutdown (EN) When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5A. During shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must be set externally to High or Low. An internal pull-down resistor of about 400k is connected and keeps EN logic low, if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple power rails. 8.3.2 Soft-Start / Tracking (SS/TR) The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush current and ensures a controlled output-voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of about 50 s, and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See Figure 40 and Figure 41 for typical start-up operation. Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 9 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com Feature Description (continued) Using a very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. There is no theoretical limit for the longest startup time. The TPS6214x can start into a pre-biased output. During monotonic pre-biased startup, both the power MOSFETs are not allowed to turn on until the devices internal ramp sets an output voltage above the pre-bias voltage. As long as the output is below about 0.5 V, a reduced current limit of typically 1.6 A is set internally. If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new start-up sequence as set by the SS/TR connection. A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in both directions, up and down (see Application and Implementation). 8.3.3 Power Good (PG) The TPS6214x has a built-in power-good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and maintain its specified logic-low level. With TPS62140 it is high-impedance when the device is turned off due to EN, UVLO, or thermal shutdown. TPS62140A features PG=Low in this case and can be used to actively discharge Vout (see Figure 47). VIN must remain present for the PG pin to stay Low. See SLVA644 for application details. If not used, the PG pin should be connected to GND but may be left floating. space Table 1. Power Good Pin Logic Table (TPS62140) PG Logic Status Device State High Impedance VFB VTH_PG Enable (EN=High) Low VFB VTH_PG Shutdown (EN=Low) UVLO Thermal Shutdown Power Supply Removal 0.7 V < VIN < VUVLO TJ > TSD VIN < 0.7 V space Table 2. Power Good Pin Logic Table (TPS62140A) PG Logic Status Device State High Impedance VFB VTH_PG Enable (EN=High) Low VFB VTH_PG Shutdown (EN=Low) UVLO 0.7 V < VIN < VUVLO Thermal Shutdown TJ > TSD Power Supply Removal VIN < 0.7 V space 8.3.4 Pin-Selectable Output Voltage (DEF) The output voltage of the TPS6214x devices can be increased by 5% above the nominal voltage by setting the DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed information on voltage margining using TPS6214x can be found in SLVA489. A pull down resistor of about 400 k is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after initially set to Low. The resistor is disconnected if the pin is set High. (1) 10 Maximum allowed voltage is 7 V. Therefore, it is recommended to connect it to VOUT or PG, not VIN. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 8.3.5 Frequency Selection (FSW) To get high power density with very small solution size, a high switching frequency allows the use of small external components for the output filter. However switching losses increase with the switching frequency. If efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally connected to the pin, acting the same way as at the DEF pin (see above). 8.3.6 Undervoltage Lockout (UVLO) If the input voltage drops, the undervoltage lockout prevents incorrect operation of the device by switching off both the power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV. 8.3.7 Thermal Shutdown The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160C (typ.), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG goes high-impedance. When TJ decreases below the hysteresis amount, the converter resumes normal operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20C is implemented on the thermal shutdown temperature. 8.4 Device Functional Modes 8.4.1 Pulse-Width Modulation (PWM) Operation The TPS6214x operates with pulse-width modulation in continuous-conduction mode (CCM) with a nominal switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the device enters power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor ripple current. 8.4.2 Power Save Mode Operation The TPS6214x enters its built-in power-save mode seamlessly if the load current decreases. This secures a high efficiency in light-load operation. The device remains in power-save mode as long as the inductor current is discontinuous. In power-save mode, the switching frequency decreases linearly with the load current, maintaining high efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and is seamless in both directions. TPS6214x includes a fixed-on-time circuit. An estimate for this on-time, in steady-state operation with FSW=Low, is: space t ON = VOUT x 400ns V IN (1) space For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can reach its minimum value at high duty cycles. The output voltage remains regulated in such case. Using tON, the typical peak inductor current in Power Save Mode can be approximated by: space Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 11 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com Device Functional Modes (continued) I LPSM ( peak ) = (V IN - VOUT ) x t ON L (2) When VIN decreases to typically 15% above VOUT, the TPS6214x does not enter power-save mode, regardless of the load current. The device maintains output regulation in PWM mode. 8.4.3 100% Duty-Cycle Operation The duty cycle of the buck converter is given by D = Vout/Vin and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty-cycle operation, turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal setpoint. This allows the conversion of small input-to-output voltage differences, e.g., for longest operation time of battery-powered applications. In 100% duty-cycle mode, the low-side FET is switched off. The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, is calculated as: space VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL ) where * * * IOUT is the output current. RDS(on) is the RDS(on) of the high-side FET. RL is the DC resistance of the inductor used. (3) 8.4.4 Current Limit and Short Circuit Protection The TPS6214x devices are protected against heavy load and short-circuit events. If a short circuit is detected (VOUT drops below 0.5 V), the current limit is reduced to 1.6 A, typically. If the output voltage rises above 0.5 V, the device runs in normal operation again. At heavy loads, the current limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot through current, then the low-side FET switches on to allow the inductor current to decrease. The low-side current limit is typically 2.4A. The high-side FET turns on again only if the current in the low-side FET has decreased below the low-side current-limit threshold. The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit is calculated as follows: space I peak ( typ ) = I LIMF + VL x t PD L where * * * * ILIMF is the static current limit, specified in the Electrical Characteristics L is the inductor value VL is the voltage across the inductor (VIN - VOUT) tPD is the internal propagation delay (4) space The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high-side switch peak current is calculated as follows: space I peak (typ ) = I LIMF + 12 (VIN - VOUT )x 30ns L Submit Documentation Feedback (5) Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS62140 is a switched mode step-down converter, able to convert a 3 V to 17 V input voltage into a 0.9 V to 6 V output voltage, providing up to 2 A. It needs a minimum amount of external components. Apart from the LC output filter and the input capacitor, only the TPS62140 (TPS62140A) with an adjustable output voltage needs an additional resistive divider to set the output voltage level. 9.2 Typical Application space (3 .. 17)V VOUT / 2A 2.2H C1 10uF PVIN SW AVIN VOS EN 100k PG R1 TPS62140 SS/TR C5 3.3nF C3 22uF FB DEF AGND FSW PGND R2 Copyright (c) 2016, Texas Instruments Incorporated Figure 7. 3.3V/2A Step-Down Converter 9.2.1 Design Requirements The following design guideline provides a component selection to operate the device within the recommended operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution size and lowest output voltage ripple. For highest efficiency set FSW = High and the device operates at the lower switching frequency. For smallest solution size and lowest output voltage ripple set FSW = Low and the device operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT = 3.3 V and T = 25C, using the external components of Table 3. 9.2.2 Detailed Design Procedure The component selection used for measurements is given as follows: Table 3. List of Components (1) REFERENCE DESCRIPTION IC 17-V, 2-A step-down converter, QFN L1 2.2-H, 3.1-A, 0.165 in x 0.165 in C1 10-F, 25-V, ceramic, 1210 Standard C3 22-F, 6.3-V, ceramic, 0805 Standard C5 3300-pF, 25-V, ceramic, 0603 R1 Dependent on Vout R2 Dependent on Vout R3 100-k, chip, 0603, 1/16W, 1% (1) MANUFACTURER TPS62140RGT, Texas Instruments XFL4020-222MEB, Coilcraft Standard See Third-Party Products Disclaimer Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 13 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 9.2.2.1 Programming the Output Voltage While the output voltage of the TPS62140 (TPS62140A) is adjustable, the TPS62141/2/3 are programmed to fixed output voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. It is recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is regulated to 800 mV. The value of the output voltage is set by the selection of the resistive divider from Equation 6. It is recommended to choose resistor values which allow a current of at least 2 A, meaning the value of R2 should not exceed 400 k. Lower resistor values are recommended for highest accuracy and mostrobust design. For applications requiring lowest current consumption, the use of fixed output-voltage versions is recommended. spacing o aeV R1 = R 2 c OUT - 1/ o e 0.8V (6) spacing In case the FB pin is opened, the device clamps the output voltage at the VOS pin internally to about 7.4 V. 9.2.2.2 External Component Selection The external components have to fulfill the needs of the application, but also the stability criteria of the devices control loop. The TPS6214X is optimized to work within a range of external components. The LC output filter's inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the corner frequency of the converter (see Output Filter and Loop Stability section). Table 4 can be used to simplify the output filter component selection. Checked cells represent combinations that are proven for stability by simulation and lab test. Further combinations should be checked for each individual application. See SLVA463 for details. Table 4. Recommended LC Output Filter Combinations (1) 4.7 F 10 F 22 F 47 F 100 F 200 F 2.2 H (2) 3.3 H 400 F 0.47 H 1 H 4.7 H (1) (2) The values in the table are nominal values. The effective capacitance was considered to vary by +20% and -50%. This LC combination is the standard value and recommended for most applications. spacing TPS6214X can be run with an inductor as low as 1 H or 2.2 H. FSW should be set Low in this case. However, for applications running with the low-frequency setting (FSW = High) or with low input voltages, 3.3 H is recommended. 9.2.2.2.1 Inductor Selection The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point, and efficiency. In addition, the inductor selected must be rated for appropriate saturation current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static load conditions. spacing I L(max) = I OUT (max) + DI L(max) 2 (7) spacing 14 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 DI L(max) = VOUT V ae c 1 - OUT c V IN (max) xc L xf c (min) SW c e o / / / / / o where * * * * IL(max) is the maximum inductor current IL is the peak-to-peak inductor ripple current L(min) is the minimum effective inductor value fSW is the actual PWM switching frequency (8) spacing Calculating the maximum inductor current using the actual operating conditions gives the minimum required inductor saturation current. It is recommended to add a margin of about 20%. A larger inductor value is also useful to get lower ripple current, but increases the transient response time and size as well. The following inductors have been used with the TPS6214x and are recommended for use: Table 5. List of Inductors (1) (2) TYPE INDUCTANCE (H) CURRENT (A) (1) DIMENSIONS [L x B x H] (mm) MANUFACTURER (2) XFL4020-222ME_ 2.2 H, 20% 3.5 4 x 4 x 2.1 Coilcraft XFL4020-332ME_ 3.3 H, 20% 2.9 4 x 4 x 2.1 Coilcraft IHLP1212BZ-11 2.2 H, 20% 3.0 3 x 3.6 x 2 Vishay IHLP1616AB-11 2.2 H, 20% 2.75 4.05 x 4.45 x 1.2 Vishay DEM4518C 1235AS-H-3R3M 3.3 H, 20% 2.5 4.5 x 4.7 x 1.9 Toko Lower of IRMS at 40C rise or ISAT at 30% drop. See Third-Party Products Disclaimer spacing The inductor value also determines the load current at which the power-save mode is entered: spacing I load ( PSM ) = 1 DI L 2 (9) spacing Using Equation 8, this current level can be adjusted by changing the inductor value. 9.2.2.2.2 Capacitor Selection 9.2.2.2.2.1 Output Capacitor The recommended value for the output capacitor is 22 F. The architecture of the TPS6214X allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low outputvoltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value can have some advantages, like smaller voltage ripple and a tighter DC output accuracy in power-save mode (see SLVA463). Note: In power-save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low ripple. Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 15 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 9.2.2.2.2.2 Input Capacitor For most applications, 10 F is sufficient and is recommended, though a larger value reduces input-current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic capacitor is recommended for best filtering and should be placed between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied from the same input source, it is recommended to place a capacitance of 0.1 uF from AVIN to AGND, to avoid potential noise coupling. 9.2.2.2.2.3 Soft-Start Capacitor A capacitance connected between the SS/TR pin and AGND allows a user-programmable start-up slope of the output voltage. A constant-current source provides 2.5 A to charge the external capacitance. The capacitor required for a given soft-start ramp time for the output voltage is given by: spacing C SS = t SS x 2.5mA 1.25V [F ] where * * CSS is the capacitance (F) required at the SS/TR pin tSS is the desired soft-start ramp time (s). (10) spacing NOTE DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a strong influence on the final effective capacitance. Therefore, the right capacitor value must be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. spacing 9.2.2.3 Tracking Function If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the FB pin tracks the SS/TR pin voltage as described in Equation 11 and shown in Figure 8. spacing VFB 0.64 x VSS / TR (11) spacing VSS/ TR [V] 1.2 0.8 0.4 0.2 0.4 0.6 VFB [V] 0.8 Figure 8. Voltage Tracking Relationship 16 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V. If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to zero, independent of the tracking voltage. Figure 9 shows how to connect devices to get ratiometric and simultaneous sequencing by using the tracking function. spacing VOUT1 PVIN SW AVIN VOS EN PG TPS62140 SS/TR FB DEF AGND FSW PGND PVIN SW AVIN VOS VOUT2 R1 EN PG TPS62140 SS/TR R2 FB DEF AGND FSW PGND Copyright (c) 2016, Texas Instruments Incorporated Figure 9. Sequence for Ratiometric and Simultaneous Startup spacing The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as VOUT1. A sequential start-up is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric start-up sequence happens if both supplies are sharing the same soft-start capacitor. Equation 10 calculates the soft-start time, though the SS/TR current must be doubled. Details about these and other tracking and sequencing circuits are found in SLVA470. Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a wider tolerance than specified. Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 17 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 9.2.2.4 Output Filter and Loop Stability The devices of the TPS6214x family are internally compensated to be stable with L-C filter combinations corresponding to a corner frequency to be calculated with Equation 12: spacing f LC = 1 2p L x C (12) spacing Proven nominal values for inductance and ceramic capacitance are given in Table 4 and are recommended for use. Different values may work, but care must be taken on the loop stability, which is affected. More information including a detailed L-C stability matrix can be found in SLVA463. The TPS6214x devices, both fixed and adjustable versions, include an internal 25 pF feed-forward capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the feedback divider, per equations Equation 13 and Equation 14: spacing f zero = 1 2p x R1 x 25 pF (13) spacing f pole = 1 2p x 25 pF ae 1 1 o // x cc + e R1 R 2 o (14) spacing Though the TPS6214x devices are stable without the pole and zero being in a particular location, adjusting their location to the specific needs of the application can provide better performance in power-save mode and/or improved transient response. An external feed-forward capacitor can also be added. A more detailed discussion on the optimization for stability vs transient response can be found in SLVA289 and SLVA466. 18 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 9.2.3 Application Curves VIN = 12 V, VOUT = 3.3 V, TA = 25C, (unless otherwise noted) 100.0 100.0 90.0 90.0 80.0 70.0 VIN=12V VIN=17V Efficiency (%) Efficiency (%) 80.0 60.0 50.0 40.0 30.0 60.0 IOUT=10mA 50.0 IOUT=1mA 40.0 0.001 0.01 0.1 Output Current (A) 1 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 0.0 10 7 8 90.0 80.0 80.0 70.0 60.0 Efficiency (%) Efficiency (%) 100.0 90.0 VIN=17V VIN=12V 40.0 30.0 14 15 16 17 G001 70.0 60.0 IOUT=10mA 50.0 IOUT=1mA IOUT=1A IOUT=100mA 40.0 30.0 20.0 0.001 0.01 0.1 Output Current (A) 1 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 0.0 10 7 8 9 10 G001 VOUT = 5 V 11 12 13 Input Voltage (V) 14 15 16 17 G001 VOUT = 5 V Figure 12. Efficiency With 2.5 MHz Figure 13. Efficiency With 2.5 MHz 100.0 100.0 90.0 90.0 80.0 80.0 70.0 VIN=12V 60.0 VIN=17V Efficiency (%) Efficiency (%) 11 12 13 Input Voltage (V) Figure 11. Efficiency With 1.25 MHz 100.0 VIN=5V 50.0 40.0 30.0 70.0 60.0 IOUT=1A IOUT=100mA IOUT=10mA IOUT=1mA 50.0 40.0 30.0 20.0 0.001 0.01 0.1 Output Current (A) 1 VOUT = 3.3 V VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 10.0 0.0 0.0001 10 VOUT = 5 V Figure 10. Efficiency With 1.25 MHz 50.0 9 G001 VOUT = 5 V 0.0 0.0001 IOUT=1A IOUT=100mA 30.0 20.0 0.0 0.0001 70.0 10.0 10 0.0 4 5 6 G001 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 VOUT = 3.3 V Figure 14. Efficiency With 1.25 MHz Copyright (c) 2011-2016, Texas Instruments Incorporated Figure 15. Efficiency With 1.25 MHz Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 19 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com 100.0 100.0 90.0 90.0 80.0 80.0 70.0 60.0 VIN=12V 50.0 Efficiency (%) Efficiency (%) SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 VIN=17V VIN=5V 40.0 30.0 60.0 IOUT=100mA 50.0 0.001 0.01 0.1 Output Current (A) 1 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 10.0 0.0 10 4 5 100.0 90.0 90.0 80.0 80.0 70.0 VIN=12V 60.0 Efficiency (%) Efficiency (%) 100.0 VIN=17V VIN=5V 40.0 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 70.0 IOUT=1A 60.0 IOUT=100mA 50.0 IOUT=10mA IOUT=1mA 40.0 30.0 20.0 0.001 0.01 0.1 Output Current (A) 1 VOUT=1.8V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=1.8V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 0.0 10 3 4 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 VOUT = 1.8 V Figure 18. Efficiency With 1.25 MHz Figure 19. Efficiency With 1.25 MHz 100.0 100.0 90.0 90.0 80.0 80.0 60.0 VIN=12V Efficiency (%) 70.0 VIN=17V 50.0 VIN=5V 40.0 5 G001 VOUT = 1.8 V Efficiency (%) 8 Figure 17. Efficiency With 2.5 MHz 30.0 30.0 70.0 60.0 IOUT=1A 50.0 IOUT=100mA 40.0 IOUT=10mA IOUT=1mA 30.0 20.0 0.001 0.01 0.1 Output Current (A) 1 VOUT = 0.9 V VOUT=0.9V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=0.9V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 10 0.0 3 4 5 G001 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 VOUT = 0.9 V Figure 20. Efficiency With 1.25 MHz 20 7 VOUT = 3.3 V Figure 16. Efficiency With 2.5 MHz, 50.0 6 G001 VOUT = 3.3 V 0.0 0.0001 IOUT=1A 40.0 20.0 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 10.0 0.0 0.0001 IOUT=1mA IOUT=10mA 30.0 20.0 0.0 0.0001 70.0 Submit Documentation Feedback Figure 21. Efficiency With 1.25 MHz Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 3.40 3.40 Output Voltage (V) Output Voltage (V) VIN=17V 3.35 VIN=12V 3.30 VIN=5V 3.25 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 3.20 0.0001 0.001 0.01 0.1 Output Current (A) 1 3.25 4 4 3.5 3.5 IOUT=2A 3 2.5 2 IOUT=0.5A IOUT=1A 1.5 1 0.5 0 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 4 7 10 13 Input Voltage (V) 16 G001 3 2.5 2 1.5 1 0.5 6 8 10 FSW = Low 12 14 Input Voltage (V) 16 0 18 VOUT = 5 V 1 Output Current (A) 1.5 2 G000 VOUT = 5 V Figure 25. Switching Frequency vs Output Current 4 4 3.5 Switching Frequency (MHz) IOUT=2A 3 2.5 IOUT=0.5A 0.5 FSW = Low 3.5 2 0 G000 Figure 24. Switching Frequency vs Input Voltage IOUT=1A 1.5 1 0.5 0 IOUT=100mA Figure 23. Output Voltage Accuracy (Line Regulation) Switching Frequency (MHz) Switching Frequency (MHz) IOUT=1A G001 Figure 22. Output Voltage Accuracy (Load Regulation) Switching Frequency (MHz) 3.30 3.20 10 IOUT=10mA IOUT=1mA 3.35 3 2.5 2 1.5 1 0.5 4 6 FSW = Low 8 10 12 Input Voltage (V) 14 16 18 VOUT = 3.3 V Figure 26. Switching Frequency vs Input Voltage Copyright (c) 2011-2016, Texas Instruments Incorporated 0 0 G000 FSW = Low 0.5 1 Output Current (A) 1.5 2 G000 VOUT = 3.3 V Figure 27. Switching Frequency vs Output Current Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 21 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com 4 4 3.5 3.5 Switching Frequency (MHz) Switching Frequency (MHz) SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 IOUT=2A 3 2.5 2 IOUT=0.5A 1.5 IOUT=1A 1 0.5 0 3 5 7 9 11 Input Voltage (V) 13 15 2 1.5 1 0 17 0 0.5 1 Output Current (A) G000 VOUT = 1.8 V FSW = Low 2 G000 VOUT = 1.8 V Figure 29. Switching Frequency vs Output Current 3 3 2.5 IOUT=2A 2 1.5 IOUT=1A 1 IOUT=0.5A 0.5 0 3 5 7 9 11 Input Voltage (V) FSW = Low 13 15 2.5 2 1.5 1 0.5 0 17 0 0.5 1 Output Current (A) G000 VOUT = 1 V FSW = Low Figure 30. Switching Frequency vs Input Voltage 2 G000 VOUT = 1 V 4 Output Current (A) 0.03 VIN=17V -40C 3.5 VOUT=3.3V, L=2.2uH (XFL4020) Cout=22uF 0.04 VIN=5V 0.02 2.5 2 85C 1.5 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 0.5 VIN=12V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Output Current (A) 1.6 Figure 32. Output Voltage Ripple Submit Documentation Feedback 1.8 2 G000 25C 3 1 0.01 0 1.5 Figure 31. Switching Frequency vs Output Current 0.05 22 1.5 Figure 28. Switching Frequency vs Input Voltage Switching Frequency (MHz) Switching Frequency (MHz) 2.5 0.5 FSW = Low Output Voltage Ripple (V) 3 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G000 Figure 33. Maximum Output Current Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 100 100 90 80 70 VIN=17V PSRR (dB) PSRR (dB) VIN=5V 80 VIN=12V 70 60 50 40 30 VIN=17V 60 50 40 30 20 20 VOUT=3.3V, IOUT=1A L=2.2uH (XFL4020) Cin=10uF, Cout=22uF 10 0 VIN=12V 90 VIN=5V 10 100 IOUT = 1A 1k 10k Frequency (Hz) 100k 1M fSW = 2.5 MHz VOUT = 3.3 V With 50 mV/div Figure 36. PWM-PSM-Transition Figure 38. Line Transient Response of Figure 37, Rising Edge Copyright (c) 2011-2016, Texas Instruments Incorporated 0 10 100 G000 Figure 34. Power-Supply Rejection Ratio VIN = 12 V VOUT=3.3V, IOUT=0.1A L=2.2uH (XFL4020) Cin=10uF, Cout=22uF 10 IOUT = 0.1A 1k 10k Frequency (Hz) 100k 1M G000 fSW = 2.5 MHz Figure 35. Power-Supply Rejection Ratio IOUT= 0.5 to 2 to 0.5 A VIN = 12 V VOUT = 3.3 V Figure 37. Load Transient Response Figure 39. Line Transient Response of Figure 37, Falling Edge Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 23 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 VIN = 12 V www.ti.com VIN = 12 V VOUT = 3.3 V Figure 41. Start-Up into 2 A Figure 40. Start-Up Into 100 mA IOUT = 1 A IOUT = 10 A Figure 42. Typical Operation in PWM Mode Figure 43. Typical Operation in Power-Save Mode 125 Free-Air Temperature (C) Free-Air Temperature (C) 125 115 105 95 TPS62140 EVM L=2.2uH (XFL4020) VIN=12V, VOUT=3.3V 85 75 0 0.5 1 1.5 Output Current (A) 115 105 95 85 75 TPS62140 EVM L=2.2uH (XFL4020) VIN=12V, VOUT=3.3V 65 2 fSW = 2.5 MHz 2.5 55 0 2 G000 4 6 8 Output Power (W) 10 12 G000 fSW = 2.5 MHz Figure 44. Maximum Ambient Temperature 24 VOUT = 3.3 V Submit Documentation Feedback Figure 45. Maximum Ambient Temperature Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 9.3 System Examples 9.3.1 LED Power Supply The TPS62140 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid excessive power loss. Because this pin provides 2.5 A, the feedback pin voltage can be adjusted by an external resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62140. Figure 46 shows an application circuit, tested with analog dimming: spacing (4 .. 17) V 2.2 H PVIN SW AVIN VOS PG EN 10uF ADIM 22uF TPS62140 FB SS/TR 187k DEF AGND FSW PGND 0.15R Copyright (c) 2016, Texas Instruments Incorporated Figure 46. Single Power LED Supply The resistor at SS/TR sets the FB voltage to a level of about 300 mV and is calculated from Equation 15. spacing V FB = 0.64 x 2.5mA x R SS / TR (15) spacing The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage accordingly. The minimum input voltage must be rated according to the forward voltage needed by the LED used. More information is available in the application note SLVA451. 9.3.2 Active Output Discharge The TPS62140A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown. Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 47). The discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability, keep the maximum current into the PG pin less than 10mA. (3 .. 17)V 1 / 2.2 H PVIN Vout / 2A SW TPS62140A AVIN EN 10uF SS/TR 3.3nF VOS PG R3 R1 22uF FB DEF AGND FSW PGND R2 Copyright (c) 2016, Texas Instruments Incorporated Figure 47. Discharge Vout through PG Pin With TPS62140A Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 25 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com System Examples (continued) 9.3.3 Inverting Power Supply The TPS6214x can be used as inverting power supply by rearranging external circuitry as shown in Figure 48. As the former GND node now represents a voltage level below system ground, the voltage difference between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16). spacing VIN + VOUT VIN max (16) spacing 10uF 2.2H (3 .. 13.7)V PVIN SW AVIN VOS 10uF PG EN 1.21M TPS62140 22uF FB SS/TR 3.3nF DEF AGND FSW PGND 383k -3.3V Copyright (c) 2016, Texas Instruments Incorporated Figure 48. -3.3V Inverting Power Supply spacing The transfer function of the inverting power supply configuration differs from the buck mode transfer function, incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output capacitance of at least 22F is recommended. A detailed design example is given in SLVA469. spacing 9.3.4 Various Output Voltages The following example circuits show how to use the various devices and configure the external circuitry to furnish different output voltages at 2A. spacing spacing (5 .. 17)V 5V / 2A 2.2 H 10uF PVIN SW AVIN VOS 100k PG EN 22uF TPS62143 SS/TR 3.3nF FB DEF AGND FSW PGND Copyright (c) 2016, Texas Instruments Incorporated Figure 49. 5-V/2-A Power Supply spacing 26 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 System Examples (continued) spacing (3.3 .. 17)V 3.3V / 2A 2.2 H 10uF PVIN SW AVIN VOS 100k PG EN 22uF TPS62142 FB SS/TR 3.3nF DEF AGND FSW PGND Copyright (c) 2016, Texas Instruments Incorporated Figure 50. 3.3-V/2-A Power Supply spacing spacing (3 .. 17)V 2.5V / 2A 2.2 H PVIN SW AVIN VOS PG EN 10uF 100k 390k 22uF TPS62140 FB SS/TR 3.3nF DEF AGND FSW PGND 180k Copyright (c) 2016, Texas Instruments Incorporated Figure 51. 2.5-V/2-A Power Supply spacing spacing (3 .. 17)V 1.8V / 2A 2.2 H 10uF PVIN SW AVIN VOS PG EN 100k 22uF TPS62141 SS/TR 3.3nF FB DEF AGND FSW PGND Copyright (c) 2016, Texas Instruments Incorporated Figure 52. 1.8-V/2-A Power Supply spacing spacing Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 27 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com System Examples (continued) (3 .. 17)V 1.5V / 2A 2.2 H PVIN SW AVIN VOS 100k PG EN 10uF 130k 22uF TPS62140 FB SS/TR 3.3nF DEF AGND FSW PGND 150k Copyright (c) 2016, Texas Instruments Incorporated Figure 53. 1.5-V/2-A Power Supply spacing spacing (3 .. 17)V 1.2V / 2A 2.2 H PVIN SW AVIN VOS 100k PG EN 10uF 75k 22uF TPS62140 SS/TR 3.3nF FB DEF AGND FSW PGND 150k Copyright (c) 2016, Texas Instruments Incorporated Figure 54. 1.2-V/2-A Power Supply spacing spacing 1V / 2A 2.2 H PVIN SW AVIN VOS 100k PG EN 10uF 51k 22uF TPS62140 SS/TR 3.3nF FB DEF AGND FSW PGND 200k Copyright (c) 2016, Texas Instruments Incorporated Figure 55. 1-V/2-A Power Supply 10 Power Supply Recommendations The TPS6214X are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's output current needs to be rated according to the output voltage and the output current of the power rail application. 28 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 11 Layout 11.1 Layout Guidelines A proper layout is critical for the operation of a switched-mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS6214x demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. See Figure 56 for the recommended layout of the TPS6214x, which is designed for common external ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the VOUT power line/plane as shown in Layout Example. Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (that is, SW). As they carry information about the output voltage, they should be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane. The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the EVM Gerber data are available for download here, SLVC394. 11.2 Layout Example space AGND C5 R1 FB AGND DEF SS/TR PG AVIN SW PGND SW PGND SW PVIN EN PVIN VOS VIN FSW R2 C3 C1 L1 VOUT GND Figure 56. Layout Recommendation Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 29 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 11.3 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: * Improving the power dissipation capability of the PCB design * Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad * Introducing airflow in the system For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (SZZA017), and (SPRA953). The TPS6214X is designed for a maximum operating junction temperature (TJ) of 125C. Therefore, the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed, increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce the thermal resistance. To get improved thermal behavior, it is recommended to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance. If short-circuit or overload conditions are present, the device is protected by limiting internal power dissipation. Experimental data, taken from the TPS62140 EVM, shows the maximum ambient temperature (without additional cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125C (see Figure 44). 30 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 www.ti.com SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: * Users Guide, SLVU437 * EVM Gerber Data, SLVC394 * Thermal Characteristics Application Note, SZZA017 and SPRA953 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 6. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS62140 Click here Click here Click here Click here Click here TPS62140A Click here Click here Click here Click here Click here TPS62141 Click here Click here Click here Click here Click here TPS62142 Click here Click here Click here Click here Click here TPS62143 Click here Click here Click here Click here Click here 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Copyright (c) 2011-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 31 TPS62140, TPS62140A, TPS62141, TPS62142, TPS62143 SLVSAJ0E - NOVEMBER 2011 - REVISED SEPTEMBER 2016 www.ti.com 12.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.6 Trademarks DCS-Control, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.8 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS62140ARGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PA7I TPS62140ARGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PA7I TPS62140RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTZ TPS62140RGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTZ TPS62141RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWA TPS62141RGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWA TPS62142RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWB TPS62142RGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWB TPS62143RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWC TPS62143RGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 11-Aug-2017 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS62140ARGTR VQFN RGT 16 TPS62140ARGTT VQFN RGT TPS62140RGTR VQFN RGT TPS62140RGTT VQFN TPS62141RGTR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62141RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62142RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62142RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62143RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62143RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62140ARGTR VQFN RGT 16 3000 552.0 367.0 36.0 TPS62140ARGTT VQFN RGT 16 250 552.0 185.0 36.0 TPS62140RGTR VQFN RGT 16 3000 367.0 367.0 35.0 TPS62140RGTT VQFN RGT 16 250 210.0 185.0 35.0 TPS62141RGTR VQFN RGT 16 3000 367.0 367.0 35.0 TPS62141RGTT VQFN RGT 16 250 210.0 185.0 35.0 TPS62142RGTR VQFN RGT 16 3000 367.0 367.0 35.0 TPS62142RGTT VQFN RGT 16 250 210.0 185.0 35.0 TPS62143RGTR VQFN RGT 16 3000 367.0 367.0 35.0 TPS62143RGTT VQFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RGT0016C VQFN - 1 mm max height SCALE 3.600 PLASTIC QUAD FLATPACK - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.00 0.08 1.68 0.07 (0.2) TYP 5 12X 0.5 8 EXPOSED THERMAL PAD 4 9 4X 1.5 SYMM 1 12 16X PIN 1 ID (OPTIONAL) 13 16 0.1 0.05 SYMM 16X 0.30 0.18 C A B 0.5 0.3 4222419/B 11/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RGT0016C VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.68) SYMM 13 16 16X (0.6) 1 12 16X (0.24) SYMM (0.58) TYP 12X (0.5) (2.8) 9 4 ( 0.2) TYP VIA 5 (R0.05) ALL PAD CORNERS 8 (0.58) TYP (2.8) LAND PATTERN EXAMPLE SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222419/B 11/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RGT0016C VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.55) 16 13 16X (0.6) 1 12 16X (0.24) 17 SYMM (2.8) 12X (0.5) 9 4 METAL ALL AROUND 5 SYMM 8 (R0.05) TYP (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 4222419/B 11/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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