Kinetis KL17 Microcontroller
48 MHz ARM® Cortex®-M0+ and 128/256 KB Flash
The KL17 series is optimized for cost-sensitive and battery-
powered applications requiring low-power general-purpose
connectivity. The product offers:
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Down to 54uA/MHz in very low power run mode and
1.96uA in deep sleep mode (RAM + RTC retained)
Core Processor
• ARM® Cortex®-M0+ core up to 48 MHz
Memories
• 128/256 KB program flash memory
• 32 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48MHz high accuracy (up to 0.5%) internal reference
clock
• 8MHz/2MHz high accuracy (up to 3%) internal
reference clock
• 1KHz reference clock active under all low-power
modes (except VLLS0)
• 32–40KHz and 3–32MHz crystal oscillator
Peripherals
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, IrDA, SPI, I2C, I2S, PWM and
other serial modules, etc.
• One serial audio interface I2S
• One 16-bit 818 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
16 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
MKL17Z128Vxx4
MKL17Z256Vxx4
MKL17Z256CAL4R
32 and 48 QFN
5x5 mm P 0.5 mm 7x7
mm P 0.5 mm
36 WLCSP
2.8x2.7 mm P 0.4 mm
64 LQFP
10x10 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm
Freescale Semiconductor, Inc. KL17P64M48SF6
Data Sheet: Technical Data Rev. 6, 02/2016
© 2014–2016 Freescale Semiconductor, Inc. All rights reserved.
Document Number:
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 85 °C for WLCSP package
and –40 to 105 °C for other packages
Packages
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
thickness
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
thickness
• 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness
• 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness
• 36 WLCSP 2.8mm x 2.7mm, 0.4mm pitch, 0.6mm
thickness
Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security
I/O
• Up to 54 general-purpose input/output pins (GPIO)
and 6 high-drive pad
Low Power
• Down to 54uA/MHz in very low power run mode
• Down to 1.96uA in VLLS3 mode (RAM + RTC
retained)
• Six flexible static modes
Ordering Information
Product Memory Package IO and ADC channel
Part number Marking (Line1/
Line2)
Flash
(KB)
SRAM
(KB)
Pin
count
Package GPIOs GPIOs
(INT/HD)1ADC
channels
(SE/DP)
MKL17Z128VFM4 M17P7V 128 32 32 QFN 28 19/6 11/2
MKL17Z256VFM4 M17P8V 256 32 32 QFN 28 19/6 11/2
MKL17Z128VFT4 M17P7V 128 32 48 QFN 40 24/6 18/3
MKL17Z256VFT4 M17P8V 256 32 48 QFN 40 24/6 18/3
MKL17Z128VLH4 MKL17Z128V//LH4 128 32 64 LQFP 54 31/6 20/4
MKL17Z256VLH4 MKL17Z256V//LH4 256 32 64 LQFP 54 31/6 20/4
MKL17Z128VMP4 M17P7V 128 32 64 MAPBGA 54 31/6 20/4
MKL17Z256VMP4 M17P8V 256 32 64 MAPBGA 54 31/6 20/4
MKL17Z256CAL4R MKL17Z256CAL4 256 32 36 WLCSP 26 23/6 7/0
1. INT: interrupt pin numbers; HD: high drive pin numbers
Related Resources
Type Description Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KL1XPB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL17P64M48SF6RM1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata The chip mask set Errata provides additional or corrective information for
a particular device mask set.
KINETIS_L_1N71K1
Table continues on the next page...
2Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Related Resources (continued)
Type Description Resource
Package
drawing
Package dimensions are provided in package drawings. 64-LQFP: 98ASS23234W1 64-
MAPBGA: 98ASA00420D, 132-
QFN: 98ASA00615D1 48-QFN:
98ASA00616D, 136-WLCSP:
98ASA00949D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 3
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Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....20
2.2.7 Designing with radiated emissions in mind..........21
2.2.8 Capacitance attributes.........................................21
2.3 Switching specifications...................................................21
2.3.1 Device clock specifications..................................21
2.3.2 General switching specifications......................... 22
2.4 Thermal specifications.....................................................22
2.4.1 Thermal operating requirements......................... 22
2.4.2 Thermal attributes................................................23
3 Peripheral operating requirements and behaviors.................. 24
3.1 Core modules.................................................................. 24
3.1.1 SWD electricals .................................................. 24
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG-Lite specifications.......................................25
3.3.2 Oscillator electrical specifications........................27
3.4 Memories and memory interfaces................................... 29
3.4.1 Flash electrical specifications..............................29
3.5 Security and integrity modules........................................ 31
3.6 Analog............................................................................. 31
3.6.1 ADC electrical specifications............................... 31
3.6.2 Voltage reference electrical specifications.......... 36
3.6.3 CMP and 6-bit DAC electrical specifications....... 37
3.6.4 12-bit DAC electrical characteristics....................39
3.7 Timers..............................................................................42
3.8 Communication interfaces............................................... 42
3.8.1 SPI switching specifications................................ 42
3.8.2 I2C.......................................................................47
3.8.3 UART...................................................................48
3.8.4 I2S/SAI switching specifications..........................49
4 Dimensions............................................................................. 53
4.1 Obtaining package dimensions....................................... 53
5 Pinouts and Packaging........................................................... 54
5.1 KL17 signal multiplexing and pin assignments................54
5.2 KL17 Family Pinouts........................................................57
5.3 Recommended connection for unused analog and
digital pins........................................................................61
6 Ordering parts......................................................................... 62
6.1 Determining valid orderable parts....................................62
7 Part identification.....................................................................62
7.1 Description.......................................................................62
7.2 Format............................................................................. 63
7.3 Fields............................................................................... 63
7.4 Example...........................................................................63
8 Terminology and guidelines.................................................... 64
8.1 Definitions........................................................................64
8.2 Examples.........................................................................64
8.3 Typical-value conditions.................................................. 65
8.4 Relationship between ratings and operating
requirements....................................................................65
8.5 Guidelines for ratings and operating requirements..........66
9 Revision History...................................................................... 66
4Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
–500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Ratings
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1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
General
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2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICIO IO pin negative DC injection current — single pin
• VIN < VSS-0.3V -3 — mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection -25 — mA
VODPU Open drain pullup voltage level VDD VDD V2
VRAM VDD voltage required to retain RAM 1.2 — V
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V —
VLVDH Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48 2.56 2.64 V —
Low-voltage warning thresholds — high range 1
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Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±60 — mV —
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V —
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±40 — mV —
VBG Bandgap voltage reference 0.97 1.00 1.03 V —
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs —
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1
VOH Output high voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1
IOHT Output high current total for all ports — 100 mA
VOL Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
0.5
V
V
1
VOL Output low voltage — high drive pad
—
0.5
V
1
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General
8Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
— 0.5 V
IOLT Output low current total for all ports — 100 mA
IIN Input leakage current (per pin) for full temperature
range
— 1 μA 2
IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2
IIN Input leakage current (total all pins) for full
temperature range
— 64 μA 2
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA
RPU Internal pullup resistors 20 50 kΩ 3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 8. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
152
166
μs
• VLLS1 → RUN
—
152
166
μs
• VLLS3 → RUN
—
93
104
μs
• LLS → RUN
—
7.5
8
μs
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General
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Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• VLPS → RUN
—
7.5
8
μs
• STOP → RUN
—
7.5
8
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
NOTE
The data at 105 °C are for QFN, LQFP and MAPBGA
packages only.
Table 9. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
5.76
6.04
6.40
6.68
mA
2
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
3.21
3.49
3.85
4.13
mA
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
6.45
6.75
7.09
7.39
mA
2
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable, 24
MHz core/12 MHz flash, VDD = 3.0 V
2
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General
10 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• at 25 °C
• at 105 °C
—
—
3.95
4.23
4.59
4.87
mA
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 12
MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
2.68
2.96
3.32
3.60
mA
2
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
8.08
8.39
8.72
9.03
mA
2
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock disable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
3.90
4.21
4.54
4.85
mA
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
2.66
2.94
3.30
3.58
mA
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock disable,
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
2.03
2.31
2.67
2.95
mA
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock enable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
5.52
5.83
6.16
6.47
mA
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
—
—
5.29
5.56
5.93
6.20
mA
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
—
—
6.91
7.19
7.55
7.91
mA
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• at 25 °C
• at 105 °C
IDD_VLPRCO Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4MHz, Flash
@1MHz, VDD = 3.0 V
• at 25 °C
—
826
907
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode, 4
MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
405
486
μA
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode, 2
MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
154
235
μA
IDD_VLPR Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
108
189
μA
IDD_VLPR Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
—
39
120
μA
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
249
330
μA
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
337
418
μA
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD =
3.0 V
• at 25 °C
—
416
497
μA
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
494
575
μA
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V
• at 25 °C
—
166
247
μA
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
— 50 131 μA
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
208
289
μA
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.81
1.89
mA
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.22
1.39
mA
IDD_VLPW Very-low-power wait mode current, core disabled,
4 MHz system/ 1 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
— 172 182 μA
IDD_VLPW Very-low-power wait mode current, core disabled,
2 MHz system/ 0.5 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
— 69 76 μA
IDD_VLPW Very-low-power wait mode current, core disabled,
125 kHz system/ 31.25 kHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
— 36 40 μA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12
MHz bus and flash, VDD = 3.0 V
—
1.81
2.06
mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
—
1.00
1.25
mA
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
161.93
181.45
236.29
390.33
171.82
191.96
271.17
465.58
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
—
3.31
10.43
34.14
104.38
5.14
17.68
61.06
164.44
μA
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
—
3.21
5.22
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Freescale Semiconductor, Inc.
Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• at 50 °C
• at 85 °C
• at 105 °C
—
—
—
10.26
33.49
102.92
17.62
60.19
162.20
μA
IDD_LLS Low-leakage stop mode current, all peripheral
disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
2.06
4.72
8.13
13.34
41.08
3.33
6.85
13.30
24.70
52.43
μA
IDD_LLS Low-leakage stop mode current with RTC current,
at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
2.46
5.12
8.53
13.74
41.48
3.73
7.25
11.78
18.91
52.83
μA
IDD_LLS Low-leakage stop mode current with RTC current,
at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
2.35
4.91
8.32
13.44
40.47
2.70
6.75
11.78
18.21
51.85
μA
3
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
1.45
3.37
5.76
9.72
30.41
1.85
4.39
8.48
14.30
37.50
μA
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
2.05
3.97
6.36
10.32
31.01
2.45
4.99
9.08
14.73
38.10
μA
3
Table continues on the next page...
General
14 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
1.96
3.86
6.23
10.21
30.25
2.36
5.67
8.53
13.37
37.02
μA
3
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
—
—
—
—
—
0.66
1.78
2.55
4.83
16.42
0.80
3.87
4.26
6.64
20.49
μA
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
—
—
—
—
—
1.26
2.38
3.15
5.43
17.02
1.40
4.47
4.86
7.24
21.09
μA
3
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
—
—
—
—
—
1.16
1.96
2.78
4.85
15.78
1.30
2.28
3.37
6.88
18.81
μA
3
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
0.35
1.25
2.53
4.40
16.09
0.47
1.44
3.24
5.24
19.29
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
General
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Table 9. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
0.18
1.09
2.25
4.25
15.95
0.28
1.31
2.94
5.10
19.10
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Table 10. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIRC8MHz 8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
93 93 93 93 93 93 µA
IIRC2MHz 2 MHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
29 29 29 29 29 29 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 224 230 238 245 253 µA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
• VLLS1
• VLLS3
• LLS
• VLPS
• STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
ILPTMR LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
200
Table continues on the next page...
General
16 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
nA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
22 22 22 22 22 22 µA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
114
34
114
34
114
34
114
34
114
34
114
34
µA
ITPM TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
147
42
147
42
147
42
147
42
147
42
147
42
µA
IBG Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
330 330 330 330 330 330 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
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Figure 2. Run mode supply current vs. core frequency
General
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General
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Current Consumption on VDD (A)
Current Consumption on VDD (A)
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP
package
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 11 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 12 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 10 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 6 dBμV
VRE_IEC IEC level 0.15–1000 N — 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
General
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of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = IRC48M, fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol Description Min. Max. Unit
CIN Input capacitance — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
fSYS System and core clock1— 48 MHz
fBUS Bus clock1— 24 MHz
fFLASH Flash clock1— 24 MHz
fLPTMR LPTMR clock — 24 MHz
VLPR and VLPS modes2
fSYS System and core clock — 4 MHz
fBUS Bus clock — 1 MHz
fFLASH Flash clock — 1 MHz
fLPTMR LPTMR clock3— 24 MHz
Table continues on the next page...
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Table 13. Device clock specifications (continued)
Symbol Description Min. Max. Unit
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
— 16 MHz
fTPM TPM asynchronous clock — 8 MHz
fLPUART0/1 LPUART0/1 asynchronous clock — 8 MHz
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5 — Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements for WLCSP package
Symbol Description Min. Max. Unit Notes
TJDie junction temperature –40 95 °C
TAAmbient temperature –40 85 °C 1
General
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1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
Table 16. Thermal operating requirements for other packages
Symbol Description Min. Max. Unit Notes
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
2.4.2 Thermal attributes
Table 17. Thermal attributes
Board type Symbo
l
Description 48
QFN
32
QFN
64
LQFP
64
MAPB
GA
36
WLCS
P
Unit Notes
Single-layer (1S) RθJA Thermal resistance,
junction to ambient
(natural convection)
86 101 70 50.3 77.6 °C/W 1
Four-layer (2s2p) RθJA Thermal resistance,
junction to ambient
(natural convection)
29 33 51 42.9 38.9 °C/W
Single-layer (1S) RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
71 84 58 41.4 69.6 °C/W
Four-layer (2s2p) RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
24 28 45 38.0 35.6 °C/W
— RθJB Thermal resistance,
junction to board
12 13 33 39.6 34.8 °C/W 2
— RθJC Thermal resistance,
junction to case
1.7 1.7 20 27.3 0.37 °C/W 3
—ΨJT Thermal characterization
parameter, junction to
package top outside
center (natural convection)
2 3 4 0.4 0.2 °C/W 4
—ΨJB Thermal characterization
parameter, junction to
package bottom (natural
convection)
- - - 12.6 - °C/W 5
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
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3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 18. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
• Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 — ns
J3 SWD_CLK clock pulse width
• Serial wire debug
20
—
ns
J4 SWD_CLK rise and fall times — 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 4. Serial wire clock input timing
Peripheral operating requirements and behaviors
24 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 5. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 19. IRC48M specification
Symbol Description Min. Typ. Max. Unit Notes
IDD Supply current — 400 500 µA —
fIRC Output frequency — 48 — MHz —
Δfirc48m_ol_lv Open loop total deviation of IRC48M
frequency at low voltage
(VDD=1.71V-1.89V) over temperature
— ± 0.5 ± 1.5 %firc48m 1
Δfirc48m_ol_hv Open loop total deviation of IRC48M
frequency at high voltage
(VDD=1.89V-3.6V) over temperature
— ± 0.5 ± 1.0 %firc48m 1
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 19. IRC48M specification (continued)
Symbol Description Min. Typ. Max. Unit Notes
TjPeriod jitter (RMS) — 35 150 ps —
Tsu Startup time — 2 3 µs —
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
Table 20. IRC8M/2M specification
Symbol Description Min. Typ. Max. Unit Notes
IDD_2M Supply current in 2 MHz mode — 14 17 µA —
IDD_8M Supply current in 8 MHz mode — 30 35 µA —
fIRC_2M Output frequency — 2 — MHz —
fIRC_8M Output frequency — 8 — MHz —
fIRC_T_2M Output frequency range (trimmed) — — ±3 %fIRC —
fIRC_T_8M Output frequency range (trimmed) — — ±3 %fIRC —
Tsu_2M Startup time — — 12.5 µs —
Tsu_8M Startup time — — 12.5 µs —
Peripheral operating requirements and behaviors
26 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Figure 6. IRC8M Frequency Drift vs Temperature curve
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 21. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
nA
μA
μA
μA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 21. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
• 24 MHz
• 32 MHz
— 1.5 — mA
IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-
power mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
Peripheral operating requirements and behaviors
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3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 22. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 48 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
Peripheral operating requirements and behaviors
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3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversblk128k Erase Block high-voltage time for 128 KB — 52 452 ms 1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1blk128k
Read 1s Block execution time
• 128 KB program flash
—
—
1.7
ms
1
trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersblk128k
Erase Flash Block execution time
• 128 KB program flash
—
88
600
ms
2
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 1.8 ms 1
trdonce Read Once execution time — — 25 μs 1
tpgmonce Program Once execution time — 65 — μs —
tersall Erase All Blocks execution time — 175 1300 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
tersallu Erase All Blocks Unsecure execution time — 175 1300 ms 2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
Peripheral operating requirements and behaviors
30 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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3.4.1.3 Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 26. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
Peripheral operating requirements and behaviors
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3.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V —
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V3
VREFL ADC reference
voltage low
VSSA VSSA VSSA V3
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 ×
VREFH
VREFH
V —
CADIN Input
capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF —
RADIN Input series
resistance
— 2 5 kΩ —
RAS Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
4
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 24 MHz 5
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 5
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
—
1200
ksps
6
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
—
461.467
ksps
6
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Peripheral operating requirements and behaviors
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RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 7. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to
0.5
LSB45
INL Integral non-linearity • 12-bit modes — ±1.0 –2.7 to
+1.9
LSB45
Table continues on the next page...
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Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
• <12-bit modes — ±0.5 –0.7 to
+0.5
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN = VDDA5
EQQuantization error • 16-bit modes
• ≤13-bit modes
—
—
–1 to 0
—
—
±0.5
LSB4
ENOB Effective number of
bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD Signal-to-noise plus
distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
-94
-85
—
—
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
82
78
95
90
—
—
dB
dB
7
EIL Input leakage error IIn × RAS mV IIn = leakage
current
(refer to the
MCU's
voltage and
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 8
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
Peripheral operating requirements and behaviors
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3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Peripheral operating requirements and behaviors
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3.6.2 Voltage reference electrical specifications
Table 29. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 3.6 V
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
Table 30 is tested under the condition of setting VREF_TRM[CHOPEN],
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
Table 30. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915 1.195 1.1977 V 1
Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1
Vout Voltage reference output — user trim 1.193 — 1.197 V 1
Vstep Voltage reference trim step — 0.5 — mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range: 0 to 70°C)
— — 50 mV 1
Ibg Bandgap only current — — 80 µA 1
Ilp Low-power buffer current — — 360 uA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation
• current = ± 1.0 mA
—
200
—
µV 1, 2
Tstup Buffer startup time — — 100 µs
Tchop_osc_st
up
Internal bandgap start-up delay with chop
oscillator enabled
— — 35 ms —
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Peripheral operating requirements and behaviors
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Table 31. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 50 °C
Table 32. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vout Voltage reference output with factory trim 1.173 1.225 V
3.6.3 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
Peripheral operating requirements and behaviors
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00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
38 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.4 12-bit DAC electrical characteristics
3.6.4.1 12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Peripheral operating requirements and behaviors
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Freescale Semiconductor, Inc.
3.6.4.2 12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 250 μA
IDDA_DACH
P
Supply current — high-speed mode — — 900 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
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Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 12. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
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Freescale Semiconductor, Inc.
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
42 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 36. SPI master mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 18 — ns —
7 tHI Data hold time (inputs) 0 — ns —
8 tvData valid (after SPSCK edge) — 15 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
11 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 37. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 96 — ns —
7 tHI Data hold time (inputs) 0 — ns —
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 37. SPI master mode timing on slew rate enabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
8 tvData valid (after SPSCK edge) — 52 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
11 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
(OUTPUT)
2
8
6 7
MSB IN2
LSB IN
MSB OUT2 LSB OUT
9
5
5
3
(CPOL=0)
4
11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) BIT 6 . . . 1
BIT 6 . . . 1
Figure 14. SPI master mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
44 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6 7
MSB IN2
BIT 6 . . . 1
MASTER MSB OUT2 MASTER LSB OUT
5
5
8
10 11
PORT DATA PORT DATA
310 11 4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) LSB IN
BIT 6 . . . 1
Figure 15. SPI master mode timing (CPHA = 1)
Table 38. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2.5 — ns —
7 tHI Data hold time (inputs) 3.5 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 31 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
13 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Peripheral operating requirements and behaviors
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Table 39. SPI slave mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 122 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
13 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
2
10
6 7
MSB IN
BIT 6 . . . 1
SLAVE MSB SLAVE LSB OUT
11
5
5
3
8
4
13
NOTE: Not defined
12
12
11
SEE
NOTE
13
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
LSB IN
BIT 6 . . . 1
Figure 16. SPI slave mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
46 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
2
6 7
MSB IN
BIT 6 . . . 1
MSB OUT SLAVE LSB OUT
5
5
10
12 13
312 13
4
SLAVE
8
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
NOTE: Not defined
11
LSB IN
BIT 6 . . . 1
Figure 17. SPI slave mode timing (CPHA = 1)
3.8.2 I2C
3.8.2.1 Inter-Integrated Circuit Interface (I2C) timing
Table 40. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Data set-up time tSU; DAT 2505— 1003, 6— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
Peripheral operating requirements and behaviors
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 47
Freescale Semiconductor, Inc.
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
Table 41. I 2C 1Mbit/s timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency fSCL 0 11MHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA 0.26 — µs
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Data set-up time tSU; DAT 50 — ns
Rise time of SDA and SCL signals tr20 +0.1Cb120 ns
Fall time of SDA and SCL signals tf20 +0.1Cb2120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START condition tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by
the input filter
tSP 0 50 ns
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 18. Timing definition for devices on the I2C bus
Peripheral operating requirements and behaviors
48 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
3.8.3 UART
See General switching specifications.
3.8.4 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks
are driven) and slave mode (clocks are input). All timing is given for noninverted
serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame
sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.4.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 42. I2S/SAI master mode timing
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 15.5 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 19 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
26 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
Peripheral operating requirements and behaviors
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 49
Freescale Semiconductor, Inc.
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 19. I2S/SAI timing — master modes
Table 43. I2S/SAI slave mode timing
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 33 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 10 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 28 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
50 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 20. I2S/SAI timing — slave modes
3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 44. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 62.5 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 45 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
— ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
Peripheral operating requirements and behaviors
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 51
Freescale Semiconductor, Inc.
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 21. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 87 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
52 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 22. I2S/SAI timing — slave modes
4Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
32-pin QFN 98ASA00615D
36-pin WLCSP 98ASA00949D
48-pin QFN 98ASA00616D
64-pin LQFP 98ASS23234W
64-pin MAPBGA 98ASA00420D
Dimensions
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 53
Freescale Semiconductor, Inc.
Pinouts and Packaging
5.1 KL17 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
VREFH can act as VREF_OUT when VREFV1 module is
enabled.
NOTE
It is prohibited to set VREFEN in 32 QFN and 36 WLCSP pin
packages because 1.2 V on-chip voltage is not available in
these packages.
64
MAP
BGA
64
LQFP
48
QFN
36
WLC
SP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
A1 1 — — 1 PTE0 DISABLED PTE0/
CLKOUT32
K
SPI1_MISO LPUART1_
TX
RTC_
CLKOUT
CMP0_OUT I2C1_SDA
B1 2 — — 2 PTE1 DISABLED PTE1 SPI1_MOSI LPUART1_
RX
SPI1_MISO I2C1_SCL
— 3 1 — — VDD VDD VDD
C4 4 2 — — VSS VSS VSS
E1 5 3 — 3 PTE16 ADC0_DP1/
ADC0_SE1
ADC0_DP1/
ADC0_SE1
PTE16 SPI0_PCS0 UART2_TX TPM_
CLKIN0
FXI00_D0
D1 6 4 — 4 PTE17 ADC0_DM1/
ADC0_SE5a
ADC0_DM1/
ADC0_SE5a
PTE17 SPI0_SCK UART2_RX TPM_
CLKIN1
LPTMR0_
ALT3
FXIO0_D1
E2 7 5 — 5 PTE18 ADC0_DP2/
ADC0_SE2
ADC0_DP2/
ADC0_SE2
PTE18 SPI0_MOSI I2C0_SDA SPI0_MISO FXIO0_D2
D2 8 6 — 6 PTE19 ADC0_DM2/
ADC0_SE6a
ADC0_DM2/
ADC0_SE6a
PTE19 SPI0_MISO I2C0_SCL SPI0_MOSI FXIO0_D3
G1 9 7 — — PTE20 ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
PTE20 TPM1_CH0 LPUART0_
TX
FXI00_D4
F1 10 8 — — PTE21 ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
PTE21 TPM1_CH1 LPUART0_
RX
FXIO0_D5
G2 11 — — — PTE22 ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22 TPM2_CH0 UART2_TX FXIO0_D6
F2 12 — — — PTE23 ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
PTE23 TPM2_CH1 UART2_RX FXIO0_D7
5
Pinouts and Packaging
54 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
64
MAP
BGA
64
LQFP
48
QFN
36
WLC
SP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
F4 13 9 E6 7 VDDA VDDA VDDA
G4 14 10 E6 — VREFH VREFH VREFH
G3 15 11 F6 — VREFL VREFL VREFL
F3 16 12 F6 8 VSSA VSSA VSSA
H1 17 13 — — PTE29 CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29 TPM0_CH2 TPM_
CLKIN0
H2 18 14 E5 9 PTE30 DAC0_OUT/
ADC0_
SE23/
CMP0_IN4
DAC0_OUT/
ADC0_
SE23/
CMP0_IN4
PTE30 TPM0_CH3 TPM_
CLKIN1
LPUART1_
TX
LPTMR0_
ALT1
H3 19 — — — PTE31 DISABLED PTE31 TPM0_CH4
H4 20 15 — — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
H5 21 16 — — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
D3 22 17 F5 10 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
D4 23 18 E4 11 PTA1 DISABLED PTA1 LPUART0_
RX
TPM2_CH0
E5 24 19 D4 12 PTA2 DISABLED PTA2 LPUART0_
TX
TPM2_CH1
D5 25 20 F4 13 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
G5 26 21 F3 14 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
F5 27 — — — PTA5 DISABLED PTA5 TPM0_CH2 I2S0_TX_
BCLK
H6 28 — — — PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0
G6 29 — — — PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_
FS
— — — E3 — PTA14 DISABLED PTA14 SPI0_PCS0 LPUART0_
TX
I2S0_RX_
BCLK
I2S0_TXD0
— — — D3 — PTA15 DISABLED PTA15 SPI0_SCK LPUART0_
RX
I2S0_RXD0
— — — C3 — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO I2S0_RX_
FS
I2S0_RXD0
— — — D2 — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI I2S0_MCLK
G7 30 22 E2 15 VDD VDD VDD
H7 31 23 F2 16 VSS VSS VSS
H8 32 24 F1 17 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_
RX
TPM_
CLKIN0
G8 33 25 E1 18 PTA19 XTAL0 XTAL0 PTA19 LPUART1_
TX
TPM_
CLKIN1
LPTMR0_
ALT1
F8 34 26 D1 19 PTA20 RESET_b PTA20 RESET_b
F7 35 27 C2 20 PTB0/
LLWU_P5
ADC0_SE8 ADC0_SE8 PTB0/
LLWU_P5
I2C0_SCL TPM1_CH0
F6 36 28 C1 21 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1
E7 37 29 — — PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0
Pinouts and Packaging
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 55
Freescale Semiconductor, Inc.
64
MAP
BGA
64
LQFP
48
QFN
36
WLC
SP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
E8 38 30 — — PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1
E6 39 31 — — PTB16 DISABLED PTB16 SPI1_MOSI LPUART0_
RX
TPM_
CLKIN0
SPI1_MISO
D7 40 32 — — PTB17 DISABLED PTB17 SPI1_MISO LPUART0_
TX
TPM_
CLKIN1
SPI1_MOSI
D6 41 — — — PTB18 DISABLED PTB18 TPM2_CH0 I2S0_TX_
BCLK
C7 42 — — — PTB19 DISABLED PTB19 TPM2_CH1 I2S0_TX_
FS
D8 43 33 — — PTC0 ADC0_SE14 ADC0_SE14 PTC0 EXTRG_IN audioUSB_
SOF_OUT
CMP0_OUT I2S0_TXD0
C6 44 34 B1 22 PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_SE15 ADC0_SE15 PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL TPM0_CH0 I2S0_TXD0
B7 45 35 B2 23 PTC2 ADC0_SE11 ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_
FS
C8 46 36 A1 24 PTC3/
LLWU_P7
DISABLED PTC3/
LLWU_P7
SPI1_SCK LPUART1_
RX
TPM0_CH2 CLKOUT I2S0_TX_
BCLK
E3 47 — C4 — VSS VSS VSS
E4 48 — B3 — VDD VDD VDD
B8 49 37 A2 25 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 LPUART1_
TX
TPM0_CH3 I2S0_MCLK
A8 50 38 A3 26 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD0 CMP0_OUT
A7 51 39 B4 27 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_MOSI EXTRG_IN I2S0_RX_
BCLK
SPI0_MISO I2S0_MCLK
B6 52 40 A4 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO audioUSB_
SOF_OUT
I2S0_RX_
FS
SPI0_MOSI
A6 53 — — — PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4 I2S0_MCLK
B5 54 — — — PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5 I2S0_RX_
BCLK
B4 55 — — — PTC10 DISABLED PTC10 I2C1_SCL I2S0_RX_
FS
A5 56 — — — PTC11 DISABLED PTC11 I2C1_SDA I2S0_RXD0
C3 57 41 — — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 FXI00_D0
A4 58 42 — — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1
C2 59 43 — — PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2
B3 60 44 — — PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3
A3 61 45 A5 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI1_PCS0 UART2_RX TPM0_CH4 FXI00_D4
C1 62 46 B5 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5
B2 63 47 A6 31 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI1_MOSI LPUART0_
RX
SPI1_MISO FXIO0_D6
Pinouts and Packaging
56 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Freescale Semiconductor, Inc.
64
MAP
BGA
64
LQFP
48
QFN
36
WLC
SP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
A2 64 48 B6 32 PTD7 DISABLED PTD7 SPI1_MISO LPUART0_
TX
SPI1_MOSI FXIO0_D7
C5 — — C5 — Reserved Reserved Reserved
— — — C6 — Reserved Reserved Reserved
— — — D5 — Reserved Reserved Reserved
— — — D6 — Reserved Reserved Reserved
5.2 KL17 Family Pinouts
Figure below shows the 32 QFN pinouts:
32
31
30
29
28
27
26
25
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTA2
PTA1
PTA0
PTE30
12
11
10
9
VSS
VDD
PTA4
PTA3
16
15
14
13
PTB0/LLWU_P5
PTA20
PTA19
PTA18
24
23
22
21
20
19
18
17
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTB1
VSSA
VDDA
PTE19
PTE18
PTE17
PTE16
PTE1
PTE0
8
7
6
5
4
3
2
1
Figure 23. 32 QFN Pinout diagram
Figure below shows the 36 WLCSP pinouts:
Pinouts and Packaging
Kinetis KL17 Microcontroller, Rev. 6, 02/2016 57
Freescale Semiconductor, Inc.
1
APTC3
B PTC1
CPTB1
DPTA20
EPTA19
1
FPTA18
2
PTC4
PTC2
PTB0
PTA17
VDD
2
VSS
3
PTC5
VDD
PTA16
PTA15
PTA14
3
PTA4
4
PTC7
PTC6
VSS
PTA2
PTA1
4
PTA3
5
PTD4
PTD5
Reserved
PTE30
5
PTA0
6
A
PTD6
BPTD7
C
D
E
VDDA/
VREFH
6
F
VSSA/
VREFL
Reserved
Reserved Reserved
Figure 24. 36 WLCSP Pinout diagram
Figure below shows the 48 QFN pinouts:
Pinouts and Packaging
58 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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VSSA
VREFL
VREFH
VDDA
PTE21
PTE20
PTE19
PTE18
PTE17
PTE16
VSS
VDD
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
36
35
34
33
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
32
31
30
29
28
27
26
25
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTA3
PTA2
PTA1
PTA0
24
23
22
21
20
19
18
17
PTE25
PTE24
PTE30
PTE29
16
15
14
13
PTA18
VSS
VDD
PTA4
Figure 25. 48 QFN Pinout diagram
Figure below shows the 64 MAPBGA pinouts:
Pinouts and Packaging
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1
A PTE0
B PTE1
C PTD5
D PTE17
E PTE16
F PTE21
G PTE20
1
H PTE29
2
PTD7
PTD6/
LLWU_P15
PTD2
PTE19
PTE18
PTE23
PTE22
2
PTE30
3
PTD4/
LLWU_P14
PTD3
PTD0
PTA0
VSS
VSSA
VREFL
3
PTE31
4
PTD1
PTC10
VSS
PTA1
VDD
VDDA
VREFH
4
PTE24
5
PTC11
PTC9
NC
PTA3
PTA2
PTA5
PTA4
5
PTE25
6
PTC8
PTC7
PTC1/
LLWU_P6/
RTC_CLKIN
PTB18
PTB16
PTB1
PTA13
6
PTA12
7
PTC6/
LLWU_P10
PTC2
PTB19
PTB17
PTB2
PTB0/
LLWU_P5
VDD
7
VSS
8
A
PTC5/
LLWU_P9
BPTC4/
LLWU_P8
C
PTC3/
LLWU_P7
D
PTC0
EPTB3
FPTA20
GPTA19
8
HPTA18
Figure 26. 64 MAPBGA Pinout diagram:
Figure below shows the 64 LQFP pinouts:
Pinouts and Packaging
60 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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PTE24
PTE31
PTE30
PTE29
VSSA
VREFL
VREFH
VDDA
PTE23
PTE22
PTE21
PTE20
PTE19
PTE18
PTE17
PTE16
VSS
VDD
PTE1
PTE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
PTB19
PTB18
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTA18
VSS
VDD
PTA13
PTA12
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTE25
Figure 27. 64 LQFP Pinout diagram
5.3 Recommended connection for unused analog and digital
pins
Table 46 shows the recommended connections for analog interface pins if those
analog interfaces are not used in the customer's application
Pinouts and Packaging
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Table 46. Recommended connection for unused analog interfaces
Pin Type KL17 Short recommendation Detailed recommendation
GPIO/Analog PTA18/EXTAL0 Float Analog input - Float
GPIO/Analog PTA19/XTAL0 Float Analog output - Float
GPIO/Analog PTx/DAC0_OUT Float Float (default is analog input)
GPIO/Analog PTx/ADCx Float Float (default is analog input)
GPIO/Analog PTx/CMPx Float Float (default is analog input)
GPIO/Digital PTA0/SWD_CLK Float Float (default is SWD with
pulldown)
GPIO/Digital PTA3/SWD_DIO Float Float (default is SWD with
pullup)
GPIO/Digital PTA4/NMI_b 10 kΩ pullup or disabled and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital PTx Float Float (default is disabled)
VDDA VDDA Always connect to VDD
potential
Always connect to VDD
potential
VREFH VREFH Always connect to VDD
potential
Always connect to VDD
potential
VREFL VREFL Always connect to VSS
potential
Always connect to VSS
potential
VSSA VSSA Always connect to VSS
potential
Always connect to VSS
potential
Reserved Reserved Tie to ground through 10 kΩ Tie to ground through 10 kΩ
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the Web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers:
7Part identification
Ordering parts
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7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 47. Part number fields descriptions
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
KL## Kinetis family • KL17
A Key attribute • Z = Cortex-M0+
FFF Program flash memory size • 128 = 128 KB
• 256 = 256 KB
R Silicon revision • (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • FM = 32 QFN (5 mm x 5 mm)
• AL = 36 WLCSP (2.8 mm x 2.7 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
CC Maximum CPU frequency (MHz) • 4 = 48 MHz
N Packaging type • R = Tape and reel
7.4 Example
This is an example part number:
Part identification
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MKL17Z256VMP4
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
64 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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8.2 Examples
Operating rating:
Operating requirement:
Operating behavior that includes a typical value:
EXAMPLE
EXAMPLEEXAMPLE
EXAMPLE
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD Supply voltage 3.3 V
Terminology and guidelines
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8.4 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9Revision History
The following table provides a revision history for this document.
Table 48. Revision History
Rev. No. Date Substantial Changes
3 09 August
2014
Initial Public release
• Updated Table 9 - Power consumption operating behaviors.
• Added a note related to 32 QFN pin package in Pinouts topic.
4 03 March
2015
• Updated the features and completed the ordering information.
• Removed thickness dimension from package diagrams.
Table continues on the next page...
Revision History
66 Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Table 48. Revision History (continued)
Rev. No. Date Substantial Changes
• Updated Related Resources table to include Chip Errata resource name and Package
Drawing part numbers in the respective rows. Also updated Product Brief resource
references.
• Updated Table 7. Voltage and current operating behaviors.
• Specified correct max. value for IIN.
• Updated Table - 9 Power consumption operating behaviors.
• Rows added for IDD for reset pin hold low (IDD_RESET_LOW) at 1.7V and 3V.
• Measurement unit updated for IDD_VLLS1 from nA to μA.
• Footnote 1 was moved in the beginning of the table as text.
• Added Table - 11 EMC radiated emissions operating behaviors for 64-pin LQFP
package under section 2.2.6.
• Updated Table - 18 (IRC48M specification) and Table - 19 (IRC8M/2M specification)
under section 3.3.1 - 'MCG-Lite specifications'.
• Removed supply voltage (VDD), temperature range (T), untrimmed (fIRC_UT), trim
function (ΔfIRC_C, ΔfIRC_F) data from Table - 18 (IRC48M specification).
• Removed supply voltage (VDD), temperature range (T) data from Table - 19
(IRC8M/2M specification).
• Added Figure 6. IRC8M Frequency Drift vs Temperature curve after Table - 19
(IRC8M/2M specification).
• Updated Table 29. VREF full-range operating behaviors.
• Removed Ac(Aging coefficient) row.
• Added Tchop_osc_stup parameter.
• Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I2C.
• Added VREF specifications (VREFH and VREFL) to Table 26. 16-bit ADC operating
conditions.
• Removed note: “This device does not have the USB_CLKIN signal available.”
512 August
2015
• In Table 9. Power consumption operating behaviors:
• Updated Max. values of IDD_WAIT, IDD_VLPW, IDD_STOP, IDD_VLPS, IDD_LLS,
IDD_VLLS3, IDD_VLLS1, IDD_VLLS0.
• Modified unit of IDD_VLLS0 from nA to μA.
• Removed IDD_RESET_LOW information.
• In Table 13. Device clock specifications, added a footnote for normal run mode.
• In Table 15. Thermal operating requirements, modified the footnote for Ambient
temperature.
• In Table 18. IRC48M specification, removed fIRC_T data and added Δfirc48m_of_lv and
Δfirc48m_of_hv specifications.
• In Table 26. 16-bit ADC operating conditions, updated Max. value of fADCK and Crate.
5.1 16 Nov 2015 • Added 36-pin WLCSP package information.
6 25 Jan 2016 • Completed all the TBDs of the 36-pin WLCSP package.
Revision History
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©2014-2016 Freescale Semiconductor, Inc.
Document Number KL17P64M48SF6
Revision 6, 02/2016