AUIRFP2907
HEXFET® Power MOSFET
08/11/11
www.irf.com 1
PD -97692A
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Features
lAdvanced Planar Technology
lLow On-Resistance
lDynamic dV/dT Rating
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
lRepetitive Avalanche Allowed
up to Tjmax
lLead-Free, RoHS Compliant
lAutomotive Qualified*
Description
Specifically designed for Automotive applications, this
Stripe Planar design of HEXFET® Power MOSFETs
utilizes the latest processing techniques to achieve
low on-resistance per silicon area. This benefit
combined with the fast switching speed and ruggedized
device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely
efficient and reliable device for use in Automotive and
a wide variety of other applications.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the
specifications is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Ambient temperature (TA) is 25°C, unless otherwise specified.
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
GDS
Gate Drain Source
V
(BR)DSS
75V
R
DS(on)
typ. 3.6mΩ
max 4.5m
Ω
I
D (Silicon Limited)
209A
h
I
D (Package Limited)
90A
Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited) A
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Package Limited)
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
d
mJ
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
c
mJ
dv/dt
Peak Diode Recovery dv/dt
e
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case )
Mounting Torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
Junction-to-Case
j
––– 0.32
R
θCS
Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
R
θJA
Junction-to-Ambient ––– 40
5.0
1970
See Fig. 12a, 12b, 15, 16
470
3.1
± 20
Max.
209
h
148
h
840
90
-55 to + 175
300
10 lbf
y
in (1.1N
y
m)
AUTOMOTIVE GRADE
TO-247AC
AUIRFP2907
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Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.25mH
RG = 25Ω, IAS = 125A. (See Figure 12).
ISD ≤ 125A, di/dt ≤ 260A/μs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
S
D
G
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 90A.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
Rθ is measured at TJ of approximately 90°C.
Static Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min.
Typ.
Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
75
–––
–––
V
Δ
V
(BR)DSS
/
Δ
T
J
Breakdown Voltage Temp. Coefficient
–––
0.085
–––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
3.6
4.5
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
gfs
Forward Transconductance
130
–––
–––
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
μA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
Gate-to-Source Reverse Leakage
–––
–––
-200
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min.
Typ.
Units
Q
g
Total Gate Charge
–––
410
620
Q
gs
Gate-to-Source Charge
–––
92
140
nC
Q
gd
Gate-to-Drain ("Miller") Charge
–––
140
210
t
d(on)
Turn-On Delay Time
–––
23
–––
t
r
Rise Time
–––
190
–––
t
d(off)
Turn-Off Delay Time
–––
130
–––
ns
t
f
Fall Time
–––
130
–––
L
D
Internal Drain Inductance
–––
5.0
–––
Between lead,
nH 6mm (0.25in.)
L
S
Internal Source Inductance
–––
13
–––
from package
and center of die contact
C
iss
Input Capacitance
–––
13000
–––
C
oss
Output Capacitance
–––
2100
–––
pF
C
rss
Reverse Transfer Capacitance
–––
500
–––
C
oss
Output Capacitance
–––
9780
–––
C
oss
Output Capacitance
–––
1360
–––
C
oss
eff.
Effective Output Capacitance
g
–––
2320
–––
Diode Characteristics
Parameter
Min.
Typ.
Units
I
S
Continuous Source Current
–––
–––
209
h
(Body Diode) A
I
SM
Pulsed Source Current
–––
–––
840
(Body Diode)
c
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
140
210
ns
Q
rr
Reverse Recovery Charge
–––
880
1320
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
T
J
= 25°C, I
F
= 125A
di/dt = 100A/μs
f
T
J
= 25°C, I
S
= 125A, V
GS
= 0V
f
showing the
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 125A
f
MOSFET symbol
V
DD
= 38V
I
D
= 125A
R
G
= 1.2
Ω
Conditions
V
GS
= 10V
f
V
GS
= 0V
ƒ = 1.0MHz, See Fig. 5
V
GS
= 0V, V
DS
= 0V to 60V
V
GS
= 0V, V
DS
= 60V, ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
DS
= 25V, I
D
= 125A
f
I
D
= 125A
V
DS
= 60V
V
GS
= 20V
V
GS
= -20V
V
GS
= 10V
f
V
DS
= 75V, V
GS
= 0V
V
DS
= 60V, V
GS
= 0V, T
J
= 150°C
mΩ
V
DS
= 25V
Conditions
V
DS
= V
GS
, I
D
= 250μA
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Qualification standards can be found at International Rectifiers web site: http//www.irf.com/
 Exceptions to AEC-Q101 requirements are noted in the qualification report.
 Highest passing voltage.
Qualification Information
†
TO-247 MSL1
Qualification Level
Automotive
(per AEC-Q101)
††
Comments: This part number(s) passed Automotive qualification.
IR’s Industrial and Consumer qualification level is granted by
extension of the higher Automotive level.
Charged Device
Model
Class C5 (+/- 1125V)
†††
AEC-Q101-005
Moisture Sensitivity Level
RoHS Compliant Yes
ESD
Machine Model Class M4 (+/- 425V)
†††
AEC-Q101-002
Human Body Model Class H3A (+/- 8000V)
†††
AEC-Q101-001
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
0.1 1 10 100
20μs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
10
100
1000
0.1 1 10 100
20μs PULSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
1
10
100
1000
4.0 5.0 6.0 7.0 8.0 9.0 10.0
V = 25V
20μs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
209A
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0100 200 300 400 500 600 700
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
125A
V = 37V
DS
V = 60V
DS
0.1
1
10
100
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
110 100
VDS, Drain-to-Source Voltage (V)
0
4000
8000
12000
16000
20000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS
= 0V, f = 1 MHZ
Ciss
= C
gs + C
gd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds
+ C
gd
0.1 1 10 100 1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100μsec
1msec
10msec
DC
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
40
80
120
160
200
240
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
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25 50 75 100 125 150 175
0
1000
2000
3000
4000
5000
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
51A
88A
125A
QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3μF
50KΩ
.2μF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 14. Threshold Voltage Vs. Temperature
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th) , Variace ( V )
ID = 250μA
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
400
800
1200
1600
2000
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 125A
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ΔTj = 25°C due to
avalanche losses
0.01
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Fig 17. For N-channel HEXFET® power MOSFETs
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
RG
VDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
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TO-247AC Part Marking Information
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
AUFP2907
YWWA
XX or XX
Date Code
Y= Year
WW= Work Week
A= Automotive, LeadFree
Part Number
IR Logo
Lot Code
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Ordering Information
Base part
number
Package Type Standard Pack Complete Part Number
Form
Quantity
AUIRFP2907
TO-247
Tube
25
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regards to product discontinuance and process change notification. All products are sold subject to IRs terms
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accordance with IRs standard warranty. Testing and other quality control techniques are used to the extent
IR deems necessary to support this warranty. Except where mandated by government requirements, testing
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