Transmit VGA for U
se with
RF DACs and Transceivers
Data Sheet
ADL6317
Rev. B Document Feedback
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FEATURES
Transmit VGA for RF DAC, transceiver, and SoC to power
amplifier interface
RF output frequency range: 1500 MHz to 3000 MHz
Internal balun with bias-tee to supply RF DAC outputs
Integrated VVA attenuation range with on-chip DAC: 20.5 dB
2-stage high linearity amplifiers
RF DSA attenuation range: 15.5 dB with 0.5 dB step
resolution
50 Ω differential inputs and 50 Ω single-ended output
Fully programmable via a 4-wire SPI
Single 5 V supply
38-terminal, 10.5 mm × 5.5 mm LGA
APPLICATIONS
2G/3G/4G/long-term evolution (LTE) in FDD/TDD broadband
communication systems
GENERAL DESCRIPTION
The ADL6317 is a transmit variable gain amplifier (VGA) that
provides an interface from radio frequency digital-to-analog
converters (RF DACs), transceivers, and systems on a chip (SoC)
to power amplifiers. Integrated balun and hybrid couplers allow
high performance RF capability in the frequency range of
1500 MHz to 3000 MHz.
To optimize performance vs. power level, the ADL6317
includes a voltage variable attenuator (VVA), high linearity
amplifiers, and a digital step attenuator (DSA). All of the
devices integrated into the ADL6317 are programmable via a
4-wire serial port interface (SPI).
The ADL6317 is manufactured on an advanced silicon
germanium (SiGe), bipolar complementary metal oxide
semiconductor (BiCMOS) process.
Table 1. Related Devices in Transmit VGA Family
Parameter Frequency Range (MHz)
ADL6316 500 to 1000
ADL6317 1500 to 3000
FUNCTIONAL BLOCK DIAGRAM
DAC
AMP1
ADL6317
CS5MUXOUT VVA_ANALOG
ANALOG
MUX TEMPERATURE
SENSOR 3.3V
LDO 1.8V SPI
LDO
ADC
GND GND
SERI AL PORT INT E RFACE
FUSE
BLOCK
AMP1
AMP2
AMP2
VVA
TXEN CS SDI SCLK SDO GND
GND
GND
GND
IN_N
IN_P
VDAC
GND
GND GND GND GND V50AMP1 V33FUSE V50AMP2
GND GND
RFOUT
GND
GND
GND
GND
CS4
VVA
DSA
DSA
20829-001
Figure 1.
ADL6317 Data Sheet
Rev. B | Page 2 of 38
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Digital Logic Timing .................................................................... 4
Absolute Maximum Ratings ........................................................... 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions ............................ 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
RF Input Balun with DAC Interface Network ....................... 14
Quadrature Hybrid .................................................................... 14
RF Signal Chain .......................................................................... 14
Basic Connections .......................................................................... 15
Programmability Guide ................................................................. 16
Signal Path Modes ...................................................................... 16
Auxiliary Mux Control .............................................................. 16
Serial Port Interface (SPI) ......................................................... 18
Device Setup .................................................................................... 19
Applications Information ............................................................. 21
Linearity Optimization .............................................................. 21
Performance and Power Optimization ................................... 21
Adjacent and Alternate Channel Power Ratios on LTE
Operation .................................................................................... 21
Layout .......................................................................................... 22
Characterization Setups ................................................................. 23
Register Summary .......................................................................... 24
Register Details ............................................................................... 25
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
REVISION HISTORY
5/2020—Revision B: Initial Version
Data Sheet ADL6317
Rev. B | Page 3 of 38
SPECIFICATIONS
V50AMP1 = V50AMP2 = 5 V, TA = 25°C, input power (PIN) = −25 dBm (−25 dBm per tone for two tones), VVA attenuation = 0 dB, DSA
attenuation = 0 dB, source resistance (RS) = load resistance (RL) = 50 Ω, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Units
FREQUENCY RANGE 1500 3000 MHz
1850 MHz
Power Gain 33.7 dB
Output 1 dB Compression Point (OP1dB) 25.7 dBm
Output Second-Order Intercept (OIP2) 49.2 dBm
Output Third-Order Intercept (OIP3) 40.9 dBm
Second Harmonic (HD2) 82.1 dBc
Third Harmonic (HD3)
47.2
dBc
Noise Figure (NF) 6.0 dB
2150 MHz
Power Gain 33.6 dB
OP1dB 24.8 dBm
OIP2 51.8 dBm
OIP3 38.4 dBm
HD2 76.1 dBc
HD3 48.8 dBc
NF 6.0 dB
2600 MHz
Power Gain 34.0 dB
OP1dB 22.8 dBm
OIP2 53.8 dBm
OIP3 34.5 dBm
HD2 84.6 dBc
HD3 50.7 dBc
NF 5.5 dB
RF INPUT/OUTPUT CHARACTERISTICS
Input
Impedance Differential 50 Ω
Return Loss Inband, 2150 MHz −18 dB
Output
Impedance Single-ended 50 Ω
Return Loss Inband, 2150 MHz −17.4 dB
Gain Flatness Deviation from best linear fit at 1850 MHz, 2150 MHz,
and 2600 MHz
Over ±100 MHz bandwidth ±0.1 dB
Over ±150 MHz bandwidth ±0.2 dB
VOLTAGE VARIABLE ATTENUATOR Via 12-bit integrated DAC or external analog voltage on
VVA_ANALOG pin
Range 20.5 dB
Gain Settling Time Minimum attenuation to maximum attenuation by VVA
DAC
386.8 ns
Maximum attenuation to minimum attenuation by VVA
DAC
1.681 µs
DSA Attenuation
Range 15.5 dB
Resolution 0.5 dB
Gain Settling Time Minimum attenuation to maximum attenuation 304.4 ns
Maximum attenuation to minimum attenuation 195.0 ns
ADL6317 Data Sheet
Rev. B | Page 4 of 38
Parameter Test Conditions/Comments Min Typ Max Units
DIGITAL LOGIC
Input Voltage SCLK, SDI, CS, CS4, CS5, TXEN
High (VIH) 1.07 V
Low (VIL) 0.68 V
Input Current
High (IIH) −100 μA
Low (IIL) 100 μA
Output Voltage SDO
At 1.8 V Register 0x121, Bit 4 = 0x0
High (VOH) Output high current (IOH) = −100 μA or −1 mA static
load
1.5 V
Low (VOL) Output low current (IOL) = 100 μA or 1 mA static load 0.2 V
At 3.3 V Register 0x121, Bit 4 = 0x1
High (VOH) IOH = −100 μA or −1 mA static load 2.7 V
Low (VOL) IOL = 100 μA or 1 mA static load 0.2 V
POWER SUPPLY
Voltage 4.75 5.0 5.25 V
Supply Current High performance mode 435 mA
Low power mode 310 mA
Power Down Current 6 mA
DIGITAL LOGIC TIMING
Table 3.
Parameter Description Min Typ Max Unit
fSCLK Maximum serial clock rate, 1/tSCLK 25 MHz
tPWH Minimum period that SCLK is in logic high state 10 ns
tPWL Minimum period that SCLK is in logic low state 10 ns
tDS Setup time between data and rising edge of SCLK 5 ns
tDH Hold time between data and rising edge of SCLK 5 ns
tDCS Setup time between falling edge of CS and rising edge of SCLK 10 ns
tDV Maximum time delay between falling edge of SCLK and output data valid for a read operation 5 ns
Timing Diagrams
R/W A3 A2 A1 A0 D7
N
D6
0
D5
0
D0
0
D1
0
D2
0
D3
0
INSTRUCT ION CY CLE DATA TRANSF E R CY CLE
SCLK
SDI
CS
A7 A6 A5 A4A80CS4 0 0 0CS5
ADDRESS
CHIP ID
20829-002
Figure 2. Serial Port Interface Register Timing, MSB First
Data Sheet ADL6317
Rev. B | Page 5 of 38
20829-003
SCLK
CS
SDI R/W CS5 CS4 0
t
SCLK
t
DCS
t
DH
t
DS
t
PWH
A2 A1 A_LSB D_MSB D6 D5 D1 D_LSB
tPWL
A7
A_MSB
0 0 0
Figure 3. Timing Diagram for the Serial Port Interface Register Write
SCLK
CS
SDI R/W CS5 CS4 0A2 A1 A_LSB
DON’T
CARE DON’T
CARE DON’T
CARE DON’T
CARE
A7
A_MSB
000
D_MSB D6 D5 D1 D_LSB
SDO
t
DV
DON’T
CARE
20829-004
Figure 4. Timing Diagram for Serial Port Interface Register Read
ADL6317 Data Sheet
Rev. B | Page 6 of 38
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
V50AMP1, V50AMP2 −0.3 V to +5.5V
V33FUSE −0.3 V to +3.6 V
VDAC −0.3 V to +3.6 V
VVA_ANALOG −0.3 V to +3.6 V
CS, SCLK, SDI, SDO, CS4, CS5, TXEN −0.3 V to +3.6 V
RF Input Power (IN_N, IN_P) at 50 Ω 10 dBm
Operating Temperature Range
(Measured at Exposed Pad)
−40°C to +105°C
Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the conduction thermal resistance from junction to case where
the case temperature is measured at the bottom of the package.
The thermal resistance values specified in Table 5 are simulated
based on JEDEC specifications (unless specified otherwise) and
should be used in compliance with JESD51-12.
Table 5. Thermal Resistance1, 2
Package Type θJA θJC BOTTOM Unit
CC-38-1
21.4
7.6 °C/W
1 For θJC BOTTOM, the case bottom is controlled at105°C and the case top is
controlled at 100°C.
2 Using enhanced heat removal (for example, PCB, heat sink, and airflow)
techniques to improve thermal resistance values.
ESD CAUTION
Data Sheet ADL6317
Rev. B | Page 7 of 38
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
GND
2
IN_N
EPAD1 EPAD2
3
GND
20
GND
7
GND
8
GND
9
NIC
10
GND
26
IN_P
4
VDAC
5
GND
6
NIC
11
GND
12
V50AMP1
13
GND
14
V33FUSE
15
NIC
16
V50AMP2
17
NIC
18
GND
19
NIC
27
CS4
28
CS5
29
VVA_ANALOG
30
GND
31
MUXOUT
32
SDO
33
SCLK
34
SDI
35
CS
36
TXEN
37
GND
38
GND
21
GND
22
RFOUT
23
GND
24
GND
25
ADL6317
TOP VIEW
(Not to Scal e)
NOTES
1. NI C = NOT INTE RNALL Y CONNECT E D. T HIS PIN HAS NO P HY S ICAL CONNECT IO N WITHI N THE CHI P .
2. EX P OSE D P AD 1. EPAD1 IS INTE RNALL Y CONNECT E D TO E P AD2. T HE E X P OSED P AD M US T BE
CONNECTED TO GRO UND FOR E LECTRICAL AND T HE RM AL PURPOSE S.
3. EX P OSE D P AD 2. EPAD2 IS INTE RNALL Y CONNECT E D TO E P AD1. T HE E X P OSED P AD M US T BE
CONNECTED TO GRO UND FOR E LECTRICAL AND T HE RM AL PURPOSES .
20829-005
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 6, 7, 8, 9, 12, 14, 19, 20, 21, 22, 24,
25, 26, 31, 38
GND Ground.
3 IN_N RF Input, Negative.
4 IN_P RF Input, Positive.
5 VDAC Supply Voltage for External RF DAC. This pin can be left open during operation
without the RF DAC.
10, 11, 16, 18, 27 NIC No Internal Connection. These pins have no physical connection within the chip.
13 V50AMP1 Amplifier 1 Analog Power Supply (5.0 V).
15 V33FUSE VCO Low Dropout (LDO) Regulator Bypass. This pin is optionally 3.3 V when the
3.3 V LDO regulator is off.
17 V50AMP2 Amplifier 2 Analog Power Supply (5.0 V).
23 RFOUT RF Output.
28, 29 CS4, CS5 Chip Select. Connect these pins to ground. Refer to the Multiple Chip
Operation to Share SPI Bus section for information about the connections in a
multiple chip operation.
30 VVA_ANALOG Analog Voltage Control for VVA.
32 MUXOUT Test Mux Output.
33 SDO Serial Port Data Output.
34 SCLK Serial Port Clock Input.
35 SDI Serial Port Data Input.
36 CS Serial Port Latch Enable Input.
37 TXEN Amplifier Enable, DSA Attenuation, and Trim Value Selection.
EPAD1 Exposed Pad 1. EPAD1 is internally connected to EPAD2. The exposed pad must
be connected to ground for electrical and thermal purposes.
EPAD2
Exposed Pad 2. EPAD2 is internally connected to EPAD1. The exposed pad must
be connected to ground for electrical and thermal purposes.
ADL6317 Data Sheet
Rev. B | Page 8 of 38
TYPICAL PERFORMANCE CHARACTERISTICS
V50AMP1 = V50AMP2 = 5 V, TA = 25°C, input power= −25 dBm (−25 dBm per tone for two tones), VVA attenuation = 0 dB, DSA attenuation
= 0 dB, RS = RL = 50 Ω, unless otherwise noted.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
GAI N (dB)
FREQUENCY (MHz)
DSA_ATTEN_x[4:0] = 0 ( Decim al )
DSA_ATTEN_x[4:0] = 31 ( Decim al )
20829-006
Figure 6. Gain vs. Frequency, 0.5 dB DSA Steps
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
GAI N (dB)
FREQUENCY (MHz)
VVA_ATTEN[11:0] = 4000 ( Decim al )
VVA_ATTEN[11:0] = 0 ( Decim al )
20829-007
Figure 7. Gain vs. Frequency, 100 VVA_ATTEN[11:0] Steps
30.00
30.25
30.50
30.75
31.00
31.25
31.50
31.75
32.00
32.25
32.50
32.75
33.00
33.25
33.50
33.75
34.00
34.25
34.50
34.75
35.00
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
GAI N (dB)
FREQUENCY (MHz)
SUPPLY VOLT AGE = 4.75V
SUPPLY VOLT AGE = 5.00V
SUPPLY VOLT AGE = 5.25V
20829-008
Figure 8. Gain vs. Frequency for Various Supplies
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
GAIN (dB)
FREQUENCY (MHz)
T
C
= –20°C
T
C
= +40°C
T
C
= +105°C
20829-009
Figure 9. Gain vs. Frequency for Various Temperatures
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
ATTENUAT ION ( dB)
DSA_AT TEN_x[4: 0] ( Decimal Cod e)
FREQUENCY = 1850MHz
FREQUENCY = 2140MHz
FREQUENCY = 2600MHz
20829-010
Figure 10. Attenuation vs. DSA_ATTEN_x[4:0] at 1850 MHz, 2150 MHz, and
2600 MHz, VVA Attenuation = 0 dB
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
–25
–24
–23
–22
–21
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0500 1000 1500 2000 2500 3000 3500
VVA VOLTAGE (V)
ATTENUATION (dB)
VVA_AT TEN[ 11: 0] ( Decimal Cod e)
FREQUENCY = 1850M Hz
FREQUENCY = 2140M Hz
FREQUENCY = 2600M Hz
20829-011
Figure 11. Attenuation and VVA Voltage vs. VVA_ATTEN[11:0] at 1850 MHz,
2150 MHz, and 2600 MHz, DSA Attenuation = 0 dB)
Data Sheet ADL6317
Rev. B | Page 9 of 38
20.0
20.5
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
28.5
29.0
29.5
30.0
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
OP1dB (dBm)
FREQUENCY (MHz)
SUPPLY VOLT AGE = 4.75V
SUPPLY VOLT AGE = 5.00V
SUPPLY VOLT AGE = 5.25V
20829-012
Figure 12. OP1dB vs. Frequency for Various Supplies
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
OP1dB (dBm)
FREQUENCY (MHz)
T
C
= –20° C
T
C
= +40°C
T
C
= +105°C
20829-013
Figure 13. OP1dB vs. Frequency for Various Temperatures
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
OIP3/OIP2 (dBm)
FREQUENCY (MHz)
OI P 3 ( dBm)
OI P 2 ( dBm)
VVA AT TENUATION = 0dB
VVA AT TENUATION = 10dB
VVA AT TENUATION = 20.5dB
20829-014
Figure 14. OIP3/OIP2 vs. Frequency at Various VVA Attenuation Values,
DSA Attenuation = 0 dB
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
OIP3/OIP2 (dBm)
FREQUENCY (MHz)
OI P 3 ( dBm)
OI P 2 ( dBm)
DSA AT TENUAT ION = 0dB
DSA AT TENUAT ION = 8dB
DSA AT TENUAT ION = 15.5d B
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
20829-015
Figure 15. OIP3/OIP2 vs. Frequency at Various DSA Values,
VVA Attenuation = 0 dB
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
OIP3/OIP2 (dBm)
FREQUENCY (MHz)
OI P 3 ( dBm)
OI P 2 ( dBm)
T
C
= +105°C
T
C
= +40°C
T
C
= –20° C
20829-016
Figure 16. OIP3/OIP2 vs. Frequency for Various Temperatures
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
–40
–39
–38
–37
–36
–35
–34
–33
–32
–31
–30
–29
–28
–27
–26
–25
–24
–23
–22
–21
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
OIP3 (dBm)
INPUT POWER (dBm)
T
C
= +105°C
T
C
= +40°C
T
C
= –20° C
FREQUENCY = 1850MHz
FREQUENCY = 2150MHz
FREQUENCY = 2600MHz
20829-017
Figure 17. OIP3 vs. Input Power for Various Temperatures at 1850 MHz,
2150 MHz, and 2600 MHz
ADL6317 Data Sheet
Rev. B | Page 10 of 38
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
–40
–39
–38
–37
–36
–35
–34
–33
–32
–31
–30
–29
–28
–27
–26
–25
–24
–23
–22
–21
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
OIP2 (dBm)
INPUTPOWER (dBm)
T
C
= +105°C
T
C
= +40°C
T
C
= –20° C
FRE Q UE NCY = 1850M Hz
FRE Q UE NCY = 2150M Hz
FRE Q UE NCY = 2600M Hz
20829-018
Figure 18. OIP2 vs. Input Power for Various Temperatures at 1850 MHz,
2150 MHz, and 2600 MHz
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
NOISE FIGURE (dB)
FREQUENCY (MHz)
TC = +105°C
TC = +40°C
TC = –20°C
VVA AT TENUATION = 0dB
VVA AT TENUATION = 10dB
VVA AT TENUATION = 20.5dB
20829-019
Figure 19. Noise Figure vs. Frequency for Various Temperatures at Various
VVA Values, DSA Attenuation = 0 dB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
NOISE FIGURE (dB)
FREQUENCY (MHz)
T
C
= +105°C
T
C
= +40°C
T
C
= –20° C
DSA AT TENUAT ION = 0dB
DSA AT TENUAT ION = 8dB
DSA AT TENUAT ION = 15.5d B
20829-020
Figure 20. Noise Figure vs. Frequency for Various Temperatures at Various
DSA Values, VVA Attenuation = 0 dB
0
5
10
15
20
25
30
35
40
45
50
55
60
0 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
GAIN (dB), OP1dB (dBm), OIP3 (dBm),
OIP2 (dBm), NOISE FIGURE (dB)
VVA AT TENUATION (dB)
OIP2(dBm)
OIP3(dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
20829-021
Figure 21. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation,
DSA Attenuation = 0 dB, Frequency = 1850 MHz
0
5
10
15
20
25
30
35
40
45
50
55
60
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GAIN (dB), OP1dB (dBm), OIP3 (dBm),
OIP2 (dBm), NOISE FIGURE (dB)
DSA AT TENUAT ION ( dB)
OIP2 (dBm)
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
20829-022
Figure 22. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation,
VVA Attenuation = 0 dB, Frequency = 1850 MHz
0
5
10
15
20
25
30
35
40
45
50
55
60
012345678910 11 12 13 14 15 16 17 18 19 20 21
GAIN (dB), OP1dB (dBm), OIP3 (dBm),
OIP2 (dBm), NOISE FIGURE (dB)
VVA AT TENUATION (dB)
OIP2 (dBm)
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
20829-023
Figure 23. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation,
DSA Attenuation = 0 dB, Frequency = 2150 MHz
Data Sheet ADL6317
Rev. B | Page 11 of 38
0
5
10
15
20
25
30
35
40
45
50
55
60
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GAIN (dB), OP1dB (dBm), OIP3 (dBm),
OIP2 (dBm), NOISE FIGURE (dB)
DSA AT TENUAT ION ( dB)
OIP2 (dBm)
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
20829-026
Figure 24. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation,
VVA Attenuation = 0 dB, Frequency = 2150 MHz
0
5
10
15
20
25
30
35
40
45
50
55
60
01234 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
GAIN (dB), OP1dB (dBm), OIP3 (dBm),
OIP2 (dBm), NOISE FIGURE (dB)
VVA AT TENUATION (dB)
OIP2 (dBm)
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
20829-025
Figure 25. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation,
DSA Attenuation = 0 dB, Frequency = 2600 MHz
0
5
10
15
20
25
30
35
40
45
50
55
60
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GAIN (dB), OP1dB (dBm), OIP3 (dBm),
OIP2 (dBm), NOISE FIGURE (dB)
DSA AT TENUAT ION ( dB)
OIP2 (dBm)
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
20829-024
Figure 26. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation,
VVA Attenuation = 0 dB, Frequency = 2600 MHz
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
50
70
90
110
130
150
170
190
210
230
250
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
PTAT VOLTAGE (V)
PT AT ADC CODE
JUNCTION TEMP E RATURE ( °C)
20829-027
Figure 27. Proportional to Absolute Temperature (PTAT) ADC Code and PTAT
Voltage vs. Junction Temperature
CH1 800mV 1MΩ –741mV M200ns
T 10.3004000µs
CH2 980mV 50Ω 1.36V
1
2
20829-028
386.81ns
START TIME STOP TIME
Figure 28. VVA Gain Settling Time, Minimum to Maximum VVA Attenuation
CH1 800mV 1MΩ –741mV M500ns
T 11.6497800
CH2 980mV 50Ω 1.36V
1
2
20829-029
1.6813µs
START TIME STO P TIM E
Figure 29. VVA Gain Settling Time, Maximum to Minimum VVA Attenuation
ADL6317 Data Sheet
Rev. B | Page 12 of 38
CH1 700mV 1MΩ –585mV M100ns
T 10.1981000µs
CH2 980mV 50Ω 1.58V
1
2
20829-030
304.40ns
START TIME STOP TI ME
Figure 30. DSA Gain Settling Time, Minimum to Maximum DSA Attenuation
CH1 700mV 1MΩ –585mV M50.0ns
T 10.1197170µs
CH2 980mV 50Ω 1.58V
1
2
20829-031
195.05ns
START TIME STOP TIME
Figure 31. DSA Gain Settling Time, Maximum to Minimum DSA Attenuation
CH1 700mV 1MΩ –585mV M50.0ns
T 10.1197170µs
CH2 980mV 50Ω 1.58V
1
2
20829-032
182.97ns
START TIME ST OP TI M E
Figure 32. TXEN Response Time, Measured from Amplifier 1 and Amplifier 2
Disabled (DSA Attenuation = 15.5 dB) to Amplifier 1 and Amplifier 2 Enabled,
(DSA Attenuation = 0 dB)
CH1 700mV 1MΩ –689mV M20.0ns
T 10.0359600µ s
CH2 980mV 50 Ω 1.45V
1
2
20829-033
54.5ns
START TIME STOP T I ME
Figure 33. TXEN Response Time Measured from Amplifier 1 and Amplifier 2
Enabled (DSA = 0 dB) to Amplifier 1 and Amplifier 2 Disabled (DSA = 15.5 dB)
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
DNL ERROR (dB)/ INL E RROR(d B)
DSA_AT TEN_x[4: 0] ( Decimal Cod e)
DNL
INL
20829-034
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Figure 34. DSA Gain Step Error, Frequency = 1850 MHz
RET URN LOS S ( dB)
0
–5
–10
–15
–25
–35
–45
–20
–30
–40
1.4 1.6 1.8 2.0
FREQUENCY ( GHz)
2.2 2.4 2.6 2.8 3.0
20829-036
WITHOUT TUNING, OPTIMUM ABOVE 2.1GHz
WITH TUNING TO OPTIMIZE FOR 1.8GHz TO 2.1GHz
WITH TUNING TO OPTIMIZE BELOW 1.8GHz
Figure 35. Return Loss of Differential RF Input S11 from 1.5 GHz to 3 GHz
Data Sheet ADL6317
Rev. B | Page 13 of 38
RET URN LOS S ( dB)
0
–5
–10
–15
–20
–25
–30 1.4 1.6 1.8 2.0
FREQUENCY ( GHz)
2.2 2.4 2.6 2.8 3.0
20829-136
Figure 36. Return Loss of Single-Ended RF Output S22 from 1.5 GHz to 3 GHz
150
155
160
165
170
175
180
185
190
195
200
205
210
215
220
225
230
235
240
245
250
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
AMPLIFIE R 1 AND AM P LI FIE R 2
SUPPLY CURRE NT (mA)
FREQUENCY (MHz)
AMPLIFIER 2 CURRENT
AMPLIFIER 1 CURRENT
T
C
= +105°C
T
C
= +40°C
T
C
= –20° C
20829-037
Figure 37. Amplifier 1 and Amplifier 2 Supply Current vs. Frequency for
Various Temperatures
ADL6317 Data Sheet
Rev. B | Page 14 of 38
THEORY OF OPERATION
The ADL6317 is a highly integrated transmit VGA used to
interface an RF DAC to the power amplifier in a transmitter.
The ADL6317 targets high dynamic range multicarrier
transmitter designs.
The ADL6317 offers multiple gain control options with an
integrated 20.5 dB VVA, on-chip DAC control or external
voltage control, a high linearity amplifier, an RF DSA with a
15.5 dB attenuation range in 0.5 dB steps, followed by the
second stage high linearity amplifier.
Putting all the building blocks of the ADL6317 together, the
signal path through the device starts with differential inputs
converted to singled-ended by the integrated balun and this
single-ended signal is then quadrature coupled by the internal
quadrature hybrid.
Next, the integrated VVA, Amplifier 1, DSA, and Amplifier 2
optimize the RF signal amplitude for performance before the
RF signal passes through the output quadrature hybrid. All the
integrated building blocks of the ADL6317 are programmable via
the SPI.
RF INPUT BALUN WITH DAC INTERFACE
NETWORK
The ADL6317 converts a single-channel, 50 Ω, input differen-
tial signal to a single-ended signal via the integrated balun.
Wideband matching allows the DAC to operate over a
frequency range from 1500 MHz to 3000 MHz, and a bias tee is
included to provide dc bias for the RF DAC.
QUADRATURE HYBRID
Integrated quadrature hybrids at the RF input and RF output
allow wideband performance gain and match with a low input
and output reflection coefficient to the RF DAC and PA.
RF SIGNAL CHAIN
The RF path includes a 20.5 dB VVA, the first stage of the fixed
gain amplifier, a 15.5 dB DSA, and the second stage of the fixed
gain amplifier (see Figure 38). The ADL6317 has two modes of
control of the VVA attenuation: internal analog control using an
integrated 12-bit DAC and external analog control. For internal
control, use Register 0x104, Bits[3:0] and Register 0x103, Bits[7:0]
to set the attenuation. The digital bits are double buffered to
avoid major carrier glitch. For this reason, Register 0x104 must
be written before Register 0x103. For external analog control of
the VVA, a control voltage is applied to the VVA_ANALOG pin
(Pin 30). Sample register writes for VVA control are shown in
Figure 38.
Table 7. Register Writes for the Control of VVA
Addres
s
Bits
Settings Description
0x105 [1:0] 00 DAC to VVA
10 VVA_ANALOG (Pin 30) to VVA
0x104 [3:0] User
defined
12-bit DAC code to set VVA
attenuation; first, write to
Register 0x104, Bits[3:0], and
then to Register 0x103, Bits[7:0]
0x103 [7:0]
User
defined
Next, the fixed gain amplifier is used in a quadrature balanced
configuration. The DSA provides a 15.5 dB range with 0.5 dB
step resolution. The digital 5-bit DSA attenuation control is found
in Bits[4:0] of Register 0x102 and Register 0x112. Finally, the
second stage fixed gain amplifier is used in a quadrature
balanced configuration.
DAC
30
VVA_ANALOG 2
0VVA CONTROL
VVA AMP
POWER UP
DEFAULT
IN G RAY
VVA_SRC
REGISTER 0x105, BIT S [ 1: 0]
REGISTER 0x102, BIT S [ 4: 0] ( TXEN = 0)
REGISTER 0x112, BIT S [ 4: 0] ( TXEN = 1)
DSA
QUADRATURE
HYBRID
AMP
VVA_AT TEN, BITS[ 11: 0] =
REGISTER 0x104, BIT S [ 3: 0]
AND
REGISTER 0x103, BIT S [ 7: 0]
BALUN QUADRATURE
HYBRID
20829-038
Figure 38. RF Signal Chain
Data Sheet ADL6317
Rev. B | Page 15 of 38
BASIC CONNECTIONS
10PF0.1µF
270PF
ADL6317
RFOUT
VDAC
C9 C12
C5
R11
560Ω
U1
VVA_ANALOG
V50AMP1
V50AMP2
SDO
26
27
1
1
2
6
7
8
9
12
14
19
20
21
22
24
25
31
38
EPAD1
EPAD2
3
4
34
32
10
11
16
18
23
15
13 17530
AGND
0.1µF
C14
AGND
AGND
10pF0.1µF
C8 C11
1µF
C6 0.1µF
C13
AGND AGND
AGND AGND
AGND
TXEN
SDI
CS
MUXOUT
VVA_ANALOG
RFOUT
V50AMP2 V33FUSE
V50AMP1
NIC
NIC
NIC
NIC
NIC
VDAC
IN_P
IN_N
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
28
IN_N
33
SCLK
SDO
SCLK 35 SDI
CS
TXEN
36
37
V33FUSE
MUXOUT
CS5
CS4
29
AGND
IN_P
AGND
AGND
20829-039
Figure 39. Basic Connections
Table 8. Basic Connections
Functional Blocks Pin No. Mnemonic Description Basic Connection
5 V 13, 17 V50AMP1,
V50AMP2
Amplifier analog supply voltage,
5 V
Decouple these pins via 10 pF and 0.1 µF
capacitors to ground. Ensure that the decoupling
capacitors are located close to the pins.
Decoupling 15 V33FUSE 3.3 V LDO regulator decoupling Decouple this pin via 0.1 µF and 1 µF capacitors
to ground. Ensure that the decoupling capacitors
are located close to the pin.
RF Inputs 5 VDAC Supply voltage for external RF DAC VDAC can be left open during operation without
the RF DAC.
3, 4 IN_N, IN_P Differential RF inputs Connect the IN_N and IN_P pins to an RF DAC or
transceiver output in differential configuration.
VVA 30 VVA_ANALOG External VVA control voltage input Voltage input pin to control VVA attenuation.
RF Output 23 RFOUT Single-ended RF output Connect RF output to power meter, network
analyzer, noise figure meter, or spectrum analyzer.
Serial Port 33 SDO SPI data output 1.8 V to 3.3 V tolerant logic levels.
34 SCLK SPI clock 1.8 V to 3.3 V tolerant logic levels.
35 SDI SPI data input 1.8 V to 3.3 V tolerant logic levels.
36 CS Chip select active low 1.8 V to 3.3 V tolerant logic levels.
Auxiliary Mux 32 MUXOUT Mux output Connect mux output to multimeter, oscilloscope,
or spectrum analyzer.
Chip Selection 28, 29 CS4, CS5 Chip selection Connect these pins to ground.
Mode Control 37 TXEN Amplifier enable, DSA attenuation,
and trim value selection
1.8 V to 3.3 V tolerant logic levels.
Ground 1, 2, 6 to 9, 12,
14, 19 to 22, 24
to 26, 31, 38
GND Ground Connect these pins to the ground of the PCB.
Exposed Pad Not applicable EPAD1, EPAD2 Exposed pads The exposed thermal pads are on the bottom of
the package. Solder the exposed pads to the PCB
ground. EPAD1 and EPAD2 are internally
connected to each other.
ADL6317 Data Sheet
Rev. B | Page 16 of 38
PROGRAMMABILITY GUIDE
Viewing the register map at the highest level, the registers are
subdivided into the major functional blocks, as shown in Table 9.
See the Register Summary section for a complete list of all the
registers on the ADL6317.
Table 9. Memory Map Functional Groups
Register Address Functional Blocks
0x000 to 0x011 Analog Devices, Inc., SPI configuration
0x100 to 0x101, 0x106 Signal path enable
0x103 to 0x105 VVA source, VVA attenuation
0x10B, 0x11B Amplifier 2 optimization
0x102, 0x107 to 0x10A
DSA attenuation, amplifier enable,
amplifier trim, TXEN = 0 mode
0x112, 0x117 to 0x11A DSA attenuation, amplifier enable,
amplifier trim, TXEN = 1 mode
0x120 to 0x121 Auxiliary mux selection, SPI supply
control
0x127 to 0x129 ADC clock, temperature readback
0x146 to 0x148 VVA and DSA attenuation readback
SIGNAL PATH MODES
The ADL6317 has two signal path modes. This feature allows two
predefined modes of operation to be controlled by TXEN, a real-
time external pin with no SPI latency. Table 10 shows the
hardware configuration to select the desired mode.
Table 10. Mode Selection and Setup Registers
TXEN (Pin 37) Mode Enable, Setup Register
0 TXEN = 0 0x102, 0x107 to 0x10A
1 TXEN = 1 0x112, 0x117 to 0x11A
The controls of each mode of operation reside in a designated
subsection of the register map. Each operational mode includes
individual control of the enables of the amplifier blocks, DSA
attenuation, and power mode. Control of these functions reside
in Register 0x102 and Register 0x107 to Register 0x10A for
TXEN = 0 mode, or Register 0x112 and Register 0x117 to
Register 0x11A for TXEN = 1 mode. The specific mode selected
by the logic level on the TXEN pin (Pin 37) determines the state
of the registers (see Table 11).
Table 11. Control Registers for the Modes
Register Address Mode Function Block
0x102 TXEN = 0 DSA attenuation
0x112 TXEN = 1 DSA attenuation
0x107 TXEN = 0 Amplifier 1 optimization
0x117 TXEN = 1 Amplifier 1 optimization
0x108 TXEN = 0 Amplifier 1 enable
0x118 TXEN = 1 Amplifier 1 enable
0x109 TXEN = 0 Amplifier 2 optimization
0x119 TXEN = 1 Amplifier 2 optimization
0x10A TXEN = 0 Amplifier 2 enable
0x11A TXEN = 1 Amplifier 2 enable
Signal Path Enable
The signal path enable bits are located in Register 0x100,
Register 0x108, Register 0x118, Register 0x10A, and
Register 0x11A. Figure 40 shows a breakdown of the individual
blocks that the particular enable bit controls.
AUXILIARY MUX CONTROL
The ADL6317 has multiple auxiliary mux control blocks that
allow various modes of operation and monitoring points (see
Figure 41 and Table 12).
DAC
CS5MUXOUT VVA_ANALOG
ANALOG
MUX TEMPERATURE
SENSOR 3.3V
LDO 1.8V SPI
LDO
ADC
GND GND
SERI AL PO RT I NTERF ACE
FUSE
BLOCK
AMP2
AMP2
AMP1
AMP1
VVA
TXEN CS SDI SCLK SDO GND
GND
GND
GND
IN_N
IN_P
VDAC
GND
GND GND GND
1: DAC_EN
2: AMUX_BG_EN
3: ADC_EN
4: DSA_EN
5: VVA_EN
6: AMP1_E N_x
1
7: AMP2_E N_x
1
V50AMP1 V33FUSE V50AMP2
GND GND
RFOUT
GND
GND
GND
GND
CS4
VVA
DSA
DSA
20829-040
3
1
5
2
4
67
1
x = 0 (LOGIC LEVEL = 0) , 1 (LOGIC LEVEL = 1) ON TXEN PIN (PIN 37)
Figure 40. Signal Path Enable Block Diagram
Data Sheet ADL6317
Rev. B | Page 17 of 38
(REG ISTER 0x104, BIT S [ 3: 0] , REG ISTER 0x103, BIT S [ 7: 0] ) = V V A_ATTE N, BITS[ 11: 0]
PIN 30
DAC
VVA_ANALOG
00
10
VVA_SRC = RE GI S TER 0x105, BIT S [ 1: 0]
ADC INPUT
ADC CLOCK
POWER-UP DEFAULTS IN GRAY 1. 8V LDO OUTP UT
MUXOUT PI N 32
AD_COUT, BITS [ 7: 0]
VVA_CTRL
ADC INPUT
3.3V LDO OUTP UT
AMUX_3_S EL = RE GIS TER 0x120, BITS[ 6: 4]
AMUX_1_S EL = RE GIS TER 0x120, BITS[ 2: 0]
AMUX_2_S EL = RE GIS TER 0x120, BIT 3
PTAT 0
1
000
002
001
0
3
2
1
ADC
20829-041
Figure 41. Auxiliary Mux Block Diagram
Table 12. Auxiliary Mux Programming Guide
Bit Name Register Address Setting Description
AMUX_3_SEL Register 0x120, Bits[6:4] ADC input, VVA_CTRL, and ADC clock selection on mux. VVA_CTRL is the
internal control voltage signal to control VVA attenuation.
000 VVA_CTRL.
001 ADC input.
010 ADC clock.
011 Not used.
100 Not used.
101 Not used.
110 Not used.
111 Not used.
AMUX_2_SEL Register 0x120, Bit 3 ADC input selection.
0 PTAT to ADC input.
1 VVA_CTRL to ADC input.
AMUX_1_SEL Register 0x120, Bits[2:0] Select mux output.
000 PTAT.
001 Output of AMUX_3_SEL.
010 1.8 V LDO output.
011 3.3 V LDO output.
100 GND.
101 GND.
110 Not used.
111 Not used.
ADL6317 Data Sheet
Rev. B | Page 18 of 38
SERIAL PORT INTERFACE (SPI)
The SPI of the ADL6317 allows the user to configure the device
for specific functions or operations via a 4-wire SPI port. This
interface provides users with added flexibility and customization.
The serial port interface consists of four control lines: SCLK, SDI,
SDO, and CS. The timing requirements for the SPI port are
shown in Table 3.
The ADL6317 protocol consists of a read/write bit, six chip select
ID bits, and nine register address bits, followed by eight data bits.
Both the address and data fields are organized with the MSB
first and end with the LSB by default.
The ADL6317 input logic level for the write cycle is with a 1.8 V
logic level (see the digital logic parameter in Table 2).
On a read cycle, the SDO is configurable for 1.8 V (default) or
3.3 V output levels by setting SPI_1P8_3P3_CTRL bit
(Register 0x121, Bit 4).
Multiple Chip Operation to Share SPI Bus
Multiple ADL6317 devices, up to four, can be addressed using
the same 4-wire SPI, which means no extra CS line for each
device. For this capability, the chip ID bits of the ADL6317 are
reserved as the chip ID (see the SPI interface port as shown in
Figure 2).
The ADL6317 ignores any writes to addresses where the six
MSBs are not equal to the chip ID, with the exception of
Register 0x000 to Register 0x00B. The ADL6317 always accepts
writes for these registers regardless of the six MSBs of the
address.
The ADL6317 only accepts reads for addresses where the six
MSBs are equal to the chip ID, including Register 0x000 to
Register 0x00B.
Figure 42 shows how to configure the chip ID and the CS5 and
CS4 pins to share a 4-wire SPI. The CS5 and CS4 settings are
shown in gray in Figure 42.
ADL6317
DEVICE 2
CHIP ID = 100000
4-WIRE SPI
CS, SDI, SDO, SCLK
CS5 PI N
1.8V CS4 P IN
ADL6317
DEVICE 0
CHIP ID = 000000
CS5 PI N CS4 PIN
ADL6317
DEVICE 3
CHIP ID = 110000
CS5 PI N
1.8V CS4 P IN 1.8V
1.8V
ADL6317
DEVICE 1
CHIP ID = 010000
CS5 PI N CS4 PIN
20829-042
Figure 42. Multiple Chip Configuration to Share SPI Bus
Data Sheet ADL6317
Rev. B | Page 19 of 38
DEVICE SETUP
The recommended sequence of steps to set up the ADL6317 is
as follows:
1. Set up the SPI interface. See Table 13.
2. Set up the common parameters, including auxiliary mux
control. See Table 14 and Table 15.
3. Set up the operating mode. See Table 16 to Table 19.
a. Set the attenuation on the DSA.
b. Enable or disable the amplifiers.
c. Set the amplifier reference currents.
d. Set the amplifier for linearity optimization.
e. Measure the internal temperature.
Table 13. SPI Interface Setup
Address Setting Notes
0x000 0x99 Soft reset, MSB first, SDO active (4-wire SPI)
0x001 0x00 Single instruction, master/slave readback, soft reset, and master/slave transfer
0x00A 0x00 Scratch pad
Table 14. Signal Path Trim
Addres
s Setting Description
0x100 0xFF Enable the DAC, auxiliary mux band gap, ADC, bias generator, DSA, and VVA
0x101 0x01 Enable IP3 optimization and 3.3 V LDO regulator
0x106 0x00 Disable the bias current, IBIAS, via the EN_IBIASGEN_RESISTOR bit (default setting)
0x105 0x00 VVA control source from DAC
0x104 0x0F Attenuation of VVA at minimum attenuation, highest four bits of 12-bit word
0x103 0xFF Attenuation of VVA at minimum attenuation, lowest eight bits of 12-bit word
Table 15. Auxiliary Mux Control
Address Setting Description
0x120 0x00 PTAT to ADC input, PTAT on mux output
0x121 0x00 Set SPI SDO voltage to 1.8 V
Table 16. Power-Down Mode Setup, TXEN = Logic Level 0
Address Setting Description
0x102 0x1F 15.5 dB attenuation on DSA
0x107 0x80 Set Amplifier 1 reference current, IREF (TRM_AMP1_IREF_0), for low power mode
0x108 0x80 Disable Amplifier 1
0x109 0x80 Set Amplifier 2 IREF (TRM_AMP2_IREF_0) for low power mode
0x10A 0x80 Disable Amplifier 2
Table 17. Normal Operating Mode Setup, TXEN = Logic Level 1
Address Setting Description
0x112 0x00 0 dB attenuation on DSA
0x117 0x82 Set Amplifier 1 IREF (TRM_AMP1_IREF_1)
0x118 0x81 Enable Amplifier 1
0x119 0x82 Set Amplifier 2 IREF (TRM_AMP2_IREF_1)
0x11A 0x81 Enable Amplifier 2
Table 18. Linearity Optimization
Address Setting Description
0x10B 0x02 Set the TRM_AMP2_CB bit
0x11B 0x02 Set the TRM_AMP2_IP3 bit
ADL6317 Data Sheet
Rev. B | Page 20 of 38
Table 19. Internal Temperature Measurement from ADC Conversion
Address Setting Description
0x000 0x18 Make SDO active
0x100 0xFF Enable ADC
0x127 0x20 Enable ADC clock divider and set ADC clock frequency
0x120 0x00 PTAT to ADC input, PTAT on mux output
0x00A 0xCC Register dummy write
0x00A 0xCC Register dummy write
0x00A 0xCC Register dummy write
0x00A 0xCC Register dummy write
0x00A 0xCC Register dummy write
0x129 Not applicable Read temperature from ADC
Data Sheet ADL6317
Rev. B | Page 21 of 38
APPLICATIONS INFORMATION
LINEARITY OPTIMIZATION
The linearity in the ADL6317 can be optimized through
the TRM_AMP2_IP3 (Register 0x11B, Bits[1:0]) and
TRM_AMP2_CB (Register 0x10B, Bits[1:0]) settings. Set the
IP3_OFF bit (Register 0x101, Bit 1) 0x00 for OIP3
optimization. The TRM_AMP2_IP3 bits control the switches in
the second amplifier that enables optimal third-order distortion
cancellation and optimal OIP3. The TRM_AMP2_CB bits
control the common base bias current on the transistor and
allows additional linearity optimization.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
OIP3 (dBm)
FREQUENCY (MHz)
20829-043
TRM_AMP2_IP3= 0
TRM_AMP2_IP3 = 1
TRM_AMP2_IP3= 2
TRM_AMP2_IP3 = 3
Figure 43. OIP3 vs. RF Frequency for Various TRM_AMP2_IP3 Settings,
TRM_AMP2_CB = 0x02, TRM_AMP1_IREF_x and TRM_AMP2_IREF_x = 0x02
Figure 43 shows that the OIP3 is optimizable across the
TRM_AMP2_IP3 settings.
Figure 43 shows better than 1.5 dB OIP3 improvement that
correlates to 3 dB improvement on IMD3 performance at
below 1.9 GHz through linearity optimization.
PERFORMANCE AND POWER OPTIMIZATION
The ADL6317 provides another level of control to optimize
power or performance. In applications where performance is
critical, the ADL6317 offers performance optimization at the
expense of power consumption. However, if low power is the
priority, the ADL6317 offers tuning options in the amplifier
blocks of the chip to further reduce power consumption.
Table 20 shows that the potential power optimization vs.
performance can fine tune the reference current on RF
amplifier settings.
ADJACENT AND ALTERNATE CHANNEL POWER
RATIOS ON LTE OPERATION
Figure 44 shows the adjacent and alternate channel power
ratios (CPR) for the ADL6317 using 5 MHz single-carrier LTE.
The adjacent CPR is −70.4 dB and the alternative CPR is
−72.9 dB at an RF of 1850 MHz. The adjacent and alternate CPR
performance varies over output power. On the ADL6317, the
output power can be varied by adjusting the input power, the
VVA attenuation, or the DSA attenuation. Figure 45 to Figure 47
show the adjacent and alternate CPR performance vs. output
power for the different methods of controlling the ADL6317.
As shown in Figure 45, the optimum adjacent and alternate
CPR can be achievable at an output power of +8 dBm, which
corresponds to an input power of −24.6 dBm driving the ADL6317
where the internal VVA is set to 0 dB, and the DSA is set to
0 dB attenuation. Figure 46 and Figure 47 show adjacent and
alternate CPR performance vs. output power that is adjusted by
VVA attenuation and by DSA attenuation, respectively, with
−17.2 dBm of input power. Figure 45 to Figure 47 show below
−65 dB adjacent and alternate CPR performance at below
+10 dBm output power, and there is gradual degradation above
+10 dBm from the contribution to the adjacent and alternate
CPR performance of the second stage RF amplifier. When
fixing the VVA attenuation and sweeping the DSA, the
adjacent and alternate CPR performance remains constant
below 6 dBm output power (see Figure 47).
Table 20. Power Optimization vs. Performance at 1850 MHz, VVA Attenuation= 0 dB, DSA Attenuation = 0 dB, TRM_AMP2_IP3 = 0x02
TRM_AMPx_IREF_1 Setting (Decimal),
Register 0x117 and Register 0x119, Bits[3:0] DC Power (W) Gain (dB) OP1dB (dBm) OIP3 (dBm) NF (dB)
3 2.36 33.1 25.8 40.3 6.6
2 2.10 33.1 25.6 40.3 5.9
1 1.84 33.1 25.1 39.2 5.8
0 1.55 32.8 24.3 36.9 5.8
ADL6317 Data Sheet
Rev. B | Page 22 of 38
–90
–100
–80
–70
–60
–50
–40
–30
–20
–10
0
CENT ER 1.85G Hz
#RES BW 30kHz SPAN 24. 52M Hz
SW E EP 103.9ms
VBW 30kHz
(10dB/DIV)
20829-044
–72.9dBc
–70.4dBc
+5.0dBm
–70.7dBc
–73.3dBc
Figure 44. LTE Carrier, Adjacent and Alternate CPR at 1850 MHz,
VVA Attenuation = 0 dB, DSA Attenuation = 11 dB, PIN = −17.2 dBm
–90
–80
–70
–60
–50
–40
–30
–6 –4 –2 0 2 4 6 8 10 12 14 16 18
ADJACENT AND ALTE RNATE CHANNEL
POWER RATIO (dB)
OUTPUT P OWE R ( dBm)
ADJACENT CPR
ALTERNAT E CP R
20829-045
Figure 45. Adjacent and Alternate Channel Power Ratio vs. Output Power
(POUT) by PIN at 1850 MHz, LTE Test Model 1.1 (TM1.1), VVA Attenuation = 0 dB,
DSA Attenuation = 0 dB
–90
–80
–70
–60
–50
–40
–30
–6 –4 –2 0 2 4 6 8 10 12 14 16 18
ADJACENT AND ALTE RNATE CHANNEL
POWER RATIO (dB)
OUTPUT P OWE R ( dBm)
ADJACENT CPR
ALTERNAT E CP R
20829-046
Figure 46. Adjacent and Alternate Channel Power Ratio vs. Output Power
(POUT) by VVA Attenuation at 1850 MHz, LTE TM1.1, PIN = −17.2 dBm, DSA
Attenuation = 0 dB
–90
–80
–70
–60
–50
–40
–30
–2 0 2 4 6 8 10 12 14 16 18
ADJACENT AND ALTE RNATE CHANNEL
POWER RATIO (dB)
OUTPUT P OWE R ( dBm)
ADJACENT CPR
ALTERNAT E CP R
20829-047
Figure 47. Adjacent and Alternate Channel Power Ratio vs. Output Power
(POUT) by DSA Attenuation at 1850 MHz, LTE TM1.1, PIN = −17.2 dBm,
VVA Attenuation = 0 dB
LAYOUT
Solder the exposed pad on the underside of the ADL6317 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Notice the use of 19 via holes on the exposed
pad of the ADL6317-EVALZ evaluation board. Connect these
ground vias to all other ground layers on the evaluation board to
maximize heat dissipation from the device package. For more
information on the ADL6317-EVALZ evaluation board,
contact Analog Devices, Inc.
Ensure that the decoupling capacitors are located close to the
supply voltage pins.
20829-048
Figure 48. Evaluation Board Layout for the ADL6317-EVALZ
Data Sheet ADL6317
Rev. B | Page 23 of 38
CHARACTERIZATION SETUPS
The primary setup used to characterize the ADL6317 is shown in
Figure 49. The setup measures gain, HD2, HD3, OIP2, and OIP3.
RFOUT
RFIN
3dB
COMBINER
PC CONTROLLER
AGI LENT PXA N9030B
SPECTRUM ANALYZ E R
KEITHLEY S46
SWIT CH SYSTEM
ROHDE & S CHWARZ
SMA100A S I GNAL GENERATO R ROHDE & S CHWARZ
SMA100A S I GNAL GENERATO R
ADL6317
EVAL UATI ON BOARD
3dB
4-WIRE SPI PROGRAMMING AUXILIARY
MUX
BOARD SUP P LY
20829-049
Figure 49. General Characterization Setup
ADL6317 Data Sheet
Rev. B | Page 24 of 38
REGISTER SUMMARY
Table 21. Register Summary
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x000
ADI_SPI_
CONFIG
[7:0]
SOFTRESET_
LSB_
FIRST_
ENDIAN_
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_
FIRST
SOFTRESET
0x00
R/W
0x001
REG_0X0001
[7:0]
SINGLE_
INSTRUCTION CSB_
STALL MASTER_
SLAVE_RB RESERVED
SOFT_RESET
MASTER_
SLAVE_
TRANSFER
0x00
R/W
0x003
CHIPTYPE
[7:0]
CHIPTYPE
0x00
R
0x004
PRODUCT_
ID_L [7:0]
PRODUCT_ID[7:0]
0x00
R
0x005
PRODUCT_
ID_H [7:0]
PRODUCT_ID[15:8]
0x00
R
0x00A
SCRATCHPAD
[7:0]
SCRATCHPAD
0x00
R/W
0x00B
SPI_REV
[7:0]
SPI_REV
0x00
R
0x010
VARIANT_
FEOL
[7:0]
FEOL
VARIANT
0x00
R
0x011
BEOL_SIF
[7:0]
SIF
BEOL
0x01
R
0x012
SPARE_012
[7:0]
SPARE_012
0x00
R
0x013
SPARE_013
[7:0]
SPARE_013
0x00
R
0x100
SIG_PATH0_0
[7:0]
DAC_EN
AMUX_
BG_EN ADC_EN
EN_IBIASGEN
DSA_EN
VVA_EN
RESERVED
0x40
R/W
0x101
SIG_PATH1_0
[7:0]
RESERVED
IP3_OFF
LDO33_EN
0x01
R/W
0x102
SIG_PATH2_0
[7:0]
RESERVED
DSA_ATTEN_0
0x3F
R/W
0x103
SIG_PATH3_0
[7:0]
VVA_ATTEN[7:0]
0x00
R/W
0x104
SIG_PATH4_0
[7:0]
RESERVED
VVA_ATTEN[11:8]
0x00
R/W
0x105
SIG_PATH5_0
[7:0]
RESERVED
VVA_SRC
0x00
R/W
0x106
SIG_PATH6_0
[7:0]
RESERVED
EN_IBIASGEN_
RESISTOR 0x00
R/W
0x107
SIG_PATH7_0
[7:0]
BYPASS_TRM_
AMP1_IREF_0 RESERVED
TRM_AMP1_
IREF_SEL_0 TRM_AMP1_IREF_0
0x00
R/W
0x108
SIG_PATH8_0
[7:0]
BYPASS_TRM_
AMP1_EN_0 RESERVED
AMP1_EN_0
0x00
R/W
0x109
SIG_PATH9_0
[7:0]
BYPASS_TRM_
AMP2_IREF_0 RESERVED
TRM_AMP2_
IREF_SEL_0 TRM_AMP2_IREF_0
0x00
R/W
0x10A
SIG_PATHA_0
[7:0]
BYPASS_TRM_
AMP2_EN_0 RESERVED
AMP2_EN_0
0x00
R/W
0x10B
SIG_PATHB_0
[7:0]
SPARE_10B
TRM_AMP2_CB
0x00
R/W
0x112
SIG_PATH2_1
[7:0]
RESERVED
DSA_ATTEN_1
0x20
R/W
0x117
SIG_PATH7_1
[7:0]
BYPASS_TRM_
AMP1_IREF_1
RESERVED
TRM_AMP1_
IREF_SEL_1
TRM_AMP1_IREF_1
0x00
R/W
0x118
SIG_PATH8_1
[7:0]
BYPASS_TRM_
AMP1_EN_1
RESERVED
AMP1_EN_1
0x00
R/W
0x119
SIG_PATH9_1
[7:0]
BYPASS_TRM_
AMP2_IREF_1 RESERVED
TRM_AMP2_
IREF_SEL_1 TRM_AMP2_IREF_1
0x00
R/W
0x11A
SIG_PATHA_1
[7:0]
BYPASS_TRM_
AMP2_EN_1 RESERVED
AMP2_EN_1
0x00
R/W
0x11B
SIG_PATHB_1
[7:0]
SPARE_11B
TRM_AMP2_IP3
0x00
R/W
0x120
AMUX_SEL
[7:0]
RESERVED
AMUX_3_SEL
AMUX_2_
SEL AMUX_1_SEL
0x20
R/W
0x121
MULTI_FUNC_
CTRL_0111 [7:0]
RESERVED
SPI_1P8_
3P3_CTRL AMUX_EX
0x00
R/W
0x127
ADC_
CONTROL_
[7:0]
RESERVED
ADC_CLOCK_
DIV_EN
ADC_MUX_
SEL
RESERVED
ADC_CLK_FREQ
0x00
R/W
0x128
ADC_EOC
[7:0]
RESERVED
ADC_EOC
0x00
R
0x129
ADC_OUT
[7:0]
TEMP_ADC_OUT
0x00
R
0x146
GENERIC_
READBACK_2
[7:0]
VVA_ATTEN_RDBK[7:0]
0x00
R
0x147
GENERIC_
READBACK_3 [7:0]
RESERVED
VVA_ATTEN_RDBK[11:8]
0x00
R
0x148
GENERIC_
READBACK_4 [7:0]
RESERVED
DSA_ATTEN_RDBK
0x00
R
Data Sheet ADL6317
Rev. B | Page 25 of 38
REGISTER DETAILS
Address: 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG
Soft Reset Soft Reset
LSB First LSB First
Endian Endian
SDO Active SDO Active
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] SOFTRESET_ (R/W) [0] SOFTRESET (R/W)
[6] LSB_FIR S T _ (R/W) [1] LSB_FIR S T (R/W)
[5] ENDIAN_ (R/W ) [2] ENDIAN (R/W)
[4] SDOACTIVE_ (R/W) [3] SDOACTIVE (R/W )
Table 22. Bit Descriptions for ADI_SPI_CONFIG
Bits Bit Name Description Reset Access
7 SOFTRESET_ Soft Reset. 0x0 R/W
0: Reset not asserted.
1: Reset asserted.
6 LSB_FIRST_ LSB First. 0x0 R/W
0: MSB first.
1: LSB first.
5 ENDIAN_ Endian. 0x0 R/W
0: Little endian.
1: Big endian.
4 SDOACTIVE_ SDO Active. 0x0 R/W
0: SDO inactive.
1: SDO active.
3 SDOACTIVE SDO Active. 0x0 R/W
0: SDO inactive.
1: SDO active.
2 ENDIAN Endian. 0x0 R/W
0: Little endian.
1: Big endian.
1 LSB_FIRST LSB First. 0x0 R/W
0: MSB first.
1: LSB first.
0 SOFTRESET Soft Reset. 0x0 R/W
0: Reset not asserted.
1: Reset asserted.
ADL6317 Data Sheet
Rev. B | Page 26 of 38
Address: 0x001, Reset: 0x00, Name: REG_0X0001
Single Instruction Master Slave Transfer
CSB Stall Soft Reset
Master Slave Readback
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] SINGLE_INSTRUCTION (R/W) [0] MASTER_SLAVE_TRANSFER (R/W )
[6] CSB_STALL (R/W ) [2:1 ] S OFT_ R ESET (R/W)
[5] MASTER_SLAVE_RB (R/W) [4:3] RESERVED
Table 23. Bit Descriptions for REG_0X0001
Bits
Bit Name
Description
Reset
Access
7 SINGLE_INSTRUCTION Single Instruction 0x0 R/W
6 CSB_STALL CS Stall 0x0 R/W
5 MASTER_SLAVE_RB Master Slave Readback 0x0 R/W
[4:3] RESERVED Reserved 0x0 R
[2:1] SOFT_RESET Soft Reset 0x0 R/W
0 MASTER_SLAVE_TRANSFER Master Slave Transfer 0x0 R/W
Address: 0x003, Reset: 0x00, Name: CHIPTYPE
Chip Type, Read Only
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CHIPTYPE (R)
Table 24. Bit Descriptions for CHIPTYPE
Bits Bit Name Description Reset Access
[7:0] CHIPTYPE Chip Type, Read Only 0x0 R
Address: 0x004, Reset: 0x00, Name: PRODUCT_ID_L
Product ID Low, Lower 8 Bits
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] PROD U CT_ID [7 :0 ] (R)
Table 25. Bit Descriptions for PRODUCT_ID_L
Bits Bit Name Description Reset Access
[7:0] PRODUCT_ID[7:0] Product ID Low, Lower 8 Bits 0x0 R
Address: 0x005, Reset: 0x00, Name: PRODUCT_ID_H
Product ID High, Higher 8 Bits
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] PRODUCT_ ID[15:8] (R)
Table 26. Bit Descriptions for PRODUCT_ID_H
Bits Bit Name Description Reset Access
[7:0] PRODUCT_ID[15:8] Product ID High, Higher 8 Bits 0x0 R
Data Sheet ADL6317
Rev. B | Page 27 of 38
Address: 0x00A, Reset: 0x00, Name: SCRATCHPAD
Scratchpad. Used by Software to test read
and write
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] SCRATCHPAD (R/W)
Table 27. Bit Descriptions for SCRATCHPAD
Bits Bit Name Description Reset Access
[7:0] SCRATCHPAD Scratchpad. Used by Software to test read and write. 0x0 R/W
Address: 0x00B, Reset: 0x00, Name: SPI_REV
SP I Register Map Revision
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] SPI_REV (R)
Table 28. Bit Descriptions for SPI_REV
Bits Bit Name Description Reset Access
[7:0] SPI_REV SPI Register Map Revision 0x0 R
Address: 0x010, Reset: 0x00, Name: VARIANT_FEOL
Front end of line (FEOL) Variant
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] FE OL (R) [3:0] VARIANT (R)
Table 29. Bit Descriptions for VARIANT_FEOL
Bits Bit Name Description Reset Access
[7:4] FEOL Front end of line (FEOL) 0x0 R
[3:0] VARIANT Variant 0x0 R
Address: 0x011, Reset: 0x01, Name: BEOL_SIF
Serial Interface Version Back end of line (BEOL) Version
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] SIF (R) [3:0] B EOL (R)
Table 30. Bit Descriptions for BEOL_SIF
Bits Bit Name Description Reset Access
[7:4] SIF Serial Interface Version 0x0 R
[3:0] BEOL Back end of line (BEOL) Version 0x1 R
Address: 0x012, Reset: 0x00, Name: SPARE_0012
Spare Register 0x012
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] SPARE_012 (R)
Table 31. Bit Descriptions for SPARE_0012
Bits Bit Name Description Reset Access
[7:0] SPARE_012 Spare Register 0x012 0x0 R
ADL6317 Data Sheet
Rev. B | Page 28 of 38
Address: 0x013, Reset: 0x00, Name: SPARE_013
Spare Register 0x013
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] SPARE_013 (R)
Table 32. Bit Descriptions for SPARE_013
Bits Bit Name Description Reset Access
[7:0] SPARE_013 Spare Register 0x013 0x0 R
Address: 0x100, Reset: 0x40, Name: SIG_PATH0_0
DAC Enable
Auxiliary Mux Bandgap Enable VVA Enable
ADC Enable DSA Enable
Enable Bias Gener ator
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
0
[7] DAC_E N (R/W) [1:0] RESERVED
[6] AMUX_BG _EN (R/W) [2] VVA_EN (R/W)
[5] ADC_E N (R/W) [3] DSA_EN (R/W)
[4] EN_IBIASGEN (R/W)
Table 33. Bit Descriptions for SIG_PATH0_0
Bits Bit Name Description Reset Access
7 DAC_EN DAC Enable. 0x0 R/W
0: Disable DAC.
1: Enable DAC.
6 AMUX_BG_EN Auxiliary Mux Band Gap Enable. 0x1 R/W
0: Disable auxiliary mux band gap.
1: Enable auxiliary mux band gap.
5 ADC_EN ADC Enable. 0x0 R/W
0: Disable ADC.
1: Enable ADC.
4 EN_IBIASGEN Enable Bias Generator. 0x0 R/W
0: Disable bias generator.
1: Enable bias generator.
3 DSA_EN DSA Enable. 0x0 R/W
0: Disable DSA.
1: Enable DSA.
2 VVA_EN VVA Enable. 0x0 R/W
0: Disable VVA.
1: Enable VVA.
[1:0] RESERVED Reserved. 0x0 R
Data Sheet ADL6317
Rev. B | Page 29 of 38
Address: 0x101, Reset: 0x01, Name: SIG_PATH1_0
3.3V LDO E nabl e
T urn of f lineari zat ion optimizat ion
functionality for IP3 optimizat ion
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:2] RESERVED [0] L DO33_EN (R/W)
[1] IP3_OFF (R / W)
Table 34. Bit Descriptions for SIG_PATH1_0
Bits Bit Name Description Reset Access
[7:2] RESERVED Reserved. 0x0 R
1 IP3_OFF Turn off linearization optimization functionality for
IP3 optimization.
0x0 R/W
0: Turn on linearization optimization functionality.
1: Turn off linearization optimization functionality.
0 LDO33_EN 3.3 V LDO Enable. 0x1 R/W
0: Disable 3.3 V LDO.
1: Enable 3.3 V LDO.
Address: 0x102, Reset: 0x3F, Name: SIG_PATH2_0
DSA At tenuator Sett ing 0
0
1
1
1
2
1
3
1
4
1
5
1
6
0
7
0
[7:5] RESERVED [4:0] DSA_ATTEN_0 (R/W)
Table 35. Bit Descriptions for SIG_PATH2_0
Bits
Bit Name
Description
Reset
Access
[7:5] RESERVED Reserved. 0x1 R
[4:0] DSA_ATTEN_0 DSA Attenuator Setting 0. 0x1F R/W
0: 0 dB.
1: 0.5 dB.
10: 1 dB.
11: 1.5 dB.
100: 2 dB.
101: 2.5 dB.
110: 3 dB.
111: 3.5 dB.
1000: 4 dB.
1001: 4.5 dB.
1010: 5 dB.
1011: 5.5 dB.
1100: 6 dB.
1101: 6.5 dB.
1110: 7 dB.
1111: 7.5 dB.
10000: 8 dB.
10001: 8.5 dB.
10010: 9 dB.
10011: 9.5 dB.
10100: 10 dB.
10101: 10.5 dB.
10110: 11 dB.
10111: 11.5 dB.
ADL6317 Data Sheet
Rev. B | Page 30 of 38
Bits Bit Name Description Reset Access
11000: 12 dB.
11001: 12.5 dB.
11010: 13 dB.
11011: 13.5 dB.
11100: 14 dB.
11101: 14.5 dB.
11110: 15 dB.
11111: 15.5 dB.
Address: 0x103, Reset: 0x00, Name: SIG_PATH3_0
VVA Att enuation DAC Setting
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] VVA_ATT EN[7:0] (R/W)
Table 36. Bit Descriptions for SIG_PATH3_0
Bits Bit Name Description Reset Access
[7:0] VVA_ATTEN[7:0] VVA Attenuation DAC Setting 0x0 R/W
Address: 0x104, Reset: 0x00, Name: SIG_PATH4_0
VVA Att enuation DAC Setting
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] RESERVED [3:0] V VA _ATTEN[11:8] (R/ W)
Table 37. Bit Descriptions for SIG_PATH4_0
Bits Bit Name Description Reset Access
[7:4] RESERVED Reserved 0x0 R
[3:0] VVA_ATTEN[11:8] VVA Attenuation DAC Setting 0x0 R/W
Address: 0x105, Reset: 0x00, Name: SIG_PATH5_0
VVA Voltage Source
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:2] RESERVED [1:0] VV A_SR C (R/W )
Table 38. Bit Descriptions for SIG_PATH5_0
Bits Bit Name Description Reset Access
[7:2] RESERVED Reserved 0x0 R
[1:0] VVA_SRC VVA Voltage Source 0x0 R/W
00: DAC to VVA
10: Pin 30 to VVA
Data Sheet ADL6317
Rev. B | Page 31 of 38
Address: 0x106, Reset: 0x00, Name: SIG_PATH6_0
Set Bi as Gener ator to Use Resistor
Reference
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:1] RESERVED [0] EN_IBIASGEN_RESISTOR (R/W)
Table 39. Bit Descriptions for SIG_PATH6_0
Bits Bit Name Description Reset Access
[7:1] RESERVED Reserved 0x0 R
0 EN_IBIASGEN_RESISTOR Set Bias Generator to Use Resistor Reference 0x0 R/W
0: Disable IBIAS
1: Enable IBIAS
Address: 0x107, Reset: 0x00, Name: SIG_PATH7_0
Bypass Fused Value of TRM_AMP1_IREF_0 Am p lifier 1 I
REF
Trim 0
Am p lifier 1 I
REF
Trim Selec t 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AM P1_IREF_0 (R/W) [3:0] TRM_AMP1_IREF_0 (R/W)
[6:5] RESERVED [4] TRM_AMP 1_IREF_SEL_0 (R/W)
Table 40. Bit Descriptions for SIG_PATH7_0
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP1_IREF_0 Bypass Fused Value of TRM_AMP1_IREF_0 0x0 R/W
[6:5] RESERVED Reserved 0x0 R
4 TRM_AMP1_IREF_SEL_0 Amplifier 1 IREF Trim Select 0 0x0 R/W
[3:0] TRM_AMP1_IREF_0 Amplifier 1 IREF Trim 0 0x0 R/W
Address: 0x108, Reset: 0x00, Name: SIG_PATH8_0
Bypass Fused Value of AMP1_EN_0
Int ernal T rim Data Enable Amplifier 1 (TXEN=0)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AMP1_EN _0 (R/W) [ 0] AMP1_EN_0 (R/W)
[6:1] RESERVED
Table 41. Bit Descriptions for SIG_PATH8_0
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP1_EN_0 Bypass Fused Value of AMP1_EN_0 Internal Trim Data 0x0 R/W
[6:1] RESERVED Reserved 0x0 R
0 AMP1_EN_0 Enable Amplifier 1 (TXEN = 0) 0x0 R/W
ADL6317 Data Sheet
Rev. B | Page 32 of 38
Address: 0x109, Reset: 0x00, Name: SIG_PATH9_0
Bypass Fused Value of TRM_AMP2_IREF_0 Am p lifier 2 I
REF
Trim 0
Am p lifier 2 I
REF
Trim Selec t 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AM P2_IREF_0 (R/W) [3:0] TRM_AMP2_IREF_0 (R/W)
[6:5] RESERVED [4] TRM_AMP 2_IREF_SEL_0 (R/W)
Table 42. Bit Descriptions for SIG_PATH9_0
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP2_IREF_0 Bypass Fused Value of TRM_AMP2_IREF_0 0x0 R/W
[6:5] RESERVED Reserved 0x0 R
4 TRM_AMP2_IREF_SEL_0 Amplifier 2 IREF Trim Select 0 0x0 R/W
[3:0] TRM_AMP2_IREF_0 Amplifier 2 IREF Trim 0 0x0 R/W
Address: 0x10A, Reset: 0x00, Name: SIG_PATHA_0
Bypass Fused Value of AMP2_EN_0
Int ernal T rim Data Enable Ampli fier 2 (TXEN=0)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AMP2_EN _0 (R /W) [ 0] A M P2_EN_0 (R/W)
[6:1] RESERVED
Table 43. Bit Descriptions for SIG_PATHA_0
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP2_EN_0 Bypass Fused Value of AMP2_EN_0 Internal Trim Data 0x0 R/W
[6:1] RESERVED Reserved 0x0 R
0 AMP2_EN_0 Enable Amplifier 2 (TXEN = 0) 0x0 R/W
Address: 0x10B, Reset: 0x00, Name: SIG_PATHB_0
Spare Register 0x10B Amplifier 2 Common B ase Trim
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:2] S PA RE_10B (R/ W) [1:0] TRM_AMP2_CB (R/W)
Table 44. Bit Descriptions for SIG_PATHB_0
Bits Bit Name Description Reset Access
[7:2] SPARE_10B Spare Register 0x10B 0x0 R/W
[1:0] TRM_AMP2_CB Amplifier 2 Common Base Trim 0x0 R/W
Data Sheet ADL6317
Rev. B | Page 33 of 38
Address: 0x112, Reset: 0x20, Name: SIG_PATH2_1
DSA At tenuator Sett i ng 1
0
0
1
0
2
0
3
0
4
0
5
1
6
0
7
0
[7:5] RESERVED [4:0] DSA_ATTEN_1 (R/W)
Table 45. Bit Descriptions for SIG_PATH2_1
Bits Bit Name Description Reset Access
[7:5] RESERVED Reserved. 0x1 R
[4:0] DSA_ATTEN_1 DSA Attenuator Setting 1. 0x0 R/W
0: 0 dB.
1: 0.5 dB.
10: 1 dB.
11: 1.5 dB.
100: 2 dB.
101: 2.5 dB.
110: 3 dB.
111: 3.5 dB.
1000: 4 dB.
1001: 4.5 dB.
1010: 5 dB.
1011: 5.5 dB.
1100: 6 dB.
1101: 6.5 dB.
1110: 7 dB.
1111: 7.5 dB.
10000: 8 dB.
10001: 8.5 dB.
10010: 9 dB.
10011: 9.5 dB.
10100: 10 dB.
10101: 10.5 dB.
10110: 11 dB.
10111: 11.5 dB.
11000: 12 dB.
11001: 12.5 dB.
11010: 13 dB.
11011: 13.5 dB.
11100: 14 dB.
11101: 14.5 dB.
11110: 15 dB.
11111: 15.5 dB.
ADL6317 Data Sheet
Rev. B | Page 34 of 38
Address: 0x117, Reset: 0x00, Name: SIG_PATH7_1
Bypass Fused Value of TRM_AMP1_IREF_1 Am p lifier 1 I
REF
Trim 1
Am p lifier 1 I
REF
Trim Selec t 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AM P1_IREF_1 (R/W) [3:0] TRM_AMP1_IREF_1 (R/W)
[6:5] RESERVED [4] TRM_AMP 1_IREF_SEL_1 (R/W)
Table 46. Bit Descriptions for SIG_PATH7_1
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP1_IREF_1 Bypass Fused Value of TRM_AMP1_IREF_1 0x0 R/W
[6:5] RESERVED Reserved 0x0 R
4 TRM_AMP1_IREF_SEL_1 Amplifier 1 IREF Trim Select 1 0x0 R/W
[3:0] TRM_AMP1_IREF_1 Amplifier 1 IREF Trim 1 0x0 R/W
Address: 0x118, Reset: 0x00, Name: SIG_PATH8_1
Bypass Fused Value of AMP1_EN_1
Int ernal T rim Data Enable Ampli fier 1 (TXEN=1)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AMP1_EN _1 (R /W) [ 0] A M P1_EN_1 (R/W)
[6:1] RESERVED
Table 47. Bit Descriptions for SIG_PATH8_1
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP1_EN_1 Bypass Fused Value of AMP1_EN_1 Internal Trim Data 0x0 R/W
[6:1] RESERVED Reserved 0x0 R
0 AMP1_EN_1 Enable Amplifier 1 (TXEN = 1) 0x0 R/W
Address: 0x119, Reset: 0x00, Name: SIG_PATH9_1
Bypass Fused Value of TRM_AMP2_IREF_1 Amp lifier 2 IREF Trim 1
Am p lifier 2 IREF Trim Selec t 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AM P2_IREF_1 (R/W) [3:0] TRM_AMP2_IREF_1 (R/W)
[6:5] RESERVED [4] TRM_AMP2_IREF_SEL_1 (R/W)
Table 48. Bit Descriptions for SIG_PATH9_1
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP2_IREF_1 Bypass Fused Value of TRM_AMP2_IREF_1 0x0 R/W
[6:5] RESERVED Reserved 0x0 R
4 TRM_AMP2_IREF_SEL_1 Amplifier 2 IREF Trim Select 1 0x0 R/W
[3:0] TRM_AMP2_IREF_1 Amplifier 2 IREF Trim 1 0x0 R/W
Address: 0x11A, Reset: 0x00, Name: SIG_PATHA_1
Bypass Fused Value of AMP2_EN_1
Int ernal T rim Data Enable Ampli fier 2 (TXEN=1)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] BYPASS_TRM_AMP2_EN _1 (R /W) [ 0] A M P2_EN_1 (R/W)
[6:1] RESERVED
Table 49. Bit Descriptions for SIG_PATHA_1
Bits Bit Name Description Reset Access
7 BYPASS_TRM_AMP2_EN_1 Bypass Fused Value of AMP2_EN_1 Internal Trim Data 0x0 R/W
[6:1] RESERVED Reserved 0x0 R
0 AMP2_EN_1 Enable Amplifier 2 (TXEN = 1) 0x0 R/W
Data Sheet ADL6317
Rev. B | Page 35 of 38
Address: 0x11B, Reset: 0x00, Name: SIG_PATHB_1
Spare Register 0x11B Amp lifie r 2 IP3 Tr im
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:2] SPARE_11B (R/W) [1:0] TRM_AMP2_IP3 (R/W)
Table 50. Bit Descriptions for SIG_PATHB_1
Bits Bit Name Description Reset Access
[7:2] SPARE_11B Spare Register 0x11B 0x0 R/W
[1:0] TRM_AMP2_IP3 Amplifier 2 IP3 Trim 0x0 R/W
00: Trim Mode 0
01: Trim Mode 1
10: Trim Mode 2
11: Trim Mode 3
Address: 0x120, Reset: 0x20, Name: AMUX_SEL
Select Mux Output
ADC Input, VVA_CTRL, ADC Clock Selection
on MUX ADC Input Selection
0
0
1
0
2
0
3
0
4
0
5
1
6
0
7
0
[7] RESERVED [2:0] AMUX_1_SEL (R/W)
[6:4] AMUX_3_SEL (R/W) [3] AMUX_2_SEL (R/W)
Table 51. Bit Descriptions for AMUX_SEL
Bits Bit Name Description Reset Access
7 RESERVED Reserved. 0x0 R/W
[6:4] AMUX_3_SEL ADC Input, VVA_CTRL, ADC Clock Selection on Mux. 0x2 R/W
000: VVA_CTRL.
001: ADC input.
010: ADC clock.
011 to 111: Not used.
3 AMUX_2_SEL ADC Input Selection. 0x0 R/W
0: PTAT to ADC input.
1: VVA_CTRL to ADC input.
[2:0] AMUX_1_SEL Select Mux Output. 0x0 R/W
000: PTAT.
001: Output of AMUX_3_SEL.
010: 1.8 V LDO output.
011: 3.3 V LDO output.
100: GND.
101: GND.
110: Not used.
111: Not used.
Address: 0x121, Reset: 0x00, Name: MULTI_FUNC_CTRL_0111
Auxiliary Mux External
SPI Supply Control
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [3:0 ] AMU X _ EX (R/W)
[4] SPI_1P8_3P3_CTRL (R/W)
Table 52. Bit Descriptions for MULTI_FUNC_CTRL_0111
Bits Bit Name Description Reset Access
[7:5] RESERVED Reserved 0x0 R
4 SPI_1P8_3P3_CTRL SPI Supply Control 0x0 R/W
0: 1.8 V readback
1: 3.3 V readback
[3:0] AMUX_EX Auxiliary Mux External 0x0 R/W
ADL6317 Data Sheet
Rev. B | Page 36 of 38
Address: 0x127, Reset: 0x00, Name: ADC_CONTROL
ADC Clock Frequency Division Ratio. Divided
Down Gated Clock
ADC Clock Divider Enable
ADC Clock Source Selection
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [2:0] ADC_CLK_FREQ (R/W)
[5] ADC_CLOCK_DIV_EN (R/W)
[3] RESERVED
[4] ADC_MUX_SEL (R/W)
Table 53. Bit Descriptions for ADC_CONTROL
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
5 ADC_CLOCK_DIV_EN ADC Clock Divider Enable. 0x0 R/W
0: Disable ADC clock divider.
1: Enable ADC clock divider.
4 ADC_MUX_SEL ADC Clock Source Selection. 0x0 R/W
0: ADC clock from SCLK.
1: Not used.
3 RESERVED Reserved. 0x0 R
[2:0] ADC_CLK_FREQ ADC Clock Frequency Division Ratio. Divided Down Gated Clock. 0x0 R/W
000: ADC clock at SCLK/2.
001: ADC clock at SCLK/1.
010: ADC clock at SCLK/2.
011: ADC clock at SCLK/4.
Address: 0x128, Reset: 0x00, Name: ADC_EOC
ADC End of Conversion (EOC)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:1] RESERVED [0] ADC_EOC (R)
Table 54. Bit Descriptions for ADC_EOC
Bits Bit Name Description Reset Access
[7:1] RESERVED Reserved 0x0 R
0 ADC_EOC ADC End of Conversion (EOC) 0x0 R
Address: 0x129, Reset: 0x00, Name: ADC_OUT
Temperature Sensor Output of Auxiliary MUX
ADC
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] TEMP_ADC_OUT (R)
Table 55. Bit Descriptions for ADC_OUT
Bits Bit Name Description Reset Access
[7:0] TEMP_ADC_OUT Temperature Sensor Output of Auxiliary Mux ADC 0x0 R
Address: 0x146, Reset: 0x00, Name: GENERIC_READBACK_2
VVA Att enuation Sett i ng Readbac k
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] VVA_ATTEN_RDBK[7: 0] (R)
Table 56. Bit Descriptions for GENERIC_READBACK_2
Bits Bit Name Description Reset Access
[7:0] VVA_ATTEN_RDBK[7:0] VVA Attenuation Setting Readback 0x0 R
Data Sheet ADL6317
Rev. B | Page 37 of 38
Address: 0x147, Reset: 0x00, Name: GENERIC_READBACK_3
VVA Att enuation Sett i ng Readbac k
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] RESERVED [3:0] VVA_ATTEN_RDBK[11: 8] (R)
Table 57. Bit Descriptions for GENERIC_READBACK_3
Bits Bit Name Description Reset Access
[7:4] RESERVED Reserved 0x0 R
[3:0] VVA_ATTEN_RDBK[11:8] VVA Attenuation Setting Readback 0x0 R
Address: 0x148, Reset: 0x00, Name: GENERIC_READBACK_4
DSA At tenuator Readback
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] DSA_ATTEN_RDBK (R)
Table 58. Bit Descriptions for GENERIC_READBACK_4
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved 0x0 R
[5:0] DSA_ATTEN_RDBK DSA Attenuator Readback 0x0 R
ADL6317 Data Sheet
Rev. B | Page 38 of 38
OUTLINE DIMENSIONS
10-11-2018-A
PKG-006045
10.60
10.50
10.40
5.60
5.50
5.40
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
6
7
19
20
25
26 38
0.70
BSC 0.20
BSC
0.70
BSC
3.50 REF
0.10
REF
8.40 REF
0.530 REF
3.50 BSC
0.45
0.40
0.35
0.50
0.45
0.40
0.498
0.448
0.398
1.08
0.98
0.88
PIN 1
CORNERAREA
SEATING
PLANE
8.50 BSC
4.15BSC
PIN 1
INDICATOR
C0.30 ×0.45°
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PADS, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 50. 38-Terminal Land Grid Array [LGA]
(CC-38-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range2 Package Description Package Option
ADL6317ACCZ −40°C to +105°C 38-Terminal Land Grid Array [LGA] CC-38-1
ADL6317ACCZ-R7 −40°C to +105°C 38-Terminal Land Grid Array [LGA] CC-38-1
ADL6317-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part
2 Measured at the exposed pad.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20829-5/20(B)
