1
LTC4211
4211fa
APPLICATIO S
U
DESCRIPTIO
U
TYPICAL APPLICATIO
U
FEATURES
■
Allows Safe Board Insertion and Removal
from a Live Backplane
■
Controls Supply Voltages from 2.5V to 16.5V
■
Programmable Soft-Start with Inrush Current
Limiting, No External Gate Capacitor Required
■
Faster Turn-Off Time Because No External Gate
Capacitor is Required
■
Dual Level Overcurrent Fault Protection
■
Programmable Response Time for Overcurrent
Protection (MS)
■
Programmable Overvoltage Protection (MS)
■
Automatic Retry or Latched Mode Operation (MS)
■
High Side Drive for an External N-Channel FET
■
User-Programmable Supply Voltage Power-Up Rate
■
FB Pin Monitors V
OUT
and Signals RESET
■
Glitch Filter Protects Against Spurious RESET Signal
The LTC
®
4211 is a Hot Swap
TM
controller that allows a
board to be safely inserted and removed from a live
backplane. An internal high side switch driver controls the
gate of an external N-channel MOSFET for supply voltages
ranging from 2.5V to 16.5V. The LTC4211 provides soft-
start and inrush current limiting during the start-up period
which has a programmable duration.
Two on-chip current limit comparators provide dual level
overcurrent circuit breaker protection. The slow com-
parator trips at VCC – 50mV and activates in 20µs (or
programmed by an external filter capacitor, MS only). The
fast comparator trips at VCC – 150mV and typically
responds in 300ns.
The FB pin monitors the output supply voltage and signals
the RESET output pin. The ON pin signal turns the chip on
and off and can also be used for the reset function. The
MS package has FAULT and FILTER pins to provide
additional functions like fault indication, autoretry or
latch-off modes, programmable current limit response
time and programmable overvoltage protection using an
external Zener diode clamp.
■
Electronic Circuit Breaker
■
Hot Board Insertion and Removal (Either On
Backplane or On Removable Card)
■
Industrial High Side Switch/Circuit Breaker
Hot Swap Controller with
Multifunction Current Control
Single Channel 5V Hot Swap Controller
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
5V
5A
GND
4211 TA01A
5
1
R4
15k
GATE
GNDTIMER
PCB CONNECTION SENSE CTIMER
10nF
FB
ON
SHORT
LONG
VCC
5V
GND LONG
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
RESET
R2
10k
R1
20k
RX
10Ω
RSENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1*
R3
36k
R5
10k
µP
LOGIC
RESET
CX
100nF
BACKPLANE
CONNECTOR
(FEMALE)
4211 TA01b
2.5ms/DIV
NO C
LOAD
V
GATE
5V/DIV
V
RESET
5V/DIV
V
ON
1V/DIV
V
TIMER
1V/DIV
Power-Up Sequence
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
2
LTC4211
4211fa
ORDER PART
NUMBER
LTC4211CS8
LTC4211IS8
S8 PART
MARKING
4211
4211I
ORDER PART
NUMBER
LTC4211CMS8
LTC4211IMS8
MS8 PART
MARKING
LTSC
LTSD
ORDER PART
NUMBER
LTC4211CMS
LTC4211IMS
MS PART
MARKING
LTSU
LTSV
T
JMAX
= 125°C, θ
JA
= 150°C/ W
Supply Voltage (V
CC
) ............................................... 17V
Input Voltage
FB, ON .................................................. –0.3V to 17V
SENSE, FILTER .......................... –0.3V to V
CC
+ 0.3V
TIMER .....................................................–0.3V to 2V
Output Voltage
GATE ............................... Internally Limited (Note 3)
RESET, FAULT ...................................... –0.3V to 17V
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
(Note 1)
Operating Temperature Range
LTC4211C .............................................. 0°C to 70°C
LTC4211I........................................... – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
SENSE
GATE
FB
RESET
ON
TIMER
GND
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C, θ
JA
= 200°C/ W
1
2
3
4
RESET
ON
TIMER
GND
8
7
6
5
VCC
SENSE
GATE
FB
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C, θ
JA
= 200°C/ W
1
2
3
4
5
RESET
ON
FILTER
TIMER
GND
10
9
8
7
6
FAULT
V
CC
SENSE
GATE
FB
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
V
CC
Supply Voltage Range ●2.5 16.5 V
I
CC
V
CC
Supply Current FB = High, ON = High, TIMER = Low ●1 1.5 mA
V
LKO
Internal V
CC
Undervoltage Lockout V
CC
Low-to-High Transition ●2.13 2.3 2.47 V
V
LKOHST
V
CC
Undervoltage Lockout Hysteresis 120 mV
I
INFB
FB Input Current V
FB
= V
CC
or GND ±1±10 µA
I
INON
ON Input Current V
ON
= V
CC
or GND ±1±10 µA
I
LEAK
RESET, FAULT Leakage Current V
RESET
= V
FAULT
= 15V, Pull-Down Device Off ●±0.1 ±2.5 µA
I
INSENSE
SENSE Input Current V
SENSE
= V
CC
or GND ±1±10 µA
V
CB(FAST)
SENSE Trip Voltage (V
CC
– V
SENSE
) Fast Comparator Trips ●130 150 170 mV
V
CB(SLOW)
SENSE Trip Voltage (V
CC
– V
SENSE
) Slow Comparator Trips ●40 50 60 mV
I
GATEUP
GATE Pull-Up Current Charge Pump On, V
GATE
≤ 0.2V ●–12.5 – 10 –7.5 µA
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC4211
4211fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
GATEDOWN
Normal GATE Pull-Down Current ON Low ●130 200 270 µA
Fast GATE Pull-Down Current FAULT Latched and Circuit Breaker 50 mA
Tripped or in UVLO
∆V
GATE
External N-Channel Gate Drive V
GATE
– V
CC
(For V
CC
= 2.5V) ●2.5 8 V
V
GATE
– V
CC
(For V
CC
= 2.7V) ●4.5 8 V
V
GATE
– V
CC
(For V
CC
= 3.3V) ●5.0 10 V
V
GATE
– V
CC
(For V
CC
= 5V) ●10 16 V
V
GATE
– V
CC
(For V
CC
= 12V) ●10 18 V
V
GATE
– V
CC
(For V
CC
= 15V) ●818V
V
GATEOV
GATE Overvoltage Lockout Threshold ●0.08 0.2 0.3 V
V
FB
FB Voltage Threshold FB High to Low ●1.223 1.236 1.248 V
∆V
FB
FB Threshold Line Regulation 2.5V ≤ V
CC
≤ 16.5V ●0.5 5 mV
V
FBHST
FB Voltage Threshold Hysteresis 3mV
V
ONHI
ON Threshold High ●1.23 1.316 1.39 V
V
ONLO
ON Threshold Low ●1.20 1.236 1.26 V
V
ONHST
ON Hysteresis 80 mV
I
FILTER
FILTER Current During Slow Fault Condition ●–2.5 –2 –1.5 µA
During Normal and Reset Conditions ●71013 µA
V
FILTER
FILTER Threshold Latched Off Threshold, FILTER Low to High ●1.20 1.236 1.26 V
V
FILTERHST
FILTER Threshold Hysteresis 80 mV
I
TMR
TIMER Current Timer On, V
TIMER
= 1V ●– 2.5 – 2 –1.5 µA
Timer Off, TIMER = 1.5V 3 mA
V
TMR
TIMER Threshold TIMER Low to High ●1.20 1.236 1.26 V
TIMER High to Low ●0.15 0.200 0.40 V
V
FAULT
FAULT Threshold Latched Off Threshold, FAULT High to Low ●1.20 1.236 1.26 V
V
FAULTHST
FAULT Threshold Hysteresis 50 mV
V
OLFAULT
Output Low Voltage I
FAULT
= 1.6mA ●0.14 0.4 V
V
OLRESET
Output Low Voltage I
RESET
= 1.6mA ●0.14 0.4 V
t
FAULTFC
FAST COMP Trip to GATE Discharging V
CB
= 0mV to 200mV Step ●300 700 ns
t
FAULTSC
SLOW COMP Trip to GATE Discharging V
CB
= 0mV to 100mV Step, ●10 20 30 µs
8-Pin Version or FILTER Floating
V
CB
= 0mV to 100mV Step, ●468 ms
10nF at FILTER Pin to GND
t
EXTFAULT
FAULT Low to GATE Discharging V
FAULT
= 5V to 0V ●135 µs
t
FILTER
FILTER High to FAULT Latched V
FILTER
= 0V to 5V ●2 4.5 7 µs
t
RESET
Circuit Breaker Reset Delay Time ON Low to FAULT High ●150 250 µs
t
OFF
Turn-Off Time ON Low to GATE Off 8 µs
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All current into device pins are positive; all current out of device
pins are negative; all voltages are referenced to ground unless otherwise
specified.
Note 3: An internal Zener at the GATE pin clamps the charge pump voltage
to a typical maximum operating voltage of 26V. External voltage applied to
the GATE pin beyond the internal Zener voltage may damage the part. If a
lower GATE pin voltage is desired, use an external Zener diode. The GATE
capacitance must be <0.15µF at maximum V
CC
.
4
LTC4211
4211fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Supply Current vs Supply Voltage Supply Current vs Temperature
Undervoltage Lockout Threshold
vs Temperature
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
16
4211 G01
4 8 12 20142 6 10 18
T
A
= 25°C
TEMPERATURE (°C)
–75
SUPPLY CURRENT (mA)
2.0
2.5
3.0
125
4211 G02
1.5
1.0
0–25 25 75
–50 150
050 100
0.5
4.0
3.5
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V
V
CC
= 3V
TEMPERATURE (°C)
–75
2.0
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.1
2.3
2.4
2.5
–25 25 50 150
4211 G03
2.2
–50 0 75 100 125
FALLING EDGE
RISING EDGE
ON Pin Threshold
vs Supply Voltage
ON Pin Threshold
vs Temperature GATE Voltage vs Supply Voltage
SUPPLY VOLTAGE (V)
1.10
ON PIN THRESHOLD (V)
1.20
1.30
1.40
1.15
1.25
1.35
4 8 12 16
4211 G04
2020 6 10 14 18
TA = 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
1.10
ON PIN THRESHOLD (V)
1.15
1.25
1.30
1.35
–25 25 50 150
4211 G05
1.20
–50 0 75 100 125
1.40 V
CC
= 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
0
GATE VOLTAGE (V)
10
20
30
5
15
25
4 8 12 16
4211 G06
2020 6 10 14 18
T
A
= 25°C
GATE Voltage vs Temperature VGATE – VCC vs Supply Voltage VGATE – VCC vs Temperature
TEMPERATURE (°C)
–75
0
GATE VOLTAGE (V)
5
15
20
25
–25 25 50 150
4211 G07
10
–50 0 75 100 125
30
VCC = 15V
VCC = 12V
VCC = 5V
VCC = 3V
SUPPLY VOLTAGE (V)
0
0
VGATE – VCC (V)
2
6
8
10
12 14 16 18
18
4211 G08
4
2 4 6 8 10 20
12
14
16
TA = 25°C
TEMPERATURE (°C)
–75
0
V
GATE
– V
CC
(V)
2
6
8
10
75
18
4211 G09
4
0 150
25
–50 100
50
–25 125
12
14
16
V
CC
= 12V
V
CC
= 15V V
CC
= 5V
V
CC
= 3V
5
LTC4211
4211fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
GATE Output Source Current
vs Supply Voltage
Normal GATE Pull-Down Current
vs Supply Voltage
Normal GATE Pull-Down Current
vs Temperature
Fast GATE Pull-Down Current
vs Supply Voltage
Feedback Threshold
vs Supply Voltage
Feedback Threshold
vs Temperature
FILTER Threshold
vs Supply Voltage
GATE Output Source Current
vs Temperature
SUPPLY VOLTAGE (V)
7
GATE OUTPUT SOURCE CURRENT (µA)
9
11
13
8
10
12
4 8 12 16
4211 G10
2020 6 10 14 18
T
A
= 25°C
TEMPERATURE (°C)
–75
7
GATE OUTPUT SOURCE CURRENT (µA)
8
10
11
12
–25 25 50 150
4211 G11
9
–50 0 75 100 125
13
V
CC
= 15V
V
CC
= 3V
V
CC
= 5V
V
CC
= 12V
SUPPLY VOLTAGE (V)
140
NORMAL GATE PULL-DOWN CURRENT (µA)
180
220
260
160
200
240
4 8 12 16
4211 G12
2020 6 10 14 18
T
A
= 25°C
TEMPERATURE (°C)
–75
140
NORMAL GATE PULL-DOWN CURRENT (µA)
160
200
220
240
–25 25 50 150
4211 G13
180
–50 0 75 100 125
260 V
CC
= 5V
SUPPLY VOLTAGE (V)
20
FAST GATE PULL-DOWN CURRENT (mA)
40
60
80
30
50
70
4 8 12 16
4211 G14
2020 6 10 14 18
T
A
= 25°C
Fast GATE Pull-Down Current
vs Temperature
TEMPERATURE (°C)
–75
20
FAST GATE PULL-DOWN CURRENT (mA)
30
50
60
70
–25 25 50 150
4211 G15
40
–50 0 75 100 125
80 V
CC
= 5V
SUPPLY VOLTAGE (V)
0
FEEDBACK THRESHOLD (V)
1.240
1.245
1.250
16
4211 G16
1.235
1.230
1.225 481221861014 20
T
A
= 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
1.225
FEEDBACK THRESHOLD (V)
1.230
1.240
1.245
1.250
–25 25 50 150
4211 G17
1.235
–50 0 75 100 125
V
CC
= 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
1.10
FILTER THRESHOLD (V)
1.20
1.30
1.40
1.15
1.25
1.35
4 8 12 16
4211 G18
2020 6 10 14 18
T
A
= 25°C
HIGH THRESHOLD
LOW THRESHOLD
6
LTC4211
4211fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FILTER Threshold vs Temperature
FILTER Pull-Up Current
vs Temperature
FILTER Pull-Down Current
vs Supply Voltage
FILTER Pull-Down Current
vs Temperature
TIMER High Threshold
vs Temperature
TIMER Low Threshold
vs Supply Voltage
TIMER Low Threshold
vs Temperature
FILTER Pull-Up Current
vs Supply Voltage
TIMER High Threshold
vs Supply Voltage
TEMPERATURE (°C)
–75
1.10
FILTER THRESHOLD (V)
1.15
1.25
1.30
1.35
–25 25 50 150
4211 G19
1.20
–50 0 75 100 125
1.40 V
CC
= 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
1.7
FILTER PULL-UP CURRENT (µA)
1.9
2.1
2.3
1.8
2.0
2.2
4 8 12 16
4211 G20
2020 6 10 14 18
T
A
= 25°C
TEMPERATURE (°C)
–75
1.7
FILTER PULL-UP CURRENT (µA)
1.8
2.0
2.1
2.2
–25 25 50 150
4211 G21
1.9
–50 0 75 100 125
2.3 VCC = 5V
SUPPLY VOLTAGE (V)
0
FILTER PULL-DOWN CURRENT (µA)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
16
4211 G22
4 8 12 20142 6 10 18
T
A
= 25°C
TEMPERATURE (°C)
–75
FILTER PULL-DOWN CURRENT (µA)
10.0
10.5
11.0
125
4211 G23
9.5
9.0
8.0 –25 25 75
–50 150
050 100
8.5
12.0
11.5
V
CC
= 5V
SUPPLY VOLTAGE (V)
1.20
TIMER HIGH THRESHOLD (V)
1.22
1.24
1.26
1.21
1.23
1.25
4 8 12 16
4211 G24
2020 6 10 14 18
T
A
= 25°C
TEMPERATURE (°C)
–75
1.20
TIMER HIGH THRESHOLD (V)
1.21
1.23
1.24
1.25
–25 25 50 150
4211 G25
1.22
–50 0 75 100 125
1.26 V
CC
= 5V
SUPPLY VOLTAGE (V)
0
TIMER LOW THRESHOLD (V)
0.6
0.8
1.0
16
4211 G26
0.4
0.2
04812
218
610 14 20
T
A
= 25°C
TEMPERATURE (°C)
–75
0
TIMER LOW THRESHOLD (V)
0.2
0.6
0.8
1.0
–25 25 50 150
4211 G27
0.4
–50 0 75 100 125
V
CC
= 5V
7
LTC4211
4211fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TIMER Pull-Up Current
vs Supply Voltage
TIMER Pull-Down Current
vs Supply Voltage
TIMER Pull-Down Current
vs Temperature VOL vs Supply Voltage
VCB (SLOW COMP)
vs Supply Voltage
VCB (SLOW COMP)
vs Temperature
VCB (FAST COMP)
vs Supply Voltage
TIMER Pull-Up Current
vs Temperature
VOL vs Temperature
SUPPLY VOLTAGE (V)
1.70
TIMER PULL-UP CURRENT (µA)
1.90
2.10
2.30
1.80
2.00
2.20
4 8 12 16
4211 G28
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
1.7
TIMER PULL-UP CURRENT (µA)
1.8
2.0
2.1
2.2
–25 25 50 150
4211 G29
1.9
–50 0 75 100 125
2.3 V
CC
= 5V
SUPPLY VOLTAGE (V)
0
TIMER PULL-DOWN CURRENT (mA)
2
4
6
1
3
5
4 8 12 16
4211 G30
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
0
TIMER PULL-DOWN CURRENT (mA)
1
3
4
5
–25 25 50 150
4211 G31
2
–50 0 75 100 125
6VCC = 5V
SUPPLY VOLTAGE (V)
0
V
OL
(V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
16
4211 G32
4 8 12 20142 6 10 18
T
A
= 25°C
RESET OR FAULT
I
OL
= 5mA
I
OL
= 1mA
TEMPERATURE (°C)
–75
V
OL
(V)
0.8
1.0
1.2
125
4211 G33
0.6
0.4
0–25 25 75
–50 150
050 100
0.2
1.6
1.4
V
CC
= 5V
RESET OR FAULT
I
OL
= 5mA
I
OL
= 1mA
SUPPLY VOLTAGE (V)
0
V
CB
(SLOW COMP) (mV)
52
56
60
16
4211 G34
48
44
50
54
58
46
42
40 42 86 12 14 18
10 20
T
A
= 25°C
TEMPERATURE (°C)
–75
40
VCB (SLOW COMP) (mV)
42
46
48
50
60
54
–25 25 50 150
4211 G35
44
56
58
52
–50 0 75 100 125
VCC = 5V
SUPPLY VOLTAGE (V)
0
V
CB
(FAST COMP) (mV)
170
165
160
155
150
145
140
135
130
16
4211 G36
4 8 12 20142 6 10 18
T
A
= 25°C
8
LTC4211
4211fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCB (FAST COMP)
vs Temperature
SLOW COMP Response Time vs
Temperature
TEMPERATURE (°C)
–75
V
CB
(FAST COMP) (mV)
150
155
160
125
4211 G37
145
140
130 –25 25 75
–50 150
050 100
135
170
165
V
CC
= 5V
SUPPLY VOLTAGE (V)
0
SLOW COMP RESPONSE TIME (µs)
26
24
22
20
18
16
14
12
10
16
4211 G38
4 8 12 20142 6 10 18
T
A
= 25°C
8-PIN VERSION
OR FILTER FLOATING
TEMPERATURE (°C)
–75
SLOW COMP RESPONSE TIME (µs)
18
20
22
125
4211 G39
16
14
10 –25 25 75
–50 150
050 100
12
26
24
8-PIN VERSION OR FILTER FLOATING
V
CC
= 15V
V
CC
= 3V
V
CC
= 12V
V
CC
= 5V
FAST COMP Response Time vs
Supply Voltage
SLOW COMP Response Time vs
Supply Voltage
FAST COMP Response Time vs
Temperature
FILTER High to FAULT Activation
Time vs Supply Voltage
FILTER High to FAULT Activation
Time vs Temperature
Circuit Breaker RESET Time
vs Supply Voltage
Circuit Breaker RESET Time
vs Temperature
SUPPLY VOLTAGE (V)
0
FAST COMP RESPONSE TIME (ns)
800
700
600
500
400
300
200
100
0
16
4211 G40
4 8 12 20142 6 10 18
T
A
= 25°C
V
CB
= 0mV TO 200mV STEP
TEMPERATURE (°C)
–75
FAST COMP RESPONSE TIME (ns)
400
500
600
125
4211 G41
300
200
0–25 25 75
–50 150
050 100
100
800
700
V
CB
= 0mV TO 200mV STEP
V
CC
= 15V
V
CC
= 3V
V
CC
= 12V
V
CC
= 5V
SUPPLY VOLTAGE (V)
3.0
FILTER HIGH TO FAULT ACTIVATION TIME (µs)
4.0
5.0
6.0
3.5
4.5
5.5
4 8 12 16
4211 G42
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
3.0
FILTER HIGH TO FAULT ACTIVATION TIME (µs)
3.5
4.5
5.0
5.5
–25 25 50 150
4211 G43
4.0
–50 0 75 100 125
6.0 V
CC
= 5V
SUPPLY VOLTAGE (V)
80
CIRCUIT BREAKER RESET TIME (µs)
120
160
200
100
140
180
4 8 12 16
4211 G44
2020 6 10 14 18
TA = 25°C
TEMPERATURE (°C)
–75
80
CIRCUIT BREAKER RESET TIME (µs)
100
140
160
180
–25 25 50 150
4211 G45
120
–50 0 75 100 125
200 V
CC
= 5V
9
LTC4211
4211fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FAULT Pin Low to GATE Discharging
Time vs Supply Voltage
FAULT Threshold Voltage
vs Supply Voltage
FAULT Threshold Voltage
vs Temperature
FAULT Pin Low to GATE Discharging
Time vs Temperature
Turn Off Time
vs Supply Voltage Turn Off Time vs Temperature
GATE Overvoltage Lockout Threshold
vs Supply Voltage
GATE Overvoltage Lockout Threshold
vs Temperature
SUPPLY VOLTAGE (V)
1.5
FAULT PIN LOW TO GATE DISCHARGING TIME (µs)
2.5
3.5
4.5
2.0
3.0
4.0
4 8 12 16
4211 G46
2020 6 10 14 18
T
A
= 25°C
TEMPERATURE (°C)
–75
1.5
FAULT PIN LOW TO GATE DISCHARGING TIME (µs)
2.0
3.0
3.5
4.0
–25 25 50 150
4211 G47
2.5
–50 0 75 100 125
4.5 VCC = 5V
SUPPLY VOLTAGE (V)
0
FAULT THRESHOLD VOLTAGE (V)
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
16
4211 G48
4 8 12 20142 6 10 18
T
A
= 25°C
HIGH THRESHOLD
LOW THRESHOLD
TEMPERATURE (°C)
–75
FAULT THRESHOLD VOLTAGE (V)
1.30
1.35
1.40
125
4211 G49
1.25
1.20
1.10 –25 25 75
–50 150
050 100
1.15
1.50
1.45
V
CC
= 5V
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
5
TURN OFF TIME (µs)
7
9
11
6
8
10
4 8 12 16
4211 G50
2020 6 10 14 18
T
A
= 25°C
TEMPERATURE (°C)
–75
5
TURN OFF TIME (µs)
6
8
9
10
–25 25 50 150
4211 G51
7
–50 0 75 100 125
11 V
CC
= 5V
SUPPLY VOLTAGE (V)
0
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
0.3
0.4
0.5
16
4211 G52
0.2
0.1
04812
218
610 14 20
T
A
= 25°C
TEMPERATURE (°C)
–75
0
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
0.1
0.3
0.4
0.5
–25 25 50 150
4211 G53
0.2
–50 0 75 100 125
V
CC
= 5V
10
LTC4211
4211fa
UU
U
PI FU CTIO S
RESET (Pin 1/Pin 1): An open-drain N-channel MOSFET
whose source connects to GND (Pin 4/Pin 5). This pin
pulls low if the voltage at the FB pin (Pin 5/Pin 6) falls below
the FB pin threshold (1.236V). During the start-up cycle,
the RESET pin goes high impedance at the end of the
second timing cycle after the FB pin goes above the FB
threshold. This pin requires an external pull-up resistor to
V
CC
. If an undervoltage lockout condition occurs, the
RESET pin pulls low independently of the FB pin to prevent
false glitches.
ON (Pin 2/Pin 2): An active high signal used to enable or
disable LTC4211 operation. COMP1’s threshold is set at
1.236V and its hysteresis is set at 80mV. If a logic high
signal is applied to the ON pin (V
ON
> 1.316V), the first
timing cycle begins if an overvoltage condition does not
exist on the GATE pin (Pin 6/Pin 7). If a logic low signal is
applied to the ON pin (V
ON
< 1.236V), the GATE pin is
pulled low by an internal 200µA current sink. The ON pin
can also be used to reset the electronic circuit breaker. If
the ON pin is cycled low and then high following a circuit
breaker trip, the internal circuit breaker is reset, and the
LTC4211 begins a new start-up cycle.
TIMER (Pin 3/Pin 4): A capacitor connected from this pin
to GND sets the LTC4211’s system timing. The LTC4211’s
initial and second start-up timing cycles and its internal
“power good” delay time are defined by this capacitor.
GND (Pin 4/Pin 5): Device Ground Connection. Connect
this pin to the system’s analog ground plane.
FB (Pin 5/Pin 6): The FB (Feedback) pin is an input to the
COMP2 comparator and monitors the output supply volt-
age through an external resistor divider. If V
FB
< 1.236V,
the RESET pin pulls low. An internal glitch filter at COMP2’s
output helps prevent negative voltage transients from
triggering a reset condition. If V
FB
> 1.239V, the RESET pin
goes high after one timing cycle.
GATE (Pin 6/Pin 7): The output signal at this pin is the
high side gate drive for the external N-channel FET pass
transistor.
(8-Lead Package/10-Lead Package)
As shown in the Block Diagram, an internal charge pump
supplies a 10µA gate current and sufficient gate voltage
drive to the external FET for supply voltages from 2.5V to
16.5V. The internal charge-pump and zener clamps at the
GATE pin determine the gate drive voltage (∆V
GATE
=
V
GATE
– V
CC
). The charge pump produces a minimum 4.5V
of ∆V
GATE
for supplies in the range of 2.7V < V
CC
< 4.75V.
For V
CC
> 4.75V, the ∆V
GATE
is limited by zener clamp Z1
connecting between GATE and V
CC
pins. The ∆V
GATE
is
typically at 12V and with guaranteed minimum value of
10V. For V
CC
> 15V, the zener clamp Z2 sets the limitation
for ∆V
GATE
. Z2 clamps the gate voltage to ground to 26V
typically. The minimum Z2’s clamp voltage is 23V. This
effectively sets ∆V
GATE
to 8V minimum.
SENSE (Pin 7/Pin 8): Circuit Breaker Set Pin. With a sense
resistor placed in the power path between V
CC
and SENSE,
the LTC4211’s electronic circuit breaker trips if the voltage
across the sense resistor exceeds the thresholds set
internally for the SLOW COMP and the FAST COMP, as
shown in the Block Diagram. The threshold for the SLOW
COMP is V
CB(SLOW)
= 50mV, and the electronic circuit
breaker trips if the voltage across the sense resistor
exceeds 50mV for 20µs. The SLOW COMP delay is fixed in
the S8/MS8 version and adjustable in the MS version of
the LTC4211. To adjust the SLOW COMP’s delay, please
refer to the section on Adjusting SLOW COMP’s Response
Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for the FAST COMP is set at
V
CB(FAST)
= 150mV, and the circuit breaker trips if the
voltage across the sense resistor exceeds 150mV for more
than 300ns. The FAST COMP’s delay is fixed in the
LTC4211 and cannot be adjusted. To disable the electronic
circuit breaker, connect the V
CC
and SENSE pins together.
V
CC
(Pin 8/Pin 9): This is the positive supply input to the
LTC4211. The LTC4211 operates from 2.5V < V
CC
< 16.5V,
and the supply current is typically 1mA. An internal und-
ervoltage lockout circuit disables the device until the
voltage at V
CC
exceeds 2.3V.
11
LTC4211
4211fa
UU
U
PI FU CTIO S
(8-Lead Package/10-Lead Package)
FAULT (Not available on S8/MS8, Pin 10 MS): FAULT is
both an input and an output. Connected to this pin are an
analog comparator (COMP6) and an open-drain N-chan-
nel FET. During normal operation, if COMP6 is driven
below 1.236V, the electronic circuit breaker trips and the
GATE pin pulls low. Typically, a 10k pull-up resistor
connects to the FAULT pin. This allows the LTC4211 to
begin a second timing cycle (VFAULT > 1.286) and start-up
properly. This also allows the use of the FAULT pin as a
status output. Under normal operating conditions, the
FAULT output is a logic high. Two conditions cause an
active low on FAULT: (1) the LTC4211’s electronic circuit
breaker trips because of an output short circuit (VOUT =
0V) or because of a fast output overcurrent transient
(FAST COMP trips circuit breaker); or (2) VFILTER >
1.236V. The FAULT output is driven to logic low and is
latched logic low until the ON pin is driven to logic low for
150µs (the tRESET duration).
FILTER (Not available S8/MS8, Pin 3 MS): Overcurrent
Fault Timing Pin and Overvoltage Fault Set pin. With a
capacitor connected from this pin to ground, the SLOW
COMP’s response time can be adjusted. In the S8/MS8
version of the LTC4211, the FILTER pin is not available and
the delay time from overcurrent detect to GATE OFF is fixed
at 20µs.
–
+
V
REF
V
REF
–+
+
–+
–
SLOW
COMP
50mV 150mV
0.2V
COMP7
M3
GLITCH FILTER
(SEE NOTE 1)
UVLO
–+
FAST
COMP
–
+
–
+
300ns
DELAY
GLITCH FILTER
150µs
GLITCH FILTER
FUNCTION OF
OVERDRIVE
BG
V
REF
0.2V
CB
TRIPS
OR UVLO ON LOW
START-UP
CURRENT
REGULATOR
GATE
CHARGING
200µA10µA
POWER BAD
CB TRIPS
V
REF
10µA
6 (7)GATE7 (8)SENSE8 (9)V
CC
M1
CHARGE
PUMP
Z1
V
Z
(TYP) = 12V
M2
GND
4 (5)
FAULT
(10)
MS ONLY
–
+
COMP1
2 ON 5 (6)
4211 BD
FB
COMP2
–
+
–
+
COMP3
t
TIMER
0.2V
V
REF
COMP4
–
+
V
REF
COMP5
NORMAL, RESET
NOTE 1: SET BY FILTER CAPACITOR FOR MS
20µs DEFAULT FOR MS8, S8
PIN NUMBERS FOR S8/MS8 (MS)
NORMAL
FAULT
TIMER
3 (4)
FILTER
(3)
MS ONLY
2µA
M6
M5
V
CC
2µA
M4
V
CC
10µA
LOGIC
RESET
1
COMP6
Z2
V
Z
(TYP) = 26V
V
CC
BLOCK DIAGRA
W
12
LTC4211
4211fa
HOT CIRCUIT INSERTION
When circuit boards are inserted into or removed from live
backplanes, the supply bypass capacitors can draw huge
transient currents from the backplane power bus as they
charge. The transient current can cause permanent dam-
age to the connector pins as well as cause glitches on the
system supply, causing other boards in the system to
reset.
The LTC4211 is designed to turn a printed circuit board’s
supply voltages ON and OFF in a controlled manner, allow-
ing the circuit board to be safely inserted or removed from
a live backplane. The device provides a system reset signal
to indicate when board supply voltage drops below a pre-
determined level, as well as a dual function fault monitor.
OUTPUT VOLTAGE MONITOR
The LTC4211 uses a 1.236V bandgap reference, precision
voltage comparator and an external resistor divider to
monitor the output supply voltage as shown in Figure 1.
The operation of the supply monitor in normal mode is il-
lustrated in Figure 2. When the supply voltage at the FB pin
drops below its reset threshold (1.236V), the comparator
COMP2 output goes high. After passing through a glitch fil-
ter, RESET is pulled low (Time Point N2). When the voltage
at the FB pin rises above its reset threshold (1.239V),
COMP2’s output goes low and a timing cycle starts (Time
Point N4). After a complete timing cycle, RESET is pulled
high by the external pull-up resistor. If the FB pin rises above
the reset threshold for less than a timing cycle, the RESET
output remains low (Time Point N3).
As shown in Figure 5, the LTC4211’s RESET pin is logic
low during any undervoltage lockout condition and during
the initial insertion of a PC board. Under normal operation,
RESET goes to logic high at the end of the soft-start cycle
only after the FB pin voltage rises above its reset threshold
of 1.239V.
+
SENSE
RSENSE
R2
R1 R3
10k
7
VCC
VOUT
8
GATELTC4211
6
2
FB
Q2
GND
ON
4211 F01
1RESET
5
CTIMER
3
TIMER
4
CLOAD
Q1
LOGIC
TIMER 1.236V
REFERENCE
COMP2
µP
RESET
SHORT
LONG
VCC
ON/RESET
GND LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
+
–
V
OUT
TIMER
RESET
V2 V2V1V1
1.236V
POWER GOOD
DELAY
N2N1 N3 N4
4211 F02
Figure 1. Supply Voltage Monitor Block Diagram
Figure 2. Supply Monitor Waveforms in Normal Mode
OPERATIO
U
13
LTC4211
4211fa
UNDERVOLTAGE LOCKOUT
The LTC4211’s power-on reset circuit initializes the start-
up procedure and ensures the chip is in the proper state if
the input supply voltage is too low. If the supply voltage
falls below 2.18V, the LTC4211 is in undervoltage lockout
(UVLO) mode, and the GATE pin is pulled low. Since the
UVLO circuitry uses hysteresis, the chip restarts after the
supply voltage rises above 2.3V and the ON pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively program
a higher undervoltage lockout level. Figure 3 shows the
external resistor divider at the ON pin programs the
system’s undervoltage lockout voltage. The system will
enter the plug-in cycle after the ON pin rises above 1.316V.
The resistor divider sets the circuit to turn on when V
CC
reaches around 79% of its final value. If a different turn on
V
CC
voltage is desired change the resistor divider value
accordingly. The FAULT comparator can be the alternative
for external undervoltage lockout setting. If the FAULT
comparator is used for this purpose, the system will wait
for the input voltage to increase above the level set by the
user before starting the second timing cycle. Also, if the
input voltage drops below the set level in normal operating
mode, the user must cycle the ON pin or V
CC
to restart the
system.
GLITCH FILTER FOR RESET
The LTC4211 has a glitch filter to prevent RESET from
generating a system reset if there are transients on the FB
OPERATIO
U
FEEDBACK TRANSIENT (mV)
0
GLITCH FILTER TIME (µs)
150
200
250
160
4211 F03
100
50
040 80 12020 18060 100 140 200
TA = 25°C
Figure 4. FB Comparator Glitch Filter Time
vs Feedback Transient Voltage
Figure 3. ON Pin Sets the Undervoltage
Lockout Voltage Externally
SYSTEM TIMING
System timing for the LTC4211 is generated at the TIMER
pin (see the Block Diagram). If the LTC4211’s internal
timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 2µA current source is then connected to the
TIMER pin to charge C
TIMER
at a rate given by Equation 1:
C Charge -Up Rate
TIMER
=µ2A
C
TIMER
(1)
When the TIMER pin voltage reaches COMP4’s threshold
of 1.236V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
tV
C
A
TIMER TIMER
=µ
1 236 2
.•
(2)
As a design aid, the LTC4211’s timer period as a function
of the C
TIMER
using standard values from 3.3nF to 0.33µF
is shown in Table 1.
V
IN
3.3V
R1
10k
R2
10k
ON PIN
(a) 3.3VIN
V
IN
5V
R1
20k
R2
10k
ON PIN
(b) 5VIN
V
IN
12V
R1
61.9k
R2
10k
ON PIN
(c) 12VIN
4211 F04
pin. The relationship between glitch filter time and the
feedback transient voltage is shown in Figure 4.
14
LTC4211
4211fa
The C
TIMER
value is vital to ensure a proper start-up and
reliable operation. A system may not get started if a timing
period is set too short in relation to the time needed for the
output voltage to ramp up from zero to its rated value.
Conversely, this timing period should not be excessive as
an output short can occur at start-up allowing the external
MOSFET to overheat. A good starting point is to set C
TIMER
= 10nF and adjust its value accordingly to suit the specific
applications.
OPERATING SEQUENCE
Power-Up, Start-Up Check and Plug-In Timing Cycle
The sequence of operations for the LTC4211 is illustrated
in the timing diagram of Figure 5. When a PC board is first
inserted into a live backplane, the LTC4211 first performs
VCC
ON
2µA2µA
10µA
PLUG-IN CYCLE
FIRST TIMING CYCLE
200µA
POWER
GOOD
(VFB > VREF)
VTMR = VREF
TIMER
12 345 6 7 8 9
RESET PULLED LOW DUE TO POWER BAD
10
SLOW COMPARATOR ARMEDCHECK FOR GATE < 0.2V
FAST COMPARATOR ARMED
CHECK FOR FILTER LOW (<VREF – 80mV)
CHECK FOR FAULT HIGH (>VREF + 50mV)
ON GOES LOW
GATE
VOUT
RESET
POWER BAD
(VFB < VREF)
SOFT-START CYCLE
SECOND TIMING CYCLE
4211 F05
Figure 5. Normal Power-Up Sequence
OPERATIO
U
Table 1. tTIMER vs CTIMER
C
TIMER
t
TIMER
0.0033µF 2.0ms
0.0047µF 2.9ms
0.0068µF 4.2ms
0.0082µF 5.1ms
0.01µF 6.2ms
0.015µF 9.3ms
0.022µF 13.6ms
0.033µF 20.4ms
0.047µF 29.0ms
0.068µF 42.0ms
0.082µF 50.7ms
0.1µF 61.8ms
0.15µF 92.7ms
0.22µF 136ms
0.33µF 204ms
15
LTC4211
4211fa
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass
transistor is pulled to ground by the internal 200µA current
source connected at the GATE pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4211 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10µA current source.
Once V
CC
and ON (the ON pin is >1.316) are valid, the
LTC4211 checks to make sure that GATE is OFF (V
GATE
<
0.2V) at Time Point 2. An internal timing circuit is enabled
and the TIMER pin voltage ramps up at the rate described
by Equation 1. At Time Point 3 (the timing period pro-
grammed by C
TIMER
), the TIMER pin voltage equals V
TMR
(1.236V). Next, the TIMER pin voltage ramps down to
Time Point 4 where the LTC4211 performs two checks: (1)
FILTER pin voltage is low (V
FILTER
< 1.156V) and (2)
FAULT pin voltage is high (V
FAULT
> 1.286V). If both
conditions are met, the LTC4211 begins a second timing
(soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point 5),
the LTC4211’s FAST COMP is armed and an internal 10µA
current source working with an internal charge pump
provides the gate drive to the external pass transistor. An
expression for the GATE voltage slew rate is given by
Equation 3:
V Slew Rate dV
dt
A
C
GATE GATE
GATE
,=µ10
(3)
where C
GATE
= Power MOSFET gate input capacitance
(C
ISS
).
For example, a Si4410DY (a 30V N-channel power MOSFET)
exhibits an approximate C
GATE
of 3300pF at V
GS
= 10V. The
LTC4211’s GATE voltage rate-of-change (slew rate) for
this example would be:
V Slew Rate dV
dt
A
pF
V
ms
GATE GATE
,.=µ=
10
3300 303
The inrush current being delivered to the load while the
GATE is ramping is dependent on C
LOAD
and C
GATE
.
Equation 4 gives an expression for the inrush current
during the second timing cycle:
IdV
dt CA
C
C
INRUSH GATE LOAD LOAD
GATE
==µ••10
(4)
For example, if C
GATE
= 3300pF and C
LOAD
= 2000µF, the
inrush current charging C
LOAD
is:
IA
F
FA
INRUSH =µ µ
µ=10 2000
0 0033 606•..
(5)
At Time Point 6, the output voltage trips COMP2’s thresh-
old, signaling an output voltage “power good” condition.
At Time Point 7, RESET is asserted high, SLOW COMP is
armed and the LTC4211 enters a fault monitor mode. The
TIMER voltage then ramps down to Time Point 8.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
ON
< 1.236V). The GATE pin
voltage is ramped to ground by the internal 200µA current
source, discharging C
GATE
and turning off the pass tran-
sistor. As C
LOAD
discharges, the output voltage crosses
COMP2’s threshold, signaling a “power bad” condition at
Time Point 10. At this point, RESET is asserted low.
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current was
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to C
LOAD
. If the
inrush current is large enough to cause a voltage drop
greater than 50mV across the sense resistor, an internal
servo loop controls the operation of the 10µA current
source at the GATE pin to regulate the load current to:
ImV
R
LIMIT SOFTSTART SENSE
()
=50
(6)
For example, the inrush current is limited to 5A when
R
SENSE
= 0.01Ω.
OPERATIO
U
16
LTC4211
4211fa
In this fashion, the inrush current is controlled and C
LOAD
is charged up slowly during the soft-start cycle.
The timing diagram in Figure 6 illustrates the operation of
the LTC4211 in a normal power-up sequence with limited
inrush current as described by Equation 6. At Time Point 5,
the GATE pin voltage begins to ramp indicating that the
power MOSFET is beginning to charge C
LOAD
. At Time
Point 5A, the inrush current causes a 50mV voltage drop
across R
SENSE
and the internal servo loop engages, limit-
ing the inrush current to a fixed level. At Time Point 6, the
GATE pin voltage continues to ramp as C
LOAD
charges until
V
OUT
reaches its final value. The charging current reduces,
and the internal servo loop disengages. At the end of the
soft-start cycle (Time Point 7), RESET is high and SLOW
COMP is armed.
PLUG-IN CYCLE
FIRST TIMING CYCLE
TIMER
ON
V
CC
12 345 6 7 8 9
RESET PULLED LOW DUE TO POWER BAD
10
200µA
4211 F06
2µA2µA
V
REF
10µA
GATE
V
OUT
POWER BAD
V
FB
< V
REF
5A
SLOW COMPARATOR ARMEDCHECK FOR GATE < 0.2V
FAST COMPARATOR ARMED
CHECK FOR FILTER LOW (<V
REF
– 80mV)
CHECK FOR FAULT HIGH (>V
REF
+ 50mV)
ON GOES LOW
GATE
V
OUT
I
LOAD
RESET
SOFT-START CYCLE
SECOND TIMING CYCLE
POWER GOOD
V
FB
> V
REF
LOAD CURRENT IS
REGULATING AT 50mV/R
SENSE
Figure 6. Normal Power-Up Sequence (With Current Limiting in Second Timing Cycle)
FREQUENCY COMPENSATION AT SOFT-START
If the external gate input capacitance (C
ISS
) is greater than
600pF, no external gate capacitor is required at GATE to
stabilize the internal current-limiting loop during soft-
start. Otherwise, connect a gate capacitor between the
GATE pin and ground to increase the total gate capacitance
to be equal to or above 600pF. The servo loop that controls
the external MOSFET during current limiting has a unity-
gain frequency of about 105kHz and phase margin of 80°
for external MOSFET gate input capacitances to 2.5nF.
USING AN EXTERNAL GATE CAPACITOR
The LTC4211 automatically limits the inrush current in one
of two ways: by controlling the GATE pin voltage slew rate
OPERATIO
U
17
LTC4211
4211fa
or by actively limiting the inrush current. The LTC4211
uses GATE voltage slew rate limiting when C
LOAD
is small
and/or the inrush current limit is set high. If GATE voltage
slew rate control is preferred with large C
LOAD
, an external
capacitor (C
GX
) can be used from GATE to ground, as
shown in Figure 7. According to Equation 3, adding C
GX
slows the GATE voltage slew rate at the expense of slower
system turn-on and turn-off time. Should this technique
be used, values for C
GX
less than 150nF are recommended.
trips, the GATE pin is immediately pulled to ground, the
external N-channel MOSFET is quickly turned OFF and
FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4211’s SLOW COMP and FAST COMP thresholds (see
Block Diagram). The SLOW COMP trips the circuit breaker
if the voltage across the SENSE resistor (V
CC
– V
SENSE
=
V
CB
) is greater than 50mV for 20µs. There may be appli-
cations where this comparator’s response time is not long
enough, for example, because of excessive supply voltage
noise. To adjust the response time of the SLOW COMP, the
MS version of the LTC4211 is chosen and a capacitor is
used at the LTC4211’s FILTER pin (see section on Adjust-
ing SLOW Comp’s Response Time). The FAST COMP trips
the circuit breaker to protect against fast load overcurrents
if the transient voltage across the sense resistor is greater
than 150mV for 300ns. The response time of the LTC4211’s
FAST COMP is fixed.
The timing diagram of Figure 6 illustrates when the
LTC4211’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4211’s FAST COMP is armed at
Time Point 5. Arming FAST COMP at Time Point 5 ensures
that the system is protected against a short-circuit
condition during the second timing cycle after CLOAD has
been fully charged. At Time Point 7, SLOW COMP is
armed when the internal control loop is disengaged.
The timing diagrams in Figures 8 and 9 illustrate the opera-
tion of the LTC4211 when the load current conditions exceed
the thresholds of the FAST COMP (V
CB(FAST)
> 150mV)
and SLOW COMP (V
CB(SLOW)
> 50mV), respectively.
RESETTING THE ELECTRONIC CIRCUIT BREAKER
Once the LTC4211’s circuit breaker is tripped, FAULT is
asserted low and the GATE pin is pulled to ground. The
LTC4211 remains latched OFF in this fault state until the
external fault is cleared. To clear the internal fault detect
circuitry and to restart the LTC4211, its ON pin must be
driven low (V
ON
< 1.236V) for at least 150µs, after which
time FAULT goes high. Toggling the ON pin from low to
high (V
ON
> 1.316V) initiates a restart sequence in the
LTC4211. The timing diagram in Figure 10 illustrates a
OPERATIO
U
M1
Si4410DY
R
SENSE
0.007Ω
C
GX
*
C
LOAD
4211 F07
+
V
CC
SENSE
LTC4211**
GATE
FB
R1
36k
V
OUT
5V
5A
V
IN
5V
R2
15k
*
**
VALUES ≤150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY =
dV
GATE
dt
V
GATE
SLEW RATE CONTROL
10µA
C
GATE
+ C
GX
()
Figure 7. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control and Large CLOAD
An external gate capacitor may also be useful to decrease
or eliminate current spikes through the MOSFET when
power is first applied. At power-up, the instantaneous in-
put voltage step attempts to pull the MOSFET gate up
through the MOSFET’s drain-to-gate capacitance. If the
MOSFET’s C
GS
is small, the gate can be pulled up high
enough to turn on the MOSFET, thereby allowing a current
spike to the output. This event occurs during the time that
the LTC4211 is coming out of UVLO and getting its intel-
ligence to hold the GATE pin low. An external capacitor
attenuates the voltage to which the GATE is pulled up and
eliminates the current spike. The value required is depen-
dent on the MOSFET capacitance specifications. In typical
applications, this capacitor is not required.
ELECTRONIC CIRCUIT BREAKER
The LTC4211 features an electronic circuit breaker func-
tion that protects against supply overvoltage, externally-
generated fault conditions and shorts or excessive load
current conditions on the supply. If the circuit breaker
18
LTC4211
4211fa
GATE
TIMER
V
CC
ON
12 345 6 78
GATE
V
OUT
A
SHORT CIRCUIT RESET PULLED LOW DUE TO POWER BAD
BC
SLOW COMPARATOR ARMED
CIRCUIT BREAKER TRIPS
FAST COMPARATOR ARMED
V
OUT
V
CC
– V
SENSE
FAULT
RESET
POWER GOOD
V
FB
> V
REF
POWER BAD
V
FB
< V
REF
FPD
>150mV
4211 F08
300ns
TYP
Figure 8. Output Short Circuit Causes Fast Comparator to Trip the Circuit Breaker
OPERATIO
U
19
LTC4211
4211fa
GATE
TIMER
VCC
12 3 45 6 7 8 A
OVER CURRENT RESET PULLED LOW DUE TO POWER BAD
BC
FAST COMPARATOR ARMED
CIRCUIT BREAKER TRIPS
CIRCUIT BREAKER TRIPS
10µA
2µA
VREF
POWER BAD
VFB < VREF
FPD
GATE
VOUT
>50mV
4211 F09
SLOW COMPARATOR ARMED
VOUT
VCC – VSENSE
FILTER
FAULT
RESET
ON
POWER GOOD
VFB > VREF
Figure 9. Mild Overcurrent Slow Comparator Trips the Circuit Breaker After Filter Programming Period
OPERATIO
U
20
LTC4211
4211fa
GATE
TIMER
VCC
12 3 45 6
GATE
VFB < VREF
>50mV
VREF
10µA
4211 F10
tRESET
tFAULTSC
2µA
FPD
VOUT
78 B 9 9A 1
FAST COMPARATOR ARMED
CIRCUIT BREAKER TRIPS
CIRCUIT BREAKER RESET
SLOW COMPARATOR ARMED
VOUT
VCC – VSENSE
FILTER
FAULT
RESET
ON ONON
VSENSE = 50mV
REGULATING
LOAD CURRENT
Figure 10. Power-Up in Overcurrent, Slow Comparator Trips the Circuit Breaker
start-up sequence where the LTC4211 is powered up into
a load overcurrent condition. Note that the circuit breaker
trips at Time Point B and is reset at Time Point 9A.
ADJUSTING SLOW COMP’S RESPONSE TIME
The response time of SLOW COMP is adjusted using a
capacitor connected from the LTC4211’s FILTER pin to
ground. If this pin is left unused, SLOW COMP’s delay
defaults to 20µs. During normal operation, the FILTER
output pin is held low as an internal 10µA pull-down
current source is connected to this pin by transistor M4.
This pull-down current source is turned off when an
overcurrent load condition is detected by SLOW COMP.
During an overcurrent condition, the internal 2µA pull-up
current source is connected to the FILTER pin by transis-
tor M5, thereby charging C
FILTER
. As the charge on the
capacitor accumulates, the voltage across C
FILTER
increases. Once the FILTER pin voltage increases to 1.236V,
the electronic circuit breaker trips and the LTC4211’s
GATE pin is switched quickly to ground by transistor M3.
After the circuit breaker is tripped, M5 is turned OFF, M4
is turned ON and the 10µA pull-down current then holds
the FILTER pin voltage low.
The SLOW COMP response time from an overcurrent fault
condition to when the circuit breaker trips (GATE OFF) is
given by Equation 7:
tV
C
As
SLOWCOMP FILTER
=µ+µ1 236 220.•
(7)
For example, if C
FILTER
= 1000pF, SLOW COMP’s response
time = 638µs. As a design aid, SLOW COMP’s delay time
(t
SLOW COMP
) versus C
FILTER
for standard values of C
FILTER
from 100pF to 1000pF is illustrated in Table 2.
OPERATIO
U
21
LTC4211
4211fa
Table 2. tSLOWCOMP vs CFILTER
C
FILTER
t
SLOWCOMP
100pF 82µs
220pF 156µs
330pF 224µs
470pF 310µs
680pF 440µs
820pF 527µs
1000pF 638µs
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4211’s
V
CC
and SENSE pins are strongly recommended. The
drawing in Figure 11 illustrates the correct way of making
connections between the LTC4211 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
The power rating of the sense resistor should accommo-
date steady-state fault current levels so that the compo-
nent is not damaged before the circuit breaker trips.
Table 4 in the Appendix lists sense resistors that can be
used with the LTC4211’s circuit breaker.
IRC-TT SENSE RESISTOR
LR251201R010F
OR EQUIVALENT
0.01Ω, 1%, 1W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TO
V
CC
TO
SENSE
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
4211 F11
Figure 11. Making PCB Connections to the Sense Resistor
OPERATIO
U
CALCULATING CIRCUIT BREAKER TRIP CURRENT
For a selected R
SENSE
value, the nominal load current that
trips the circuit breaker is given by Equation 10:
IV
R
mV
R
TRIP NOM CB NOM
SENSE NOM SENSE NOM
() ()
() ()
==
50
(10)
The minimum load current that trips the circuit breaker is
given by Equation 11.
IV
R
mV
R
TRIP MIN CB MIN
SENSE MAX SENSE MAX
() ()
() ()
==
40
(11)
where
RR R
SENSE MAX SENSE NOM TOL
() ()
•=+
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥
1100
SENSE RESISTOR CONSIDERATIONS
The fault current level at which the LTC4211’s internal
electronic circuit breaker trips is determined by a sense
resistor connected between the LTC4211’s V
CC
and SENSE
pins and two separate trip points. The first trip point is set
by the SLOW COMP’s threshold, V
CB(SLOW)
= 50mV, and
occurs should a load current fault condition exist for more
than 20µs. The current level at which the electronic circuit
breaker trips is given by Equation 8:
IV
R
mV
R
TRIP SLOW CB SLOW
SENSE SENSE
() ()
==
50
(8)
The second trip point is set by the FAST COMP’s threshold,
V
CB(FAST)
= 150mV, and occurs during fast load current
transients that exist for 300ns or longer. The current level
at which the circuit breaker trips in this case is given by
Equation 9:
IV
R
mV
R
TRIP FAST CB FAST
SENSE SENSE
() ()
==
150
(9)
As a design aid, the currents at which electronic circuit
breaker trips for common values for R
SENSE
are shown in
Table 3.
Table 3. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE
R
SENSE
I
TRIP(SLOW)
I
TRIP(FAST)
0.005Ω10A 30A
0.006Ω8.3A 25A
0.007Ω7.1A 21A
0.008Ω6.3A 19A
0.009Ω5.6A 17A
0.01Ω5A 15A
22
LTC4211
4211fa
The maximum load current that trips the circuit breaker is
given in Equation 12.
IV
R
mV
R
TRIP MAX CB MAX
SENSE MIN SENSE MIN
() ()
() ()
==
60
(12)
where
RR R
SENSE MIN SENSE NOM TOL
() ( )
•–=⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
1100 ⎦⎦
⎥
For example:
If a sense resistor with 7mΩ ±5% R
TOL
is used for current
limiting, the nominal trip current I
TRIP(NOM)
= 7.1A. From
Equations 11 and 12, I
TRIP(MIN)
= 5.4A and I
TRIP(MAX)
=
9.02A respectively.
For proper operation and to avoid the circuit breaker
tripping unnecessarily, the minimum trip current
(I
TRIP(MIN)
) must exceed the circuit’s maximum operating
load current. For reliability purposes, the operation at the
maximum trip current (I
TRIP(MAX)
) must be evaluated
carefully. If necessary, two resistors with the same R
TOL
can be connected in parallel to yield an R
SENSE(NOM)
value
that fits the circuit requirements.
POWER MOSFET SELECTION CRITERIA
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, V
DS(MAX)
, and the
maximum drain current, I
D(MAX)
of the MOSFET. The
V
DS(MAX)
rating must exceed the maximum input supply
voltage (including surges, spikes, ringing, etc.) and the
I
D(MAX)
rating must exceed the maximum short-circuit
current in the system during a fault condition. In addition,
consider three other key parameters: 1) the required gate-
source (V
GS
) voltage drive, 2) the voltage drop across the
drain-to-source on resistance, R
DS(ON)
and 3) the maxi-
mum junction temperature rating of the MOSFET.
Power MOSFETs are classified into two categories: stan-
dard MOSFETs (R
DS(ON)
specified at V
GS
= 10V)
logic-level MOSFETs (R
DS(ON)
specified at V
GS
= 5V), and
sub-logic-level MOSFETs (R
DS(ON)
specified at V
GS
= 2.5V).
The absolute maximum rating for V
GS
is typically ±20V for
standard MOSFETs. However, the V
GS
maximum rating
for logic-level MOSFETs ranges from ±8V to ±20V de-
pending upon the manufacturer and the specific part
number. The LTC4211’s GATE overdrive as a function of
V
CC
is illustrated in the Typical Performance curves. Logic-
level and sub-logic-level MOSFETs are recommended for
low supply voltage applications and standard MOSFETs
can be used for applications where supply voltage is
greater than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
V
GS
voltage on the external MOSFET. Usually, the selected
external MOSFET should have a ±V
GS(MAX)
rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
V
GS
voltage. In addition, the ±V
GS(MAX)
rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower ±V
GS(MAX)
rating MOSFETs can be used with the
LTC4211 if the GATE overdrive is clamped to a lower
voltage. The circuit in Figure 12 illustrates the use of Zener
diodes to clamp the LTC4211’s GATE overdrive signal if
lower voltage MOSFETs are used.
OPERATIO
U
V
CC
V
OUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
4211 F12
R
SENSE
GATE
D2*
D1*
Q1
R
G
200Ω
Figure 12. Optional Gate Clamp for Lower VGS(MAX) MOSFETs
23
LTC4211
4211fa
The R
DS(ON)
of the external pass transistor should be low
to make its drain-source voltage (V
DS
) a small percentage
of V
CC
. At a V
CC
= 2.5V, V
DS
+ V
RSENSE
= 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low R
DS(ON)
. At higher V
CC
voltages, the
V
DS
requirement can be relaxed in which case MOSFET
package dissipation (P
D
and T
J
) may limit the value of
R
DS(ON)
. Table 5 lists some power MOSFETs that can be
used with the LTC4211.
For reliable circuit operation, the maximum junction tem-
perature (T
J(MAX)
) for a power MOSFET should not exceed
the manufacturer’s recommended value. This includes
normal mode operation, start-up, current-limit and
autoretry mode in a fault condition. Under normal condi-
tions the junction temperature of a power MOSFET is given
by Equation 13:
MOSFET Junction Temperature,
T
J(MAX)
≤ T
A(MAX)
+ θ
JA
• P
D
(13)
where
P
D
= (I
LOAD
)
2
• R
DS(ON)
θ
JA
= junction-to-ambient thermal resistance
T
A(MAX)
= maximum ambient temperature
If a short circuit happens during start-up, the external
MOSFET can experience a big single pulse energy. This is
especially true if the applications only employed a small
gate capacitor or no gate capacitor at all. Consult the safe
operating area (SOA) curve of the selected MOSFET to
ensure that the T
J(MAX)
is not exceeded during start-up.
USING STAGGERED PIN CONNECTORS
The LTC4211 can be used on either a printed circuit board
or on the backplane side of the connector, and examples
for both are shown in Figures 13 and 14. Printed circuit
board edge connectors with staggered pins are recom-
mended as the insertion and removal of circuit boards do
sequence the pin connections. Supply voltage and ground
connections on the printed circuit board should be wired
to the edge connector’s long pins or blades. Control and
status signals (like RESET, FAULT and ON) passing through
the card’s edge connector should be wired to short length
pins or blades.
PCB CONNECTION SENSE
There are a number of ways to use the LTC4211’s ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4211 commences
a start-up cycle.
The first example is shown in the schematic on the front
page of this data sheet. In this case, the LTC4211 is
mounted on the PCB and a 20k/10k resistive divider is
connected to the ON pin. On the edge connector, R1 is
wired to a short pin. Until the connectors are fully mated,
the ON pin is held low, keeping the LTC4211 in an OFF
state. Once the connectors are mated, the resistive divider
is con
nected to V
CC
, V
ON
> 1.316V and the LTC4211
begins a start-up cycle.
In Figure 13, an LTC4211 is illustrated in a basic configu-
ration on a PCB daughter card. The ON pin is connected to
V
CC
on the backplane through a 10k pull-up resistor once
the card is seated into the backplane. R2 bleeds off any
potential static charge which might exist on the backplane,
the connector or during card installation.
A third example is shown in Figure 14 where the LTC4211
is mounted on the backplane. In this example, a 2N2222
transistor and a pair of resistors (R4, R5) form the PCB
connection sense circuit. With the card out of the chassis,
Q2’s base is biased to V
CC
through R5, biasing Q2 ON and
driving the LTC4211’s ON pin low. The base of Q2 is also
wired to a socket on the backplane connector. When a card
is firmly seated into the backplane, the base of Q2 is then
grounded through a short pin connection on the card. Q2
is biased OFF, the LTC4211’s ON pin is pulled-up to V
CC
and a start-up cycle begins.
In the previous three examples, the connection sense was
hard wired with no processor (low) interrupt capability. As
illustrated in Figure 15, the addition of an inexpensive
logic-level discrete MOSFET and a couple of resistors
offers processor interrupt control to the connection sense.
R4 keeps the gate of M2 at V
CC
until the card is firmly
mated to the backplane. A logic low for the ON/OFF signal
turns M2 OFF, allows the ON pin to pull high and turns on
the LTC4211.
OPERATIO
U
24
LTC4211
4211fa
APPLICATIO S I FOR ATIO
WUUU
A more elaborate connection sense scheme is shown in
Figure 16. The bases of Q1 and Q2 are wired to short pins
located on opposite ends of the edge connector because
the installation/removal of printed circuit cards generally
requires rocking the card back and forth. When V
CC
makes connection, the bases of transistors Q1 and Q2 are
pulled high, biasing them ON. When either one of them is
ON, the LTC4211’s ON pin is held low, keeping the
LTC4211 OFF. When both the short base connector pins
+
VCC
RESET
SENSEON
R5
15k
LTC4211
GATE
FB
8
7
6
5
4211 F13
1
2
4
3CTIMER
10nF
GND
TIMER
R4
36k
VOUT
5V
5A
Q1
Si4410DY
RSENSE
0.007Ω
COUT
R6
10k
Z1*
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
R1
10Ω
C1
0.1µF
R2
10k
VIN
5V
SHORT
LONG
5V
VCC
RESET
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
+
V
CC
SENSE
ON
R2
100k
RESET
LTC4211
GATE
FB
78
6
1
5
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
4211 F14
2
4
3C
TIMER
10nF
R3
10k
GND
TIMER
RESET
V
OUT
5V
5A
Q1
Si4410DY
R
SENSE
0.007Ω
C
OUT
R1
36k
R4
10k
R5
10k
PCB
CONNECTION
SENSE
R
X
10Ω
C
X
0.1µF
Z1*
V
IN
5V
SHORT
LONG
SHORT
PCB EDGE
CONNECTOR
(MALE)
LONG
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
Q2
R7
15k
Figure 13. Hot Swap Controller On Daughter Board (Staggered Pin Connections)
Figure 14. Hot Swap Controller on Backplane (Staggered Pin Connections)
of Q1 and Q2 finally mate to the backplane, their bases are
grounded, biasing the transistors OFF. The ON pin volt-
age is then pulled high by R3 enabling the LTC4211 and
a power-up cycle begins.
A software-initiated power-down cycle can be started by
momentarily driving transistor M1 with a logic high signal.
This in turn will drive the LTC4211’s ON pin low. If the ON
pin is held low for more than 8µs, the LTC4211’s GATE pin
is switched to ground.
25
LTC4211
4211fa
APPLICATIO S I FOR ATIO
WUUU
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
5V
5A
4211 F15
5
1
R6
15k
GATE
GNDTIMER
PCB CONNECTION SENSE
CTIMER
10nF
FB
ON
SHORT
LONG
VCC
5V
GND
ON/OFF
LONG
ZZ1 = 1SMA10A OR SMAJ10A
M2: 2N7002LT1
* OPTIONAL
RESET
R2
10k
R4
10k
M2
R1
10k
RX
10Ω
RSENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1*
R5
36k
R7
10k
µP
LOGIC
RESET
SHORT
CX
100nF
BACKPLANE
CONNECTOR
(FEMALE)
Figure 15. Connection Sense with ON/OFF Control
+
V
CC
SENSE
LTC4211
8
2
34
76
C
LOAD
V
OUT
5V
5A
4211 F16
5
1
R5
15k
GATE
GNDTIMER
PCB CONNECTION SENSE
C
TIMER
10nF
FB
ON
LONG
V
CC
GND
ON/RESET
LONG
RESET
M1
R
X
10Ω
R
SENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE)
M2
Si4410DY
Z1* R3
10k
R2
10k
R1
10k
R8
10k
R4
36k
R7
10k
µP
LOGIC
RESET
SHORT
SHORT
LAST BLADE OR PIN ON CONNECTOR
SHORT
C
X
0.1µF
BACKPLANE
CONNECTOR
(FEMALE)
Q1
Q2
LAST BLADE OR PIN ON CONNECTOR
Z1 = 1SMA10A OR SMAJ10A
M1: 2N7002LT1
Q1, Q2: MMBT3904LT1
* OPTIONAL
Figure 16. Connection Sense for Rocking the Daughter Board Back and Forth
26
LTC4211
4211fa
APPLICATIO S I FOR ATIO
WUUU
Figure 17. 12V Hot Swap Application
12V Hot Swap Application
Figure 17 shows a 12V, 3A hot swap application circuit.
The resistor divider R1/R2 programs the undervoltage
lockout externally and allows the system to start up after
V
CC
increases above 9.46V. The resistor divider R3/R4
monitors V
OUT
and signals the RESET pin when V
OUT
goes
above 10.54V. Transient voltage suppressor Z1 and snub-
ber network (C
X
, R
X
) are highly recommended to protect
the 12V applications system from ringing and voltage
spikes. R
G
is recommended for V
CC
> 10V and it can
minimize high frequency parasitic oscillations in the power
MOSFET.
AUTORETRY AFTER A FAULT
To configure the LTC4211 to automatically retry after a
fault condition, the FAULT and ON pins can be connected
to a pull-up resistor (R
AUTO
) to the supply, as shown in
FAULT
V
CC
LTC4211MS
SENSE
GATE
FB
1
2
3
4
5
10
R
SENSE
0.007Ω
Q1
Si4410DY
9
8
7
6
RESET
ON
FILTER
TIMER
C
TIMER
10nF
GND
C
FILTER
100pF
R
AUTO
(SEE NOTE)
R
PULL-UP
10k
C
AUTO
1µF
R3
10ΩZ1*
NOTE:
Q1 MOUNTED TO 300mm
2
COPPER AREA
R
AUTO
= 1M YIELDS 2.5%
DUTY CYCLE AND Q1 T
CASE
= 50°C
R
AUTO
= 3.2M YIELDS 0.8%
DUTY CYCLE AND Q1 T
CASE
= 37°C
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
4211 F18
C1
0.1µF
R1
36k
V
OUT
5V
5A
C
LOAD
R2
15k
+
LONG
V
CC
5V
GND
RESET
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
Figure 18. LTC4211MS Autoretry Application
Figure 18. In this case, the autoretry circuitry will attempt
to restart the LTC4211 with a 50% duty cycle, as shown in
the timing diagram of Figure 19. To prevent overheating
the external MOSFET and other components during the
autoretry sequence, adding a capacitor (C
AUTO
) to the
circuit introduces an RC time constant (t
OFF
) that adjusts
the autoretry duty cycle. Equation 14 gives the autoretry
duty cycle, modified by this external time constant:
Autoretry Duty Cycle t
tt
TIMER
OFF TIMER
≈+2100
••%
(14)
where t
TIMER
= LTC4211 system timing(see TIMER func-
tion) and t
OFF
is a time needed to charge capacitor C
AUTO
from 0V to the ON pin threshold (1.316V).
For the values shown, the external RC time constant is set
at 1 second, the t
TIMER
delay equals 6.2ms and the
autoretry duty cycle drops from 50% to 2.5%.
+
VCC SENSE
LTC4211
8
2
34
76
CLOAD
VOUT
12V
3A
GND
4211 F17
5
1
R4
12.4k
GATE
GNDTIMER
PCB CONNECTION SENSE CTIMER
8.2nF
FB
ON
SHORT
LONG
VCC
12V
GND LONG
Z1 = 1SMA12A OR SMAJ12A
** HIGHLY RECOMMENDED
RESET
R2
10k
R1
61.9k
RX
10Ω
RSENSE
0.012Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1** RG
100ΩR3
93.1k
R5
10k
µP
LOGIC
RESET
CX
100nF
BACKPLANE
CONNECTOR
(FEMALE)
27
LTC4211
4211fa
To increase the RC delay, the user may either increase
C
AUTO
or R
AUTO
. However, increasing C
AUTO
> 2µF will
actually limit the RC delay due to the reset sink-current
capability of the FAULT pin. Therefore, in order to increase
the RC delay, it is more effective to either increase R
AUTO
or to put a bleed resistor in parallel with C
AUTO
to GND. As
an example, increasing R
AUTO
from 1M to 3.2M decreases
duty cycle to 0.8%.
HOT SWAPPING TWO SUPPLIES
Using two external pass transistors, the LTC4211 can
switch two supply voltages. In some cases, it is necessary
to bring up the dominant supply first during power-up but
ramp them down together during the power-down phase.
The circuit in Figure 20 shows how to program two
different delays for the pass transistors. The 5V supply is
powered up first. R1 and C3 are used to set the rise and fall
times on the 5V supply. Next, the 3.3V supply ramps up
APPLICATIO S I FOR ATIO
WUUU
1
VCC
TIMER
GATE
RESET
VCC – VSENSE
FILTER
VOUT
235674 B8
SLOW COMPARATOR ARMED
FAST COMPARATOR ARMED
tOFF t1t2tFILTER tOFF
VREF
>50mV
GATE
VFB < VREF VOUT
FPD
tRESET
VSENSE = 50mV
REGULATED
LOAD CURRENT
10µA
4211 F19
2µA
ON/FAULTON/FAULT
DUTY CYCLE = (tFILTER << t1, t2 AND tOFF)
t2
tOFF + t1 + t2
with 20ms delay set by R6 and C2. On the falling edge, both
supplies ramp down together because D1 and D2 bypass
R1 and R6.
OVERVOLTAGE TRANSIENT PROTECTION
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often
placed at the supply connection of every active device, in
addition to one or more large value bulk bypass capacitors
per supply rail. If power is connected abruptly, the large
bypass capacitors slow the rate of rise of the supply
voltage and heavily damp any parasitic resonance of lead
or PC track inductance working against the supply bypass
capacitors.
The opposite is true for LTC4211 Hot Swap circuits
mounted on plug-in cards. In most cases, there is no
supply bypass capacitor present on the powered supply
Figure 19. Autoretry Timing
28
LTC4211
4211fa
APPLICATIO S I FOR ATIO
WUUU
voltage side of the MOSFET switch. An abrupt connection,
produced by inserting the board into a backplane connec-
tor, resulting in a fast rising edge applied on the supply line
of the LTC4211.
Since there is no bulk capacitance to damp the parasitic
track inductance, supply voltage transients excite
parasitic resonant circuits formed by the power MOSFET
capacitance and the combined parasitic inductance from
the wiring harness, the backplane and the circuit board
traces.
I
n these applications, there are two methods that should
be applied together for eliminating these supply voltage
transients: using transient voltage suppressor to clip the
transient to a safe level and snubber networks. Snubber
networks are series RC networks whose time constants
are experimentally determined based on the board’s para-
sitic resonance circuits. As a starting point, the capacitors
in these networks are chosen to be 10× to 100× the power
MOSFET’s COSS under bias. The series resistor is a value
determined experimentally and ranges from 1Ω to 50Ω,
depending on the parasitic resonance circuit. For applica-
tions with supply voltages of 12V or higher the ringing and
overshoot during hot-swapping or when the output is
short-circuited can easily exceed the absolute maximum
specification of the LTC4211. To reduce the danger,
transient voltage suppressors and snubber networks are
highly recommended. For applications with lower supply
voltage such as 5V, usually a snubber is adequate to
reduce the supply ringing. Although, the need of a tran-
sient voltage suppressor arises for inductive and high
current application. Note that in all LTC4211 5V applica-
tions schematics, transient suppressor and snubber net-
works have been added for protection. The transient
suppressor is optional and a simple short-circuit test can
be performed to determine the need of it. These protection
networks should be mounted very close to the LTC4211’s
supply input rail using short lead lengths to minimize lead
inductance. This is shown schematically in Figure 21, and
a recommended layout of the transient protection devices
around the LTC4211 is shown in Figure 22.
1
2
3
4
8
7
6
5
V
CC
SENSE
GATE
FB
RESET
ON
TIMER
GND
LTC4211
4211 F20
D1
1N4148
D2
1N4148
Q1
1/2 Si4936DY
Q2
1/2 Si4936DY
R2
0.015Ω
5%
R3
10Ω
5%
R8
10Ω
Z1* C4
0.1µF
C1
10nF
16V
R1
10k
5%
R6
1M
5%
R7
10Ω
5%
R4
2.74k
1%
TRIP POINT: 4.06V
R5
1.2k
1%
C3
0.047µF
25V
C2
0.022µF
25V
C
LOAD
C
LOAD
D3**
V
OUT1
3.3V
2A
V
OUT2
5V
2A
5V OUT
3.3V OUT
CURRENT LIMIT: 3.3A
+
+
R9
10Ω
R10
10k
10k
Z2* C5
0.1µF
R11
10k
LONG
3.3V
GND
RESET
LONG
**D3 IS OPTIONAL AND HELPS DISCHARGE V
OUT1
IF V
OUT2
SHORTS
PCB EDGE
CONNECTOR
(MALE)
LONG
BACKPLANE
CONNECTOR
(FEMALE)
5V
SHORT
SHORT
ON
Z1, Z2: 1SMA10A OR SMAJ10A
* OPTIONAL
Figure 20. Switching 5V and 3.3V
Figure 21. Placing Transient Protection Devices
Close to the LTC4211’s Input Rail
+
VCC SENSE
LTC4211
8
34
76
COUT
VOUT
5V
5A
OUTPUT
GND
INPUT
GND
4211 F21
5
1
2
R2
15k
GATE
GND TIMER
C
TIMER
FB
ON ON
RESET
R
X
10Ω
V
IN
5V
R
SENSE
0.007Ω
Q1
Si4410DY
R1
36k
RESET
Z1*
C
X
0.1µF
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
29
LTC4211
4211fa
RESET
ON
TIMER
GND
V
CC
SENSE
LTC4211**
1
4211 F28
GATE
FB
D
D
D
D
G
S
S
S
W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
CURRENT FLOW
FROM LOAD
SENSE RESISTOR
(R
SENSE
)
POWER MOSFET
(SO-8)
W
W
VIA TO
GND PLANE
NOTES:
DRAWING IS NOT TO SCALE!
*OPTIONAL COMPONENTS
**ADDITIONAL DETAILS OMITTED
FOR CLARITY
R4
15k
C
TIMER
10nF
R3
36k
C
GX
*
R
GX
*
R
X
C
X
SNUBBER
NETWORK
Z1*
TRANSIENT
VOLTAGE
SUPPRESSOR
APPLICATIO S I FOR ATIO
WUUU
Figure 22. Recommended Layout for LTC4211 Protection Devices, RSENSE, Power MOSFET and Feedback Network
30
LTC4211
4211fa
SUPPLY OVERVOLTAGE DETECTION/
PROTECTION USING FILTER PIN
In addition to using external protection devices around the
LTC4211 for large scale transient protection, low power
Zener diodes can be used with the LTC4211’s FILTER pin
to act as a supply overvoltage detection/protection circuit
on either the high side (input) or low side (output) of the
external pass transistor. Recall that internal control cir-
cuitry keeps the LTC4211 GATE voltage from ramping up
if V
FILTER
> 1.156V, or when an external fault condition
(V
FILTER
> 1.236V) causes FAULT to be asserted low.
High Side (Input) Overvoltage Protection
As shown in Figure 23, a low power Zener diode can be
used to sense an overvoltage condition on the input
(high) side of the main 5V supply. In this example, a low
bias current 1N4691 Zener diode is chosen to protect the
system. Here, the Zener diode is connected from V
CC
to
the LTC4211’s FILTER pin (Pin 3 MS). If the input voltage
to the system is greater than 6.8V during start-up, the
voltage on the FILTER pin is pulled higher than its 1.156V
APPLICATIO S I FOR ATIO
WUUU
threshold. As a result, the GATE pin is not allowed to ramp
and the second timing cycle will not commence until the
supply overvoltage condition is removed. Should the
supply overvoltage condition occur during normal op-
eration, internal control logic would trip the electronic
circuit breaker and the GATE would be pulled to ground,
shutting OFF the external pass transistor. If a lower
supply overvoltage threshold is desired, use a Zener
diode with a smaller breakdown voltage.
A timing diagram for illustrating LTC4211 operation under
a high side overvoltage condition is shown in Figure 24.
The start-up sequence in this case (between Time Points
1 and 2) is identical to any other start-up sequence under
normal operating conditions. At Time Point 2A, the input
supply voltage causes the Zener diode to conduct thereby
forcing V
FILTER
> 1.156V. At Time Point 3, FAULT is
asserted low and the TIMER pin voltage ramps down. At
Time Point 4, the LTC4211 checks if V
FILTER
< 1.156V.
Figure 23. LTC4211MS High Side Overvoltage Protection Implementation
1
2
3
4
5
10
9
8
7
6
FAULT
V
CC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Z1 = 1SMA10A OR SMAJ10A
Z2 = 1N4691
* OPTIONAL
Q1
Si4410DY
R1
36k
V
OUT
5V
5A
R2
15k
C
LOAD
4211 F23
R
SENSE
0.007Ω
+
C
TIMER
10nF
C
FILTER
47pF
Z2
6.2V
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R3
10Ω
Z1* C1
0.1µF
R5
10k
R6
10k
R7
10k
R4
10k
31
LTC4211
4211fa
FAULT is asserted low (but not latched) to indicate a start-
up failure. Only if the input overvoltage condition is re-
moved before Time Point 5 does the start-up sequence
resume at the second timing cycle. At this point in time, the
GATE pin voltage is allowed to ramp up, FAULT is pulled
to logic high and the circuit breaker is armed. Should, at
any time after Time Point 5, a supply overvoltage condition
develop (V
FILTER
> 1.236V), the electronic circuit breaker
will trip, the GATE will be pulled low to turn off the external
MOSFET and FAULT will be asserted low and latched. This
sequence is shown in detail at Time Point B.
APPLICATIO S I FOR ATIO
WUUU
Low Side (Output) Overvoltage Protection
A Zener diode can be used in a similar fashion to detect/
protect the system against a supply overvoltage condition
on the load (or low) side of the pass transistor. In this case,
the Zener diode is connected from the load to the LTC4211’s
FILTER pin, as shown in Figure 25. An additional diode,
D1, prevents the FILTER pin from pulling low during an
output short-circuit. Figure 26 illustrates the timing dia-
gram for a low side output overvoltage condition. In this
example, the LTC4211 can only sense the overvoltage
supply condition after Time Point 5 and the GATE pin has
Figure 24. High Side Overvoltage Protection
1
VCC ON
TIMER
GATE
RESET
FILTER
>VREF – 80mV
FAULT
VOUT
GATE
VOUT
23 5672A 4 8 A B C
SLOW COMPARATOR ARMED
IF OVERVOLTAGE GOES
AWAY, SECOND CYCLE
CONTINUES
OVERVOLTAGE
IF ANY FAULT HAPPENS
AFTER THIS POINT, THE
CIRCUIT BREAKER TRIPS
AND FAULT LATCHES LOW
OVERVOLTAGE CIRCUIT BREAKER
TRIPS, GATE PULLS DOWN AND
FAULT LATCHES LOW
FAULT IS PULLED LOW (BUT NOT LATCHED)
DUE TO A START-UP OVERVOLTAGE PROBLEM
POWER GOOD
VFB > VREF
POWER BAD
VFB < VREF
FPD
4211 F24
>VREF
FAULT
LATCHED LOW
32
LTC4211
4211fa
APPLICATIO S I FOR ATIO
WUUU
Figure 25. LTC4211MS Low Side Overvoltage Protection Implementation
Figure 26. Low Side Overvoltage Protection
1
2
3
4
5
10
9
8
7
6
FAULT
VCC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Q1
Si4410DY
R1
36k
VOUT
5V
5A
R2
15k
CLOAD
4211 F25
RSENSE
0.007Ω
+
CTIMER
10nF
CFILTER
47pF
Z2
6.2V
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R4
10Ω
Z1* C1
0.1µF
R5
10k
R7
10k
R6
10k
R3
10k
Z1 = 1SMA10A OR SMAJ10A
Z2 = 1N4691
* OPTIONAL
D1
IN4148
12 34 5
CIRCUIT BREAKER TRIPSOVERVOLTAGE SENSED BY FILTER PIN
VCC
TIMER
GATE
VOUT
RESET
FILTER
ON
6A 6B
FAULT
FPD
4211 F26
VREF
33
LTC4211
4211fa
APPLICATIO S I FOR ATIO
WUUU
ramped up to its nominal operating value. After Time
Point 5, a supply voltage fault occurs at the load and the
Zener diode begins to conduct, causing V
FILTER
to in-
crease. At Time Point 6A, V
FILTER
is greater than 1.236V,
the circuit breaker is tripped, the GATE pin voltage is pulled
to ground and FAULT is asserted low and latched.
In either case, the LTC4211 can be configured to auto-
matically initiate a start-up sequence. Please refer to the
section on AutoRetry After a Fault for additional
information.
PCB Layout Considerations
For proper operation of the LTC4211’s circuit breaker
function, a 4-wire Kelvin connection to the sense resistors
is highly recommended. A recommended PCB layout for
the sense resistor, the power MOSFET and the GATE drive
components around the LTC4211 is illustrated in
Figure 22. In Hot Swap applications where load currents
can reach 10A or more, narrow PCB tracks exhibit more
resistance than wider tracks and operate at more elevated
temperatures. Since the sheet resistance of 1 ounce cop-
per foil is approximately 0.54mΩ/square, track resis-
tances add up quickly in high current applications. Thus,
to keep PCB track resistance and temperature rise to a
minimum, PCB track width must be appropriately sized.
Consult Appendix A of LTC Application Note 69 for details
on sizing and calculating trace resistances as a function of
copper thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
34
LTC4211
4211fa
APPE DIX
U
Table 4 lists some current sense resistors that can be used
with the circuit breaker. Table 5 lists some power MOSFETs
that are available. Table 6 lists the web sites of several
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
Table 4. Sense Resistor Selection Guide
CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER
1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT
2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT
2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT
3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale
5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT
10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale
Table 5. N-Channel Selection Guide
CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 2 MMDF3N02HD Dual N-Channel SO-8 ON Semiconductor
R
DS(ON)
= 0.1Ω, C
ISS
= 455pF
2 to 5 MMSF5N02HD Single N-Channel SO-8 ON Semiconductor
R
DS(ON)
= 0.025Ω, C
ISS
= 1130pF
5 to 10 MTB50N06V Single N-Channel DD Pak ON Semiconductor
R
DS(ON)
= 0.028Ω, C
ISS
= 1570pF
10 to 20 MTB75N05HD Single N-Channel DD Pak ON Semiconductor
R
DS(ON)
= 0.0095Ω, C
ISS
= 2600pF
Table 6. Manufacturers’ Web Sites
MANUFACTURER WEB SITE
TEMIC Semiconductor www.temic.com
International Rectifier www.irf.com
ON Semiconductor www.onsemi.com
Harris Semiconductor www.semi.harris.com
IRC-TT www.irctt.com
Vishay-Dale www.vishay.com
Vishay-Siliconix www.vishay.com
Diodes, Inc. www.diodes.com
35
LTC4211
4211fa
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MSOP (MS8) 0102
0.53 ± 0.015
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.077)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
(.005 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BCS
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.88 ± 0.1
(.192 ± .004)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
0.52
(.206)
REF
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
MSOP (MS) 1001
0.53 ± 0.01
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
0.86
(.034)
REF
0.50
(.0197)
TYP
12345
4.88 ± 0.10
(.192 ± .004)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
36
LTC4211
4211fa
LT 0906 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2006
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1421 Two Channels, Hot Swap Controller 24-Pin, Operates from 3V to 12V and Supports –12V
LTC1422 Single Channel, Hot Swap Controller 8-Pin, Operates from 2.7V to 12V
LT1640AL/LT1640AH Negative Voltage Hot Swap Controller 8-Pin, Operates from –10V to –80V
LT1641-1/LT1641-2 Positive Voltage Hot Swap Controller 8-Pin, Operates from 9V to 80V, Latch-Off/Auto Retry
LTC1642 Single Channel, Hot Swap Controller 16-Pin, Overvoltage Protection to 33V
LTC1644 PCI Hot Swap Controller 16-Pin, 3.3V, 5V and ±12V, 1V Precharge, PCI Reset Logic
LTC1647 Dual Channel, Hot Swap Controller 8-Pin, 16-Pin, Operates from 2.7V to 16.5V
LTC4230 Triple Hot Swap Controller with Multifunction Current Control Operates from 1.7V to 16.5V
TYPICAL APPLICATIO S
U
LOW COST OVERVOLTAGE PROTECTION
There is an alternative method to implementing the over-
voltage protection using a resistor divider at the FILTER
pin (see Figures 27 and 28). In this implementation, the
SLOW COMP is NULL in Normal Mode. Only the FAST
COMP circuit breaker is available and the current limit level
is 150mV/R
SENSE
. During the soft-cycle, the inrush cur-
rent servo loop is at 50mV/R
SENSE
. So, the heavy load
should only turn on at/after the end of second cycle where
the RESET pin goes high.
Figure 27. LTC4211MS High Side Overvoltage Protection Implementation
(In Normal Mode, SLOW COMP is Disabled, In Soft-Start Cycle, ISOFTSTART is Still 50mV/RSENSE)
Figure 28. LTC4211MS Low Side Overvoltage Protection Implementation
(In Normal Mode, SLOW COMP is Disabled, In Soft-Start Cycle, ISOFTSTART is Still 50mV/RSENSE)
1
2
3
4
5
10
9
8
7
6
FAULT
V
CC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Q1
Si4410DY
R1
36k
V
OUT
5V
5A
R2
15k
C
LOAD
4211 F29
R
SENSE
0.007Ω
+
C
TIMER
10nF
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R3
10Ω
Z1* C1
0.1µF
R5
10k
R6
10k
R8
4.3k
R7
10k
R9
750Ω
R4
10k
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
1
2
3
4
5
10
9
8
7
6
FAULT
V
CC
SENSE
GATE
FB
RESET
ON
FILTER
TIMER
GND
LTC4211
Q1
Si4410DY
R1
3.6k
V
OUT
5V
5A
R2
750Ω
C
LOAD
4211 F30
R
SENSE
0.007Ω
+
R8
750Ω
C
TIMER
10nF
LONG
5V
GND
FAULT
LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
SHORT
SHORT
SHORT
RESET
ON/OFF
R7
10Ω
Z1* C1
0.1µF
R4
10k
R6
10k
R5
10k
R3
10k
Z1 = 1SMA10A OR SMAJ10A
* OPTIONAL
