To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual 78K0/KF1 8-Bit Single-Chip Microcontrollers PD780143 PD780144 PD780146 PD780148 PD78F0148 PD780143(A) PD780144(A) PD780146(A) PD780148(A) PD78F0148(A) Document No. U15947EJ3V1UD00 (3rd edition) Date Published August 2005 N CP(K) (c) Printed in Japan PD780143(A1) PD780144(A1) PD780146(A1) PD780148(A1) PD78F0148(A1) PD780143(A2) PD780144(A2) PD780146(A2) PD780148(A2) [MEMO] 2 User's Manual U15947EJ3V1UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U15947EJ3V1UD 3 Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U15947EJ3V1UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 User's Manual U15947EJ3V1UD 5 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KF1 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KF1: PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1), 78F0148(A1), 780143(A2), 780144(A2), 780146(A2), and 780148(A2) Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KF1 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KF1 User's Manual (This Manual) 78K/0 Series Instructions User's Manual * Pin functions * CPU functions * Internal block functions * Instruction set * Interrupts * Explanation of each instruction * Other on-chip peripheral functions * Electrical specifications How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) grade products, (A1) grade products, and (A2) grade products: Only the quality grade differs between standard products and (A), (A1), and (A2) grade products. Read the part number as follows. * PD780143 PD780143(A), 780143(A1), 780143(A2) * * * * PD780144 PD780144(A), 780144(A1), 780144(A2) PD780146 PD780146(A), 780146(A1), 780146(A2) PD780148 PD780148(A), 780148(A1), 780148(A2) PD78F0148 PD78F0148(A), 78F0148(A1) * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark shows major revised points. * How to interpret the register format: For a bit number enclosed in brackets, the bit name is defined as a reserved word in the RA78K0, and is defined as the sfr variable by #pragma sfr directive in the CC78K0. 6 User's Manual U15947EJ3V1UD * To check the details of a register when you know the register name: See APPENDIX C REGISTER INDEX. * To know details of the 78K/0 Series instructions: Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). Caution Examples in this manual employ the "standard" quality grade for general electronics. When using examples in this manual for the "special" quality grade, review the quality grade of each part and/or circuit actually used. Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: xxx (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ... xxxx or xxxxB Numerical representations: Binary ... xxxx Decimal Hexadecimal ... xxxxH Differences Between 78K0/KF1 and 78K0/KF1+ Series Name 78K0/KF1 78K0/KF1+ Item Mask ROM version Available None Flash Power supply Two power supplies Single power supply memory version Self programming function None Available Option byte None Internal oscillator can be stopped/cannot be stopped selectable Product with on-chip debug function None Available Regulator Available None Power-on-clear function 2.85 V 0.15 V or 3.5 V 0.2 V selectable 2.1 V 0.1 V (fixed) Minimum instruction execution time 0.166 s (at 12 MHz operation) 0.125 s (at 16 MHz operation) User's Manual U15947EJ3V1UD 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/KF1 User's Manual This manual 78K0/KF1+ User's Manual U16819E 78K/0 Series Instructions User's Manual U12326E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Assembler Package CC78K0 C Compiler SM78K Series Ver. 2.52 System Simulator Document No. Operation U16629E Language U14446E Structured Assembly Language U11789E Operation U16613E Language U14298E Operation U16768E External Part User Open Interface U15802E Specifications ID78K0-NS Ver. 2.52 Integrated Debugger Operation U16488E ID78K0-QB Ver. 2.81 Integrated Debugger Operation U16996E PM plus Ver. 5.10 U16569E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name Document No. IE-78K0-NS In-Circuit Emulator U13731E IE-78K0-NS-A In-Circuit Emulator U14889E IE-78K0K1-ET In-Circuit Emulator U16604E QB-78K0KX1H In-Circuit Emulator U17081E IE-780148-NS-EM1 Emulation Board To be prepared Documents Related to Flash Memory Programming Document Name Document No. PG-FP3 Flash Memory Programmer User's Manual U13502E PG-FP4 Flash Memory Programmer User's Manual U15260E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 8 User's Manual U15947EJ3V1UD Other Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. User's Manual U15947EJ3V1UD 9 CONTENTS CHAPTER 1 OUTLINE............................................................................................................................. 18 1.1 Expanded-Specification Products and Conventional Products (Standard Products, (A) Grade Products Only) ..................................................................... 18 1.2 Features ..................................................................................................................................... 19 1.3 Applications .............................................................................................................................. 20 1.4 Ordering Information ................................................................................................................ 21 1.5 Pin Configuration (Top View)................................................................................................... 24 1.6 Kx1 Series Lineup..................................................................................................................... 26 1.7 1.8 1.6.1 78K0/Kx1, 78K0/Kx1+ product lineup........................................................................................... 26 1.6.2 V850ES/Kx1, V850ES/Kx1+ product lineup ................................................................................. 29 Block Diagram........................................................................................................................... 32 Outline of Functions ................................................................................................................. 33 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 36 2.1 Pin Function List....................................................................................................................... 36 2.2 Description of Pin Functions ................................................................................................... 40 2.3 2.2.1 P00 to P06 (port 0) ....................................................................................................................... 40 2.2.2 P10 to P17 (port 1) ....................................................................................................................... 41 2.2.3 P20 to P27 (port 2) ....................................................................................................................... 41 2.2.4 P30 to P33 (port 3) ....................................................................................................................... 42 2.2.5 P40 to P47 (port 4) ....................................................................................................................... 42 2.2.6 P50 to P57 (port 5) ....................................................................................................................... 42 2.2.7 P60 to P67 (port 6) ....................................................................................................................... 43 2.2.8 P70 to P77 (port 7) ....................................................................................................................... 43 2.2.9 P120 (port 12) .............................................................................................................................. 43 2.2.10 P130 (port 13) .............................................................................................................................. 43 2.2.11 P140 to P145 (port 14) ................................................................................................................. 44 2.2.12 AVREF ........................................................................................................................................... 44 2.2.13 AVSS ............................................................................................................................................ 44 2.2.14 RESET ......................................................................................................................................... 45 2.2.15 REGC........................................................................................................................................... 45 2.2.16 X1 and X2..................................................................................................................................... 45 2.2.17 XT1 and XT2 ................................................................................................................................ 45 2.2.18 VDD and EVDD .............................................................................................................................. 45 2.2.19 VSS and EVSS ............................................................................................................................... 45 2.2.20 VPP (flash memory versions only) ................................................................................................. 45 2.2.21 IC (mask ROM versions only)....................................................................................................... 45 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 46 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 50 3.1 Memory Space........................................................................................................................... 50 10 3.1.1 Internal program memory space................................................................................................... 56 3.1.2 Internal data memory space ......................................................................................................... 57 3.1.3 Special function register (SFR) area ............................................................................................ 57 3.1.4 Data memory addressing ............................................................................................................. 58 User's Manual U15947EJ3V1UD 3.2 3.3 3.4 Processor Registers................................................................................................................. 63 3.2.1 Control registers............................................................................................................................63 3.2.2 General-purpose registers ............................................................................................................67 3.2.3 Special function registers (SFRs)..................................................................................................68 Instruction Address Addressing............................................................................................. 73 3.3.1 Relative addressing.......................................................................................................................73 3.3.2 Immediate addressing...................................................................................................................74 3.3.3 Table indirect addressing ..............................................................................................................75 3.3.4 Register addressing ......................................................................................................................75 Operand Address Addressing................................................................................................. 76 3.4.1 Implied addressing ........................................................................................................................76 3.4.2 Register addressing ......................................................................................................................77 3.4.3 Direct addressing ..........................................................................................................................78 3.4.4 Short direct addressing .................................................................................................................79 3.4.5 Special function register (SFR) addressing...................................................................................80 3.4.6 Register indirect addressing..........................................................................................................81 3.4.7 Based addressing .........................................................................................................................82 3.4.8 Based indexed addressing............................................................................................................83 3.4.9 Stack addressing...........................................................................................................................84 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 85 4.1 Port Functions .......................................................................................................................... 85 4.2 Port Configuration .................................................................................................................... 87 4.3 4.4 4.2.1 Port 0 ............................................................................................................................................88 4.2.2 Port 1 ............................................................................................................................................92 4.2.3 Port 2 ............................................................................................................................................97 4.2.4 Port 3 ............................................................................................................................................98 4.2.5 Port 4 ..........................................................................................................................................100 4.2.6 Port 5 ..........................................................................................................................................101 4.2.7 Port 6 ..........................................................................................................................................102 4.2.8 Port 7 ..........................................................................................................................................105 4.2.9 Port 12 ........................................................................................................................................106 4.2.10 Port 13 ........................................................................................................................................107 4.2.11 Port 14 ........................................................................................................................................108 Registers Controlling Port Function..................................................................................... 112 Port Function Operations ...................................................................................................... 117 4.4.1 Writing to I/O port ........................................................................................................................117 4.4.2 Reading from I/O port..................................................................................................................117 4.4.3 Operations on I/O port.................................................................................................................117 CHAPTER 5 EXTERNAL BUS INTERFACE ...................................................................................... 118 5.1 External Bus Interface............................................................................................................ 118 5.2 Registers Controlling External Bus Interface...................................................................... 121 5.3 External Bus Interface Function Timing .............................................................................. 124 5.4 Example of Connection with Memory................................................................................... 129 CHAPTER 6 CLOCK GENERATOR .................................................................................................... 130 6.1 Functions of Clock Generator ............................................................................................... 130 User's Manual U15947EJ3V1UD 11 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Configuration of Clock Generator......................................................................................... 130 Registers Controlling Clock Generator ................................................................................ 132 System Clock Oscillator......................................................................................................... 139 6.4.1 X1 oscillator................................................................................................................................ 139 6.4.2 Subsystem clock oscillator ......................................................................................................... 139 6.4.3 When subsystem clock is not used ............................................................................................ 142 6.4.4 Internal oscillator ........................................................................................................................ 142 6.4.5 Prescaler .................................................................................................................................... 142 Clock Generator Operation .................................................................................................... 143 Time Required to Switch Between Internal Oscillation Clock and X1 Input Clock .......... 150 Time Required for CPU Clock Switchover ........................................................................... 151 Clock Switching Flowchart and Register Setting ................................................................ 152 6.8.1 Switching from internal oscillation clock to X1 input clock .......................................................... 152 6.8.2 Switching from X1 input clock to internal oscillation clock .......................................................... 153 6.8.3 Switching from X1 input clock to subsystem clock ..................................................................... 154 6.8.4 Switching from subsystem clock to X1 input clock ..................................................................... 155 6.8.5 Register settings......................................................................................................................... 156 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................... 157 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 ......................................................... 157 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01................................................... 158 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 .......................................... 163 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 ......................................................... 174 7.5 7.4.1 Interval timer operation............................................................................................................... 174 7.4.2 PPG output operations ............................................................................................................... 177 7.4.3 Pulse width measurement operations ........................................................................................ 180 7.4.4 External event counter operation................................................................................................ 188 7.4.5 Square-wave output operation ................................................................................................... 191 7.4.6 One-shot pulse output operation ................................................................................................ 193 Cautions for 16-Bit Timer/Event Counters 00 and 01.......................................................... 198 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 201 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 ........................................................... 201 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51..................................................... 203 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................ 205 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 ......................................................... 210 8.5 8.4.1 Operation as interval timer ......................................................................................................... 210 8.4.2 Operation as external event counter .......................................................................................... 212 8.4.3 Square-wave output operation ................................................................................................... 213 8.4.4 PWM output operation................................................................................................................ 214 Cautions for 8-Bit Timer/Event Counters 50 and 51............................................................ 218 CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 219 9.1 Functions of 8-Bit Timers H0 and H1.................................................................................... 219 9.2 Configuration of 8-Bit Timers H0 and H1 ............................................................................. 219 9.3 Registers Controlling 8-Bit Timers H0 and H1..................................................................... 223 9.4 Operation of 8-Bit Timers H0 and H1 .................................................................................... 229 9.4.1 12 Operation as interval timer/square-wave output ......................................................................... 229 User's Manual U15947EJ3V1UD 9.4.2 Operation as PWM output mode .................................................................................................232 9.4.3 Carrier generator mode operation (8-bit timer H1 only)...............................................................238 CHAPTER 10 WATCH TIMER ............................................................................................................. 245 10.1 Functions of Watch Timer ..................................................................................................... 245 10.2 Configuration of Watch Timer ............................................................................................... 247 10.3 Register Controlling Watch Timer ........................................................................................ 247 10.4 Watch Timer Operations ........................................................................................................ 249 10.4.1 Watch timer operation .................................................................................................................249 10.4.2 Interval timer operation ...............................................................................................................250 10.5 Cautions for Watch Timer...................................................................................................... 251 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 252 11.1 Functions of Watchdog Timer............................................................................................... 252 11.2 Configuration of Watchdog Timer ........................................................................................ 254 11.3 Registers Controlling Watchdog Timer................................................................................ 255 11.4 Operation of Watchdog Timer ............................................................................................... 258 11.4.1 Watchdog timer operation when "Internal oscillator cannot be stopped" is selected by mask option ............................................................................................................................258 11.4.2 Watchdog timer operation when "Internal oscillator can be stopped by software" is selected by mask option ..........................................................................................................259 11.4.3 Watchdog timer operation in STOP mode (when "Internal oscillator can be stopped by software" is selected by mask option).........................................................................................................260 11.4.4 Watchdog timer operation in HALT mode (when "Internal oscillator can be stopped by software" is selected by mask option).........................................................................................................262 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 263 12.1 Functions of Clock Output/Buzzer Output Controller ........................................................ 263 12.2 Configuration of Clock Output/Buzzer Output Controller .................................................. 264 12.3 Registers Controlling Clock Output/Buzzer Output Controller ......................................... 264 12.4 Clock Output/Buzzer Output Controller Operations ........................................................... 267 12.4.1 Clock output operation ................................................................................................................267 12.4.2 Operation as buzzer output.........................................................................................................267 CHAPTER 13 A/D CONVERTER ......................................................................................................... 268 13.1 Functions of A/D Converter................................................................................................... 268 13.2 Configuration of A/D Converter ............................................................................................ 269 13.3 Registers Used in A/D Converter .......................................................................................... 271 13.4 A/D Converter Operations ..................................................................................................... 277 13.4.1 Basic operations of A/D converter...............................................................................................277 13.4.2 Input voltage and conversion results...........................................................................................279 13.4.3 A/D converter operation mode ....................................................................................................280 13.5 How to Read A/D Converter Characteristics Table ............................................................. 283 13.6 Cautions for A/D Converter ................................................................................................... 285 CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 290 14.1 Functions of Serial Interface UART0 .................................................................................... 290 14.2 Configuration of Serial Interface UART0.............................................................................. 291 User's Manual U15947EJ3V1UD 13 14.3 Registers Controlling Serial Interface UART0 ..................................................................... 294 14.4 Operation of Serial Interface UART0..................................................................................... 299 14.4.1 Operation stop mode.................................................................................................................. 299 14.4.2 Asynchronous serial interface (UART) mode ............................................................................. 300 14.4.3 Dedicated baud rate generator................................................................................................... 306 CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 311 15.1 Functions of Serial Interface UART6 .................................................................................... 311 15.2 Configuration of Serial Interface UART6 .............................................................................. 315 15.3 Registers Controlling Serial Interface UART6 ..................................................................... 318 15.4 Operation of Serial Interface UART6..................................................................................... 326 15.4.1 Operation stop mode.................................................................................................................. 326 15.4.2 Asynchronous serial interface (UART) mode ............................................................................. 327 15.4.3 Dedicated baud rate generator................................................................................................... 342 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 349 16.1 Functions of Serial Interfaces CSI10 and CSI11 .................................................................. 349 16.2 Configuration of Serial Interfaces CSI10 and CSI11 ........................................................... 350 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11................................................... 352 16.4 Operation of Serial Interfaces CSI10 and CSI11 .................................................................. 358 16.4.1 Operation stop mode.................................................................................................................. 358 16.4.2 3-wire serial I/O mode ................................................................................................................ 359 CHAPTER 17 SERIAL INTERFACE CSIA0........................................................................................ 369 17.1 Functions of Serial Interface CSIA0...................................................................................... 369 17.2 Configuration of Serial Interface CSIA0 ............................................................................... 370 17.3 Registers Controlling Serial Interface CSIA0....................................................................... 372 17.4 Operation of Serial Interface CSIA0 ...................................................................................... 381 17.4.1 Operation stop mode.................................................................................................................. 381 17.4.2 3-wire serial I/O mode ................................................................................................................ 382 17.4.3 3-wire serial I/O mode with automatic transmit/receive function................................................. 387 CHAPTER 18 MULTIPLIER/DIVIDER ................................................................................................... 409 18.1 Functions of Multiplier/Divider .............................................................................................. 409 18.2 Configuration of Multiplier/Divider........................................................................................ 409 18.3 Register Controlling Multiplier/Divider ................................................................................. 414 18.4 Operations of Multiplier/Divider ............................................................................................ 415 18.4.1 Multiplication operation............................................................................................................... 415 18.4.2 Division operation....................................................................................................................... 417 CHAPTER 19 INTERRUPT FUNCTIONS............................................................................................. 419 19.1 Interrupt Function Types........................................................................................................ 419 19.2 Interrupt Sources and Configuration.................................................................................... 419 19.3 Registers Controlling Interrupt Functions ........................................................................... 423 19.4 Interrupt Servicing Operations.............................................................................................. 430 14 19.4.1 Maskable interrupt request acknowledgement ........................................................................... 430 19.4.2 Software interrupt request acknowledgment .............................................................................. 432 19.4.3 Multiple interrupt servicing.......................................................................................................... 433 User's Manual U15947EJ3V1UD 19.4.4 Interrupt request hold ..................................................................................................................436 CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 437 20.1 Functions of Key Interrupt..................................................................................................... 437 20.2 Configuration of Key Interrupt .............................................................................................. 437 20.3 Register Controlling Key Interrupt........................................................................................ 438 CHAPTER 21 STANDBY FUNCTION.................................................................................................. 439 21.1 Standby Function and Configuration ................................................................................... 439 21.1.1 Standby function .........................................................................................................................439 21.1.2 Registers controlling standby function.........................................................................................440 21.2 Standby Function Operation ................................................................................................. 443 21.2.1 HALT mode .................................................................................................................................443 21.2.2 STOP mode ................................................................................................................................448 CHAPTER 22 RESET FUNCTION ....................................................................................................... 452 22.1 Register for Confirming Reset Source ................................................................................. 459 CHAPTER 23 CLOCK MONITOR ........................................................................................................ 460 23.1 Functions of Clock Monitor ................................................................................................... 460 23.2 Configuration of Clock Monitor............................................................................................. 460 23.3 Register Controlling Clock Monitor ...................................................................................... 461 23.4 Operation of Clock Monitor ................................................................................................... 462 CHAPTER 24 POWER-ON-CLEAR CIRCUIT ..................................................................................... 467 24.1 Functions of Power-on-Clear Circuit .................................................................................... 467 24.2 Configuration of Power-on-Clear Circuit ............................................................................. 468 24.3 Operation of Power-on-Clear Circuit .................................................................................... 468 24.4 Cautions for Power-on-Clear Circuit .................................................................................... 469 CHAPTER 25 LOW-VOLTAGE DETECTOR ....................................................................................... 471 25.1 Functions of Low-Voltage Detector ...................................................................................... 471 25.2 Configuration of Low-Voltage Detector................................................................................ 472 25.3 Registers Controlling Low-Voltage Detector....................................................................... 472 25.4 Operation of Low-Voltage Detector ...................................................................................... 475 25.5 Cautions for Low-Voltage Detector ...................................................................................... 479 CHAPTER 26 REGULATOR ................................................................................................................. 483 26.1 Outline of Regulator ............................................................................................................... 483 CHAPTER 27 MASK OPTIONS ........................................................................................................... 485 CHAPTER 28 PD78F0148................................................................................................................... 486 28.1 Internal Memory Size Switching Register ............................................................................ 487 28.2 Internal Expansion RAM Size Switching Register .............................................................. 488 28.3 Writing with Flash Programmer ............................................................................................ 489 28.4 Programming Environment ................................................................................................... 496 28.5 Communication Mode ............................................................................................................ 496 User's Manual U15947EJ3V1UD 15 28.6 Processing of Pins on Board................................................................................................. 500 28.6.1 VPP pin........................................................................................................................................ 500 28.6.2 Serial interface pins.................................................................................................................... 501 28.6.3 RESET pin.................................................................................................................................. 503 28.6.4 Port pins ..................................................................................................................................... 503 28.6.5 REGC pin ................................................................................................................................... 503 28.6.6 Other signal pins ........................................................................................................................ 503 28.6.7 Power supply.............................................................................................................................. 503 28.7 Programming Method............................................................................................................. 504 28.7.1 Controlling flash memory............................................................................................................ 504 28.7.2 Flash memory programming mode............................................................................................. 505 28.7.3 Selecting communication mode.................................................................................................. 505 28.7.4 Communication commands ........................................................................................................ 506 CHAPTER 29 INSTRUCTION SET....................................................................................................... 507 29.1 Conventions Used in Operation List..................................................................................... 507 29.1.1 Operand identifiers and specification methods........................................................................... 507 29.1.2 Description of operation column ................................................................................................. 508 29.1.3 Description of flag operation column .......................................................................................... 508 29.2 Operation List.......................................................................................................................... 509 29.3 Instructions Listed by Addressing Type .............................................................................. 517 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) ...................................... 520 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS)........................................................... 545 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) ................................ 570 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) ................................ 591 CHAPTER 34 PACKAGE DRAWINGS ................................................................................................ 607 CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS........................................................... 609 CHAPTER 36 CAUTIONS FOR WAIT................................................................................................. 612 36.1 Cautions for Wait .................................................................................................................... 612 36.2 Peripheral Hardware That Generates Wait ........................................................................... 613 36.3 Example of Wait Occurrence ................................................................................................. 614 APPENDIX A DEVELOPMENT TOOLS............................................................................................... 615 A.1 Software Package ................................................................................................................... 619 A.2 Language Processing Software ............................................................................................ 619 A.3 Control Software ..................................................................................................................... 620 A.4 Flash Memory Writing Tools.................................................................................................. 620 A.5 Debugging Tools (Hardware)................................................................................................. 621 A.5.1 16 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A............................................... 621 User's Manual U15947EJ3V1UD A.6 A.5.2 When using in-circuit emulator IE-78K0K1-ET ............................................................................622 A.5.3 When using in-circuit emulator QB-78K0KX1H ...........................................................................623 Debugging Tools (Software).................................................................................................. 624 APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 625 B.1 When Using IE-78K0-NS, IE-78K0-NS-A, or IE-78K0K1-ET................................................. 625 B.2 When Using QB-78K0KX1H ................................................................................................... 630 APPENDIX C REGISTER INDEX......................................................................................................... 631 C.1 Register Index (In Alphabetical Order with Respect to Register Names)......................... 631 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................ 635 APPENDIX D LIST OF CAUTIONS..................................................................................................... 639 APPENDIX E REVISION HISTORY ..................................................................................................... 662 E.1 Major Revisions in This Edition ............................................................................................ 662 E.2 Revision History up to Previous Edition .............................................................................. 664 User's Manual U15947EJ3V1UD 17 CHAPTER 1 OUTLINE 1.1 Expanded-Specification Products and Conventional Products (Standard Products, (A) Grade Products Only) The expanded-specification products and conventional products refer to the following products. Expanded-specification products: Products with a rankNote E or after * Mask ROM version for which order was received on or after the end of May 2004 * Flash memory version for which order was received on or after the end of August 2004 Conventional products: Note Products with rankNote I or K * Products other than the above expanded-specification products The rank is indicated by the 5th digit from the left in the 3rd column (lot number) marked on the package. xxxx Lot number Year Week code code Rank Expanded-specification products and conventional products of standard products and (A) grade products differ in operating frequency ratings. The differences are shown in Table 1-1. Table 1-1. Differences Between Expanded-Specification Products and Conventional Products of Standard Products and (A) Grade Products Guaranteed Operating Speed (Minimum Instruction Supply Voltage (VDD) Conventional Products (Rank: I, K) Expanded-Specification Products Execution Time) (Rank: E or After) 12 MHz (0.166 s) Not used 4.0 to 5.5 V 10 MHz (0.2 s) 4.0 to 5.5 V 3.5 to 4.0 V 8.38 MHz (0.238 s) 3.3 to 4.0 V 3.0 to 3.5 V 5 MHz (0.4 s) 2.7 to 3.3 V 2.5 to 3.0 V Cautions 1. The specifications of the peripheral functions (timer, serial interface, A/D converter, etc.) are conventional when operating at VDD = 2.7 to 5.5 V. Therefore, to select the count clock or base clock of a peripheral function, satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock or base clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock or base clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock or base clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock or base clock 2.5 MHz 2. Rewrite the flash memory in the ranges of fX = 2 to 10 MHz and VDD = 2.7 to 5.5 V as ever. 18 User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE 1.2 Features { Minimum instruction execution time can be changed from high speed (0.166 s: @ 12 MHz operation with X1 input clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) { General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) { ROM, RAM capacities Item Program Memory Data Memory (ROM) Internal High-Speed Part Number PD780143 Mask ROM 32 KB PD780146 48 KB PD780148 60 KB Flash memory - 1024 bytes 24 KB PD780144 PD78F0148 Internal Expansion RAM RAM 1024 bytes Note Note 1024 bytes 60 KB Note The internal flash memory and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). { Buffer RAM: 32 bytes (can be used for transfer in 3-wire serial I/O mode with automatic transmit/receive function) { External memory expansion space: 64 KB (with external bus interface function) { On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) { Short startup is possible via the CPU default start using internal oscillator { On-chip clock monitor function using internal oscillator { On-chip watchdog timer (operable with internal oscillation clock) { On-chip multiplier/divider { On-chip key interrupt function { On-chip clock output/buzzer output controller { On-chip regulator { I/O ports: 67 (N-ch open drain: 4) { Timer PD780143, 780144: 7 channels PD780146, 780148, 78F0148: 8 channels { Serial interface PD780143, 780144: 3 channels Note (UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UART : 1 channel, CSI with automatic transmit/receive function: 1 channel) PD780146, 780148, 78F0148: 4 channels Note (UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI: 1 channel, CSI/UART : 1 channel, CSI with automatic transmit/receive function: 1 channel) { 10-bit resolution A/D converter: 8 channels Note Select either of the functions of these alternate-function pins. User's Manual U15947EJ3V1UD 19 CHAPTER 1 OUTLINE { Supply voltage: VDD = 2.5 to 5.5 VNotes 1, 2 (expanded-specification products of standard products and (A) grade products) Notes 1, 2 VDD = 2.7 to 5.5 V (conventional products of standard products and (A) grade products) VDD = 3.3 to 5.5 VNote 2 ((A1) grade products, (A2) grade products) { Operating ambient temperature: TA = -40 to +85C (standard product, (A) grade product) TA = -40 to +105C (flash memory version of (A1) grade product) TA = -40 to +110C (mask ROM version of (A1) grade product) TA = -40 to +125C (mask ROM version of (A2) grade product) Notes 1. Use the product in a voltage range of 3.0 to 5.5 V when the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.85 V 0.15 V. 2. Use the product in a voltage range of 3.7 to 5.5 V when the detection voltage (VPOC) of the power-onclear (POC) circuit is 3.5 V 0.2 V. 1.3 Applications { Automotive equipment * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control { Home audio, car audio { AV equipment { PC peripheral equipment (keyboards, etc.) { Household electrical appliances * Outdoor air conditioner units * Microwave ovens, electric rice cookers { Industrial equipment * Pumps * Vending machines * FA (Factory Automation) 20 User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE 1.4 Ordering Information (1) Mask ROM versions Part Number PD780143GK-xxx-9EU PD780143GC-xxx-8BT PD780144GK-xxx-9EU PD780144GC-xxx-8BT PD780146GK-xxx-9EU PD780146GC-xxx-8BT PD780148GK-xxx-9EU PD780148GC-xxx-8BT PD780143GK-xxx-9EU-A PD780143GC-xxx-8BT-A PD780144GK-xxx-9EU-A PD780144GC-xxx-8BT-A PD780146GK-xxx-9EU-A PD780146GC-xxx-8BT-A PD780148GK-xxx-9EU-A PD780148GC-xxx-8BT-A PD780143GK(A)-xxx-9EU PD780143GC(A)-xxx-8BT PD780144GK(A)-xxx-9EU PD780144GC(A)-xxx-8BT PD780146GK(A)-xxx-9EU PD780146GC(A)-xxx-8BT PD780148GK(A)-xxx-9EU PD780148GC(A)-xxx-8BT PD780143GK(A1)-xxx-9EU PD780143GC(A1)-xxx-8BT PD780144GK(A1)-xxx-9EU PD780144GC(A1)-xxx-8BT PD780146GK(A1)-xxx-9EU PD780146GC(A1)-xxx-8BT PD780148GK(A1)-xxx-9EU PD780148GC(A1)-xxx-8BT PD780143GK(A2)-xxx-9EU PD780143GC(A2)-xxx-8BT PD780144GK(A2)-xxx-9EU PD780144GC(A2)-xxx-8BT PD780146GK(A2)-xxx-9EU PD780146GC(A2)-xxx-8BT PD780148GK(A2)-xxx-9EU PD780148GC(A2)-xxx-8BT Package Quality Grade 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special Remarks 1. xxx indicates ROM code suffix. 2. Products that have the part numbers suffixed by "-A" are lead-free products. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U15947EJ3V1UD 21 CHAPTER 1 OUTLINE (2) Flash memory versions Part Number Package PD78F0148M1GK-9EU PD78F0148M1GC-8BT PD78F0148M2GK-9EU PD78F0148M2GC-8BT PD78F0148M3GK-9EU PD78F0148M3GC-8BT PD78F0148M4GK-9EU PD78F0148M4GC-8BT PD78F0148M5GK-9EU PD78F0148M5GC-8BT PD78F0148M6GK-9EU PD78F0148M6GC-8BT PD78F0148M1GK-9EU-A PD78F0148M1GC-8BT-A PD78F0148M2GK-9EU-A PD78F0148M2GC-8BT-A PD78F0148M3GK-9EU-A PD78F0148M3GC-8BT-A PD78F0148M4GK-9EU-A PD78F0148M4GC-8BT-A PD78F0148M5GK-9EU-A PD78F0148M5GC-8BT-A PD78F0148M6GK-9EU-A PD78F0148M6GC-8BT-A PD78F0148M1GK(A)-9EU PD78F0148M1GC(A)-8BT PD78F0148M2GK(A)-9EU PD78F0148M2GC(A)-8BT PD78F0148M3GK(A)-9EU PD78F0148M3GC(A)-8BT PD78F0148M4GK(A)-9EU PD78F0148M4GC(A)-8BT PD78F0148M5GK(A)-9EU PD78F0148M5GC(A)-8BT PD78F0148M6GK(A)-9EU PD78F0148M6GC(A)-8BT PD78F0148M1GK(A1)-9EU PD78F0148M1GC(A1)-8BT PD78F0148M2GK(A1)-9EU PD78F0148M2GC(A1)-8BT PD78F0148M5GK(A1)-9EU PD78F0148M5GC(A1)-8BT PD78F0148M6GK(A1)-9EU PD78F0148M6GC(A1)-8BT 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Standard Standard Remark Quality Grade 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Standard Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Standard Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Standard Standard 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Standard Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Standard Standard 80-pin plastic QFP (14 x 14) Standard 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Standard Standard 80-pin plastic TQFP (fine pitch) (12 x 12) Standard 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Standard Special Special 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Special Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Special Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Special Special Special 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Special Special Special 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Special Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special 80-pin plastic TQFP (fine pitch) (12 x 12) Special 80-pin plastic QFP (14 x 14) Special Products that have the part numbers suffixed by "-A" are lead-free products. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. 22 User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE Mask ROM versions (PD780143, 780144, 780146, and 780148) include mask options. When ordering, it is possible to select "Power-on-clear (POC) circuit can be used/cannot be used", "Internal oscillator can be stopped/cannot be stopped by software" and "Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63)". Flash memory versions corresponding to the mask options of the mask ROM versions are as follows. Table 1-2. Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions Flash Memory Versions Mask Option POC Circuit POC cannot be used POC used Cannot be stopped PD78F0148M1GK-9EU PD78F0148M1GC-8BT PD78F0148M1GK-9EU-A PD78F0148M1GC-8BT-A PD78F0148M1GK(A)-9EU PD78F0148M1GC(A)-8BT PD78F0148M1GK(A1)-9EU PD78F0148M1GC(A1)-8BT Can be stopped by software PD78F0148M2GK-9EU PD78F0148M2GC-8BT PD78F0148M2GK-9EU-A PD78F0148M2GC-8BT-A PD78F0148M2GK(A)-9EU PD78F0148M2GC(A)-8BT PD78F0148M2GK(A1)-9EU PD78F0148M2GC(A1)-8BT Cannot be stopped PD78F0148M3GK-9EU PD78F0148M3GC-8BT PD78F0148M3GK-9EU-A PD78F0148M3GC-8BT-A PD78F0148M3GK(A)-9EU PD78F0148M3GC(A)-8BT Can be stopped by software PD78F0148M4GK-9EU PD78F0148M4GC-8BT PD78F0148M4GK-9EU-A PD78F0148M4GC-8BT-A PD78F0148M4GK(A)-9EU PD78F0148M4GC(A)-8BT Cannot be stopped PD78F0148M5GK-9EU PD78F0148M5GC-8BT PD78F0148M5GK-9EU-A PD78F0148M5GC-8BT-A PD78F0148M5GK(A)-9EU PD78F0148M5GC(A)-8BT PD78F0148M5GK(A1)-9EU PD78F0148M5GC(A1)-8BT Can be stopped by software PD78F0148M6GK-9EU PD78F0148M6GC-8BT PD78F0148M6GK-9EU-A PD78F0148M6GC-8BT-A PD78F0148M6GK(A)-9EU PD78F0148M6GC(A)-8BT PD78F0148M6GK(A1)-9EU PD78F0148M6GC(A1)-8BT (VPOC = 2.85 V 0.15 V) POC used (Part Number) Internal Oscillator (VPOC = 3.5 V 0.2 V) User's Manual U15947EJ3V1UD 23 CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) * 80-pin plastic TQFP (fine pitch) (12 x 12) P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P70/KR0 P71/KR1 P72/KR2 P73/KR3 P74/KR4 P75/KR5 P76/KR6 P77/KR7 P40/AD0 P41/AD1 P42/AD2 P43/AD3 * 80-pin plastic QFP (14 x 14) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVREF AVSS P120/INTP0 P33/TI51/TO51/INTP4 P32/INTP3 P31/INTP2 P30/INTP1 IC (VPP) VDD REGC VSS X1 X2 RESET XT1 XT2 P130 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P00/TI000 P01/TI010/TO00 P02/SO11Note P03/SI11Note P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P140/PCL/INTP6 P141/BUZ/BUSY0/INTP7 P63 P62 EVSS EVDD P61 P60 P142/SCKA0 P143/SIA0 P144/SOA0 P145/STB0 P06/TI011Note/TO01Note P05/SSI11Note/TI001Note P04/SCK11Note 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVSS pin to VSS. 3. Connect the REGC pin as follows. Standard Product and (A) Grade Product When regulator is used Connect to VSS via a capacitor (1 F: recommended) When regulator is not used Connect directly to VDD 4. Connect the VPP pin to EVSS or VSS during normal operation. Remark 24 Figures in parentheses apply only to the PD78F0148. User's Manual U15947EJ3V1UD (A1) Grade Product and (A2) Grade Product - (Regulator cannot be used.) CHAPTER 1 OUTLINE Pin Identification A8 to A15: Address bus REGC: Regulator capacitance AD0 to AD7: Address/data bus RESET: Reset ANI0 to ANI7: Analog input RxD0, RxD6: Receive data ASTB: Address strobe RD: Read strobe AVREF: Analog reference voltage SCK10, SCK11Note, AVSS: Analog ground SCKA0: Serial clock input/output Note BUSY0: Serial busy input SI10, SI11 BUZ: Buzzer output SO10, SO11Note, EVDD: Power supply for port SOA1: Serial data output EVSS: Ground for port SSI11Note: Serial interface chip select input IC: Internally connected STB0: Serial strobe , SIA0: INTP0 to INTP7: External interrupt input TI000, TI010, KR0 to KR7: Key return TI001Note, TI011Note, P00 to P06: Port 0 TI50, TI51: Serial data input Timer input Note P10 to P17: Port 1 TO00, TO01 P20 to P27: Port 2 TO50, TO51, P30 to P33: Port 3 TOH0, TOH1: Timer output P40 to P47: Port 4 TxD0, TxD6: Transmit data P50 to P57: Port 5 VDD: Power supply P60 to P67: Port 6 VPP: Programming power supply P70 to P77: Port 7 VSS: Ground P120: Port 12 WAIT: Wait P130: Port 13 WR: Write strobe P140 to P145: Port 14 X1, X2: Crystal oscillator (X1 input clock) PCL: Programmable clock output XT1, XT2: Crystal oscillator (Subsystem clock) , Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ3V1UD 25 CHAPTER 1 OUTLINE 1.6 1.6.1 Kx1 Series Lineup 78K0/Kx1, 78K0/Kx1+ product lineup * 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 PD78F0103 Two-power-supply flash memory: 24 KB, RAM: 768 B 78K0/KB1+ PD780103 Mask ROM: 24 KB, RAM: 768 B Single-power-supply flash memory: 24 KB, RAM: 768 B PD780102 Mask ROM: 16 KB, RAM: 768 B PD78F0102H Single-power-supply flash memory: 16 KB, RAM: 768 B PD780101 Mask ROM: 8 KB, RAM: 512 B PD78F0103H PD78F0101H Single-power-supply flash memory: 8 KB, RAM: 512 B * 44-pin LQFP (10 x 10 mm 0.8 mm pitch) 78K0/KC1 PD78F0114 Two-power-supply flash memory: 32 KB, RAM: 1 KB 78K0/KC1+ PD780114 Mask ROM: 32 KB, RAM: 1 KB PD780113 Mask ROM: 24 KB, RAM: 1 KB PD780112 Mask ROM: 16 KB, RAM: 512 B PD78F0114H/HDNote Single-power-supply flash memory: 32 KB, RAM: 1 KB PD78F0113H Single-power-supply flash memory: 24 KB, RAM: 1 KB PD78F0112H Single-power-supply flash memory: 16 KB, RAM: 512 B PD780111 Mask ROM: 8 KB, RAM: 512 B * 52-pin LQFP (10 x 10 mm 0.65 mm pitch) 78K0/KD1 PD78F0124 Two-power-supply flash memory: 32 KB, RAM: 1 KB 78K0/KD1+ PD780124 Mask ROM: 32 KB, RAM: 1 KB PD780123 Mask ROM: 24 KB, RAM: 1 KB PD780122 Mask ROM: 16 KB, RAM: 512 B PD78F0124H/HDNote Single-power-supply flash memory: 32 KB, RAM: 1 KB PD78F0123H Single-power-supply flash memory: 24 KB, RAM: 1 KB PD78F0122H Single-power-supply flash memory: 16 KB, RAM: 512 B PD780121 Mask ROM: 8 KB, RAM: 512 B * 64-pin LQFP, TQFP (10 x 10 mm 0.5 mm pitch, 12 x 12 mm 0.65 mm pitch, 14 x 14 mm 0.8 mm pitch) 78K0/KE1 PD78F0138 Two-power-supply flash memory: 60 KB, RAM: 2 KB PD78F0134 Two-power-supply flash memory: 32 KB, RAM: 1 KB 78K0/KE1+ PD780138 PD78F0138H/HDNote Mask ROM: 60 KB, RAM: 2 KB Single-power-supply flash memory: 60 KB, RAM: 2 KB PD780136 Mask ROM: 48 KB, RAM: 2 KB PD78F0136H Single-power-supply flash memory: 48 KB, RAM: 2 KB PD780134 PD78F0134H Mask ROM: 32 KB, RAM: 1 KB Single-power-supply flash memory: 32 KB, RAM: 1 KB PD780133 Mask ROM: 24 KB, RAM: 1 KB Single-power-supply flash memory: 24 KB, RAM: 1 KB PD780132 Mask ROM: 16 KB, RAM: 512 B PD78F0133H PD78F0132H Single-power-supply flash memory: 16 KB, RAM: 512 B PD780131 Mask ROM: 8 KB, RAM: 512 B * 80-pin TQFP, QFP (12 x 12 mm 0.5 mm pitch, 14 x 14 mm 0.65 mm pitch) 78K0/KF1 PD78F0148 Two-power-supply flash memory: 60 KB, RAM: 2 KB 78K0/KF1+ PD780148 Mask ROM: 60 KB, RAM: 2 KB PD78F0148H/HDNote Single-power-supply flash memory: 60 KB, RAM: 2 KB PD780146 Mask ROM: 48 KB, RAM: 2 KB PD780144 Mask ROM: 32 KB, RAM: 1 KB PD780143 Mask ROM: 24 KB, RAM: 1 KB Note Product with on-chip debug function 26 User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number Item Number of pins Internal Mask ROM memory (KB) Flash memory RAM Power supply voltage Minimum instruction execution time X1 input Subclock Internal oscillation Port CMOS I/O CMOS input CMOS output N-ch open-drain I/O Timer 16 bits (TM0) 8 bits (TM5) 8 bits (TMH) For watch WDT Note 3 Serial 3-wire CSI interface Automatic transmit/ receive 3-wire CSI Note 3 UART UART supporting LIN-bus 10-bit A/D converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT Clock output/buzzer output 78K0/KB1 8 78K0/KC1 30 pins - 16/ 24 - 24 0.75 0.5 8/ 16 78K0/KD1 44 pins 24/ - 32 - 32 0.5 1 0.166 s (when 12 MHz, VDD = 4.0 to 5.5 V) 0.2 s (when 10 MHz, VDD = 3.5 to 5.5 V) 0.238 s (when 8.38 MHz, VDD = 3.0 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.5 to 5.5 V) 8/ 16 Multiplier/divider ROM correction Standby function Operating ambient temperature 24/ 32 64 pins - 48/ 60 2 to 12 MHz 32.768 kHz 240 kHz (TYP.) 26 38 8 1 4 2 ch 2 ch 2 ch 1 ch 1 ch 2 ch - - 19 - 1 ch 1 ch - 1 ch - 4 ch 6 11 12 - 8/ 16 78K0/KF1 - 24/ 32 80 pins 48/ - 60 - - - - 32 32 60 0.5 1 0.5 1 2 1 Notes 1, 2 VDD = 2.5 to 5.5 V <Connect REGC pin to VDD> 0.166 s (when 12 MHz, VDD = 4.0 to 5.5 V) 0.2 s (when 10 MHz, VDD = 3.5 to 5.5 V) 0.238 s (when 8.38 MHz, VDD = 3.0 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.5 to 5.5 V) Clock 17 4 52 pins 24/ - 32 78K0/KE1 60 2 54 1 ch 2 ch 1 ch 2 ch 1 ch 1 ch 1 ch 8 ch 7 8 15 4 ch 9 16 19 8 ch 9 17 20 Provided 2.85 V 0.15 V/3.5 V 0.20 V (selectable by mask option) 2.85 V/3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided - Clock output Provided only - 16 bits x 16 bits, 32 bits / 16 bits - - Provided HALT/STOP mode Standard products, special (A) grade products: -40 to +85C Special (A1) grade products: -40 to +110C (mask ROM version), -40 to +105C (flash memory version) Special (A2) grade products: -40 to +125C (mask ROM version) Notes 1. Use the product in a voltage range of 3.0 to 5.5 V when the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.85 V 0.15 V. 2. Use the product in a voltage range of 3.7 to 5.5 V when the detection voltage (VPOC) of the power-on-clear (POC) circuit is 3.5 V 0.2 V. 3. Select either of the functions of these alternate-function pins. User's Manual U15947EJ3V1UD 27 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+ 30 pins 44 pins 52 pins 64 pins 80 pins Item Number of pins Internal memory (KB) Flash memory RAM 8 16/24 16 24/32 16 24/32 16 24/32 48/60 0.5 0.75 0.5 1 0.5 1 0.5 1 2 Power supply voltage Minimum instruction execution time Clock VDD = 2.5 to 5.5 V (with internal oscillation clock or subclock: VDD = 2.0 to 5.5 V - 3 to 4 MHz - Subclock 32.768 kHz Internal oscillation 240 kHz (TYP.) CMOS I/O 17 CMOS input 4 19 26 4 1 ch 8 bits (TM5) 2 ch 1 ch 2 ch 8 bits (TMH) 2 ch - For watch 1 ch WDT 1 ch Note 2 Serial 3-wire CSI interface Automatic transmit/ receive 3-wire CSI Note 2 UART 1 ch 2 ch - 1 ch - 1 ch UART supporting LIN-bus 1 ch 10-bit A/D converter 4 ch Interrupts External 6 Internal Key return input 11 8 ch 7 12 - 2.35 V/2.6 V/2.85 V/3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided - Clock output only - External bus interface ROM correction Self-programming function Product with on-chip debug function Standby function Operating ambient temperature 28 20 8 ch Clock monitor Multiplier/divider 9 19 Provided 2.1 V 0.1 V (detection voltage is fixed) WDT Clock output/buzzer output 9 16 4 ch POC LVI 8 15 RESET pin 2. 54 1 - 16 bits (TM0) Notes 1. 38 8 CMOS output N-ch open-drain I/O Reset ) 2 to 16 MHz RC Timer 2 Note 1 0.125 s (when 16 MHz, VDD = 4.0 to 5.5 V) 0.2 s (when 10MHz, VDD = 3.5 to 5.5 V) 0.238 s (when 8.38 MHz, VDD = 3.0 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.5 to 5.5 V) Crystal/ceramic Port 60 - Provided Provided 16 bits x 16 bits, 32 bits / 16 bits - Provided - Provided PD78F0114HD, 78F0124HD, 78F0138HD, 78F0148HD HALT/STOP mode TA = -40 to +85C Use the product in a voltage range of 2.2 to 5.5 V when the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.1 V 0.1 V. Select either of the functions of these alternate-function pins. User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE 1.6.2 V850ES/Kx1, V850ES/Kx1+ product lineup * 64-pin plastic LQFP (10 x 10 mm, 0.5 mm pitch) * 64-pin plastic TQFP (12 x 12 mm, 0.65 mm pitch) * 64-pin plastic LQFP (14 x 14 mm, 0.8 mm pitch) V850ES/KE1 PD70F3207HY PD70F3207H Single-power-supply flash memory: 128 KB, RAM: 4 KB V850ES/KE1+ PD703207Y PD703207 Mask ROM: 128 KB, RAM: 4 KB PD703206Y PD70F3302Y PD703302Y PD70F3302 Single-power-supply flash memory: 128 KB, RAM: 4 KB PD703302 Mask ROM: 128 KB, RAM: 4 KB PD703301Y PD703206 PD703301 Mask ROM: 96 KB, RAM: 4 KB Mask ROM: 96 KB, RAM: 4 KB * 80-pin plastic TQFP (12 x 12 mm, 0.5 mm pitch) * 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) V850ES/KF1 PD70F3211HY PD70F3211H Single-power-supply flash memory: 256 KB, RAM: 12 KB PD70F3210HY PD70F3210H Single-power-supply flash memory: 128 KB, RAM: 6 KB PD70F3210Y PD70F3210 Two-power-supply flash memory: 128 KB, RAM: 6 KB V850ES/KF1+ PD703211Y PD703211 Mask ROM: 256 KB, RAM: 12 KB PD703210Y PD703210 Mask ROM: 128 KB, RAM: 4 KB PD703209Y PD70F3308Y PD703308Y PD703308 PD70F3308 Single-power-supply flash memory: 256 KB, RAM: 12 KB Mask ROM: 256 KB, RAM: 12 KB PD70F3306Y PD70F3306 Single-power-supply flash memory: 128 KB, RAM: 6 KB PD703209 Mask ROM: 96 KB, RAM: 4 KB PD703208Y PD703208 Mask ROM: 64 KB, RAM: 4 KB * 100-pin plastic LQFP (14 x 14 mm, 0.5 mm pitch) * 100-pin plastic QFP (14 x 20 mm, 0.65 mm pitch) V850ES/KG1 PD70F3215HY PD70F3215H Single-power-supply flash memory: 256 KB, RAM: 16 KB PD70F3214HY PD70F3214H Single-power-supply flash memory: 128 KB, RAM: 6 KB PD70F3214Y PD70F3214 Two-power-supply flash memory: 128 KB, RAM: 6 KB V850ES/KG1+ PD703215Y PD703215 Mask ROM: 256 KB, RAM: 16 KB PD703214Y PD703214 Mask ROM: 128 KB, RAM: 6 KB PD703213Y PD703313Y PD70F3313Y PD70F3313 Single-power-supply flash memory: 256 KB, RAM: 16 KB PD703313 Mask ROM: 256 KB, RAM: 16 KB PD70F3311Y PD70F3311 Single-power-supply flash memory: 128 KB, RAM: 6 KB PD703213 Mask ROM: 96 KB, RAM: 4 KB PD703212Y PD703212 Mask ROM: 64 KB, RAM: 4 KB * 144-pin plastic LQFP (20 x 20 mm, 0.5 mm pitch) V850ES/KJ1 PD70F3218HY PD70F3218H Single-power-supply flash memory: 256 KB, RAM: 16 KB V850ES/KJ1+ PD703218Y PD703218 Mask ROM: 256 KB, RAM: 16 KB PD70F3217HY PD703217Y PD70F3217H PD703217 Single-power-supply flash memory: 128 KB, RAM: 6 KB PD70F3217Y PD70F3217 Two-power-supply flash memory: 128 KB, RAM: 6 KB Mask ROM: 128 KB, RAM: 6 KB PD703216Y PD703318Y PD70F3318Y PD703318 PD70F3318 Single-power-supply flash memory: 256 KB, RAM: 16 KB Mask ROM: 256 KB, RAM: 16 KB PD70F3316Y PD70F3316 Single-power-supply flash memory: 128 KB, RAM: 6 KB PD703216 Mask ROM: 96 KB, RAM: 4 KB User's Manual U15947EJ3V1UD 29 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Part Number V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 Item Number of pins Internal memory (KB) Mask ROM 64 pins Flash memory RAM 80 pins - 96/128 - 128 4 64/ 128 96 - - 4 100 pins - 256 - 128 - 256 6 64/ 128 96 12 - - 4 VDD = 2.7 to 5.5 V Minimum instruction execution time 50 ns @ 20 MHz X1 input 2 to 10 MHz Subclock 32.768 kHz Timer - 96/ 128 128 - 256 - 16 - 256 128 - 6 8 8 8 16 CMOS I/O 43 59 76 112 N-ch open-drain I/O 1 2 - 4 6 1 ch 1 ch 2 ch 4 ch 6 ch 8 bits (TM5) 2 ch 2 ch 2 ch 2 ch 8 bits (TMH) 2 ch 2 ch 2 ch 2 ch Interval timer 1 ch 1 ch 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch UART UART supporting LIN-bus 2 Note IC 1 ch - 16 bits (TM0) Serial CSI interface Automatic transmit/ receive 3-wire CSI 1 ch - 16 bits (TMP) RTO 1 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 6 bits x 1 ch 6 bits x 1 ch 6 bits x 2 ch 2 ch 2 ch 2 ch 3 ch - 1 ch 2 ch 2 ch 2 ch 2 ch 2 ch 3 ch - - - - 1 ch 1 ch 1 ch 2 ch Address space - 128 KB 3 MB 15 MB Address bus - 16 bits 22 bits 24 bits Mode - Multiplexed mode only - - - - 10-bit A/D converter 8 ch 8 ch 8 ch 16 ch 8-bit D/A converter - - 2 ch 2 ch Interrupts External 8 8 8 External bus DMA controller Internal Key return input Reset 26 26 8 ch 29 LVI Not provided Clock monitor Not provided WDT1 Provided WDT2 Provided ROM correction 4 points Not provided Provided HALT/IDLE/STOP/sub-IDLE mode TA = -40 to +85C Note Provided in the Y version only. 30 User's Manual U15947EJ3V1UD 8 34 Provided Not provided Operating ambient temperature 31 8 ch POC Standby function Multiplexed/separate mode 8 ch RESET pin Regulator 256 16 CMOS input WDT2 - - Internal oscillation Ports 256 6 Power supply voltage Clock 144 pins - 40 43 8 ch CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1+ is shown below. Part Number V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+ Item Number of pins Internal memory (KB) Mask ROM 64 pins 80 pins 100 pins - 128 256 - 128/256 - 128/256 - - 128 - - 256 - 256 - 256 6 16 6 16 Flash memory RAM 4 6 12 Power supply voltage VDD = 2.7 to 5.5 V Minimum instruction execution time 50 ns @ 20 MHz Clock X1 input 2 to 10 MHz Subclock 32.768 kHz Internal oscillation Ports 240 kHz (TYP.) CMOS input 8 8 8 16 CMOS I/O 43 59 76 112 N-ch open-drain I/O Timer 144 pins 96/128 1 2 16 bits (TMP) 1 ch 1 ch 1 ch 4 1 ch 6 16 bits (TM0) 1 ch 2 ch 4 ch 6 ch 8 bits (TM5) 2 ch 2 ch 2 ch 2 ch 8 bits (TMH) 2 ch 2 ch 2 ch 2 ch Interval timer 1 ch 1 ch 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch WDT2 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 6 bits x 1 ch 6 bits x 1 ch 6 bits x 2 ch 2 ch 2 ch 2 ch 3 ch - 1 ch 2 ch 2 ch UART 1 ch 1 ch 1 ch 2 ch UART supporting LIN-bus 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 2 ch Address space - 128 KB 3 MB 15 MB Address bus - 16 bits 22 bits 24 bits Mode - Multiplexed mode only - - 4 ch 4 ch 10-bit A/D converter 8 ch 8 ch 8 ch 16 ch 8-bit D/A converter - - 2 ch 2 ch Interrupts External 9 9 9 9 27 30 42 48 8 ch 8 ch 8 ch 8 ch RTO Serial CSI interface Automatic transmit/ receive 3-wire CSI 2 Note IC External bus DMA controller Internal Key return input Reset RESET pin Provided POC LVI Fixed to 2.7 V or lower 3.1 V/3.3 V 0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Clock monitor Provided (monitoring by internal oscillator) WDT1 Provided WDT2 Provided ROM correction Regulator Standby function Operating ambient temperature Multiplexed/separate mode 4 points Not provided Provided HALT/IDLE/STOP/sub-IDLE mode TA = -40 to +85C Note Provided in the Y version only. User's Manual U15947EJ3V1UD 31 CHAPTER 1 OUTLINE 1.7 Block Diagram TO00/TI010/P01 TI000/P00 16-bit timer/ event counter 00 TO01Note/TI011Note/P06 TI001Note/P05 16-bit timer/Note event counter 01 TOH0/P15 8-bit timer H0 TOH1/P16 8-bit timer H1 8-bit timer/ event counter 50 TI50/TO50/P17 8-bit timer/ event counter 51 TI51/TO51/P33 Port 0 7 P00 to P06 Port 1 8 P10 to P17 Port 2 8 P20 to P27 Port 3 4 P30 to P33 Port 4 8 P40 to P47 Port 5 8 P50 to P57 Port 6 8 P60 to P67 Port 7 8 P70 to P77 Port 12 P120 Port 13 P130 Watch timer 78K/0 CPU core Watchdog timer RxD0/P11 TxD0/P10 Serial interface UART0 RxD6/P14 TxD6/P13 Serial interface UART6 SI10/P11 SO10/P12 SCK10/P10 Serial interface CSI10 SI11Note/P03 SO11Note/P02 SCK11Note/P04 SSI11Note/P05 Internal expansion RAMNote Serial interface CSI11Note SIA0/P143 SOA0/P144 SCKA0/P142 STB0/P145 BUSY0/P141 ANI0/P20 to ANI7/P27 AVREF AVSS Internal high-speed RAM ROM (Flash memory) Port 14 6 P140 to P145 Buzzer output BUZ/P141 Clock output control PCL/P140 Clock monitor Power on clear/ low voltage indicator Key return POC/LVI control 8 KR0/P70 to KR7/P77 Reset control Serial interface CSIA0 8 8 External access 8 A/D converter AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 INTP0/P120 INTP1/P30 to INTP4/P33 Internal oscillator 4 Interrupt control INTP5/P16 INTP6/P140, INTP7/P141 Note PD780146, 780148, and 78F0148 only. 32 Voltage regulator REGC VDD, VSS, IC EVDD EVSS (VPP) Multiplier & divider Remark System control RESET X1 X2 XT1 XT2 2 Items in parentheses are available only in the PD78F0148. User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE 1.8 Outline of Functions (1/2) Item Internal memory ROM PD780143 PD780144 24 KB PD780146 32 KB 48 KB PD780148 60 KB PD78F0148 Note 60 KB (flash memory) High-speed 1 KB RAM - Expansion RAM Buffer RAM Memory space X1 input clock (oscillation frequency) Expanded-specification products of standard products and (A) grade products 1 KB 1 KB Note 32 bytes 64 KB Ceramic/crystal/external clock oscillation * REGC pin is connected directly to VDD 2 to 12 MHz: VDD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 3.5 to 5.5 V, 2 to 8.38 MHz: VDD = 3.0 to 5.5 V, 2 to 5 MHz: VDD = 2.5 to 5.5 V * 1 F capacitor is connected to REGC pin 2 to 8.38 MHz: VDD = 4.0 to 5.5 V Conventional products of standard products and (A) grade products * REGC pin is connected directly to VDD 2 to 10 MHz: VDD = 4.0 to 5.5 V, 2 to 8.38 MHz: VDD = 3.3 to 5.5 V, 2 to 5 MHz: VDD = 2.7 to 5.5 V * 1 F capacitor is connected to REGC pin 2 to 8.38 MHz: VDD = 4.0 to 5.5 V (A1) grade products * REGC pin is connected directly to VDD 2 to 10 MHz: 2 to 5 MHz: (A2) grade products VDD = 4.5 to 5.5 V, 2 to 8.38 MHz: VDD = 4.0 to 5.5 V, VDD = 3.3 to 5.5 V * REGC pin is connected directly to VDD 2 to 8.38 MHz: VDD = 4.0 to 5.5 V, 2 to 5 MHz: VDD = 3.3 to 5.5 V Internal oscillation clock Internal oscillation (240 kHz (TYP.): VDD = 2.5 to 5.5 V) (oscillation frequency) Subsystem clock Crystal/external clock oscillation (32.768 kHz: VDD = 2.5 to 5.5 V) (oscillation frequency) General-purpose registers 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time 0.166 s/0.333 s/0.666 s/1.333 s/2.666 s (X1 input clock: @ fXP = 12 MHz operation) 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (TYP.) (Internal oscillation clock: @ fR = 240 kHz (TYP.) operation) 122 s (subsystem clock: @ fXT = 32.768 kHz operation) Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, and Boolean operation) I/O ports Total: 67 CMOS I/O 54 CMOS input 8 CMOS output N-ch open-drain I/O 1 4 * BCD adjust, etc. Note The internal flash memory capacity and internal expansion RAM capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). User's Manual U15947EJ3V1UD 33 CHAPTER 1 OUTLINE (2/2) PD780143 Item PD780144 PD780146 PD780148 PD78F0148 * 16-bit timer/event counter: 2 channels (1 channel only in the PD780143, 780144) Timers * 8-bit timer/event counter: 2 channels Timer outputs Clock output * 8-bit timer: 2 channels * Watch timer * Watchdog timer: 1 channel 1 channel 5 (PWM output: 4) 6 (PWM output: 4) * 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (X1 input clock: @10 MHz operation) * 32.768 kHz (subsystem clock: @32.768 kHz operation) Buzzer output 1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (X1 input clock: @10 MHz operation) A/D converter 10-bit resolution x 8 channels Serial interface * UART mode supporting LIN-bus: 1 channel * 3-wire serial I/O mode: (None in the PD780143, 780144) 1 channel * 3-wire serial I/O mode with automatic transmit/receive function: 1 channel Note 1 * 3-wire serial I/O mode/UART mode : 1 channel * 16 bits x 16 bits = 32 bits (multiplication) Multiplier/divider * 32 bits / 16 bits = 32 bits remainder of 16 bits (division) Vectored interrupt sources Internal 17 External 9 Key interrupt Reset 20 Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). * Reset using RESET pin * Internal reset by watchdog timer * Internal reset by clock monitor * Internal reset by power-on-clear * Internal reset by low-voltage detector Supply voltage * Expanded-specification products of standard products and (A) grade products: VDD = 2.5 to 5.5 V Notes 2, 3 * Conventional products of standard products and (A) grade products: Notes 2, 3 VDD = 2.7 to 5.5 V Note 3 * (A1) grade products, (A2) grade products: VDD = 3.3 to 5.5 V Operating ambient temperature * Standard products, (A) grade products: TA = -40 to +85C * (A1) grade products: TA = -40 to +110C (mask ROM versions), -40 to +105C (flash memory versions) * (A2) grade products: TA = -40 to +125C (mask ROM versions) Package * 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (fine pitch) (12 x 12) Notes 1. 34 Select either of the functions of these alternate-function pins. 2. Use the product in a voltage range of 3.0 to 5.5 V when the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.85 V 0.15 V. 3. Use the product in a voltage range of 3.7 to 5.5 V when the detection voltage (VPOC) of the power-on-clear (POC) circuit is 3.5 V 0.2 V. User's Manual U15947EJ3V1UD CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/ 8-Bit Timer/ Event Counters 00 Note 1 and 01 Event Counters 50 and 51 TM00 Operation mode TM50 TM51 TMH0 Watchdog Timer TMH1 Note 2 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel External event counter 1 channel 1 channel 1 channel 1 channel - - - - - - - - - - - - 1 channel Timer output 1 output 1 output 1 output 1 output 1 output 1 output - - PPG output 1 output 1 output - - - - - - PWM output - - 1 output 1 output 1 output 1 output - - Pulse width measurement 2 inputs 2 inputs - - - - - - Square-wave output 1 output 1 output 1 output 1 output 1 output 1 output - - 2 2 1 1 1 1 1 - Interrupt source Notes 1. 2. Remark Note 1 Watch Timer Interval timer Watchdog timer Function TM01 8-Bit Timers H0 and H1 16-bit timer/event counter 01 is available only in the PD780146, 780148, and 78F0148. The watch timer function and interval timer function can be used simultaneously. TM51 and TMH1 can be used in combination as a carrier generator mode. User's Manual U15947EJ3V1UD 35 CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 VDD Pins other than port pins (1) Port pins (1/2) Pin Name I/O I/O P00 P01 P02 P03 Function Port 0. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. After Reset Input Alternate Function TI000 TI010/TO00 SO11 SI11 Note Note P04 SCK11 P05 SSI11 P06 TI011 Note Note /TI001 Note I/O P10 P11 P12 P13 Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input /TO01 Note Note SCK10/TxD0 SI10/RxD0 SO10 TxD6 P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 Input Port 2. 8-bit input-only port. Input ANI0 to ANI7 P30 to P32 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input INTP1 to INTP3 Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input P33 P40 to P47 I/O INTP4/TI51/TO51 AD0 to AD7 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. 36 User's Manual U15947EJ3V1UD CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name P50 to P57 I/O I/O Function Port 5. After Reset Input Alternate Function A8 to A15 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 to P63 I/O Port 6. N-ch open-drain I/O port. 8-bit I/O port. Use of an on-chip pull-up Input/output can be specified in 1-bit units. resistor can be specified - Input by a mask option only for mask ROM versions. P64 Use of an on-chip pull-up RD P65 resistor can be specified by a software setting. WR P66 WAIT P67 ASTB P70 to P77 I/O Port 7. Input KR0 to KR7 Input INTP0 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. - Output 1-bit output-only port. P140 P141 I/O Port 14. Input 6-bit I/O port. BUZ/BUSY0/ Input/output can be specified in 1-bit units. P142 PCL/INTP6 Use of an on-chip pull-up resistor can be specified by a software setting. INTP7 SCKA0 P143 SIA0 P144 SOA0 P145 STB0 User's Manual U15947EJ3V1UD 37 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name INTP0 I/O Input INTP1 to INTP3 Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P120 P30 to P32 INTP4 P33/TI51/TO51 INTP5 P16/TOH1 INTP6 P140/PCL INTP7 P141/BUZ/BUSY0 Input SI10 SI11 Serial data input to serial interface Input Note P11/RxD0 P03 SIA0 P143 SO10 SO11 Output Serial data output from serial interface Input Note P02 SOA0 P144 SCK10 SCK11 I/O Clock input/output for serial interface Input Note Note P10/TxD0 P04 SCKA0 SSI11 P12 P142 Input Serial interface chip select input Input P05/TI001 BUSY0 Input Serial interface busy input Input P141/BUZ/INTP7 STB0 Output Serial interface strobe output Input P145 RxD0 Input Serial data input to asynchronous serial interface Input P11/SI10 RxD6 P14 Output TxD0 Serial data output from asynchronous serial interface Input TxD6 P10/SCK10 P13 TI000 Input Note External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Input P00 TI001 External count clock input to 16-bit timer/event counter 01 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 P05/SSI11 TI010 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 P01/TO00 Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 P06/TO01 Note TI011 Output TO00 TO01 Note Input 16-bit timer/event counter 01 output Input TI50 16-bit timer/event counter 00 output TI51 External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 Output TO50 8-bit timer/event counter 50 output Note P01/TI010 P06/TI011 Input Note Note P17/TO50 P33/TO51/INTP4 Input P17/TI50 TO51 8-bit timer/event counter 51 output P33/TI51/INTP4 TOH0 8-bit timer H0 output P15 TOH1 8-bit timer H1 output P16/INTP5 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. 38 User's Manual U15947EJ3V1UD CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name I/O Function After Reset Alternate Function PCL Output Clock output (for trimming of X1 input clock, subsystem clock) Input P140/INTP6 BUZ Output Buzzer output Input P141/INTP7/BUSY0 AD0 to AD7 I/O Lower address/data bus for external memory expansion Input P40 to P47 A8 to A15 Output Higher address bus for external memory expansion Input P50 to P57 RD Output Strobe signal output for external memory read operation Input P64 WR Output Strobe signal output for external memory write operation Input P65 WAIT Input Wait insertion on external memory access Input P66 ASTB Output Strobe output that externally latches address information output Input P67 Input P20 to P27 to ports 4 and 5 for access to external memory ANI0 to ANI7 Input A/D converter analog input AVREF Input A/D converter reference voltage input and positive power supply - - - - for port 2 AVSS - A/D converter ground potential. Make the same potential as EVSS or VSS. KR0 to KR7 REGC Input - Key interrupt input Input Connecting regulator output stabilization capacitor. When using the regulator, connect to VSS via a capacitor (1 F: P70 to P77 - - recommended). When the regulator is not used, connect directly to VDD. RESET Input System reset input - - X1 Input Connecting resonator for X1 input clock oscillation - - - - - - - - X2 XT1 - Input Connecting resonator for subsystem clock oscillation XT2 - VDD - Positive power supply (except for ports) - - EVDD - Positive power supply for ports - - VSS - Ground potential (except for ports) - - EVSS - Ground potential for ports - - IC - Internally connected. Connect directly to EVSS or VSS. - - VPP - Flash memory programming mode setting. High-voltage - - application for program write/verify. Connect to EVSS or VSS in normal operation mode. User's Manual U15947EJ3V1UD 39 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input. (a) TI000, TI001Note These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01. (b) TI010, TI011Note These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01. (c) TO00, TO01Note These are timer output pins. (d) SI11Note This is a serial interface serial data input pin. (e) SO11Note This is a serial interface serial data output pin. (f) SCK11Note This is a serial interface serial clock I/O pin. (g) SSI11Note This is a serial interface chip select input pin. Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. 40 User's Manual U15947EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial interface serial data input pin. (b) SO10 This is a serial interface serial data output pin. (c) SCK10 This is a serial interface serial clock I/O pin. (d) RxD0, RxD6 These are the serial data input pins of the asynchronous serial interface. (e) TxD0, TxD6 These are the serial data output pins of the asynchronous serial interface. (f) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins. (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit input-only port. (2) Control mode P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter. User's Manual U15947EJ3V1UD 41 CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input pins and timer I/O pins. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin. 2.2.5 P40 to P47 (port 4) P40 to P47 function as an 8-bit I/O port. These pins also function as address/data bus pins. The following operation modes can be specified. (1) Port mode P40 to P47 function as an 8-bit I/O port. P40 to P47 can be set to input or output in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). (2) Control mode P40 to P47 function as the pins for the lower address/data bus (AD0 to AD7) in external memory expansion mode. Caution The external bus interface function cannot be used in (A1) grade products and (A2) grade products. 2.2.6 P50 to P57 (port 5) P50 to P57 function as an 8-bit I/O port. These pins also function as address bus pins. The following operation modes can be specified. (1) Port mode P50 to P57 function as an 8-bit I/O port. P50 to P57 can be set to input or output in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). (2) Control mode P50 to P57 function as the pins for the higher address bus (A8 to A15) in external memory expansion mode. Caution The external bus interface function cannot be used in (A1) grade products and (A2) grade products. 42 User's Manual U15947EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.2.7 P60 to P67 (port 6) P60 to P67 function as an 8-bit I/O port. These pins also function as control pins in external memory expansion mode. The following operation modes can be specified. (1) Port mode P60 to P67 function as an 8-bit I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. Use of an on-chip pull-up resistor can be specified for P64 to P67 by pull-up resistor option register 6 (PU6). (2) Control mode P64 to P67 function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode. Cautions 1. P66 functions as an I/O port if the external wait is not used in external memory expansion mode. 2. The external bus interface function cannot be used in (A1) grade products and (A2) grade products. 2.2.8 P70 to P77 (port 7) P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units. (1) Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins. 2.2.9 P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified. (1) Port mode P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.10 P130 (port 13) P130 functions as a 1-bit output-only port. User's Manual U15947EJ3V1UD 43 CHAPTER 2 PIN FUNCTIONS 2.2.11 P140 to P145 (port 14) P140 to P145 function as a 6-bit I/O port. These pins also function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. The following operation modes can be specified in 1-bit units. (1) Port mode P140 to P145 function as a 6-bit I/O port. P140 to P145 can be set to input or output in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 to P145 function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. (a) INTP6, INTP7 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) PCL This is a clock output pin. (c) BUZ This is a buzzer output pin. (d) SIA0 This is a serial interface serial data input pin. (e) SOA0 This is a serial interface serial data output pin. (f) SCKA0 This is a serial interface serial clock I/O pin. (g) BUSY0 This is a serial interface busy input pin. (h) STB0 This is a serial interface strobe output pin. 2.2.12 AVREF This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to EVDD or VDDNote. Note Connect port 2 directly to EVDD when it is used as a digital port. 2.2.13 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the EVSS pin or VSS pin. 44 User's Manual U15947EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.2.14 RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting the capacitor for the regulator. When using the regulator, connect this pin to VSS via a capacitor (1 F: recommended). When the regulator is not used, connect this pin directly to VDD pin. Caution A regulator cannot be used with (A1) grade products and (A2) grade products. Be sure to connect the REGC pin of these products directly to VDD. 2.2.16 X1 and X2 These are the pins for connecting a resonator for X1 input clock. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. 2.2.17 XT1 and XT2 These are the pins for connecting a resonator for subsystem clock. When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin. 2.2.18 VDD and EVDD VDD is the positive power supply pin for other than ports. EVDD is the positive power supply pin for ports. 2.2.19 VSS and EVSS VSS is the ground potential pin for other than ports. EVSS is the ground potential pin for ports. 2.2.20 VPP (flash memory versions only) This is a pin for flash memory programming mode setting and high-voltage application for program write/verify. Connect to EVSS or VSS in the normal operation mode. 2.2.21 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KF1 at shipment. Connect it directly to EVSS or VSS pin with the shortest possible wire in the normal operation mode. When a potential difference is produced between the IC pin and the EVSS or VSS pin because the wiring between these two pins is too long or external noise is input to the IC pin, the user's program may not operate normally. * Connect the IC pin directly to EVSS or VSS. EVSS or VSS IC As short as possible User's Manual U15947EJ3V1UD 45 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (1/2) Pin Name P00/TI000 I/O Circuit Type 8-A I/O I/O P03/SI11 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P01/TI010/TO00 P02/SO11 Recommended Connection of Unused Pins Note Note P04/SCK11 P05/SSI11 P06/TI011 Note Note Note /TI001 Note /TO01 P10/SCK10/TxD0 P11/SI10/RxD0 Note Note Note P12/SO10 5-A P13/TxD6 P14/RxD6 8-A P15/TOH0 5-A P16/TOH1/INTP5 8-A P17/TI50/TO50 P20/ANI0 to P27/ANI7 9-C Input P30/INTP1 to P32/INTP3 8-A I/O Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P33/TI51/TO51/INTP4 P40/AD0 to P47/AD7 Connect to EVDD or EVSS. 5-A P50/A8 to P57/A15 P60, P61 (Mask ROM version) 13-S Input: P60, P61 (Flash memory version) 13-R Output: Leave this pin open at low-level output after clearing the output latch of the port to 0. P62, P63 (Mask ROM version) 13-V P62, P63 (Flash memory version) 13-W P64/WD 5-A Input: Independently connect to EVDD via a resistor. Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P65/WR P66/WAIT P67/ASTB P70/KR0 to P77/KR7 8-A P120/INTP0 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. 46 User's Manual U15947EJ3V1UD CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Type I/O P130 3-C Output P140/PCL/INTP6 8-A I/O Recommended Connection of Unused Pins Leave open. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0 5-A P145/STB RESET 2 XT1 16 Input Note 1 Connect directly to EVSS or VSS - XT2 - AVREF Connect to EVDD or VDD. . Leave open. Connect directly to EVDD or VDD Note 2 . Connect directly to EVSS or VSS. AVSS IC Connect to EVSS or VSS. VPP Notes 1. Except for rank K and rank I products. When using rank K or rank I products, handle as follows. <When regulator is not used (REGC pin is connected directly to VDD)> * XT1: Connect directly to EVDD or VDD. <When regulator is used (a 1 F capacitor is connected to REGC pin)> * XT1: Connect directly to the REGC pin. 2. Connect port 2 directly to EVDD when it is used as a digital port. User's Manual U15947EJ3V1UD 47 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 8-A Type 2 EVDD Pullup enable P-ch IN VDD Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch Type 9-C Type 3-C EVDD P-ch Data Comparator P-ch IN + N-ch - AVSS OUT VREF (threshold voltage) N-ch Input enable Type 5-A Type 13-R EVDD Pullup enable P-ch IN/OUT VDD Data Data Output disable P-ch IN/OUT Output disable N-ch Input enable 48 User's Manual U15947EJ3V1UD N-ch CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-W Type 13-S EVDD Mask option Data Output disable IN/OUT IN/OUT Data Output disable N-ch N-ch Input enable Middle-voltage input buffer Type 16 Type 13-V EVDD Feedback cut-off Mask option IN/OUT Data Output disable P-ch N-ch XT1 Input enable XT2 Middle-voltage input buffer User's Manual U15947EJ3V1UD 49 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space 78K0/KF1 products can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all 78K0/KF1 products are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) IMS 50 IXS PD780143 C6H PD780144 C8H PD780146 CCH PD780148 CFH PD78F0148 Value corresponding to mask ROM version 0CH 0AH User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map ( PD780143) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Data memory space FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH ROM/RAM space in which instructions can be fetched 6000H 5FFFH 5FFFH Reserved Buffer RAM 32 x 8 bits Program area 1000H 0FFFH CALLF entry area Reserved 0800H 07FFH External memory 38912 x 8 bits Program area 0080H 007FH CALLT table area 0040H 003FH Internal ROM 24576 x 8 bits 0000H Vector table area 0000H User's Manual U15947EJ3V1UD 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( PD780144) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Data memory space FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH 7FFFH Program area Reserved Buffer RAM 32 x 8 bits 1000H 0FFFH CALLF entry area Reserved 0800H 07FFH Program area ROM/RAM space in which instructions can be fetched 8000H 7FFFH External memory 30720 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Internal ROM 32768 x 8 bits 0000H 0000H 52 Vector table area User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( PD780146) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH Data memory space FA00H F9FFH F800H F7FFH Reserved BFFFH Buffer RAM 32 x 8 bits Reserved Program area 1000H 0FFFH CALLF entry area Internal expansion RAM 1024 x 8 bits 0800H 07FFH F400H F3FFH ROM/RAM space in which instructions can be fetched C000H BFFFH Program area External memory 13312 x 8 bits 0080H 007FH CALLT table area Internal ROM 49152 x 8 bits 0000H 0040H 003FH Vector table area 0000H User's Manual U15947EJ3V1UD 53 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( PD780148) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH Data memory space FA00H F9FFH F800H F7FFH Reserved EFFFH Buffer RAM 32 x 8 bits Reserved Program area 1000H 0FFFH CALLF entry area Internal expansion RAM 1024 x 8 bits 0800H 07FFH F400H F3FFH ROM/RAM space in which instructions can be fetched F000H EFFFH Program area External memory 1024 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Internal ROM 61440 x 8 bits 0000H 54 Vector table area 0000H User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( PD78F0148) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH Data memory space FA00H F9FFH F800H F7FFH Reserved EFFFH Buffer RAM 32 x 8 bits Reserved Program area 1000H 0FFFH CALLF entry area Internal expansion RAM 1024 x 8 bits 0800H 07FFH F400H F3FFH ROM/RAM space in which instructions can be fetched Program area External memory 1024 x 8 bits 0080H 007FH CALLT table area F000H EFFFH Flash memory 61440 x 8 bits 0000H 0040H 003FH Vector table area 0000H User's Manual U15947EJ3V1UD 55 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KF1 products incorporate internal ROM (mask ROM or flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure PD780143 Capacity 24576 x 8 bits (0000H to 5FFFH) Mask ROM PD780144 32768 x 8 bits (0000H to 7FFFH) PD780146 49152 x 8 bits (0000H to BFFFH) PD780148 61440 x 8 bits (0000H to EFFFH) PD78F0148 61440 x 8 bits (0000H to EFFFH) Flash memory The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-3. Vector Table Vector Table Address Interrupt Source Vector Table Address RESET input, POC, LVI, 0020H INTTM000 clock monitor, WDT 0022H INTTM010 0004H INTLVI 0024H INTAD 0006H INTP0 0026H INTSR0 0008H INTP1 0028H INTWTI 000AH INTP2 002AH INTTM51 000CH INTP3 002CH INTKR 000EH INTP4 002EH INTWT 0010H INTP5 0030H INTP6 0012H INTSRE6 0032H INTP7 0014H INTSR6 0034H INTDMU 0016H INTST6 0036H INTCSI11 0018H INTCSI10/INTST0 0038H INTTM001 Note 001AH INTTMH1 003AH INTTM011 Note 001CH INTTMH0 003CH INTACSI 001EH INTTM50 003EH BRK 0000H Note Available only in the PD780146, 780148, and 78F0148. 56 Interrupt Source User's Manual U15947EJ3V1UD Note CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space 78K0/KF1 products incorporate the following RAMs. (1) Internal high-speed RAM The internal high-speed RAM is allocated to the area FB00H to FEFFH in a 1024 x 8 bits configuration. The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. (2) Internal expansion RAM Table 3-4. Internal Expansion RAM Capacity Part Number Internal Expansion RAM PD780143 - PD780144 PD780146 1024 x 8 bits (F400H to F7FFH) PD780148 PD78F0148 The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory. 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see Table 3-5 Special Function Register List in 3.2.3 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. User's Manual U15947EJ3V1UD 57 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KF1, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-6 to 3-10 show correspondence between data memory and addressing. For details of each addressing mode, see 3.4 Operand Address Addressing. Figure 3-6. Correspondence Between Data Memory and Addressing (PD780143) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Direct addressing Reserved Register indirect addressing Buffer RAM 32 x 8 bits Based addressing Based indexed addressing Reserved External memory 38912 x 8 bits 6000H 5FFFH Internal ROM 24576 x 8 bits 0000H 58 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Correspondence Between Data Memory and Addressing (PD780144) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Direct addressing Reserved Register indirect addressing Buffer RAM 32 x 8 bits Based addressing Based indexed addressing Reserved External memory 30720 x 8 bits 8000H 7FFFH Internal ROM 32768 x 8 bits 0000H User's Manual U15947EJ3V1UD 59 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing (PD780146) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Reserved Buffer RAM 32 x 8 bits Direct addressing Reserved Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits F400H F3FFH External memory 13312 x 8 bits C000H BFFFH Internal ROM 49152 x 8 bits 0000H 60 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Correspondence Between Data Memory and Addressing (PD780148) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Reserved Buffer RAM 32 x 8 bits Direct addressing Reserved Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits F400H F3FFH External memory 1024 x 8 bits F000H EFFFH Internal ROM 61440 x 8 bits 0000H User's Manual U15947EJ3V1UD 61 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing (PD78F0148) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Reserved Buffer RAM 32 x 8 bits Direct addressing Reserved Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits F400H F3FFH External memory 1024 x 8 bits F000H EFFFH Flash memory 61440 x 8 bits 0000H 62 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KF1 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-11. Format of Program Counter 15 PC 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-12. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 0 ISP CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. User's Manual U15947EJ3V1UD 63 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see 19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) cannot be acknowledged. Actual interrupt request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-13. Format of Stack Pointer 15 SP 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using the stack. 64 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) Interrupt, BRK instructions (when SP = FEE0H) SP SP FEE0H FEDDH FEE0H FEDFH PSW FEDEH PC15 to PC8 FEDDH PC7 to PC0 User's Manual U15947EJ3V1UD 65 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) RETI, RETB instructions (when SP = FEDDH) SP SP 66 FEE0H FEDDH FEE0H FEDFH PSW FEDEH PC15 to PC8 FEDDH PC7 to PC0 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-16. Configuration of General-Purpose Registers (a) Absolute name 16-bit processing 8-bit processing FEFFH R7 BANK0 RP3 R6 FEF8H R5 BANK1 RP2 R4 FEF0H R3 RP1 BANK2 R2 FEE8H R1 RP0 BANK3 R0 FEE0H 15 0 7 0 (b) Function name 16-bit processing 8-bit processing FEFFH H BANK0 HL L FEF8H D BANK1 DE E FEF0H B BC BANK2 C FEE8H A AX BANK3 X FEE0H 15 User's Manual U15947EJ3V1UD 0 7 0 67 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined as the sfr variable by #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon RESET input. 68 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol R/W After Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits Reset - 00H FF00H Port register 0 P0 R/W FF01H Port register 1 P1 R/W - 00H FF02H Port register 2 P2 R - Undefined FF03H Port register 3 P3 R/W - 00H FF04H Port register 4 P4 R/W - 00H FF05H Port register 5 P5 R/W - 00H FF06H Port register 6 P6 R/W - 00H FF07H Port register 7 P7 R/W - 00H - Undefined A/D conversion result register ADCR R - FF0AH Receive buffer register 6 RXB6 R - - FFH FF0BH Transmit buffer register 6 TXB6 R/W - - FFH FF0CH Port register 12 P12 R/W - 00H FF0DH Port register 13 P13 R/W - 00H FF0EH Port register 14 P14 R/W - 00H FF0FH Serial I/O shift register 10 SIO10 R - - 00H - 0000H FF08H FF09H 16-bit timer counter 00 TM00 R - 16-bit timer capture/compare register 000 CR000 R/W - - 0000H 16-bit timer capture/compare register 010 CR010 R/W - - 0000H FF16H 8-bit timer counter 50 TM50 R - - 00H FF17H 8-bit timer compare register 50 CR50 R/W - - 00H - 00H FF10H FF11H FF12H FF13H FF14H FF15H FF18H 8-bit timer H compare register 00 CMP00 R/W - FF19H 8-bit timer H compare register 10 CMP10 R/W - - 00H FF1AH 8-bit timer H compare register 01 CMP01 R/W - - 00H FF1BH 8-bit timer H compare register 11 CMP11 R/W - - 00H FF1FH 8-bit timer counter 51 TM51 R - - 00H FF20H Port mode register 0 PM0 R/W - FFH FF21H Port mode register 1 PM1 R/W - FFH FF23H Port mode register 3 PM3 R/W - FFH - FFH FF24H Port mode register 4 PM4 R/W FF25H Port mode register 5 PM5 R/W - FFH FF26H Port mode register 6 PM6 R/W - FFH FF27H Port mode register 7 PM7 R/W - FFH FF28H A/D converter mode register ADM R/W - 00H FF29H Analog input channel specification register ADS R/W - 00H FF2AH Power-fail comparison mode register PFM R/W - 00H FF2BH Power-fail comparison threshold register PFT R/W - - 00H User's Manual U15947EJ3V1UD 69 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol R/W After Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits Reset - FFH FF2CH Port mode register 12 PM12 R/W FF2EH Port mode register 14 PM14 R/W - FFH FF30H Pull-up resistor option register 0 PU0 R/W - 00H FF31H Pull-up resistor option register 1 PU1 R/W - 00H FF33H Pull-up resistor option register 3 PU3 R/W - 00H FF34H Pull-up resistor option register 4 PU4 R/W - 00H FF35H Pull-up resistor option register 5 PU5 R/W - 00H FF36H Pull-up resistor option register 6 PU6 R/W - 00H - 00H FF37H Pull-up resistor option register 7 PU7 R/W FF3CH Pull-up resistor option register 12 PU12 R/W - 00H FF3EH Pull-up resistor option register 14 PU14 R/W - 00H FF40H Clock output selection register CKS R/W - 00H FF41H 8-bit timer compare register 51 CR51 R/W - - 00H FF43H 8-bit timer mode control register 51 TMC51 R/W - 00H FF47H Memory expansion mode register MEM R/W - 00H FF48H External interrupt rising edge enable register EGP R/W - 00H R/W - 00H R - - 00H SOTB11 R/W - - Undefined FF49H External interrupt falling edge enable register FF4AH Serial I/O shift register 11 Note EGN SIO11 Note FF4CH Transmit buffer register 11 FF4FH Input switch control register ISC R/W - 00H FF50H Asynchronous serial interface operation mode ASIM6 R/W - 01H ASIS6 R - - 00H ASIF6 R - - 00H CKSR6 R/W - - 00H - FFH register 6 FF53H Asynchronous serial interface reception error status register 6 FF55H Asynchronous serial interface transmission status register 6 FF56H Clock selection register 6 FF57H Baud rate generator control register 6 BRGC6 R/W - FF58H Asynchronous serial interface control register 6 ASICL6 R/W - 16H FF60H Remainder data register 0 SDR0 SDR0L R - 00H SDR0H - MDA0L MDA0LL R/W - FF63H MDA0LH - FF64H MDA0H MDA0HL R/W - - - - FF61H FF62H Multiplication/division data register A0 FF65H FF66H MDA0HH Multiplication/division data register B0 MDB0 MDB0L FF67H R/W MDB0H 00H 00H 00H 00H 00H 00H 00H FF68H Multiplier/divider control register 0 DMUC0 R/W - 00H FF69H 8-bit timer H mode register 0 TMHMD0 R/W - 00H FF6AH Timer clock selection register 50 TCL50 R/W - - 00H Note PD780146, 780148, and 78F0148 only. 70 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol R/W After Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits Reset - 00H FF6BH 8-bit timer mode control register 50 TMC50 R/W FF6CH 8-bit timer H mode register 1 TMHMD1 R/W - 00H FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W - 00H FF6EH Key return mode register KRM R/W - 00H FF6FH Watch timer operation mode register WTM R/W - 00H FF70H Asynchronous serial interface operation mode ASIM0 R/W - 01H R/W - - 1FH register 0 FF71H Baud rate generator control register 0 BRGC0 FF72H Receive buffer register 0 RXB0 Asynchronous serial interface reception error FF73H R - - FFH ASIS0 R - - 00H W - - FFH status register 0 FF74H Transmit shift register 0 TXS0 FF80H Serial operation mode register 10 CSIM10 R/W - 00H FF81H Serial clock selection register 10 CSIC10 R/W - 00H FF84H Transmit buffer register 10 SOTB10 R/W - - Undefined CSIM11 R/W - 00H CSIC11 R/W - 00H TCL51 R/W - - 00H - 00H FF88H Serial operation mode register 11 FF89H Serial clock selection register 11 FF8CH Timer clock selection register 51 Note 1 Note 1 FF90H Serial operation mode specification register 0 CSIMA0 R/W FF91H Serial status register 0 CSIS0 R/W - 00H FF92H Serial trigger register 0 CSIT0 R/W - 00H FF93H Divisor selection register 0 BRGCA0 R/W - - 03H FF94H Automatic data transfer address point ADTP0 R/W - - 00H ADTI0 R/W - - 00H specification register 0 Automatic data transfer interval specification FF95H register 0 FF96H Serial I/O shift register 0 SIOA0 R/W - - 00H FF97H Automatic data transfer address count register 0 ADTC3 R - - 00H - 67H FF98H Watchdog timer mode register WDTM R/W - FF99H Watchdog timer enable register WDTE R/W - - 9AH FFA0H Internal oscillation mode register RCM R/W - 00H FFA1H Main clock mode register MCM R/W - 00H FFA2H Main OSC control register MOC R/W - 00H FFA3H Oscillation stabilization time counter status register OSTC R - 00H FFA4H Oscillation stabilization time select register OSTS R/W - - 05H FFA9H Clock monitor mode register CLM R/W - 00H - 00H - 0000H FFACH Reset control flag register RESF R - Note 1 TM01 R - 16-bit timer counter 01 FFB0H Note 2 FFB1H Notes 1. 2. PD780146, 780148, and 78F0148 only. This value varies depending on the reset source. User's Manual U15947EJ3V1UD 71 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (4/4) Address FFB2H Special Function Register (SFR) Name Symbol R/W After Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits Reset R/W - - 0000H CR011 R/W - - 0000H TMC01 R/W - 00H PRM01 R/W - 00H CRC01 R/W - 00H TOC01 R/W - 00H - 00H 16-bit timer capture/compare register 001 Note 1 CR001 16-bit timer capture/compare register 011 Note 1 FFB3H FFB4H FFB5H Note 1 FFB6H 16-bit timer mode control register 01 FFB7H Prescaler mode register 01 Note 1 Note 1 FFB8H Capture/compare control register 01 Note 1 FFB9H 16-bit timer output control register 01 FFBAH 16-bit timer mode control register 00 TMC00 R/W FFBBH Prescaler mode register 00 PRM00 R/W - 00H FFBCH Capture/compare control register 00 CRC00 R/W - 00H FFBDH 16-bit timer output control register 00 TOC00 R/W - 00H FFBEH Low-voltage detection register LVIM R/W - 00H FFBFH Low-voltage detection level selection register LVIS R/W - - 00H FFE0H Interrupt request flag register 0L IF0 IF0L R/W 00H FFE1H Interrupt request flag register 0H IF0H R/W IF1L R/W IF1H R/W MK0L R/W MK0H R/W MK1L R/W MK1H R/W PR0L R/W PR0H R/W PR1L R/W PR1H R/W IMS R/W - - CFH FFE2H Interrupt request flag register 1L FFE3H Interrupt request flag register 1H FFE4H Interrupt mask flag register 0L FFE5H Interrupt mask flag register 0H FFE6H Interrupt mask flag register 1L FFE7H Interrupt mask flag register 1H FFE8H Priority specification flag register 0L FFE9H Priority specification flag register 0H FFEAH Priority specification flag register 1L FFEBH Priority specification flag register 1H FFF0H IF1 MK0 MK1 PR0 PR1 Internal memory size switching register Note 2 00H 00H 00H FFH FFH FFH DFH FFH FFH FFH FFH FFF4H Internal expansion RAM size switching register IXS R/W - - 0CH FFF8H Memory expansion wait setting register MM R/W - 10H FFFBH Processor clock control register PCC R/W - 00H Note 2 Notes 1. 2. PD780146, 780148, and 78F0148 only. The default value of IMS and IXS are fixed (IMS = CFH, IXS = 0CH) in all 78K0/KF1 products regardless of the internal memory capacity. Therefore, set the following value to each product. IMS 72 IXS PD780143 C6H PD780144 C8H PD780146 CCH PD780148 CFH PD78F0148 Value corresponding to mask ROM version 0CH 0AH User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC indicates the start address of the instruction after the BR instruction. PC + 15 8 7 0 6 S jdisp8 15 0 PC When S = 0, all bits of are 0. When S = 1, all bits of are 1. User's Manual U15947EJ3V1UD 73 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low Addr. High Addr. 15 0 8 7 PC In the case of CALLF !addr11 instruction 7 6 4 0 3 fa10-8 CALLF fa7-0 15 PC 74 0 11 10 0 0 0 8 7 1 User's Manual U15947EJ3V1UD 0 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Illustration] 7 Operation code 6 1 5 1 1 ta4-0 1 15 Effective address 0 7 0 0 0 0 0 0 0 8 7 6 0 0 1 1 0 5 0 0 Memory (Table) Low Addr. High Addr. Effective address+1 15 8 0 7 PC 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 A 15 0 7 X 8 7 0 PC User's Manual U15947EJ3V1UD 75 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KF1 instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets ROR4/ROL4 A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 76 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 and RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code User's Manual U15947EJ3V1UD 77 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (lower) addr16 (upper) Memory 78 User's Manual U15947EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration]. [Operand format] Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] MOV 0FE30H, A; when transferring value of A register to saddr (FE30H) Operation code 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 0 OP code saddr-offset Short direct memory 8 7 15 Effective address 1 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 User's Manual U15947EJ3V1UD 79 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name sfrp 16-bit manipulatable special function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 80 1 8 7 1 1 1 1 1 1 1 User's Manual U15947EJ3V1UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces. [Operand format] Identifier Description - [DE], [HL] [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 D DE 0 8 7 E 7 Memory 0 The memory address specified with the register pair DE The contents of the memory addressed are transferred. 7 0 A User's Manual U15947EJ3V1UD 81 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL + byte] [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] 16 HL 8 7 H 0 L 7 Memory The contents of the memory addressed are transferred. 7 0 A 82 User's Manual U15947EJ3V1UD 0 +10 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL + B], [HL + C] [Description example] In the case of MOV A, [HL + B] (selecting B register) Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 HL 8 7 0 H L + 7 0 B 7 Memory 0 The contents of the memory addressed are transferred. 7 0 A User's Manual U15947EJ3V1UD 83 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] In the case of PUSH DE (saving DE register) Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP SP 84 FEE0H FEDEH Memory FEE0H FEDFH D FEDEH E User's Manual U15947EJ3V1UD 0 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREF and EVDD. The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 78K0/KF1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types P50 P00 Port 0 Port 5 P06 P57 P10 P60 Port 1 Port 6 P17 P67 P20 P70 Port 2 Port 7 P27 P77 P30 Port 12 P120 Port 13 P130 P33 P140 P40 Port 3 Port 14 Port 4 P145 P47 User's Manual U15947EJ3V1UD 85 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (1/2) Pin Name P00 I/O I/O Function Port 0. After Reset Input 7-bit I/O port. P01 SO11 Use of an on-chip pull-up resistor can be specified by a P03 TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Alternate Function SI11 software setting. Note Note P04 SCK11 P05 SSI11 P06 TI011 Note Note /TI001 Note I/O P10 Port 1. Input 8-bit I/O port. P11 SCK10/TxD0 SO10 Use of an on-chip pull-up resistor can be specified by a P13 TxD6 software setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 Input Note SI10/RxD0 Input/output can be specified in 1-bit units. P12 /TO01 Note Port 2. Input ANI0 to ANI7 Input INTP1 to INTP3 8-bit input-only port. P30 to P32 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a P33 INTP4/TI51/TO51 software setting. P40 to P47 I/O Port 4. Input AD0 to AD7 Input A8 to A15 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P57 I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. 86 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (2/2) Pin Name I/O I/O P60 to P63 Function After Reset Port 6. N-ch open-drain I/O port. 8-bit I/O port. Use of an on-chip pull-up Input/output can be specified resistor can be specified by a in 1-bit units. mask option only for mask Alternate Function - Input ROM versions. P64 Use of an on-chip pull-up RD P65 resistor can be specified by a WR software setting. P66 WAIT P67 ASTB P70 to P77 I/O Port 7. Input KR0 to KR7 Input INTP0 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. - Output 1-bit output-only port. I/O P140 P141 Port 14. Input BUZ/BUSY0/ Input/output can be specified in 1-bit units. INTP7 Use of an on-chip pull-up resistor can be specified by a P142 PCL/INTP6 6-bit I/O port. software setting. SCKA0 P143 SIA0 P144 SOA0 P145 STB0 4.2 Port Configuration Ports include the following hardware. Table 4-3. Port Configuration Item Control registers Configuration Port mode register (PM0, PM1, PM3 to PM7, PM12, PM14) Port register (P0 to P7, P12 to P14) Pull-up resistor option register (PU0, PU1, PU3 to PU7, PU12, PU14) Port Total: 67 (CMOS I/O: 54, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4) Pull-up resistor * Mask ROM version Total: 58 (software control: 54, mask option specification: 4) * Flash memory version: Total: 54 User's Manual U15947EJ3V1UD 87 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O, serial interface data I/O, and clock I/O. RESET input sets port 0 to input mode. Figures 4-2 to 4-5 show block diagrams of port 0. Caution When P02/SO11Note, P03/SI11Note, and P04/SCK11Note are used as general-purpose ports, do not write to serial clock selection register 11 (CSIC11). Figure 4-2. Block Diagram of P00, P03, and P05 EVDD WRPU PU0 PU00, PU03, PU05 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P00, P03, P05) P00/TI000, P03/SI11Note, P05/SSI11Note/TI001Note WRPM PM0 PM00, PM03, PM05 Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal 88 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 and P06 EVDD WRPU PU0 PU01, PU06 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P01, P06) P01/TI010/TO00, P06/TI011Note/TO01Note WRPM PM0 PM01, PM06 Alternate function Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 89 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 EVDD WRPU PU0 PU02 P-ch Internal bus Selector RD WRPORT Output latch (P02) P02/SO11Note WRPM PM0 PM02 Alternate function Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal 90 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P04 EVDD WRPU PU0 PU04 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P04) P04/SCK11Note WRPM PM0 PM04 Alternate function Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 91 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. RESET input sets port 1 to input mode. Figures 4-6 to 4-10 show block diagrams of port 1. Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not write to serial clock selection register 10 (CSIC10). Figure 4-6. Block Diagram of P10 EVDD WRPU PU1 PU10 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P10) P10/SCK10/TxD0 WRPM PM1 PM10 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal 92 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P11 and P14 EVDD WRPU PU1 PU11, PU14 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P11, P14) P11/SI10/RxD0, P14/RxD6 WRPM PM1 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 93 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P12 and P15 EVDD WRPU PU1 PU12, PU15 P-ch Internal bus Selector RD WRPORT Output latch (P12, P15) P12/SO10 P15/TOH0 WRPM PM1 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal 94 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P13 EVDD WRPU PU1 PU13 P-ch Selector Internal bus RD WRPORT Output latch (P13) P13/TxD6 WRPM PM1 PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 95 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 EVDD WRPU PU1 PU16, PU17 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P16, P17) P16/TOH1/INTP5, P17/TI50/TO50 WRPM PM1 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal 96 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27 Internal bus RD A/D converter RD: P20/ANI0 to P27/ANI7 Read signal User's Manual U15947EJ3V1UD 97 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input and timer I/O. RESET input sets port 3 to input mode. Figures 4-12 and 4-13 show block diagrams of port 3. Figure 4-12. Block Diagram of P30 to P32 EVDD WRPU PU3 PU30 to PU32 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P30 to P32) P30/INTP1 to P32/INTP3 WRPM PM3 PM30 to PM32 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal 98 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P33 EVDD WRPU PU3 PU33 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P33) P33/INTP4/TI51/TO51 WRPM PM3 PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 99 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4). This port can also be used as an address/data bus in external memory expansion mode. RESET input sets port 4 to input mode. Figure 4-14 shows a block diagram of port 4. Figure 4-14. Block Diagram of P40 to P47 EVDD WRPU PU4 PU40 to PU47 Alternate function RD P-ch Selector WRPORT Internal bus Output latch (P40 to P47) Selector Alternate function WRPM PM4 PM40 to PM47 Memory expansion mode register (MEM) PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 100 User's Manual U15947EJ3V1UD P40/AD0 to P47/AD7 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (PU5). This port can also be used as an address bus in external memory expansion mode. RESET input sets port 5 to input mode. Figure 4-15 shows a block diagram of port 5. Figure 4-15. Block Diagram of P50 to P57 EVDD WRPU PU5 PU50 to PU57 P-ch RD Selector WRPORT Internal bus Output latch (P50 to P57) Selector P50/A8 to P57/A15 Alternate function WRPM PM5 PM50 to PM57 Memory expansion mode register (MEM) PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 101 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on the higher 4 bits/lower 4 bits of the port, and whether the product is a mask ROM version or a flash memory version. Table 4-4. Pull-up Resistor of Port 6 Higher 4 Bits (Pins P64 to P67) Mask ROM version Lower 4 Bits (Pins P60 to P63) An on-chip pull-up resistor can be An on-chip pull-up resistor can be connected in 1-bit units by PU6 specified in 1-bit units by mask option Flash memory version On-chip pull-up resistors are not provided PU6: Pull-up resistor option register 6 The P60 to P63 pins are N-ch open-drain pins. The P64 to P67 pins can also be used for the control signal output function in external memory expansion mode. RESET input sets port 6 to input mode. Figures 4-16 to 4-18 show block diagrams of port 6. Caution P66 can be used as an I/O port when an external wait is not used in external memory expansion mode. Figure 4-16. Block Diagram of P60 to P63 EVDD Mask option resistor RD Internal bus Selector WRPORT Output latch (P60 to P63) WRPM P60 to P63 PM6 PM60 to PM63 PM6: Port mode register 6 RD: Read signal WRxx: Write signal 102 Mask ROM versions only No pull-up resistor for flash memory versions User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P64, P65, and P67 EVDD WRPU PU6 PU64, PU65, PU67 P-ch RD Selector WRPORT Internal bus Output latch (P64, P65, P67) Selector P64/RD, P65/WR, P67/ASTB Alternate function WRPM PM6 PM64, PM65, PM67 Memory expansion mode register (MEM) PU6: Pull-up resistor option register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 103 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P66 EVDD WRPU PU6 PU66 Alternate function RD P-ch Internal bus Selector WRPORT Output latch (P66) WRPM Selector Memory expansion mode register (MEM) PM6 PM66 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal 104 User's Manual U15947EJ3V1UD P66/WAIT CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). This port can also be used for key return input. RESET input sets port 7 to input mode. Figure 4-19 shows a block diagram of port 7. Figure 4-19. Block Diagram of P70 to P77 EVDD WRPU PU7 PU70 to PU77 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P70 to P77) P70/KR0 to P77/KR7 WRPM PM7 PM70 to PM77 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 105 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used for external interrupt request input. RESET input sets port 12 to input mode. Figure 4-20 shows a block diagram of port 12. Figure 4-20. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P120) P120/INTP0 WRPM PM12 PM120 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal 106 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 4-21 shows a block diagram of port 13. Figure 4-21. Block Diagram of P130 Internal bus RD WRPORT Output latch (P130) RD: P130 Read signal WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. User's Manual U15947EJ3V1UD 107 CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, busy input, buzzer output, and clock output. RESET input sets port 14 to input mode. Figures 4-22 to 4-25 show block diagrams of port 14. Figure 4-22. Block Diagram of P140 and P141 EVDD WRPU PU14 PU140, PU141 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P140, P141) P140/PCL/INTP6, P141/BUZ/BUSY0/INTP7 WRPM PM14 PM140, PM141 Alternate function PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal 108 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P142 EVDD WRPU PU14 PU142 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P142) P142/SCKA0 WRPM PM14 PM142 Alternate function PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 109 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P143 EVDD WRPU PU14 PU143 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P143) P143/SIA0 WRPM PM14 PM143 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal 110 User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P144 and P145 EVDD WRPU PU14 PU144, PU145 P-ch Internal bus Selector RD WRPORT Output latch (P144, P145) P144/SOA0, P145/STB0 WRPM PM14 PM144, PM145 Alternate function PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal User's Manual U15947EJ3V1UD 111 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. * Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) * Port registers (P0 to P7, P12 to P14) * Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) (1) Port mode registers (PM0, PM1, PM3 to PM7, PM12, and PM14) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table 4-5. Figure 4-26. Format of Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W 7 6 5 4 3 2 1 0 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W 7 6 5 4 3 2 1 0 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H FFH R/W 7 6 5 4 3 2 1 0 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R/W 7 6 5 4 3 2 1 0 PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R/W 7 6 5 4 3 2 1 0 PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PM120 FF2CH FFH R/W 7 6 5 4 3 2 1 0 1 1 PM145 PM144 PM143 PM142 PM141 PM140 FF2EH FFH R/W PM1 PM3 PM4 PM5 PM12 PM14 Pmn pin I/O mode selection PMmn (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 112 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function Function Name PMxx Pxx I/O P00 TI000 Input 1 x P01 TI010 Input 1 x P02 SO11 P03 SI11 TO00 Note 1 Note 1 P04 SCK11 P05 SSI11 Note 1 0 0 Input 1 x Input 1 x Output 0 1 1 x Note 1 Input 1 x Note 1 Input 1 x TI011 Note 1 Output 0 0 Input 1 x Output 0 1 TxD0 Output 0 1 TO01 P10 0 0 Input Note 1 TI001 P06 Output Output SCK10 SI10 Input 1 x RxD0 Input 1 x P12 SO10 Output 0 0 P13 TxD6 Output 0 1 P11 P14 RxD6 Input 1 x P15 TOH0 Output 0 0 P16 TOH1 Output 0 0 INTP5 Input 1 x TI50 Input 1 x TO50 Output 0 0 P30 to P32 INTP1 to INTP3 Input 1 x P33 INTP4 Input 1 x P17 TI51 Input 1 x TO51 Output 0 0 P40 to P47 AD0 to AD7 I/O x Note 2 P50 to P57 A8 to A15 Output x Note 2 P64 RD Output x Note 2 P65 WR Output x Note 2 P66 WAIT Input P67 ASTB Output x Note 2 Note 2 1 x Note 2 Notes 1. SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 2. When using the alternate functions of the P40 to P47, P50 to P57, and P64 to P67 pins, select the 78F0148. function by using the memory expansion mode register (MEM). Remark x: Don't care PMxx: Port mode register Pxx: Port output latch User's Manual U15947EJ3V1UD 113 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function Function Name PMxx Pxx I/O P70 to P77 KR0 to KR7 Input 1 x P120 INTP0 Input 1 x P140 PCL Output 0 0 INTP6 Input 1 x BUZ Output 0 0 BUSY0 Input 1 x INTP7 Input 1 x P142 SCKA0 Input 1 x Output 0 1 P143 SIA0 Input 1 x P144 SOA0 Output 0 0 P145 STB0 Output 0 0 P141 Remark x: Don't care PMxx: Port mode register Pxx: 114 Port output latch User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H (but P2 is undefined). Figure 4-27. Format of Port Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 P06 P05 P04 P03 P02 P01 P00 FF00H 00H (output latch) R/W 7 6 5 4 3 2 1 0 P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 FF02H Undefined R 7 6 5 4 3 2 1 0 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 FF04H 00H (output latch) R/W 7 6 5 4 3 2 1 0 P5 P57 P56 P55 P54 P53 P52 P51 P50 FF05H 00H (output latch) R/W 7 6 5 4 3 2 1 0 P6 P67 P66 P65 P64 P63 P62 P61 P60 FF06H 00H (output latch) R/W 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 P120 FF0CH 00H (output latch) R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 P130 FF0DH 00H (output latch) R/W FF0EH 00H (output latch) R/W P2 P3 P4 P7 P12 P13 P14 7 6 5 4 3 2 1 0 0 0 P145 P144 P143 P142 P141 P140 m = 0 to 7, 12 to 14; n = 0 to 7 Pmn Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level User's Manual U15947EJ3V1UD 115 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, or P140 to P145 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. On-chip pull-up resistors cannot be connected for bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 to PU7, PU12, and PU14. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Caution Use of a pull-up resistor can be specified for P60 to P63 pins by a mask option only in the mask ROM versions. Figure 4-28. Format of Pull-up Resistor Option Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 FF30H 00H R/W 7 6 5 4 3 2 1 0 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W 7 6 5 4 3 2 1 0 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W 7 6 5 4 3 2 1 0 PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 FF34H 00H R/W 7 6 5 4 3 2 1 0 PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50 FF35H 00H R/W 7 6 5 4 3 2 1 0 PU67 PU66 PU65 PU64 0 0 0 0 FF36H 00H R/W 7 6 5 4 3 2 1 0 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W 7 6 5 4 3 2 1 0 0 0 PU145 PU144 PU143 PU142 PU141 PU140 FF3EH 00H R/W PU1 PU3 PU6 PU7 PU12 PU14 PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 116 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected User's Manual U15947EJ3V1UD CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. User's Manual U15947EJ3V1UD 117 CHAPTER 5 EXTERNAL BUS INTERFACE 5.1 External Bus Interface The external bus interface connects external devices to areas other than the internal ROM, RAM, and SFR areas. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc. The external bus interface is usable only when the X1 input clock is selected as the CPU clock. Caution The external bus interface function cannot be used in (A1) grade products and (A2) grade products. Table 5-1. Pin Functions in External Memory Expansion Mode Pin Function When External Device Is Connected Name Alternate Function Function AD0 to AD7 Multiplexed address/data bus P40 to P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 5-2. State of Ports 4 to 6 Pins in External Memory Expansion Mode External Port 4 Port 0 to 7 Expansion Mode Single-chip mode Port Port 5 0 1 Address/data Port 4 KB expansion mode Address/data Address 16 KB expansion mode Address/data Address Full-address mode Address/data Address 118 3 4 5 6 Port 256-byte expansion mode Caution 2 Port 6 7 0 1 2 3 4 5 6 7 Port Port Port Port RD, WR, WAIT, ASTB Port RD, WR, WAIT, ASTB Port RD, WR, WAIT, ASTB Port RD, WR, WAIT, ASTB When the external wait function is not used, the WAIT pin can be used as a port in all modes. User's Manual U15947EJ3V1UD CHAPTER 5 EXTERNAL BUS INTERFACE The memory maps when the external bus interface is used are as follows. Figure 5-1. Memory Map When Using External Bus Interface (1/2) (a) Memory map of PD780143 and of PD78F0148 when internal ROM (flash memory) size is 24 KB FFFFH (b) Memory map of PD780144 and of PD78F0148 when internal ROM (flash memory) size is 32 KB FFFFH SFR SFR FF00H FEFFH FF00H FEFFH Internal high-speed RAM FB00H FAFFH Internal high-speed RAM FB00H FAFFH Reserved Reserved FA20H FA1FH FA20H FA1FH Buffer RAM FA00H F9FFH Buffer RAM FA00H F9FFH Reserved Reserved F800H F7FFH F800H F7FFH Full-address mode (when MM2 to MM0 = 111) Full-address mode (when MM2 to MM0 = 111) C000H BFFFH A000H 9FFFH 16 KB expansion mode (when MM2 to MM0 = 101) 16 KB expansion mode (when MM2 to MM0 = 101) 9000H 8FFFH 4 KB expansion mode (when MM2 to MM0 = 100) 7000H 6FFFH 4 KB expansion mode (when MM2 to MM0 = 100) 6100H 60FFH 6000H 5FFFH 256-byte expansion mode (when MM2 to MM0 = 011) 8100H 80FFH 8000H 7FFFH 256-byte expansion mode (when MM2 to MM0 = 011) Single-chip mode Single-chip mode 0000H 0000H User's Manual U15947EJ3V1UD 119 CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-1. Memory Map When Using External Bus Interface (2/2) (c) Memory map of PD780146 and of PD78F0148 when internal ROM (flash memory) size is 48 KB (d) Memory map of PD780148 and of PD78F0148 when internal ROM (flash memory) size is 60 KB FFFFH FFFFH SFR FF00H FEFFH SFR FF00H FEFFH Internal high-speed RAM Internal high-speed RAM FB00H FAFFH FB00H FAFFH Reserved Reserved FA20H FA1FH FA20H FA1FH Buffer RAM FA00H F9FFH Buffer RAM FA00H F9FFH Reserved F800H F7FFH Reserved F800H F7FFH Internal expansion RAM Internal expansion RAM F400H F3FFH F400H F3FFH Full-address mode (when MM2 to MM0 = 111) or 16 KB expansion mode (when MM2 to MM0 = 101) or 4 KB expansion mode (when MM2 to MM0 = 100) Full-address mode (when MM2 to MM0 = 111) or 16 KB expansion mode (when MM2 to MM0 = 101) D000H CFFFH 4 KB expansion mode (when MM2 to MM0 = 100) C100H C0FFH C000H BFFFH 256-byte expansion mode (when MM2 to MM0 = 011) F100H F0FFH F000H EFFFH 256-byte expansion mode (when MM2 to MM0 = 011) Single-chip mode Single-chip mode 0000H 120 0000H User's Manual U15947EJ3V1UD CHAPTER 5 EXTERNAL BUS INTERFACE 5.2 Registers Controlling External Bus Interface The external bus interface is controlled by the following two registers. * Memory expansion mode register (MEM) * Memory expansion wait setting register (MM) (1) Memory expansion mode register (MEM) MEM sets the external expansion area. MEM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears MEM to 00H. Figure 5-2. Format of Memory Expansion Mode Register (MEM) Address: FF47H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 MEM 0 0 0 0 0 MM2 MM1 MM0 MM2 MM1 MM0 Single-chip/memory P40 to P47, P50 to P57, P64 to P67 pin state expansion mode selection P40 to P47 P50 to P53 P54, P55 0 0 0 Single-chip mode Port mode 0 1 1 Memory AD0 to 256-byte expansion mode 1 0 0 mode P56, P57 P64 to P67 P64 = RD Port mode AD7 P65 = WR Note 4 KB P66 = WAIT A8 to A11 Port mode P67 = ASTB mode 1 0 1 16 KB A12, A13 Port mode mode 1 1 1 Full-address A14, A15 mode Other than above Setting prohibited User's Manual U15947EJ3V1UD 121 CHAPTER 5 EXTERNAL BUS INTERFACE Note When the CPU accesses the external memory expansion area, the lower bits of the address to be accessed are output to the specified pins (except in the full-address mode). Figure 5-3. Pins Specified for Address (with PD780143) External Address Expansion Mode Accessed by CPU Pins Specified for Address A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 256-byte 6000H (0) (1) (1) (0) (0) (0) (0) (0) 0 0 0 0 0 0 0 0 expansion mode 6001H (0) (1) (1) (0) (0) (0) (0) (0) 0 0 0 0 0 0 0 1 6055H (0) (1) (1) (0) (0) (0) (0) (0) 0 1 0 1 0 1 0 1 60FEH (0) (1) (1) (0) (0) (0) (0) (0) 1 1 1 1 1 1 1 0 60FFH (0) (1) (1) (0) (0) (0) (0) (0) 1 1 1 1 1 1 1 1 4 KB 6000H (0) (1) (1) (0) 0 0 0 0 0 0 0 0 0 0 0 0 expansion mode 6001H (0) (1) (1) (0) 0 0 0 0 0 0 0 0 0 0 0 1 6100H (0) (1) (1) (0) 0 0 0 1 0 0 0 0 0 0 0 0 6FFFH (0) (1) (1) (0) 1 1 1 1 1 1 1 1 1 1 1 1 16 KB 6000H (0) (1) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 expansion mode 7000H (0) (1) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 8000H (1) (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9000H (1) (0) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 9FFFH (1) (0) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 6000H 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 6001H 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 F7FFH 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 Full-address mode Remark 122 The value in ( ) is not actually output. This pin can be used as a port pin. User's Manual U15947EJ3V1UD CHAPTER 5 EXTERNAL BUS INTERFACE (2) Memory expansion wait setting register (MM) MM sets the number of waits. MM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 5-4. Format of Memory Expansion Wait Setting Register (MM) Address: FFF8H After reset: 10H R/W Symbol 7 6 5 4 3 2 1 0 MM 0 0 PW1 PW0 0 0 0 0 PW1 PW0 0 0 No wait 0 1 Wait (one wait state inserted) 1 0 Setting prohibited 1 1 Wait control by external wait pin Wait control Cautions 1. To control wait with external wait pin, be sure to set WAIT/P66 pin to input mode (set bit 6 (PM66) of port mode register 6 (PM6) to 1). 2. If the external wait pin is not used for wait control, the WAIT/P66 pin can be used as an I/O port pin. User's Manual U15947EJ3V1UD 123 CHAPTER 5 EXTERNAL BUS INTERFACE 5.3 External Bus Interface Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data read and instruction fetch from external memory. During internal memory read, the read strobe signal is not output (maintains high level). (2) WR pin (Alternate function: P65) Write strobe signal output pin. The write strobe signal is output in data write to external memory. During internal memory write, the write strobe signal is not output (maintains high level). (3) WAIT pin (Alternate function: P66) External wait signal input pin. When the external wait is not used, the WAIT pin can be used as an I/O port. During internal memory access, the external wait signal is ignored. (4) ASTB pin (Alternate function: P67) Address strobe signal output pin. The address strobe signal is output regardless of data access and instruction fetch from external memory. During internal memory access, the address strobe signal is output. (5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57) Address/data signal output pins. Valid signal is output or input during data accesses and instruction fetches from external memory. These signals change even during internal memory access (output values are undefined). The timing charts are shown in Figures 5-5 to 5-8. 124 User's Manual U15947EJ3V1UD CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-5. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB RD AD0 to AD7 Lower address Instruction code Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB RD AD0 to AD7 Lower address Instruction code Higher address A8 to A15 Internal wait signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD AD0 to AD7 A8 to A15 Lower address Instruction code Higher address WAIT User's Manual U15947EJ3V1UD 125 CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-6. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB RD AD0 to AD7 Lower address Read data Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB RD AD0 to AD7 Lower address A8 to A15 Read data Higher address Internal wait signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD AD0 to AD7 A8 to A15 Lower address Read data Higher address WAIT 126 User's Manual U15947EJ3V1UD CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-7. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB WR AD0 to AD7 Hi-Z Lower address Write data Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB WR AD0 to AD7 Lower address Hi-Z Write data Higher address A8 to A15 Internal wait signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting ASTB WR AD0 to AD7 A8 to A15 Lower address Hi-Z Write data Higher address WAIT User's Manual U15947EJ3V1UD 127 CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-8. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB RD WR AD0 to AD7 Lower address Hi-Z Read data Write data Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB RD WR AD0 to AD7 Lower address Hi-Z Read data A8 to A15 Write data Higher address Internal wait signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD WR AD0 to AD7 A8 to A15 Lower address Hi-Z Read data Write data Higher address WAIT Remark 128 The read-modify-write timing is that of an operation when a bit manipulation instruction is executed. User's Manual U15947EJ3V1UD CHAPTER 5 EXTERNAL BUS INTERFACE 5.4 Example of Connection with Memory An example of connecting the PD780144 with external memory (in this example, SRAM) is shown in Figure 5-9. In addition, the external bus interface function is used in the full-address mode, and the addresses from 0000H to 7FFFH (32 KB) are allocated to internal ROM, and the addresses after 8000H to SRAM. Figure 5-9. Connection Example of PD780144 and Memory VDD PD780144 PD43256B CS RD OE WR WE I/O1 to I/O8 Data bus Address bus A8 to A14 ASTB A0 to A14 74HC573 LE Q0 to Q7 AD0 to AD7 D0 to D7 OE User's Manual U15947EJ3V1UD 129 CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. * X1 oscillator The X1 oscillator oscillates a clock of fXP = 2.0 to 12.0 MHzNote. Oscillation can be stopped by executing the STOP instruction or setting the main OSC control register (MOC) and processor clock control register (PCC). * Internal oscillator The internal oscillator oscillates a clock of fR = 240 kHz (TYP.). Oscillation can be stopped by setting the internal oscillation mode register (RCM) when "Can be stopped by software" is set by a mask option and the X1 input clock is used as the CPU clock. * Subsystem clock oscillator The subsystem clock oscillator oscillates a clock of fXT = 32.768 kHz. Oscillation cannot be stopped. When subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the processor clock control register (PCC), and the operating current can be reduced in the STOP mode. Note Expanded-specification products of standard products and (A) grade products: fXP = 2.0 to 12.0 MHz Conventional products of standard products and (A) grade products, (A1) grade products: fXP = 2.0 to 10.0 MHz (A2) grade products: fXP = 2.0 to 8.38 MHz Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Internal oscillation clock frequency 3. fXT: Subsystem clock oscillation frequency 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Control registers Configuration Processor clock control register (PCC) Internal oscillation mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Oscillator X1 oscillator Internal oscillator Subsystem clock oscillator 130 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR Figure 6-1. Block Diagram of Clock Generator Internal bus Main OSC control register (MOC) MCC CLS Oscillation stabilization time select register (OSTS) Main clock mode register (MCM) OSTS2 OSTS1 OSTS0 MCS MCM0 MSTOP Processor clock control register (PCC) CLS CSS PCC2 PCC1 PCC0 3 4 X1 oscillation stabilization time counter STOP Controller Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) Control signal C P U CPU clock (fCPU) X1 X1 oscillator X2 fXP fX Prescaler Operation clock switch Internal oscillator fX 22 fX 23 fX 24 fCPU Selector fX 2 fR Watch clock, clock output function Prescaler Clock to peripheral hardware Mask option 1: Cannot be stopped 0: Can be stopped Prescaler 1/2 fXT Subsystem clock oscillator XT1 XT2 FRC 8-bit timer H1, watchdog timer RSTOP Internal oscillation mode register (RCM) Internal bus User's Manual U15947EJ3V1UD 131 CHAPTER 6 CLOCK GENERATOR 6.3 Registers Controlling Clock Generator The following six registers are used to control the clock generator. * Processor clock control register (PCC) * Internal oscillation mode register (RCM) * Main clock mode register (MCM) * Main OSC control register (MOC) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop and whether to use the on-chip feedback resistorNote of the subsystem clock oscillator. PCC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PCC to 00H. Note The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage (see Figure 6-11 Subsystem Clock Feedback Resistor). 132 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 00H R/W Note 1 Symbol <7> <6> <5> <4> 3 2 1 0 PCC MCC FRC CLS CSS 0 PCC2 PCC1 PCC0 MCC Control of X1 oscillator operation 0 Oscillation possible 1 Oscillation stopped FRC Subsystem clock feedback resistor selection 0 On-chip feedback resistor used 1 On-chip feedback resistor not used Note 3 CLS CPU clock status 0 X1 input clock or internal oscillation clock 1 Subsystem clock CSS Note 4 Note 2 PCC2 PCC1 PCC0 CPU clock (fCPU) selection MCM0 = 0 0 0 0 1 0 0 2. 1 fX fR fX/2 fR/2 fXP Note 5 fXP/2 0 1 0 fX/2 2 0 1 1 fX/2 3 Setting prohibited fXP/2 3 1 0 0 fX/2 4 Setting prohibited fXP/2 4 0 0 0 fXT/2 0 0 1 0 1 0 0 1 1 1 0 0 Other than above Notes 1. 0 MCM0 = 1 Setting prohibited fXP/2 2 Setting prohibited Bit 5 is read-only. When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator operation. When the CPU is operating on the internal oscillation clock, use bit 7 (MSTOP) of the main OSC control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP instruction should not be used. 3. Clear this bit to 0 when the subsystem clock is used and set to 1 when the subsystem clock is not used. 4. Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register (MCM) are 1. 5. Setting is prohibited for the (A1) and (A2) grade products. Caution Be sure to clear bit 3 to 0. User's Manual U15947EJ3V1UD 133 CHAPTER 6 CLOCK GENERATOR Remarks 1. MCM0: Bit 0 of main clock mode register (MCM) 2. fX: Main system clock oscillation frequency (X1 input clock oscillation frequency or internal oscillation clock frequency) 3. fR: Internal oscillation clock frequency 4. fXP: X1 input clock oscillation frequency 5. fXT: Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KF1. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 6-2. Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU Note 1 Internal Oscillation Clock X1 Input Clock At 10 MHz At 12 MHz Operation Operation Note 1 Subsystem Clock (at 240 kHz (TYP.) Operation) (at 32.768 kHz Operation) Note 2 fX 0.2 s 0.166 s 8.3 s (TYP.) fX/2 - 0.4 s 0.333 s 16.6 s (TYP.) - fX/2 2 0.8 s 0.666 s Setting prohibited - fX/2 3 1.6 s 1.333 s Setting prohibited - fX/2 4 3.2 s 2.666 s Setting prohibited - Note 3 - fXT/2 Notes 1. 122.1 s - The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/internal oscillation clock) (see Figure 6-4). 2. Expanded-specification products of standard products and (A) grade products only 3. Setting is prohibited for the (A1) and (A2) grade products. (2) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. This register is valid when "Can be stopped by software" is set for internal oscillator by a mask option, and the X1 input clock or subsystem clock is selected as the CPU clock. If "Cannot be stopped" is selected for internal oscillator by a mask option, settings for this register are invalid. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-3. Format of Internal Oscillation Mode Register (RCM) Address: FFA0H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> RCM 0 0 0 0 0 0 0 RSTOP RSTOP Internal oscillator oscillating/stopped 0 Internal oscillator oscillating 1 Internal oscillator stopped Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting RSTOP. 134 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/internal oscillation clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-4. Format of Main Clock Mode Register (MCM) Address: FFA1H After reset: 00H R/W Note Symbol 7 6 5 4 3 2 <1> <0> MCM 0 0 0 0 0 0 MCS MCM0 MCS CPU clock status 0 Operates with internal oscillation clock 1 Operates with X1 input clock MCM0 Selection of clock supplied to CPU 0 Internal oscillation clock 1 X1 input clock Note Bit 1 is read-only. Cautions 1. When internal oscillation clock is selected as the clock to be supplied to the CPU, the divided clock of the internal oscillator output (fX) is supplied to the peripheral hardware (fX = 240 kHz (TYP.)). Operation of the peripheral hardware with internal oscillation clock cannot be guaranteed. Therefore, when internal oscillation clock is selected as the clock supplied to the CPU, do not use peripheral hardware. In addition, stop the peripheral hardware before switching the clock supplied to the CPU from the X1 input clock to the internal oscillation clock. Note, however, that the following peripheral hardware can be used when the CPU operates on the internal oscillation clock. * Watchdog timer * Clock monitor * 8-bit timer H1 when fR/27 is selected as count clock * Peripheral hardware selecting external clock as the clock source (Except when external count clock of TM0n (n = 0, 1) is selected (TI00n valid edge)) 2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1 input clock operation (bit 4 (CSS) of the processor clock control register (PCC) is changed from 1 to 0). User's Manual U15947EJ3V1UD 135 CHAPTER 6 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the internal oscillation clock. Therefore, this register is valid only when the CPU is operating with the internal oscillation clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-5. Format of Main OSC Control Register (MOC) Address: FFA2H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 MOC MSTOP 0 0 0 0 0 0 0 MSTOP Control of X1 oscillator operation 0 X1 oscillator operating 1 X1 oscillator stopped Cautions 1. Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting MSTOP. 2. To stop X1 oscillation when the CPU is operating on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is not possible). 136 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the internal oscillation clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP = 1, and MCC = 1 clear OSTC to 00H. Figure 6-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 OSTC 0 0 0 MOST11 MOST13 MOST11 MOST13 MOST14 MOST15 MOST16 1 1 1 1 1 6 5 0 4 0 1 0 0 1 0 0 1 1 0 0 1 1 3 0 1 1 0 1 1 2 MOST14 1 MOST15 0 MOST16 Oscillation stabilization time status When fXP = When fXP = 10 MHz 12 MHz Note 11 204.8 s min. 170.7 s min. 13 819.2 s min. 682.7 s min. 14 1.64 ms min. 1.37 ms min. 15 3.27 ms min. 2.73 ms min. 16 6.55 ms min. 5.46 ms min. 2 /fXP min. 2 /fXP min. 2 /fXP min. 2 /fXP min. 2 /fXP min. Note Expanded-specification products of standard products and (A) grade products only Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remark fXP: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD 137 CHAPTER 6 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU clock. After STOP mode is released with internal oscillation clock selected as CPU clock, the oscillation stabilization time must be confirmed by OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 6-7. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection When fXP = 10 MHz 0 0 0 1 1 11 204.8 s 170.7 s 13 819.2 s 682.7 s 14 1.64 ms 1.37 ms 15 3.27 ms 2.73 ms 16 6.55 ms 5.46 ms 2 /fXP 0 2 /fXP 0 1 1 2 /fXP 1 0 0 2 /fXP 1 0 1 2 /fXP Other than above Note When fXP = 12 MHz Setting prohibited Note Expanded-specification products of standard products and (A) grade products only Cautions 1. To set the STOP mode while the X1 input clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Before setting OSTS, confirm with OSTC that the desired oscillation stabilization time has elapsed. 3. If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remark 138 fXP: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.4 6.4.1 System Clock Oscillator X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator when the REGC pin is connected directly to VDD. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin. Figure 6-8 shows examples of the external circuit of the X1 oscillator. Figure 6-8. Examples of External Circuit of X1 Oscillator (a) Crystal, ceramic oscillation VSS X1 (b) External clock External clock X1 X2 X2 Crystal resonator or ceramic resonator 6.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (Standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator when the REGC pin is connected directly to VDD. In this case, input the clock signal to the XT1 pin and the inverse signal to the XT2 pin. Figure 6-9 shows examples of external circuit of the subsystem clock oscillator. Figure 6-9. Examples of External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock VSS XT1 External clock XT1 32.768 kHz XT2 XT2 Cautions are listed on the next page. User's Manual U15947EJ3V1UD 139 CHAPTER 6 CLOCK GENERATOR Caution When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 6-8 and 6-9 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-10 shows examples of incorrect resonator connection. Figure 6-10. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS Remark X1 X2 VSS X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. 140 X1 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR Figure 6-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 VSS High current VSS A X1 B X2 C High current (e) Signals are fetched VSS Remark X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. User's Manual U15947EJ3V1UD 141 CHAPTER 6 CLOCK GENERATOR 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect directly to EVSS or VSSNote XT2: Leave open Note This refers to connection in products with a rank other than K and I. For connection in the products with rank K or I, refer to Note 1 of Table 2-2 Pin I/O Circuit Types. When the subsystem clock is not used, set so that the use of the on-chip feedback resistor is disabled (setting bit 6 (FRC) of the processor clock control register (PCC) to 1) after a reset is released. Figure 6-11. Subsystem Clock Feedback Resistor FRC P-ch Feedback resistor XT1 Remark XT2 The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage. 6.4.4 Internal oscillator An internal oscillator is incorporated in the 78K0/KF1. "Can be stopped by software" or "Cannot be stopped" can be selected using a mask option. The internal oscillator always oscillates the internal oscillation clock after RESET release (240 kHz (TYP.)). 6.4.5 Prescaler The prescaler generates various clocks by dividing the X1 oscillator output when the X1 input clock is selected as the clock to be supplied to the CPU. Caution When the internal oscillation clock is selected as the clock supplied to the CPU, the prescaler generates various clocks by dividing the internal oscillator output (fX = 240 kHz (TYP.)). 142 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. * X1 input clock fXP * Internal oscillation clock fR * Subsystem clock fXT * CPU clock fCPU * Clock to peripheral hardware The CPU starts operation when the internal oscillator starts outputting after reset release in the 78K0/KF1, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the internal oscillation clock, so the device can be started by the internal oscillation clock after reset release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) Improvement of performance Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using internal oscillator is shown in Figure 6-12. User's Manual U15947EJ3V1UD 143 CHAPTER 6 CLOCK GENERATOR Figure 6-12. Timing Diagram of CPU Default Start Using Internal Oscillator X1 input clock (fXP) Internal oscillation clock (fR) Subsystem clock (fXT) RESET Switched by software Internal oscillation clock CPU clock X1 input clock Operation stopped: 17/fR X1 oscillation stabilization time: 211/fXP to 216/fXPNote Note Check using the oscillation stabilization time counter status register (OSTC). (a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is cleared to 0 and the internal oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the internal oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the RESET period, oscillation of the X1 input clock and internal oscillation clock is stopped. (b) After RESET release, the CPU clock can be switched from the internal oscillation clock to the X1 input clock using bit 0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1 (MCS) of MCM. (c) Internal oscillator can be set to stopped/oscillating using the internal oscillation mode register (RCM) when "Can be stopped by software" is selected for the internal oscillator by a mask option, if the X1 input or subsystem clock is used as the CPU clock. Make sure that MCS is 1 at this time. (d) When internal oscillation clock is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time. When the subsystem clock is used as the CPU clock, whether the X1 input clock stops or oscillates can be set by the processor clock control register (PCC). In addition, HALT mode can be used during operation with the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation cannot be stopped by the STOP instruction). (e) Select the X1 input clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using the oscillation stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and internal oscillation clock is being used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC). 144 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 6-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 6-3 and 6-4, respectively. Figure 6-13. Status Transition Diagram (1/4) (1) When "Internal oscillator can be stopped by software" is selected by mask option (when subsystem clock is not used) HALTNote 4 HALT instruction Interrupt Interrupt HALT instruction HALT instruction Status 4 RSTOP = 0 CPU clock: fXP fXP: Oscillating fR: Oscillation stopped RSTOP = 1Note 1 Interrupt Interrupt Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating STOP instruction MCM0 = 0 MCM0 = 1Note 2 Interrupt STOP instruction HALT instruction Interrupt MSTOP = 1Note 3 Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating MSTOP = 0 Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating STOP instruction Interrupt Interrupt STOP instruction STOPNote 4 Reset release ResetNote 5 Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register 2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock (MCM) is 1. oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 3. When shifting from status 2 to status 1, make sure that MCS is 0. 4. When "Internal oscillator can be stopped by software" is selected by a mask option, the watchdog timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer. However, oscillation of internal oscillator does not stop even in the HALT and STOP modes if RSTOP = 0. 5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15947EJ3V1UD 145 CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (2/4) (2) When "Internal oscillator can be stopped by software" is selected by mask option (when subsystem clock is used) Status 6 CPU clock: fXT fXP: Oscillation stopped fR: Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1 HALT instruction Status 5 CPU clock: fXT fXP: Oscillating fR: Oscillating/ oscillation stopped Interrupt HALTNote 4 HALT instruction HALT instruction Interrupt HALT instruction Interrupt CSS = 0Note 5 CSS = 1Note 5 Status 4 Status 3 CPU clock: fXP RSTOP = 0 CPU clock: fXP fXP: Oscillating fXP: Oscillating fR: Oscillation RSTOP = 1Note 1 fR: Oscillating stopped HALT instruction Interrupt Status 1 Status 2 MCM0 = 0 MSTOP = 1Note 3 CPU clock: fR CPU clock: fR fXP: Oscillation fXP: Oscillating stopped MCM0 = 1Note 2 fR: Oscillating MSTOP = 0 fR: Oscillating STOP STOP instruction instruction Interrupt Interrupt STOP instruction Interrupt STOPNote 4 Reset release ResetNote 6 Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1. 2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 3. 4. When shifting from status 2 to status 1, make sure that MCS is 0. When "Internal oscillator can be stopped by software" is selected by a mask option, the clock supply to the watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless of the setting of bit 0 (RSTOP) of the internal oscillation mode register (RCM) and bit 0 (MCM0) of the main clock mode register (MCM). 5. The operation cannot be shifted between subsystem clock operation and internal oscillation clock operation. 6. 146 All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (3/4) (3) When "Internal oscillator cannot be stopped" is selected by mask option (when subsystem clock is not used) HALT Interrupt Interrupt HALT instruction Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating MCM0 = 0 MCM0 = 1Note 1 Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating HALT instruction MSTOP = 1Note 2 MSTOP = 0 Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating STOP instruction Interrupt STOP instruction HALT instruction Interrupt STOP instruction Interrupt STOPNote 3 Interrupt Reset release ResetNote 4 Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 2. 3. When shifting from status 2 to status 1, make sure that MCS is 0. The watchdog timer operates using internal oscillation clock even in STOP mode if "Internal oscillator cannot be stopped" is selected by a mask option. Internal oscillation clock division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution. 4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15947EJ3V1UD 147 CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (4/4) (4) When "Internal oscillator cannot be stopped" is selected by mask option (when subsystem clock is used) Status 5 CPU clock: fXT fXP: Oscillation stopped fR: Oscillating Interrupt MCC = 0 MCC = 1 HALT instruction Status 4 CPU clock: fXT fXP: Oscillating fR: Oscillating Interrupt HALT HALT instruction Interrupt CSS = 0Note 4 Interrupt HALT instruction CSS = 1Note 4 Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating MCM0 = 0 MCM0 = 1Note 1 Interrupt Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating MSTOP = 1Note 2 MSTOP = 0 Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating STOP instruction Interrupt STOP instruction HALT instruction HALT instruction STOP instruction Interrupt STOPNote 3 Interrupt Reset release ResetNote 5 Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 2. When shifting from status 2 to status 1, make sure that MCS is 0. 3. The watchdog timer operates using internal oscillation clock even in STOP mode if "Internal oscillator cannot be stopped" is selected by a mask option. Internal oscillation clock division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution. 4. The operation cannot be shifted between subsystem clock operation and internal oscillation clock operation. 5. 148 All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR Table 6-3. Relationship Between Operation Clocks in Each Operation Status Status Operation X1 Oscillator MSTOP = 0 MSTOP = 1 MCC = 0 Mode Reset Internal Oscillator Note 1 MCC = 1 Subsystem CPU Clock Note 2 RSTOP = 0 RSTOP = 1 After Oscillator Release Oscillating Internal Stopped Stopped Clock Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1 Stopped oscillation STOP Oscillating Oscillating Stopped HALT Oscillating Stopped Note 3 Stopped Note 4 Internal X1 oscillation Notes 1. 2. When "Cannot be stopped" is selected for internal oscillator by a mask option. When "Can be stopped by software" is selected for internal oscillator by a mask option. 3. Operates using the CPU clock at STOP instruction execution. 4. Operates using the CPU clock at HALT instruction execution. Caution The RSTOP setting is valid only when "Can be stopped by software" is set for internal oscillator by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: Bit 7 of the processor clock control register (PCC) RSTOP: Bit 0 of the internal oscillation mode register (RCM) MCM0: Bit 0 of the main clock mode register (MCM) Table 6-4. Oscillation Control Flags and Clock Oscillation Status X1 Oscillator MSTOP = 1 Note MSTOP = 0 Note RSTOP = 0 Stopped RSTOP = 1 Setting prohibited RSTOP = 0 Oscillating RSTOP = 1 MCC = 1 Note MCC = 0 Note RSTOP = 0 Oscillating Oscillating Stopped Stopped RSTOP = 1 RSTOP = 0 Internal Oscillator Oscillating Stopped Oscillating RSTOP = 1 Oscillating Stopped Note Setting X1 oscillator oscillating/stopped differs depending on the CPU clock used. * When the internal oscillation clock is used as the CPU clock: Set using the MSTOP bit * When the subsystem clock is used as the CPU clock: Set using the MCC bit Caution The RSTOP setting is valid only when "Can be stopped by software" is set for internal oscillator by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: Bit 7 of the processor clock control register (PCC) RSTOP: Bit 0 of the internal oscillation mode register (RCM) User's Manual U15947EJ3V1UD 149 CHAPTER 6 CLOCK GENERATOR 6.6 Time Required to Switch Between Internal Oscillation Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the internal oscillation clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 6-5). Bit 1 (MCS) of MCM is used to judge that operation is performed using either the internal oscillation clock or X1 input clock. To stop the original clock after switching the clock, wait for the number of clocks shown in Table 6-5. Table 6-5. Maximum Time Required to Switch Between Internal Oscillation Clock and X1 Input Clock PCC Time Required for Switching X1Internal oscillation PCC2 PCC1 PCC0 0 0 0 fXP/fR + 1 clock 0 0 1 fXP/2fR + 1 clock Internal oscillationX1 2 clocks Note Note 2 clocks Note Setting is prohibited for the (A1) and (A2) grade products. Caution To calculate the maximum time, set fR = 120 kHz. Remarks 1. PCC: Processor clock control register 2. fXP: X1 input clock oscillation frequency 3. fR: Internal oscillation clock frequency 4. The maximum time is the number of clocks of the CPU clock before switching. 150 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.7 Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 6-6). Whether the system is operating on the X1 input clock (or internal oscillation clock) or the subsystem clock can be ascertained using bit 5 (CLS) of the PCC register. Table 6-6. Maximum Time Required for CPU Clock Switchover Set Value Before Set Value After Switchover Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 0 0 0 0 0 0 0 0 0 1 16 clocks 0 0 1 0 0 16 clocks 0 1 16 clocks 1 0 1 0 0 16 clocks 1 x x x 2fXP/fXT clocks (733 clocks) 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks fXP/fXT clocks (367 clocks) 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks fXP/2fXT clocks (184 clocks) 0 1 1 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 clock 1 clock 2 clocks fXP/4fXT clocks (92 clocks) fXP/8fXT clocks 1 clock (46 clocks) 1 x x x 2 clocks 2 clocks 2 clocks 2 clocks 2 clocks Cautions 1. Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1 input clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS from 1 to 0). 2. Setting the following values is prohibited when the CPU operates on the internal oscillation clock. * CSS, PCC2, PCC1, PCC0 = 0, 0, 0, 1 (settable only for standard products and (A) grade products) * CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 0 * CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 1 * CSS, PCC2, PCC1, PCC0 = 0, 1, 0, 0 Remarks 1. The maximum time is the number of clocks of the CPU clock before switching. 2. Figures in parentheses apply to operation with fXP = 12 MHz and fXT = 32.768 kHz. User's Manual U15947EJ3V1UD 151 CHAPTER 6 CLOCK GENERATOR 6.8 Clock Switching Flowchart and Register Setting 6.8.1 Switching from internal oscillation clock to X1 input clock Figure 6-14. Switching from Internal Oscillation Clock to X1 Input Clock (Flowchart) After reset release PCC = 00H RCM = 00H MCM = 00H MOC = 00H OSTC = 00H OSTS = 05HNote Register initial value after reset ; fCPU = fR ; Internal oscillation ; Internal oscillation clock operation ; X1 oscillation ; Oscillation stabilization time status register ; Oscillation stabilization time fXP/216 Each processing OSTC checkNote Internal oscillation clock operation ; X1 oscillation stabilization time status check X1 oscillation stabilization time has not elapsed X1 oscillation stabilization time has elapsed PCC setting Internal oscillation clock operation (dividing set PCC) MCM.0 1 MCM.1 (MCS) is changed from 0 to 1 X1 input clock operation X1 input clock operation Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register and then switch to the X1 input clock operation after the oscillation stabilization wait time has elapsed. The OSTS register setting is valid only after STOP mode is released by interrupt during X1 input clock operation. 152 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.8.2 Switching from X1 input clock to internal oscillation clock Figure 6-15. Switching from X1 Input Clock to Internal Oscillation Clock (Flowchart) Register setting in X1 input clock operation PCC.7 (MCC) = 0 PCC.4 (CSS) = 0 MCM = 03H ; X1 oscillation ; X1 input clock or internal oscillation clock ; X1 input clock operation RCM.0Note (RSTOP) = 1? ; Internal oscillator oscillating? Yes: RSTOP = 1 X1 input clock operation No: RSTOP = 0 RSTOP = 0 MCM0 0 ; Internal oscillation clock operation MCM.1 (MCS) is changed from 1 to 0 Internal oscillation clock operation Internal oscillation clock operation Note Required only when "Can be stopped by software" is selected for internal oscillator by a mask option. User's Manual U15947EJ3V1UD 153 CHAPTER 6 CLOCK GENERATOR 6.8.3 Switching from X1 input clock to subsystem clock Figure 6-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart) Register setting in X1 input clock operation PCC.7 (MCC) = 0 PCC.4 (CSS) = 0 MCM = 03H ; X1 oscillation ; X1 input clock or internal oscillation clock ; X1 input clock operation X1 input clock operation CSS 1Note ; Subsystem clock operation MCS = 1 not changed. CLS is changed from 0 to 1. Subsystem clock Subsystem clock operation Note Set CSS to 1 after confirming that oscillation of the subsystem clock is stabilized. 154 User's Manual U15947EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.8.4 Switching from subsystem clock to X1 input clock Figure 6-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart) PCC.4 (CSS) = 1 MCM = 03H ; Subsystem clock operation No: X1 oscillating MCC = 1? ; X1 oscillating? Yes: X1 oscillation stopped MCC 0 ; X1 oscillation enabled Subsystem clock operation OSTC check X1 oscillation stabilization time not elapsed ; Wait for X1 oscillation stabilization time X1 oscillation stabilization time elapsed CSS 0 ; X1 input clock operation CLS is changed from 1 to 0. MCS = 1 not changed. X1 input clock operation X1 input clock operation User's Manual U15947EJ3V1UD 155 CHAPTER 6 CLOCK GENERATOR 6.8.5 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 6-7. Clock and Register Setting fCPU Mode Setting Flag PCC Register MCM Status Flag MOC RCM PCC MCM Register Register Register Register Register X1 input MCC CSS MCM0 Note 1 MSTOP RSTOP CLS MCS Internal oscillator oscillating 0 0 1 0 0 0 1 clock Internal oscillator stopped 0 0 1 0 1 0 1 Internal X1 oscillating 0 0 0 0 0 0 0 1 Note 2 oscillation clock X1 stopped Subsystem 0 X1 oscillating, internal oscillator oscillating Note 3 0 0 1 0 1 Note 5 1 Note 5 1 Note 5 1 Note 5 Note 4 clock X1 stopped, internal oscillator oscillating X1 oscillating, internal oscillator stopped X1 stopped, internal oscillator stopped Notes 1. 2. 1 0 1 1 1 1 0 0 0 0 Note 6 0 1 1 0 Note 6 0 1 1 0 Note 6 1 1 1 0 Note 6 1 1 1 Valid only when "Can be stopped by software" is selected for internal oscillator by a mask option. Do not set MCC = 1 or MSTOP = 1 during X1 input clock operation (even if MCC = 1 or MSTOP = 1 is set, the X1 oscillation does not stop). 3. Do not set MCC = 1 during internal oscillation clock operation (even if MCC = 1 is set, the X1 oscillation 4. Shifting to subsystem clock operation mode must be performed from the X1 input clock operation mode. does not stop). To stop X1 oscillation during internal oscillation clock operation, use MSTOP. From subsystem clock operation mode, only X1 input clock operation mode can be shifted to. 5. 6. Do not set MCM0 = 0 (shifting to internal oscillation clock operation) during subsystem clock operation. Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, X1 oscillation does not stop). To stop X1 oscillation during subsystem clock operation, use MCC. 156 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The PD780143 and 780144 incorporate 16-bit timer/event counter 00, and the PD780146, 780148, and 78F0148 incorporate 16-bit timer/event counters 00 and 01. 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01Note have the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output (1) Interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) PPG output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (3) Pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. (4) External event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (5) Square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (6) One-shot pulse output 16-bit timer/event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. Note Available only for the PD780146, 780148, and 78F0148. User's Manual U15947EJ3V1UD 157 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Configuration Timer counter 16 bits (TM0n) Register 16-bit timer capture/compare register: 16 bits (CR00n, CR01n) Timer input TI00n, TI01n Timer output TO0n, output controller Control registers 16-bit timer mode control register 0n (TMC0n) 16-bit timer capture/compare control register 0n (CRC0n) 16-bit timer output control register 0n (TOC0n) Prescaler mode register 0n (PRM0n) Port mode register 0 (PM0) Port register 0 (P0) PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Remark n = 0: Figures 7-1 and 7-2 show the block diagrams. Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) Selector CRC002CRC001 CRC000 Noise eliminator TI010/TO00/P01 Selector To CR010 16-bit timer capture/compare register 000 (CR000) INTTM000 Match Noise eliminator 16-bit timer counter 00 (TM00) Output controller TO00/TI010/ P01 Match 2 Output latch (P01) Noise eliminator TI000/P00 Clear PM01 16-bit timer capture/compare register 010 (CR010) Selector fX Selector fX fX/22 fX/28 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) 158 TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 (PD780146, 780148, and 78F0148 Only) Internal bus Capture/compare control register 01 (CRC01) Selector CRC012CRC011 CRC010 Noise eliminator TI011/TO01/P06 Selector To CR011 16-bit timer capture/compare register 001 (CR001) INTTM001 Match Noise eliminator 16-bit timer counter 01 (TM01) Output controller TO01/TI011/ P06 Match 2 Output latch (P06) Noise eliminator TI001/P05 Clear PM06 16-bit timer capture/compare register 011 (CR011) Selector fX Selector fX fX/24 fX/26 INTTM011 CRC012 PRM011 PRM010 Prescaler mode register 01 (PRM01) TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) Internal bus User's Manual U15947EJ3V1UD 159 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) Symbol After reset: 0000H FF11H (TM00) FFB1H (TM01) R FF10H (TM00) FFB0H (TM01) TM0n (n = 0, 1) The count value is reset to 0000H in the following cases. <1> At RESET input <2> If TMC0n3 and TMC0n2 are cleared <3> If the valid edge of TI00n is input in the mode in which clear & start occurs when inputting the valid edge of TI00n <4> If TM0n and CR00n match in the mode in which clear & start occurs on a match of TM0n and CR00n <5> OSPT0n is set to 1 in one-shot pulse output mode (2) 16-bit timer capture/compare register 00n (CR00n) CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register 0n (CRC0n). CR00n can be set by a 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) Symbol After reset: 0000H FF13H (CR000) FFB3H (CR001) R/W FF12H (CR000) FFB2H (CR001) CR00n (n = 0, 1) * When CR00n is used as a compare register The value set in CR00n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM00n) is generated if they match. The set value is held until CR00n is rewritten. * When CR00n is used as a capture register It is possible to select the valid edge of the TI00n pin or the TI01n pin as the capture trigger. The TI00n or TI01n pin valid edge is set using prescaler mode register 0n (PRM0n) (see Table 7-2). 160 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge Rising edge 0 1 Rising edge Falling edge 0 0 No capture operation Both rising and falling edges 1 1 ES1n1 ES1n0 (2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1) CR00n Capture Trigger TI01n Pin Valid Edge Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES0n1, ES0n0 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited. 2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n) ES1n1, ES1n0: Bits 7 and 6 of prescaler mode register 0n (PRM0n) CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n) 3. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Cautions 1. Set a value other than 0000H to CR00n in the mode in which clear & start occurs on a match of TM0n and CR00n. 2. If CR00n is set to 0000H in the free-running mode and in the clear mode using the valid edge of the TI00n pin, an interrupt request (INTTM00n) is generated when the value of CR00n changes from 0000H to 0001H following TM0n overflow (FFFFH). Moreover, INTTM00n is generated after a match of TM0n and CR00n is detected, a valid edge of the TI01n pin is detected, or the timer is cleared by a one-shot trigger. 3. When the valid edge of the TI01n pin is used, P01 or P06 cannot be used as the timer output (TO0n) pin. Moreover, when the TO0n pin is used, the valid edge of the TI01n pin cannot be used. 4. When CR00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If timer count stop and capture trigger input conflict, the captured data is undefined. 5. Do not rewrite CR00n during TM0n operation. User's Manual U15947EJ3V1UD 161 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n (CRC0n). CR01n can be set by a 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n) Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) Symbol After reset: 0000H FF15H (CR010) FFB5H (CR011) R/W FF14H (CR010) FFB4H (CR011) CR01n (n = 0, 1) * When CR01n is used as a compare register The value set in the CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten. * When CR01n is used as a capture register It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n valid edge is set by prescaler mode register 0n (PRM0n) (see Table 7-3). Table 7-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1) CR01n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES0n1, ES0n0 = 1, 0 is prohibited. 2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n) CRC0n2: Bit 2 of capture/compare control register 0n (CRC0n) 3. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated when the value changes from 0000H to 0001H after an overflow (FFFFH) of TM0n. Moreover, INTTM01n is generated after a match of TM0n and CR01n is detected, a valid edge of the TI00n pin is detected, or the timer is cleared by a one-shot trigger. 2. When CR01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 7-20. 162 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 0n (TMC0n) This register sets the 16-bit timer operating mode, 16-bit timer counter 0n (TM0n) clear mode, and output timing, and detects an overflow. TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC0n to 00H. Caution 16-bit timer counter 0n (TM0n) starts operation at the moment TMC0n2 and TMC0n3 are set to values other than 0, 0 (operation stop mode), respectively. Clear TMC0n2 and TMC0n3 to 0, 0 to stop the operation. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD 163 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol 7 6 5 4 TMC00 0 0 0 0 R/W 3 2 1 <0> TMC003 TMC002 TMC001 OVF00 Operating mode and clear TMC003 TMC002 TMC001 TO00 inversion timing selection Interrupt request generation mode selection 0 0 0 Operation stop 0 0 1 (TM00 cleared to 0) 0 1 0 Free-running mode 0 1 1 No change Not generated Match between TM00 and <When used as compare CR000 or match between register> TM00 and CR010 Generated on match between Match between TM00 and TM00 and CR000, or match CR000, match between TM00 between TM00 and CR010 and CR010 or TI000 valid edge <When used as capture - 1 0 0 Clear & start occurs on TI000 1 0 1 valid edge 1 1 0 Clear & start occurs on match Match between TM00 and between TM00 and CR000 CR000 or match between register> Generated by inputting CR000 capture trigger TM00 and CR010 1 1 Match between TM00 and 1 CR000, match between TM00 and CR010 or TI000 valid edge OVF00 16-bit timer counter 00 (TM00) overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag. 2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00). 3. If any of the following modes is selected: the mode in which clear & start occurs on match between TM00 and CR000, the mode in which clear & start occurs at the TI000 valid edge, or free-running mode, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. Remarks 1. TO00: 16-bit timer/event counter 00 output pin 2. TI000: 16-bit timer/event counter 00 input pin 3. TM00: 16-bit timer counter 00 4. CR000: 16-bit timer capture/compare register 000 5. CR010: 16-bit timer capture/compare register 010 164 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol 7 6 5 4 TMC01 0 0 0 0 R/W 3 2 1 <0> TMC013 TMC012 TMC011 OVF01 Operating mode and clear TMC013 TMC012 TMC011 TO01 inversion timing selection Interrupt request generation mode selection 0 0 0 Operation stop 0 0 1 (TM01 cleared to 0) 0 1 0 Free-running mode 0 1 1 No change Not generated Match between TM01 and <When used as compare CR001 or match between register> TM01 and CR011 Generated on match between Match between TM01 and TM01 and CR001, or match CR001, match between TM01 between TM01 and CR011 and CR011 or TI001 valid edge <When used as capture - 1 0 0 Clear & start occurs on TI001 1 0 1 valid edge 1 1 0 Clear & start occurs on match Match between TM01 and between TM01 and CR001 CR001 or match between register> Generated by inputting CR001 capture trigger TM01 and CR011 1 1 Match between TM01 and 1 CR001, match between TM01 and CR011 or TI001 valid edge OVF01 16-bit timer counter 01 (TM01) overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1. Timer operation must be stopped before writing to bits other than the OVF01 flag. 2. Set the valid edge of the TI001/P05 pin using prescaler mode register 01 (PRM01). 3. If any of the following modes is selected: the mode in which clear & start occurs on match between TM01 and CR001, the mode in which clear & start occurs at the TI001 valid edge, or free-running mode, when the set value of CR001 is FFFFH and the TM01 value changes from FFFFH to 0000H, the OVF01 flag is set to 1. Remarks 1. TO01: 16-bit timer/event counter 01 output pin 2. TI001: 16-bit timer/event counter 01 input pin 3. TM01: 16-bit timer counter 01 4. CR001: 16-bit timer capture/compare register 001 5. CR011: 16-bit timer capture/compare register 011 User's Manual U15947EJ3V1UD 165 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0n to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC001 CR000 capture trigger selection 0 Captures on valid edge of TI010 1 Captures on valid edge of TI000 by reverse phase CRC000 Note CR000 operating mode selection 0 Operates as compare register 1 Operates as capture register Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of TI000. Cautions 1. Timer operation must be stopped before setting CRC00. 2. When the mode in which clear & start occurs on a match between TM00 and CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. To ensure that the capture operation is performed properly, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00). 166 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC01 0 0 0 0 0 CRC012 CRC011 CRC010 CRC012 CR011 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC011 CR001 capture trigger selection 0 Captures on valid edge of TI011 1 Captures on valid edge of TI001 by reverse phase CRC010 Note CR001 operating mode selection 0 Operates as compare register 1 Operates as capture register Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of TI001. Cautions 1. Timer operation must be stopped before setting CRC01. 2. When the mode in which clear & start occurs on a match between TM01 and CR001 is selected with 16-bit timer mode control register 01 (TMC01), CR001 should not be specified as a capture register. 3. To ensure that the capture operation is performed properly, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 01 (PRM01). (3) 16-bit timer output control register 0n (TOC0n) This register controls the operation of 16-bit timer/event counter 0n output controller. It sets/resets the timer output F/F (LV0n), enables/disables output inversion and 16-bit timer/event counter 0n timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TOC0n to 00H. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 167 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-10. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software 0 No one-shot pulse output trigger 1 One-shot pulse output trigger OSPE00 One-shot pulse output operation control 0 Successive pulse output mode 1 One-shot pulse output mode TOC004 Note Timer output F/F control using match of CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation LVS00 LVR00 Timer output F/F status setting 0 0 No change 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TOC001 Timer output F/F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output control 0 Disables output (output fixed to level 0) 1 Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than TOC004. 2. If LVS00 and LVR00 are read, 0 is read. 3. OSPT00 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT00 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required to write to OSPT00 successively. 6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously. 7. Perform <1> and <2> below in the following order, not at the same time. <1> Set TOC001, TOC004, TOE00, OSPE00: Timer output operation setting <2> Set LVS00, LVR00: Timer output F/F setting 168 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC01 0 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger control via software 0 No one-shot pulse output trigger 1 One-shot pulse output trigger OSPE01 One-shot pulse output operation control 0 Successive pulse output mode 1 One-shot pulse output mode TOC014 Note Timer output F/F control using match of CR011 and TM01 0 Disables inversion operation 1 Enables inversion operation LVS01 LVR01 Timer output F/F status setting 0 0 No change 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TOC011 Timer output F/F control using match of CR001 and TM01 0 Disables inversion operation 1 Enables inversion operation TOE01 Timer output control 0 Disables output (output fixed to level 0) 1 Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI001 valid edge. In the mode in which clear & start occurs on a match between the TM01 register and CR001 register, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than TOC014. 2. If LVS01 and LVR01 are read, 0 is read. 3. OSPT01 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT01 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 01 (PRM01) is required to write to OSPT01 successively. 6. Do not set LVS01 to 1 before TOE01, and do not set LVS01 and TOE01 to 1 simultaneously. 7. Perform <1> and <2> below in the following order, not at the same time. <1> Set TOC011, TOC014, TOE01, OSPE01: Timer output operation setting <2> Set LVS01, LVR01: Timer output F/F setting User's Manual U15947EJ3V1UD 169 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n and TI01n input valid edges. PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM0n to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 7-12. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM00 ES101 ES100 ES001 ES000 0 0 PRM001 PRM000 ES101 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES001 ES000 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges PRM001 PRM000 0 0 fX (10 MHz) 0 1 fX/2 (2.5 MHz) 1 0 fX/2 (39.06 kHz) 1 1 TI000 valid edge Notes 1. TI010 valid edge selection TI000 valid edge selection Note 1 Count clock selection 2 8 Note 2 Set the count clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock 2.5 MHz 2. 170 The external clock requires a pulse longer than two cycles of the internal clock (fX). User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an external clock is used and when the internal oscillation clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to eliminate noise. 2. Always set data to PRM00 after stopping the timer operation. 3. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI000 and the capture trigger. 4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, if the TI000 pin or TI010 pin is high level when re-enabling operation after the operation has been stopped, the rising edge is not detected. 5. When the valid edge of the TI010 pin is used, P01 cannot be used as the timer output (TO00) pin. Moreover, when the TO00 pin is used, the valid edge of the TI010 pin cannot be used. Remarks 1. fX: X1 input clock oscillation frequency 2. TI000, TI010: 16-bit timer/event counter 00 input pin 3. Figures in parentheses are for operation with fX = 10 MHz. User's Manual U15947EJ3V1UD 171 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-13. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM01 ES111 ES110 ES011 ES010 0 0 PRM011 PRM010 ES111 ES110 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES011 ES010 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges PRM011 PRM010 0 0 fX (10 MHz) 0 1 fX/2 (625 kHz) 1 0 fX/2 (156.25 kHz) 1 1 TI001 valid edge Notes 1. TI011 valid edge selection TI001 valid edge selection Note 1 Count clock selection 4 6 Note 2 Set the count clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock 2.5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fX). Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 16-bit timer/event counter 01 is not guaranteed. When an external clock is used and when the internal oscillation clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 01 is not guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to eliminate noise. 2. Always set data to PRM01 after stopping the timer operation. 3. If the valid edge of TI001 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI001 and the capture trigger. 4. If the TI001 or TI011 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI001 pin or TI011 pin to enable the operation of 16-bit timer counter 01 (TM01). Care is therefore required when pulling up the TI001 or TI011 pin. However, if the TI001 pin or TI011 pin is high level when re-enabling operation after the operation has been stopped, the rising edge is not detected. 5. When the valid edge of the TI011 pin is used, P06 cannot be used as the timer output (TO01) pin. Moreover, when the TO01 pin is used, the valid edge of the TI011 pin cannot be used. 172 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Remarks 1. fX: X1 input clock oscillation frequency 2. TI001, TI011: 16-bit timer/event counter 01 input pin 3. Figures in parentheses are for operation with fX = 10 MHz. (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01Note/TI011Note pins for timer output, clear PM01 and PM06 and the output latches of P01 and P06 to 0. When using the P01/TO00/TI010 and P06/TO01Note/TI011Note pins for timer input, set PM01 and PM06 to 1. At this time, the output latches of P01 and P06 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 to FFH. Figure 7-14. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH 6 5 4 R/W Symbol 7 3 2 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 6) 0 Output mode (output buffer on) 1 Input mode (output buffer off) 1 0 Note Available only for the PD780146, 780148, and 78F0148. User's Manual U15947EJ3V1UD 173 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-15 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-15 for the set value). <2> Set any value to the CR00n register. <3> Set the count clock by using the PRM0n register. <4> Set the TMC0n register to start the operation (see Figure 7-15 for the set value). Caution Do not rewrite CR00n during TM0n operation. Remark For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (CR00n) as the interval. When the count value of 16-bit timer counter 0n (TM0n) matches the value set in CR00n, counting continues with the TM0n value cleared to 0 and the interrupt request signal (INTTM00n) is generated. The count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register 0n (PRM0n). Remark 174 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-15. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0/1 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0/1 0/1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remarks 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. 2. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-16. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n Selector fX (fX)Note 1 fX/22 (fX/24)Note 1 fX/28 (fX/26)Note 1 TI000/P00 (TI001/P05)Note 1 Note 2 16-bit timer counter 0n (TM0n) OVF0n Noise eliminator Clear circuit fX Notes 1. Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. 2. OVF0n is set to 1 only when 16-bit timer capture/compare register 00n is set to FFFFH. Figure 7-17. Timing of Interval Timer Operation t Count clock TM0n count value 0000H 0001H N Timer operation enabled CR00n 0000H 0001H Clear N N N 0000H 0001H Clear N N INTTM00n Interrupt acknowledged Remark Interval time = (N + 1) x t N = 0001H to FFFFH (settable range) n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 176 User's Manual U15947EJ3V1UD N Interrupt acknowledged CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-18 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-18 for the set value). <2> Set any value to the CR00n register as the cycle. <3> Set any value to the CR01n register as the duty factor. <4> Set the TOC0n register (see Figure 7-18 for the set value). <5> Set the count clock by using the PRM0n register. <6> Set the TMC0n register to start the operation (see Figure 7-18 for the set value). Caution To change the value of the duty factor (the value of the CR01n register) during operation, see Caution 2 in Figure 7-20 PPG Output Operation Timing. Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. In the PPG output operation, rectangular waves are output from the TO0n pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 01n (CR01n) and in 16-bit timer capture/compare register 00n (CR00n), respectively. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 0 x 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 1 0/1 0/1 1 1 Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited). Inverts output on match between TM0n and CR01n. Disables one-shot pulse output. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0/1 0/1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Cautions 1. Values in the following range should be set in CR00n and CR01n: 0000H CR01n < CR00n FFFFH 2. The pulse generated through PPG output has a cycle of [CR00n setting value + 1], and has a duty of [(CR01n setting value + 1)/(CR00n setting value + 1)]. Remark x: Don't care PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: 178 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) Selector fX (fX)Note fX/2 (fX/24)Note 2 fX/28 (fX/26)Note Noise eliminator Output controller TI000/P00 (TI001/P05)Note Clear circuit 16-bit timer counter 0n (TM0n) fX TO00/TI010/P01 ( TO01/TI011/P06 ) 16-bit timer capture/compare register 01n (CR01n) Note Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. Figure 7-20. PPG Output Operation Timing t Count clock TM0n count value N 0000H 0001H M-1 M Clear N-1 N 0000H 0001H Clear CR00n capture value N CR01n capture value M TO0n Pulse width: (M + 1) x t 1 cycle: (N + 1) x t Cautions 1. Do not rewrite CR00n during TM0n operation. 2. In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n operation using the following procedure. <1> Disable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 0) <2> Disable the INTTM01n interrupt (TMMK01n = 1) <3> Rewrite CR01n <4> Wait for 1 cycle of the TM0n count clock <5> Enable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 1) <6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0) <7> Enable the INTTM01n interrupt (TMMK01n = 0) Remarks 1. 0000H M < N FFFFH 2. n = 0: PD780143, 780144, n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00n pin. When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 0n (PRM0n) and the valid level of the TI00n or TI01n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-21. CR01n Capture Operation with Rising Edge Specified Count clock TM0n N-3 N-2 N-1 N N+1 TI00n Rising edge detection N CR01n INTTM01n Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figures 7-22, 7-25, 7-27, and 7-29 for the set value). <2> Set the count clock by using the PRM0n register. <3> Set the TMC0n register to start the operation (see Figures 7-22, 7-25, 7-27, and 7-29 for the set value). Caution To use two capture registers, set the TI00n and TI01n pins. Remarks 1. For the setting of the TI00n (or TI01n) pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n (or INTTM01n) interrupt, see CHAPTER 19 FUNCTIONS. 3. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 180 User's Manual U15947EJ3V1UD INTERRUPT CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set. Specify both the rising and falling edges of the TI00n pin by using bits 4 and 5 (ES0n0 and ES0n1) of PRM0n. Sampling is performed using the count clock selected by PRM0n, and a capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI00n and CR01n Are Used) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 0 1 0/1 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 1 0/1 0 CR00n used as compare register CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 1 1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter fX/22 (fX/24)Note 6 Note 8 fX/2 (fX/2 ) Selector fX (fX)Note 16-bit timer counter 0n (TM0n) OVF0n 16-bit timer capture/compare register 01n (CR01n) TI00n INTTM01n Internal bus Note Frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16bit timer/event counter 01. Figure 7-24. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM0n count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 TI00n pin input CR01n capture value D0 D1 D2 D3 INTTM01n Note OVF0n (D1 - D0) x t (10000H - D1 + D2) x t Note Clear OVF0n by software. Remark 182 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD (D3 - D2) x t CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI00n pin and the TI01n pin. When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set. Also, when the edge specified by bits 6 and 7 (ES1n0 and ES1n1) of PRM0n is input to the TI01n pin, the value of TM0n is taken into 16-bit timer capture/compare register 00n (CR00n) and an interrupt request signal (INTTM00n) is set. Specify both the rising and falling edges as the edges of the TI00n and TI01n pins, by using bits 4 and 5 (ES0n0 and ES0n1) and bits 6 and 7 (ES1n0 and ES1n1) of PRM0n. Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a capture operation is only performed when a valid level of the TI00n or TI01n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-25. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 0 1 0/1 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 1 0 1 CR00n used as capture register Captures valid edge of TI01n pin to CR00n. CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 1 1 1 1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-26. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM0n count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 TI00n pin input D0 CR01n capture value D1 D2 INTTM01n TI01n pin input CR00n capture value D1 D2 + 1 INTTM00n Note OVF0n (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1)) x t Note Clear OVF0n by software. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 184 User's Manual U15947EJ3V1UD (D3 - D2) x t D3 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI00n pin. When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set. Also, when the inverse edge to that of the capture operation is input into CR01n, the value of TM0n is taken into 16-bit timer capture/compare register 00n (CR00n). Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-27. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 0 1 0/1 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 1 1 1 CR00n used as capture register Captures to CR00n at inverse edge to valid edge of TI00n. CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0 1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-28. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM0n count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 TI00n pin input CR01n capture value D0 CR00n capture value D2 D1 D3 INTTM01n Note OVF0n (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t Note Clear OVF0n by software. (4) Pulse width measurement by means of restart When input of a valid edge to the TI00n pin is detected, the count value of 16-bit timer counter 0n (TM0n) is taken into 16-bit timer capture/compare register 01n (CR01n), and then the pulse width of the signal input to the TI00n pin is measured by clearing TM0n and restarting the count operation. Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n) and a capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 186 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-29. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 0 0/1 0 Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC00n 1 1 1 CR00n used as capture register Captures to CR00n at inverse edge to valid edge of TI00n. CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0 1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Figure 7-30. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM0n count value 0000H 0001H D0 0000H 0001H D2 0000H 0001H D1 TI00n pin input CR01n capture value D0 D2 D1 CR00n capture value INTTM01n D1 x t D2 x t Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-31 for the set value). <2> Set the count clock by using the PRM0n register. <3> Set any value to the CR00n register (0000H cannot be set). <4> Set the TMC0n register to start the operation (see Figure 7-31 for the set value). Remarks 1. For the setting of the TI00n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. The external event counter counts the number of external clock pulses input to the TI00n pin using 16-bit timer counter 0n (TM0n). TM0n is incremented each time the valid edge specified by prescaler mode register 0n (PRM0n) is input. When the TM0n count value matches the 16-bit timer capture/compare register 00n (CR00n) value, TM0n is cleared to 0 and the interrupt request signal (INTTM00n) is generated. Input a value other than 0000H to CR00n (a count operation with 1-bit pulse cannot be carried out). Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). Sampling is performed using the internal clock (fX) and an operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. 188 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0/1 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0 1 3 2 0 0 PRM0n1 PRM0n0 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 189 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 00n (CR00n) Match INTTM00n Clear Noise eliminator fX 16-bit timer counter 0n (TM0n) OVF0nNote Valid edge of TI00n Note OVF0n is set to 1 only when CR00n is set to FFFFH. Figure 7-33. External Event Counter Operation Timing (with Rising Edge Specified) TI00n pin input TM0n count value 0000H 0001H 0002H 0003H 0004H 0005H N-1 N 0000H 0001H 0002H 0003H N CR00n INTTM00n Caution When reading the external event counter count value, TM0n should be read. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 190 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 7-34 for the set value). <3> Set the TOC0n register (see Figure 7-34 for the set value). <4> Set any value to the CR00n register (0000H cannot be set). <5> Set the TMC0n register to start the operation (see Figure 7-34 for the set value). Caution Do not rewrite CR00n during TM0n operation. Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 00n (CR00n). The TO0n pin output status is reversed at intervals determined by the count value preset to CR00n + 1 by setting bit 0 (TOE0n) and bit 1 (TOC0n1) of 16-bit timer output control register 0n (TOC0n) to 1. This enables a square wave with any selected frequency to be output. Figure 7-34. Control Register Settings in Square-Wave Output Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register User's Manual U15947EJ3V1UD 191 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0/1 0/1 1 1 Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited). Does not invert output on match between TM0n and CR01n. Disables one-shot pulse output. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0/1 0/1 3 2 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Figure 7-35. Square-Wave Output Operation Timing Count clock TM0n count value CR00n 0000H 0001H 0002H N-1 N 0000H 0001H 0002H N INTTM00n TO0n pin output Remark 192 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD N-1 N 0000H CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figures 7-36 and 7-38 for the set value). <3> Set the TOC0n register (see Figures 7-36 and 7-38 for the set value). <4> Set any value to the CR00n and CR01n registers (0000H cannot be set). <5> Set the TMC0n register to start the operation (see Figures 7-36 and 7-38 for the set value). Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n (if necessary, INTTM01n) interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n), capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in Figure 7-36, and by setting bit 6 (OSPT0n) of the TOC0n register to 1 by software. By setting the OSPT0n bit to 1, 16-bit timer/event counter 0n is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 01n (CR01n). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 00n (CR00n)Note. Even after the one-shot pulse has been output, the TM0n register continues its operation. To stop the TM0n register, the TMC0n3 and TMC0n2 bits of the TMC0n register must be cleared to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register and inactive with the CR01n register. Do not set N to M. Cautions 1. Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI00n pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD 193 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-36. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 TMC0n3 0 0 0 0 0 TMC0n2 TMC0n1 1 OVF0n 0 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 0 0/1 0 CR00n as compare register CR01n as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 0 1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 1 Enables TO0n output. Inverts output upon match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited.) Inverts output upon match between TM0n and CR01n. Sets one-shot pulse output mode. Set to 1 for output. (d) Prescaler mode register 0n (PRM0n) PRM0n ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Caution Do not set the CR00n and CR01n registers to 0000H. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 194 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-37. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 04H (TM0n count starts) Count clock TM0n count 0000H 0001H N N+1 0000H N-1 N M-1 M M+1 M+2 CR01n set value N N N N CR00n set value M M M M OSPT0n INTTM01n INTTM00n TO0n pin output Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits. Remark N<M (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n), capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in Figure 7-38, and by using the valid edge of the TI00n pin as an external trigger. The valid edge of the TI00n pin is specified by bits 4 and 5 (ES0n0, ES0n1) of prescaler mode register 0n (PRM0n). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI00n pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (CR01n). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 00n (CR00n)Note. Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register and inactive with the CR01n register. Do not set N to M. Caution Do not input the external trigger again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-38. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n 7 6 5 4 0 0 0 0 TMC0n3 TMC0n2 TMC0n1 1 0 OVF0n 0 0 Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n 7 6 5 4 3 0 0 0 0 0 CRC0n2 CRC0n1 CRC0n0 0 0/1 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 0 1 1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 Enables TO0n output. Inverts output upon match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited.) Inverts output upon match between TM0n and CR01n. Sets one-shot pulse output mode. (d) Prescaler mode register 0n (PRM0n) PRM0n ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0 1 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Caution Do not set the CR00n and CR01n registers to 0000H. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 196 User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC0n is set to 08H (TM0n count starts) t Count clock TM0n count value 0000H 0001H 0000H N N+1 N+2 M-2 M-1 M M+1 M+2 CR01n set value N N N N CR00n set value M M M M TI00n pin input INTTM01n INTTM00n TO0n pin output Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits. Remark N<M n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 197 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.5 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count clock. Figure 7-40. Start Timing of 16-Bit Timer Counter 0n (TM0n) Count clock TM0n count value 0000H 0001H 0002H 0003H 0004H Timer start (2) 16-bit timer capture/compare register 00n setting In the mode in which clear & start occurs on a match between TM0n and CR00n, set 16-bit timer capture/compare register 00n (CR00n) to other than 0000H. This means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 0n is used as an external event counter. (3) Capture register data retention timing The values of 16-bit timer capture/compare registers 00n and 01n (CR00n and CR01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped. (4) Valid edge setting Set the valid edge of the TI00n pin after clearing bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control register 0n (TMC0n) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). (5) Re-triggering one-shot pulse (a) One-shot pulse output by software Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. (b) One-shot pulse output with external trigger Do not input the external trigger again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. (c) One-shot pulse output function When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI00n pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Remark 198 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (6) Operation of OVF0n flag <1> The OVF0n flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM0n and CR00n, the mode in which clear & start occurs at the TI00n valid edge, or the free-running mode CR00n is set to FFFFH TM0n is counted up from FFFFH to 0000H. Figure 7-41. Operation Timing of OVF0n Flag Count clock CR00n FFFFH TM0n FFFEH FFFFH 0000H 0001H OVF0n INTTM00n <2> Even if the OVF0n flag is cleared before the next count clock is counted (before TM0n becomes 0001H) after the occurrence of TM0n overflow, the OVF0n flag is re-set newly so this clear is invalid. (7) Conflicting operations If a conflict occurs between the read period of the 16-bit timer capture/compare register (CR00n/CR01n) and capture trigger input (CR00n/CR01n used as capture register), the priority is given to the capture trigger input. The data read from CR00n/CR01n is undefined. Figure 7-42. Capture Register Data Retention Timing Count clock TM0n count value N N+1 N+2 M M+1 M+2 Edge input INTTM01n Capture read signal CR01n capture value X N+2 Capture M+1 Capture, but read value is not guaranteed PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Remark n = 0: User's Manual U15947EJ3V1UD 199 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (8) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (CR01n). <2> Regardless of the CPU's operation mode, when the timer stops, the input signals to the TI00n/TI01n pins are not acknowledged. <3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI00n valid edge. In the mode in which clear & start occurs on a match between the TM0n register and CR00n register, one-shot pulse output is not possible because an overflow does not occur. (9) Capture operation <1> If TI00n valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for TI00n is not possible. <2> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0n (PRM0n). <3> The capture operation is performed at the falling edge of the count clock. An interrupt request input (INTTM00n/INTTM01n), however, is generated at the rise of the next count clock. (10) Compare operation A capture operation may not be performed for CR00n/CR01n set in compare mode even if a capture trigger has been input. (11) Edge detection <1> If the TI00n or TI01n pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the TI00n or TI01n pin to enable the 16-bit timer counter 0n (TM0n) operation, a rising edge is detected immediately after the operation is enabled. Be careful therefore when pulling up the TI00n or TI01n pin. However, if the TI00n pin or TI01n pin is high level when re-enabling operation after the operation has been stopped, the rising edge is not detected. <2> The sampling clock used to eliminate noise differs when the TI00n valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is only performed when a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width. Remark 200 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Selector Match Selector Note 1 S Q INV 8-bit timer OVF counter 50 (TM50) R Clear Selector TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50) Note 2 S 3 INTTM50 Selector TI50/TO50/P17 fX fX/2 fX/22 fX/26 fX/28 fX/213 Mask circuit 8-bit timer compare register 50 (CR50) R Invert level To TMH0 To UART0 To UART6 TO50/ TI50/P17 Output latch (P17) PM17 TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus Notes 1. Timer output F/F 2. PWM output F/F User's Manual U15947EJ3V1UD 201 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Selector Note 1 S Q INV 8-bit timer OVF counter 51 (TM51) R Clear Selector TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) Note 2 S 3 R Timer output F/F 2. PWM output F/F 202 Invert level TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus Notes 1. INTTM51 Selector Match Selector TI51/TO51/P33/INTP4 fX fX/2 fX/24 fX/26 fX/28 fX/212 Mask circuit 8-bit timer compare register 51 (CR51) User's Manual U15947EJ3V1UD TO51/TI51/ P33/INTP4 Output latch (P33) PM33 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n) Timer input TI5n Timer output TO5n Control registers Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1) or port mode register 3 (PM3) Port register 1 (P1) or port register 3 (P3) (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) After reset: 00H R Symbol TM5n (n = 0, 1) In the following situations, the count value is cleared to 00H. <1> RESET input <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. Remark n = 0, 1 User's Manual U15947EJ3V1UD 203 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In PWM mode, when the TO5n pin becomes active due to a TM5n overflow and the values of TM5n and CR5n match, the TO5n pin becomes inactive. The value of CR5n can be set within 00H to FFH. RESET input clears CR5n to 00H. Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n) Address: FF17H (CR50), FF41H (CR51) After reset: 00H R/W Symbol CR5n (n = 0, 1) Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark 204 n = 0, 1 User's Manual U15947EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) * Port register 1 (P1) or port register 3 (P3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of TI5n input. TCL5n can be set by an 8-bit memory manipulation instruction. RESET input clears TCL5n to 00H. Remark n = 0, 1 Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 TCL502 TCL501 TCL500 0 0 0 TI50 falling edge 0 0 1 TI50 rising edge 0 1 0 fX (10 MHz) 0 1 1 fX/2 (5 MHz) 1 0 0 fX/2 (2.5 MHz) 1 0 1 fX/2 (156.25 kHz) 1 1 0 fX/2 (39.06 kHz) 1 1 1 fX/2 (1.22 kHz) Note Count clock selection 2 6 8 13 Note Set the count clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock 2.5 MHz Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer/event counter 50 is not guaranteed. 2. When rewriting TCL50 to other data, stop the timer operation beforehand. 3. Be sure to clear bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz. User's Manual U15947EJ3V1UD 205 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL51 0 0 0 0 0 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 0 0 0 TI51 falling edge 0 0 1 TI51 rising edge 0 1 0 fX (10 MHz) 0 1 1 fX/2 (5 MHz) 1 0 0 fX/2 (625 kHz) 1 0 1 fX/2 (156.25 kHz) 1 1 0 fX/2 (39.06 kHz) 1 1 1 fX/2 (2.44 kHz) Note Count clock selection 4 6 8 12 Note Set the count clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock 2.5 MHz Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer/event counter 51 is not guaranteed. 2. When rewriting TCL51 to other data, stop the timer operation beforehand. 3. Be sure to clear bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz. 206 User's Manual U15947EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip-flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0, 1 Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH After reset: 00H R/W Symbol <7> 6 5 4 <3> <2> 1 <0> TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear & start occurs on a match between TM50 and CR50 1 PWM (free-running) mode LVS50 LVR50 0 0 No change 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TMC501 Timer output F/F status setting In other modes (TMC506 = 0) In PWM mode (TMC506 = 1) Timer F/F control Active level selection 0 Inversion operation disabled Active-high 1 Inversion operation enabled Active-low TOE50 Timer output control 0 Output disabled (TM50 output is low level) 1 Output enabled (Refer to the next page for Caution and Remark.) User's Manual U15947EJ3V1UD 207 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H R/W Symbol <7> 6 5 4 <3> <2> 1 <0> TMC51 TCE51 TMC516 0 0 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start TMC516 TM51 operating mode selection 0 Mode in which clear & start occurs on a match between TM51 and CR51 1 PWM (free-running) mode LVS51 LVR51 0 0 No change 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TMC511 Timer output F/F status setting In other modes (TMC516 = 0) In PWM mode (TMC516 = 1) Timer F/F control Active level selection 0 Inversion operation disabled Active-high 1 Inversion operation enabled Active-low TOE51 Timer output control 0 Output disabled (TM51 output is low level) 1 Output enabled Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode. 2. Perform <1> to <4> below in the following order, not at the same time. <1> Set TMC5n1, TMC5n6: Operation mode setting <2> Set TOE5n to enable output: Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting <4> Set TCE5n 3. Stop operation before rewriting TMC5n6. Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0. 2. If LVS5n and LVR5n are read, the value is 0. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin regardless of the value of TCE5n. 4. n = 0, 1 208 User's Manual U15947EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0. When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer input, set PM17 and PM33 to 1. The output latches of P17 and P33 at this time may be 0 or 1. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 8-9. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Figure 8-10. Format of Port Mode Register 3 (PM3) Address: FF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 PM33 PM32 PM31 PM30 PM3n P3n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD 209 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). Setting <1> Set the registers. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Clear TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. Figure 8-11. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM5n count value 00H 01H Count start CR5n N N 00H 01H Clear N 00H 01H Clear N N N TCE5n INTTM5n Interrupt acknowledged Interval time Remark Interval time = (N + 1) x t N = 01H to FEH n = 0, 1 210 N User's Manual U15947EJ3V1UD Interrupt acknowledged Interval time CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H 00H 00H CR5n 00H 00H TCE5n INTTM5n Interval time (c) When CR5n = FFH t Count clock TM5n CR5n 01 FF FE FF 00 FE FF FF 00 FF TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time Remark n = 0, 1 User's Manual U15947EJ3V1UD 211 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. Setting <1> Set each register. * Set the port mode register (PM17 or PM33)Note to 1. * TCL5n: Select TI5n input edge. TI5n falling edge TCL5n = 00H TI5n rising edge TCL5n = 01H * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 0000xx00B x = Don't care) <2> When TCE5n = 1 is set, the number of pulses input from TI5n is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Note 8-bit timer/event counter 50: PM17 8-bit timer/event counter 51: PM33 Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified) TI5n Count start TM5n count value 00H 01H 02H 03H 04H 05H CR5n N = 00H to FFH n = 0, 1 212 N 00H N INTTM5n Remark N-1 User's Manual U15947EJ3V1UD 01H 02H 03H CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. Note Note * Clear the port output latch (P17 or P33) and port mode register (PM17 or PM33) to 0. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. LVS5n LVR5n Timer Output F/F Status Setting 1 0 High-level output 0 1 Low-level output Timer output F/F inversion enabled Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. Frequency = 1/2t (N + 1) (N: 00H to FFH) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remark n = 0, 1 User's Manual U15947EJ3V1UD 213 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 8.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark 214 n = 0, 1 User's Manual U15947EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. Note Note * Clear the port output latch (P17 or P33) and port mode register (PM17 or PM33) to 0. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select PWM mode. The timer output F/F is not changed. TMC5n1 Active Level Selection 0 Active-high 1 Active-low Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Clear TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 PWM output operation <1> PWM output (output from TO5n) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. For details of timing, see Figures 8-14 and 8-15. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) Remark n = 0, 1 User's Manual U15947EJ3V1UD 215 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM5n 00H 01H CR5n N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n <1> <5> <2> Active level <3> Inactive level Active level (b) CR5n = 00H t Count clock TM5n 00H 01H CR5n 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n L Inactive level Inactive level (c) CR5n = FFH t TM5n 00H 01H CR5n FFH FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n Inactive level Active level Active level Inactive level Inactive level Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) correspond to <1> to <3> and <5> in PWM output operation in 8.4.4 (1) PWM output basic operation. 2. n = 0, 1 216 User's Manual U15947EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is transferred to CR5n at overflow immediately after change. t Count clock TM5n N N+1 N+2 CR5n N TCE5n INTTM5n FFH 00H 01H 02H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 M H TO5n <2> <1> CR5n change (N M) (b) CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow. t Count clock TM5n N N+1 N+2 CR5n TCE5n INTTM5n N FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H N M M+1 M+2 M H TO5n <1> CR5n change (N M) <2> Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). User's Manual U15947EJ3V1UD 217 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 8-16. 8-Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H 01H 02H Timer start Remark 218 n = 0, 1 User's Manual U15947EJ3V1UD 03H 04H CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. * Interval timer * PWM output mode * Square-wave output * Carrier generator mode (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware. Table 9-1. Configuration of 8-Bit Timers H0 and H1 Item Configuration Timer register 8-bit timer counter Hn Registers 8-bit timer H compare register 0n (CMP0n) Timer output TOHn Control registers 8-bit timer H mode register n (TMHMDn) 8-bit timer H compare register 1n (CMP1n) 8-bit timer H carrier control register 1 (TMCYC1) Note Port mode register 1 (PM1) Port register 1 (P1) Note 8-bit timer H1 only Remark n = 0, 1 Figures 9-1 and 9-2 show the block diagrams. User's Manual U15947EJ3V1UD 219 220 Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode control register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 3 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) 2 Decoder TOH0/P15 fX fX/2 fX/22 fX/26 fX/210 8-bit timer/ event counter 50 output Selector User's Manual U15947EJ3V1UD Match Interrupt generator F/F R Output controller Level inversion Output latch (P15) 8-bit timer counter H0 Clear PWM mode signal Timer H enable signal 1 0 INTTMH0 PM15 CHAPTER 9 8-BIT TIMERS H0 AND H1 Selector Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode control register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 8-bit timer H compare register 01 (CMP01) 8-bit timer H compare register 11 (CMP11) 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1) INTTM51 Reload/ interrupt control 2 TOH1/ INTP5/ P16 Decoder fX fX/22 fX/24 fX/26 fX/212 fR/27 Selector User's Manual U15947EJ3V1UD Match Interrupt generator F/F R Output controller Level inversion Output latch (P16) 8-bit timer counter H1 Carrier generator mode signal Clear PWM mode signal Timer H enable signal 1 0 INTTMH1 PM16 CHAPTER 9 8-BIT TIMERS H0 AND H1 Selector 221 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) Symbol 7 6 5 After reset: 00H 4 3 R/W 2 1 0 CMP0n (n = 0, 1) Caution CMP0n cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF19H (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 After reset: 00H 4 3 R/W 2 1 0 CMP1n can be rewritten during timer count operation. An interrupt request signal (INTTMHn) is generated if the values of the timer count and CMP1n match after setting CMP1n in carrier generator mode. The timer count value is cleared at the same time. If the CMP1n value is rewritten during timer operation, transferring is performed at the timing at which the count value and CMP1n value match. If the transfer timing and writing from CPU to CMP1n conflict, transfer is not performed. Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark 222 n = 0, 1 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register 1 (TMCYC1) Note * Port mode register 1 (PM1) * Port register 1 (P1) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0, 1 User's Manual U15947EJ3V1UD 223 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H TMHMD0 After reset: 00H R/W <7> 6 5 4 TMHE0 CKS02 CKS01 CKS00 TMHE0 3 <0> <1> TMMD01 TMMD00 TOLEV0 TOEN0 Timer operation enable 0 Stops timer count operation (counter is cleared to 0) 1 Enables timer count operation (count operation started by inputting clock) Count clock (fCNT) selectionNote 1 CKS02 CKS01 CKS00 0 0 0 fX 0 0 1 fX/2 0 1 0 0 1 1 1 0 0 fX/210 1 0 1 TM50 outputNote 2 Other than above (10 MHz) (5 MHz) fX/2 2 (2.5 MHz) fX/2 6 (156.25 kHz) Timer operation mode 0 0 Interval timer mode 1 0 PWM output mode Other than above (9.77 kHz) Setting prohibited TMMD01 TMMD00 Setting prohibited TOLEV0 Timer output level control (in default mode) 0 Low level 1 High level TOEN0 Notes 1. 2 Timer output control 0 Disables output 1 Enables output Set the count clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock 2.5 MHz 2. When selecting the TM50 output as the count clock, note the following. * PWM mode (TMC506 = 1) Set the clock to 50% duty and start the 8-bit timer/event counter 50 operation beforehand. * Mode in which clear & start occurs on a match of TM50 and CR50 (TMC506 = 0) Enable the timer F/F inversion operation (TMC501 = 1) and start the 8-bit timer/event counter 50 operation beforehand. In the both modes, it is not necessary to enable the timer output for the TO50 pin. 224 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer H0 is not guaranteed. 2. When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited. 3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz. User's Manual U15947EJ3V1UD 225 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH TMHMD1 After reset: 00H R/W <7> 6 5 4 TMHE1 CKS12 CKS11 CKS10 TMHE1 3 <1> <0> TOEN1 Timer operation enable 0 Stops timer count operation (counter is cleared to 0) 1 Enables timer count operation (count operation started by inputting clock) Count clock (fCNT) selectionNote CKS12 CKS11 CKS10 0 0 0 0 0 1 0 1 0 0 1 1 fX/26 1 0 0 1 0 1 Other than above (10 MHz) fX fX/2 2 (2.5 MHz) fX/2 4 (625 kHz) fX/2 (156.25 kHz) 12 (2.44 kHz) 7 (1.88 kHz (TYP.)) fR/2 Setting prohibited TMMD11 TMMD10 Timer operation mode 0 0 Interval timer mode 0 1 Carrier generator mode 1 0 PWM output mode 1 1 Setting prohibited TOLEV1 Timer output level control (in default mode) 0 Low level 1 High level TOEN1 Timer output control 0 Disables output 1 Enables output Note Set the count clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock 2.5 MHz 226 2 TMMD11 TMMD10 TOLEV1 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer H1 is not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (fR/27)). 2. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. 3. In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 4. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. Remarks 1. fX: X1 input clock oscillation frequency 2. fR: Internal oscillation clock frequency 3. Figures in parentheses apply to operation at fX = 10 MHz, fR = 240 kHz (TYP.). User's Manual U15947EJ3V1UD 227 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Address: FF6DH After reset: 00H R/WNote <0> TMCYC1 0 0 0 0 0 RMC1 NRZB1 0 0 Low-level output 0 1 High-level output 1 0 Low-level output 1 1 Carrier pulse output RMC1 NRZB1 NRZ1 Remote control output NRZ1 Carrier pulse output status flag 0 Carrier output disabled status (low-level status) 1 Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status) Note Bit 0 is read-only. (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 9-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 228 After reset: FFH P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. (1) Usage Generates the INTTMHn signal repeatedly at the same interval. <1> Set each register. Figure 9-9. Register Setting During Interval Timer/Square-Wave Output Operation (i) TMHMDn Setting timer H mode register n (TMHMDn) TMHEn CKSn2 CKSn1 CKSn0 0 0/1 0/1 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting * Compare value (N) <2> Count operation starts when TMHEn = 1. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn to 0. Remark n = 0, 1 User's Manual U15947EJ3V1UD 229 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 8-bit timer counter Hn 00H 01H N 00H 01H N Clear 00H 01H 00H Clear N CMP0n TMHEn INTTMHn Interval time TOHn <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive by clearing the TMHEn bit to 0 during timer Hn operation. If these are inactive from the first, the level is retained. Remark n = 0, 1 N = 01H to FEH 230 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 User's Manual U15947EJ3V1UD 231 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn and the CMP1n register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 9-11. Register Setting in PWM Output Mode (i) TMHMDn Setting timer H mode register n (TMHMDn) TMHEn CKSn2 CKSn1 CKSn0 0 0/1 0/1 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time, the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. 232 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N+1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register value after rewriting the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). User's Manual U15947EJ3V1UD 233 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Remark n = 0, 1 Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H CMP0n A5H CMP1n 01H A5H 00H 01H 02H A5H 00H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <2> <3> <4> TOHn (TOLEVn = 1) <1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0). <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 234 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP0n FFH CMP1n 00H FFH 00H TMHEn INTTMHn TOHn (TOLEVn = 0) (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP0n FFH CMP1n FEH FEH FFH 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 User's Manual U15947EJ3V1UD 235 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark 236 n = 0, 1 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP0n 01H CMP1n 01H (03H) <2> 03H <2>' TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0). <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 User's Manual U15947EJ3V1UD 237 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. (1) Carrier generation In carrier generator mode, 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of 8-bit timer/event counter 51 and the NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below. 238 RMC1 Bit NRZB1 Bit 0 0 Output Low-level output 0 1 High-level output 1 0 Low-level output 1 1 Carrier pulse output User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 9-13. Transfer Timing TMHE1 8-bit timer H1 count clock INTTM51 INTTM5H1 <1> NRZ1 0 1 0 <2> NRZB1 1 0 1 RMC1 <1> The INTTM51 signal is synchronized with the count clock of 8-bit timer H1 and is output as the INTTM5H1 signal. <2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. 2. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. User's Manual U15947EJ3V1UD 239 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode (i) TMHMD1 Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 TOEN1 1 0/1 0 0/1 Timer output enabled Timer output level inversion setting Carrier generator mode selection Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... Carrier output enable bit (v) TCL51 and TMC51 register setting * See 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, 8-bit timer H1 starts counting. <3> When TCE51 of 8-bit timer mode control register 51 (TMC51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with count clock of 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <8> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin. <9> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. 240 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/fCNT Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. (4) Timing chart The carrier output control timing is shown below. Cautions 1. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 2. In the carrier generator mode, three operating clocks (signal selected by CKS12 to CKS10 bits of TMHMD1 register) or more are required from when the CMP11 register value is changed to when the value is transferred to the register. 3. Be sure to set the RMC1 bit before the count operation is started. User's Manual U15947EJ3V1UD 241 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter Hn count value 00H N 00H N 00H N 00H CMPn0 N CMPn1 N N 00H N 00H N TMHEn INTTMHn <3> <4> <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value 00H 01H L 00H 01H L 00H 01H L 00H 01H L 00H 01H L CR5n TCE5n <5> INTTM5n INTTM5Hn NRZBn 0 1 0 1 0 <6> NRZn 0 1 0 1 0 Carrier clock TOHn <7> <1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level. 242 User's Manual U15947EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter Hn count value 00H N 00H 01H M 00H N 00H 01H CMPn0 N CMPn1 M M 00H N 00H TMHEn INTTMHn <3> <4> <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value 00H 01H L 00H 01H L 00H 01H L 00H 01H L 00H 01H L CR5n TCE5n <5> INTTM5n INTTM5Hn NRZBn NRZn 0 1 0 0 1 1 0 0 1 0 Carrier clock <6> TOHn <7> <1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). User's Manual U15947EJ3V1UD 243 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H N CMP01 <3> M CMP11 <3>' M (L) L TMHE1 INTTMH1 <2> Carrier clock <4> <5> <1> <1> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <2> When the count value of 8-bit timer counter H1 matches the CMP01 register value, 8-bit timer counter H1 is cleared and the INTTMH1 signal is output. <3> The CMP11 register can be rewritten during 8-bit timer H1 operation, however, the changed value (L) is latched. The CMP11 register is changed when the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match (<3>'). <4> When the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match, the INTTMH1 signal is output, the carrier signal is inverted, and 8-bit timer counter H1 is cleared to 00H. <5> The timing at which the count value of 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L). 244 User's Manual U15947EJ3V1UD CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. fX/27 11-bit prescaler fW fWX fWX/24 5-bit counter fWX/25 INTWT Clear fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Selector fXT Selector Clear Selector Selector Figure 10-1. Watch Timer Block Diagram WTM7 WTM6 WTM5 INTWTI WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency fWX: fW or fW/29 User's Manual U15947EJ3V1UD 245 CHAPTER 10 WATCH TIMER (1) Watch timer When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at fXT = 32.768 kHz When Operated at fX = 10 MHz 4 488 s 205 s 5 977 s 410 s 13 0.25 s 0.105 s 14 0.5 s 0.210 s 2 /fW 2 /fW 2 /fW 2 /fW Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency (2) Interval timer Interrupt requests (INTWTI) are generated at preset time intervals. Table 10-2. Interval Timer Interval Time Interval Time When Operated at fXT = 32.768 kHz 4 488 s 5 2 /fW 205 s 977 s 410 s 6 1.95 ms 820 s 7 3.91 ms 1.64 ms 8 7.81 ms 3.28 ms 9 15.6 ms 6.55 ms 10 31.3 ms 13.1 ms 11 62.5 ms 26.2 ms 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency 246 When Operated at fX = 10 MHz User's Manual U15947EJ3V1UD CHAPTER 10 WATCH TIMER 10.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 10-3. Watch Timer Configuration Item Configuration Counter 5 bits x 1 Prescaler 11 bits x 1 Control register Watch timer operation mode register (WTM) 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears WTM to 00H. User's Manual U15947EJ3V1UD 247 CHAPTER 10 WATCH TIMER Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH Symbol WTM After reset: 00H R/W 7 6 5 4 3 2 <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection 7 0 fX/2 (78.125 kHz) 1 fXT (32.768 kHz) WTM6 WTM5 WTM4 Prescaler interval time selection 4 0 0 0 2 /fW 0 0 1 2 /fW 0 1 0 2 /fW 0 1 1 2 /fW 1 0 0 2 /fW 1 0 1 2 /fW 1 1 0 2 /fW 1 1 1 2 /fW WTM3 WTM2 5 6 7 8 9 10 11 Interrupt time selection 14 0 0 2 /fW 0 1 2 /fW 1 0 2 /fW 1 1 2 /fW 13 5 4 WTM1 5-bit counter operation control 0 Clear after operation stop 1 Start WTM0 Caution Watch timer operation enable 0 Operation stop (clear both prescaler and timer) 1 Operation enable Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT) 2. fX: X1 input clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. Figures in parentheses apply to operation with fX = 10 MHz, fXT = 32.768 kHz. 248 User's Manual U15947EJ3V1UD CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops. When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 211 x 1/fW seconds occurs in the first overflow (INTWT) after zero-second start. The interrupt request is generated at the following time intervals. Table 10-4. Watch Timer Interrupt Time WTM3 0 WTM2 0 Interrupt Time Selection 0.5 s 0.210 s 0.25 s 0.105 s 5 977 s 410 s 4 488 s 205 s 1 2 /fW 0 2 /fW Remark (WTM7 = 0) 13 2 /fW 1 1 When Operated at fX = 10 MHz (WTM7 = 1) 14 0 1 When Operated at fXT = 32.768 kHz 2 /fW fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency User's Manual U15947EJ3V1UD 249 CHAPTER 10 WATCH TIMER 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is cleared to 0, the count operation stops. Table 10-5. Interval Timer Interval Time WTM6 WTM5 0 WTM4 0 0 0 0 0 1 1 0 Interval Time 488 s 205 s 5 977 s 410 s 6 1.95 ms 820 s 7 3.91 ms 1.64 ms 8 7.81 ms 3.28 ms 9 15.6 ms 6.55 ms 10 31.3 ms 13.1 ms 11 62.5 ms 26.2 ms 2 /fW 2 /fW 1 1 2 /fW 1 0 0 2 /fW 0 1 1 1 1 0 1 Remark 1 When Operated at fX = 10 MHz (WTM7 = 0) 4 2 /fW 0 1 When Operated at fXT = 32.768 kHz (WTM7 = 1) 2 /fW 2 /fW 2 /fW fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Overflow Start Overflow Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) T nxT Remark nxT fW: Watch timer clock frequency n: The number of times of interval timer operations Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0) 250 User's Manual U15947EJ3V1UD CHAPTER 10 WATCH TIMER 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM. This is because there is a delay up to one 11-bit prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT signal is generated at the specified intervals. Figure 10-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) It takes a maximum of 0.515625 seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT User's Manual U15947EJ3V1UD 251 CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION. Table 11-1. Loop Detection Time of Watchdog Timer Loop Detection Time During Internal Oscillation Clock Operation During X1 Input Clock Operation 11 2 /fXP (819.2 s) 12 2 /fXP (1.64 ms) 13 2 /fXP (3.28 ms) 14 2 /fXP (6.55 ms) 15 2 /fXP (13.11 ms) 16 2 /fXP (26.21 ms) 17 2 /fXP (52.43 ms) 18 2 /fXP (104.86 ms) 2 /fR (4.27 ms) 2 /fR (8.53 ms) 2 /fR (17.07 ms) 2 /fR (34.13 ms) 2 /fR (68.27 ms) 2 /fR (136.53 ms) 2 /fR (273.07 ms) 2 /fR (546.13 ms) 13 14 15 16 17 18 19 20 Remarks 1. fR: Internal oscillation clock frequency 2. fXP: X1 input clock oscillation frequency 3. Figures in parentheses apply to operation at fR = 480 kHz (MAX.) (standard products, (A) grade products), fXP = 10 MHz. The operation mode of the watchdog timer (WDT) is switched according to the mask option setting of the internal oscillator as shown in Table 11-2. 252 User's Manual U15947EJ3V1UD CHAPTER 11 WATCHDOG TIMER Table 11-2. Mask Option Setting and Watchdog Timer Operation Mode Mask Option Internal Oscillator Cannot Be Stopped Watchdog timer clock Fixed to fR Internal Oscillator Can Be Stopped by Software * Selectable by software (fXP, fR or stopped) Note 1 . * When reset is released: fR source Operation starts with the maximum interval Operation after reset 18 Operation starts with the maximum interval 18 (2 /fR). (2 /fR). Operation mode selection The interval can be changed only once. The clock selection/interval can be changed only once. Features The watchdog timer cannot be stopped. The watchdog timer can be stopped in standby mode Notes 1. Note 2 . As long as power is being supplied, internal oscillator cannot be stopped (except in the reset period). 2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> If the clock source is fXP, clock supply to the watchdog timer is stopped under the following conditions. * When fXP is stopped * In HALT/STOP mode * During oscillation stabilization time <2> If the clock source is fR, clock supply to the watchdog timer is stopped under the following conditions. * If the CPU clock is fXP and if fR is stopped by software before execution of the STOP instruction * In HALT/STOP mode Remarks 1. fR: Internal oscillation clock frequency 2. fXP: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD 253 CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 11-1. Block Diagram of Watchdog Timer fR/22 4 fXP/2 211/fR to 218/fR Clock input controller 16-bit counter 2 Watchdog timer enable register (WDTE) Selector or 213/fXP to 220/fXP 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus 254 Internal reset signal 3 Clear 0 Output controller User's Manual U15947EJ3V1UD Mask option (to set "Internal oscillator cannot be stopped" or "Internal oscillator can be stopped by software") CHAPTER 11 WATCHDOG TIMER 11.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. RESET input sets this register to 67H. Figure 11-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF98H After reset: 67H R/W Symbol 7 6 5 4 3 2 1 0 WDTM 0 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Internal oscillation clock (fR) 0 1 X1 input clock (fXP) 1 x Watchdog timer operation stopped WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 Overflow time setting During internal oscillation clock During X1 input clock operation operation 11 2 /fXP (819.2 s) 12 2 /fXP (1.64 ms) 13 2 /fXP (3.28 ms) 14 2 /fXP (6.55 ms) 15 2 /fXP (13.11 ms) 16 2 /fXP (26.21 ms) 17 2 /fXP (52.43 ms) 18 2 /fXP (104.86 ms) 0 0 0 2 /fR (4.27 ms) 0 0 1 2 /fR (8.53 ms) 0 1 0 2 /fR (17.07 ms) 0 1 1 2 /fR (34.13 ms) 1 0 0 2 /fR (68.27 ms) 1 0 1 2 /fR (136.53 ms) 1 1 0 2 /fR (273.07 ms) 1 1 1 2 /fR (546.13 ms) Notes 1. 13 14 15 16 17 18 19 20 If "Internal oscillator cannot be stopped" is specified by a mask option, this cannot be set. The internal oscillation clock will be selected no matter what value is written. 2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1). User's Manual U15947EJ3V1UD 255 CHAPTER 11 WATCHDOG TIMER Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. 2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Internal oscillator cannot be stopped" is selected by a mask option, other values are ignored). 3. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 4. WDTM cannot be set by a 1-bit memory manipulation instruction. 5. If "Internal oscillator can be stopped by software" is selected by the mask option and the watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not resume operation even if WDCS4 is cleared to 0. In addition, the internal reset signal is not generated. Remarks 1. fR: Internal oscillation clock frequency 2. fXP: X1 input clock oscillation frequency 3. x: Don't care 4. Figures in parentheses apply to operation at fR = 480 kHz (MAX.) (standard products, (A) grade products), fXP = 10 MHz. 256 User's Manual U15947EJ3V1UD CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 9AH. Figure 11-3. Format of Watchdog Timer Enable Register (WDTE) Address: FF99H After reset: 9AH 7 Symbol R/W 6 5 4 3 2 1 0 WDTE Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 3. The value read from WDTE is 9AH (this differs from the written value (ACH)). The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog timer is shown below. Table 11-4. Relationship Between Watchdog Timer Operation and Internal Reset Signal Generated by Watchdog Timer Watchdog Timer Operation Internal Reset Signal Generation Cause "Internal Oscillator "Internal Oscillator Can Be Stopped by Software" Is Selected by Mask Option Cannot Be Stopped" Is Watchdog Timer Is Selected by Mask Operating Watchdog Timer Stopped WDCS4 Is Set to 1 Option Source Clock to Watchdog Timer Is (Watchdog Timer Is Stopped Always Operating) - - Watchdog timer Internal reset signal is Internal reset signal is overflows generated. generated. Write to WDTM for the Internal reset signal is Internal reset signal is Internal reset signal is Internal reset signal is second time generated. generated. not generated and the generated when the watchdog timer does source clock to the not resume operation. watchdog timer resumes operation. Write other than "ACH" Internal reset signal is Internal reset signal is Internal reset signal is Internal reset signal is to WDTE generated. generated. not generated. generated when the Access WDTE by 1-bit source clock to the memory manipulation watchdog timer instruction resumes operation. User's Manual U15947EJ3V1UD 257 CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Watchdog timer operation when "Internal oscillator cannot be stopped" is selected by mask option The operation clock of watchdog timer is fixed to the internal oscillation clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Internal oscillation clock * Cycle: 218/fR (546.13 ms: At operation with fR = 480 kHz (MAX.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2. * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. The operation clock (internal oscillation clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared. Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. 258 User's Manual U15947EJ3V1UD CHAPTER 11 WATCHDOG TIMER 11.4.2 Watchdog timer operation when "Internal oscillator can be stopped by software" is selected by mask option The operation clock of the watchdog timer can be selected as either the internal oscillation clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Internal oscillation clock * Cycle: 218/fR (546.13 ms: At operation with fR = 480 kHz (MAX.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2, 3. * Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Internal oscillation clock (fR) X1 input clock (fXP) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. 2. 3. As soon as WDTM is written, the counter of the watchdog timer is cleared. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. For the watchdog timer operation during STOP mode and HALT mode in each status, see 11.4.3 Watchdog timer operation in STOP mode and 11.4.4 Watchdog timer operation in HALT mode. User's Manual U15947EJ3V1UD 259 CHAPTER 11 WATCHDOG TIMER 11.4.3 Watchdog timer operation in STOP mode (when "Internal oscillator can be stopped by software" is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or internal oscillation clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (fXP) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) CPU operation Normal operation Oscillation stabilization time STOP Normal operation fXP Oscillation stopped Oscillation stabilization time (set by OSTS register) fR Watchdog timer Operating Operation stopped Operating (2) When the CPU clock is the X1 input clock (fXP) and the watchdog timer operation clock is the internal oscillation clock (fR) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-5. Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Internal Oscillation Clock) CPU operation Normal operation Oscillation stabilization time STOP fXP Oscillation stabilization time (set by OSTS register) Oscillation stopped fR Watchdog timer 260 Operating Operation stopped Operating User's Manual U15947EJ3V1UD Normal operation CHAPTER 11 WATCHDOG TIMER (3) When the CPU clock is the internal oscillation clock (fR) and the watchdog timer operation clock is the X1 input clock (fXP) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. <1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses. <2> The CPU clock is switched to the X1 input clock (fXP). Figure 11-6. Operation in STOP Mode (CPU Clock: Internal Oscillation Clock, WDT Operation Clock: X1 Input Clock) <1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) has elapsed Normal operation (Internal CPU operation oscillation clock) Clock supply stopped STOP Normal operation (Internal oscillation clock) fXP Oscillation stopped Oscillation stabilization time (set by OSTS register) fR 17 clocks Watchdog timer Operating Operation stopped Operating <2> Timing when counting is started after the CPU clock is switched to the X1 input clock (fXP) Normal operation (Internal oscillation clock) Normal operation (Internal CPU operation oscillation clock) CPU clock fR fXPNote Clock supply stopped STOP Normal operation (X1 input clock) fXP Oscillation stopped Oscillation stabilization time (set by OSTS register) fR 17 clocks Watchdog timer Operating Operation stopped Operating Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register (OSTC). User's Manual U15947EJ3V1UD 261 CHAPTER 11 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the internal oscillation clocks (fR) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Internal Oscillation Clock) Normal operation (Internal CPU operation oscillation clock) Clock supply stopped STOP Normal operation (Internal oscillation clock) fXP Oscillation stopped Oscillation stabilization time (set by OSTS register) fR 17 clocks Watchdog timer 11.4.4 Operating Operation stopped Operating Watchdog timer operation in HALT mode (when "Internal oscillator can be stopped by software" is selected by mask option) The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the X1 input clock (fXP), internal oscillation clock (fR), or subsystem clock (fXT), or whether the operation clock of the watchdog timer is the X1 input clock (fXP) or internal oscillation clock (fR). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-8. Operation in HALT Mode CPU operation Normal operation Normal operation HALT fXP fR fXT Watchdog timer Operating Operation stopped 262 User's Manual U15947EJ3V1UD Operating CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 12-1 shows the block diagram of clock output/buzzer output controller. Figure 12-1. Block Diagram of Clock Output/Buzzer Output Controller fX 8 4 fX/210 to fX/213 Selector Prescaler BUZ/BUSY0/ INTP7/P141 Output latch (P141) BZOE fXT BCS0, BCS1 Selector fX to fX/27 Clock controller CLOE BZOE BCS1 BCS0 CLOE CCS3 CCS2 PM141 CCS1 PCL/INTP6/P140 Output latch (P140) PM140 CCS0 Clock output selection register (CKS) Internal bus User's Manual U15947EJ3V1UD 263 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Clock Output/Buzzer Output Controller Configuration Item Control registers Configuration Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 12.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output selection register (CKS) * Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CKS to 00H. 264 User's Manual U15947EJ3V1UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H Symbol CKS After reset: 00H R/W <7> 6 5 <4> 3 2 1 0 BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification 0 Clock division circuit operation stopped. BUZ fixed to low level. 1 Clock division circuit operation enabled. BUZ output enabled. BCS1 BCS0 BUZ output clock selection 10 0 0 fX/2 (9.77 kHz) 0 1 fX/2 (4.88 kHz) 1 0 fX/2 (2.44 kHz) 1 1 fX/2 (1.22 kHz) 11 12 13 CLOE PCL output enable/disable specification 0 Clock division circuit operation stopped. PCL fixed to low level. 1 Clock division circuit operation enabled. PCL output enabled. Note CCS3 CCS2 CCS1 CCS0 0 0 0 0 fX (10 MHz) 0 0 0 1 fX/2 (5 MHz) 0 0 1 0 fX/2 (2.5 MHz) 0 0 1 1 fX/2 (1.25 MHz) 0 1 0 0 fX/2 (625 kHz) 0 1 0 1 fX/2 (312.5 kHz) 0 1 1 0 fX/2 (156.25 kHz) 0 1 1 1 fX/2 (78.125 kHz) 0 0 0 fXT (32.768 kHz) 1 Other than above PCL output clock selection 2 3 4 5 6 7 Setting prohibited Note Set the PCL output clock to satisfy the following condition. * PCL output clock 10 MHz Remarks 1. fX: X1 input clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. Figures in parentheses are for operation with fX = 10 MHz or fXT = 32.768 kHz. User's Manual U15947EJ3V1UD 265 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/BUSY0/INTP7/BUZ pin for buzzer output, clear PM140 and PM141 and the output latches of P140 and P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM14 to FFH. Figure 12-3. Format of Port Mode Register 14 (PM14) Address: FF2EH R/W Symbol 7 6 5 4 3 2 1 0 PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 PM14n 266 After reset: FFH P14n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.4 Clock Output/Buzzer Output Controller Operations 12.4.1 Clock output operation The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after securing high level of the clock. Figure 12-4. Remote Control Output Application Example CLOE * * Clock output 12.4.2 Operation as buzzer output The buzzer frequency is output as the following procedure. <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output selection register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output. User's Manual U15947EJ3V1UD 267 CHAPTER 13 A/D CONVERTER 13.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. (2) Power-fail detection function This function is used to detect a voltage drop in a battery. The A/D conversion result (ADCR register value) and power-fail comparison threshold register (PFT) value are compared. INTAD is generated only when a comparative condition has been matched. Figure 13-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Sample & hold circuit Tap selector Selector Voltage comparator AVSS Successive approximation register (SAR) AVSS INTAD Controller Comparator A/D conversion result register (ADCR) 3 ADS2 ADS1 Analog input channel specification register (ADS) 268 ADS0 ADCS FR2 FR1 FR0 ADCE Power-fail comparison threshold register (PFT) PFEN PFCM Power-fail comparison mode register (PFM) A/D converter mode register (ADM) Internal bus User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. Table 13-1. Registers of A/D Converter Used on Software Item Configuration A/D conversion result register (ADCR) Registers A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification register (ADS) can be used as input port pins. (2) Sample & hold circuit The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with the analog input signal. Figure 13-2. Circuit Configuration of Series Resistor String AVREF ADCS P-ch Series resistor string AVSS (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). User's Manual U15947EJ3V1UD 269 CHAPTER 13 A/D CONVERTER (6) A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) Controller When A/D conversion has been completed or when the power-fail detection function is used, this controller compares the result of A/D conversion (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). It generates the interrupt INTAD only if a specified comparison condition is satisfied as a result. (8) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential as that of the VDD pin even when the A/D converter is not used. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AVREF and AVSS. (9) AVSS pin This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin even when the A/D converter is not used. (10) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (11) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (12) Power-fail comparison mode register (PFM) This register is used to set the power-fail monitor mode. (13) Power-fail comparison threshold register (PFT) This register is used to set the threshold value that is to be compared with the value of the A/D conversion result register (ADCR). 270 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following five registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * A/D conversion result register (ADCR) * Power-fail comparison mode register (PFM) * Power-fail comparison threshold register (PFT) User's Manual U15947EJ3V1UD 271 CHAPTER 13 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-3. Format of A/D Converter Mode Register (ADM) Address: FF28H Symbol ADM After reset: 00H R/W <7> 6 5 4 3 2 1 <0> ADCS 0 FR2 FR1 FR0 0 0 ADCE ADCS A/D conversion operation control 0 Stops conversion operation 1 Enables conversion operation FR2 FR1 Conversion time selectionNote 1 FR0 fX = 2 MHz fX = 8.38 MHz fX = 10 MHz 0 0 0 288/fX 144 s 34.3 s 28.8 s 0 0 1 240/fX 120 s 28.6 s 24.0 s 0 1 0 192/fX 96 s 22.9 s 19.2 s 1 0 0 144/fX 72 s 17.2 s 14.4 s 60 s 14.3 s 12.0 s 48 s 11.5 s 9.6 s 1 0 1 120/fX 1 1 0 96/fX Other than above Boost reference voltage generator operation controlNote 2 ADCE Notes 1. 2. Setting prohibited 0 Stops operation of reference voltage generator 1 Enables operation of reference voltage generator Set so that the A/D conversion time is as follows. * Standard products, (A) grade products: 14 s or longer but less than 100 s * (A1) grade products: 14 s or longer but less than 60 s * (A2) grade products: 16 s or longer but less than 48 s A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that generates the reference voltage for boosting is controlled by ADCE, and it takes 14 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 14 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. 272 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER Table 13-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion waiting mode (only reference voltage generator consumes power) 1 0 Conversion mode (reference voltage generator operation stopped 1 1 Conversion mode (reference voltage generator operates) Note ) Note Data of first conversion cannot be used. Figure 13-4. Timing Chart When Boost Reference Voltage Generator Is Used Boost reference voltage generator: operating ADCE Boost reference voltage Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 14 s or longer to stabilize the reference voltage. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the identical data. 2. For the sampling time of the A/D converter and the A/D conversion start delay time, see (11) in 13.6 Cautions for A/D Converter. 3. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. Remark fX: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD 273 CHAPTER 13 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-5. Format of Analog Input Channel Specification Register (ADS) Address: FF29H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 0 ADS2 ADS1 ADS0 ADS2 ADS1 ADS0 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 Analog input channel specification Cautions 1. Be sure to clear bits 3 to 7 of ADS to 0. 2. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is operating on the subsystem clock and the X1 input clock is stopped. CHAPTER 36 CAUTIONS FOR WAIT. 274 User's Manual U15947EJ3V1UD For details, see CHAPTER 13 A/D CONVERTER (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion result, and FF08H indicates the lower 2 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. RESET input makes ADCR undefined. Figure 13-6. Format of A/D Conversion Result Register (ADCR) Address: FF08H, FF09H Symbol After reset: Undefined R FF09H FF08H ADCR 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. User's Manual U15947EJ3V1UD 275 CHAPTER 13 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-7. Format of Power-Fail Comparison Mode Register (PFM) Address: FF2AH Symbol PFM After reset: 00H R/W <7> <6> 5 4 3 2 1 0 PFEN PFCM 0 0 0 0 0 0 PFEN Power-fail comparison enable 0 Stops power-fail comparison (used as a normal A/D converter) 1 Enables power-fail comparison (used for power-fail detection) PFCM 0 1 Power-fail comparison mode selection Higher 8 bits of ADCR PFT Interrupt request signal (INTAD) generation Higher 8 bits of ADCR < PFT Higher 8 bits of ADCR PFT No INTAD generation Higher 8 bits of ADCR < PFT INTAD generation No INTAD generation Caution If data is written to PFM, a wait cycle is generated. Do not write data to PFM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. (5) Power-fail comparison threshold register (PFT) The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the values with the A/D conversion result. 8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result. PFT can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-8. Format of Power-Fail Comparison Threshold Register (PFT) Address: FF2BH Symbol PFT After reset: 00H R/W 7 6 5 4 3 2 1 0 PFT7 PFT6 PFT5 PFT4 PFT3 PFT2 PFT1 PFT0 Caution If data is written to PFT, a wait cycle is generated. Do not write data to PFT when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. 276 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for 14 s or longer. <3> Set ADCS to 1 and start the conversion operation. (<4> to <10> are operations performed by hardware.) <4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation has ended. <6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <7> The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <9> Comparison is continued in this way up to bit 0 of SAR. <10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <11> Repeat steps <4> to <10>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the status of ADCE = 0, however, start from <2>. User's Manual U15947EJ3V1UD 277 CHAPTER 13 A/D CONVERTER Figure 13-9. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined Conversion result ADCR INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to one of the ADM, analog input channel specification register (ADS), power-fail comparison mode register (PFM), or power-fail comparison threshold register (PFT) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. RESET input makes the A/D conversion result register (ADCR) undefined. 278 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or (ADCR - 0.5) x where, INT( ): AVREF 1024 VAIN < (ADCR + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: A/D conversion result register (ADCR) value SAR: Successive approximation register Figure 13-10 shows the relationship between the analog input voltage and the A/D conversion result. Figure 13-10. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 FF40H 3 00C0H 2 0080H 1 0040H A/D conversion result (ADCR) 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF User's Manual U15947EJ3V1UD 279 CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison mode register (PFM). * Normal 10-bit A/D converter (PFEN = 0) * Power-fail detection function (PFEN = 1) (1) A/D conversion operation (when PFEN = 0) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 0, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register (PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the conversion result is undefined. Figure 13-11. A/D Conversion Operation Rewriting ADM ADCS = 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result is not retained ADCR ANIn INTAD (PFEN = 0) Remarks 1. n = 0 to 7 2. m = 0 to 7 280 User's Manual U15947EJ3V1UD ANIn Stopped ANIm CHAPTER 13 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started. When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM. <1> When PFEN = 1 and PFCM = 0 The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when the higher 8 bits of ADCR PFT. <2> When PFEN = 1 and PFCM = 1 The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when the higher 8 bits of ADCR < PFT. Figure 13-12. Power-Fail Detection (When PFEN = 1 and PFCM = 0) A/D conversion ANIn ANIn ANIn ANIn Higher 8 bits of ADCR 80H 7FH 80H PFT 80H INTAD (PFEN = 1) Note First conversion Condition match Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is replaced by the next conversion result. Remark n = 0 to 7 User's Manual U15947EJ3V1UD 281 CHAPTER 13 A/D CONVERTER The setting methods are described below. * When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Set bit 7 (ADCS) of ADM to 1. <4> An interrupt request signal (INTAD) is generated. <5> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <Change the channel> <6> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS. <7> An interrupt request signal (INTAD) is generated. <8> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <Complete A/D conversion> <9> Clear ADCS to 0. <10> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <3> is 14 s or more. 2. It is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. However, do not use the first conversion result after <3> in this case. 4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0. * When used as power-fail function <1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM). <2> Set power-fail comparison condition using bit 6 (PFCM) of PFM. <3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <4> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <5> Set a threshold value to the power-fail comparison threshold register (PFT). <6> Set bit 7 (ADCS) of ADM to 1. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <8> The higher 8 bits of ADCR and PFT are compared and an interrupt request signal (INTAD) is generated if the conditions match. <Change the channel> <9> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS. <10> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <11> The higher 8 bits of ADCR and the power-fail comparison threshold register (PFT) are compared and an interrupt request signal (INTAD) is generated if the conditions match. <Complete A/D conversion> <12> Clear ADCS to 0. <13> Clear ADCE to 0. Cautions 1. Make sure the period of <3> to <6> is 14 s or more. 2. It is no problem if the order of <3>, <4>, and <5> is changed. 3. <3> must not be omitted if the power-fail function is used. 4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0. 282 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-13. Overall Error Figure 13-14. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 0......0 Analog input 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. User's Manual U15947EJ3V1UD 283 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-15. Zero-Scale Error Figure 13-16. Full-Scale Error Full-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 Ideal line 011 010 001 Zero-scale error 000 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 13-17. Integral Linearity Error Figure 13-18. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Differential linearity error Integral linearity error 0......0 0 Analog input 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time 284 Conversion time User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 (see Figure 13-2). (2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end of conversion ADCR read has priority. After the read operation, the new conversion result is written to ADCR. <2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 13-19, to reduce noise. Figure 13-19. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI7 C = 100 to 1,000 pF AVSS VSS User's Manual U15947EJ3V1UD 285 CHAPTER 13 A/D CONVERTER (5) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 13-19). (7) AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. 286 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 13-20. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ANIn ADCR ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF Remarks 1. n = 0 to 7 2. m = 0 to 7 (9) Conversion results just after A/D conversion start The A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 14 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. User's Manual U15947EJ3V1UD 287 CHAPTER 13 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-21 and Table 13-3. Figure 13-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait period A/D Sampling conversion time start delay time Sampling time Conversion time Conversion time Table 13-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) FR2 FR1 FR0 Conversion Time Sampling Time A/D Conversion Start Delay Time MIN. MAX. 0 0 0 288/fX 40/fX 32/fX 36/fX 0 0 1 240/fX 32/fX 28/fX 32/fX 0 1 0 192/fX 24/fX 24/fX 28/fX 1 0 0 144/fX 20/fX 16/fX 18/fX 1 0 1 120/fX 16/fX 14/fX 16/fX 1 1 0 96/fX 12/fX 12/fX 14/fX Other than above - Setting prohibited Note - - Note The A/D conversion start delay time is the time after wait period. For the wait function, see CHAPTER 36 CAUTIONS FOR WAIT. Remark fX: X1 input clock oscillation frequency (12) Register generating wait cycle Do not read data from the ADCR register and do not write data to the ADM, ADS, PFM, and PFT registers while the CPU is operating on the subsystem clock and while oscillation of the clock input to X1 is stopped. 288 User's Manual U15947EJ3V1UD CHAPTER 13 A/D CONVERTER (13) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin R1 R2 ANIn C1 C2 C3 Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF R1 R2 C1 C2 C3 2.7 V 12 k 8 k 8 pF 3 pF 2 pF 4.5 V 4 k 2.7 k 8 pF 1.4 pF 2 pF Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values. 2. n = 0 to 7 User's Manual U15947EJ3V1UD 289 CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 14.4.2 Asynchronous serial interface (UART) mode and 14.4.3 Dedicated baud rate generator. * Two-pin configuration TXD0: Transmit data output pin RXD0: Receive data input pin * Length of communication data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Four operating clock inputs selectable * Fixed to LSB-first communication Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 290 User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 14.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Registers Configuration Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Port mode register 1 (PM1) Port register 1 (P1) User's Manual U15947EJ3V1UD 291 292 Figure 14-1. Block Diagram of Serial Interface UART0 Filter RxD0/ SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial interface operation mode register 0 (ASIM0) fX/23 Baud rate generator Reception control Receive buffer register 0 (RXB0) INTST0 Transmission control Transmit shift register 0 (TXS0) Reception unit Internal bus 8-bit timer/ event counter 50 output User's Manual U15947EJ3V1UD INTSR0 Baud rate generator control register 0 (BRGC0) 7 Baud rate generator 7 TxD0/ SCK10/P10 Output latch (P10) Registers Transmission unit PM10 CHAPTER 14 SERIAL INTERFACE UART0 fX/2 5 Asynchronous serial interface reception error status register 0 (ASIS0) Selector fX/2 CHAPTER 14 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input or POWER0 = 0 sets this register to FFH. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pins. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. RESET input, POWER0 = 0, or TXE0 = 0 sets this register to FFH. Caution Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. User's Manual U15947EJ3V1UD 293 CHAPTER 14 SERIAL INTERFACE UART0 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial communication operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2) Address: FF70H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Enables/disables transmission 0 Disables transmission (synchronously resets the transmission circuit). 1 Enables transmission. RXE0 2. . Enables operation of the internal operation clock. TXE0 Notes 1. Note 2 Enables/disables reception 0 Disables reception (synchronously resets the reception circuit). 1 Enables reception. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. 294 User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity. CL0 Reception operation Note Specifies character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL0 Specifies number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to 0, and then clear POWER0 to 0. 2. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to 0, and then clear POWER0 to 0. 3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. 4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 6. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. 7. Be sure to set bit 0 to 1. User's Manual U15947EJ3V1UD 295 CHAPTER 14 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input or clearing bit 7 (POWER0) or bit 5 (RXE0) of ASIM0 to 0 clears this register to 00H. 00H is read when this register is read. Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) Address: FF73H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS0 0 0 0 0 0 PE0 FE0 OVE0 PE0 Status flag indicating parity error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If the parity of transmit data does not match the parity bit on completion of reception. FE0 Status flag indicating framing error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If the stop bit is not detected on completion of reception. OVE0 Status flag indicating overrun error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If receive data is set to the RXB0 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. 296 User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH. Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FF71H After reset: 1FH R/W Symbol 7 6 5 4 3 2 1 0 BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00 TPS01 TPS00 0 0 TM50 output 0 1 fX/2 (5 MHz) 1 0 fX/2 (1.25 MHz) 1 1 fX/2 (312.5 kHz) MDL04 MDL03 Base clock (fXCLK0) selection Note 1 Note 2 3 5 MDL02 MDL01 MDL00 k Selection of 5-bit counter output clock Notes 1. 0 0 x x x x Setting prohibited 0 1 0 0 0 8 fXCLK0/8 0 1 0 0 1 9 fXCLK0/9 0 1 0 1 0 10 fXCLK0/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 0 1 0 26 fXCLK0/26 1 1 0 1 1 27 fXCLK0/27 1 1 1 0 0 28 fXCLK0/28 1 1 1 0 1 29 fXCLK0/29 1 1 1 1 0 30 fXCLK0/30 1 1 1 1 1 31 fXCLK0/31 Set the base clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Base clock 10 MHz * VDD = 3.3 to 4.0 V: Base clock 8.38 MHz * VDD = 2.7 to 3.3 V: Base clock 5 MHz * VDD = 2.5 to 2.7 V: Base clock 2.5 MHz 2. When selecting the TM50 output as the base clock, note the following. * PWM mode (TMC506 = 1) Set the clock to 50% duty and start the 8-bit timer/event counter 50 operation beforehand. * Mode in which clear & start occurs on a match of TM50 and CR50 (TMC506 = 0) Enable the timer F/F inversion operation (TMC501 = 1) and start the 8-bit timer/event counter 50 operation beforehand. In the both modes, it is not necessary to enable the timer output for the TO50 pin. User's Manual U15947EJ3V1UD 297 CHAPTER 14 SERIAL INTERFACE UART0 Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the base clock is the internal oscillation clock, the operation of serial interface UART0 is not guaranteed. 2. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 3. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fX: X1 input clock oscillation frequency 3. k: 4. x: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) Don't care 5. Figures in parentheses apply to operation at fX = 10 MHz. 6. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) 7. TMC501: Bit 1 of TMC50 (4) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of P10 to 1. When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 14-5. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 298 After reset: FFH P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Address: FF70H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit TXE0 0 Notes 1. 2. . Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). RXE0 0 Note 2 Enables/disables reception Disables reception (synchronously resets the reception circuit). The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1. Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. User's Manual U15947EJ3V1UD 299 CHAPTER 14 SERIAL INTERFACE UART0 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the BRGC0 register (see Figure 14-4). <2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 14-2). <3> Set bit 7 (POWER0) of the ASIM0 register to 1. <4> Set bit 6 (TXE0) of the ASIM0 register to 1. Transmission is enabled. Set bit 5 (RXE0) of the ASIM0 register to 1. Reception is enabled. <5> Write data to the TXS0 register. Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER0 0 1 TXE0 0 0 RXE0 0 1 PM10 x Note x Note P10 PM11 Pin Function TxD0/SCK10/P10 RxD0/SI10/P11 Stop SCK10/P10 SI10/P11 x x Note 1 x Reception SCK10/P10 RxD0 Note Note Transmission TxD0 SI10/P11 x Transmission/ TxD0 RxD0 1 0 0 1 1 1 0 1 x 1 x x Note UART0 Operation Note x Note P11 reception Note Can be set as port function. Remark x: don't care POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: 300 Bit 6 of ASIM0 RXE0: Bit 5 of ASIM0 PM1x: Port mode register P1x: Port output latch User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity bit D7 Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (ASIM0). Figure 14-7. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 User's Manual U15947EJ3V1UD D6 D7 Stop 301 CHAPTER 14 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. 302 User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (c) Transmission The TXD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 14-8. Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST0 2. Stop bit length: 2 TXD0 (output) Stop INTST0 User's Manual U15947EJ3V1UD 303 CHAPTER 14 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR0) is generated after completion of reception. Figure 14-9. Reception Completion Interrupt Request Timing RXD0 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR0 RXB0 Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0) before reading RXB0. 304 User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt servicing (INTSR0) (see Figure 14-3). The contents of ASIS0 are reset to 0 when ASIS0 is read. Table 14-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). (f) Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-10. Noise Filter Circuit Base clock RXD0/SI10/P11 In Q Internal signal A Match detector User's Manual U15947EJ3V1UD In Q Internal signal B LD_EN 305 CHAPTER 14 SERIAL INTERFACE UART0 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed to low level when POWER0 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Figure 14-11. Configuration of Baud Rate Generator POWER0 Baud rate generator fX/2 POWER0, TXE0 (or RXE0) fX/23 Selector 5-bit counter fXCLK0 fX/25 8-bit timer/ event counter 50 output Match detector BRGC0: TPS01, TPS00 Remark 306 1/2 Baud rate BRGC0: MDL04 to MDL00 POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: Bit 6 of ASIM0 RXE0: Bit 5 of ASIM0 BRGC0: Baud rate generator control register 0 User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK0 [bps] 2xk fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78,125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%] User's Manual U15947EJ3V1UD 307 CHAPTER 14 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator Baud Rate [bps] fX = 10.0 MHz TPS01, k TPS00 fX = 8.38 MHz Calculated ERR[%] Value TPS01, k TPS00 fX = 4.19 MHz Calculated ERR[%] Value TPS01, k TPS00 Calculated ERR[%] Value 2400 - - - - - - - - 3 27 2425 1.03 4800 - - - - 3 27 4850 1.03 3 14 4676 -2.58 9600 3 16 9766 1.73 3 14 9353 -2.58 2 27 9699 1.03 10400 3 15 10417 0.16 3 13 10072 -3.15 2 25 10475 0.72 19200 3 8 19531 1.73 2 27 19398 1.03 2 14 18705 -2.58 31250 2 20 31250 0 2 17 30809 -1.41 - - - - 38400 2 16 39063 1.73 2 14 38796 -2.58 2 27 38796 1.03 76800 2 8 78125 1.73 1 27 77593 1.03 1 14 74821 -2.58 115200 1 22 113636 -1.36 1 18 116389 1.03 1 9 116389 1.03 153600 1 16 156250 1.73 1 14 149643 -2.58 - - - - 230400 1 11 227273 -1.36 1 9 232778 1.03 - - - - Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK0)) k: 308 Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) fX: X1 input clock oscillation frequency ERR: Baud rate error User's Manual U15947EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-12. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART0 Start bit Bit 0 Bit 1 Bit 7 Stop bit Parity bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART0 k: Set value of BRGC0 FL: 1-bit data length Margin of latch timing: 2 clocks User's Manual U15947EJ3V1UD 309 CHAPTER 14 SERIAL INTERFACE UART0 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 FL 2k Therefore, the maximum receivable baud rate at the transmission destination is as follows. -1 BRmax = (FLmin/11) = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k Brate 21k - 2 The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 14-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 16 +4.14% -4.19% 24 +4.34% -4.38% 31 +4.44% -4.47% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC0 310 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 15.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 15.4.2 Asynchronous serial interface (UART) mode and 15.4.3 Dedicated baud rate generator. * Two-pin configuration TXD6: Transmit data output pin RXD6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Twelve operating clock inputs selectable * MSB- or LSB-first communication selectable * Inverted transmission operation * Synchronous break field transmission is 13-bit length output * More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if UART6 is used in the LIN communication operation. User's Manual U15947EJ3V1UD 311 CHAPTER 15 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 15-1 and 15-2 outline the transmission and reception operations of LIN. Figure 15-1. LIN Transmission Operation Wakeup signal frame Synchronous break field Synchronous field Identifier field Data field Data field Checksum field Sleep bus Note 1 8 bits 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TX6 Note 3 INTST6 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The synchronous break field is output by hardware. The output width is adjusted by baud rate generator control register 6 (BRGC6) (see 15.4.2 (2) (h) SBF transmission). 3. Remark 312 INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-2. LIN Reception Operation Wakeup signal frame Synchronous break field Synchronous field Identifier field Data field Data field Checksum field 13 bitsNote 2 SF reception ID reception Data reception Data Data reception receptionNote 5 Sleep bus RX6 Disable Enable SBF reception Note 3 Reception interrupt (INTSR6) Edge detection Note 1 (INTP0) Note 4 Capture timer Notes 1. Disable Enable The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. 2. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. 3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. 4. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). 5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. To perform a LIN receive operation, use a configuration like the one shown in Figure 15-3. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally. User's Manual U15947EJ3V1UD 313 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode (PM120) Output latch (P120) Port input switch control (ISC0) <ISC0> 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector Selector P00/TI000 TI000 input Port mode (PM00) Output latch (P00) Remark Port input switch control (ISC1) <ISC1> 0: Select TI000 (P00) 1: Select RxD6 (P14) ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11) The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> * External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. * 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the synchronous field (SF) length and divides it by the number of bits. * Serial interface UART6 314 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 15.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Registers Configuration Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) User's Manual U15947EJ3V1UD 315 316 Figure 15-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note Filter INTSR6 Reception control INTSRE6 Selector Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) Transmission control Transmit shift register 6 (TXS6) Reception unit Internal bus Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) Baud rate generator 8 INTST6 TXD6/ P13 Registers Output latch (P13) Transmission unit Note Selectable with input switch control register (ISC). PM13 CHAPTER 15 SERIAL INTERFACE UART6 User's Manual U15947EJ3V1UD fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 8-bit timer/ event counter 50 output RXD6/ P14 CHAPTER 15 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. User's Manual U15947EJ3V1UD 317 CHAPTER 15 SERIAL INTERFACE UART6 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Note 3 . Enables operation of the internal operation clock TXE6 Notes 1. Note 2 Enables/disables transmission 0 Disables transmission (synchronously resets the transmission circuit). 1 Enables transmission The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the POWER6 bit. 318 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception 0 Disables reception (synchronously resets the reception circuit). 1 Enables reception PS61 PS60 Transmission operation Reception operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity. CL6 Specifies character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL6 Specifies number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 ISRM6 Note Enables/disables occurrence of reception completion interrupt in case of error 0 "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). 1 "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0, and then clear POWER6 to 0. 2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0, and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 5. Fix the PS61 and PS60 bits to 0 when UART6 is used in the LIN communication operation. 6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. User's Manual U15947EJ3V1UD 319 CHAPTER 15 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read when this register is read. Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF53H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS6 0 0 0 0 0 PE6 FE6 OVE6 PE6 Status flag indicating parity error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. 320 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 15-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF55H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIF6 0 0 0 0 0 0 TXBF6 TXSF6 TXBF6 Transmit buffer data flag 0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) 1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. User's Manual U15947EJ3V1UD 321 CHAPTER 15 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 0 0 0 0 fX (10 MHz) 0 0 0 1 fX/2 (5 MHz) 0 0 1 0 fX/2 (2.5 MHz) 0 0 1 1 fX/2 (1.25 MHz) 0 1 0 0 fX/2 (625 kHz) 0 1 0 1 fX/2 (312.5 kHz) 0 1 1 0 fX/2 (156.25 kHz) 0 1 1 1 fX/2 (78.13 kHz) 1 0 0 0 fX/2 (39.06 kHz) 1 0 0 1 fX/2 (19.53 kHz) 1 0 1 0 fX/2 (9.77 kHz) 1 0 1 1 TM50 output Other than above Notes 1. Base clock (fXCLK6) selection Note 1 2 3 4 5 6 7 8 9 10 Note 2 Setting prohibited Set the base clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Base clock 10 MHz * VDD = 3.3 to 4.0 V: Base clock 8.38 MHz * VDD = 2.7 to 3.3 V: Base clock 5 MHz * VDD = 2.5 to 2.7 V: Base clock 2.5 MHz 2. When selecting the TM50 output as the base clock, note the following. * PWM mode (TMC506 = 1) Set the clock to 50% duty and start the 8-bit timer/event counter 50 operation beforehand. * Mode in which clear & start occurs on a match of TM50 and CR50 (TMC506 = 0) Enable the timer F/F inversion operation (TMC501 = 1) and start the 8-bit timer/event counter 50 operation beforehand. In the both modes, it is not necessary to enable the timer output for the TO50 pin. 322 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the base clock is the internal oscillation clock, the operation of serial interface UART6 is not guaranteed. 2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF57H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8-bit counter 0 0 0 0 0 x x x x Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6/8 0 0 0 0 1 0 0 1 9 fXCLK6/9 0 0 0 0 1 0 1 0 10 fXCLK6/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 0 252 fXCLK6/252 1 1 1 1 1 1 0 1 253 fXCLK6/253 1 1 1 1 1 1 1 0 254 fXCLK6/254 1 1 1 1 1 1 1 1 255 fXCLK6/255 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) 3. x: Don't care User's Manual U15947EJ3V1UD 323 CHAPTER 15 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an interrupt signal is generated). Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) Address: FF58H After reset: 16H R/W Note Symbol <7> <6> 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 0 1 0 1 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger 0 - 1 SBF reception trigger DIR6 First bit specification 0 MSB 1 LSB TXDLV6 Enables/disables inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Note Bits 2 to 5 and 7 are read-only. Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode. The status of the SBRF6 flag is held (1). 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. 324 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 15-11. Format of Input Switch Control Register (ISC) Address: FF4FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 (P00) 1 RxD6 (P14) ISC0 INTP0 input source selection 0 INTP0 (P120) 1 RxD6 (P14) (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TxD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. When using the P14/RxD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 15-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD 325 CHAPTER 15 SERIAL INTERFACE UART6 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit TXE6 0 Notes 1. . Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6 0 Note 2 Enables/disables reception Disables reception (synchronously resets the reception circuit). The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when POWER6 = 0. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode. To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. Remark To use the RxD6/P14 and TxD6/P13 pins as general-purpose port pins, see CHAPTER 4 FUNCTIONS. 326 User's Manual U15947EJ3V1UD PORT CHAPTER 15 SERIAL INTERFACE UART6 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 15-8). <2> Set the BRGC6 register (see Figure 15-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 15-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 15-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. User's Manual U15947EJ3V1UD 327 CHAPTER 15 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 P13 PM14 P14 UART6 Operation 0 0 0 x Note x Note 1 0 1 x Note x Note 1 0 0 1 1 1 0 1 x Note 1 x Note 1 x Note Pin Function TxD6/P13 Stop P13 P14 Reception P13 RxD6 Note Transmission TxD6 P14 x Transmission/ TxD6 RxD6 x x reception Note Can be set as port function. Remark x: don't care POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) 328 TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 PM1x: Port mode register P1x: Port output latch RxD6/P14 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. User's Manual U15947EJ3V1UD 329 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start 330 D0 D1 D2 D3 D4 D5 User's Manual U15947EJ3V1UD D6 D7 Stop Stop CHAPTER 15 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. User's Manual U15947EJ3V1UD 331 CHAPTER 15 SERIAL INTERFACE UART6 (c) Normal transmission The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 15-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 15-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) INTST6 332 User's Manual U15947EJ3V1UD Stop CHAPTER 15 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is incorporated in a LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 Transmission Status 0 Transmission is completed. 1 Transmission is in progress. Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, an overrun error may occur, which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame. An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. User's Manual U15947EJ3V1UD 333 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6. Transmission completion interrupt occurs? No Yes Transfer executed necessary number of times? Yes No Read ASIF6 TXSF6 = 0? Yes Yes of Completion transmission processing Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) 334 User's Manual U15947EJ3V1UD No CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 User's Manual U15947EJ3V1UD 335 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-18. Timing of Ending Continuous Transmission TXD6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop INTST6 TXB6 Data (n - 1) Data (n) Data (n - 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: 336 Bit 6 of asynchronous serial interface operation mode register 6 (ASIM6) User's Manual U15947EJ3V1UD FF CHAPTER 15 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 15-19. Reception Completion Interrupt Request Timing RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. User's Manual U15947EJ3V1UD 337 CHAPTER 15 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing (INTSR6/INTSRE6) (see Figure 15-6). The contents of ASIS6 are reset to 0 when ASIS6 is read. Table 15-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 15-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception 338 (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 15-21. Noise Filter Circuit Base clock RXD6/P14 In Internal signal A Q Match detector In Q Internal signal B LD_EN (h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 15-1 LIN Transmission Operation. SBF transmission is used to transmit an SBF length that is a low-level width of 13 bits or more by adjusting the baud rate value of the ordinary UART transmission function. [Setting method] Transmit 00H by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. This enables a low-level transmission of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). Adjust the baud rate value to adjust this 10-bit low level to the targeted SBF length. Example If LIN is to be transmitted under the following conditions * Base clock of UART6 = 5 MHz (set by clock selection register 6 (CKSR6)) * Target baud rate value = 19200 bps To realize the above baud rate value, the length of a 13-bit SBF is as follows if the baud rate generator control register 6 (BRGC6) is set to 130. * 13-bit SBF length = 0.2 s x 130 x 2 x 13 = 676 s To realize a 13-bit SBF length in 10 bits, set a value 1.3 times the targeted baud rate to BRGC6. In this example, set 169 to BRGC6. The transmission length of a 10-bit low level in this case is as follows, and matches the 13-bit SBF length. * 10-bit low-level transmission length = 0.2 s x 169 x 2 x 10 = 676 s User's Manual U15947EJ3V1UD 339 CHAPTER 15 SERIAL INTERFACE UART6 If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Figure 15-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to generalpurpose register. Clear TXE6 and RXE6 bits of ASIM6 register to 0 (to disable transmission/ reception). Set value to BRGC6 register to realize desired SBF length. Clear TXE6 and RXE6 bits of ASIM6 register to 0. Set character length of data to 8 bits and parity to 0 or even using ASIM6 register. Rewrite saved BRGC6 value to BRGC6 register. Set TXE6 bit of ASIM6 register to 1 to enable transmission. Re-set PS61 bit, PS60 bit, and CL6 bit of ASIM6 register to desired value. Set TXB6 register to "00H" and start transmission. Set TXE6 bit of ASIM6 register to 1 to enable transmission. End No INTST6 occurred? Yes Figure 15-23. SBF Transmission 1 TXD6 2 3 4 5 6 7 8 9 INTST6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request 340 User's Manual U15947EJ3V1UD 10 11 12 13 Stop CHAPTER 15 SERIAL INTERFACE UART6 (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 15-24. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) 1 RXD6 2 3 4 5 6 7 8 9 10 11 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) 1 RXD6 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 Remark RXD6: "0" RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request User's Manual U15947EJ3V1UD 341 CHAPTER 15 SERIAL INTERFACE UART6 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. 342 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-25. Configuration of Baud Rate Generator POWER6 fX Baud rate generator fX/2 fX/22 POWER6, TXE6 (or RXE6) fX/23 fX/24 fX/25 Selector fX/26 8-bit counter fXCLK6 fX/27 fX/28 fX/29 fX/210 8-bit timer/ event counter 50 output Match detector CKSR6: TPS63 to TPS60 Remark 1/2 Baud rate BRGC6: MDL67 to MDL60 POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 CKSR6: Clock selection register 6 BRGC6: Baud rate generator control register 6 User's Manual U15947EJ3V1UD 343 CHAPTER 15 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 [bps] 2xk fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] 344 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 15-4. Set Data of Baud Rate Generator Baud Rate [bps] fX = 10.0 MHz TPS63 to k TPS60 fX = 8.38 MHz Calculated ERR[%] TPS63 to Value TPS60 k fX = 4.19 MHz Calculated ERR[%] TPS63 to Value TPS60 k Calculated ERR[%] Value 600 6H 130 601 0.16 6H 109 601 0.11 5H 109 601 0.11 1200 5H 130 1202 0.16 5H 109 1201 0.11 4H 109 1201 0.11 2400 4H 130 2404 0.16 4H 109 2403 0.11 3H 109 2403 0.11 4800 3H 130 4808 0.16 3H 109 4805 0.11 2H 109 4805 0.11 9600 2H 130 9615 0.16 2H 109 9610 0.11 1H 109 9610 0.11 10400 2H 120 10417 0.16 2H 101 10371 0.28 1H 101 10475 -0.28 19200 1H 130 19231 0.16 1H 109 19220 0.11 0H 109 19220 0.11 31250 1H 80 31250 0.00 0H 134 31268 0.06 0H 67 31268 0.06 38400 0H 130 38462 0.16 0H 109 38440 0.11 0H 55 38090 -0.80 76800 0H 65 76923 0.16 0H 55 76182 -0.80 0H 27 77593 1.03 115200 0H 43 116279 0.94 0H 36 116389 1.03 0H 18 116389 1.03 153600 0H 33 151515 -1.36 0H 27 155185 1.03 0H 14 149643 -2.58 230400 0H 22 227272 -1.36 0H 18 232778 1.03 0H 9 232778 1.03 Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) fX: X1 input clock oscillation frequency ERR: Baud rate error User's Manual U15947EJ3V1UD 345 CHAPTER 15 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 15-26. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 Bit 1 Bit 7 Stop bit Parity bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 15-26, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: Set value of BRGC6 FL: 1-bit data length Margin of latch timing: 2 clocks 346 User's Manual U15947EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 FL 2k Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k -1 Brate BRmax = (FLmin/11) = 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k Brate 21k - 2 The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 15-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 User's Manual U15947EJ3V1UD 347 CHAPTER 15 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 15-27. Data Frame Length During Continuous Transmission Start bit of second byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 348 User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The PD780143 and 780144 incorporate serial interface CSI10, and the PD780146, 780148, and 78F0148 incorporate serial interfaces CSI10 and CSI11. 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 16.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK1n) and two serial data lines (SI1n and SO1n). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 16.4.2 3-wire serial I/O mode. User's Manual U15947EJ3V1UD 349 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Transmit buffer register 1n (SOTB1n) Registers Serial I/O shift register 1n (SIO1n) Serial operation mode register 1n (CSIM1n) Control registers Serial clock selection register 1n (CSIC1n) Port mode register 0 (PM0) or port mode register 1 (PM1) Port register 0 (P0) or port register 1 (P1) Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 16-1. Block Diagram of Serial Interface CSI10 Internal bus 8 8 Serial I/O shift register 10 (SIO10) SI10/P11/RXD0 Transmit data controller Transmit buffer register 10 (SOTB10) Output latch Output selector SO10/P12 Output latch (P12) 350 Selector Transmit controller fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 SCK10/P10/TxD0 Clock start/stop controller & clock phase controller User's Manual U15947EJ3V1UD INTCSI10 PM12 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-2. Block Diagram of Serial Interface CSI11 (PD780146, 780148, and 78F0148 Only) Internal bus SI11/P03 8 8 Serial I/O shift register 11 (SIO11) Transmit buffer register 11 (SOTB11) Transmit data controller Output selector SO11/P02 Output latch (P02) Output latch SSI11 PM02 Selector Transmit controller fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 SCK11/P04 Clock start/stop controller & clock phase controller INTCSI11 (1) Transmit buffer register 1n (SOTB1n) This register sets the transmit data. Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to the serial output pin (SO1n). SOTB1n can be written or read by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication). 2. The SSI11 pin can be used in the slave mode. For details of the transmission/reception operation, see 16.4.2 (2) Communication operation. (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. During reception, the data is read from the serial input pin (SI1n) to SIO1n. RESET input clears this register to 00H. Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication). 2. The SSI11 pin can be used in the slave mode. For details of the reception operation, see 16.4.2 (2) Communication operation. PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Remark n = 0: User's Manual U15947EJ3V1UD 351 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) (1) Serial operation mode register 1n (CSIM1n) CSIM1n is used to select the operation mode and enable or disable operation. CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark PD780143, 780144 n = 0: n = 0, 1: PD780146, 780148, 78F0148 Figure 16-3. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD10 0 Note 5 1 DIR10 . Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode Note 6 First bit specification 0 MSB 1 LSB CSOT10 Notes 1. Note 3 Communication status flag 0 Communication is stopped. 1 Communication is in progress. Bit 0 is a read-only bit. 2. When using P10/SCK10/TxD0, P11/SI10/RxD0, or P12/SO10 as a general-purpose port, see 3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. CHAPTER 4 PORT FUNCTIONS, Caution 3 of Figure 16-5, and Table 16-2. 4. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). 5. The SO10 output is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. 6. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). Caution Be sure to clear bit 5 to 0. 352 User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Address: FF88H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD11 0 Note 5 1 SSE11 Transmit/receive mode control Receive mode (transmission disabled). Notes 6, 7 SSI11 pin use selection 0 SSI11 pin is not used 1 SSI11 pin is used Note 8 First bit specification 0 MSB 1 LSB CSOT11 2. . Transmit/receive mode DIR11 Notes 1. Note 3 Communication status flag 0 Communication is stopped. 1 Communication is in progress. Bit 0 is a read-only bit. When using P02/SO11, P03/SI11, or P04/SCK11 as a general-purpose port, see CHAPTER 4 PORT FUNCTIONS, Caution 3 of Figure 16-6, and Table 16-2. 3. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. 4. Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication). 5. The SO11 output is fixed to the low level when TRMD11 is 0. Reception is started when data is read from SIO11. 6. Do not rewrite SSE11 when CSOT11 = 1 (during serial communication). 7. Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1. 8. Do not rewrite DIR11 when CSOT11 = 1 (during serial communication). User's Manual U15947EJ3V1UD 353 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CSIC10 0 0 0 CKP10 DAP10 CKS102 CKS101 CKS100 CKP10 DAP10 0 0 Specification of data transmission/reception timing Type 1 SCK10 D7 D6 D5 D4 D3 D2 D1 D0 SO10 SI10 input timing 0 1 2 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 1 0 3 SCK10 D7 D6 D5 D4 D3 D2 D1 D0 SO10 SI10 input timing 1 1 4 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing CKS102 CKS101 CKS100 0 0 0 0 0 1 CSI10 serial clock selection fX/2 (5 MHz) 2 fX/2 (2.5 MHz) Master mode 5 Master mode 6 Master mode 7 fX/2 (1.25 MHz) 1 fX/2 (625 kHz) 1 0 0 fX/2 (312.5 kHz) fX/2 (156.25 kHz) 1 1 0 fX/2 (78.13 kHz) Master mode 1 1 1 External clock input to SCK10 Slave mode Note Set the serial clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Serial clock 5 MHz * VDD = 3.3 to 4.0 V: Serial clock 4.19 MHz * VDD = 2.7 to 3.3 V: Serial clock 2.5 MHz * VDD = 2.5 to 2.7 V: Serial clock 1.25 MHz 354 Master mode Master mode 0 1 1 Master mode 4 1 0 0 Mode 3 0 1 Note User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Cautions 1. When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of the internal oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed. 2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 3. Clear CKP10 to 0 to use P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 as general-purpose port pins. 4. The phase type of the data clock is type 1 after reset. Remarks 1. Figures in parentheses are for operation with fx = 10 MHz. 2. fX: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD 355 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CSIC11 0 0 0 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 0 0 Specification of data transmission/reception timing Type 1 SCK11 D7 D6 D5 D4 D3 D2 D1 D0 SO11 SI11 input timing 0 1 2 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 1 0 3 SCK11 D7 D6 D5 D4 D3 D2 D1 D0 SO11 SI11 input timing 1 1 4 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing CKS112 CKS111 CKS110 0 0 0 fX/2 (5 MHz) 0 0 1 fX/2 (2.5 MHz) 0 0 1 1 1 1 0 0 0 1 0 1 CSI11 serial clock selection Note Mode Master mode 2 Master mode 3 Master mode 4 Master mode 5 Master mode 6 Master mode 7 fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) 1 1 0 fX/2 (78.13 kHz) Master mode 1 1 1 External clock input to SCK11 Slave mode Note Set the serial clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Serial clock 5 MHz * VDD = 3.3 to 4.0 V: Serial clock 4.19 MHz * VDD = 2.7 to 3.3 V: Serial clock 2.5 MHz * VDD = 2.5 to 2.7 V: Serial clock 1.25 MHz Cautions 1. When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of the internal oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI11 is not guaranteed. 2. Do not write to CSIC11 while CSIE11 = 1 (operation enabled). 3. Clear CKP11 to 0 to use P02/SO11, P03/SI11, and P04/SCK11 as general-purpose port pins. 4. The phase type of the data clock is type 1 after reset. Remarks 1. Figures in parentheses are for operation with fx = 10 MHz. 2. fX: X1 input clock oscillation frequency 356 User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. When using P10/SCK10 and P04/SCK11Note as the clock output pins of the serial interface, clear PM10 and PM04 to 0 and set the output latches of P10 and P04 to 1. When using P12/SO10 and P02/SO11Note as the data output pins of the serial interface, clear PM12 and PM02, and the output latches of P12 and P02 to 0. When using P10/SCK10 and P04/SCK11Note as the clock input pins of the serial interface, P11/SI10/RxD0 and P03/SI11Note as the data input pins, and P05/SSI11/TI001 as the chip select input pin, set PM10, PM04, PM11, PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1. PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Note PD780146, 780148, 78F0148 only. Figure 16-7. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH 6 5 4 R/W Symbol 7 3 2 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 6) 0 Output mode (output buffer on) 1 Input mode (output buffer off) 1 0 Figure 16-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol 7 After reset: FFH 6 5 4 R/W 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD 357 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD0, P11/SI10/RXD0, P12/SO10, P02/SO11Note, P03/SI11Note, and P04/SCK11Note pins can be used as ordinary I/O port pins in this mode. Note PD780146, 780148, and 78F0148 only (1) Register used The operation stop mode is set by serial operation mode register 1n (CSIM1n). To set the operation stop mode, clear bit 7 (CSIE1n) of CSIM1n to 0. (a) Serial operation mode register 1n (CSIM1n) CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1n to 00H. PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Remark n = 0: * Serial operation mode register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 0 Notes 1. Operation control in 3-wire serial I/O mode Note 1 Disables operation and asynchronously resets the internal circuit Note 2 . To use the SI10/RxD0/P11, SO10/P12, and SCK10/TxD0/P10 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS, Caution 3 of Figure 16-5, and Table 16-2. 2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. * Serial operation mode register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 0 Notes 1. Operation control in 3-wire serial I/O mode Note 1 Disables operation and asynchronously resets the internal circuit Note 2 . To use the SI11/P03, SO11/P02, SCK11/P04, and SSI11/TI001/P05 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS, Caution 3 of Figure 16-6, and Table 16-2. 2. 358 Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines. (1) Registers used * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC1n register (see Figures 16-5 and 16-6). <2> Set bits 0 and 4 to 6 (CSOT1n, DIR1n, SSE11 (serial interface CSI11 only), and TRMD1n) of the CSIM1n register (see Figures 16-3 and 16-4). <3> Set bit 7 (CSIE1n) of the CSIM1n register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 1n (SOTB1n). Data transmission/reception is started. Read data from serial I/O shift register 1n (SIO1n). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD 359 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 CSI10 P10 Pin Function Operation SI10/RxD0/ SO10/P12 P11 0 x x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop SCK10/ TxD0/P10 RxD0/P11 P12 TxD0/ P10 1 0 1 x x Note 1 x Note 1 1 Slave x reception 1 1 x Note 1 x Note 1 0 0 1 SI10 Slave x P12 Note 3 Note 3 RxD0/P11 SO10 Note 3 1 1 x 0 0 1 Slave x reception 1 0 1 x x x Note 1 0 1 SCK10 Note 3 (input) SI10 SO10 SCK10 Note 3 transmission/ Note 1 SCK10 (input) transmission 1 Note 2 (input) Note 3 Master reception SI10 P12 SCK10 (output) 1 1 x Note 1 x Note 1 0 0 0 Master 1 RxD0/P11 SO10 transmission 1 1 1 x 0 0 0 Master 1 SI10 SO10 transmission/ reception Notes 1. Can be set as port function. 2. To use P10/SCK10/TxD0 as port pins, clear CKP10 to 0. 3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. Remark x: don't care CSIE10: Bit 7 of serial operation mode register 10 (CSIM10) TRMD10: Bit 6 of CSIM10 CKP10: Bit 4 of serial clock selection register 10 (CSIC10) CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 360 PM1x: Port mode register P1x: Port output latch User's Manual U15947EJ3V1UD SCK10 (output) SCK10 (output) CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 ( PD780146, 780148, 78F0148 only) CSI11 CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 Pin Function Operation 0 x x x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop SI11/ SO11/ SCK11/ SSI11/ P03 P02 P04 TI001/P05 P03 P02 P04 Note 2 TI001/ P05 1 0 0 1 x 1 x Slave reception SI11 P02 Note 3 SCK11 TI001/ (input) P05 Note 3 1 1 1 1 0 x Note 1 x Note 1 0 0 1 x x Note 1 x x SSI11 Note 1 Slave P03 SO11 Note 3 transmission SCK11 TI001/ (input) P05 Note 3 1 1 1 1 0 1 x 0 0 1 x x Note 1 x x SSI11 Note 1 Slave SI11 SO11 transmission/ 1 1 0 1 0 1 x x Note 1 x Note 1 0 1 x Note 1 reception x x Note 1 Note 3 Master 1 1 0 x x Note 1 0 0 0 1 x Note 1 x Note 1 Master 1 1 0 1 x 0 0 0 1 x x Note 1 Master P05 SSI11 SI11 P02 P03 SO11 transmission Note 1 TI001/ (input) Note 3 reception Note 1 SCK11 SI11 SO11 transmission/ SCK11 TI001/ (output) P05 SCK11 TI001/ (output) P05 SCK11 TI001/ (output) P05 reception Notes 1. Can be set as port function. 2. To use P04/SCK11 as port pins, clear CKP11 to 0. 3. To use the slave mode, set CKS112, CKS111, and CKS110 to 1, 1, 1. Remark x: don't care CSIE11: Bit 7 of serial operation mode register 11 (CSIM11) TRMD11: Bit 6 of CSIM11 CKP11: Bit 4 of serial clock selection register 11 (CSIC11) CKS112, CKS111, CKS110: Bits 2 to 0 of CSIC11 PM0x: Port mode register P0x: Port output latch User's Manual U15947EJ3V1UD 361 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition, data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. Reception is started when data is read from serial I/O shift register 1n (SIO1n). However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in the slave mode. <1> Low level input to the SSI11 pin Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read. <2> High level input to the SSI11 pin Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read, transmission/reception or reception will not be started. <3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low level is input to the SSI11 pin Transmission/reception or reception is started. <4> A high level is input to the SSI11 pin during transmission/reception or reception Transmission/reception or reception is suspended. After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared to 0. Then the next communication is enabled. Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial communication). 2. When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. Remark 362 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) (1) Transmission/reception timing (Type 1; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (receive AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 363 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (input AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 364 User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-10. Timing of Clock/Data Phase (a) Type 1; CKP1n = 0, DAP1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (b) Type 2; CKP1n = 0, DAP1n = 1 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (c) Type 3; CKP1n = 1, DAP1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (d) Type 4; CKP1n = 1, DAP1n = 1 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 365 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11. Output Operation of First Bit (1) When CKP1n = 0, DAP1n = 0 (or CKP1n = 1, DAP1n = 0) SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch First bit SO1n 2nd bit The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising) edge of SCK1n, and the data is output from the SO1n pin. (2) When CKP1n = 0, DAP1n = 1 (or CKP1n = 1, DAP1n = 1) SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch First bit SO1n 2nd bit 3rd bit The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling) edge of SCK1n, and the data is output from the SO1n pin. Remark 366 PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1) Type 1; when CKP1n = 0 and DAP1n = 0 (or CKP1n = 1, DAP1n = 0) SCK1n ( Next request is issued.) Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch Last bit SO1n (2) Type 2; when CKP1n = 0 and DAP1n = 1 (or CKP1n = 1, DAP1n = 1) SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Remark n = 0: Last bit PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ3V1UD 367 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 16-3. SO1n Output Status TRMD1n TRMD1n = 0 DAP1n DIR1n - - Outputs low level DAP1n = 0 - Value of SO1n latch Note TRMD1n = 1 SO1n Output Note . (low-level output) DAP1n = 1 DIR1n = 0 Value of bit 7 of SOTB1n DIR1n = 1 Value of bit 0 of SOTB1n Note Status after reset Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 368 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 17.1 Functions of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 17.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCKA0) and two serial data lines (SIA0 and SOA0). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. For details, see 17.4.2 3-wire serial I/O mode. (3) 3-wire serial I/O mode with automatic transmit/receive function (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCKA0) and two serial data lines (SIA0 and SOA0). The processing time of data communication can be shortened in the 3-wire serial I/O mode with automatic transmit/receive function because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. Data can be communicated to/from a display driver etc. without using software since a 32-byte transfer buffer RAM is incorporated. Also, the incorporation of handshake pins (STB0, BUSY0) has made connection to peripheral LSIs easy. For details, see 17.4.3 3-wire serial I/O mode with automatic transmit/receive function. * Master mode/slave mode selectable * Communication data length: 8 bits * MSB/LSB-first selectable for communication data * Automatic transmit/receive function: Number of transfer bytes can be specified between 1 and 32 Transfer interval can be specified (0 to 63 clocks) Single communication/repeat communication selectable * On-chip dedicated baud rate generator (6/8/16/32 divisions) * 3-wire SOA0: Serial data output SIA0: Serial data input SCKA0: Serial clock I/O * Handshake function incorporated STB0: Strobe output BUSY0: Busy input * Transmission/reception completion interrupt: INTACSI * Internal 32-byte buffer RAM User's Manual U15947EJ3V1UD 369 CHAPTER 17 SERIAL INTERFACE CSIA0 17.2 Configuration of Serial Interface CSIA0 Serial interface CSIA0 includes the following hardware. Table 17-1. Configuration of Serial Interface CSIA0 Item Registers Configuration Serial I/O shift register 0 (SIOA0) Automatic data transfer address count register 0 (ADTC0) Control registers Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0) Serial trigger register 0 (CSIT0) Divisor selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Port mode register 14 (PM14) Port register 14 (P14) 370 User's Manual U15947EJ3V1UD Figure 17-1. Block Diagram of Serial Interface CSIA0 Automatic data transfer address point specification register 0 (ADTP0) Buffer RAM Automatic data transfer address count register 0 (ADTC0) Internal bus ATE0 Serial trigger register 0 (CSIT0) DIR0 RXAE User's Manual U15947EJ3V1UD SOA0/P144 TXAE Divisor selection register 0 (BRGCA0) ATSTP0 ATSTA0 Serial status register 0 (CSIS0) P144 STBE0 BUSYE0 BUSYLV0 ERRE0 ERRF0 TSF0 PM144 2 STB0/P145 PM145 Serial clock counter P145 Interrupt generator INTACSI 4 Serial transfer controller BUSY0/P141 SCKA0/P142 PM142 P142 Selector fW/6 to fW/32 Automatic data transfer interval specification register 0 (ADTI0) 6-bit counter MASTER0 Baud rate generator fX 3 CHAPTER 17 SERIAL INTERFACE CSIA0 ATM0 Serial I/O shift register 0 (SIOA0) SIA0/P143 371 CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial I/O shift register 0 (SIOA0) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 0). Writing transmit data to SIOA0 starts the communication. In addition, after a communication completion interrupt request (INTACSI) is output (bit 0 (TSF0) of serial status register 0 (CSIS0) = 0), data can be received by reading data from SIOA0. This register can be written or read by an 8-bit memory manipulation instruction. However, writing to SIOA0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. RESET input clears this register to 00H. Cautions 1. A communication operation is started by writing to SIOA0. Consequently, when transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the SIOA0 register to start the communication operation, and then perform a receive operation. 2. Do not write data to SIOA0 while the automatic transmit/receive function is operating. (2) Automatic data transfer address count register 0 (ADTC0) This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading ADTC0 register value. This register can be read by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. However, reading from ADTC0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. Figure 17-2. Format of Automatic Data Transfer Address Count Register 0 (ADTC0) Address: FF97H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ADTC0 0 0 0 ADTC04 ADTC03 ADTC02 ADTC01 ADTP00 17.3 Registers Controlling Serial Interface CSIA0 Serial interface CSIA0 is controlled by the following eight registers. * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Port mode register 14 (PM14) * Port register 14 (P14) 372 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 17-3. Format of Serial Operation Mode Specification Register 0 (CSIMA0) Address: FF90H After reset: 00H Symbol < > CSIMA0 CSIAE0 ATE0 CSIAE0 R/W ATM0 MASTER0 < > < > TXEA0 RXEA0 DIR0 0 Control of CSIA0 operation enable/disable 0 CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuitNote. 1 CSIA0 operation enabled ATE0 Control of automatic communication operation enable/disable 0 1-byte communication mode 1 Automatic communication mode ATM0 Automatic communication mode specification 0 Single transfer mode (stops at the address specified by the ADTP0 register) 1 Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer) MASTER0 CSIA0 master/slave mode specification 0 Slave mode (synchronous with SCKA0 input clock) 1 Master mode (synchronous with internal clock) Control of transmit operation enable/disable TXEA0 0 Transmit operation disabled (SOA0: Low level) 1 Transmit operation enabled Control of receive operation enable/disable RXEA0 0 Receive operation disabled 1 Receive operation enabled First bit specification DIR0 0 MSB 1 LSB Note Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial I/O shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset. Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed. 2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized registers. 3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. User's Manual U15947EJ3V1UD 373 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Serial status register 0 (CSIS0) This is an 8-bit register used to select the base clock, control the communication operation, and indicate the status of serial interface CSIA0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. However, rewriting CSIS0 is prohibited when bit 0 (TSF0) is 1. Figure 17-4. Format of Serial Status Register 0 (CSIS0) (1/2) Address: FF91H After reset: 00H R/WNote 1 Symbol 7 6 5 4 3 2 1 0 CSIS0 0 CKS00 STBE0 BUSYE0 BUSYLV0 ERRE0 ERRF0 TSF0 Base clock (fW) selectionNote 2 CKS00 0 fX (10 MHz) 1 fX/2 (5 MHz) STBE0Notes 3, 4 Strobe output enable/disable 0 Strobe output disabled 1 Strobe output enabled BUSYE0 Busy signal detection enable/disable 0 Busy signal detection disabled (input via BUSY0 pin is ignored) 1 Busy signal detection enabled and communication wait by busy signal is executed BUSYLV0Note 5 Notes 1. 2. Busy signal active level setting 0 Low level 1 High level Bits 0 and 1 are read-only. Set the base clock to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Base clock 10 MHz * VDD = 3.3 to 4.0 V: Base clock 8.38 MHz * VDD = 2.7 to 3.3 V: Base clock 5 MHz * VDD = 2.5 to 2.7 V: Base clock 2.5 MHz 3. 4. STBE0 is valid only in master mode. When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks are used for 1-byte transfer if ADTI0 = 00H is set. 5. Caution In bit error detection by busy input, the active level specified by BUSYLV0 is detected. Be sure to clear bit 7 to 0. Remarks 1. Figures in parentheses apply to operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency 374 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-4. Format of Serial Status Register 0 (CSIS0) (2/2) ERRE0Note Bit error detection enable/disable 0 Error detection disabled 1 Error detection enabled ERRF0 Bit error detection flag 0 * Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 * At reset input * When communication is started by setting bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1 or writing to SIOA0. 1 Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer period is detected via BUSY0 pin input). TSF0 Transfer status detection flag 0 * * * * 1 From the transfer start to the end of the specified transfer Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 At reset input At the end of the specified transfer When transfer is stopped by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1 Note The ERRE0 setting is valid even when BUSYE0 = 0. Caution When TSF0 is 1, rewriting serial operation mode specification register 0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer. User's Manual U15947EJ3V1UD 375 CHAPTER 17 SERIAL INTERFACE CSIA0 (3) Serial trigger register 0 (CSIT0) This is an 8-bit register used to control execution/stop of automatic data transfer between buffer RAM and serial I/O shift register 0 (SIOA0). This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. However, manipulate only when bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is 1 (manipulation prohibited when ATE0 = 0). Figure 17-5. Format of Serial Trigger Register 0 (CSIT0) Address: FF92H After reset: 00H R/W Symbol 7 6 5 4 3 2 <1> <0> CSIT0 0 0 0 0 0 0 ATSTP0 ATSTA0 ATSTP0 Automatic data transfer stop 0 - 1 Automatic data transfer stopped ATSTA0 Automatic data transfer start 0 - 1 Automatic data transfer started Cautions 1. Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1byte transfer is complete. 2. ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is generated. 3. After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by ATSTA0 after re-setting the registers. 376 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 (4) Divisor selection register 0 (BRGCA0) This is an 8-bit register used to select the base clock divisor of CSIA0. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting BRGCA0 is prohibited. Figure 17-6. Format of Divisor Selection Register 0 (BRGCA0) Address: FF93H After reset: 03H R/W Symbol 7 6 5 4 3 2 1 0 BRGCA0 0 0 0 0 0 0 BRGCA01 BRGCA00 BRGCA01 BRGCA00 0 0 fW/6 (1.67 MHz) 0 1 fW/23 (1.25 MHz) 1 0 fW/24 (625 kHz) 1 1 fW/25 (312.5 kHz) CSIA0 base clock (fW) divisor selection Remarks 1. Figures in parentheses apply to operation with fW = 10 MHz. 2. fW: Base clock frequency selected by CKS00 bit of CSIS0 register (5) Automatic data transfer address point specification register 0 (ADTP0) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1). This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTP0 is prohibited. In the 78K0/KF1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When ADTP0 is set to 07H 8 bytes of FA00H to FA07H are transferred. In repeat transfer mode (bit 5 (ATM0) of CSIMA0 = 1), transfer is performed repeatedly up to the address specified with ADTP0. Example When ADTP0 is set to 07H (repeat transfer mode) Transfer is repeated as FA00H to FA07H, FA00H to FA07H, ... . Figure 17-7. Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0) Address: FF94H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTP0 0 0 0 ADTP04 ADTP03 ADTP02 ADTP01 ADTP00 Caution Be sure to clear bits 7 to 5 to 0. User's Manual U15947EJ3V1UD 377 CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between buffer RAM address values and ADTP0 setting values is shown below. Table 17-2. Relationship Between Buffer RAM Address Values and ADTP0 Setting Values 378 Buffer RAM Address Value ADTP0 Setting Value Buffer RAM Address Value ADTP0 Setting Value FA00H 00H FA10H 10H FA01H 01H FA11H 11H FA02H 02H FA12H 12H FA03H 03H FA13H 13H FA04H 04H FA14H 14H FA05H 05H FA15H 15H FA06H 06H FA16H 16H FA07H 07H FA17H 17H FA08H 08H FA18H 18H FA09H 09H FA19H 19H FA0AH 0AH FA1AH 1AH FA0BH 0BH FA1BH 1BH FA0CH 0CH FA1CH 1CH FA0DH 0DH FA1DH 1DH FA0EH 0EH FA1EH 1EH FA0FH 0FH FA1FH 1FH User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 (6) Automatic data transfer interval specification register 0 (ADTI0) This is an 8-bit register used to specify the interval time between 1-byte communications during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1). Set this register when in master mode (bit 4 (MASTER0) of CSIMA0 = 1) (setting is unnecessary in slave mode). Setting in 1-byte communication mode (bit 6 (ATE0) of CSIMA0 = 0) is also valid. When the interval time specified by ADTI0 after the end of 1-byte communication has elapsed, an interrupt request signal (INTACSI) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTI0 is prohibited. Figure 17-8. Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0) Address: FF95H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTI0 0 0 ADTI05 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Caution Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. Example Interval time when busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Therefore, clearing STBE0 and BUSYE0 to 0 is required to perform no-wait transfer. The specified interval time is the serial clock (specified by divisor selection register 0 (BRGCA0)) multiplied by an integer value. Example When ADTI0 = 03H SCKA0 Interval time of 3 clocks User's Manual U15947EJ3V1UD 379 CHAPTER 17 SERIAL INTERFACE CSIA0 (7) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using P142/SCKA0, P144/SOA0, and P145/STB0 pins as the clock output, data output, or strobe output of the serial interface, clear PM142, PM144, PM145, and the output latches of P142, P144, and P145 to 0. When using P141/BUSY0, P142/SCKA0, and P143/SIA0 pins as the busy input, clock input, or data input of the serial interface, set PM141, PM142, and PM143 to 1. At this time, the output latches of P141, P142, and P143 may be 0 or 1. PM14 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 17-9. Format of Port Mode Register 14 (PM14) Address: FF2EH R/W Symbol 7 6 5 4 3 2 1 0 PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 PM14n 380 After reset: FFH P14n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 17.4 Operation of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P142/SCKA0, P143/SIA0, and P144/SOA0 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode specification register 0 (CSIMA0). To set the operation stop mode, clear bit 7 (CSIAE0) of CSIMA0 to 0. (a) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Address: FF90H After reset: 00H R/W < > CSIMA0 CSIAE0 CSIAE0 0 ATE0 ATM0 MASTER0 < > < > TXEA0 RXEA0 DIR0 0 Control of CSIA0 operation enable/disable CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuit User's Manual U15947EJ3V1UD 381 CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.2 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is cleared to 0. The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: serial clock (SCKA0), serial output (SOA0), and serial input (SIA0) lines. (1) Registers used * Serial operation mode specification register 0 (CSIMA0)Note 1 * Serial status register 0 (CSIS0)Note 2 * Divisor selection register 0 (BRGCA0) * Port mode register 14 (PM14) * Port register 14 (P14) Notes 1. Bits 7, 6, and 4 to 1 (CSIAE0, ATE0, MASTER0, TXEA0, RXEA0, and DIR0) are used. Setting of bit 5 (ATM0) is invalid. 2. Only bit 0 (TSF0) is used. The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the BRGCA0 register (see Figure 17-6)Note 1. <2> Set bits 4 to 1 (MASTER0, TXEA0, RXEA0, and DIR0) of the CSIMA0 register (see Figure 17-3). <3> Set bit 7 (CSIAE0) of the CSIMA0 register to 1 and clear bit 6 (ATE0) to 0. <4> Write data to serial I/O shift register 0 (SIOA0). Data transmission/reception is startedNote 2. Notes 1. This register does not have to be set when the slave mode is specified (MASTER0 = 0). 2. Write dummy data to SIOA0 only for reception. Caution Take relationship with the other party of communication when setting the port mode register and port register. 382 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between the register settings and pins is shown below. Table 17-3. Relationship Between Register Settings and Pins CSIAE0 ATE0 0 x MASTER0 PM143 xNote 1 x P143 xNote 1 PM144 xNote 1 P144 PM142 xNote 1 xNote 1 P142 xNote 1 Serial I/O Serial Clock Shift Counter SIA0/ SOA0/ SCKA0/ Register 0 Operation P143 P144 P142 Operation Control Operation Pin Function Clear P143 P144 P142 Operation Count SIA0Note 2 SOA0Note 3 SCKA0 enabled operation stopped 1 0 1Note 2 0 xNote 2 0Note 3 0Note 3 1 0 1 x 1 (input) SCKA0 (output) Notes 1. Can be set as port function. 2. Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. 3. Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0. Remark x: don't care CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ATE0: Bit 6 of CSIMA0 MASTER0: PM14x: Bit 4 of CSIMA0 Port mode register P14x: Port output latch User's Manual U15947EJ3V1UD 383 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1, 0, respectively, if communication data is written to serial I/O shift register 0 (SIOA0), the data is output via the SOA0 pin in synchronization with the SCKA0 falling edge, and then input via the SIA0 pin in synchronization with SCKA0 falling edge, and stored in the SIOA0 register in synchronization with the rising edge 1 clock later. Data transmission and data reception can be performed simultaneously. If only reception is to be performed, communication can only be started by writing a dummy value to the SIOA0 register. When communication of 1 byte is complete, an interrupt request signal (INTACSI) is generated. In 1-byte transmission/reception, the setting of bit 5 (ATM0) of CSIMA0 is invalid. Be sure to read data after confirming that bit 0 (TSF0) of serial status register 0 (CSIS0) = 0. Figure 17-10. 3-Wire Serial I/O Mode Timing SCKA0 1 2 3 4 5 6 7 8 SIA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SOA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI0 DO0 TSF0 ACSIIF Transfer starts at falling edge of SCKA0 SIOA0 write Caution 384 The SOA0 pin becomes low level by an SIOA0 write. User's Manual U15947EJ3V1UD End of transfer CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data communication direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-11. Format of Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SOA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 SOA0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 User's Manual U15947EJ3V1UD 385 CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Switching MSB/LSB as start bit Figure 17-12 shows the configuration of serial I/O shift register 0 (SIOA0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. Switching MSB/LSB as the start bit can be specified using bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-12. Transfer Bit Order Switching Circuit 7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate SOA0 latch SIA0 Shift register 0 (SIOA0) D Q SOA0 SCKA0 Start bit switching is realized by switching the bit order for data written to SIOA0. The SIOA0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (d) Communication start Serial communication is started by setting communication data to serial I/O shift register 0 (SIOA0) when the following two conditions are satisfied. * Serial interface CSIA0 operation control bit (CSIAE0) = 1 * Serial communication is not in progress Caution If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. Upon termination of 8-bit communication, serial communication automatically stops and the interrupt request flag (ACSIIF) is set. 386 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM. In addition, to transmit/receive data continuously, handshake signals (STB0 and BUSY0) generated by hardware are supported. Therefore, connection to peripheral LSIs such as OSD (On Screen Display) LSIs and LCD controller/drivers can be easily realized. (1) Registers used * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Port mode register 14 (PM14) * Port register 14 (P14) The relationship between the register settings and pins is shown below. User's Manual U15947EJ3V1UD 387 388 Table 17-4. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 STBE0 BUSYE0 ERRE0 PM143 P143 PM144 P144 PM142 P142 PM145 P145 PM141 P141 0 1 x x 1 0 x x Note 1 1 Notes 1. User's Manual U15947EJ3V1UD Remark Pin Function Serial Clock Counter SIA0/ SOA10/ SCKA0/ STB0/ BUSY0/ Operation Control P143 P144 P142 P145 P141 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 Operation stopped Clear x Note 1 0/1 0 0 0/1 1 1 0/1 1 x 0 0 1 x x 0 1 xNote 1 xNote 1 xNote 1 xNote 1 Note 1 0 x Note 1 0 x Note 1 1 x Note 1 Operation enabled Count operation x P143 Note 2 SIA0 P144 P142 P145 P141 SOA10 SCKA0 P145 (input) P141 SCKA0 P145 P141 (output) STB0 BUSY0 Can be set as port function. Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. x: don't care CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ATE0: Bit 6 of CSIMA0 MASTER0: Bit 4 of CSIMA0 STBE0: Bit 5 of serial status register 0 (CSIS0) BUSYE0: Bit 4 of CSIS0 ERRE0: PM14x: Bit 2 of CSIS0 Port mode register P14x: Port output latch CHAPTER 17 SERIAL INTERFACE CSIA0 2. Serial I/O Shift Register 0 Operation CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FA00H of buffer RAM (up to FA1FH at maximum). The transmit data should be in the order from lower address to higher address. <2> Set the automatic data transfer address point specification register 0 (ADTP0) to the value obtained by subtracting 1 from the number of transmit data bytes. (b) Setting example of automatic transmission/reception mode <1> Set bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) to 1. <2> Set bit 2 (RXEA0) and bit 3 (TXEA0) of CSIMA0 to 1. <3> Set a data transfer interval in automatic data transfer interval specification register 0 (ADTI0). <4> Set bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1. Caution Take relationship with the other party of communication when setting the port mode register and port register. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data indicated by automatic data transfer address count register 0 (ADTC0) is transferred to SIOA0, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address indicated by ADTC0. * ADTC0 is incremented and the next data transmission/reception is carried out. Data transmission/reception continues until the ADTC0 incremental output matches the set value of automatic data transfer address point specification register 0 (ADTP0) (end of automatic transmission/reception). However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is cleared after a match between ADTP0 and ADTC0, and then repeated transmission/reception is started. * When automatic transmission/reception is terminated, TSF0 is cleared to 0. (3) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOA0 pin via the SIOA0 register in synchronization with the SCKA0 falling edge by performing (a) and (b) in (2) Automatic transmit/receive data setting. The data is then input from the SIA0 pin via the SIOA0 register in synchronization with the SCKA0 falling edge and the receive data is stored in the buffer RAM in synchronization with the rising edge 1 clock later. Data transfer ends if bit 0 (TSF0) of serial status register 0 (CSIS0) is set to 1 when any of the following conditions is met. * Reset by clearing bit 7 (CSIAE0) of the CSIMA0 register to 0 * Transfer of 1 byte is complete by setting bit 1 (ATSTP0) of the CSIT0 register to 1 * Transfer of 1 byte is complete when bit 1 (ERRF0) of the CSIS0 register becomes 1 while bit 2 (ERRE0) = 1 * Transfer of the range specified by the ADTP0 register is complete User's Manual U15947EJ3V1UD 389 CHAPTER 17 SERIAL INTERFACE CSIA0 At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already been transferred and re-execute transfer by performing (a) and (b) in (2) Automatic transmit/receive data setting. In addition, when busy control and strobe control are not performed, the BUSY0/BUZ/INTP7/P141 and STB0/P145 pins can be used as ordinary I/O port pins. Figure 17-13 shows the operation timing in automatic transmission/reception mode and Figure 17-14 shows the operation flowchart. Figure 17-15 shows the operation of internal buffer RAM when 6 bytes of data are transmitted/received. Figure 17-13. Automatic Transmission/Reception Mode Operation Timings Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF TSF0 Cautions 1. Because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer RAM after 1byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: 390 Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-14. Automatic Transmission/Reception Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the automatic transmission/reception mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Transmission/reception operation Increment pointer value Hardware execution Write receive data from SIOA0 to internal buffer RAM ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End ADTP0: Automatic data transfer address point specification register 0 ADTI0: Automatic data transfer interval specification register 0 ATSTA0: Bit 0 of serial trigger register 0 (CSIT0) SIOA0: Serial I/O shift register 0 ADTC0: Automatic data transfer address count register 0 TSF0: Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ3V1UD 391 CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission/reception (ATM0 = 0, RXEA0 = 1, TXEA0 = 1) in automatic transmission/reception mode, internal buffer RAM operates as follows. (i) Starting transmission/reception (see Figure 17-15 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, receive data 1 (R1) is transferred from SIOA0 to the buffer RAM, and automatic data transfer address count register 0 (ADTC0) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOA0. (ii) 4th byte transmission/reception point (see Figure 17-15 (b).) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to SIOA0. When transmission of the fourth byte is completed, the receive data 4 (R4) is transferred from SIOA0 to the internal buffer RAM, and ADTC0 is incremented. (iii) Completion of transmission/reception (see Figure 17-15 (c).) When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIOA0 to the internal buffer RAM, and the interrupt request flag (ACSIIF) is set (INTACSI generation). Bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared. Figure 17-15. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (1/2) (a) Starting transmission/reception FA1FH FA05H Transmit data 6 (T6) Receive data 1 (R1) SIOA0 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) +1 Transmit data 2 (T2) FA00H 392 Transmit data 1 (T1) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-15. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception FA1FH FA05H Transmit data 6 (T6) Receive data 4 (R4) SIOA0 5 ADTP0 3 ADTC0 0 ACSIIF Transmit data 5 (T5) Transmit data 4 (T4) Receive data 3 (R3) +1 Receive data 2 (R2) FA00H Receive data 1 (R1) (c) Completion of transmission/reception FA1FH FA05H Receive data 6 (R6) SIOA0 Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) 5 ADTP0 5 ADTC0 1 ACSIIF Receive data 2 (R2) FA00H Receive data 1 (R1) User's Manual U15947EJ3V1UD 393 CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Automatic transmission mode In this mode, the specified number of 8-bit unit data is transmitted. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. When the final byte has been transmitted, an interrupt request flag (ACSIIF) is set. The termination of automatic transmission and reception can also be judged by bit 0 (TSF0) of serial status register 0 (CSIS0). If a receive operation, busy control and strobe control are not executed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as normal I/O port pins. Figure 17-16 shows the automatic transmission mode operation timing, and Figure 17-17 shows the operation flowchart. Figure 17-18 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted. Figure 17-16. Automatic Transmission Mode Operation Timing Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF TSF0 Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: 394 Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-17. Automatic Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the automatic transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment pointer value Transmission operation Hardware execution ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End ADTP0: Automatic data transfer address point specification register 0 ADTI0: Automatic data transfer interval specification register 0 ATSTA0: Bit 0 of serial trigger register 0 (CSIT0) SIOA0: Serial I/O shift register 0 ADTC0: Automatic data transfer address count register 0 TSF0: Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ3V1UD 395 CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission (ATM0 = 0, RXEA0 = 0, TXEA0 = 1, ATE0 = 1) in automatic transmission mode, internal buffer RAM operates as follows. (i) Starting transmission (see Figure 17-18 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, automatic data transfer address count register 0 (ADTC0) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOA0. (ii) 4th byte transmission point (see Figure 17-18 (b).) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to SIOA0. When transmission of the fourth byte is completed, ADTC0 is incremented. (iii) Completion of transmission (see Figure 17-18 (c).) When transmission of the sixth byte is completed, the interrupt request flag (ACSIIF) is set (INTACSI generation). Bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared. Figure 17-18. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (1/2) (a) Starting transmission FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) +1 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H 396 Transmit data 1 (T1) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-18. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (2/2) (b) 4th byte transmission point FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) +1 5 ADTP0 3 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H Transmit data 1 (T1) (c) Completion of transmission FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) 5 ADTP0 5 ADTC0 1 ACSIIF Transmit data 2 (T2) FA00H Transmit data 1 (T1) User's Manual U15947EJ3V1UD 397 CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. Unlike the basic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (ACSIIF) is not set, automatic data transfer address count register 0 (ADTC0) is reset to 0, and the internal buffer RAM contents are transmitted again. When a reception operation, busy control and strobe control are not performed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as ordinary I/O port pins. The repeat transmission mode operation timing is shown in Figure 17-19, and the operation flowchart in Figure 17-20. Figure 17-21 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode. Figure 17-19. Repeat Transmission Mode Operation Timing Interval Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. 398 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-20. Repeat Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the repeat transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment pointer value Transmission operation Hardware execution No ADTP0 = ADTC0 Yes Reset ADTC0 to 0 ADTP0: Automatic data transfer address point specification register 0 ADTI0: Automatic data transfer interval specification register 0 ATSTA0: Bit 0 of serial trigger register 0 (CSIT0) SIOA0: Serial I/O shift register 0 ADTC0: Automatic data transfer address count register 0 User's Manual U15947EJ3V1UD 399 CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission (ATM0 = 1, RXEA0 = 0, TXEA0 = 1, ATE0 = 1) in repeat transmission mode, internal buffer RAM operates as follows. (i) Starting transmission (see Figure 17-21 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, automatic data transfer address count register 0 (ADTC0) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOA0. (ii) Upon completion of transmission of 6 bytes (see Figure 17-21 (b).) When transmission of the sixth byte is completed, the interrupt request flag (ACSIIF) is not set. ADTC0 is reset to 0. (iii) 7th byte transmission point (see Figure 17-21 (c).) Transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0 again. When transmission of the first byte is completed, ADTC0 is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOA0. Figure 17-21. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (1/2) (a) Starting transmission FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) +1 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H 400 Transmit data 1 (T1) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-21. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) 5 ADTP0 5 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H Transmit data 1 (T1) (c) 7th byte transmission point FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) +1 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H Transmit data 1 (T1) User's Manual U15947EJ3V1UD 401 CHAPTER 17 SERIAL INTERFACE CSIA0 (d) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-22. Format of CSIA0 Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SOA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 402 SIA0 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 SOA0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1. During 8-bit data communication, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data communication. When suspended, bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared to 0 after transfer of the 8th bit. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TSF0 = 1. Figure 17-23. Automatic Transmission/Reception Suspension and Restart Suspend ATSTP0 = 1 (Suspend command) Restart command ATSTA0 = 1 SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ATSTP0: Bit 1 of serial trigger register 0 (CSIT0) ATSTA0: Bit 0 of CSIT0 User's Manual U15947EJ3V1UD 403 CHAPTER 17 SERIAL INTERFACE CSIA0 (4) Synchronization control Busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. When using this busy control option, the following conditions must be satisfied. * Bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1. Figure 17-24 shows the system configuration of the master device and slave device when the busy control option is used. Figure 17-24. System Configuration When Busy Control Option Is Used Master device (78K0/KF1) SCKA0 SOA0 SIA0 BUSY0 Slave device SCKA SIA SOA Busy output The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin. The master device samples the input busy signal in synchronization with the falling of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is active. The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0. BUSYLV0 = 1: Active-high BUSYLV0 = 0: Active-low When using the busy control option, select the internal clock as the serial clock. Control with the busy signal cannot be implemented with the external clock. Figure 17-25 shows the operation timing when the busy control option is used. Caution Busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (ADTI0). 404 User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-25. Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 Wait ACSIIF Busy input released Busy input valid TSF0 Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock. Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the busy signal was sampled. To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clock. Figure 17-26 shows the timing of the busy signal and releasing the waiting. This figure shows an example in which the busy signal is active as soon as transmission/reception has been started. Figure 17-26. Busy Signal and Wait Release (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 (active-high) 1.5 clocks (min.) If made inactive immediately after sampled Wait Busy input released Busy input valid User's Manual U15947EJ3V1UD 405 CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Busy & strobe control option Strobe control is a function used to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB0/P145 pin when 8-bit transmission/reception has been completed. By this signal, the slave device can determine the timing of the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. To use the strobe control option, the following conditions must be satisfied: * Bit 6 (ATE0) of the serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 5 (STBE0) of serial status register 0 (CSIS0) is set to 1. Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB0/P145 pin, the BUSY0/BUZ/INTP7/P141 pin can be sampled to keep transmission/reception waiting while the busy signal is input. A high level lasting for one transfer clock is output from the STB0/P145 pin in synchronization with the falling edge of the ninth serial clock as the strobe signal. The busy signal is detected at the rising edge of the serial clock two clocks after 8-bit data transmission/reception completion. When the strobe control option is not used, the P145/STB0 pin can be used as a normal I/O port pin. Figure 17-27 shows the operation timing when the busy & strobe control options are used. When the strobe control option is used, the interrupt request flag (ACSIIF) that is set on completion of transmission/reception is set after the strobe signal is output. Figure 17-27. Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB0 BUSY0 ACSIIF Busy input released Busy input valid TSF0 Caution When TSF0 is cleared, the SOA0 pin goes low. Remark ACSIIF: Interrupt request flag TSF0: 406 Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ3V1UD CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. A bit shift is detected by using the busy signal as follows: The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). The master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2 (ERRE0) of serial status register 0 (CSIS0) is set to 1. If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has occurred, error processing is executed (by setting bit 1 (ERRF0) of serial status register 0 (CSIS0) to 1, and communication is suspended and an interrupt request signal (INTACSI) is output). Although communication is suspended after completion of 1-byte data communication, slave signal output, wait due to the busy signal, and wait due to the interval time specified by ADTI0 are not executed. If ERRE0 = 0, ERRF0 cannot become 1 even if a bit shift occurs. Figure 17-28 shows the operation timing of the bit shift detection function by the busy signal. Remark The bit error function is valid both in the master mode and slave mode. The setting of ERRE0 is valid even when BUSYE0 = 0. Figure 17-28. Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 0) SCKA0 (Master) Bit shift due to noise SCKA0 (Slave) SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 ACSIIF CSIAE0 ERRF0 Busy not detected Error interrupt request generated Error detected ACSIIF: Interrupt request flag CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ERRF0: Bit 1 of serial status register 0 (CSIS0) User's Manual U15947EJ3V1UD 407 CHAPTER 17 SERIAL INTERFACE CSIA0 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in automatic data transfer interval specification register 0 (ADTI0) and bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0). When ADTI0 is cleared to 00H, an interval time based on the STBE0 and BUSYE0 settings is generated. For example, when ADTI0 = 00H and STBE0 = BUSYE0 = 1, an interval time of two clocks is generated. If an interval time of two clocks or more is set by ADTI0, the interval time set by ADTI0 is generated regardless of the STBE0 and BUSYE0 settings. Example Interval time when busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Figure 17-29. Automatic Transmit/Receive Interval Time Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF ACSIIF: 408 Interrupt request flag User's Manual U15947EJ3V1UD CHAPTER 18 MULTIPLIER/DIVIDER 18.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits, 16-bit remainder (division) 18.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware. Table 18-1. Configuration of Multiplier/Divider Item Registers Configuration Remainder data register 0 (SDR0) Multiplication/division data register A0 (MDA0H, MDA0L) Multiplication/division data register B0 (MDB0) Control register Multiplier/divider control register 0 (DMUC0) Figure 18-1 shows the block diagram of the multiplier/divider. User's Manual U15947EJ3V1UD 409 410 Figure 18-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 (MDB0 (MDB0H+MDB0L) Multiplication/division data register A0 Remainder data register 0 (SDR0 (SDR0H+SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL)) DMUSEL0 DMUE Start MDA000 INTDMU Clear Controller User's Manual U15947EJ3V1UD 17-bit adder Controller CPU clock CHAPTER 18 MULTIPLIER/DIVIDER Controller 6-bit counter CHAPTER 18 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. This register can be read by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 18-2. Format of Remainder Data Register 0 (SDR0) Address: FF60H, FF61H After reset: 0000H Symbol SDR0 R FF61H (SDR0H) FF60H (SDR0L) SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. 2. SDR0 is reset when the operation is started (when DMUE is set to 1). User's Manual U15947EJ3V1UD 411 CHAPTER 18 MULTIPLIER/DIVIDER (2) Multiplication/division data register A0 (MDA0H, MDA0L) MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L). Figure 18-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) Address: FF62H, FF63H, FF64H, FF65H Symbol MDA0H R/W FF65H (MDA0HH) FF64H (MDA0HL) MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 031 030 Symbol MDA0L After reset: 0000H, 0000H 029 028 027 026 025 024 023 022 FF63H (MDA0LH) 021 020 019 018 017 016 FF62H (MDA0LL) MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). 2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. 3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed. 412 User's Manual U15947EJ3V1UD CHAPTER 18 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 18-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result 0 Division mode Dividend Division result (quotient) 1 Multiplication mode Higher 16 bits: 0, Lower 16 bits: Multiplier A Multiplication result (product) The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDA0 (bits 15 to 0) x MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) * Register configuration during division <Dividend> <Divisor> <Quotient> <Remainder> MDA0 (bits 31 to 0) / MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) ... SDR0 (bits 15 to 0) MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is set to 1. MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H. (3) Multiplication/division data register B0 (MDB0) MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the division mode. This register can be set by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 18-4. Format of Multiplication/Division Data Register B0 (MDB0) Address: FF66H, FF67H After reset: 0000H Symbol MDB0 R/W FF67H (MDB0H) FF66H (MDB0L) MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. 2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. User's Manual U15947EJ3V1UD 413 CHAPTER 18 MULTIPLIER/DIVIDER 18.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 18-5. Format of Multiplier/Divider Control Register 0 (DMUC0) Address: FF68H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 DMUC0 DMUE 0 0 0 0 0 0 DMUSEL0 DMUENote Operation start/stop 0 Stops operation 1 Starts operation DMUSEL0 Operation mode (multiplication/division) selection 0 Division mode 1 Multiplication mode Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is complete. Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). 3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). 414 User's Manual U15947EJ3V1UD CHAPTER 18 MULTIPLIER/DIVIDER 18.4 Operations of Multiplier/Divider 18.4.1 Multiplication operation * Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. * During operation 3. The operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The operation result data is stored in the MDA0L and MDA0H registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 18.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 18.4.2 Division operation. User's Manual U15947EJ3V1UD 415 416 Figure 18-6. Timing Chart of Multiplication Operation (00DAH x 0093H) Operation clock DMUE DMUSEL0 Internal clock User's Manual U15947EJ3V1UD XXXX SDR0 MDA0 XXXX XXXX MDB0 XXXX INTDMU XXXX 00DA 0093 1 2 3 4 5 6 7 8 9 A B C D E F 10 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00DA 0000 0049 0024 005B 0077 003B 0067 007D 003E 001F 000F 0007 0003 0001 0000 0000 006D 8036 C01B E00D 7006 B803 5C01 2E00 9700 4B80 A5C0 D2E0 E970 F4B8 FA5C 7D2E 0 CHAPTER 18 MULTIPLIER/DIVIDER 0 Counter CHAPTER 18 MULTIPLIER/DIVIDER 18.4.2 Division operation * Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start. * During operation 3. The operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 (SDR0) during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The result data is stored in the MDA0L, MDA0H, and SDR0 registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 18.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 18.4.2 Division operation. User's Manual U15947EJ3V1UD 417 418 Figure 18-7. Timing Chart of Division Operation (DCBA2586H / 0018H) Operation clock DMUE DMUSEL0 "0" Internal clock 0 Counter 0000 User's Manual U15947EJ3V1UD MDA0 XXXX XXXX DCBA 2586 MDB0 XXXX 0018 INTDMU 2 3 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 B974 72E8 E5D1 CBA2 A744 2E89 6D12 BA25 4B0C A618 2C30 6860 BAC1 6182 C304 8609 0C12 1824 3049 6093 C126 824C 0499 0932 64D8 C9B0 9361 26C3 4D87 9B0E 361D 6C3A 0 CHAPTER 18 MULTIPLIER/DIVIDER XXXX SDR0 1 CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to its predetermined priority (see Table 19-1). A standby release signal is generated and STOP and HALT modes are released. Nine external interrupt requests and 20 (17 in the PD780143 and 780144) internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 19.2 Interrupt Sources and Configuration A total of 30 (27 in the PD780143 and 780144) interrupt sources exist for maskable and software interrupts (see Table 19-1). User's Manual U15947EJ3V1UD 419 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Note 1 Type Priority Name Trigger Internal/ Vector Basic External Table Configuration Address Maskable Note 3 Type Note 2 0 INTLVI Low-voltage detection Internal 0004H (A) 1 INTP0 Pin input edge detection External 0006H (B) 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTP4 000EH 6 INTP5 0010H 7 INTSRE6 UART6 reception error generation 8 INTSR6 End of UART6 reception 0014H 9 INTST6 End of UART6 transmission 0016H 10 INTCSI10/ End of CSI10 communication/end of UART0 0018H INTST0 transmission INTTMH1 Match between TMH1 and CMP01 11 Internal 0012H (A) 001AH (when compare register is specified) 12 INTTMH0 Match between TMH0 and CMP00 001CH (when compare register is specified) 13 INTTM50 Match between TM50 and CR50 001EH (when compare register is specified) 14 INTTM000 Match between TM00 and CR000 0020H (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) 15 INTTM010 Match between TM00 and CR010 0022H (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) 16 INTAD End of A/D conversion 0024H 17 INTSR0 End of UART0 reception or reception error 0026H generation 18 INTWTI Watch timer reference time interval signal 0028H 19 INTTM51 Match between TM51 and CR51 002AH (when compare register is specified) Notes 1. The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 420 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1. 3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 0. User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Note 1 Type Priority Name Trigger Internal/ Vector Basic External Table Configuration Address Maskable 20 INTKR 21 INTWT 22 INTP6 23 INTP7 24 INTDMU 25 26 Key interrupt detection Type Note 2 External 002CH (C) Watch timer overflow Internal 002EH (A) Pin input edge detection External 0030H (B) 0032H End of multiply/divide operation Internal 0034H Note 3 End of CSI11 communication 0036H Note 3 Match between TM01 and CR001 (when 0038H INTCSI11 INTTM001 (A) compare register is specified), TI011 pin valid edge detection (when capture register is specified) 27 Note 3 INTTM011 Match between TM01 and CR011 (when 003AH compare register is specified), TI001 pin valid edge detection (when capture register is specified) 28 INTACSI Software - BRK Reset - RESET End of CSIA0 communication 003CH BRK instruction execution - 003EH (D) Reset input - 0000H - Note 4 POC Power-on-clear LVI Low-voltage detection Note 5 Clock monitor X1 oscillation stop detection WDT Notes 1. WDT overflow The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 2. 3. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1. The interrupt sources INTCSI11, INTTM001, and INTTM011 are available only in the PD780146, 780148, and 78F0148. 4. When "POC used" is selected by a mask option. 5. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1. User's Manual U15947EJ3V1UD 421 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Priority controller IF Vector table address generator Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Interrupt request Edge detector MK IF IE PR ISP Priority controller Vector table address generator Standby release signal IF: 422 Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus MK Interrupt request Key interrupt detector IE PR ISP Priority controller IF Vector table address generator 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt request IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag Priority controller Vector table address generator KRM: Key return mode register 19.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) * Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) * Priority specification flag register (PR0L, PR0H, PR1L, PR1H) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 19-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. User's Manual U15947EJ3V1UD 423 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-2. Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Register Register LVIIF INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTSRE6 SREIF6 SREMK6 SREPR6 INTSR6 SRIF6 INTST6 STIF6 IF0H LVIMK MK0L Register INTLVI INTCSI10 IF0L Priority Specification Flag SRMK6 MK0H STMK6 DUALIF0 Note 1 LVIPR PR0L SRPR6 PR0H STPR6 Note 2 DUALMK0 DUALPR0 Note 2 INTST0 INTTMH1 TMIFH1 TMMKH1 TMPRH1 INTTMH0 TMIFH0 TMMKH0 TMPRH0 INTTM50 TMIF50 TMMK50 TMPR50 INTTM000 TMIF000 TMMK000 TMPR000 INTTM010 TMIF010 TMMK010 TMPR010 INTAD ADIF INTSR0 SRIF0 SRMK0 SRPR0 INTWTI WTIIF WTIMK WTIPR INTTM51 TMIF51 TMMK51 TMPR51 INTKR KRIF KRMK KRPR INTWT WTIF WTMK WTPR INTP6 PIF6 PMK6 PPR6 INTP7 PIF7 PMK7 PPR7 INTDMU INTCSI11 DMUIF Note 3 INTTM001 Note 3 INTTM011 Note 3 INTACSI Notes 1. 2. 3. 424 IF1L IF1H Note 3 CSIIF11 TMIF001 Note 3 TMIF011 Note 3 ACSIIF ADMK MK1L DMUMK CSIMK11 MK1H Note 3 ADPR PR1L DMUPR PR1H Note 3 CSIPR11 TMMK001 Note 3 TMPR001 Note 3 TMMK011 Note 3 TMPR011 Note 3 ACSIMK ACSIPR If either of the two types of interrupt sources is generated, these flags are set (1). Both types of interrupt sources are supported. PD780146, 780148, and 78F0148 only. User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 Address: FFE2H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF1L PIF7 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF 5 <4> <3> <2> <1> <0> Address: FFE3H Symbol IF1H After reset: 00H 7 0 6 0 R/W 0 ACSIIF XXIFX TMIF011 Note TMIF001 Note Note CSIIF11 DMUIF Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request signal is generated, interrupt request status Note PD780146, 780148, and 78F0148 only. Be sure to clear these bits to 0 in the PD780143 and 780144. Cautions 1. Be sure to clear bits 5 to 7 of IF1H to 0. 2. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. User's Manual U15947EJ3V1UD 425 CHAPTER 19 INTERRUPT FUNCTIONS Caution 3. Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the interrupt request flag register. A 1-bit manipulation instruction such as "IF0L.0 = 0;" and "_asm("clr1 IF0L, 0");" should be used when describing in C language, because assembly instructions after compilation must be 1-bit memory manipulation instructions (CLR1). If an 8-bit memory manipulation instruction "IF0L & = 0xfe;" is described in C language, for example, it is converted to the following three assembly instructions after compilation: mov a, IF0L and a, #0FEH mov IF0L, a In this case, at the timing between "mov a, IF0L" and "mov IF0L, a", if the request flag of another bit of the identical interrupt request flag register (IF0L) is set to 1, it is cleared to 0 by "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. RESET input sets MK0L, MK0H, and MK1L to FFH and MK1H to DFH. Figure 19-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 Address: FFE6H Symbol MK1L MK1H R/W <7> <6> <5> <4> <3> <2> <1> <0> PMK7 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK <4> <3> <2> <1> <0> Address: FFE7H Symbol After reset: FFH After reset: DFH 7 1 6 1 R/W 5 0 XXMKX ACSIMK Note TMMK011 Note TMMK001 CSIMK11 Note DMUMK Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note PD780146, 780148, and 78F0148 only. Be sure to set these bits to 1 in the PD780143 and 780144. Caution Be sure to set bits 6 and 7 of MK1H to 1 and clear bit 5 to 0. 426 User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 19-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) Address: FFE8H After reset: FFH Symbol PR0L <7> <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H After reset: FFH Symbol PR0H <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 Symbol PR1H After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> PPR7 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR <4> <3> <2> <1> <0> Address: FFEBH Symbol R/W <7> Address: FFEAH PR1L R/W After reset: FFH 7 1 R/W 6 1 5 1 XXPRX ACSIPR TMPR011 Note TMPR001 Note CSIPR11 Note DMUPR Priority level selection 0 High priority level 1 Low priority level Note PD780146, 780148, and 78F0148 only. Be sure to set these bits to 1 in the PD780143 and 780144. Caution Be sure to set bits 5 to 7 of PR1H to 1. User's Manual U15947EJ3V1UD 427 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 19-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) Address: FF48H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGP7 EPG6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 EGP R/W Address: FF49H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges EGN R/W INTPn pin valid edge selection (n = 0 to 7) Table 19-3 shows the ports corresponding to EGPn and EGNn. Table 19-3. Ports Corresponding to EGPn and EGNn Detection Enable Register Edge Detection Port Interrupt Request Signal EGP0 EGN0 P120 INTP0 EGP1 EGN1 P30 INTP1 EGP2 EGN2 P31 INTP2 EGP3 EGN3 P32 INTP3 EGP4 EGN4 P33 INTP4 EGP5 EGN5 P16 INTP5 EGP6 EGN6 P140 INTP6 EGP7 EGN7 P141 INTP7 Caution Select the port mode after clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. Remark 428 n = 0 to 7 User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 19-6. Format of Program Status Word PSW <7> <6> <5> <4> <3> 2 <1> 0 After reset IE Z RBS1 AC RBS0 0 ISP CY 02H Used when normal instruction is executed ISP Priority of interrupt currently being serviced 0 High-priority interrupt servicing (low-priority interrupt disabled) 1 Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled) IE Interrupt request acknowledgment enable/disable 0 Disabled 1 Enabled User's Manual U15947EJ3V1UD 429 CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Maskable interrupt request acknowledgement A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 19-4 below. For the interrupt request acknowledgment timing, see Figures 19-8 and 19-9. Table 19-4. Time from Generation of Maskable Interrupt Request Until Servicing Note Minimum Time Maximum Time When xxPR = 0 7 clocks 32 clocks When xxPR = 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 19-7 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. 430 User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending Any high-priority interrupt request among those simultaneously generated with xxPR = 0? No No No IE = 1? Yes Interrupt request held pending Interrupt request held pending Any high-priority interrupt request among those simultaneously generated? No IE = 1? Vectored interrupt servicing Yes ISP = 1? Yes Yes Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR: Priority specification flag IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) User's Manual U15947EJ3V1UD 431 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, jump to interrupt servicing Instruction Interrupt servicing program xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 19-9. Interrupt Request Acknowledgment Timing (Maximum Time) CPU processing Instruction 25 clocks 6 clocks Divide instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF (xxPR = 1) 33 clocks xxIF (xxPR = 0) 32 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) 19.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. 432 User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS 19.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). Also, when an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of one main processing instruction execution. Table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 19-10 shows multiple interrupt servicing examples. Table 19-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request PR = 0 Interrupt PR = 1 Request Interrupt Being Serviced Maskable interrupt Software Maskable Interrupt Request IE = 1 IE = 0 IE = 1 IE = 0 ISP = 0 x x x ISP = 1 x x x x Software interrupt Remarks 1. : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: Interrupt request acknowledgment is disabled. IE = 1: Interrupt request acknowledgment is enabled. 4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H. PR = 0: Higher priority level PR = 1: Lower priority level User's Manual U15947EJ3V1UD 433 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing IE = 0 EI IE = 0 IE = 0 EI INTxx (PR = 1) INTzz servicing EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 1 RETI IE = 1 RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing IE = 0 EI EI INTxx (PR = 0) INTyy (PR = 1) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: 434 Interrupt request acknowledgment disabled User's Manual U15947EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 EI INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgment disabled User's Manual U15947EJ3V1UD 435 CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW.bit, CY * MOV1 CY, PSW.bit * AND1 CY, PSW.bit * OR1 CY, PSW.bit * XOR1 CY, PSW.bit * SET1 PSW.bit * CLR1 PSW.bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW.bit, $addr16 * BF PSW.bit, $addr16 * BTCLR PSW.bit, $addr16 * EI * DI * Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and PR1H registers Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 19-11 shows the timing at which interrupt requests are held pending. Figure 19-11. Interrupt Request Hold CPU processing Instruction N Instruction M PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). 436 User's Manual U15947EJ3V1UD CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 20-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0 Controls KR0 signal in 1-bit units. KRM1 Controls KR1 signal in 1-bit units. KRM2 Controls KR2 signal in 1-bit units. KRM3 Controls KR3 signal in 1-bit units. KRM4 Controls KR4 signal in 1-bit units. KRM5 Controls KR5 signal in 1-bit units. KRM6 Controls KR6 signal in 1-bit units. KRM7 Controls KR7 signal in 1-bit units. 20.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 20-2. Configuration of Key Interrupt Item Control register Configuration Key return mode register (KRM) Figure 20-1. Block Diagram of Key Interrupt KR7 KR6 KR5 KR4 Edge detector KR3 INTKR KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) User's Manual U15947EJ3V1UD 437 CHAPTER 20 KEY INTERRUPT FUNCTION 20.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 20-2. Format of Key Return Mode Register (KRM) Address: FF6EH Symbol KRM After reset: 00H R/W 7 6 5 4 3 2 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRMn 0 KRM1 KRM0 Key interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the corresponding pull-up resistor register 7 (PU7) to 1. 2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. After that, clear the interrupt request flag and then enable interrupts. 3. The bits not used in the key interrupt mode can be used as normal ports. 438 User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function and Configuration 21.1.1 Standby function Table 21-1. Relationship Between Operation Clocks in Each Operation Status Status Operation Mode Reset X1 Oscillator MSTOP = 0 MSTOP = 1 MCC = 0 Internal Oscillator Note 1 MCC = 1 Note 2 Clock After Oscillator Release Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1 RSTOP = 0 RSTOP = 1 Oscillating Stopped Stopped Subsystem CPU Clock Internal Stopped oscillation Oscillating STOP HALT Oscillating Oscillating Stopped Stopped Note 3 Stopped Note 4 Internal X1 oscillation Notes 1. When "Cannot be stopped" is selected for internal oscillator by a mask option. 2. When "Can be stopped by software" is selected for internal oscillator by a mask option. 3. Operates using the CPU clock at STOP instruction execution. 4. Operates using the CPU clock at HALT instruction execution. Caution The RSTOP setting is valid only when "Can be stopped by software" is set for internal oscillator by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: Bit 7 of the processor clock control register (PCC) RSTOP: Bit 0 of the internal oscillation mode register (RCM) MCM0: Bit 0 of the main clock mode register (MCM) The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the X1 oscillator, internal oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. User's Manual U15947EJ3V1UD 439 CHAPTER 21 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the X1 oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. STOP mode can be used only when CPU is operating on the X1 input clock or internal oscillation clock. HALT mode can be used when CPU is operating on the X1 input clock, internal oscillation clock, or subsystem clock. However, when the STOP instruction is executed during internal oscillation clock operation, the X1 oscillator stops, but internal oscillator does not stop. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction. 3. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 4. If the internal oscillator is operating before the STOP mode is set, oscillation of the internal oscillation clock cannot be stopped in the STOP mode. However, when the internal oscillation clock is used as the CPU clock, the CPU operation is stopped for 17/fR (s) after STOP mode is released. 21.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark 440 For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR. User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the internal oscillation clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. Reset release (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP (bit 7 of MOC register) = 1, and MCC (bit 7 of PCC register) = 1 clear OSTC to 00H. Figure 21-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 OSTC 0 0 0 MOST11 MOST13 MOST11 MOST13 MOST14 MOST15 MOST16 1 1 1 1 1 6 5 0 0 1 0 0 1 1 0 0 1 1 3 0 0 1 4 0 1 1 0 1 1 2 MOST14 1 MOST15 0 MOST16 Oscillation stabilization time status When fXP = When fXP = 10 MHz 12 MHz Note 11 204.8 s min. 170.7 s min. 13 819.2 s min. 682.7 s min. 14 1.64 ms min. 1.37 ms min. 15 3.27 ms min. 2.73 ms min. 16 6.55 ms min. 5.46 ms min. 2 /fXP min. 2 /fXP min. 2 /fXP min. 2 /fXP min. 2 /fXP min. Note Expanded-specification products of standard products and (A) grade products only Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 3. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remark fXP: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD 441 CHAPTER 21 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock. After STOP mode is released when the internal oscillation clock is selected as the CPU clock, check the oscillation stabilization time using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 21-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection When fXP = 10 MHz 0 0 0 1 1 0 1 1 0 1 1 0 0 0 1 Other than above Note When fXP = 12 MHz 11 204.8 s 170.7 s 13 819.2 s 682.7 s 14 1.64 ms 1.37 ms 15 3.27 ms 2.73 ms 16 6.55 ms 5.46 ms 2 /fXP 2 /fXP 2 /fXP 2 /fXP 2 /fXP Setting prohibited Note Expanded-specification products of standard products and (A) grade products only Cautions 1. To set the STOP mode while the X1 input clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Before setting OSTS, confirm with OSTC that the desired oscillation stabilization time has elapsed. 3. If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 4. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remark 442 fXP: X1 input clock oscillation frequency User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operation 21.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the X1 input clock, internal oscillation clock, or subsystem clock. The operating statuses in the HALT mode are shown below. Table 21-2. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on X1 Input Clock When Internal Oscillation Clock Continues When Internal Oscillation Clock StoppedNote 1 When Subsystem Clock Used When Subsystem Clock Used Item When Subsystem Clock Not Used System clock Clock supply to the CPU is stopped CPU Operation stopped When Subsystem Clock Not Used When HALT Instruction Is Executed While CPU Is Operating on Internal Oscillation Clock When X1 Input Clock Oscillation Continues When Subsystem Clock Used When Subsystem Clock Not Used When X1 Input Clock Oscillation Stopped When Subsystem Clock Used When Subsystem Clock Not Used Port (output latch) Status before HALT mode was set is retained 16-bit timer/event counter 00 Operable Operation not guaranteed 16-bit timer/event counter 01Note 2 Operable Operation not guaranteed 8-bit timer/event counter 50 Operable Operation not guaranteed when count clock other than TI50 is selected 8-bit timer/event counter 51 Operable Operation not guaranteed when count clock other than TI51 is selected 8-bit timer H0 Operable Operation not guaranteed when count clock other than TM50 output is selected during 8-bit timer/event counter 50 operation 8-bit timer H1 Operable Operation not guaranteed when count clock other than fR/27 is selected Watch timer Operable Watchdog timer OperableNote 3 Operable Internal oscillator cannot be stoppedNote 5 Operable Internal oscillator can be stoppedNote 5 Operation stopped OperableNote 3 OperableNote 4 Operation not guaranteed - OperableNote 4 Operation not guaranteed Operable A/D converter Operable Operation not guaranteed Serial interface Operable Operation not guaranteed when serial clock other than TM50 output is selected during TM50 operation UART0 UART6 Operable CSI10 Operable Operation not guaranteed when serial clock other than external SCK10 is selected CSI11Note 2 Operable Operation not guaranteed when serial clock other than external SCK11 is selected CSIA0 Operable Clock monitor Operable Multiplier/divider Operable Power-on-clear functionNote 6 Operable Low-voltage detection function Operable External interrupt Operable Notes 1. 2. 3. 4. 5. 6. Operation not guaranteed Operation stopped Operable Operation stopped Operation not guaranteed When "Stopped by software" is selected for internal oscillator by a mask option and internal oscillator is stopped by software (for mask options, see CHAPTER 27 MASK OPTIONS). PD780146, 780148, and 78F0148 only. Operable when the X1 input clock is selected. Operation not guaranteed when other than subsystem clock is selected. "Internal oscillator cannot be stopped" or "Internal oscillator can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option. User's Manual U15947EJ3V1UD 443 CHAPTER 21 STANDBY FUNCTION Table 21-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When X1 Input Clock Oscillation Continues Item When Internal Oscillation Clock Continues When Internal Oscillation Clock StoppedNote 1 System clock Clock supply to the CPU is stopped CPU Operation stopped When X1 Input Clock Oscillation Stopped When Internal Oscillation Clock Continues When Internal Oscillation Clock StoppedNote 1 Port (output latch) Status before HALT mode was set is retained 16-bit timer/event counter 00 Operable Operation stopped 16-bit timer/event counter 01 Operable Operation stopped 8-bit timer/event counter 50 Operable Operable only when TI50 is selected as the count clock 8-bit timer/event counter 51 Operable Operable only when TI51 is selected as the count clock 8-bit timer H0 Operable Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer H1 Operable Note 2 Watch timer Watchdog timer Operable only when the X1 input clock is selected as the count clock Operable Internal oscillator cannot be stoppedNote 3 Operable Internal oscillator can be stoppedNote 3 Operation stopped Operable only when fR/27 is selected as the count clock Operation stopped Operable only when subsystem clock is selected - Operable - A/D converter Operable Not operable Serial interface Operable Operable only when TM50 output is selected as the serial clock during TM50 operation UART0 UART6 Operable CSI10 Operable Operable only when external SCK10 is selected as the serial clock CSI11Note 2 Operable Operable only when external SCK11 is selected as the serial clock CSIA0 Operable Clock monitor Operable Multiplier/divider Operable Power-on-clear functionNote 4 Operable Low-voltage detection function Operable External interrupt Operable Notes 1. Operation stopped Operation stopped Operation stopped When "Stopped by software" is selected for internal oscillator by a mask option and internal oscillator is 2. stopped by software (for mask options, see CHAPTER 27 MASK OPTIONS). PD780146, 780148, and 78F0148 only. 3. "Internal oscillator cannot be stopped" or "Internal oscillator can be stopped by software" can be selected by a mask option. 4. 444 When "POC used" is selected by a mask option. User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 21-3. HALT Mode Release by Interrupt Request Generation HALT instruction Interrupt request Wait Standby release signal Status of CPU Operating mode HALT mode Wait Operating mode Oscillation X1 input clock, internal oscillation clock, or subsystem clock Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 8 or 9 clocks * When vectored interrupt servicing is not carried out: 2 or 3 clocks User's Manual U15947EJ3V1UD 445 CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-4. HALT Mode Release by RESET Input (1/2) (1) When X1 input clock is used as CPU clock HALT instruction RESET signal Status of CPU Operating mode HALT mode (X1 input clock) Oscillates X1 input clock Operation Operating mode stopped (17/fR) (Internal oscillation clock) Oscillation Oscillates stopped Reset period Oscillation stabilization time (211/fXP to 216/fXP) (2) When internal oscillation clock is used as CPU clock HALT instruction RESET signal Status of CPU Operating mode HALT mode (Internal oscillation clock) Internal oscillation clock Oscillates Operation Operating mode stopped (Internal oscillation clock) Oscillation (17/fR) Oscillates stopped Reset period Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Internal oscillation clock frequency 446 User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION Figure 21-4. HALT Mode Release by RESET Input (2/2) (3) When subsystem clock is used as CPU clock HALT instruction RESET signal Operating mode Status of CPU Reset period HALT mode Operation stopped Operating mode (17/fR) (Internal oscillation clock) Subsystem clock Subsystem clock Oscillates Remark fR: Internal oscillation clock frequency Table 21-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt MKxx PRxx IE ISP 0 0 0 x request Operation Next address instruction execution 0 0 1 x Interrupt servicing execution 0 1 0 1 Next address 0 1 x 0 instruction execution 0 1 1 1 Interrupt servicing execution RESET input 1 x x x HALT mode held - - x x Reset processing x: don't care User's Manual U15947EJ3V1UD 447 CHAPTER 21 STANDBY FUNCTION 21.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set when the CPU clock before the setting was the X1 input clock or internal oscillation clock. Caution Because the interrupt request signal is used to release the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. Table 21-4. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on X1 Input Clock When Internal Oscillation Clock Continues When Internal Oscillation Clock StoppedNote 1 When STOP Instruction Is Executed While CPU Is Operating on Internal Oscillation Clock Item When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem Clock Used Clock Not Used Clock Used Clock Not Used Clock Used Clock Not Used System clock Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped. CPU Operation stopped Port (output latch) Status before STOP mode was set is retained 16-bit timer/event counter 00 Operation stopped 16-bit timer/event counter 01Note 2 Operation stopped 8-bit timer/event counter 50 Operable only when TI50 is selected as the count clock 8-bit timer/event counter 51 Operable only when TI51 is selected as the count clock 8-bit timer H0 Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer H1 OperableNote 3 Note 4 Operable Watch timer Watchdog timer Internal oscillator cannot be stoppedNote 5 Operable Internal oscillator can be stoppedNote 5 Operation stopped A/D converter OperableNote 3 Operation stopped Note 4 Note 4 Operation stopped Operable Operation stopped Operable - Operation stopped Operable Operation stopped Serial interface UART0 Operable only when TM50 output is selected as the serial clock during TM50 operation UART6 CSI10 Operable only when external SCK10 is selected as the serial clock CSI11Note 2 Operable only when external SCK11 is selected as the serial clock CSIA0 Operation stopped Clock monitor Operation stopped Multiplier/divider Operation stopped Power-on-clear functionNote 6 Operable Low-voltage detection function Operable External interrupt Operable Notes 1. 2. 3. 4. 5. 6. 448 When "Stopped by software" is selected for internal oscillator by a mask option and internal oscillator is stopped by software (for mask options, see CHAPTER 27 MASK OPTIONS). PD780146, 780148, and 78F0148 only. Operable only when fR/27 is selected as the count clock. Operable when the subsystem clock is selected. "Internal oscillator cannot be stopped" or "Internal oscillator can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option. User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION (2) STOP mode release Figure 21-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode X1 input clock Internal oscillation clock X1 input clock is selected as CPU clock when STOP instruction is executed HALT status (oscillation stabilization time set by OSTS) Internal oscillation clock is selected as CPU clock when STOP instruction is executed Internal oscillation clock Operation stopped (17/fR) X1 input clock X1 input clock Clock switched by software The STOP mode can be released by the following two sources. User's Manual U15947EJ3V1UD 449 CHAPTER 21 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 21-6. STOP Mode Release by Interrupt Request Generation (1) When X1 input clock is used as CPU clock Wait (set by OSTS) STOP instruction Standby release signal Status of CPU Operating mode X1 input clock (X1 input clock) Oscillates STOP mode Oscillation stabilization wait Operating mode (X1 input clock) Oscillation stopped (HALT mode status) Oscillates Oscillation stabilization time (set by OSTS) (2) When internal oscillation clock is used as CPU clock STOP instruction Standby release signal Operating mode Status of CPU (Internal oscillation clock) STOP mode Operation stopped Operating mode (17/fR) (Internal oscillation clock) Oscillates Internal oscillation clock Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. fR: Internal oscillation clock frequency 450 User's Manual U15947EJ3V1UD CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 21-7. STOP Mode Release by RESET Input (1) When X1 input clock is used as CPU clock STOP instruction RESET signal Status of CPU Operating mode (X1 input clock) Oscillates X1 input clock STOP mode Oscillation stopped Reset period Operation Operating mode stopped (17/f R) (Internal oscillation clock) Oscillation Oscillates stopped Oscillation stabilization time (211/fXP to 216/fXP) (2) When internal oscillation clock is used as CPU clock STOP instruction RESET signal Status of CPU Operating mode Reset period Operation Operating mode stopped (17/f (Internal oscillation clock) R) Oscillation Oscillates stopped STOP mode (Internal oscillation clock) Internal oscillation clock Oscillates Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Internal oscillation clock frequency Table 21-5. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt MKxx PRxx IE ISP 0 0 0 x request Operation Next address instruction execution 0 0 1 x 0 1 0 1 Next address 0 1 x 0 instruction execution 0 1 1 1 Interrupt servicing Interrupt servicing execution execution RESET input 1 x x x STOP mode held - - x x Reset processing x: don't care User's Manual U15947EJ3V1UD 451 CHAPTER 22 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 input clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is input. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 22-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a high level is input to the RESET pin, the reset is released and program execution starts using the internal oscillation clock after the CPU clock operation has stopped for 17/fR (s). A reset generated by the watchdog timer and clock monitor sources is automatically released after the reset, and program execution starts using the internal oscillation clock after the CPU clock operation has stopped for 17/fR (s) (see Figures 22-2 to 22-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program execution starts using the internal oscillation clock after the CPU clock operation has stopped for 17/fR (s) (see CHAPTER 24 POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, the X1 input clock and internal oscillation clock stop oscillating. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to lowlevel output. 452 User's Manual U15947EJ3V1UD Figure 22-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Watchdog timer reset signal CLMRF LVIRF Set Set Set Clear Clear Clear User's Manual U15947EJ3V1UD RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register Reset signal CHAPTER 22 RESET FUNCTION Clock monitor reset signal 453 CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset by RESET Input Internal oscillation clock X1 input clock CPU clock Reset period (Oscillation stop) Normal operation Operation stop (17/fR) Normal operation (Reset processing, internal oscillation clock) RESET Internal reset signal Delay Delay Port pin (except P130) Hi-Z Note Port pin (P130) Note Set P130 to high-level output by software. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. Figure 22-3. Timing of Reset Due to Watchdog Timer Overflow Internal oscillation clock X1 input clock CPU clock Reset period (Oscillation stop) Normal operation Operation stop (17/fR) Watchdog timer overflow Normal operation (Reset processing, internal oscillation clock) Internal reset signal Hi-Z Port pin (except P130) Note Port pin (P130) Note Set P130 to high-level output by software. Caution A watchdog timer internal reset resets the watchdog timer. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. 454 User's Manual U15947EJ3V1UD CHAPTER 22 RESET FUNCTION Figure 22-4. Timing of Reset in STOP Mode by RESET Input Internal oscillation clock X1 input clock CPU clock STOP instruction execution Operation stop Normal Reset period Stop status operation (Oscillation stop) (Oscillation stop) (17/fR) Normal operation (Reset processing, internal oscillation clock) RESET Internal reset signal Delay Delay Hi-Z Port pin (except P130) Port pin (P130) Note Note Set P130 to high-level output by software. Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. 2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24 POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR. User's Manual U15947EJ3V1UD 455 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (1/3) Hardware Status After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined Note 2 General-purpose registers Undefined Note 2 Port registers (P0 to P7, P12 to P14) (output latches) 00H (undefined only for P2) Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) FFH Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) 00H Input switch control register (ISC) 00H Internal memory size switching register (IMS) CFH Internal expansion RAM size switching register (IXS) 0CH Memory expansion mode register (MEM) 00H Memory expansion wait setting register (MM) 10H Processor clock control register (PCC) 00H Internal oscillation mode register (RCM) 00H Main clock mode register (MCM) 00H Main OSC control register (MOC) 00H Oscillation stabilization time select register (OSTS) 05H Oscillation stabilization time counter status register (OSTC) 00H 16-bit timer/event Note 3 counters 00, 01 Timer counters 00, 01 (TM00, TM01) 0000H Capture/compare registers 000, 010, 001, 011 (CR000, CR010, CR001, CR011) 0000H Mode control registers 00, 01 (TMC00, TMC01) 00H Prescaler mode registers 00, 01 (PRM00, PRM01) 00H 8-bit timer/event counters 50, 51 8-bit timers H0, H1 Capture/compare control registers 00, 01 (CRC00, CRC01) 00H Timer output control registers 00, 01 (TOC00, TOC01) 00H Timer counters 50, 51 (TM50, TM51) 00H Compare registers 50, 51 (CR50, CR51) 00H Timer clock selection registers 50, 51 (TCL50, TCL51) 00H Mode control registers 50, 51 (TMC50, TMC51) 00H Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H Mode registers (TMHMD0, TMHMD1) 00H Note 4 Carrier control register 1 (TMCYC1) 00H Watch timer Operation mode register (WTM) 00H Clock output/buzzer output controller Clock output selection register (CKS) 00H Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 456 2. 3. When a reset is executed in the standby mode, the pre-reset status is held even after reset. 16-bit timer/event counter 01 is available only for the PD780146, 780148, and 78F0148. 4. 8-bit timer H1 only. User's Manual U15947EJ3V1UD CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Watchdog timer A/D converter Serial interface UART0 Serial interface UART6 Serial interfaces CSI10, Note CSI11 Serial interface CSIA0 Multiplier/divider Status After Reset Acknowledgment Mode register (WDTM) 67H Enable register (WDTE) 9AH Conversion result register (ADCR) Undefined Mode register (ADM) 00H Analog input channel specification register (ADS) 00H Power-fail comparison mode register (PFM) 00H Power-fail comparison threshold register (PFT) 00H Receive buffer register 0 (RXB0) FFH Transmit shift register 0 (TXS0) FFH Asynchronous serial interface operation mode register 0 (ASIM0) 01H Baud rate generator control register 0 (BRGC0) 1FH Receive buffer register 6 (RXB6) FFH Transmit buffer register 6 (TXB6) FFH Asynchronous serial interface operation mode register 6 (ASIM6) 01H Asynchronous serial interface reception error status register 6 (ASIS6) 00H Asynchronous serial interface transmission status register 6 (ASIF6) 00H Clock selection register 6 (CKSR6) 00H Baud rate generator control register 6 (BRGC6) FFH Asynchronous serial interface control register 6 (ASICL6) 16H Transmit buffer registers 10, 11 (SOTB10, SOTB11) Undefined Serial I/O shift registers 10, 11 (SIO10, SIO11) Undefined Serial operation mode registers 10, 11 (CSIM10, CSIM11) 00H Serial clock selection registers 10, 11 (CSIC10, CSIC11) 00H Shift register 0 (SIOA0) 00H Operation mode specification register 0 (CSIMA0) 00H Status register 0 (CSIS0) 00H Trigger register 0 (CSIT0) 00H Divisor selection register 0 (BRGCA0) 03H Automatic data transfer address point specification register 0 (ADTP0) 00H Automatic data transfer interval specification register 0 (ADTI0) 00H Automatic data transfer address count register 0 (ADTC0) 00H Remainder data register 0 (SDR0) 0000H Multiplication/division data register A0 (MDA0H, MDA0L) 0000H Multiplication/division data register B0 (MDB0) 0000H Multiplier/divider control register 0 (DMUC0) 00H Key interrupt Key return mode register (KRM) 00H Clock monitor Mode register (CLM) 00H Note Serial interface CSI11 is available only for the PD780146, 780148, and 78F0148. User's Manual U15947EJ3V1UD 457 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Acknowledgment Note Reset function Reset control flag register (RESF) 00H Low-voltage detector Low-voltage detection register (LVIM) 00H Low-voltage detection level selection register (LVIS) 00H Interrupt Note Note Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) 00H Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) FFH Mask flag register 1H (MK1H) DFH Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L, PR1H) FFH External interrupt rising edge enable register (EGP) 00H External interrupt falling edge enable register (EGN) 00H Note These values vary depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI Register RESF See Table 22-2. LVIM Cleared (00H) Cleared (00H) Cleared (00H) LVIS 458 User's Manual U15947EJ3V1UD Cleared (00H) Held CHAPTER 22 RESET FUNCTION 22.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KF1. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 22-5. Format of Reset Control Flag Register (RESF) Address: FFACH After reset: 00H Note R Symbol 7 6 5 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 CLMRF LVIRF WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. CLMRF Internal reset request by clock monitor (CLM) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by low-voltage detector (LVI) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 22-2. Table 22-2. RESF Status When Reset Request Is Generated Reset Source RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI Flag WDTRF Cleared (0) Cleared (0) Set (1) Held Held CLMRF Held Set (1) Held LVIRF Held Held Set (1) User's Manual U15947EJ3V1UD 459 CHAPTER 23 CLOCK MONITOR 23.1 Functions of Clock Monitor The clock monitor samples the X1 input clock using the internal oscillator, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION. The clock monitor automatically stops under the following conditions. * Reset is released and during the oscillation stabilization time * In STOP mode and during the oscillation stabilization time * When the X1 input clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation stabilization time * When the internal oscillation clock is stopped Remark MSTOP: Bit 7 of main OSC control register (MOC) MCC: Bit 7 of processor clock control register (PCC) 23.2 Configuration of Clock Monitor Clock monitor includes the following hardware. Table 23-1. Configuration of Clock Monitor Item Configuration Control register Clock monitor mode register (CLM) Figure 23-1. Block Diagram of Clock Monitor Internal bus Clock monitor mode register (CLM) CLME X1 oscillation control signal (MCC, MSTOP) X1 oscillation stabilization status (OSTC overflow) Operation mode controller X1 oscillation monitor circuit X1 input clock Internal oscillation clock Remark MCC: Bit 7 of processor clock control register (PCC) MSTOP: Bit 7 of main OSC control register (MOC) OSTC: 460 Oscillation stabilization time counter status register (OSTC) User's Manual U15947EJ3V1UD Internal reset signal CHAPTER 23 CLOCK MONITOR 23.3 Register Controlling Clock Monitor Clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 23-2. Format of Clock Monitor Mode Register (CLM) Address: FFA9H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> CLM 0 0 0 0 0 0 0 CLME Enables/disables clock monitor operation CLME 0 Disables clock monitor operation 1 Enables clock monitor operation Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal reset signal. 2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. User's Manual U15947EJ3V1UD 461 CHAPTER 23 CLOCK MONITOR 23.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. <Monitor start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <Monitor stop condition> * Reset is released and during the oscillation stabilization time * In STOP mode and during the oscillation stabilization time * When the X1 input clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation stabilization time * When the internal oscillation clock is stopped Remark MSTOP: Bit 7 of main OSC control register (MOC) MCC: Bit 7 of processor clock control register (PCC) Table 23-2. Operation Status of Clock Monitor (When CLME = 1) CPU Operation Clock X1 input clock Operation Mode STOP mode X1 Input Clock Status Internal Oscillation Clock Status Stopped Oscillating Stopped RESET input Oscillating HALT mode Internal oscillation STOP mode clock RESET input Stopped Note Oscillating Stopped Normal operation mode Clock Monitor Status Oscillating Stopped Stopped Note Note Oscillating Operating Stopped Stopped Normal operation mode Oscillating Operating HALT mode Stopped Stopped Note The internal oscillation clock is stopped only when the "Internal oscillator can be stopped by software" is selected by a mask option. If "Internal oscillator cannot be stopped" is selected, the internal oscillation clock cannot be stopped. The clock monitor timing is as shown in Figure 23-3. 462 User's Manual U15947EJ3V1UD CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of X1 input clock 4 clocks of internal oscillation clock X1 input clock Internal oscillation clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time) CPU operation Normal operation Reset Clock supply stopped Normal operation (internal oscillation clock) X1 input clock Oscillation stopped Oscillation stabilization time Internal oscillation clock Oscillation stopped 17 clocks RESET Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Waiting for end of oscillation stabilization time Monitoring RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register is 05H (216/fXP)) of the X1 input clock, monitoring is not performed until the oscillation stabilization time of the X1 input clock ends. Monitoring is automatically started at the end of the oscillation stabilization time. User's Manual U15947EJ3V1UD 463 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time) CPU operation Normal operation Clock supply stopped Reset Normal operation (internal oscillation clock) X1 input clock Oscillation stabilization time Internal oscillation clock 17 clocks RESET Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Monitoring RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS register is 05H (216/fXP)) of the X1 input clock, monitoring is started. (4) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode) CPU operation Normal operation STOP Oscillation stabilization time Normal operation X1 input clock (CPU clock) Oscillation stopped Oscillation stabilization time (time set by OSTS register) Internal oscillation clock CLME Clock monitor status Monitoring Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. 464 User's Manual U15947EJ3V1UD CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on internal oscillation clock and before entering STOP mode) CPU operation Normal operation Clock supply stopped STOP Normal operation X1 input clock Oscillation stopped Oscillation stabilization time (time set by OSTS register) Internal oscillation clock (CPU clock) 17 clocks CLME Clock monitor status Monitoring Monitoring stopped Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. (6) Clock monitor status after X1 input clock oscillation is stopped by software Normal operation (internal oscillation clock or subsystem clockNote) CPU operation X1 input clock Oscillation stopped Oscillation stabilization time (time set by OSTS register) Monitoring stopped Monitoring stopped Internal oscillation clock MSTOP or MCCNote CLME Clock monitor status Monitoring Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the X1 input clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped when oscillation of the X1 input clock is stopped and during the oscillation stabilization time. Note The register that controls oscillation of the X1 input clock differs depending on the type of the clock supplied to the CPU. * When CPU operates on internal oscillation clock: Controlled by bit 7 (MSTOP) of the main OSC control * When CPU operates on subsystem clock: register (MOC) Controlled by bit 7 (MCC) of the processor clock control register (PCC) User's Manual U15947EJ3V1UD 465 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after internal oscillation clock is stopped by software Normal operation (X1 input clock or subsystem clock) CPU operation X1 input clock Internal oscillation clock Oscillation stopped RSTOP Note CLME Clock monitor status Monitoring Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the internal oscillation clock is stopped, monitoring automatically starts after the internal oscillation clock is stopped. Monitoring is stopped when oscillation of the internal oscillation clock is stopped. Note If it is specified by a mask option that internal oscillator cannot be stopped, the setting of bit 0 (RSTOP) of the internal oscillation mode register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS) of the main clock mode register (MCM) is 1. 466 User's Manual U15947EJ3V1UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC), and generates internal reset signal when VDD < VPOC. * The following can be selected by a mask option. * POC disabled POC used (detection voltage: VPOC = 2.85 V 0.15 V)Note * POC used (detection voltage: VPOC = 3.5 V 0.2 V) * Note This option cannot be selected in (A1) and (A2) grade products because their supply voltage VDD is 3.3 to 5.5 V. Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), low-voltage detector (LVI), or clock monitor. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT, LVI, or the clock monitor. For details of the RESF, see CHAPTER 22 RESET FUNCTION. User's Manual U15947EJ3V1UD 467 CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 24-1. Figure 24-1. Block Diagram of Power-on-Clear Circuit VDD VDD Mask option + Internal reset signal - Detection voltage source (VPOC) 24.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC) are compared, and when VDD < VPOC, an internal reset signal is generated. Figure 24-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC) Time Internal reset signal 468 User's Manual U15947EJ3V1UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 24-3. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Reset Checking cause of resetNote 2 ; The internal oscillation clock is set as the CPU clock when the reset signal is generated ; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register. Power-on-clear Start timer (set to 50 ms) Check stabilization of oscillation Note 1 Change CPU clock No 50 ms has passed? (TMIFH1 = 1?) ; 8-bit timer H1 can operate with the internal oscillation clock. Source: fR (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fR: Internal oscillation clock frequency) ; Check the stabilization of oscillation of the X1 input clock by using the OSTC register. ; Change the CPU clock from the internal oscillation clock to the X1 input clock. ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing Notes 1. 2. ; Initialization of ports If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. User's Manual U15947EJ3V1UD 469 CHAPTER 24 POWER-ON-CLEAR CIRCUIT Figure 24-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset cause WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer CLMRF of RESF register = 1? Yes No Reset processing by clock monitor LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated 470 User's Manual U15947EJ3V1UD CHAPTER 25 LOW-VOLTAGE DETECTOR 25.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. Note * Detection levels of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. Note Detection levels of supply voltage differ as follows. Expanded-specification products of standard products and (A) grade products: 8 levels Conventional products of standard products and (A) grade products: 7 levels (A1) grade products and (A2) grade products: 5 levels When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, see CHAPTER 22 RESET FUNCTION. User's Manual U15947EJ3V1UD 471 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.2 Configuration of Low-Voltage Detector A block diagram of the low-voltage detector is shown below. Figure 25-1. Block Diagram of Low-Voltage Detector Low-voltage detection level selector VDD VDD N-ch Selector Internal reset signal + - INTLVI Detection voltage source 3 LVIS2 LVIS1 LVIS0 LVION LVIE Low-voltage detection level selection register (LVIS) LVIMD LVIF Low-voltage detection register (LVIM) Internal bus 25.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. 472 User's Manual U15947EJ3V1UD CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-2. Format of Low-Voltage Detection Register (LVIM) Address: FFBEH After reset: 00H R/WNote 1 Symbol <7> 6 5 <4> 3 2 <1> <0> LVIM LVION 0 0 LVIE 0 0 LVIMD LVIF Notes 2, 3 LVION LVIE Enables low-voltage detection operation 0 Disables operation 1 Enables operation Notes 2, 4, 5 Specifies reference voltage generator 0 Disables operation 1 Enables operation Note 2 LVIMD Low-voltage detection operation mode selection 0 Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI) 1 Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI) Note 6 LVIF Low-voltage detection flag 0 Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled 1 Supply voltage (VDD) < detection voltage (VLVI) Notes 1. 2. Bit 0 is read-only. LVION, LVIE, and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared to 0 in the case of an LVI reset. 3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is confirmed at LVIF. 4. If "POC cannot be used" is selected by a mask option, wait for 2 ms or more by software from 5. If "POC used" is selected by a mask option, setting of LVIE is invalid because the reference when LVIE is set to 1 until LVION is set to 1. voltage generator in the LVI circuit always operates. 6. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Caution To stop LVI, follow either of the procedures below. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then clear LVIE to 0. User's Manual U15947EJ3V1UD 473 CHAPTER 25 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 0 LVIS2 LVIS1 LVIS0 LVIS2 LVIS1 LVIS0 0 0 0 VLVI0 (4.3 V 0.2 V) 0 0 1 VLVI1 (4.1 V 0.2 V) 0 1 0 VLVI2 (3.9 V 0.2 V) 0 1 1 VLVI3 (3.7 V 0.2 V) 1 0 0 VLVI4 (3.5 V 0.2 V) 1 0 1 VLVI5 (3.3 V 0.15 V) 1 1 0 VLVI6 (3.1 V 0.15 V) 1 1 1 VLVI7 (2.85 V 0.15 V) Detection level Note 1 Notes 1, 2 Notes 1, 2 Notes 1, 3, 4 Notes 1. When the detection voltage of the POC circuit is specified as VPOC = 3.5 V 0.2 V by a mask option, do not select VLVI4 to VLVI7 as the LVI detection voltage. Even if VLVI4 to VLVI7 are selected, the POC circuit has priority. 2. Settable only for the expanded-specification/conventional products of the standard products and (A) grade products. 3. When the detection voltage of the POC circuit is specified as VPOC = 2.85 V 0.15 V by a mask option, do not select VLVI7 as the LVI detection voltage. Even if VLVI7 is selected, the POC circuit has priority. 4. Settable only for expanded-specification products of the standard products and (A) grade products. Caution Be sure to clear bits 3 to 7 to 0. 474 User's Manual U15947EJ3V1UD CHAPTER 25 LOW-VOLTAGE DETECTOR 25.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 25-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <8> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <5>. 2. If "POC used" is selected by a mask option, procedures <3> and <4> are not required. 3. If supply voltage (VDD) > detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order. User's Manual U15947EJ3V1UD 475 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) LVIE flag (set by software) <1>Note 1 Not cleared Not cleared <3> Clear <4> 2 ms or longer LVION flag (set by software) Not cleared Not cleared <5> Clear <6> 0.2 ms or longer LVIF flag <7> LVIMD flag (set by software) Clear Note 2 Not cleared Not cleared <8> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. The LVIMK flag is set to "1" by RESET input. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET FUNCTION. Remark <1> to <8> in Figure 25-4 above correspond to <1> to <8> in the description of "when starting operation" in 25.4 (1) When used as reset. 476 User's Manual U15947EJ3V1UD CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <8> Clear the interrupt request flag of LVI (LVIIF) to 0. <9> Release the interrupt mask flag of LVI (LVIMK). <10> Execute the EI instruction (when vectored interrupts are used). Figure 25-5 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <9> above. Caution If "POC used" is selected by a mask option, procedures <3> and <4> are not required. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0 first, and then clear LVIE to 0. User's Manual U15947EJ3V1UD 477 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) <1>Note 1 <9> Cleared by software LVIE flag (set by software) <3> <4> 2 ms or longer LVION flag (set by software) <5> <6> 0.2 ms or longer LVIF flag <7> Note 2 INTLVI LVIIF flag Note 2 <8> Cleared by software Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by RESET input. The LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 25-5 above correspond to <1> to <9> in the description of "when starting operation" in 25.4 (2) When used as interrupt. 478 User's Manual U15947EJ3V1UD CHAPTER 25 LOW-VOLTAGE DETECTOR 25.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (a) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take action (b) below. In this system, take the following actions. <Action> (a) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. User's Manual U15947EJ3V1UD 479 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Checking cause of resetNote 2 ; The internal oscillation clock is set as the CPU clock when the reset signal is generated ; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register. LVI Start timer (set to 50 ms) Check stabilization of oscillation Note 1 Change CPU clock No 50 ms has passed? (TMIFH1 = 1?) ; 8-bit timer H1 can operate with the internal oscillation clock. Source: fR (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fR: Internal oscillation clock frequency) ; Check the stabilization of oscillation of the X1 input clock by using the OSTC register. ; Change the CPU clock from the internal oscillation clock to the X1 input clock. ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing Notes 1. 2. 480 ; Initialization of ports If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. User's Manual U15947EJ3V1UD CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset cause WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer CLMRF of RESF register = 1? Yes No Reset processing by clock monitor LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector User's Manual U15947EJ3V1UD 481 CHAPTER 25 LOW-VOLTAGE DETECTOR (b) When used as interrupt Check that "supply voltage (VDD) > detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0 and enable interrupts (EI). In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) > detection voltage (VLVI)" using the LVIF flag, and then enable interrupts (EI). 482 User's Manual U15947EJ3V1UD CHAPTER 26 REGULATOR 26.1 Outline of Regulator The 78K0/KF1 includes a circuit to realize constant-voltage operation inside the device. To stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (1 F: recommended). The output voltage of the regulator is 3.5 V (TYP.). The supply voltage and oscillation frequency at which the regulator can be used are as follows. * Power supply voltage: VDD = 4.0 to 5.5 V * Oscillation frequency: fX = 2.0 to 8.38 MHz The regulator of the 78K0/KF1 stops operating in the following cases. * During the reset period * In STOP mode * In HALT mode when the CPU is operating on the subsystem clock and when X1 oscillation is stopped Figure 26-1 shows the block diagram of the periphery of the regulator. Figure 26-1. Block Diagram of Regulator Periphery EVDD system I/O buffer Internal digital circuits EVDD Flash memory (PD78F0148 only) A/D converter X1, sub, internal oscillator AVREF Bidirectional level shifter Regulator REGC VDD VPP 1 F Cautions 1. Directly connect the REGC pin of standard products and (A) grade products to VDD when the regulator is not used. 2. The regulator cannot be used with (A1) and (A2) grade products. Be sure to connect the REGC pin of these products directly to VDD. User's Manual U15947EJ3V1UD 483 CHAPTER 26 REGULATOR Figure 26-2. REGC Pin Connection (a) When REGC = VDD VDD Input voltage = 2.5 to 5.5 VNote REG REGC Voltage supply to oscillator/internal logic = 2.5 to 5.5 VNote Note 2.7 to 5.5 V for the conventional products (b) When connecting REGC pin to VSS via a capacitor VDD Input voltage = 4.0 to 5.5 V REG REGC Voltage supply to oscillator/internal logic = 3.5 V 1 F (recommended) 484 User's Manual U15947EJ3V1UD CHAPTER 27 MASK OPTIONS Mask ROM versions are provided with the following mask options. 1. Power-on-clear (POC) circuit * POC cannot be used * POC used (detection voltage: VPOC = 2.85 V 0.15 V)Note * POC used (detection voltage: VPOC = 3.5 V 0.2 V) 2. Internal oscillator * Cannot be stopped * Can be stopped by software 3. Pull-up resistor of P60 to P63 pins * Pull-up resistor can be incorporated in 1-bit units (Pull-up resistors are not available for the flash memory versions.) Note This option cannot be selected in (A1) and (A2) grade products because their supply voltage VDD is 3.3 to 5.5 V. Flash memory versions that support the mask options of the mask ROM versions are as follows. Table 27-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions Mask Option POC Circuit Flash Memory Version Internal Oscillator Cannot be stopped PD78F0148M1, 78F0148M1(A), 78F0148M1(A1) Can be stopped by software PD78F0148M2, 78F0148M2(A), 78F0148M2(A1) POC used (VPOC = 2.85 V 0.15 V) Cannot be stopped PD78F0148M3, 78F0148M3(A) Can be stopped by software PD78F0148M4, 78F0148M4(A) POC used (VPOC = 3.5 V 0.2 V) Cannot be stopped PD78F0148M5, 78F0148M5(A), 78F0148M5(A1) Can be stopped by software PD78F0148M6, 78F0148M6(A), 78F0148M6(A1) POC cannot be used User's Manual U15947EJ3V1UD 485 CHAPTER 28 PD78F0148 The PD78F0148 is provided as the flash memory version of the 78K0/KF1. The PD78F0148 replaces the internal mask ROM of the PD780148 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. PD78F0148 and the mask ROM versions. Table 28-1 lists the differences between the Table 28-1. Differences Between PD78F0148 and Mask ROM Versions PD78F0148 Item Internal ROM configuration Flash memory Mask ROM Versions Mask ROM PD780143: 24 KB PD780144: 32 KB PD780146: 48 KB PD780148: 60 KB Note Internal ROM capacity 60 KB Internal expansion RAM capacity 1024 bytes PD780143: None PD780144: None PD780146: 1024 bytes PD780148: 1024 bytes IC pin None Available VPP pin Available None Note Electrical specifications, Refer to the description of electrical specifications and recommended soldering recommended soldering conditions conditions. Note The same capacity as the mask ROM versions can be specified by means of the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. 486 User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 28.1 Internal Memory Size Switching Register The PD78F0148 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved. IMS is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution The initial value of IMS is CFH. Be sure to set the value of the relevant mask ROM version at initialization. Figure 28-1. Format of Internal Memory Size Switching Register (IMS) Address: FFF0H After reset: CFH Symbol 7 6 5 4 3 2 1 0 RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 1 1 0 IMS R/W Other than above Internal high-speed RAM capacity selection 1024 bytes Setting prohibited ROM3 ROM2 ROM1 ROM0 0 1 1 0 24 KB 1 0 0 0 32 KB 1 1 0 0 48 KB 1 1 1 1 60 KB Other than above Internal ROM capacity selection Setting prohibited The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 28-2. Table 28-2. Internal Memory Size Switching Register Settings Target Mask ROM Versions IMS Setting PD780143 C6H PD780144 C8H PD780146 CCH PD780148 CFH Caution When using a mask ROM version, be sure to set the value indicated in Table 28-2 to IMS. User's Manual U15947EJ3V1UD 487 CHAPTER 28 PD78F0148 28.2 Internal Expansion RAM Size Switching Register This register is used to set the internal expansion RAM capacity via software. This register is set by an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution The initial value of IXS is 0CH. Be sure to set the value of the relevant mask ROM version at initialization. Figure 28-2. Format of Internal Expansion RAM Size Switching Register (IXS) Address: FFF4H After reset: 0CH R/W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 1 1 0 0 0 bytes 0 1 0 1 0 1024 bytes Other than above Internal expansion RAM capacity selection Setting prohibited The IXS settings required to obtain the same memory map as mask ROM versions are shown in Table 28-3. Table 28-3. Internal Expansion RAM Size Switching Register Settings Target Mask ROM Versions IXS Setting PD780143 0CH PD780144 0CH PD780146 0AH PD780148 0AH Caution When using a mask ROM version, be sure to set the value indicated in Table 28-3 to IXS. 488 User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 28.3 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the PD78F0148 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the PD78F0148 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 28-4. Wiring Between PD78F0148 and Dedicated Flash Programmer (1/2) (1) 3-wire serial I/O (CSI10) Pin Configuration of Dedicated Flash Programmer Signal Name I/O With CSI10 Pin Function Pin Name With CSI10 + HS Pin No. Pin Name Pin No. SI/RxD Input Receive signal SO10/P12 20 SO10/P12 20 SO/TxD Output Transmit signal SI10/RxD0/P11 19 SI10/RxD0/P11 19 SCK Output Transfer clock SCK10/TxD0/P10 18 SCK10/TxD0/P10 18 CLK Output Clock to PD78F0148 X1 12 X1 12 X2 Note 13 X2 Note 13 /RESET Output Reset signal RESET 14 RESET 14 VPP Output Write voltage VPP 8 VPP 8 H/S Input Handshake signal Not needed HS/P15/TOH0 23 VDD I/O VDD voltage generation/voltage VDD 9 VDD 9 monitor EVDD 31 EVDD 31 AVREF 1 AVREF 1 VSS 11 VSS 11 EVSS 30 EVSS 30 AVSS 2 AVSS 2 GND - Ground Not needed Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * To GND via a 1 F capacitor * Directly to VDD 2. When connecting the REGC pin to GND via a 1 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the board to supply a clock. User's Manual U15947EJ3V1UD 489 CHAPTER 28 PD78F0148 Table 28-4. Wiring Between PD78F0148 and Dedicated Flash Programmer (2/2) (2) UART (UART0, UART6) Pin Configuration of Dedicated Flash Programmer Signal Name SI/RxD I/O Input Pin Function Receive signal With UART0 Pin Name TxD0/ With UART0 + HS Pin No. 18 SCK10/P10 SO/TxD Output Transmit signal RxD0/SI10/ Output Transfer clock Not needed TxD0/ 19 RxD0/SI10/ Output Clock to PD78F0148 X1 Not X2 12 Note Pin Name Pin No. 18 TxD6/P13 21 19 RxD6/P14 22 Not Not needed P11 Not needed needed CLK Pin No. SCK10/P10 P11 SCK Pin Name With UART6 needed X1 12 13 X2 Note Not needed X1 12 13 X2 Note 13 /RESET Output Reset signal RESET 14 RESET 14 RESET 14 VPP Output Write voltage VPP 8 VPP 8 VPP 8 H/S Input Handshake signal Not needed HS/P15/TOH0 23 Not needed Not needed VDD GND I/O - Not needed VDD voltage generation/voltage VDD 9 VDD 9 VDD 9 monitor EVDD 31 EVDD 31 EVDD 31 AVREF 1 AVREF 1 AVREF 1 VSS 11 VSS 11 VSS 11 EVSS 30 EVSS 30 EVSS 30 AVSS 2 AVSS 2 AVSS 2 Ground Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * To GND via a 1 F capacitor * Directly to VDD 2. When connecting the REGC pin to GND via a 1 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the board to supply a clock. 490 User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 28-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD User's Manual U15947EJ3V1UD 491 CHAPTER 28 PD78F0148 Figure 28-4. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): 492 Connect directly to VDD User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 Figure 28-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD User's Manual U15947EJ3V1UD 493 CHAPTER 28 PD78F0148 Figure 28-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): 494 Connect directly to VDD User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 Figure 28-7. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD User's Manual U15947EJ3V1UD 495 CHAPTER 28 PD78F0148 28.4 Programming Environment The environment required for writing a program to the flash memory of the PD78F0148 is illustrated below. Figure 28-8. Environment for Writing Program to Flash Memory VPP XXXXXX Bxxxxx XXXX XXXX YYYY Axxxx XXX YYY USB VDD Cxxxxxx STATVE PG-FP4 (Flash Pro4) VSS XXXXX RS-232C RESET Note Dedicated flash programmer CSI10/UART0/UART6 PD78F0148 Host machine Note Flashpro IV only A host machine that controls the dedicated flash programmer is necessary. To interface between the dedicated flash programmer and the PD78F0148, CSI10, UART0, or UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 28.5 Communication Mode Communication between the dedicated flash programmer and the PD78F0148 is established by serial communication via CSI10, UART0, or UART6 of the PD78F0148. (1) CSI10 Transfer rate: 200 kHz to 2 MHz Figure 28-9. Communication with Dedicated Flash Programmer (CSI10) VPP VPP VDD VDD/EVDD/AVREF GND VSS/EVSS/AVSS XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx Dedicated flash programmer /RESET RESET SI/RxD SO10 SO/TxD SI10 SCK SCK10 CLK X1 X2 496 User's Manual U15947EJ3V1UD PD78F0148 CHAPTER 28 PD78F0148 (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 28-10. Communication with Dedicated Flash Programmer (CSI10 + HS) VPP VPP VDD VDD/EVDD/AVREF GND XXX YYY VSS/EVSS/AVSS XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXXX YYYY Axxxx Bxxxxx Cxxxxxx Dedicated flash programmer /RESET RESET SI/RxD SO10 SO/TxD SI10 SCK SCK10 CLK X1 PD78F0148 X2 H/S HS (3) UART0 Transfer rate: 4800 to 38400 bps Figure 28-11. Communication with Dedicated Flash Programmer (UART0) XXXXXX XXXX Cxxxxxx STATVE PG-FP4 (Flash Pro4) VPP VDD VDD/EVDD/AVREF GND VSS/EVSS/AVSS XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx VPP Dedicated flash programmer /RESET RESET SO/TxD RxD0 SI/RxD TxD0 CLK PD78F0148 X1 X2 User's Manual U15947EJ3V1UD 497 CHAPTER 28 PD78F0148 (4) UART communication mode supporting handshake Transfer rate: 4800 to 38400 bps Figure 28-12. Communication with Dedicated Flash Programmer (UART0 + HS) VDD VDD/EVDD/AVREF VSS/EVSS/AVSS XXXXXX Axxxx XXXX Bxxxxx STATVE PG-FP4 (Flash Pro4) XXXXX XXXX YYYY VPP GND Cxxxxxx XXX YYY VPP Dedicated flash programmer /RESET RESET SI/RxD TxD0 SO/TxD RxD0 CLK PD78F0148 X1 X2 H/S HS (5) UART6 Transfer rate: 4800 to 76800 bps Figure 28-13. Communication with Dedicated Flash Programmer (UART6) VPP VDD VDD GND VSS XXXXXX XXXX Bxxxxx Cxxxxxx STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx VPP Dedicated flash programmer /RESET RESET SI/RxD TxD6 SO/TxD RxD6 CLK X1 X2 498 User's Manual U15947EJ3V1UD PD78F0148 CHAPTER 28 PD78F0148 If Flashpro III/Flashpro IV is used as the dedicated flash programmer, Flashpro III/Flashpro IV generates the following signal for the PD78F0148. For details, refer to the Flashpro III/Flashpro IV Manual. Table 28-5. Pin Connection Flashpro III/Flashpro IV Signal Name I/O PD78F0148 Connection Pin Name CSI10 UART0 UART6 Pin Function VPP Output Write voltage VPP VDD I/O VDD voltage generation/voltage monitor VDD, EVDD, AVREF Ground VSS, EVSS, AVSS Clock output to PD78F0148 X1, X2 - GND CLK Output Note /RESET Output Reset signal RESET SI/RxD Input Receive signal SO10/TxD0/TxD6 SO/TxD Output Transmit signal SI10/RxD0/RxD6 SCK Output Transfer clock SCK10 H/S Input Handshake signal HS { { { x x x Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Remark : Be sure to connect the pin. {: The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. : In handshake mode User's Manual U15947EJ3V1UD 499 CHAPTER 28 PD78F0148 28.6 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. 28.6.1 VPP pin In the normal operation mode, the VPP pin is connected to VSS. In addition, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin in the flash memory programming mode. Perform the following pin processing. (1) Connect pull-down resistor RVPP = 10 k to the VPP pin. (2) Switch the input of the VPP pin to the programmer side by using a jumper on the board or to GND directly. Figure 28-14. Example of Connection of VPP Pin PD78F0148 Dedicated flash programmer connection pin VPP Pull-down resistor (RVPP) 500 User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 28.6.2 Serial interface pins The pins used by each serial interface are listed below. Table 28-6. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 CSI10 + HS SO10, SI10, SCK10, HS/P15 UART0 TxD0, RxD0 UART0 + HS TxD0, RxD0, HS/P15 UART6 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. (1) Signal collision If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 28-15. Signal Collision (Input Pin of Serial Interface) PD78F0148 Signal collision Input pin Dedicated flash programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. Therefore, isolate the signal of the other device. User's Manual U15947EJ3V1UD 501 CHAPTER 28 PD78F0148 (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device. Figure 28-16. Malfunction of Other Device PD78F0148 Pin Dedicated flash programmer connection pin Other device Input pin If the signal output by the PD78F0148 in the flash memory programming mode affects the other device, isolate the signal of the other device. PD78F0148 Pin Dedicated flash programmer connection pin Other device Input pin If the signal output by the dedicated flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 502 User's Manual U15947EJ3V1UD CHAPTER 28 PD78F0148 28.6.3 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash programmer. Figure 28-17. Signal Collision (RESET Pin) PD78F0148 Dedicated flash programmer connection pin Signal collision RESET Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. Therefore, isolate the signal of the reset signal generator. 28.6.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. 28.6.5 REGC pin Handle the REGC pin in the same manner as during normal operation. * PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor * PD78F0148(A1): Connect directly to VDD 28.6.6 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its inverse signal to X2. 28.6.7 Power supply To use the power supply output of the flash programmer, connect the VDD pin to VDD of the flash programmer, and the VSS pin to VSS of the flash programmer. To use the on-board power supply, connect in compliance with the normal operation mode. However, be sure to connect the VDD and VSS pins to VDD and GND of the flash programmer, respectively, because the voltage is monitored by the flash programmer. Supply the same other power supplies (EVDD, EVSS, AVREF, and AVSS) as those in the normal operation mode. User's Manual U15947EJ3V1UD 503 CHAPTER 28 PD78F0148 28.7 Programming Method 28.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 28-18. Flash Memory Manipulation Procedure Start VPP pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory End? Yes End 504 User's Manual U15947EJ3V1UD No CHAPTER 28 PD78F0148 28.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the PD78F0148 in the flash memory programming mode. To set the mode, set the VPP pin and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 28-19. Flash Memory Programming Mode VPP pulse 1 10.0 V 2 *** n VDD VPP VSS RESET Flash memory programming mode VPP VSS 10.0 V Operation mode Normal operation mode Flash memory programming mode 28.7.3 Selecting communication mode In the PD78F0148 a communication mode is selected by inputting pulses (up to 11 pulses) to the VPP pin after the dedicated flash memory programming mode is entered. These VPP pulses are generated by the flash programmer. The following table shows the relationship between the number of pulses and communication modes. Table 28-7. Communication Modes Standard (TYPE) SettingNote 1 Communication Mode Pins Used Number Port Speed On Target Frequency Multiply Rate of VPP (COMM PORT) (SIO CLOCK) (CPU CLOCK) (Flashpro Clock) (Multiple Rate) Pulses 3-wire serial I/O SIO-ch0 (CSI10) (SIO ch-0) 3-wire serial I/O with SIO-H/S handshake supported (SIO ch-3 (CSI10 + HS) + handshake) UART UART-ch0 (UART0) (UART ch-0) UART UART-ch1 (UART6) (UART ch-1) UART with UART-ch3 handshake supported (UART ch-3) 200 kHz to 2 MHzNote 2 Optional 2 MHz to 1.0 10 MHz 200 kHz to 2 MHzNote 2 SO10, SI10, 0 SCK10 SO10, SI10, 3 SCK10, HS/P15 Notes 2, 3 4800 to 38400 bps TxD0, RxD0 8 4800 to 76800 bpsNotes 2, 3 TxD6, RxD6 9 4800 to 38400 bpsNotes 2, 3 TxD0, RxD0, 11 HS/P15 (UART0 + HS) Notes 1. Selection items for Standard settings on Flashpro IV (TYPE settings on Flashpro III). 2. The possible setting range differs depending on the voltage. For details, refer to the chapters of electrical specifications. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Caution When UART0 or UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the VPP pulse has been received. Remark Items enclosed in parentheses in the setting item column are the set value and set item when they differ from those of Flashpro IV. User's Manual U15947EJ3V1UD 505 CHAPTER 28 PD78F0148 28.7.4 Communication commands The PD78F0148 communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the PD78F0148 are called commands, and the commands sent from the PD78F0148 to the dedicated flash programmer are called response commands. Figure 28-20. Communication Commands XXXXXX Command XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx Dedicated flash programmer Response command PD78F0148 The flash memory control commands of the PD78F0148 are listed in the table below. All these commands are issued from the programmer and the PD78F0148 perform processing corresponding to the respective commands. Table 28-8. Flash Memory Control Commands Classification Command Name Verify Function Compares the contents of the entire memory Batch verify command with the input data. Erase Batch erase command Erases the contents of the entire memory. Blank check Batch blank check command Checks the erasure status of the entire memory. Data write High-speed write command Writes data by specifying the write address and number of bytes to be written, and executes a verify check. Writes data from the address following that of Successive write command the high-speed write command executed immediately before, and executes a verify check. System setting, control Status read command Obtains the operation status Oscillation frequency setting command Sets the oscillation frequency Erase time setting command Sets the erase time for batch erase Write time setting command Sets the write time for writing data Baud rate setting command Sets the baud rate when UART is used Silicon signature command Reads the silicon signature information Reset command Escapes from each status The PD78F0148 returns a response command for the command issued by the dedicated flash programmer. The response commands sent from the PD78F0148 are listed below. Table 28-9. Response Commands Command Name 506 Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KF1 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 29-1. Operand Identifiers and Specification Methods Identifier Specification Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special function register symbol sfrp Special function register symbol (16-bit manipulatable register even addresses only) saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even address only) addr16 0000H to FFFFH Immediate data or labels Note Note (Only even addresses for 16-bit data transfer instructions) addr11 0800H to 0FFFH Immediate data or labels addr5 0040H to 007FH Immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label RBn RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, see Table 3-5 Special Function Register List. User's Manual U15947EJ3V1UD 507 CHAPTER 29 INSTRUCTION SET 29.1.2 Description of operation column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag RBS: Register bank select flag IE: Interrupt request enable flag ( ): Memory contents indicated by address or register contents in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 29.1.3 Description of flag operation column (Blank): Not affected 0: Cleared to 0 1: x: Set to 1 Set/cleared according to the result R: Previously saved value is restored 508 User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET 29.2 Operation List Instruction Group 8-bit data Mnemonic MOV transfer Operands r, #byte 2 Notes 1. Z AC CY Note 2 4 - r byte saddr, #byte 3 6 7 sfr, #byte 3 - 7 sfr byte A, r Note 3 1 2 - Ar r, A Note 3 1 2 - rA 2 4 5 A (saddr) saddr, A 2 4 5 (saddr) A A, sfr 2 - 5 A sfr sfr, A 2 - 5 sfr A A, !addr16 3 8 9+n A (addr16) !addr16, A 3 8 9+m (addr16) A PSW, #byte 3 - 7 PSW byte A, PSW 2 - 5 A PSW PSW, A 2 - 5 PSW A A, [DE] 1 4 5+n A (DE) [DE], A 1 4 5+m (DE) A A, [HL] 1 4 5+n A (HL) [HL], A 1 4 5+m (HL) A A, [HL + byte] 2 8 9+n A (HL + byte) [HL + byte], A 2 8 9+m (HL + byte) A A, [HL + B] 1 6 7+n A (HL + B) [HL + B], A 1 6 7+m (HL + B) A A, [HL + C] 1 6 7+n A (HL + C) [HL + C], A 1 6 7+m (HL + C) A 1 2 - Ar A, r Note 3 Flag Operation Note 1 (saddr) byte A, saddr XCH Clocks Bytes A, saddr 2 4 6 A (saddr) A, sfr 2 - 6 A sfr A, !addr16 3 8 10 + n + m A (addr16) A, [DE] 1 4 6 + n + m A (DE) A, [HL] 1 4 6 + n + m A (HL) A, [HL + byte] 2 8 10 + n + m A (HL + byte) A, [HL + B] 2 8 10 + n + m A (HL + B) A, [HL + C] 2 8 10 + n + m A (HL + C) x x x x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15947EJ3V1UD 509 CHAPTER 29 INSTRUCTION SET Instruction Group 16-bit data Mnemonic MOVW transfer Operands 6 8 10 sfrp, #word 4 - 10 sfrp word AX, saddrp 2 6 8 AX (saddrp) saddrp, AX 2 6 8 (saddrp) AX AX, sfrp 2 - 8 AX sfrp sfrp, AX 2 - 8 sfrp AX 1 4 - AX rp 1 4 - rp AX 3 10 12 + 2n AX (addr16) 12 + 2m (addr16) AX AX, rp Note 3 rp, AX Note 3 AX, rp ADD A, #byte Note 3 saddr, #byte A, r Note 4 r, A 3 10 1 4 - AX rp 2 4 - A, CY A + byte x x x 3 6 8 (saddr), CY (saddr) + byte x x x 2 4 - A, CY A + r x x x 2 4 - r, CY r + A x x x A, CY A + (saddr) x x x A, saddr 2 4 5 A, !addr16 3 8 9+n A, CY A + (addr16) x x x A, [HL] 1 4 5+n A, CY A + (HL) x x x A, [HL + byte] 2 8 9+n A, CY A + (HL + byte) x x x A, [HL + B] 2 8 9+n A, CY A + (HL + B) x x x A, [HL + C] 2 8 9+n A, CY A + (HL + C) x x x A, #byte 2 4 - A, CY A + byte + CY x x x 3 6 8 (saddr), CY (saddr) + byte + CY x x x 2 4 - A, CY A + r + CY x x x r, A 2 4 - r, CY r + A + CY x x x A, saddr 2 4 5 A, CY A + (saddr) + CY x x x A, !addr16 3 8 9+n A, CY A + (addr16) + CY x x x A, [HL] 1 4 5+n A, CY A + (HL) + CY x x x saddr, #byte A, r Notes 1. (saddrp) word 3 4 !addr16, AX ADDC rp word saddrp, #word XCHW operation Z AC CY Note 2 rp, #word Flag Operation Note 1 - AX, !addr16 8-bit Clocks Bytes Note 4 A, [HL + byte] 2 8 9+n A, CY A + (HL + byte) + CY x x x A, [HL + B] 2 8 9+n A, CY A + (HL + B) + CY x x x A, [HL + C] 2 8 9+n A, CY A + (HL + C) + CY x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 510 User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET Instruction Group 8-bit Mnemonic SUB operation Operands A, #byte saddr, #byte Note 2 2 4 - A, CY A - byte x x x 3 6 8 (saddr), CY (saddr) - byte x x x 4 - A, CY A - r x x x 2 4 - r, CY r - A x x x A, saddr 2 4 5 A, CY A - (saddr) x x x Note 3 A, !addr16 3 8 9+n A, CY A - (addr16) x x x A, [HL] 1 4 5+n A, CY A - (HL) x x x A, [HL + byte] 2 8 9+n A, CY A - (HL + byte) x x x x x x x x x A, [HL + B] 2 8 9+n A, CY A - (HL + B) A, [HL + C] 2 8 9+n A, CY A - (HL + C) A, #byte 2 4 - A, CY A - byte - CY x x x saddr, #byte 3 6 8 (saddr), CY (saddr) - byte - CY x x x 2 4 - A, CY A - r - CY x x x r, A 2 4 - r, CY r - A - CY x x x A, saddr 2 4 5 A, CY A - (saddr) - CY x x x A, !addr16 3 8 9+n A, CY A - (addr16) - CY x x x x x x x x x Note 3 A, [HL] 1 4 5+n A, CY A - (HL) - CY A, [HL + byte] 2 8 9+n A, CY A - (HL + byte) - CY A, [HL + B] 2 8 9+n A, CY A - (HL + B) - CY x x x A, [HL + C] 2 8 9+n A, CY A - (HL + C) - CY x x x A, #byte 2 4 - A A byte x saddr, #byte A, r r, A Notes 1. Z AC CY Note 1 2 A, r AND Flag Operation r, A A, r SUBC Clocks Bytes Note 3 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x 2 4 - rrA x A A (saddr) x A, saddr 2 4 5 A, !addr16 3 8 9+n A A (addr16) x A, [HL] 1 4 5+n A A (HL) x A, [HL + byte] 2 8 9+n A A (HL + byte) x A, [HL + B] 2 8 9+n A A (HL + B) x A, [HL + C] 2 8 9+n A A (HL + C) x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. User's Manual U15947EJ3V1UD 511 CHAPTER 29 INSTRUCTION SET Instruction Group 8-bit Mnemonic OR Operands A, #byte operation saddr, #byte Note 2 2 4 - A A byte x 3 6 8 (saddr) (saddr) byte x 4 - AAr x 2 4 - rrA x A, saddr 2 4 5 A A (saddr) x Note 3 A, !addr16 3 8 9+n A A (addr16) x A, [HL] 1 4 5+n A A (HL) x A, [HL + byte] 2 8 9+n A A (HL + byte) x x x A, [HL + B] 2 8 9+n A A (HL + B) A, [HL + C] 2 8 9+n A A (HL + C) A, #byte 2 4 - A A byte x saddr, #byte 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x r, A 2 4 - rrA x A, saddr 2 4 5 A A (saddr) x A, !addr16 3 8 9+n A A (addr16) x x Note 3 A, [HL] 1 4 5+n A A (HL) A, [HL + byte] 2 8 9+n A A (HL + byte) x A, [HL + B] 2 8 9+n A A (HL + B) x A, [HL + C] 2 8 9+n A A (HL + C) x A, #byte 2 4 - A - byte x x x saddr, #byte A, r r, A Notes 1. Z AC CY Note 1 2 A, r CMP Flag Operation r, A A, r XOR Clocks Bytes Note 3 3 6 8 (saddr) - byte x x x 2 4 - A-r x x x 2 4 - r-A x x x A - (saddr) x x x A, saddr 2 4 5 A, !addr16 3 8 9+n A - (addr16) x x x A, [HL] 1 4 5+n A - (HL) x x x A, [HL + byte] 2 8 9+n A - (HL + byte) x x x A, [HL + B] 2 8 9+n A - (HL + B) x x x A, [HL + C] 2 8 9+n A - (HL + C) x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 512 User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Z AC CY Note 1 Note 2 AX, CY AX + word x x x AX, CY AX - word x x x x x x 16-bit ADDW AX, #word 3 6 - operation SUBW AX, #word 3 6 - CMPW AX, #word 3 6 - AX - word Multiply/ MULU X 2 16 - AX A x X divide DIVUW C 2 25 - AX (Quotient), C (Remainder) AX / C Increment/ INC decrement DEC INCW Rotate 2 - rr+1 x x 2 4 6 (saddr) (saddr) + 1 x x r 1 2 - rr-1 x x x x saddr 2 4 6 (saddr) (saddr) - 1 rp 1 4 - rp rp + 1 rp 1 4 - rp rp - 1 A, 1 1 2 - (CY, A7 A0, Am - 1 Am) x 1 time x ROL A, 1 1 2 - (CY, A0 A7, Am + 1 Am) x 1 time x RORC A, 1 1 2 - (CY A0, A7 CY, Am - 1 Am) x 1 time x ROLC A, 1 1 2 - (CY A7, A0 CY, Am + 1 Am) x 1 time x ROR4 [HL] 2 10 12 + n + m A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 ROL4 [HL] 2 10 12 + n + m A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 2 4 - ADJBA ADJBS Bit MOV1 2. 1 DECW adjustment Notes 1. r saddr ROR BCD manipulate Flag Operation Decimal Adjust Accumulator after Addition x x x x x 2 4 - Decimal Adjust Accumulator after Subtract CY, saddr.bit 3 6 7 CY (saddr.bit) x CY, sfr.bit 3 - 7 CY sfr.bit x CY, A.bit 2 4 - CY A.bit x CY, PSW.bit 3 - 7 CY PSW.bit x CY, [HL].bit 2 6 7+n CY (HL).bit x saddr.bit, CY 3 6 8 (saddr.bit) CY sfr.bit, CY 3 - 8 sfr.bit CY A.bit, CY 2 4 - A.bit CY PSW.bit, CY 3 - 8 PSW.bit CY [HL].bit, CY 2 6 x x x 8 + n + m (HL).bit CY When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15947EJ3V1UD 513 CHAPTER 29 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 Bit AND1 manipulate OR1 XOR1 SET1 CLR1 Notes 1. 2. Flag Operation Z AC CY Note 2 CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7+n CY CY (HL).bit x CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7+n CY CY (HL).bit x CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7+n CY CY (HL).bit x saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 - 8 sfr.bit 1 A.bit 2 4 - A.bit 1 6 PSW.bit 1 PSW.bit 2 - [HL].bit 2 6 saddr.bit 2 4 6 (saddr.bit) 0 x x x x x x 8 + n + m (HL).bit 1 sfr.bit 3 - 8 sfr.bit 0 A.bit 2 4 - A.bit 0 PSW.bit 2 - 6 PSW.bit 0 8 + n + m (HL).bit 0 [HL].bit 2 6 SET1 CY 1 2 - CY 1 CLR1 CY 1 2 - CY 0 0 NOT1 CY 1 2 - CY CY x 1 When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 514 User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET Instruction Group Call/return Mnemonic CALL Operands !addr16 Clocks Bytes 3 Note 1 Note 2 7 - Operation Flag Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLF !addr11 2 5 - (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 CALLT [addr5] 1 6 - (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 BRK 1 6 - (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 RET 1 6 - 6 - PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 PCH (SP + 1), PCL (SP), R R R PSW (SP + 2), SP SP + 3 RETB 1 6 - PCH (SP + 1), PCL (SP), R R R PSW (SP + 2), SP SP + 3 Stack PUSH manipulate PSW rp 1 1 2 - (SP - 1) PSW, SP SP - 1 4 - (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 POP PSW 1 2 - PSW (SP), SP SP + 1 rp 1 4 - rpH (SP + 1), rpL (SP), SP, #word 4 - 10 SP word SP, AX 2 - 8 SP AX R R R SP SP + 2 MOVW AX, SP 2 - 8 AX SP Unconditional BR !addr16 3 6 - PC addr16 branch $addr16 2 6 - PC PC + 2 + jdisp8 AX 2 8 - PCH A, PCL X Conditional BC $addr16 2 6 - PC PC + 2 + jdisp8 if CY = 1 branch BNC $addr16 2 6 - PC PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 - PC PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 - PC PC + 2 + jdisp8 if Z = 0 Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. User's Manual U15947EJ3V1UD 515 CHAPTER 29 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 Z AC CY Note 2 Conditional BT saddr.bit, $addr16 3 8 9 PC PC + 3 + jdisp8 if (saddr.bit) = 1 branch sfr.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if sfr.bit = 1 BF BTCLR Flag Operation A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 - 9 PC PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 + n PC PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if PSW. bit = 0 [HL].bit, $addr16 3 10 11 + n saddr.bit, $addr16 4 10 12 sfr.bit, $addr16 4 - 12 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PSW.bit, $addr16 4 - 12 PC PC + 4 + jdisp8 if PSW.bit = 1 x x x then reset PSW.bit [HL].bit, $addr16 3 10 12 + n + m PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit DBNZ B, $addr16 2 6 - B B - 1, then 6 - C C -1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 10 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 CPU SEL 2 4 - RBS1, 0 n control NOP 1 2 - No Operation EI 2 - 6 IE 1 (Enable Interrupt) DI 2 - 6 IE 0 (Disable Interrupt) HALT 2 6 - Set HALT Mode STOP 2 6 - Set STOP Mode Notes 1. 2. RBn When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 516 User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET 29.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None [HL + B] First Operand A r [HL + C] ADD MOV MOV MOV MOV ADDC XCH XCH XCH XCH SUB ADD ADD ADD SUBC ADDC ADDC ADDC ADDC ADDC AND SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV MOV SUB MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD RORC ROLC SUB MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ ADD INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV PUSH MOV POP [DE] MOV [HL] MOV ROR4 ROL4 [HL + byte] MOV [HL + B] [HL + C] X MULU C DIVUW Note Except r = A User's Manual U15947EJ3V1UD 517 CHAPTER 29 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None First Operand A.bit MOV1 BT SET1 BF CLR1 BTCLR sfr.bit MOV1 BT SET1 BF CLR1 BTCLR saddr.bit MOV1 BT SET1 BF CLR1 BTCLR PSW.bit MOV1 BT SET1 BF CLR1 BTCLR [HL].bit MOV1 BT SET1 BF CLR1 BTCLR CY 518 MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 User's Manual U15947EJ3V1UD CHAPTER 29 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User's Manual U15947EJ3V1UD 519 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) Target products (expanded-specification products): Products with a rankNote E or after * Mask ROM versions for which orders were received on or after the end of May 2004 * Flash memory versions for which orders were received on or after the end of August 2004 Note The rank is indicated by the 5th digit from the left in the 3rd column (lot number) marked on the package. xxxx Lot number Year Week code code Rank Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V EVDD -0.3 to +6.5 V REGC -0.3 to +6.5 V VSS -0.3 to +0.3 V EVSS -0.3 to +0.3 -0.3 to VDD + 0.3 AVREF Input voltage VI1 V -0.3 to +0.3 AVSS VPP V Note 1 PD78F0148, 78F0148(A) only, Note 2 P00 to P06, P10 to P17, P20 to P27, P30 V -0.3 to +10.5 -0.3 to VDD + 0.3 V Note 1 V Note 1 V to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET VI2 P62, P63 N-ch open drain On-chip pull-up resistor VI3 Output voltage Analog input voltage VPP in flash programming mode (PD78F0148, 78F0148(A) only) -0.3 to +13 -0.3 to VDD + 0.3 V -0.3 to +10.5 V VO -0.3 to VDD + 0.3 VAN AVSS - 0.3 to AVREF + 0.3 Note 1 V Note 1 V and -0.3 to VDD + 0.3 Note 1 Output current, high IOH Per pin Total of P00 to P06, P40 to P47, P50 to all pins -60 mA P57, P64 to P67, P70 to P77, mA -30 mA -30 mA P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 Note 1. Must be 6.5 V or lower. (See Note 2 on the next page.) 520 -10 User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Symbol Output current, low IOL Conditions Per pin P00 to P06, P10 to P17, P30 to P33, Ratings Unit 20 mA P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 30 mA Total of P00 to P06, P40 to P47, P50 to P57, 35 mA all pins P60, P61, P64 to P67, P70 to P77, 70 mA P142 to P145 35 mA In normal operation mode -40 to +85 C In flash memory programming mode -10 to +85 PD780143, 780144, 780146, 780148, -65 to +150 P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Operating ambient TA temperature Storage temperature Tstg C 780143(A), 780144(A), 780146(A), 780148(A) PD78F0148, 78F0148(A) -40 to +125 Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.5 V) of the operating voltage range (15 s if the supply voltage is dropped by the regulator) (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.5 V) of the operating voltage range of VDD (see b in the figure below). VDD 2.5 V 0V a b VPP 2.5 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 521 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit VSS X1 X2 Parameter Conditions resonator VSS X1 MHz When the REGC 4.0 V VDD 5.5 V 2.0 12 MHz pin is connected 3.5 V VDD < 4.0 V 2.0 10 3.0 V VDD < 3.5 V 2.0 8.38 2.5 V VDD < 3.0 V 2.0 5.0 4.0 V VDD 5.5 V 2.0 8.38 MHz When the REGC 4.0 V VDD 5.5 V 2.0 12 MHz pin is connected 3.5 V VDD < 4.0 V 2.0 10 3.0 V VDD < 3.5 V 2.0 8.38 2.5 V VDD < 3.0 V 2.0 5.0 2.0 12 3.5 V VDD < 4.0 V 2.0 10 3.0 V VDD < 3.5 V 2.0 8.38 2.5 V VDD < 3.0 V 2.0 5.0 X1 input high-/low- 4.0 V VDD 5.5 V 38 500 level width (tXPH, 3.5 V VDD < 4.0 V 46 500 3.0 V VDD < 3.5 V 56 500 2.5 V VDD < 3.0 V 96 500 is connected to the Note 2 When a capacitor Oscillation Note 1 frequency (fXP) is connected to the REGC pin C1 C2 Note 2 directly to VDD X1 input frequency 4.0 V VDD 5.5 V External Note 3 Note 1 (fXP) clock X1 X2 tXPL) Notes 1. 2. 3. Unit 8.38 C2 X2 MAX. 2.0 Note 1 frequency (fXP) directly to VDD Crystal TYP. 4.0 V VDD 5.5 V When a capacitor Oscillation REGC pin C1 MIN. MHz ns Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Connect the REGC pin directly to VDD. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal oscillation clock after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time counter status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 522 User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) Internal Oscillator Characteristics (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Parameter Internal oscillator Conditions Oscillation frequency (fR) MIN. TYP. MAX. Unit 120 240 480 kHz MIN. TYP. MAX. Unit 32 32.768 35 kHz 32 38.5 kHz 12 15 s Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Crystal Recommended Circuit VSS XT2 resonator XT1 Parameter Conditions Oscillation frequency Note (fXT) Rd C4 External clock XT2 C3 XT1 XT1 input frequency Note (fXT) XT1 input high-/low-level width (tXTH, tXTL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U15947EJ3V1UD 523 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) Recommended Oscillator Constants Caution For the resonator selection of the PD780143(A), 780144(A), 780146(A), 780148(A), and 78F0148(A) and oscillator constants, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (a) PD780143, 780144, 780146, 780148 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Murata Mfg. Part Number SMD/ Lead Frequency (MHz) C1 (pF) C2 (pF) Internal (47) Internal (15) Internal (47) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) 8.00 Internal (10) Internal (15) Internal (10) Internal (15) 10.0 Internal (10) Internal (15) Internal (10) Internal (15) 12.0 Internal (10) Internal (10) CSTCC2M00G56-R0 SMD 2.00 CSTCR4M00G53-R0 CSTCR4M00G53U-R0 CSTLS4M00G53-B0 CSTLS4M00G53U-B0 CSTCR4M19G53-R0 CSTCR4M19G53U-R0 CSTLS4M19G53-B0 CSTLS4M19G53U-B0 CSTCR4M91G53-R0 CSTCR4M91G53U-R0 CSTLS4M91G53-B0 CSTLS4M91G53U-B0 CSTCR5M00G53-R0 CSTCR5M00G53U-R0 CSTLS5M00G53-B0 CSTLS5M00G53U-B0 CSTCR6M00G53-R0 CSTCR6M00G53U-R0 CSTLS6M00G53-B0 CSTLS6M00G53U-B0 CSTCE8M00G52-R0 SMD 4.00 CSTLS8M00G53-B0 CSTLS8M00G53U-B0 CSTCE10M0G52-R0 Lead CSTLS10M0G53-B0 CSTLS10M0G53U-B0 CSTCE12M0G52-R0 Lead Lead SMD 4.194 Lead SMD 4.915 Lead SMD 5.00 Lead SMD 6.00 Lead SMD SMD SMD Recommended Circuit Constants Oscillation Voltage Range When Capacitor Is Connected to Note REGC Pin MIN. MAX. (V) (V) 4.0 5.5 - - REGC Pin Is Connected Directly to VDD MIN. MAX. (V) (V) 2.5 5.5 Note When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. 524 User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) (b) PD78F0148 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Murata Mfg. Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants MIN. (V) MAX. (V) MIN. (V) MAX. (V) 4.0 5.5 2.5 5.5 - - 2.00 Internal (47) Internal (47) CSTCR4M00G55-R0 SMD 4.00 Internal (39) Internal (39) Internal (47) Internal (47) Internal (39) Internal (39) Internal (47) Internal (47) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (10) Internal (10) Internal (15) Internal (15) Internal (10) Internal (10) Internal (15) Internal (15) Internal (10) Internal (10) Lead CSTLS4M00G56U-B0 CSTCR4M19G55-R0 SMD 4.194 CSTCR4M19G55U-R0 CSTLS4M19G56-B0 Lead CSTLS4M19G56U-B0 CSTCR4M91G53-R0 SMD 4.915 CSTCR4M91G53U-R0 CSTLS4M91G53-B0 Lead CSTLS4M91G53U-B0 CSTCR5M00G53-R0 SMD 5.00 CSTCR5M00G53U-R0 CSTLS5M00G53-B0 Lead CSTLS5M00G53U-B0 CSTCR6M00G53-R0 SMD 6.00 CSTCR6M00G53U-R0 CSTLS6M00G53-B0 Lead CSTLS6M00G53U-B0 CSTCE8M00G52-R0 SMD CSTLS8M00G53-B0 Lead 8.00 CSTLS8M00G53U-B0 CSTCE10M0G52-R0 SMD CSTLS10M0G53-B0 Lead 10.0 CSTLS10M0G53U-B0 CSTCE12M0G52-R0 SMD 12.0 REGC Pin Is Connected Directly to VDD C2 (pF) SMD CSTLS4M00G56-B0 When Capacitor Is Connected to Note REGC Pin C1 (pF) CSTCC2M00G56-R0 CSTCR4M00G55U-R0 Oscillation Voltage Range Note When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User's Manual U15947EJ3V1UD 525 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (1/4) (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Output current, low Input voltage, high Symbol IOH IOL VIH1 VIH2 MAX. Unit Per pin Conditions 4.0 V VDD 5.5 V -5 mA Total of P10 to P17, P30 to P33, P120, P130, P140, P141 4.0 V VDD 5.5 V -25 mA Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 4.0 V VDD 5.5 V -25 mA All pins 2.5 V VDD < 4.0 V -10 mA 10 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 15 mA Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 4.0 V VDD 5.5 V 30 mA 4.0 V VDD 5.5 V Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 30 mA All pins 2.5 V VDD < 4.0 V 10 mA P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 2.7 V VDD 5.5 V 0.7VDD VDD V 2.5 V VDD < 2.7 V 0.8VDD VDD V 2.7 V VDD 5.5 V 0.8VDD VDD V 2.5 V VDD < 2.7 V 0.85VDD VDD V 2.7 V VDD 5.5 V 0.7AVREF AVREF V 2.5 V VDD < 2.7 V 0.8AVREF P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET P20 to P27 VIH4 P60, P61 Note P62, P63 N-ch open drain On-chip pull-up resistor VIH6 Input voltage, low VIL1 VIL2 VIL3 TYP. 4.0 V VDD 5.5 V Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 VIH3 VIH5 MIN. X1, X2, XT1, XT2 AVREF V 2.7 V VDD 5.5 V 0.7VDD VDD V 2.5 V VDD < 2.7 V 0.8VDD VDD V V 2.7 V VDD 5.5 V 0.7VDD 12 2.5 V VDD < 2.7 V 0.8VDD 12 V 2.7 V VDD 5.5 V 0.7VDD VDD V 2.5 V VDD < 2.7 V 0.8VDD VDD V 2.7 V VDD 5.5 V VDD - 0.5 VDD V 2.5 V VDD < 2.7 V VDD - 0.2 VDD V P12, P13, P15, P40 to P47, P50 to 2.7 V VDD 5.5 V P57, P64 to P67, P144, P145 2.5 V VDD < 2.7 V 0 0.3VDD V 0 0.2VDD V 2.7 V VDD 5.5 V 0 0.2VDD V 2.5 V VDD < 2.7 V 0 0.15VDD V P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET P20 to P27 Note 2.7 V VDD 5.5 V 0 0.3AVREF V 2.5 V VDD < 2.7 V 0 0.2AVREF V 0.3VDD V VIL4 P60, P61 2.7 V VDD 5.5 V 0 2.5 V VDD < 2.7 V 0 0.2VDD V VIL5 P62, P63 2.7 V VDD 5.5 V 0 0.3VDD V 2.5 V VDD < 2.7 V 0 0.2VDD V VIL6 X1, X2, XT1, XT2 2.7 V VDD 5.5 V 0 0.4 V 2.5 V VDD < 2.7 V 0 0.2 V Note When used as digital input ports, set AVREF = VDD. Remark 526 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (2/4) (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Output voltage, low Input leakage current, high Input leakage current, low Symbol Conditions MIN. TYP. MAX. Unit Total of P10 to P17, P30 to P33, P120, P130, P140, P141 IOH = -25 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA V Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 IOH = -25 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA V IOH = -100 A 2.5 V VDD < 4.0 V V Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 IOL = 30 mA 4.0 V VDD 5.5 V, IOL = 10 mA 1.3 V Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 IOL = 30 mA 4.0 V VDD 5.5 V, IOL = 10 mA 1.3 V IOL = 400 A 2.5 V VDD < 4.0 V 0.4 V VOL2 P60 to P63 4.0 V VDD 5.5 V, IOL = 15 mA 2.0 V ILIH1 VI = VDD 3 A VOH VOL1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET 3 A 20 A P62, P63 (N-ch open drain) 3 A P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET -3 A -20 A VI = AVREF P20 to P27 ILIH2 VI = VDD X1, X2 ILIH3 VI = 12 V ILIL1 VI = 0 V ILIL2 X1, X2 ILIL3 VDD - 0.5 Note 1 , XT1, XT2 Note 1 , XT1, XT2 Note 1 Note 1 -3 P62, P63 (N-ch open drain) Note 2 A Output leakage current, high ILOH VO = VDD 3 A Output leakage current, low ILOL VO = 0 V -3 A Pull-up resistance value RL VI = 0 V 10 100 k VPP supply voltage (PD78F0148, 78F0148(A) only) VPP1 In normal operation mode 0 0.2VDD V Notes 1. 2. 30 When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -45 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 527 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (3/4): PD78F0148, 78F0148(A) (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Supply Note 1 current IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 Conditions X1 crystal oscillation operating Note 2 mode X1 crystal oscillation HALT mode fXP = 12 MHz Notes 3, 7 VDD = 5.0 V 10% fXP = 10 MHz Notes 3, 7 VDD = 5.0 V 10% MIN. TYP. MAX. Unit When A/D converter is stopped 16.8 31.5 mA When A/D converter is Note 9 operating When A/D converter is stopped 17.8 33.5 mA 14.0 26.2 mA When A/D converter is Note 9 operating 15.0 28.2 mA fXP = 8.38 MHz Notes 3, 8 VDD = 5.0 V 10% When A/D converter is stopped 8.4 15.8 mA When A/D converter is Note 9 operating 9.4 17.8 mA fXP = 5 MHz Note 3 VDD = 3.0 V 10% When A/D converter is stopped 4.6 8.2 mA When A/D converter is Note 9 operating 5.2 9.4 mA fXP = 12 MHz Note 7 VDD = 5.0 V 10% When peripheral functions are stopped 2.3 fXP = 10 MHz Note 7 VDD = 5.0 V 10% When peripheral functions are stopped fXP = 8.38 MHz Note 8 VDD = 5.0 V 10% When peripheral functions are stopped fXP = 5 MHz VDD = 3.0 V 10% When peripheral functions are stopped When peripheral functions are operating 1 mA mA 4.0 mA 9.9 mA 2 mA 6.85 mA 0.44 0.88 mA When peripheral functions are operating 2.6 mA Internal oscillation operating Note 4 mode VDD = 5.0 V 10% 0.53 2.12 mA VDD = 3.0 V 10% 0.40 1.60 mA Internal oscillation Note 4 HALT mode VDD = 5.0 V 10% 0.19 0.76 mA VDD = 3.0 V 10% 0.16 0.64 mA 32.768 kHz crystal oscillation operating Notes 4, 6 mode VDD = 5.0 V 10% 130 260 VDD = 3.0 V 10% 98 196 A A 32.768 kHz crystal VDD = 5.0 V 10% oscillation HALT VDD = 3.0 V 10% Notes 4, 6 mode VDD = 5.0 V 10% STOP mode 20 40 6 12 0.1 30 When peripheral functions are operating POC: OFF, Internal oscillator: OFF POC: OFF, Internal oscillator: ON 14 58 Note 5 3.5 35.5 Note 5 POC: ON POC: ON VDD = 3.0 V 10% , Internal oscillator: OFF 17.5 63.5 POC: OFF, Internal oscillator: OFF 0.05 10 POC: OFF, Internal oscillator: ON 7.5 25 Note 5 3.5 15.5 Note 5 11 30.5 POC: ON POC: ON Notes 1. 2.0 When peripheral functions are operating 4.6 11.3 , Internal oscillator: ON , Internal oscillator: OFF , Internal oscillator: ON A A A A A A A A A A Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. 5. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0148M1, 78F0148M2, 78F0148M1(A), and 6. 78F0148M2(A). When the PD78F0148M1, 78F0148M2, 78F0148M1(A), and 78F0148M2(A) (including LVIE = 0) are selected and internal oscillator is stopped. Peripheral operation current is not included. 528 7. 8. When the REGC pin is connected directly to VDD. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). 9. Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (4/4): PD780143, 780144, 780146, 780148, 780143(A), 780144(A), 780146(A), 780148(A) (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Supply Note 1 current IDD1 Conditions X1 crystal oscillation operating Note 2 mode fXP = 12 MHz Notes 3, 7 VDD = 5.0 V 10% fXP = 10 MHz Notes 3, 7 VDD = 5.0 V 10% fXP = 8.38 MHz Notes 3, 8 VDD = 5.0 V 10% fXP = 5 MHz Note 3 VDD = 3.0 V 10% IDD2 X1 crystal oscillation HALT mode mA 20.5 mA When A/D converter is stopped 7.7 15.4 mA When A/D converter is Note 9 operating 8.7 17.4 mA When A/D converter is stopped 4.3 9.5 mA When A/D converter is Note 9 operating 5.3 11.5 mA 2.2 4.4 mA 2.8 5.6 mA fXP = 12 MHz Note 7 VDD = 5.0 V 10% When peripheral functions are stopped 2.0 4.0 mA 9.4 mA fXP = 10 MHz Note 7 VDD = 5.0 V 10% When peripheral functions are stopped fXP = 8.38 MHz Note 8 VDD = 5.0 V 10% When peripheral functions are stopped fXP = 5 MHz VDD = 3.0 V 10% When peripheral functions are stopped IDD4 Internal oscillation Note 4 HALT mode IDD7 18.5 10.3 When A/D converter is stopped Internal oscillation VDD = 5.0 V 10% Note 4 operating mode VDD = 3.0 V 10% IDD6 9.3 When A/D converter is Note 9 operating When A/D converter is Note 9 operating IDD3 IDD5 MIN. TYP. MAX. Unit When A/D converter is stopped When peripheral functions are operating When peripheral functions are operating 0.85 When peripheral functions are operating 0.33 3.4 mA 8.1 mA 1.71 mA 5.59 mA 0.66 mA 2 mA 0.28 1.12 mA When peripheral functions are operating 0.17 0.68 mA VDD = 5.0 V 10% 70 280 VDD = 3.0 V 10% 35 140 32.768 kHz crystal VDD = 5.0 V 10% oscillation VDD = 3.0 V 10% operating Notes 4, 6 mode 38 76 17 34 A A A A 32.768 kHz crystal VDD = 5.0 V 10% oscillation HALT VDD = 3.0 V 10% Notes 4, 6 mode 20 40 6 12 STOP mode VDD = 5.0 V 10% POC: OFF, Internal oscillator: OFF 0.1 30 POC: OFF, Internal oscillator: ON 14 58 Note 5 3.5 35.5 Note 5 17.5 63.5 POC: ON POC: ON VDD = 3.0 V 10% , Internal oscillator: OFF , Internal oscillator: ON POC: OFF, Internal oscillator: OFF 0.05 10 POC: OFF, Internal oscillator: ON 7.5 25 Note 5 3.5 15.5 Note 5 11 30.5 POC: ON POC: ON Notes 1. 1.7 , Internal oscillator: OFF , Internal oscillator: ON A A A A A A A A A A Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. When X1 oscillator is stopped. 5. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. 6. When POC-OFF (including LVIE = 0) is selected by a mask option and internal oscillator is stopped. Peripheral operation current is not included. 7. 8. When the REGC pin is connected directly to VDD. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). 9. Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD 529 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Instruction cycle (minimum TCY instruction execution time) Conditions Note 4 , tTIH0, Note 1 4.0 V VDD 5.5 V 0.238 16 s input Note 2 4.0 V VDD 5.5 V 0.166 16 s clock clock 0.2 16 s 3.0 V VDD < 3.5 V Note 3 0.238 16 s 2.5 V VDD < 3.0 V Note 3 0.4 16 s 3.5 V VDD < 4.0 V 4.0 V VDD 5.5 V 4.17 8.33 33.3 s 114 122 125 s s 2/fsam + input high-level width, tTIL0 low-level width Unit X1 Subsystem clock operation TI011 MAX. system Internal oscillation clock TI000, TI010, TI001 TYP. Main operation Note 4 MIN. 0.1 2.7 V VDD < 4.0 V Note 5 s 2/fsam + 0.2 2.5 V VDD < 2.7 V Note 5 s 2/fsam + Note 5 0.5 TI50, TI51 input frequency fTI5 4.0 V VDD 5.5 V 10 MHz 2.7 V VDD < 4.0 V 5 MHz 2.5 V VDD < 2.7 V 2.5 MHz TI50, TI51 input high-level width, tTIH5, 4.0 V VDD 5.5 V 50 ns low-level width 2.7 V VDD < 4.0 V 100 ns 2.5 V VDD < 2.7 V 200 ns tTIL5 Interrupt input high-level width, tINTH, 2.7 V VDD 5.5 V 1 s low-level width tINTL 2.5 V VDD < 2.7 V 2 s Key return input low-level width tKR 4.0 V VDD 5.5 V 50 ns 2.7 V VDD < 4.0 V 100 ns 2.5 V VDD < 2.7 V RESET low-level width Notes 1. tRSL 200 ns 2.7 V VDD 5.5 V 10 s 2.5 V VDD < 2.7 V 20 s When the REGC pin is connected to VSS via a capacitor (1 F: recommended). 2. When the REGC pin is connected directly to VDD. 3. The following characteristics are applied when P62 or P63 input is read at VDD lower than 3.5 V. Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions MIN. Main system X1 input Note 2 3.3 V VDD < 3.5 V 0.238 clock clock 2.7 V VDD < 3.3 V 0.4 operation 2.5 V VDD < 2.7 V 0.8 TYP. MAX. Unit 16 s 16 s 16 s 4. PD780146, 780148, 78F0148, 780146(A), 780148(A), and 78F0148(A) only. 5. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. 530 User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) (a) When REGC pin is connected to VSS via capacitor (1 F: recommended) 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] (b) When REGC pin is connected directly to VDD 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.166 0.1 0 1.0 2.0 2.5 3.0 3.5 4.0 5.0 5.5 6.0 Supply voltage VDD [V] User's Manual U15947EJ3V1UD 531 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) (2) Read/write operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1/2) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 20 ns Address hold time tADH 6 ns Data input time from address tADD1 (2 + 2n)tCY - 54 ns tADD2 (3 + 2n)tCY - 60 ns Address output time from RD tRDAD 100 ns Data input time from RD tRDD1 (2 + 2n)tCY - 87 ns tRDD2 (3 + 2n)tCY - 93 ns 0 Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY - 33 ns tRDL2 (2.5 + 2n)tCY - 33 ns Input time from RD to WAIT tRDWT1 tCY - 43 ns ns tRDWT2 tCY - 43 Input time from WR to WAIT tWRWT tCY - 25 ns WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 6 ns WR low-level width tWRL1 (1.5 + 2n)tCY - 15 ns Delay time from ASTB to RD tASTRD 6 ns Delay time from ASTB to WR tASTWR 2tCY - 15 ns Delay time from RD to ASTB at tRDAST 0.8tCY - 15 1.2tCY ns tRDADH 0.8tCY - 15 1.2tCY + 30 ns Write data output time from RD tRDWD 40 Write data output time from WR tWRWD 10 60 ns Address hold time from WR tWRADH 0.8tCY - 15 1.2tCY + 30 ns Delay time from WAIT to RD tWTRD 0.8tCY 2.5tCY + 25 ns Delay time from WAIT to WR tWTWR 0.8tCY 2.5tCY + 25 ns external fetch Address hold time from RD at external fetch ns Caution TCY can only be used at 0.238 s (MIN). Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) 532 User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) (2) Read/write operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 30 ns Address hold time tADH 10 ns Input time from address to data tADD1 (2 + 2n)tCY - 108 ns tADD2 (3 + 2n)tCY - 120 ns Output time from RD to address tRDAD 200 ns Input time from RD to data tRDD1 (2 + 2n)tCY - 148 ns tRDD2 (3 + 2n)tCY - 162 ns 0 Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY - 40 ns tRDL2 (2.5 + 2n)tCY - 40 ns Input time from RD to WAIT tRDWT1 tCY - 75 ns tRDWT2 tCY - 60 ns Input time from WR to WAIT tWRWT tCY - 50 ns WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 10 ns WR low-level width tWRL1 (1.5 + 2n)tCY - 30 ns Delay time from ASTB to RD tASTRD 10 ns Delay time from ASTB to WR tASTWR 2tCY - 30 ns Delay time from RD to ASTB at tRDAST 0.8tCY - 30 1.2tCY ns tRDADH 0.8tCY - 30 1.2tCY + 60 ns Write data output time from RD tRDWD 40 Write data output time from WR tWRWD 20 120 ns Hold time from WR to address tWRADH 0.8tCY - 30 1.2tCY + 60 ns Delay time from WAIT to RD tWTRD 0.5tCY 2.5tCY + 50 ns Delay time from WAIT to WR tWTWR 0.5tCY 2.5tCY + 50 ns external fetch Hold time from RD to address at external fetch ns Caution TCY can only be used at 0.4 s (MIN). Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) User's Manual U15947EJ3V1UD 533 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) (3) Serial interface (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 312.5 kbps MAX. Unit 312.5 kbps MAX. Unit (b) UART mode (UART0, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width SI1n setup time (to SCK1n) Symbol MIN. TYP. 4.0 V VDD 5.5 V 200 ns 3.3 V VDD < 4.0 V 240 ns 2.7 V VDD < 3.3 V 400 ns 2.5 V VDD < 2.7 V 800 ns tKH1, 2.7 V VDD 5.5 V tKCY1/2 - 10 ns tKL1 2.5 V VDD < 2.7 V tKCY1/2 - 50 ns tSIK1 2.7 V VDD 5.5 V 30 ns 2.5 V VDD < 2.7 V 70 ns 2.7 V VDD 5.5 V 30 ns 2.5 V VDD < 2.7 V 70 tKCY1 SI1n hold time (from SCK1n) tKSI1 Delay time from SCK1n to Conditions tKSO1 Note C = 100 pF SO1n output ns 2.7 V VDD 5.5 V 30 ns 2.5 V VDD < 2.7 V 120 ns MAX. Unit Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY2 Conditions MIN. TYP. 2.7 V VDD 5.5 V 400 ns 2.5 V VDD < 2.7 V 800 ns tKCY2/2 ns 80 ns 50 ns tKH2, tKL2 SI1n setup time (to SCK1n) tSIK2 SI1n hold time (from SCK1n) tKSI2 Delay time from SCK1n to tKSO2 Note C = 100 pF SO1n output Note C is the load capacitance of the SO1n output line. Remark 534 PD780143, 780144, 780143(A), 780144(A) n = 0, 1: PD780146, 780148, 78F0148, 780146(A), 780148(A), 78F0148(A) n = 0: User's Manual U15947EJ3V1UD 120 ns CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tTH3, tTL3 SIA0 setup time (to SCKA0) tSIK3 SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to SOA0 tKSO3 Conditions tSBD Strobe signal high-level width tSBW Busy signal setup time (to busy TYP. MAX. Unit 4.0 V VDD 5.5 V 600 ns 2.7 V VDD < 4.0 V 1200 ns 2.5 V VDD < 2.7 V 2400 ns 4.0 V VDD 5.5 V tKCY3/2 - 50 ns 2.7 V VDD < 4.0 V tKCY3/2 - 100 ns 2.5 V VDD < 2.7 V tKCY3/2 - 200 ns 100 ns 300 ns Note C = 100 pF output Time from SCKA0 to STB0 MIN. 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns 2.5 V VDD < 2.7 V 600 ns tKCY3/2 - 100 ns 4.0 V VDD 5.5 V tKCY3 - 30 ns 2.7 V VDD < 4.0 V tKCY3 - 60 ns 2.5 V VDD < 2.7 V tKCY3 - 120 ns 100 ns tBYS signal detection timing) Busy signal hold time (from busy tBYH signal detection timing) 4.0 V VDD 5.5 V 100 ns 2.7 V VDD < 4.0 V 150 ns 2.5 V VDD < 2.7 V 300 ns Time from busy inactive to SCKA0 tSPS 2tKCY3 ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY4 tKH4, tKL4 SIA0 setup time (to SCKA0) tSIK4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to SOA0 tKSO4 Conditions tR4, tF4 TYP. MAX. Unit 600 ns 2.7 V VDD < 4.0 V 1200 ns 2.5 V VDD < 2.7 V 2400 ns 4.0 V VDD 5.5 V 300 ns 2.7 V VDD < 4.0 V 600 ns 2.5 V VDD < 2.7 V 1200 ns 100 ns 300 ns Note C = 100 pF output SCKA0 rise/fall time MIN. 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns 2.5 V VDD < 2.7 V 600 ns 120 ns 1000 ns When external device expansion function is used When external device expansion function is not used Note C is the load capacitance of the SOA0 output line. User's Manual U15947EJ3V1UD 535 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fXP tXPL tXPH VIH6 (MIN.) VIL6 (MAX.) X1 input 1/fXT tXTL tXTH VIH6 (MIN.) XT1 input VIL6 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Note PD780146, 780148, 78F0148, 780146(A), 780148(A), and 78F0148(A) only. 536 User's Manual U15947EJ3V1UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) RESET Input Timing tRSL RESET Read/Write Operation External fetch (no wait): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS tADH Instruction code tRDAD tRDD1 tRDADH tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External fetch (wait insertion): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS tADH tRDAD Instruction code tRDADH tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL User's Manual U15947EJ3V1UD tWTRD 537 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) External data access (no wait): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Lower 8-bit address tADS tADH Hi-Z tRDAD tRDD2 tASTH Hi-Z Write data Read data tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRADH tWRWD WR tASTWR tWRL1 External data access (wait insertion): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Lower 8-bit address tADS tADH tASTH Hi-Z Read data Hi-Z Write data tRDAD tRDH tRDD2 ASTB tASTRD RD tRDWD tRDL2 tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTL tWTRD tWTL tWRWT 538 User's Manual U15947EJ3V1UD tWTWR CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0: PD780143, 780144, 780143(A), 780144(A) n = 0, 1: PD780146, 780148, 78F0148, 780146(A), 780148(A), 78F0148(A) User's Manual U15947EJ3V1UD 539 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 D2 D2 D1 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYS 10+nNote tBYH BUSY0 (active-high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. 540 User's Manual U15947EJ3V1UD 1 tSPS CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) A/D Converter Characteristics (TA = -40 to +85C, 2.5 V VDD = EVDD 5.5 V, 2.5 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.0 V AVREF 5.5 V 0.2 0.4 %FSR 2.7 V AVREF < 4.0 V 0.3 0.6 %FSR 2.5 V AVREF < 2.7 V 0.6 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Note 1 Integral non-linearity error Differential non-linearity error Analog input voltage Note 1 4.0 V AVREF 5.5 V 14 100 s 2.7 V AVREF < 4.0 V 17 100 s 2.5 V AVREF < 2.7 V 48 100 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.5 V AVREF < 2.7 V 1.2 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.5 V AVREF < 2.7 V 1.2 %FSR 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB 2.5 V AVREF < 2.7 V 8.5 LSB 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB 2.5 V AVREF < 2.7 V 3.5 LSB AVREF V VIAN AVSS Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage VPOC0 Power supply rise time Response delay time 1 Note 3 Conditions Mask option = 3.5 V Note 1 Note 2 MIN. TYP. MAX. Unit 3.3 3.5 3.7 V 2.7 2.85 3.0 V VPOC1 Mask option = 2.85 V tPTH VDD: 0 V 2.7 V 0.0015 ms VDD: 0 V 3.3 V 0.002 ms tPTHD When power supply rises, after reaching 3.0 ms 1.0 ms detection voltage (MAX.) Response delay time 2 Minimum pulse width Note 4 tPD When VDD falls tPW 0.2 ms Notes 1. When flash memory version PD78F0148M5, 78F0148M6, 78F0148M5(A), or 78F0148M6(A) is used 2. When flash memory version PD78F0148M3, 78F0148M4, 78F0148M3(A), or 78F0148M4(A) is used 3. Time required from voltage detection to reset release. 4. Time required from voltage detection to internal reset output. User's Manual U15947EJ3V1UD 541 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time LVI Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage Note 1 Response time TYP. MAX. Unit 4.1 4.3 4.5 V VLVI1 3.9 4.1 4.3 V VLVI2 3.7 3.9 4.1 V VLVI3 3.5 3.7 3.9 V VLVI4 3.3 3.5 3.7 V VLVI5 3.15 3.3 3.45 V VLVI6 2.95 3.1 3.25 V VLVI7 2.7 2.85 3.0 V 0.2 2.0 ms tLW Reference voltage stabilization wait time Operation stabilization wait time 2. Conditions tLD Minimum pulse width Notes 1. MIN. VLVI0 Note 3 Note 2 0.2 ms tLWAIT0 0.5 2.0 ms tLWAIT1 0.1 0.2 ms Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by the POC mask option (when flash memory version PD78F0148M1, 78F0148M2, 78F0148M1(A), or 78F0148M2(A) is used). 3. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 2. VPOCn < VLVIm (n = 0 and 1, m = 0 to 7) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT0 tLWAIT1 LVIE 1 LVION 1 542 User's Manual U15947EJ3V1UD tLD Time CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention supply voltage VDDDR Conditions When POC-OFF is selected by mask option Release signal set time MIN. TYP. 1.6 MAX. Unit 5.5 V Note tSREL s 0 Note When flash memory version PD78F0148M1, 78F0148M2, 78F0148M1(A), or 78F0148M2(A) is used Flash Memory Programming Characteristics: PD78F0148, 78F0148(A) (TA = +10 to +60C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Write erase characteristics Parameter Symbol Conditions VPP supply voltage VPP2 During flash memory programming VDD supply current IDD When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V VPP supply current IPP VPP = VPP2 Step erase time Note 1 Ter Note 2 Overall erase time Tera Note 3 Twb Writeback time Number of writebacks per 1 writeback command Cwb MIN. TYP. MAX. Unit 9.7 10.0 10.3 V 37 mA 0.199 0.2 When step erase time = 0.2 s 49.4 50 When writeback time = 50 ms 100 mA 0.201 s 20 s/chip 50.6 ms 60 Times 16 Times 52 s 520 s 20 Times/ Note 4 Number of erases/writebacks Note 5 Step write time Overall write time per word Cerwb Twr Note 6 Twrw 48 When step write time = 50 s (1 word = 1 48 50 byte) Note 7 Number of rewrites per chip Cerwr 1 erase + 1 write after erase = 1 rewrite area Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time before erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 50 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries 5. must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. 6. The actual write time per word is 100 s longer. The internal verify time during or after a write is not 7. included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. User's Manual U15947EJ3V1UD 543 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit tDP 10 s Release time from VPP to RESET tPR 10 s VPP pulse input start time from RESET tRP 2 ms VPP pulse high-/low-level width tPW 8 s VPP pulse input end time from RESET tRPE VPP pulse low-level input voltage VPPL 0.8VDD VPP pulse high-level input voltage VPPH 9.7 Set time from VDD to VPP Flash Write Mode Setting Timing VDD VDD 0V tDP tRP tPW VPPH VPP VPPL tPW 0V tPR tRPE VDD RESET (input) 0V 544 User's Manual U15947EJ3V1UD 10.0 14 ms 1.2VDD V 10.3 V CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) Target products (conventional products): Products with rankNote I or K * Mask ROM versions for which orders were received before the end of May 2004 * Flash memory versions for which orders were received before the end of August 2004 Note The rank is indicated by the 5th digit from the left in the 3rd column (lot number) marked on the package. xxxx Lot number Year Week code code Rank Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V EVDD -0.3 to +6.5 V REGC -0.3 to +6.5 V VSS -0.3 to +0.3 V EVSS -0.3 to +0.3 -0.3 to VDD + 0.3 AVREF Input voltage VI1 V -0.3 to +0.3 AVSS VPP V Note 1 PD78F0148, 78F0148(A) only, Note 2 P00 to P06, P10 to P17, P20 to P27, P30 V -0.3 to +10.5 -0.3 to VDD + 0.3 V Note 1 V Note 1 V to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET VI2 P62, P63 N-ch open drain On-chip pull-up resistor VI3 Output voltage Analog input voltage VPP in flash programming mode (PD78F0148, 78F0148(A) only) -0.3 to +13 -0.3 to VDD + 0.3 V -0.3 to +10.5 V VO -0.3 to VDD + 0.3 VAN AVSS - 0.3 to AVREF + 0.3 Note 1 V Note 1 V and -0.3 to VDD + 0.3 Note 1 Output current, high IOH Per pin Total of P00 to P06, P40 to P47, P50 to all pins -60 mA P57, P64 to P67, P70 to P77, -10 mA -30 mA -30 mA P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 Note 1. Must be 6.5 V or lower. (See Note 2 on the next page.) User's Manual U15947EJ3V1UD 545 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Symbol Output current, low IOL Conditions Per pin P00 to P06, P10 to P17, P30 to P33, Ratings Unit 20 mA P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 30 mA Total of P00 to P06, P40 to P47, P50 to P57, 35 mA all pins P60, P61, P64 to P67, P70 to P77, 70 mA P142 to P145 35 mA In normal operation mode -40 to +85 C In flash memory programming mode -10 to +85 PD780143, 780144, 780146, 780148, -65 to +150 P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Operating ambient TA temperature Storage temperature Tstg C 780143(A), 780144(A), 780146(A), 780148(A) PD78F0148, 78F0148(A) -40 to +125 Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (15 s if the supply voltage is dropped by the regulator) (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below). VDD 2.7 V 0V a b VPP 2.7 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 546 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit VSS X1 X2 Parameter Conditions resonator VSS X1 MHz When the REGC 4.0 V VDD 5.5 V 2.0 10 MHz pin is connected 3.3 V VDD < 4.0 V 2.0 8.38 2.7 V VDD < 3.3 V 2.0 5.0 4.0 V VDD < 5.5 V 2.0 8.38 MHz When the REGC 4.0 V VDD 5.5 V 2.0 10 MHz pin is connected 3.3 V VDD < 4.0 V 2.0 8.38 2.7 V VDD < 3.3 V 2.0 5.0 4.0 V VDD 5.5 V 2.0 10 3.3 V VDD < 4.0 V 2.0 8.38 2.7 V VDD < 3.3 V 2.0 5.0 X1 input high- 4.0 V VDD 5.5 V 46 500 /low-level width 3.3 V VDD < 4.0 V 56 500 2.7 V VDD < 3.3 V 96 500 is connected to Note 2 When a capacitor Oscillation Note 1 frequency (fXP) is connected to the REGC pin C1 C2 Note 2 directly to VDD External X1 input Note 3 clock Note 1 X1 X2 frequency (fXP) (tXPH, tXPL) Notes 1. 2. 3. Unit 8.38 C2 X2 MAX. 2.0 Note 1 frequency (fXP) directly to VDD Crystal TYP. 4.0 V VDD < 5.5 V When a capacitor Oscillation the REGC pin C1 MIN. MHz ns Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Connect the REGC pin directly to VDD. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal oscillation clock after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time counter status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. User's Manual U15947EJ3V1UD 547 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) Internal Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Parameter Internal oscillator Conditions Oscillation frequency (fR) MIN. TYP. MAX. Unit 120 240 480 kHz MIN. TYP. MAX. Unit 32 32.768 35 kHz 32 38.5 kHz 12 15 s Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Crystal Recommended Circuit VSS XT2 resonator XT1 Parameter Conditions Oscillation frequency Note (fXT) Rd C4 External clock XT2 C3 XT1 XT1 input frequency Note (fXT) XT1 input high-/low-level width (tXTH, tXTL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 548 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) Recommended Oscillator Constants Caution For the resonator selection of the PD780143(A), 780144(A), 780146(A), 780148(A), and 78F0148(A) and oscillator constants, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (a) PD780143, 780144, 780146, 780148 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Murata Mfg. Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants C2 (pF) MIN. (V) MAX. (V) MIN. (V) MAX. (V) 4.0 5.5 2.7 5.5 - - SMD 2.00 Internal (47) Internal (47) CSTCR4M00G53-R0 SMD 4.00 Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (10) Internal (10) Internal (15) Internal (15) Internal (10) Internal (10) Internal (15) Internal (15) CSTLS4M00G53-B0 Lead CSTLS4M00G53U-B0 CSTCR4M19G53-R0 SMD 4.194 CSTCR4M19G53U-R0 CSTLS4M19G53-B0 Lead CSTLS4M19G53U-B0 CSTCR4M91G53-R0 SMD 4.915 CSTCR4M91G53U-R0 CSTLS4M91G53-B0 Lead CSTLS4M91G53U-B0 CSTCR5M00G53-R0 SMD 5.00 CSTCR5M00G53U-R0 CSTLS5M00G53-B0 Lead CSTLS5M00G53U-B0 CSTCR6M00G53-R0 SMD 6.00 CSTCR6M00G53U-R0 CSTLS6M00G53-B0 Lead CSTLS6M00G53U-B0 CSTCE8M00G52-R0 SMD CSTLS8M00G53-B0 Lead 8.00 CSTLS8M00G53U-B0 CSTCE10M0G52-R0 SMD CSTLS10M0G53-B0 Lead CSTLS10M0G53U-B0 10.0 REGC Pin Is Connected Directly to VDD C1 (pF) CSTCC2M00G56-R0 CSTCR4M00G53U-R0 Oscillation Voltage Range When Capacitor Is Connected to Note REGC Pin Note When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User's Manual U15947EJ3V1UD 549 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) (b) PD78F0148 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Murata Mfg. Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants MIN. (V) MAX. (V) MIN. (V) MAX. (V) 4.0 5.5 2.7 5.5 - - 2.00 Internal (47) Internal (47) CSTCR4M00G55-R0 SMD 4.00 Internal (39) Internal (39) Internal (47) Internal (47) Internal (39) Internal (39) Internal (47) Internal (47) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (10) Internal (10) Internal (15) Internal (15) Internal (10) Internal (10) Internal (15) Internal (15) Lead CSTLS4M00G56U-B0 CSTCR4M19G55-R0 SMD 4.194 CSTCR4M19G55U-R0 CSTLS4M19G56-B0 Lead CSTLS4M19G56U-B0 CSTCR4M91G53-R0 SMD 4.915 CSTCR4M91G53U-R0 CSTLS4M91G53-B0 Lead CSTLS4M91G53U-B0 CSTCR5M00G53-R0 SMD 5.00 CSTCR5M00G53U-R0 CSTLS5M00G53-B0 Lead CSTLS5M00G53U-B0 CSTCR6M00G53-R0 SMD 6.00 CSTCR6M00G53U-R0 CSTLS6M00G53-B0 Lead CSTLS6M00G53U-B0 CSTCE8M00G52-R0 SMD CSTLS8M00G53-B0 Lead 8.00 CSTLS8M00G53U-B0 CSTCE10M0G52-R0 SMD CSTLS10M0G53-B0 Lead CSTLS10M0G53U-B0 10.0 REGC Pin Is Connected Directly to VDD C2 (pF) SMD CSTLS4M00G56-B0 When Capacitor Is Connected to Note REGC Pin C1 (pF) CSTCC2M00G56-R0 CSTCR4M00G55U-R0 Oscillation Voltage Range Note When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. 550 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) DC Characteristics (1/4) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Conditions MIN. TYP. MAX. Unit Per pin 4.0 V VDD 5.5 V -5 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V -25 mA 4.0 V VDD 5.5 V -25 mA All pins 2.7 V VDD < 4.0 V -10 mA Per pin for P00 to P06, P10 4.0 V VDD 5.5 V 10 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 15 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V 30 mA 4.0 V VDD 5.5 V 30 mA 2.7 V VDD < 4.0 V 10 mA 0.7VDD VDD V 0.8VDD VDD V 0.7AVREF AVREF V 0.7VDD VDD V P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 Output current, low IOL to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 All pins Input voltage, high VIH1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET VIH3 P20 to P27 VIH4 P60, P61 VIH5 P62, P63 Note N-ch open drain 0.7VDD 12 V On-chip pull-up resistor 0.7VDD VDD V VDD - 0.5 VDD V 0 0.3VDD V 0 0.2VDD V 0 0.3AVREF V (mask ROM version only) Input voltage, low VIH6 X1, X2, XT1, XT2 VIL1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note VIL3 P20 to P27 VIL4 P60, P61 0 0.3VDD V VIL5 P62, P63 0 0.3VDD V VIL6 X1, X2, XT1, XT2 0 0.4 V Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 551 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) DC Characteristics (2/4) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Output voltage, low Input leakage current, high Input leakage current, low Symbol Conditions MIN. TYP. MAX. Unit Total of P10 to P17, P30 to P33, P120, P130, P140, P141 IOH = -25 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA V Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 IOH = -25 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA V IOH = -100 A 2.7 V VDD < 4.0 V V Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 IOL = 30 mA 4.0 V VDD 5.5 V, IOL = 10 mA 1.3 V Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 IOL = 30 mA 4.0 V VDD 5.5 V, IOL = 10 mA 1.3 V IOL = 400 A 2.7 V VDD < 4.0 V 0.4 V VOL2 P60 to P63 4.0 V VDD 5.5 V, IOL = 15 mA 2.0 V ILIH1 VI = VDD P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET 3 A VOH VOL1 3 A 20 A P62, P63 (N-ch open drain) 3 A P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET -3 A -20 A VI = AVREF P20 to P27 ILIH2 VI = VDD X1, X2 ILIH3 VI = 12 V ILIL1 VI = 0 V ILIL2 X1, X2 ILIL3 VDD - 0.5 Note 1 , XT1, XT2 Note 1 , XT1, XT2 Note 1 Note 1 -3 P62, P63 (N-ch open drain) Note 2 A Output leakage current, high ILOH VO = VDD 3 A Output leakage current, low ILOL VO = 0 V -3 A Pull-up resistance value RL VI = 0 V 10 100 k VPP supply voltage (PD78F0148, 78F0148(A) only) VPP1 In normal operation mode 0 0.2VDD V Notes 1. 2. 30 When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -45 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remark 552 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) DC Characteristics (3/4): PD78F0148, 78F0148(A) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Supply Note 1 current IDD1 Conditions X1 crystal oscillation operating Note 2 mode fXP = 10 MHz Notes 3, 7 VDD = 5.0 V 10% When A/D converter is stopped 14.0 26.2 mA When A/D converter is Note 9 operating 15.0 28.2 mA When A/D converter is stopped 8.4 15.8 mA When A/D converter is Note 9 operating 9.4 17.8 mA When A/D converter is stopped 4.6 8.2 mA When A/D converter is Note 9 operating 5.2 9.4 mA fXP = 10 MHz Note 7 VDD = 5.0 V 10% When peripheral functions are stopped 2.0 fXP = 8.38 MHz Note 8 VDD = 5.0 V 10% When peripheral functions are stopped fXP = 5 MHz VDD = 3.0 V 10% When peripheral functions are stopped fXP = 8.38 MHz Notes 3, 8 VDD = 5.0 V 10% fXP = 5 MHz Note 3 VDD = 3.0 V 10% IDD2 IDD3 IDD4 IDD5 IDD6 X1 crystal oscillation HALT mode MIN. TYP. MAX. Unit When peripheral functions are operating When peripheral functions are operating 0.44 When peripheral functions are operating mA mA 2 mA 6.85 mA 0.88 mA 2.6 mA Internal oscillation operating Note 4 mode VDD = 5.0 V 10% 0.53 2.12 mA VDD = 3.0 V 10% 0.40 1.60 mA 32.768 kHz crystal oscillation operating Notes 4, 6 mode VDD = 5.0 V 10% 130 260 A VDD = 3.0 V 10% 98 196 A 32.768 kHz crystal VDD = 5.0 V 10% oscillation HALT VDD = 3.0 V 10% Notes 4, 6 mode 20 40 A 6 12 A POC: OFF, Internal oscillator: OFF 0.1 30 A POC: OFF, Internal oscillator: ON STOP mode VDD = 5.0 V 10% 14 58 A Note 5 3.5 35.5 A Note 5 17.5 63.5 A POC: OFF, Internal oscillator: OFF 0.05 10 A POC: OFF, Internal oscillator: ON POC: ON POC: ON VDD = 3.0 V 10% , Internal oscillator: OFF , Internal oscillator: ON 7.5 25 A Note 5 3.5 15.5 A Note 5 11 30.5 A POC: ON POC: ON Notes 1. 1 4.0 9.9 , Internal oscillator: OFF , Internal oscillator: ON Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. 5. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0148M1, 78F0148M2, 78F0148M1(A), and 6. 78F0148M2(A). When the PD78F0148M1, 78F0148M2, 78F0148M1(A), and 78F0148M2(A) (including LVIE = 0) are selected and internal oscillator is stopped. Peripheral operation current is not included. 7. 8. When the REGC pin is connected directly to VDD. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). 9. Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD 553 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) DC Characteristics (4/4): PD780143, 780144, 780146, 780148, 780143(A), 780144(A), 780146(A), 780148(A) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Supply IDD1 current Note 1 Conditions fXP = 10 MHz Notes 3, 7 VDD = 5.0 V 10% X1 crystal oscillation operating mode MIN. TYP. MAX. Unit When A/D converter is stopped 7.7 15.4 mA When A/D converter is 8.7 17.4 mA When A/D converter is stopped 4.3 9.5 mA When A/D converter is 5.3 11.5 mA When A/D converter is stopped 2.2 4.4 mA When A/D converter is 2.8 5.6 mA 1.7 3.4 mA 8.1 mA 1.71 mA 5.59 mA 0.66 mA 2 mA Note 9 operating Note 2 fXP = 8.38 MHz Notes 3, 8 VDD = 5.0 V 10% Note 9 operating fXP = 5 MHz Note 3 VDD = 3.0 V 10% Note 9 operating IDD2 X1 crystal oscillation HALT mode IDD3 IDD5 fXP = 8.38 MHz Note 8 VDD = 5.0 V 10% When peripheral functions are stopped fXP = 5 MHz VDD = 3.0 V 10% When peripheral functions are stopped When peripheral functions are operating When peripheral functions are operating 0.33 When peripheral functions are operating 0.28 1.12 mA VDD = 3.0 V 10% 0.17 0.68 mA 32.768 kHz crystal VDD = 5.0 V 10% 38 76 A oscillation operating VDD = 3.0 V 10% Notes 4, 6 mode 17 34 A 32.768 kHz crystal VDD = 5.0 V 10% 20 40 A oscillation HALT 6 12 A POC: OFF, Internal oscillator: OFF 0.1 30 A POC: OFF, Internal oscillator: ON Notes 4, 6 STOP mode VDD = 3.0 V 10% VDD = 5.0 V 10% 14 58 A Note 5 3.5 35.5 A Note 5 17.5 63.5 A POC: OFF, Internal oscillator: OFF 0.05 10 A POC: OFF, Internal oscillator: ON POC: ON POC: ON VDD = 3.0 V 10% , Internal oscillator: OFF , Internal oscillator: ON 7.5 25 A Note 5 3.5 15.5 A Note 5 11 30.5 A POC: ON POC: ON Notes 1. 0.85 VDD = 5.0 V 10% mode IDD6 When peripheral functions are stopped operating mode Internal oscillation Note 4 IDD4 fXP = 10 MHz Note 7 VDD = 5.0 V 10% , Internal oscillator: OFF , Internal oscillator: ON Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. When X1 oscillator is stopped. 5. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. 6. When POC-OFF (including LVIE = 0) is selected by a mask option and internal oscillator is stopped. Peripheral operation current is not included. 554 7. 8. When the REGC pin is connected directly to VDD. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). 9. Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Instruction cycle (minimum TCY instruction execution time) Conditions MIN. X1 input Note 1 4.0 V VDD 5.5 V 0.238 16 s clock Note 2 4.0 V VDD 5.5 V 16 s 3.3 V VDD < 4.0 V 0.238 16 s 2.7 V VDD < 3.3 V 16 s Internal oscillation clock Subsystem clock operation Note 3 TI011 , tTIH0, 4.0 V VDD 5.5 V input high-level width, tTIL0 low-level width 0.2 0.4 4.17 8.33 16.67 s 114 122 125 s 0.1 2.7 V VDD < 4.0 V fTI5 s 2/fsam + Note 4 s 2/fsam + 0.2 TI50, TI51 input frequency Unit system operation TI000, TI010, TI001 MAX. Main clock Note 3 TYP. Note 4 4.0 V VDD 5.5 V 10 MHz 2.7 V VDD < 4.0 V 5 MHz TI50, TI51 input high-level width, tTIH5, 4.0 V VDD 5.5 V 50 ns low-level width tTIL5 2.7 V VDD < 4.0 V 100 ns Interrupt input high-level width, tINTH, 1 s low-level width tINTL Key return input low-level width tKR 4.0 V VDD 5.5 V 50 ns 2.7 V VDD < 4.0 V 100 ns 10 s RESET low-level width Notes 1. 2. 3. 4. tRSL When the REGC pin is connected to VSS via a capacitor (1 F: recommended). When the REGC pin is connected directly to VDD. PD780146, 780148, 78F0148, 780146(A), 780148(A), and 78F0148(A) only. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. User's Manual U15947EJ3V1UD 555 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) (a) When REGC pin is connected to VSS via capacitor (1 F: recommended) 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] (b) When REGC pin is connected directly to VDD 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 2.7 3.3 4.0 Supply voltage VDD [V] 556 User's Manual U15947EJ3V1UD 5.0 5.5 6.0 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) (2) Read/write operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1/2) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 20 ns Address hold time tADH 6 ns Data input time from address tADD1 (2 + 2n)tCY - 54 ns tADD2 (3 + 2n)tCY - 60 ns Address output time from RD tRDAD 100 ns Data input time from RD tRDD1 (2 + 2n)tCY - 87 ns tRDD2 (3 + 2n)tCY - 93 ns 0 Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY - 33 ns tRDL2 (2.5 + 2n)tCY - 33 ns Input time from RD to WAIT tRDWT1 tCY - 43 ns tRDWT2 tCY - 43 ns Input time from WR to WAIT tWRWT tCY - 25 ns WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 6 ns WR low-level width tWRL1 (1.5 + 2n)tCY - 15 ns Delay time from ASTB to RD tASTRD 6 ns Delay time from ASTB to WR tASTWR 2tCY - 15 ns Delay time from RD to ASTB at tRDAST 0.8tCY - 15 1.2tCY ns tRDADH 0.8tCY - 15 1.2tCY + 30 ns Write data output time from RD tRDWD 40 Write data output time from WR tWRWD 10 60 ns Address hold time from WR tWRADH 0.8tCY - 15 1.2tCY + 30 ns Delay time from WAIT to RD tWTRD 0.8tCY 2.5tCY + 25 ns Delay time from WAIT to WR tWTWR 0.8tCY 2.5tCY + 25 ns external fetch Address hold time from RD at external fetch ns Caution TCY can only be used at 0.238 s (MIN). Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) User's Manual U15947EJ3V1UD 557 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) (2) Read/write operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 30 ns Address hold time tADH 10 ns Input time from address to data tADD1 (2 + 2n)tCY - 108 ns tADD2 (3 + 2n)tCY - 120 ns Output time from RD to address tRDAD 200 ns Input time from RD to data tRDD1 (2 + 2n)tCY - 148 ns tRDD2 (3 + 2n)tCY - 162 ns 0 Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY - 40 ns tRDL2 (2.5 + 2n)tCY - 40 ns Input time from RD to WAIT tRDWT1 tCY - 75 ns ns tRDWT2 tCY - 60 Input time from WR to WAIT tWRWT tCY - 50 ns WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 10 ns WR low-level width tWRL1 (1.5 + 2n)tCY - 30 ns Delay time from ASTB to RD tASTRD 10 ns Delay time from ASTB to WR tASTWR 2tCY - 30 ns Delay time from RD to ASTB at tRDAST 0.8tCY - 30 1.2tCY ns tRDADH 0.8tCY - 30 1.2tCY + 60 ns Write data output time from RD tRDWD 40 Write data output time from WR tWRWD 20 120 ns Hold time from WR to address tWRADH 0.8tCY - 30 1.2tCY + 60 ns Delay time from WAIT to RD tWTRD 0.5tCY 2.5tCY + 50 ns Delay time from WAIT to WR tWTWR 0.5tCY 2.5tCY + 50 ns external fetch Hold time from RD to address at external fetch ns Caution TCY can only be used at 0.4 s (MIN). Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) 558 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) (3) Serial interface (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 312.5 kbps MAX. Unit 312.5 kbps MAX. Unit (b) UART mode (UART0, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 Conditions MIN. TYP. 4.0 V VDD 5.5 V 200 ns 3.3 V VDD < 4.0 V 240 ns 2.7 V VDD < 3.3 V 400 ns tKCY1/2 - 10 ns 30 ns 30 ns tKH1, tKL1 SI1n setup time (to SCK1n) tSIK1 SI1n hold time (from SCK1n) tKSI1 Delay time from SCK1n to tKSO1 Note C = 100 pF 30 ns MAX. Unit SO1n output Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns 80 ns tKL2 SI1n setup time (to SCK1n) tSIK2 SI1n hold time (from SCK1n) tKSI2 Delay time from SCK1n to tKSO2 50 Note C = 100 pF ns 120 ns SO1n output Note C is the load capacitance of the SO1n output line. Remark PD780143, 780144, 780143(A), 780144(A) n = 0, 1: PD780146, 780148, 78F0148, 780146(A), 780148(A), 78F0148(A) n = 0: User's Manual U15947EJ3V1UD 559 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tTH3, tTL3 SIA0 setup time (to SCKA0) tSIK3 SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to SOA0 tKSO3 Conditions 4.0 V VDD 5.5 V Strobe signal high-level width Busy signal setup time (to busy MAX. Unit 600 ns 1200 ns 4.0 V VDD 5.5 V tKCY3/2 - 50 ns 2.7 V VDD < 4.0 V tKCY3/2 - 100 ns 100 ns 300 ns Note C = 100 pF 4.0 V VDD 5.5 V 200 2.7 V VDD < 4.0 V 300 ns tKCY3/2 - 100 ns 4.0 V VDD 5.5 V tKCY3 - 30 ns 2.7 V VDD < 4.0 V tKCY3 - 60 ns 100 ns 4.0 V VDD 5.5 V 100 ns 2.7 V VDD < 4.0 V 150 ns tSBD tSBW TYP. 2.7 V VDD < 4.0 V output Time from SCKA0 to STB0 MIN. tBYS signal detection timing) Busy signal hold time (from busy tBYH signal detection timing) Time from busy inactive to SCKA0 tSPS 2tKCY3 ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY4 tKH4, tKL4 SIA0 setup time (to SCKA0) tSIK4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to SOA0 tKSO4 Conditions tR4, tF4 TYP. MAX. Unit 4.0 V VDD 5.5 V 600 ns 2.7 V VDD < 4.0 V 1200 ns 4.0 V VDD 5.5 V 300 ns 2.7 V VDD < 4.0 V 600 ns 100 ns 300 ns Note C = 100 pF output SCKA0 rise/fall time MIN. 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns 120 ns 1000 ns When external device expansion function is used When external device expansion function is not used Note C is the load capacitance of the SOA0 output line. 560 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fXP tXPL tXPH VIH6 (MIN.) VIL6 (MAX.) X1 input 1/fXT tXTL tXTH VIH6 (MIN.) XT1 input VIL6 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Note PD780146, 780148, 78F0148, 780146(A), 780148(A), and 78F0148(A) only. User's Manual U15947EJ3V1UD 561 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) RESET Input Timing tRSL RESET Read/Write Operation External fetch (no wait): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS tADH Instruction code tRDAD tRDD1 tRDADH tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External fetch (wait insertion): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS tADH tRDAD Instruction code tRDADH tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 562 tWTL User's Manual U15947EJ3V1UD tWTRD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) External data access (no wait): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Lower 8-bit address tADS tADH Hi-Z tRDAD tRDD2 tASTH Hi-Z Write data Read data tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRADH tWRWD WR tASTWR tWRL1 External data access (wait insertion): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Lower 8-bit address tADS tADH tASTH Hi-Z Read data Hi-Z Write data tRDAD tRDH tRDD2 ASTB tASTRD RD tRDWD tRDL2 tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTL tWTRD tWTL tWRWT User's Manual U15947EJ3V1UD tWTWR 563 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0: PD780143, 780144, 780143(A), 780144(A) n = 0, 1: PD780146, 780148, 78F0148, 780146(A), 780148(A), 78F0148(A) 564 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 D2 D2 D1 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYS 10+nNote tBYH 1 tSPS BUSY0 (active-high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. User's Manual U15947EJ3V1UD 565 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) A/D Converter Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. Resolution 10 Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Note 1 Integral non-linearity error Differential non-linearity error Analog input voltage Note 1 TYP. MAX. Unit 10 10 bit 4.0 V AVREF 5.5 V 0.2 0.4 %FSR 2.7 V AVREF < 4.0 V 0.3 0.6 %FSR 4.0 V AVREF 5.5 V 14 100 s 2.7 V AVREF < 4.0 V 17 100 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 2.5 LSB LSB 2.7 V AVREF < 4.0 V 4.5 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB AVREF V MAX. Unit VIAN AVSS Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage Power supply rise time Response delay time 1 Note 3 Response delay time 2 Note 4 Minimum pulse width Conditions MIN. Note 1 VPOC0 Mask option = 3.5 V VPOC1 Mask option = 2.85 V tPTH VDD: 0 V 2.7 V 0.0015 VDD: 0 V 3.3 V 0.002 Note 2 tPTHD When power supply rises, after reaching detection voltage (MAX.) tPD When VDD falls tPW TYP. 3.3 3.5 3.7 V 2.7 2.85 3.0 V ms ms 0.2 3.0 ms 1.0 ms ms Notes 1. When flash memory version PD78F0148M5, 78F0148M6, 78F0148M5(A), or 78F0148M6(A) is used 2. When flash memory version PD78F0148M3, 78F0148M4, 78F0148M3(A), or 78F0148M4(A) is used 3. Time required from voltage detection to reset release. 4. Time required from voltage detection to internal reset output. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time 566 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) LVI Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage Note 1 Conditions MIN. TYP. MAX. Unit VLVI0 4.1 4.3 4.5 V VLVI1 3.9 4.1 4.3 V VLVI2 3.7 3.9 4.1 V VLVI3 3.5 3.7 3.9 V VLVI4 3.3 3.5 3.7 V VLVI5 3.15 3.3 3.45 V VLVI6 2.95 3.1 3.25 V 0.2 2.0 ms Response time tLD Minimum pulse width tLW Reference voltage stabilization wait tLWAIT0 0.5 2.0 ms tLWAIT1 0.1 0.2 ms time 0.2 ms Note 2 Operation stabilization wait time Notes 1. 2. Note 3 Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by the POC mask option (when flash memory version PD78F0148M1, 78F0148M2, 78F0148M1(A), or 78F0148M2(A) is used). 3. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 2. VPOCn < VLVIm (n = 0 and 1, m = 0 to 6) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT0 tLWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol VDDDR Conditions When POC-OFF is selected by mask option Release signal set time MIN. 1.6 TYP. MAX. Unit 5.5 V Note tSREL 0 s Note When flash memory version PD78F0148M1, 78F0148M2, 78F0148M1(A), or 78F0148M2(A) is used User's Manual U15947EJ3V1UD 567 CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) Flash Memory Programming Characteristics: PD78F0148, 78F0148(A) (TA = +10 to +60C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Write erase characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit 9.7 10.0 10.3 V VPP supply voltage VPP2 During flash memory programming VDD supply current IDD When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V 37 mA VPP supply current IPP VPP = VPP2 100 mA 0.201 s 20 s/chip Step erase time Note 1 Ter Note 2 Overall erase time Writeback time Tera Note 3 Cwb 0.2 When step erase time = 0.2 s Twb Number of writebacks per 1 writeback command 0.199 49.4 50 When writeback time = 50 ms 50.6 ms 60 Times 16 Times 52 s 520 s 20 Times/ Note 4 Number of erases/writebacks Note 5 Step write time Overall write time per word Cerwb Twr Note 6 Twrw 48 When step write time = 50 s (1 word = 1 48 50 byte) Note 7 Number of rewrites per chip Cerwr 1 erase + 1 write after erase = 1 rewrite area Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time before erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 50 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries 5. must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. 6. The actual write time per word is 100 s longer. The internal verify time during or after a write is not 7. included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. 568 User's Manual U15947EJ3V1UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit tDP 10 s Release time from VPP to RESET tPR 10 s VPP pulse input start time from RESET tRP 2 ms VPP pulse high-/low-level width tPW 8 s VPP pulse input end time from RESET tRPE VPP pulse low-level input voltage VPPL 0.8VDD VPP pulse high-level input voltage VPPH 9.7 Set time from VDD to VPP 10.0 14 ms 1.2VDD V 10.3 V Flash Write Mode Setting Timing VDD VDD 0V tDP tRP tPW VPPH VPP VPPL tPW 0V tPR tRPE VDD RESET (input) 0V User's Manual U15947EJ3V1UD 569 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Target products: PD780143(A1), 780144(A1), 780146(A1), 780148(A1), 78F0148(A1) Cautions 1. Be sure to connect the REGC pin of (A1) grade products directly to VDD. 2. The external bus interface function cannot be used with (A1) grade products. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V EVDD -0.3 to +6.5 V REGC -0.3 to +6.5 V VSS -0.3 to +0.3 V EVSS -0.3 to +0.3 -0.3 to VDD + 0.3 AVREF Input voltage VI1 V -0.3 to +0.3 AVSS VPP V Note 1 PD78F0148(A1) only, Note 2 P00 to P06, P10 to P17, P20 to P27, P30 V -0.3 to +10.5 -0.3 to VDD + 0.3 V Note 1 V Note 1 V to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET VI2 P62, P63 N-ch open drain On-chip pull-up resistor VI3 Output voltage Analog input voltage VPP in flash programming mode (PD78F0148(A1) only) -0.3 to +13 -0.3 to VDD + 0.3 V -0.3 to +10.5 V VO -0.3 to VDD + 0.3 VAN AVSS - 0.3 to AVREF + 0.3 Note 1 V Note 1 V and -0.3 to VDD + 0.3 Note 1 Output current, high IOH Per pin Total of P00 to P06, P40 to P47, P50 to all pins -48 mA P57, P64 to P67, P70 to P77, -8 mA -24 mA -24 mA P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 Note 1. Must be 6.5 V or lower. (Refer to Note 2 on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 570 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Symbol Output current, low IOL Conditions Per pin P00 to P06, P10 to P17, P30 to Ratings Unit 16 mA P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 24 mA Total of P00 to P06, P40 to P47, P50 to 28 mA all pins P57, P60, P61, P64 to P67, 56 mA P70 to P77, P142 to P145 28 mA -40 to +110 C P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Operating ambient TA PD780143(A1), 780144(A1), 780146(A1), 780148(A1) temperature PD78F0148(A1) -40 to +105 In normal operation mode -10 to +85 In flash memory programming mode Storage temperature Tstg PD780143(A1), 780144(A1), -65 to +150 C 780146(A1), 780148(A1) PD78F0148(A1) -40 to +125 Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (3.3 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (3.3 V) of the operating voltage range of VDD (see b in the figure below). VDD 3.3 V 0V a b VPP 3.3 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 571 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) X1 Oscillator Characteristics Note 1 , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (TA = -40 to +110C Resonator Recommended Circuit Parameter Conditions Note 3 Ceramic Note 2 resonator VSS X1 C1 X2 Oscillation frequency (fXP) C2 Note 3 Crystal Note 2 resonator VSS X1 C1 X2 Oscillation frequency (fXP) Notes 1. Unit MHz 4.5 V VDD 5.5 V 2.0 10 4.0 V VDD < 4.5 V 2.0 8.38 3.3 V VDD < 4.0 V 2.0 5.0 4.5 V VDD 5.5 V 2.0 10 2.0 8.38 2.0 5.0 4.5 V VDD 5.5 V 2.0 10 4.0 V VDD < 4.5 V 2.0 8.38 3.3 V VDD < 4.0 V 2.0 5.0 X1 input high-/low-level width 4.5 V VDD 5.5 V 46 500 (tXPH, tXPL) 4.0 V VDD < 4.5 V 56 500 3.3 V VDD < 4.0 V 96 500 X1 input frequency (fXP) X1 MAX. 4.0 V VDD < 4.5 V Note 3 Note 2 clock TYP. 3.3 V VDD < 4.0 V C2 External MIN. X2 MHz MHz ns TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. Connect the REGC pin directly to VDD. 3. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal oscillation clock after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time counter status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 572 User's Manual U15947EJ3V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Internal Oscillator Characteristics Note (TA = -40 to +110C , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Parameter Internal oscillator Note Conditions Oscillation frequency (fR) MIN. TYP. MAX. Unit 120 240 490 kHz TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) Subsystem Clock Oscillator Characteristics Note 1 , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (TA = -40 to +110C Resonator Crystal Recommended Circuit VSS XT2 resonator XT1 Parameter Conditions Oscillation frequency MIN. TYP. MAX. Unit 32 32.768 35 kHz 32 38.5 kHz 12 15 s Note 2 (fXT) Rd C4 External clock XT2 C3 XT1 XT1 input frequency Note 2 (fXT) XT1 input high-/low-level width (tXTH, tXTL) Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U15947EJ3V1UD 573 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (1/6): PD78F0148(A1) (TA = -40 to +105C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Conditions MIN. TYP. MAX. Unit Per pin 4.0 V VDD 5.5 V -4 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V -20 mA 4.0 V VDD 5.5 V -20 mA 4.0 V VDD 5.5 V -25 mA 3.3 V VDD < 4.0 V -8 mA 4.0 V VDD 5.5 V 8 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 12 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V 24 mA 4.0 V VDD 5.5 V 24 mA 4.0 V VDD 5.5 V 30 mA 3.3 V VDD < 4.0 V 8 mA 0.7VDD VDD V 0.8VDD VDD V 0.7AVREF AVREF V 0.7VDD VDD V 0.7VDD 12 V VDD - 0.5 VDD V 0 0.3VDD V 0 0.2VDD V 0 0.3AVREF V P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 All pins Output current, low IOL Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 All pins Input voltage, high VIH1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Input voltage, low Note VIH3 P20 to P27 VIH4 P60, P61 VIH5 P62, P63 VIH6 X1, X2, XT1, XT2 VIL1 P12, P13, P15, P40 to P47, P50 to P57, P64 to N-ch open drain P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note VIL3 P20 to P27 VIL4 P60, P61 0 0.3VDD V VIL5 P62, P63 0 0.3VDD V VIL6 X1, X2, XT1, XT2 0 0.4 V Note When used as digital input ports, set AVREF = VDD. Remark 574 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (2/6): PD78F0148(A1) (TA = -40 to +105C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions MIN. Total of P10 to P17, P30 4.0 V VDD 5.5 V, VDD - 1.0 to P33, P120, P130, IOH = -4 mA TYP. MAX. Unit V P140, P141 IOH = -20 mA Total of P00 to P06, P40 4.0 V VDD 5.5 V, VDD - 1.0 to P47, P50 to P57, P64 IOH = -4 mA V to P67, P70 to P77, P142 to P145 IOH = -20 mA Output voltage, low VOL1 IOH = -100 A 3.3 V VDD < 4.0 V Total of P10 to P17, P30 4.0 V VDD 5.5 V, to P33, P62, P63, P120, IOL = 8 mA VDD - 0.5 V 1.3 V 1.3 V P130, P140, P141 IOL = 24 mA Total of P00 to P06, P40 4.0 V VDD 5.5 V, to P47, P50 to P57, P60, IOL = 8 mA P61, P64 to P67, P70 to P77, P142 to P145 IOL = 24 mA VOL2 IOL = 400 A 3.3 V VDD < 4.0 V 0.4 V P60 to P63 4.0 V VDD 5.5 V, 2.0 V 10 A 10 A 20 A IOL = 12 mA Input leakage current, high ILIH1 P00 to P06, P10 to P17, P30 to VI = VDD P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET VI = AVREF Input leakage current, low P20 to P27 Note 1 , XT1, XT2 Note 1 ILIH2 VI = VDD X1, X2 ILIH3 VI = 12 V P62, P63 (N-ch open drain) 20 A ILIL1 VI = 0 V P00 to P06, P10 to P17, P20 to -10 A -20 A P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET ILIL2 X1, X2 ILIL3 Note 1 , XT1, XT2 Note 1 -10 P62, P63 (N-ch open drain) Note 2 A Output leakage current, high ILOH VO = VDD 10 A Output leakage current, low ILOL VO = 0 V -10 A Pull-up resistance value RL VI = 0 V 10 120 k VPP supply voltage (PD78F0148 only) VPP1 In normal operation mode 0 0.2VDD V Notes 1. 2. Remark 30 When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -55 A flows during only one cycle. At all other times, the maximum leakage current is -10 A. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 575 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (3/6): PD78F0148(A1) (TA = -40 to +105C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 Conditions fXP = 10 MHz Note 3 VDD = 5.0 V 10% X1 crystal oscillation operating mode IDD2 MIN. TYP. MAX. Unit When A/D converter is stopped 14.0 27.6 mA When A/D converter is 15.0 29.6 mA 2.0 5.4 mA 11.3 mA Note 7 operating Note 2 X1 crystal oscillation HALT fXP = 10 MHz VDD = 5.0 V 10% mode When peripheral functions are stopped When peripheral functions are operating IDD3 Internal VDD = 5.0 V 10% 0.53 3.52 mA VDD = 5.0 V 10% 0.19 2.16 mA VDD = 5.0 V 10% 130 1700 A VDD = 5.0 V 10% 20 1400 A VDD = 5.0 V 10% POC: OFF, Internal oscillator: OFF 0.1 1400 A 14 1500 A 3.5 1400 A 17.5 1500 A oscillation operating mode IDD4 Note 4 Internal oscillation HALT mode IDD5 Note 4 32.768 kHz crystal oscillation operating mode IDD6 Notes 4, 6 32.768 kHz crystal oscillation HALT mode IDD7 Notes 4, 6 STOP mode POC: OFF, Internal oscillator: ON Note 5 POC: ON , Internal oscillator: OFF Note 5 POC: ON Notes 1. , Internal oscillator: ON Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. 5. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0148M1(A1) and 78F0148M2(A1). 6. When the PD78F0148M1(A1) and 78F0148M2(A1) (including LVIE = 0) are selected and internal oscillator is stopped. Peripheral operation current is not included. 7. 576 Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (4/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) (TA = -40 to +110C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Conditions MIN. TYP. MAX. Unit Per pin 4.0 V VDD 5.5 V -4 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V -20 mA 4.0 V VDD 5.5 V -20 mA All pins 3.3 V VDD < 4.0 V -8 mA Per pin for P00 to P06, P10 4.0 V VDD 5.5 V 8 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 12 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V 24 mA 4.0 V VDD 5.5 V 24 mA 3.3 V VDD < 4.0 V 8 mA 0.7VDD VDD V 0.8VDD VDD V 0.7AVREF AVREF V 0.7VDD VDD V P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 Output current, low IOL to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 All pins Input voltage, high VIH1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Input voltage, low VIH3 P20 to P27 VIH4 P60, P61 VIH5 P62, P63 Note N-ch open drain 0.7VDD 12 V On-chip pull-up resistor 0.7VDD VDD V VDD - 0.5 VDD V 0 0.3VDD V 0 0.2VDD V 0 0.3AVREF V VIH6 X1, X2, XT1, XT2 VIL1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note VIL3 P20 to P27 VIL4 P60, P61 0 0.3VDD V VIL5 P62, P63 0 0.3VDD V VIL6 X1, X2, XT1, XT2 0 0.4 V Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 577 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (5/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) (TA = -40 to +110C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions MIN. Total of P10 to P17, P30 4.0 V VDD 5.5 V, VDD - 1.0 to P33, P120, P130, IOH = -4 mA TYP. MAX. Unit V P140, P141 IOH = -20 mA Total of P00 to P06, P40 4.0 V VDD 5.5 V, VDD - 1.0 to P47, P50 to P57, P64 IOH = -4 mA V to P67, P70 to P77, P142 to P145 IOH = -20 mA Output voltage, low VOL1 IOH = -100 A 3.3 V VDD < 4.0 V Total of P10 to P17, P30 4.0 V VDD 5.5 V, to P33, P62, P63, P120, IOL = 8 mA VDD - 0.5 V 1.3 V 1.3 V P130, P140, P141 IOL = 24 mA Total of P00 to P06, P40 4.0 V VDD 5.5 V, to P47, P50 to P57, P60, IOL = 8 mA P61, P64 to P67, P70 to P77, P142 to P145 IOL = 24 mA Input leakage current, high IOL = 400 A 3.3 V VDD < 4.0 V 0.4 V VOL2 P60 to P63 IOL = 12 mA 2.0 V ILIH1 VI = VDD 10 A 10 A 20 A P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET VI = AVREF Input leakage current, low P20 to P27 Note 1 , XT1, XT2 Note 1 ILIH2 VI = VDD X1, X2 ILIH3 VI = 12 V P62, P63 (N-ch open drain) 10 A ILIL1 VI = 0 V P00 to P06, P10 to P17, P20 to -10 A -20 A P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET ILIL2 X1, X2 ILIL3 Note 1 , XT1, XT2 Note 1 -10 P62, P63 (N-ch open drain) Note 2 A Output leakage current, high ILOH VO = VDD 10 A Output leakage current, low ILOL VO = 0 V -10 A Pull-up resistance value RL VI = 0 V 120 k Notes 1. 2. 10 30 When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -55 A flows during only one cycle. At all other times, the maximum leakage current is -10 A. Remark 578 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (6/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) (TA = -40 to +110C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 Conditions fXP = 10 MHz Note 3 VDD = 5.0 V 10% X1 crystal oscillation operating mode IDD2 MIN. TYP. MAX. Unit When A/D converter is stopped 7.7 16.5 mA When A/D converter is 8.7 18.5 mA 1.7 4.5 mA 9.2 mA Note 7 operating Note 2 X1 crystal oscillation HALT fXP = 10 MHz VDD = 5.0 V 10% mode When peripheral functions are stopped When peripheral functions are operating IDD3 Internal VDD = 5.0 V 10% 0.28 2.22 mA VDD = 5.0 V 10% 35 1240 mA VDD = 5.0 V 10% 38 1200 A VDD = 5.0 V 10% 20 1100 A POC: OFF, Internal oscillator: OFF 0.1 1100 A POC: OFF, Internal oscillator: ON 14 1200 A 3.5 1100 A 17.5 1200 A oscillation operating mode IDD4 Note 4 Internal oscillation HALT mode IDD5 Note 4 32.768 kHz crystal oscillation operating mode IDD6 Notes 4, 6 32.768 kHz crystal oscillation HALT mode IDD7 Notes 4, 6 STOP mode VDD = 5.0 V 10% Note 5 POC: ON , Internal oscillator: OFF Note 5 POC: ON Notes 1. , Internal oscillator: ON Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. When X1 oscillator is stopped. 5. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. 6. When POC-OFF (including LVIE = 0) is selected by a mask option and internal oscillator is stopped. Peripheral operation current is not included. 7. Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD 579 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Characteristics (1) Basic operation Note 1 , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (TA = -40 to +110C Parameter Symbol Instruction cycle (minimum TCY instruction execution time) Conditions MIN. X1 input 4.5 V VDD 5.5 V 0.2 16 s clock 4.0 V VDD < 4.5 V 0.238 16 s 3.3 V VDD < 4.0 V 0.4 16 s Internal oscillation clock Subsystem clock operation Note 2 TI011 , tTIH0, 4.0 V VDD 5.5 V 4.09 8.33 16.67 s 114 122 125 s 0.1 3.3 V VDD < 4.0 V fTI5 Note 3 s 2/fsam + 0.2 TI50, TI51 input frequency s 2/fsam + input high-level width, tTIL0 low-level width Unit system operation TI000, TI010, TI001 MAX. Main clock Note 2 TYP. Note 3 4.0 V VDD 5.5 V 10 MHz 3.3 V VDD < 4.0 V 5 MHz TI50, TI51 input high-level width, tTIH5, 4.0 V VDD 5.5 V 50 ns low-level width tTIL5 3.3 V VDD < 4.0 V 100 ns Interrupt input high-level width, tINTH, 1 s low-level width tINTL Key return input low-level width tKR 4.0 V VDD 5.5 V 50 ns 3.3 V VDD < 4.0 V 100 ns 10 s RESET low-level width Notes 1. tRSL TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. 3. PD780146(A1), 780148(A1), and 78F0148(A1) only. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. 580 User's Manual U15947EJ3V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 3.3 4.0 4.5 5.0 5.5 6.0 Supply voltage VDD [V] User's Manual U15947EJ3V1UD 581 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial interface Note (TA = -40 to +110C , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Note TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 312.5 kbps MAX. Unit 312.5 kbps MAX. Unit (b) UART mode (UART0, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 SCK1n high-/low-level width Conditions MIN. TYP. 4.5 V VDD 5.5 V 200 ns 4.0 V VDD < 4.5 V 240 ns 3.3 V VDD < 4.0 V 400 ns tKCY1/2 - 10 ns 30 ns tKH1, tKL1 SI1n setup time (to SCK1n) tSIK1 SI1n hold time (from SCK1n) tKSI1 Delay time from SCK1n to tKSO1 30 ns Note C = 100 pF 30 ns MAX. Unit SO1n output Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns 80 ns 50 ns tKL2 SI1n setup time (to SCK1n) tSIK2 SI1n hold time (from SCK1n) tKSI2 Delay time from SCK1n to tKSO2 Note C = 100 pF SO1n output Note C is the load capacitance of the SO1n output line. Remark n = 0: PD780143(A1), 780144(A1) n = 0, 1: PD780146(A1), 780148(A1), 78F0148(A1) 582 User's Manual U15947EJ3V1UD 120 ns CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tTH3, tTL3 SIA0 setup time (to SCKA0) tSIK3 SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to SOA0 tKSO3 Conditions 4.5 V VDD 5.5 V Strobe signal high-level width Busy signal setup time (to busy MAX. Unit 600 ns 1200 ns 4.5 V VDD 5.5 V tKCY3/2 - 50 ns 3.3 V VDD < 4.5 V tKCY3/2 - 100 ns 100 ns 300 ns Note C = 100 pF 4.5 V VDD 5.5 V 200 3.3 V VDD < 4.5 V 300 ns tKCY3/2 - 100 ns 4.5 V VDD 5.5 V tKCY3 - 30 ns 3.3 V VDD < 4.5 V tKCY3 - 60 ns 100 ns 4.5 V VDD 5.5 V 100 ns 3.3 V VDD < 4.5 V 150 ns tSBD tSBW TYP. 3.3 V VDD < 4.5 V output Time from SCKA0 to STB0 MIN. tBYS signal detection timing) Busy signal hold time (from busy tBYH signal detection timing) Time from busy inactive to SCKA0 tSPS 2tKCY3 ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY4 tKH4, tKL4 SIA0 setup time (to SCKA0) tSIK4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to SOA0 tKSO4 output SCKA0 rise/fall time Conditions MIN. TYP. MAX. Unit 4.5 V VDD 5.5 V 600 3.3 V VDD < 4.5 V 1200 ns 4.5 V VDD 5.5 V 300 ns 3.3 V VDD < 4.5 V 600 ns 100 ns 300 ns Note C = 100 pF ns 4.5 V VDD 5.5 V 200 ns 3.3 V VDD < 4.5 V 300 ns 1000 ns tR4, tF4 Note C is the load capacitance of the SOA0 output line. User's Manual U15947EJ3V1UD 583 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fXP tXPL tXPH VIH6 (MIN.) VIL6 (MAX.) X1 input 1/fXT tXTL tXTH VIH6 (MIN.) XT1 input VIL6 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL INTP0 to INTP7 Note PD780146(A1), 780148(A1), and 78F0148(A1) only. 584 User's Manual U15947EJ3V1UD tINTH CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) RESET Input Timing tRSL RESET Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm Output data SO1n Remark m = 1, 2 n = 0: PD780143(A1), 780144(A1) n = 0, 1: PD780146(A1), 780148(A1), 78F0148(A1) User's Manual U15947EJ3V1UD 585 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 D2 D2 D1 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYS 10+nNote tBYH BUSY0 (active-high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. 586 User's Manual U15947EJ3V1UD 1 tSPS CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) A/D Converter Characteristics Note 1 (TA = -40 to +110C , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. Resolution 10 Notes 2, 3 Overall error Conversion time tCONV Notes 2, 3 Zero-scale error Full-scale error Notes 2, 3 Note 2 Integral non-linearity error Differential non-linearity error Analog input voltage Note 2 TYP. MAX. Unit 10 10 bit 4.0 V AVREF 5.5 V 0.2 0.6 %FSR 3.3 V AVREF < 4.0 V 0.3 0.8 %FSR 4.0 V AVREF 5.5 V 14 60 s 3.3 V AVREF < 4.0 V 19 60 s 4.0 V AVREF 5.5 V 0.6 %FSR 3.3 V AVREF < 4.0 V 0.8 %FSR 4.0 V AVREF 5.5 V 0.6 %FSR 3.3 V AVREF < 4.0 V 0.8 %FSR 4.0 V AVREF 5.5 V 4.5 LSB 3.3 V AVREF < 4.0 V 6.5 LSB 4.0 V AVREF 5.5 V 2.0 LSB 3.3 V AVREF < 4.0 V 2.5 LSB AVREF V VAIN AVSS Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. Excludes quantization error (1/2 LSB). 3. This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +110CNote 1) Parameter Symbol Detection voltage Conditions VPOC0 Mask option = 3.5 V Note 2 MIN. TYP. MAX. Unit 3.3 3.5 3.72 V tPTH VDD: 0 V 3.3 V Response delay time 1 Note 3 tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Note 4 tPD When VDD falls 1.0 ms Power supply rise time Minimum pulse width 0.002 tPW ms 0.2 ms Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. When flash memory version PD78F0148M5(A1) or 78F0148M6(A1) is used 3. Time required from voltage detection to reset release. 4. Time required from voltage detection to internal reset output. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U15947EJ3V1UD 587 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +110CNote 1) Parameter Symbol Detection voltage Note 2 Conditions MIN. TYP. MAX. Unit VLVI0 4.1 4.3 4.52 V VLVI1 3.9 4.1 4.32 V VLVI2 3.7 3.9 4.12 V VLVI3 3.5 3.7 3.92 V VLVI4 3.3 3.5 3.72 V 0.2 2.0 ms Response time tLD Minimum pulse width tLW Reference voltage stabilization wait tLWAIT0 0.5 2.0 ms tLWAIT1 0.1 0.2 ms time 0.2 ms Note 3 Operation stabilization wait time Note 4 Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. Time required from voltage detection to interrupt output or internal reset output. 3. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by mask option (when flash memory version PD78F0148M1(A1) or 78F0148M2(A1) is used). 4. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 2. VPOC0 < VLVIm (m = 0 to 4) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT0 tLWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +110C Parameter Data retention supply voltage Symbol VDDDR Conditions When POC-OFF is selected by mask option Release signal set time MIN. 2.0 ) MAX. Unit 5.5 V Note 2 tSREL 0 Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. When flash memory version PD78F0148M1(A1) or 78F0148M2(A1) is used 588 TYP. Note 1 User's Manual U15947EJ3V1UD s CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Flash Memory Programming Characteristics: PD78F0148(A1) (TA = +10 to +60C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Write erase characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit 9.7 10.0 10.3 V VPP supply voltage VPP2 During flash memory programming VDD supply current IDD When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V 37 mA VPP supply current IPP VPP = VPP2 100 mA 0.201 s 20 s/chip Step erase time Note 1 Ter Note 2 Overall erase time Writeback time Tera Note 3 Cwb 0.2 When step erase time = 0.2 s Twb Number of writebacks per 1 writeback command 0.199 49.4 50 When writeback time = 50 ms 50.6 ms 60 Times 16 Times 52 s 520 s 20 Times/ Note 4 Number of erases/writebacks Note 5 Step write time Overall write time per word Cerwb Twr Note 6 Twrw 48 When step write time = 50 s (1 word = 1 48 50 byte) Note 7 Number of rewrites per chip Cerwr 1 erase + 1 write after erase = 1 rewrite area Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time before erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 50 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries 5. must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. 6. The actual write time per word is 100 s longer. The internal verify time during or after a write is not 7. included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. User's Manual U15947EJ3V1UD 589 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit tDP 10 s Release time from VPP to RESET tPR 10 s VPP pulse input start time from RESET tRP 2 ms VPP pulse high-/low-level width tPW 8 s VPP pulse input end time from RESET tRPE VPP pulse low-level input voltage VPPL 0.8VDD VPP pulse high-level input voltage VPPH 9.7 Set time from VDD to VPP Flash Write Mode Setting Timing VDD VDD 0V tDP tRP tPW VPPH VPP VPPL tPW 0V tPR tRPE VDD RESET (input) 0V 590 User's Manual U15947EJ3V1UD 10.0 14 ms 1.2VDD V 10.3 V CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Target products: PD780143(A2), 780144(A2), 780146(A2), 780148(A2) Cautions 1. Be sure to connect the REGC pin of (A2) grade products directly to VDD. 2. The external bus interface function cannot be used with (A2) grade products. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V EVDD -0.3 to +6.5 V REGC -0.3 to +6.5 V VSS -0.3 to +0.3 V EVSS -0.3 to +0.3 -0.3 to VDD + 0.3 AVREF VI1 V -0.3 to +0.3 AVSS Input voltage V Note P00 to P06, P10 to P17, P20 to P27, P30 -0.3 to VDD + 0.3 V Note V to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET VI2 P62, P63 N-ch open drain Analog input voltage V Note VO -0.3 to VDD + 0.3 Note VAN AVSS - 0.3 to AVREF + 0.3 On-chip pull-up resistor Output voltage -0.3 to +13 -0.3 to VDD + 0.3 V V Note V and -0.3 to VDD + 0.3 Note Output current, high IOH Per pin Total of P00 to P06, P40 to P47, P50 to all pins -42 mA P57, P64 to P67, P70 to P77, -7 mA -21 mA -21 mA P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 591 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions Per pin P00 to P06, P10 to P17, P30 to Ratings Unit 14 mA P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 Total of P00 to P06, P40 to P47, P50 to all pins P57, P60, P61, P64 to P67, 49 mA P70 to P77, P142 to P145 P10 to P17, P30 to P33, P62, 21 mA 24.5 mA 24.5 mA -40 to +125 C -65 to +150 C P63, P120, P130, P140, P141 Operating ambient TA In normal operation mode temperature Storage temperature Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 592 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Ceramic Note 2 resonator Recommended Circuit VSS X1 C1 Crystal Note 2 resonator External Note 2 clock VSS X1 X2 Parameter Conditions MIN. TYP. MAX. Unit MHz 4.0 V VDD 5.5 V 2.0 8.38 (fXP) 3.3 V VDD < 4.0 V 2.0 5.0 Oscillation frequency Oscillation frequency Note 1 C2 X2 C1 C2 X1 X2 4.0 V VDD 5.5 V 2.0 8.38 (fXP) 3.3 V VDD < 4.0 V 2.0 5.0 X1 input frequency 4.0 V VDD 5.5 V 2.0 8.38 3.3 V VDD < 4.0 V 2.0 5.0 X1 input high-/low- 4.0 V VDD 5.5 V 56 500 level width (tXPH, tXPL) 3.3 V VDD < 4.0 V 96 500 Note 1 Note 1 (fXP) MHz MHz ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Connect the REGC pin directly to VDD. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal oscillation clock after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time counter status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U15947EJ3V1UD 593 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Internal Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Parameter Internal oscillator Conditions Oscillation frequency (fR) MIN. TYP. MAX. Unit 120 240 495 kHz Subsystem Clock Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Crystal Recommended Circuit VSS XT2 resonator XT1 Parameter Conditions Oscillation frequency MIN. TYP. MAX. Unit 32 32.768 35 kHz 32 38.5 kHz 12 15 s Note (fXT) Rd C4 External clock XT2 C3 XT1 XT1 input frequency Note (fXT) XT1 input high-/low-level width (tXTH, tXTL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 594 User's Manual U15947EJ3V1UD CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (1/3) (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Conditions MIN. TYP. MAX. Unit Per pin 4.0 V VDD 5.5 V -3.5 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V -17.5 mA 4.0 V VDD 5.5 V -17.5 mA All pins 3.3 V VDD < 4.0 V -7 mA Per pin for P00 to P06, P10 4.0 V VDD 5.5 V 7 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 10.5 mA Total of P10 to P17, P30 to 4.0 V VDD 5.5 V 21 mA 4.0 V VDD 5.5 V 21 mA 3.3 V VDD < 4.0 V 7 mA 0.7VDD VDD V 0.8VDD VDD V 0.7AVREF AVREF V 0.75VDD VDD V P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 Output current, low IOL to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 All pins Input voltage, high VIH1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Input voltage, low VIH3 P20 to P27 VIH4 P60, P61 VIH5 P62, P63 Note N-ch open drain 0.7VDD 12 V On-chip pull-up resistor 0.7VDD VDD V VDD - 0.5 VDD V 0 0.3VDD V 0 0.2VDD V 0 0.3AVREF V VIH6 X1, X2, XT1, XT2 VIL1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note VIL3 P20 to P27 VIL4 P60, P61 0 0.25VDD V VIL5 P62, P63 0 0.3VDD V VIL6 X1, X2, XT1, XT2 0 0.4 V Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD 595 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (2/3) (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions MIN. Total of P10 to P17, P30 4.0 V VDD 5.5 V, VDD - 1.0 to P33, P120, P130, IOH = -3.5 mA TYP. MAX. Unit V P140, P141 IOH = -17.5 mA Total of P00 to P06, P40 4.0 V VDD 5.5 V, VDD - 1.0 to P47, P50 to P57, P64 IOH = -3.5 mA V to P67, P70 to P77, P142 to P145 IOH = -17.5 mA Output voltage, low VOL1 IOH = -100 A 3.3 V VDD < 4.0 V Total of P10 to P17, P30 4.0 V VDD 5.5 V, to P33, P62, P63, P120, IOL = 7 mA VDD - 0.5 V 1.3 V 1.3 V P130, P140, P141 IOL = 21 mA Total of P00 to P06, P40 4.0 V VDD 5.5 V, to P47, P50 to P57, P60, IOL = 7 mA P61, P64 to P67, P70 to P77, P142 to P145 IOL = 21 mA VOL2 IOL = 400 A 3.3 V VDD < 4.0 V 0.4 V P60 to P63 4.0 V VDD 5.5 V, 2.0 V 10 A 10 A 20 A IOL = 10.5 mA Input leakage current, high ILIH1 P00 to P06, P10 to P17, P30 to VI = VDD P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET VI = AVREF Input leakage current, low P20 to P27 Note 1 , XT1, XT2 Note 1 ILIH2 VI = VDD X1, X2 ILIH3 VI = 12 V P62, P63 (N-ch open drain) 40 A ILIL1 VI = 0 V P00 to P06, P10 to P17, P20 to -10 A -20 A P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET ILIL2 X1, X2 ILIL3 Note 1 , XT1, XT2 Note 1 -10 P62, P63 (N-ch open drain) Note 2 A Output leakage current, high ILOH VO = VDD 10 A Output leakage current, low ILOL VO = 0 V -10 A Pull-up resistance value RL VI = 0 V 120 k Notes 1. 2. 10 30 When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -55 A flows during only one cycle. At all other times, the maximum leakage current is -10 A. Remark 596 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ3V1UD CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (3/3) (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 Conditions fXP = 8.38 MHz Note 3 VDD = 5.0 V 10% X1 crystal oscillation operating mode IDD2 MIN. TYP. MAX. Unit When A/D converter is stopped 6.7 15.0 mA When A/D converter is 7.7 17.0 mA 1.5 4.7 mA 8.7 mA Note 7 operating Note 2 X1 crystal oscillation HALT fXP = 8.38 MHz Note 3 VDD = 5.0 V 10% mode When peripheral functions are stopped When peripheral functions are operating IDD3 Internal VDD = 5.0 V 10% 0.28 2.82 mA VDD = 5.0 V 10% 35 1840 A VDD = 5.0 V 10% 38 1800 A VDD = 5.0 V 10% 20 1700 A VDD = 5.0 V 10% POC: OFF, Internal oscillator: OFF 0.1 1700 A 14 1800 A 3.5 1700 A 17.5 1800 A oscillation operating mode IDD4 Note 4 Internal oscillation HALT mode IDD5 Note 4 32.768 kHz crystal oscillation operating mode IDD6 Notes 4, 6 32.768 kHz crystal oscillation HALT mode IDD7 Notes 4, 6 STOP mode POC: OFF, Internal oscillator: ON Note 5 POC: ON , Internal oscillator: OFF Note 5 POC: ON Notes 1. , Internal oscillator: ON Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When PCC = 00H. 4. When X1 oscillator is stopped. 5. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. 6. When POC-OFF (including LVIE = 0) is selected by a mask option and internal oscillator is stopped. Peripheral operation current is not included. 7. Including the current that flows through the AVREF pin. User's Manual U15947EJ3V1UD 597 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Instruction cycle (minimum TCY instruction execution time) Conditions Note 1 , tTIH0, 4.0 V VDD 5.5 V 0.238 16 s clock 3.3 V VDD < 4.0 V 0.4 16 s Internal oscillation clock 4.0 V VDD 5.5 V input high-level width, tTIL0 low-level width 4.04 8.33 16.67 s 114 122 125 s 0.1 3.3 V VDD < 4.0 V fTI5 s 2/fsam + Note 2 s 2/fsam + 0.2 TI50, TI51 input frequency Unit X1 input Subsystem clock operation TI011 MAX. system operation TI000, TI010, TI001 TYP. Main clock Note 1 MIN. Note 2 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 8.38 MHz 5 MHz TI50, TI51 input high-level width, tTIH5, 4.0 V VDD 5.5 V 59.6 ns low-level width tTIL5 3.3 V VDD < 4.0 V 100 ns Interrupt input high-level width, tINTH, 1 s low-level width tINTL Key return input low-level width tKR 4.0 V VDD 5.5 V 59.6 ns 3.3 V VDD < 4.0 V 100 ns 10 s RESET low-level width Notes 1. 2. tRSL PD780146(A2) and 780148(A2) only. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. 598 User's Manual U15947EJ3V1UD CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 3.3 4.0 5.0 5.5 6.0 Supply voltage VDD [V] User's Manual U15947EJ3V1UD 599 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) Serial interface (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 261.9 kbps MAX. Unit 261.9 kbps MAX. Unit (b) UART mode (UART0, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V SCK1n high-/low-level width tKH1, MIN. TYP. 240 ns 400 ns tKCY1/2 - 10 ns 30 ns 30 ns tKL1 SI1n setup time (to SCK1n) tSIK1 SI1n hold time (from SCK1n) tKSI1 Delay time from SCK1n to tKSO1 Note C = 100 pF 30 ns MAX. Unit SO1n output Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns tKL2 SI1n setup time (to SCK1n) tSIK2 80 ns SI1n hold time (from SCK1n) tKSI2 50 ns Delay time from SCK1n to tKSO2 Note C = 100 pF SO1n output Note C is the load capacitance of the SO1n output line. Remark n = 0: PD780143(A2), 780144(A2) n = 0, 1: PD780146(A2), 780148(A2) 600 User's Manual U15947EJ3V1UD 120 ns CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time Symbol Conditions tKCY3 MIN. TYP. MAX. Unit 1200 SCKA0 high-/low-level width tTH3, tTL3 SIA0 setup time (to SCKA0) tSIK3 SIA0 hold time (from SCKA0) tKSI3 ns tKCY3/2 - 100 ns 100 ns 300 ns Note Delay time from SCKA0 to SOA0 output tKSO3 Time from SCKA0 to STB0 tSBD tKCY3/2 - 100 ns Strobe signal high-level width tSBW tKCY3 - 60 ns Busy signal setup time (to busy signal tBYS 100 ns tBYH 150 ns C = 100 pF 300 ns detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to SCKA0 2tKCY3 tSPS ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKA0 cycle time tKCY4 1200 ns SCKA0 high-/low-level width tKH4, tKL4 600 ns SIA0 setup time (to SCKA0) tSIK4 100 ns SIA0 hold time (from SCKA0) tKSI4 300 ns Delay time from SCKA0 to SOA0 output tKSO4 SCKA0 rise/fall time tR4, tF4 Note C = 100 pF 300 ns 1000 ns Note C is the load capacitance of the SOA0 output line. User's Manual U15947EJ3V1UD 601 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fXP tXPL tXPH VIH6 (MIN.) VIL6 (MAX.) X1 input 1/fXT tXTL tXTH VIH6 (MIN.) XT1 input VIL6 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL INTP0 to INTP7 Note PD780146(A2) and 780148(A2) only. 602 User's Manual U15947EJ3V1UD tINTH CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) RESET Input Timing tRSL RESET Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm Output data SO1n Remark m = 1, 2 n = 0: PD780143(A2), 780144(A2) n = 0, 1: PD780146(A2), 780148(A2) User's Manual U15947EJ3V1UD 603 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 D2 D2 D1 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYS 10+nNote tBYH BUSY0 (active-high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. 604 User's Manual U15947EJ3V1UD 1 tSPS CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) A/D Converter Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.0 V AVREF 5.5 V 0.2 0.7 %FSR 3.3 V AVREF < 4.0 V 0.3 0.9 %FSR 48 s 48 s Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Note 1 Integral non-linearity error Differential non-linearity error Analog input voltage Notes 1. 2. Note 1 4.0 V AVREF 5.5 V 16 3.3 V AVREF < 4.0 V 19 4.0 V AVREF 5.5 V 0.7 %FSR 3.3 V AVREF < 4.0 V 0.9 %FSR 4.0 V AVREF 5.5 V 0.7 %FSR 3.3 V AVREF < 4.0 V 0.9 %FSR 4.0 V AVREF 5.5 V 5.5 LSB 3.3 V AVREF < 4.0 V 7.5 LSB 4.0 V AVREF 5.5 V 2.5 LSB 3.3 V AVREF < 4.0 V 3.0 LSB AVREF V VIAN AVSS Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +125C) Parameter Symbol Detection voltage Power supply rise time Response delay time 1 Note 1 Conditions VPOC0 Mask option = 3.5 V tPTH VDD: 0 V 3.3 V tPTHD When power supply rises, after reaching MIN. TYP. MAX. Unit 3.3 3.5 3.76 V 0.002 ms 3.0 ms 1.0 ms detection voltage (MAX.) Response delay time 2 Minimum pulse width Notes 1. 2. Note 2 tPD When VDD falls tPW 0.2 ms Time required from voltage detection to reset release. Time required from voltage detection to internal reset output. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U15947EJ3V1UD 605 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +125C) Parameter Symbol Detection voltage Note 1 Conditions MIN. TYP. MAX. Unit VLVI0 4.1 4.3 4.56 V VLVI1 3.9 4.1 4.36 V VLVI2 3.7 3.9 4.16 V VLVI3 3.5 3.7 3.96 V VLVI4 3.3 3.5 3.76 V 0.2 2.0 ms Response time tLD Minimum pulse width tLW Reference voltage stabilization wait tLWAIT0 0.5 2.0 ms tLWAIT1 0.1 0.2 ms time 0.2 ms Note 2 Operation stabilization wait time Notes 1. 2. Note 3 Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by the mask option. 3. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 2. VPOC0 < VLVIm (m = 0 to 4) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT0 tLWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +125C) Parameter Data retention supply voltage Symbol VDDDR Conditions When POC-OFF is selected by mask MIN. 2.0 TYP. MAX. Unit 5.5 V option Release signal set time 606 tSREL 0 User's Manual U15947EJ3V1UD s CHAPTER 34 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 41 61 40 detail of lead end S C D P T 80 R 21 1 20 U Q F G L H I J M K S N S M NOTE ITEM Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 14.00.2 B 12.00.2 C 12.00.2 D F 14.00.2 1.25 G 1.25 H 0.220.05 I 0.08 J 0.5 (T.P.) K L 1.00.2 0.5 M 0.1450.05 N 0.08 P 1.0 Q 0.10.05 R 3 +4 -3 S 1.10.1 T 0.25 U 0.60.15 P80GK-50-9EU-1 User's Manual U15947EJ3V1UD 607 CHAPTER 34 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 41 40 60 61 detail of lead end S C D R Q 80 1 21 20 F J G I H M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.200.20 B 14.000.20 C 14.000.20 D 17.200.20 F 0.825 G 0.825 H I 0.320.06 0.13 J 0.65 (T.P.) K 1.600.20 L 0.800.20 M 0.17 +0.03 -0.07 N P 0.10 1.400.10 Q 0.1250.075 R +7 3 -3 S 1.70 MAX. P80GC-65-8BT-1 608 User's Manual U15947EJ3V1UD CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 35-1. Surface Mounting Type Soldering Conditions (1/3) (1) PD780143GC-xxx-8BT, 780144GC-xxx-8BT, 780146GC-xxx-8BT, 780148GC-xxx-8BT, PD780143GC(A)-xxx-8BT, 780144GC(A)-xxx-8BT, 780146GC(A)-xxx-8BT, 780148GC(A)-xxx-8BT, PD780143GC(A1)-xxx-8BT, 780144GC(A1)-xxx-8BT, 780146GC(A1)-xxx-8BT, 780148GC(A1)-xxx-8BT, PD780143GC(A2)-xxx-8BT, 780144GC(A2)-xxx-8BT, 780146GC(A2)-xxx-8BT, 780148GC(A2)-xxx-8BT, PD78F0148M1GC-8BT, 78F0148M2GC-8BT, 78F0148M3GC-8BT, 78F0148M4GC-8BT, 78F0148M5GC-8BT, PD78F0148M6GC-8BT, 78F0148M1GC(A)-8BT, 78F0148M2GC(A)-8BT, 78F0148M3GC(A)-8BT, PD78F0148M4GC(A)-8BT, 78F0148M5GC(A)-8BT, 78F0148M6GC(A)-8BT, 78F0148M1GC(A1)-8BT, PD78F0148M2GC(A1)-8BT, 78F0148M5GC(A1)-8BT, 78F0148M6GC(A1)-8BT Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Note Count: 2 times or less, Exposure limit: 7 days IR35-107-2 (after that, prebake at 125C for 10 hours) VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Note Count: 2 times or less, Exposure limit: 7 days VP15-107-2 (after that, prebake at 125C for 10 hours) Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, WS60-107-1 Preheating temperature: 120C max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U15947EJ3V1UD 609 CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS Table 35-1. Surface Mounting Type Soldering Conditions (2/3) (2) PD780143GK-xxx-9EU, 780144GK-xxx-9EU, 780146GK-xxx-9EU, 780148GK-xxx-9EU, 780143GK(A)-xxx-9EU, PD780144GK(A)-xxx-9EU, 780146GK(A)-xxx-9EU, 780148GK(A)-xxx-9EU, 780143GK(A1)-xxx-9EU, PD780144GK(A1)-xxx-9EU, 780146GK(A1)-xxx-9EU, 780148GK(A1)-xxx-9EU, 780143GK(A2)-xxx-9EU, PD780144GK(A2)-xxx-9EU, 780146GK(A2)-xxx-9EU, 780148GK(A2)-xxx-9EU Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Note Count: 2 times or less, Exposure limit: 7 days IR35-107-2 (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), VPS Note Count: 2 times or less, Exposure limit: 7 days VP15-107-2 (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. (3) PD78F0148M1GK-9EU, 78F0148M2GK-9EU, 78F0148M3GK-9EU, 78F0148M4GK-9EU, 78F0148M5GK-9EU, PD78F0148M6GK-9EU, 78F0148M1GK(A)-9EU, 78F0148M2GK(A)-9EU, 78F0148M3GK(A)-9EU, PD78F0148M4GK(A)-9EU, 78F0148M5GK(A)-9EU, 78F0148M6GK(A)-9EU, 78F0148M1GK(A1)-9EU, PD78F0148M2GK(A1)-9EU, 78F0148M5GK(A1)-9EU, 78F0148M6GK(A1)-9EU Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Note Count: 2 times or less, Exposure limit: 3 days Recommended Condition Symbol IR35-103-2 (after that, prebake at 125C for 10 hours) VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Note Count: 2 times or less, Exposure limit: 3 days VP15-103-2 (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 610 User's Manual U15947EJ3V1UD CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS Table 35-1. Surface Mounting Type Soldering Conditions (3/3) (4) PD780143GC-xxx-8BT-A, 780144GC-xxx-8BT-A, 780146GC-xxx-8BT-A, 780148GC-xxx-8BT-A, PD780143GK-xxx-9EU-A, 780144GK-xxx-9EU-A, 780146GK-xxx-9EU-A, 780148GK-xxx-9EU-A, PD78F0148M1GC-8BT-A, 78F0148M2GC-8BT-A, 78F0148M3GC-8BT-A, PD78F0148M4GC-8BT-A, 78F0148M5GC-8BT-A, 78F0148M6GC-8BT-A, PD78F0148M1GK-9EU-A, 78F0148M2GK-9EU-A, 78F0148M3GK-9EU-A, PD78F0148M4GK-9EU-A, 78F0148M5GK-9EU-A, 78F0148M6GK-9EU-A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 7 days Note IR60-207-3 (after that, prebake at 125C for 20 to 72 hours) Wave soldering When the pin pitch of the package is 0.65 mm or more, wave soldering can also be performed. - For details, contact an NEC Electronics sales representative. Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark Products that have the part numbers suffixed by "-A" are lead-free products. User's Manual U15947EJ3V1UD 611 CHAPTER 36 CAUTIONS FOR WAIT 36.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Table 361). This must be noted when real-time processing is performed. 612 User's Manual U15947EJ3V1UD CHAPTER 36 CAUTIONS FOR WAIT 36.2 Peripheral Hardware That Generates Wait Table 36-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 36-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access Number of Wait Clocks Watchdog timer WDTM Write 3 clocks (fixed) Serial interface UART0 ASIS0 Read 1 clock (fixed) Serial interface UART6 ASIS6 Read 1 clock (fixed) A/D converter ADM Write 2 to 5 clocks ADS Write (when ADM.5 flag = "1") PFM Write PFT Write ADCR Read Note Note 2 to 9 clocks (when ADM.5 flag = "0") 1 to 5 clocks (when ADM.5 flag = "1") 1 to 9 clocks (when ADM.5 flag = "0") <Calculating maximum number of wait clocks> {(1/fMACRO) x 2/(1/fCPU)} + 1 *The result after the decimal point is truncated if it is less than tCPUL after it has been multiplied by (1/fCPU), and is rounded up if it exceeds tCPUL. fMACRO: Macro operating frequency 2 (When bit 5 (FR2) of ADM = "1": fX/2, when bit 5 (FR2) of ADM = "0": fX/2 ) fCPU: CPU clock frequency tCPUL: Low-level width of CPU clock Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1. Caution When the CPU is operating on the subsystem clock and the X1 input clock is stopped (MCC = 1), do not access the registers listed above using an access method in which a wait request is issued. Remark The clock is the CPU clock (fCPU). User's Manual U15947EJ3V1UD 613 CHAPTER 36 CAUTIONS FOR WAIT 36.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte> Number of execution clocks: 10 (7 clocks when data is written to a register that does not issue a wait (MOV sfr, #byte).) <2> Serial interface UART6 <On execution of MOV A, ASIS6> Number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).) <3> A/D converter Table 36-2. Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter) <On execution of MOV ADM, A; MOV ADS, A; or MOV A, ADCR> * When fX = 10 MHz, tCPUL = 50 ns Value of Bit 5 (FR2) 0 fX 9 clocks fX/2 1 Number of Wait Clocks fCPU of ADM Register 14 clocks 5 clocks 10 clocks fX/2 2 3 clocks 8 clocks fX/2 3 2 clocks fX/2 4 fX fX/2 fX/2 2 fX/2 3 fX/2 4 0 clocks (1 clock 7 clocks Note ) 10 clocks 3 clocks 8 clocks 2 clocks 0 clocks (1 clock 0 clocks (1 clock Note ) ) X1 input clock oscillation frequency tCPUL: Low-level width of CPU clock 614 ) 7 clocks Note The clock is the CPU clock (fCPU). fX: Note 5 clocks (6 clocks 5 clocks Note On execution of MOV A, ADCR Remark Number of Execution Clocks User's Manual U15947EJ3V1UD Note 5 clocks (6 clocks ) Note 5 clocks (6 clocks ) APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KF1. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * WindowsTM Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95 * Windows 98 * Windows NTTM Ver. 4.0 * Windows 2000 * Windows XP User's Manual U15947EJ3V1UD 615 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/3) (1) When using the in-circuit emulators IE-78K0-NS, IE-78K0-NS-A Software package * Software package Debugging software Language processing software * Assembler package * Integrated debugger * C compiler package * System simulator * Device file * C library source fileNote 1 Control software * Project manager (Windows only)Note 2 Host machine (PC or EWS) Interface adapter, PC card interface, etc. Power supply unit Flash memory write environment In-circuit emulatorNote 3 Emulation board Flash programmer Performance board Flash memory write adapter Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. 2. The C library source file is not included in the software package. The project manager PM plus is included in the assembler package. PM plus is only used for Windows. 3. 616 Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately. User's Manual U15947EJ3V1UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/3) (2) When using the in-circuit emulator IE-78K0K1-ET Software package * Software package Debugging software Language processing software * Assembler package * Integrated debugger * C compiler package * System simulator * Device file * C library source fileNote 1 Control software * Project manager (Windows only)Note 2 Host machine (PC or EWS) Interface adapter Power supply unit Flash memory write environment Flash programmer In-circuit emulatorNote 3 Flash memory write adapter Emulation probe Flash memory Conversion socket or conversion adapter Target system Notes 1. The C library source file is not included in the software package. 2. The project manager PM plus is included in the assembler package. 3. In-circuit emulator IE-78K0K1-ET is supplied with integrated debugger ID78K0-NS, a device file, power PM plus is only used for Windows. supply unit, and PCI bus interface adapter IE-70000-PCI-IF-A. Any other products are sold separately. User's Manual U15947EJ3V1UD 617 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (3/3) (3) When using the in-circuit emulator QB-78K0KX1H Software package * Software package Debugging software Language processing software * Assembler package * Integrated debugger * C compiler package * System simulator * Device file * C library source fileNote 1 Control software * Project manager (Windows only)Note 2 Host machine (PC or EWS) USB interface cable Power supply unit Flash memory write environment Flash programmer In-circuit emulatorNote 3 Flash memory write adapter Emulation probe Flash memory Conversion socket or conversion adapter Target system Notes 1. 2. The C library source file is not included in the software package. The project manager PM plus is included in the assembler package. PM plus is only used for Windows. 3. In-circuit emulator QB-78K0KX1H is supplied with integrated debugger ID78K0-QB, flash memory programmer PG-FPL (unsupported in the 78K0/Kx1 products), power supply unit, and USB interface cable. Any other products are sold separately. 618 User's Manual U15947EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package Part number: SxxxxSP78K0 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP78K0 xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software RA78K0 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780148) (sold separately). <Precaution when using RA78K0 in PC environment> This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxRA78K0 CC78K0 This compiler converts programs written in C language into object codes executable with C compiler package a microcontroller. This compiler should be used in combination with an assembler package and device file (both sold separately). <Precaution when using CC78K0 in PC environment> This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxCC78K0 Note 1 DF780148 This file contains information peculiar to the device. Device file This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0, ID78K0-NS, ID78K0, and ID78K0-QB) (all sold separately). The corresponding OS and host machine differ depending on the tool to be used. Part number: SxxxxDF780148 CC78K0-L Note 2 This is a source file of the functions that configure the object library included in the C C library source file compiler package. This file is required to match the object library included in the C compiler package to the user's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0-L Notes 1. The DF780148 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, ID78K0, and ID78K0-QB. 2. The CC78K0-L is not included in the software package (SP78K0). User's Manual U15947EJ3V1UD 619 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxRA78K0 SxxxxCC78K0 SxxxxCC78K0-L xxxx Host Machine AB17 PC-9800 series, BB17 IBM PC/AT compatibles 3P17 HP9000 series 700 3K17 SPARCstation OS Windows (Japanese version) TM TM Supply Medium CD-ROM Windows (English version) HP-UX TM SunOS TM TM Solaris (Rel. 10.10) (Rel. 4.1.4) (Rel. 2.5.1) SxxxxDF780148 xxxx Host Machine OS AB13 PC-9800 series, Windows (Japanese version) BB13 IBM PC/AT compatibles Windows (English version) Supply Medium 3.5-inch 2HD FD A.3 Control Software PM plus This is control software designed to enable efficient user program development in the Project manager Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from PM plus. <Caution> PM plus is included in the assembler package (RA78K0). It can only be used in Windows. A.4 Flash Memory Writing Tools Flashpro III Flash programmer dedicated to microcontrollers with on-chip flash memory. (part number: FL-PR3, PG-FP3) Flashpro IV (part number: FL-PR4, PG-FP4) Flash programmer FA-80GK-9EU FA-80GC-8BT Flash memory writing adapter used connected to the Flashpro III/Flashpro IV. * FA-80GK-9EU: For 80-pin plastic TQFP (GK-9EU type) Flash memory writing adapter * FA-80GC-8BT: For 80-pin plastic QFP (GC-8BT type) Remark FL-PR3, FL-PR4, FA-80GK-9EU, and FA-80GC-8BT are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 620 User's Manual U15947EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A Remark Operations where the oscillation frequencies exceed 10 MHz are only supported in IE-78K0-NS control code N or later, IE-78K0-NS-A control code G or later, and IE-780148-NS-EM1 control code E or later. IE-78K0-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. IE-78K0-NS-PA Performance board This board is connected to the IE-78K0-NS to expand its functions. Adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. IE-78K0-NS-A In-circuit emulator Product that combines the IE-78K0-NS and IE-78K0-NS-PA IE-70000-MC-PS-B Power supply unit This adapter is used for supplying power from a 100 V to 240 V AC outlet. IE-70000-98-IF-C Interface adapter This adapter is required when using a PC-9800 series computer (except notebook type) as the host machine (C bus compatible). IE-70000-CD-IF-A PC card interface This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). IE-70000-PC-IF-C Interface adapter This adapter is required when using an IBM PC/AT compatible computer as the host machine (ISA bus compatible). IE-70000-PCI-IF-A Interface adapter This adapter is required when using a computer with a PCI bus as the host machine. IE-780148-NS-EM1 Emulation board This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. NP-80GK NP-H80GK-TQ Emulation probe This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic TQFP (GK-9EU type). TGK-080SDW Conversion adapter NP-80GC Emulation probe This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic QFP (GC-8BT type). EV-9200GC-80 Conversion socket NP-80GC-TQ NP-H80GC-TQ Emulation probe This conversion adapter is used to connect the NP-80GK and target system board on which an 80-pin plastic TQFP (GK-9EU type) can be mounted. This conversion socket is used to connect the NP-80GC and target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic QFP (GC-8BT type). TGC-080SBP Conversion adapter This conversion adapter is used to connect the NP-80GC-TQ or NP-H80GC-TQ and a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. Remarks 1. NP-80GK, NP-H80GK-TQ, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. TGK-080SDW and TGC-080SBP are products of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 3. EV-9200GC-80 is sold in five-device units. 4. TGK-080SDW and TGC-080SBP are sold in individual units. User's Manual U15947EJ3V1UD 621 APPENDIX A DEVELOPMENT TOOLS A.5.2 When using in-circuit emulator IE-78K0K1-ET Remark Operations where the oscillation frequencies exceed 10 MHz are only supported in IE-78K0K1-ET control code C or later. Note IE-78K0K1-ET The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K0/Kx1 product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. IE-70000-98-IF-C This adapter is required when using a PC-9800 series computer (except notebook type) Interface adapter as the host machine (C bus compatible). IE-70000-CD-IF-A This is PC card and interface cable required when using a notebook-type computer as PC card interface the host machine (PCMCIA socket compatible). IE-70000-PC-IF-C This adapter is required when using an IBM PC/AT compatible computer as the host Interface adapter machine (ISA bus compatible). IE-70000-PCI-IF-A This adapter is required when using a computer with a PCI bus as the host machine. Interface adapter This is supplied with IE-78K0K1-ET. NP-80GK This probe is used to connect the in-circuit emulator and target system, and is designed NP-H80GK-TQ Emulation probe for an 80-pin plastic TQFP (GK-9EU type). TGK-080SDW This conversion adapter is used to connect the NP-80GK and target system board on Conversion which an 80-pin plastic TQFP (GK-9EU type) can be mounted. adapter NP-80GC This probe is used to connect the in-circuit emulator and target system, and is designed Emulation probe for an 80-pin plastic QFP (GC-8BT type). EV-9200GC-80 This conversion socket is used to connect the NP-80GC and target system board on Conversion which an 80-pin plastic QFP (GC-8BT type) can be mounted. socket NP-80GC-TQ This probe is used to connect the in-circuit emulator and target system, and is designed NP-H80GC-TQ for an 80-pin plastic QFP (GC-8BT type). Emulation probe TGC-080SBP This conversion adapter is used to connect the NP-80GC-TQ or NP-H80GC-TQ and a Conversion target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. adapter Note IE-78K0K1-ET is supplied with a power supply unit and PCI bus interface adapter IE-70000-PCI-IF-A. It is also supplied with integrated debugger ID78K0-NS and a device file as control software. Remarks 1. NP-80GK, NP-H80GK-TQ, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. TGK-080SDW and TGC-080SBP are products of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 3. EV-9200GC-80 is sold in five-device units. 4. TGK-080SDW and TGC-080SBP are sold in individual units. 622 User's Manual U15947EJ3V1UD APPENDIX A DEVELOPMENT TOOLS A.5.3 When using in-circuit emulator QB-78K0KX1H Note 1 QB-78K0KX1H The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using the 78K0/Kx1 or 78K0/Kx1+. It corresponds to the integrated debugger (ID78K0-QB). This emulator should be used in combination with a power supply unit and emulation probe. USB is used to connect this emulator to the host machine. Note 2 QB-144-CA-01 This adapter is used in waveform monitoring using the oscilloscope, etc. Check pin adapter QB-80-EP-01T This is a flexible type probe used to connect the in-circuit emulator to the target system. Emulation probe QB-80GK-EA-01T This adapter is used to perform the pin conversion from the in-circuit emulator to the QB-80GC-EA-01T target connector. Exchange adapter * QB-80GK-EA-01T: 80-pin plastic TQFP (GK-9EU type) * QB-80GC-EA-01T: 80-pin plastic QFP (GC-8BT type) QB-80GK-YS-01T This adapter is used to adjust the height between the target system and in-circuit QB-80GC-YS-01T emulator if required. Space adapter * QB-80GK-YS-01T: 80-pin plastic TQFP (GK-9EU type) * QB-80GC-YS-01T: 80-pin plastic QFP (GC-8BT type) QB-80GK-YQ-01T This connector is used to connect the target connector to the exchange adapter. QB-80GC-YQ-01T * QB-80GK-YQ-01T: 80-pin plastic TQFP (GK-9EU type) YQ connector * QB-80GC-YQ-01T: 80-pin plastic QFP (GC-8BT type) QB-80GK-HQ-01T This adapter is used to mount the target device onto the target device with socket. QB-80GC-HQ-01T * QB-80GK-HQ-01T: 80-pin plastic TQFP (GK-9EU type) Mount adapter * QB-80GC-HQ-01T: 80-pin plastic QFP (GC-8BT type) QB-80GK-NQ-01T This connector is used to mount the QB-78K0KX1H onto the target system. QB-80GC-NQ-01T * QB-80GK-NQ-01T: 80-pin plastic TQFP (GK-9EU type) Target connector * QB-80GC-NQ-01T: 80-pin plastic QFP (GC-8BT type) Notes 1. QB-78K0KX1H is supplied with a power supply unit, USB interface cable, and flash memory programmer PG-FPL (unsupported in the 78K0/Kx1 products). It is also supplied with integrated debugger ID78K0-QB as control software. 2. Remark Under development The package contents differ depending on the part number. * QB-78K0KX1H-ZZZ: In-circuit emulator only * QB-78K0KX1H-T80GK, QB-78K0KX1H-T80GC: In-circuit emulator and accessories (emulation probe, exchange adapter, YQ connector, target connector). User's Manual U15947EJ3V1UD 623 APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based System simulator software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with the device file (DF780148) (sold separately). Part number: SxxxxSM78K0 ID78K0-NS This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS (supporting in-circuit emulators and ID78K0-QB are Windows-based software. IE-78K0-NS, IE-78K0-NS-A, and It has improved C-compatible debugging functions and can display the results of tracing IE-78K0K1-ET), with the source program using an integrating window function that associates the source ID78K0-QB (supporting in-circuit program, disassemble display, and memory display with the trace result. It should be emulator QB-78K0KX1H) used in combination with the device file (sold separately). Integrated debugger Part number: SxxxxID78K0-NS, SxxxxID78K0-QB Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSM78K0 SxxxxID78K0-NS SxxxxID78K0-QB xxxx 624 Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) User's Manual U15947EJ3V1UD Supply Medium CD-ROM APPENDIX B NOTES ON TARGET SYSTEM DESIGN B.1 When Using IE-78K0-NS, IE-78K0-NS-A, or IE-78K0K1-ET The following shows a diagram of the connection conditions between the emulation probe and conversion adapter. Design your system making allowances for conditions such as the shape of parts mounted on the target system, as shown below. Table B-1. Distance Between IE System and Conversion Adapter Emulation Probe Conversion Adapter Distance Between IE System and Conversion Adapter NP-80GC EV-9200GC-80 170 mm NP-80GC-TQ TGC-080SBP 170 mm NP-H80GC-TQ 370 mm NP-80GK TGK-080SDW NP-H80GK-TQ 170 mm 370 mm Figure B-1. Distance Between IE System and Conversion Adapter In-circuit emulator IE-78K0-NS, IE-78K0-NS-A, or IE-78K0K1-ET Target system Emulation board IE-780148-NS-EM1 170 mmNote CN6 Emulation probe NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, NP-H80GK-TQ Conversion adapter EV-9200GC-80, TGC-080SBP, TGK-080SDW Note Distance when using NP-80GC, NP-80GC-TQ, and NP-80GK. This is 370 mm when using NP-H80GC-TQ and NP-H80GK-TQ. Remark The NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, and NP-H80GK-TQ are products of Naito Densei Machida Mfg. Co., Ltd. The TGC-080SBP and TGK-080SDW are products of TOKYO ELETECH CORPORATION. User's Manual U15947EJ3V1UD 625 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When Using NP-80GC-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-80GC-TQ 24.8 mm Conversion adapter TGC-080SBP 11 mm 25 mm 21 mm 40 mm 21 mm 34 mm Target system 626 User's Manual U15947EJ3V1UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-3. Connection Conditions of Target System (When Using NP-H80GC-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-H80GC-TQ 25.3 mm Conversion adapter TGC-080SBP 11 mm 25 mm 21 mm 42 mm 21 mm 45 mm Target system User's Manual U15947EJ3V1UD 627 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-4. Connection Conditions of Target System (When Using NP-80GK) Emulation board IE-780148-NS-EM1 Emulation probe NP-80GK 23 mm Conversion adapter TGK-080SDW 11 mm 18 mm 40 mm 18 mm 34 mm Target system 628 User's Manual U15947EJ3V1UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-5. Connection Conditions of Target System (When Using NP-H80GK-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-H80GK-TQ 23 mm Conversion adapter TGK-080SDW 11 mm 18 mm 42 mm 18 mm 45 mm Target system User's Manual U15947EJ3V1UD 629 APPENDIX B NOTES ON TARGET SYSTEM DESIGN B.2 When Using QB-78K0KX1H The following shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions. (a) 80-pin GK package 15 10.5 10 10.5 10 Figure B-6. Restricted Area on Target System (80-Pin GK Package) 15 13.375 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note Height can be regulated by using space adapters (each adds 2.4 mm) (b) 80-pin GC package 15 13.375 22.05 10 10 15 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note Height can be regulated by using space adapters (each adds 2.4 mm) 630 22.05 Figure B-7. Restricted Area on Target System (80-Pin GC Package) User's Manual U15947EJ3V1UD APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D conversion result register (ADCR) .......................................................................................................................275 A/D converter mode register (ADM)............................................................................................................................272 Analog input channel specification register (ADS) ......................................................................................................274 Asynchronous serial interface control register 6 (ASICL6)..........................................................................................324 Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................294 Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................318 Asynchronous serial interface reception error status register 0 (ASIS0).....................................................................296 Asynchronous serial interface reception error status register 6 (ASIS6).....................................................................320 Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................321 Automatic data transfer address count register 0 (ADTC0) ........................................................................................372 Automatic data transfer address point specification register 0 (ADTP0) .....................................................................377 Automatic data transfer interval specification register 0 (ADTI0) ................................................................................379 [B] Baud rate generator control register 0 (BRGC0).........................................................................................................297 Baud rate generator control register 6 (BRGC6).........................................................................................................323 [C] Capture/compare control register 00 (CRC00)............................................................................................................166 Capture/compare control register 01 (CRC01)............................................................................................................166 Clock monitor mode register (CLM) ............................................................................................................................461 Clock output selection register (CKS) .........................................................................................................................264 Clock selection register 6 (CKSR6).............................................................................................................................322 [D] Divisor selection register 0 (BRGCA0)........................................................................................................................377 [E] 8-bit timer compare register 50 (CR50).......................................................................................................................204 8-bit timer compare register 51 (CR51).......................................................................................................................204 8-bit timer counter 50 (TM50)......................................................................................................................................203 8-bit timer counter 51 (TM51)......................................................................................................................................203 8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................228 8-bit timer H compare register 00 (CMP00) ................................................................................................................222 8-bit timer H compare register 01 (CMP01) ................................................................................................................222 8-bit timer H compare register 10 (CMP10) ................................................................................................................222 8-bit timer H compare register 11 (CMP11) ................................................................................................................222 8-bit timer H mode register 0 (TMHMD0)....................................................................................................................223 8-bit timer H mode register 1 (TMHMD1)....................................................................................................................223 8-bit timer mode control register 50 (TMC50) .............................................................................................................207 8-bit timer mode control register 51 (TMC51) .............................................................................................................207 User's Manual U15947EJ3V1UD 631 APPENDIX C REGISTER INDEX External interrupt falling edge enable register (EGN)..................................................................................................428 External interrupt rising edge enable register (EGP)...................................................................................................428 [I] Input switch control register (ISC) ...............................................................................................................................325 Internal expansion RAM size switching register (IXS).................................................................................................488 Internal memory size switching register (IMS).............................................................................................................487 Internal oscillation mode register (RCM) .....................................................................................................................134 Interrupt mask flag register 0H (MK0H).......................................................................................................................426 Interrupt mask flag register 0L (MK0L) ........................................................................................................................426 Interrupt mask flag register 1H (MK1H).......................................................................................................................426 Interrupt mask flag register 1L (MK1L) ........................................................................................................................426 Interrupt request flag register 0H (IF0H) .....................................................................................................................425 Interrupt request flag register 0L (IF0L).......................................................................................................................425 Interrupt request flag register 1H (IF1H) .....................................................................................................................425 Interrupt request flag register 1L (IF1L).......................................................................................................................425 [K] Key return mode register (KRM) .................................................................................................................................438 [L] Low-voltage detection level selection register (LVIS)..................................................................................................474 Low-voltage detection register (LVIM).........................................................................................................................472 [M] Main clock mode register (MCM) ................................................................................................................................135 Main OSC control register (MOC) ...............................................................................................................................136 Memory expansion mode register (MEM) ...................................................................................................................121 Memory expansion wait setting register (MM).............................................................................................................123 Multiplication/division data register A0 (MDA0H, MDA0L) ..........................................................................................412 Multiplication/division data register B0 (MDB0) ...........................................................................................................413 Multiplier/divider control register 0 (DMUC0)...............................................................................................................414 [O] Oscillation stabilization time counter status register (OSTC)...............................................................................137, 441 Oscillation stabilization time select register (OSTS)............................................................................................138, 442 [P] Port mode register 0 (PM0) .........................................................................................................................112, 173, 357 Port mode register 1 (PM1) .................................................................................................112, 209, 228, 298, 325, 357 Port mode register 12 (PM12) .....................................................................................................................................112 Port mode register 14 (PM14) .....................................................................................................................112, 266, 380 Port mode register 3 (PM3) .................................................................................................................................112, 209 Port mode register 4 (PM4) .........................................................................................................................................112 Port mode register 5 (PM5) .........................................................................................................................................112 Port mode register 6 (PM6) .........................................................................................................................................112 Port mode register 7 (PM7) .........................................................................................................................................112 Port register 0 (P0)......................................................................................................................................................115 Port register 1 (P1)......................................................................................................................................................115 632 User's Manual U15947EJ3V1UD APPENDIX C REGISTER INDEX Port register 12 (P12)..................................................................................................................................................115 Port register 13 (P13)..................................................................................................................................................115 Port register 14 (P14)..................................................................................................................................................115 Port register 2 (P2)......................................................................................................................................................115 Port register 3 (P3)......................................................................................................................................................115 Port register 4 (P4)......................................................................................................................................................115 Port register 5 (P5)......................................................................................................................................................115 Port register 6 (P6)......................................................................................................................................................115 Port register 7 (P7)......................................................................................................................................................115 Power-fail comparison mode register (PFM)...............................................................................................................276 Power-fail comparison threshold register (PFT)..........................................................................................................276 Prescaler mode register 00 (PRM00)..........................................................................................................................170 Prescaler mode register 01 (PRM01)..........................................................................................................................170 Priority specification flag register 0H (PR0H) ..............................................................................................................427 Priority specification flag register 0L (PR0L) ...............................................................................................................427 Priority specification flag register 1H (PR1H) ..............................................................................................................427 Priority specification flag register 1L (PR1L) ...............................................................................................................427 Processor clock control register (PCC) .......................................................................................................................132 Pull-up resistor option register 0 (PU0) .......................................................................................................................116 Pull-up resistor option register 1 (PU1) .......................................................................................................................116 Pull-up resistor option register 12 (PU12) ...................................................................................................................116 Pull-up resistor option register 14 (PU14) ...................................................................................................................116 Pull-up resistor option register 3 (PU3) .......................................................................................................................116 Pull-up resistor option register 4 (PU4) .......................................................................................................................116 Pull-up resistor option register 5 (PU5) .......................................................................................................................116 Pull-up resistor option register 6 (PU6) .......................................................................................................................116 Pull-up resistor option register 7 (PU7) .......................................................................................................................116 [R] Receive buffer register 0 (RXB0) ................................................................................................................................293 Receive buffer register 6 (RXB6) ................................................................................................................................317 Remainder data register 0 (SDR0)..............................................................................................................................411 Reset control flag register (RESF) ..............................................................................................................................459 [S] Serial clock selection register 10 (CSIC10).................................................................................................................354 Serial clock selection register 11 (CSIC11).................................................................................................................354 Serial I/O shift register 0 (SIOA0)................................................................................................................................372 Serial I/O shift register 10 (SIO10) ..............................................................................................................................351 Serial I/O shift register 11 (SIO11) ..............................................................................................................................351 Serial operation mode register 10 (CSIM10)...............................................................................................................352 Serial operation mode register 11 (CSIM11)...............................................................................................................352 Serial operation mode specification register 0 (CSIMA0)............................................................................................373 Serial status register 0 (CSIS0)...................................................................................................................................374 Serial trigger register 0 (CSIT0) ..................................................................................................................................376 16-bit timer capture/compare register 000 (CR000)....................................................................................................160 16-bit timer capture/compare register 001 (CR001)....................................................................................................160 16-bit timer capture/compare register 010 (CR010)....................................................................................................162 User's Manual U15947EJ3V1UD 633 APPENDIX C REGISTER INDEX 16-bit timer capture/compare register 011 (CR011) ....................................................................................................162 16-bit timer counter 00 (TM00)....................................................................................................................................160 16-bit timer counter 01 (TM01)....................................................................................................................................160 16-bit timer mode control register 00 (TMC00)............................................................................................................163 16-bit timer mode control register 01 (TMC01)............................................................................................................163 16-bit timer output control register 00 (TOC00)...........................................................................................................167 16-bit timer output control register 01 (TOC01)...........................................................................................................167 [T] Timer clock selection register 50 (TCL50)...................................................................................................................205 Timer clock selection register 51 (TCL51)...................................................................................................................205 Transmit buffer register 10 (SOTB10) .........................................................................................................................351 Transmit buffer register 11 (SOTB11) .........................................................................................................................351 Transmit buffer register 6 (TXB6)................................................................................................................................317 Transmit shift register 0 (TXS0) ..................................................................................................................................293 [W] Watch timer operation mode register (WTM) ..............................................................................................................247 Watchdog timer enable register (WDTE).....................................................................................................................257 Watchdog timer mode register (WDTM)......................................................................................................................255 634 User's Manual U15947EJ3V1UD APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: A/D conversion result register ..............................................................................................................275 ADM: A/D converter mode register.................................................................................................................272 ADS: Analog input channel specification register ..........................................................................................274 ADTC0: Automatic data transfer address count register 0 .................................................................................372 ADTI0: Automatic data transfer interval specification register 0 .......................................................................379 ADTP0: Automatic data transfer address point specification register 0 .............................................................377 ASICL6: Asynchronous serial interface control register 6...................................................................................324 ASIF6: Asynchronous serial interface transmission status register 6 ...............................................................321 ASIM0: Asynchronous serial interface operation mode register 0.....................................................................294 ASIM6: Asynchronous serial interface operation mode register 6.....................................................................318 ASIS0: Asynchronous serial interface reception error status register 0............................................................296 ASIS6: Asynchronous serial interface reception error status register 6............................................................320 [B] BRGCA0: Divisor selection register 0 ...................................................................................................................377 BRGC0: Baud rate generator control register 0 ..................................................................................................297 BRGC6: Baud rate generator control register 6 ..................................................................................................323 [C] CKS: Clock output selection register .............................................................................................................264 CKSR6: Clock selection register 6 .....................................................................................................................322 CLM: Clock monitor mode register.................................................................................................................461 CMP00: 8-bit timer H compare register 00 .........................................................................................................222 CMP01: 8-bit timer H compare register 01 .........................................................................................................222 CMP10: 8-bit timer H compare register 10 .........................................................................................................222 CMP11: 8-bit timer H compare register 11 .........................................................................................................222 CR000: 16-bit timer capture/compare register 000............................................................................................160 CR001: 16-bit timer capture/compare register 001............................................................................................160 CR010: 16-bit timer capture/compare register 010............................................................................................162 CR011: 16-bit timer capture/compare register 011............................................................................................162 CR50: 8-bit timer compare register 50.............................................................................................................204 CR51: 8-bit timer compare register 51.............................................................................................................204 CRC00: Capture/compare control register 00 ....................................................................................................166 CRC01: Capture/compare control register 01 ....................................................................................................166 CSIC10: Serial clock selection register 10 ..........................................................................................................354 CSIC11: Serial clock selection register 11 ..........................................................................................................354 CSIM10: Serial operation mode register 10 ........................................................................................................352 CSIM11: Serial operation mode register 11 ........................................................................................................352 CSIMA0: Serial operation mode specification register 0......................................................................................373 CSIS0: Serial status register 0..........................................................................................................................374 CSIT0: Serial trigger register 0 .........................................................................................................................376 [D] DMUC0: Multiplier/divider control register 0........................................................................................................414 User's Manual U15947EJ3V1UD 635 APPENDIX C REGISTER INDEX [E] EGN: External interrupt falling edge enable register ......................................................................................428 EGP: External interrupt rising edge enable register .......................................................................................428 [I] IF0H: Interrupt request flag register 0H ..........................................................................................................425 IF0L: Interrupt request flag register 0L...........................................................................................................425 IF1H: Interrupt request flag register 1H ..........................................................................................................425 IF1L: Interrupt request flag register 1L...........................................................................................................425 IMS: Internal memory size switching register................................................................................................487 ISC: Input switch control register ..................................................................................................................325 IXS: Internal expansion RAM size switching register....................................................................................488 [K] KRM: Key return mode register ......................................................................................................................438 [L] LVIM: Low-voltage detection register ..............................................................................................................472 LVIS: Low-voltage detection level selection register ......................................................................................474 [M] MCM: Main clock mode register......................................................................................................................135 MDA0H: Multiplication/division data register A0..................................................................................................412 MDA0L: Multiplication/division data register A0..................................................................................................412 MDB0: Multiplication/division data register B0..................................................................................................413 MEM: Memory expansion mode register.........................................................................................................121 MK0H: Interrupt mask flag register 0H .............................................................................................................426 MK0L: Interrupt mask flag register 0L ..............................................................................................................426 MK1H: Interrupt mask flag register 1H .............................................................................................................426 MK1L: Interrupt mask flag register 1L ..............................................................................................................426 MM: Memory expansion wait setting register................................................................................................123 MOC: Main OSC control register ....................................................................................................................136 [O] OSTC: Oscillation stabilization time counter status register .....................................................................137, 441 OSTS: Oscillation stabilization time select register ..................................................................................138, 442 [P] P0: Port register 0 .......................................................................................................................................115 P1: Port register 1 .......................................................................................................................................115 P12: Port register 12 .....................................................................................................................................115 P13: Port register 13 .....................................................................................................................................115 P14: Port register 14 .....................................................................................................................................115 P2: Port register 2 .......................................................................................................................................115 P3: Port register 3 .......................................................................................................................................115 P4: Port register 4 .......................................................................................................................................115 P5: Port register 5 .......................................................................................................................................115 P6: Port register 6 .......................................................................................................................................115 636 User's Manual U15947EJ3V1UD APPENDIX C REGISTER INDEX P7: Port register 7.......................................................................................................................................115 PCC: Processor clock control register ...........................................................................................................132 PFM: Power-fail comparison mode register ...................................................................................................276 PFT: Power-fail comparison threshold register .............................................................................................276 PM0: Port mode register 0 ............................................................................................................. 112, 173, 357 PM1: Port mode register 1 ..................................................................................... 112, 209, 228, 298, 325, 357 PM12: Port mode register 12 ...........................................................................................................................112 PM14: Port mode register 14 ........................................................................................................... 112, 266, 380 PM3: Port mode register 3 .....................................................................................................................112, 209 PM4: Port mode register 4 .............................................................................................................................112 PM5: Port mode register 5 .............................................................................................................................112 PM6: Port mode register 6 .............................................................................................................................112 PM7: Port mode register 7 .............................................................................................................................112 PR0H: Priority specification flag register 0H ....................................................................................................427 PR0L: Priority specification flag register 0L .....................................................................................................427 PR1H: Priority specification flag register 1H ....................................................................................................427 PR1L: Priority specification flag register 1L .....................................................................................................427 PRM00: Prescaler mode register 00 ..................................................................................................................170 PRM01: Prescaler mode register 01 ..................................................................................................................170 PU0: Pull-up resistor option register 0...........................................................................................................116 PU1: Pull-up resistor option register 1...........................................................................................................116 PU12: Pull-up resistor option register 12.........................................................................................................116 PU14: Pull-up resistor option register 14.........................................................................................................116 PU3: Pull-up resistor option register 3...........................................................................................................116 PU4: Pull-up resistor option register 4...........................................................................................................116 PU5: Pull-up resistor option register 5...........................................................................................................116 PU6: Pull-up resistor option register 6...........................................................................................................116 PU7: Pull-up resistor option register 7...........................................................................................................116 [R] RCM: Internal oscillation mode register..........................................................................................................134 RESF: Reset control flag register.....................................................................................................................459 RXB0: Receive buffer register 0 ......................................................................................................................293 RXB6: Receive buffer register 6 ......................................................................................................................317 [S] SDR0: Remainder data register 0 ....................................................................................................................411 SIO10: Serial I/O shift register 10 .....................................................................................................................351 SIO11: Serial I/O shift register 11 .....................................................................................................................351 SIOA0: Serial I/O shift register 0 .......................................................................................................................372 SOTB10: Transmit buffer register 10 ...................................................................................................................351 SOTB11: Transmit buffer register 11 ...................................................................................................................351 [T] TCL50: Timer clock selection register 50 ..........................................................................................................205 TCL51: Timer clock selection register 51 ..........................................................................................................205 TM00: 16-bit timer counter 00..........................................................................................................................160 TM01: 16-bit timer counter 01..........................................................................................................................160 User's Manual U15947EJ3V1UD 637 APPENDIX C REGISTER INDEX TM50: 8-bit timer counter 50............................................................................................................................203 TM51: 8-bit timer counter 51............................................................................................................................203 TMC00: 16-bit timer mode control register 00 ....................................................................................................163 TMC01: 16-bit timer mode control register 01 ....................................................................................................163 TMC50: 8-bit timer mode control register 50 ......................................................................................................207 TMC51: 8-bit timer mode control register 51 ......................................................................................................207 TMCYC1: 8-bit timer H carrier control register 1 ...................................................................................................228 TMHMD0: 8-bit timer H mode register 0 ................................................................................................................223 TMHMD1: 8-bit timer H mode register 1 ................................................................................................................223 TOC00: 16-bit timer output control register 00 ...................................................................................................167 TOC01: 16-bit timer output control register 01 ...................................................................................................167 TXB6: Transmit buffer register 6......................................................................................................................317 TXS0: Transmit shift register 0 ........................................................................................................................293 [W] WDTE: Watchdog timer enable register ............................................................................................................257 WDTM: Watchdog timer mode register..............................................................................................................255 WTM: Watch timer operation mode register....................................................................................................247 638 User's Manual U15947EJ3V1UD APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. "Classification (hard/soft)" in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs Hard Classification Chapter 1 Chapter (1/23) Function Operating frequency rating Details of Function Hard Soft Soft Hard Soft Chapter 2 Chapter 3 Chapter 4 Memory space Port functions Page Peripheral function: Count clock, base clock The specifications of the peripheral functions (timer, serial interface, A/D converter, etc.) are conventional when operating at VDD = 2.7 to 5.5 V. Therefore, to select the count clock or base clock of a peripheral function, satisfy the following conditions. * VDD = 4.0 to 5.5 V: Count clock or base clock 10 MHz * VDD = 3.3 to 4.0 V: Count clock or base clock 8.38 MHz * VDD = 2.7 to 3.3 V: Count clock or base clock 5 MHz * VDD = 2.5 to 2.7 V: Count clock or base clock 2.5 MHz p. 18 Flash memory Rewrite the flash memory in the ranges of fX = 2 to 10 MHz and VDD = 2.7 to 5.5 V as ever. p. 18 Connect the IC (Internally Connected) pin directly to VSS. p. 24 Connect the AVSS pin to VSS. p. 24 - Pin connection Pin functions Cautions Connect the REGC pin as follows. p. 24 Connect the VPP pin to EVSS or VSS during normal operation. p. 24 Ports 4, 5, 6 The external bus interface function cannot be used in (A1) grade products and (A2) grade products. pp. 42, 43 P66 P66 functions as an I/O port if the external wait is not used in external memory expansion mode. p. 43 REGC pin A regulator cannot be used with (A1) grade products and (A2) grade products. Be sure to connect the REGC pin of these products directly to VDD. p. 45 IMS: Internal memory size switching register, IXS: Internal expansion RAM size switching register Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all 78K0/KF1 products are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. p. 50 SFR area: Do not access addresses to which SFRs are not assigned. Special function register p. 57 SP: Stack pointer Since RESET input makes the SP contents undefined, be sure to initialize the SP before using the stack. p. 64 P02, P03, P04 When P02/SO11, P03/SI11, and P04/SCK11 are used as general-purpose ports, do not write to serial clock selection register 11 (CSIC11). p. 88 P10, P11, P12 When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as generalpurpose ports, do not write to serial clock selection register 10 (CSIC10). p. 92 P66 P66 can be used as an I/O port when an external wait is not used in external memory expansion mode. p. 102 P60 to P63 Use of a pull-up resistor can be specified for P60 to P63 pins by a mask option only in the mask ROM versions. p. 116 In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. p. 117 - User's Manual U15947EJ3V1UD 639 APPENDIX D LIST OF CAUTIONS Hard Classification External bus interface - p. 118 When the external wait function is not used, the WAIT pin can be used as a port in p. 118 all modes. To control wait with external wait pin, be sure to set WAIT/P66 pin to input mode (set bit 6 (PM66) of port mode register 6 (PM6) to 1). p. 123 If the external wait pin is not used for wait control, the WAIT/P66 pin can be used as an I/O port pin. p. 123 Be sure to clear bit 3 to 0. PCC: Processor clock control register (PCC) p. 133 RCM: Internal oscillation mode register Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting RSTOP. p. 134 Main clock MCM: Main clock mode register When internal oscillation clock is selected as the clock to be supplied to the CPU, the divided clock of the internal oscillator output (fX) is supplied to the peripheral hardware (fX = 240 kHz (TYP.)). Operation of the peripheral hardware with internal oscillation clock cannot be guaranteed. Therefore, when internal oscillation clock is selected as the clock supplied to the CPU, do not use peripheral hardware. In addition, stop the peripheral hardware before switching the clock supplied to the CPU from the X1 input clock to the internal oscillation clock. Note, however, that the following peripheral hardware can be used when the CPU operates on the internal oscillation clock. * Watchdog timer * Clock monitor 7 * 8-bit timer H1 when fR/2 is selected as count clock * Peripheral hardware selecting external clock as the clock source (Except when external count clock of TM0n (n = 0, 1) is selected (TI00n valid edge)) p. 135 Subsystem clock Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1 input clock operation (bit 4 (CSS) of the processor clock control register (PCC) is changed from 1 to 0). p. 135 Main clock MOC: Main OSC control Subsystem register Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting MSTOP. p. 136 Internal oscillator clock Main clock OSTC: Oscillation stabilization time counter status register To stop X1 oscillation when the CPU is operating on the subsystem clock, set bit 7 p. 136 (MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is not possible). After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 137 If the STOP mode is entered and then released while the internal oscillation clock p. 137 is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. The wait time when STOP mode is released does not include the time after STOP p. 137 mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. Hard Soft 640 The external bus interface function cannot be used in (A1) grade products and (A2) grade products. Page Hard Soft Hard - Cautions Soft Chapter 6 Details of Function MM: Memory expansion wait setting register Soft Chapter 5 Chapter (2/23) Function OSTS: Oscillation stabilization time select register To set the STOP mode while the X1 input clock is used as the CPU clock, set OSTS before executing the STOP instruction. p. 138 Before setting OSTS, confirm with OSTC that the desired oscillation stabilization time has elapsed. p. 138 User's Manual U15947EJ3V1UD APPENDIX D LIST OF CAUTIONS Soft Classification Main clock Details of Function OSTS: Oscillation stabilization time select register Soft Soft Hard Chapter 7 Cautions If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. Page p. 138 The wait time when STOP mode is released does not include the time after STOP p. 138 mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. Hard Chapter 6 Chapter (3/23) Function X1 oscillator, subsystem clock oscillator - When using the X1 oscillator and subsystem clock oscillator, wire as follows in the p. 140 area enclosed by the broken lines in Figures 6-8 and 6-9 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. Prescaler - When the internal oscillation clock is selected as the clock supplied to the CPU, the prescaler generates various clocks by dividing the internal oscillator output (fX = 240 kHz (TYP.)). p. 142 Internal oscillator - The RSTOP setting is valid only when "Can be stopped by software" is set for internal oscillator by a mask option. p. 149 To calculate the maximum time, set fR = 120 kHz. p. 150 CPU clock - 16-bit timer/ event counters 00, 01 (TM00, TM01) CR00n: 16-bit timer capture/ compare register 00n p. 151 Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1 input clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS from 1 to 0). Setting the following values is prohibited when the CPU operates on the internal oscillation clock. * CSS, PCC2, PCC1, PCC0 = 0, 0, 0, 1 (settable only for standard products and (A) grade products) * CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 0 * CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 1 * CSS, PCC2, PCC1, PCC0 = 0, 1, 0, 0 p. 151 Set a value other than 0000H to CR00n in the mode in which clear & start occurs on a match of TM0n and CR00n. p. 161 If CR00n is set to 0000H in the free-running mode and in the clear mode using the p. 161 valid edge of the TI00n pin, an interrupt request (INTTM00n) is generated when the value of CR00n changes from 0000H to 0001H following TM0n overflow (FFFFH). Moreover, INTTM00n is generated after a match of TM0n and CR00n is detected, a valid edge of the TI01n pin is detected, or the timer is cleared by a one-shot trigger. When the valid edge of the TI01n pin is used, P01 or P06 cannot be used as the timer output (TO0n) pin. Moreover, when the TO0n pin is used, the valid edge of the TI01n pin cannot be used. User's Manual U15947EJ3V1UD p. 161 641 APPENDIX D LIST OF CAUTIONS Hard Classification Page p. 161 Do not rewrite CR00n during TM0n operation. pp. 161, 174, 179, 191 If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated when the value changes from 0000H to 0001H after an overflow (FFFFH) of TM0n. Moreover, INTTM01n is generated after a match of TM0n and CR01n is detected, a valid edge of the TI00n pin is detected, or the timer is cleared by a one-shot trigger. p. 162 When CR01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. p. 162 CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 7-20. p. 162 TMC0n: 16-bit timer mode control register 0n 16-bit timer counter 0n (TM0n) starts operation at the moment TMC0n2 and TMC0n3 are set to values other than 0, 0 (operation stop mode), respectively. Clear TMC0n2 and TMC0n3 to 0, 0 to stop the operation. p. 163 TMC00: 16-bit timer mode control register 00 Timer operation must be stopped before writing to bits other than the OVF00 flag. p. 164 Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00). p. 164 Soft When CR00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If timer count stop and capture trigger input conflict, the captured data is undefined. 16-bit timer/ event counters 00, 01 (TM00, TM01) CR00n: 16-bit timer capture/ compare register 00n CR01n: 16-bit timer capture/ compare register 01n TMC01: 16-bit timer mode control register 01 Hard Soft Hard CRC00: Capture/ compare control register 00 642 Cautions Hard Details of Function Soft Chapter 7 Chapter (4/23) Function CRC01: Capture/ compare control register 01 p. 164 If any of the following modes is selected: the mode in which clear & start occurs on match between TM00 and CR000, the mode in which clear & start occurs at the TI000 valid edge, or free-running mode, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. Timer operation must be stopped before writing to bits other than the OVF01 flag. p. 165 Set the valid edge of the TI001/P05 pin using prescaler mode register 01 (PRM01). p. 165 p. 165 If any of the following modes is selected: the mode in which clear & start occurs on match between TM01 and CR001, the mode in which clear & start occurs at the TI001 valid edge, or free-running mode, when the set value of CR001 is FFFFH and the TM01 value changes from FFFFH to 0000H, the OVF01 flag is set to 1. Timer operation must be stopped before setting CRC00. p. 166 When the mode in which clear & start occurs on a match between TM00 and CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. p. 166 To ensure that the capture operation is performed properly, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00). p. 166 Timer operation must be stopped before setting CRC01. p. 167 When the mode in which clear & start occurs on a match between TM01 and CR001 is selected with 16-bit timer mode control register 01 (TMC01), CR001 should not be specified as a capture register. p. 167 To ensure that the capture operation is performed properly, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 01 (PRM01). p. 167 User's Manual U15947EJ3V1UD APPENDIX D LIST OF CAUTIONS Soft Classification Soft Hard 16-bit timer/ event counters 00, 01 (TM00, TM01) Details of Function TOC00: 16-bit timer output control register 00 Hard Soft Hard Soft Hard TOC01: 16-bit timer output control register 01 Cautions Page Timer operation must be stopped before setting other than TOC004. p. 168 If LVS00 and LVR00 are read, 0 is read. p. 168 OSPT00 is automatically cleared after data is set, so 0 is read. p. 168 Do not set OSPT00 to 1 other than in one-shot pulse output mode. p. 168 A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required to write to OSPT00 successively. p. 168 Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously. p. 168 Perform <1> and <2> below in the following order, not at the same time. <1> Set TOC001, TOC004, TOE00, OSPE00: Timer output operation setting <2> Set LVS00, LVR00: Timer output F/F setting p. 168 Timer operation must be stopped before setting other than TOC014. p. 169 If LVS01 and LVR01 are read, 0 is read. p. 169 OSPT01 is automatically cleared after data is set, so 0 is read. p. 169 Do not set OSPT01 to 1 other than in one-shot pulse output mode. p. 169 A write interval of two cycles or more of the count clock selected by prescaler mode register 01 (PRM01) is required to write to OSPT01 successively. p. 169 Do not set LVS01 to 1 before TOE01, and do not set LVS01 and TOE01 to 1 simultaneously. p. 169 Perform <1> and <2> below in the following order, not at the same time. <1> Set TOC011, TOC014, TOE01, OSPE01: Timer output operation setting <2> Set LVS01, LVR01: Timer output F/F setting p. 169 p. 171 PRM00: When the internal oscillation clock is selected as the clock to be supplied to the Prescaler mode CPU, the clock of the internal oscillator is divided and supplied as the count clock. register 00 If the count clock is the internal oscillation clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an external clock is used and when the internal oscillation clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to eliminate noise. Always set data to PRM00 after stopping the timer operation. p. 171 If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI000 and the capture trigger. p. 171 If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, if the TI000 pin or TI010 pin is high level when re-enabling operation after the operation has been stopped, the rising edge is not detected. p. 171 When the valid edge of the TI010 pin is used, P01 cannot be used as the timer output (TO00) pin. Moreover, when the TO00 pin is used, the valid edge of the TI010 pin cannot be used. p. 171 PRM01: p. 172 When the internal oscillation clock is selected as the clock to be supplied to the Prescaler mode CPU, the clock of the internal oscillator is divided and supplied as the count clock. register 01 If the count clock is the internal oscillation clock, the operation of 16-bit timer/event counter 01 is not guaranteed. When an external clock is used and when the internal oscillation clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 01 is not guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to eliminate noise. Soft Chapter 7 Chapter (5/23) Function Always set data to PRM01 after stopping the timer operation. p. 172 If the valid edge of TI001 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI001 and the capture trigger. p. 172 User's Manual U15947EJ3V1UD 643 APPENDIX D LIST OF CAUTIONS Soft Classification 16-bit timer/ event counters 00, 01 (TM00, TM01) Details of Function Soft Cautions PRM01: If the TI001 or TI011 pin is high level immediately after system reset, the rising Prescaler mode edge is immediately detected after the rising edge or both the rising and falling register 01 edges are set as the valid edge(s) of the TI001 pin or TI011 pin to enable the operation of 16-bit timer counter 01 (TM01). Care is therefore required when pulling up the TI001 or TI011 pin. However, if the TI001 pin or TI011 pin is high level when re-enabling operation after the operation has been stopped, the rising edge is not detected. Page p. 172 When the valid edge of the TI011 pin is used, P06 cannot be used as the timer output (TO01) pin. Moreover, when the TO01 pin is used, the valid edge of the TI011 pin cannot be used. p. 172 CR01n: 16-bit timer capture/ compare register 01n To change the value of the duty factor (the value of the CR01n register) during operation, see Caution 2 in Figure 7-20 PPG Output Operation Timing. p. 177 CR00n, CR01n: 16-bit timer capture/compare registers 00n, 01n Values in the following range should be set in CR00n and CR01n: 0000H CR01n < CR00n FFFFH p. 178 PPG output In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n p. 179 operation using the following procedure. <1> Disable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 0) <2> Disable the INTTM01n interrupt (TMMK01n = 1) <3> Rewrite CR01n <4> Wait for 1 cycle of the TM0n count clock <5> Enable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 1) <6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0) <7> Enable the INTTM01n interrupt (TMMK01n = 0) Pulse width measurement To use two capture registers, set the TI00n and TI01n pins. p. 180 External event counter When reading the external event counter count value, TM0n should be read. p. 190 Hard Chapter 7 Chapter (6/23) Function The pulse generated through PPG output has a cycle of [CR00n setting value + 1], p. 178 and has a duty of [(CR01n setting value + 1)/(CR00n setting value + 1)]. Hard Do not set the CR00n and CR01n registers to 0000H. p. 194 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits. p. 195 One-shot pulse Do not input the external trigger again while the one-shot pulse is being output. output: External To output the one-shot pulse again, wait until the current one-shot pulse output is trigger completed. Hard Soft Hard p. 193 When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI00n pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Soft One-shot pulse Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To p. 193 output: output the one-shot pulse again, wait until the current one-shot pulse output is Software trigger completed. 644 Timer start errors p. 195 Do not set the CR00n and CR01n registers to 0000H. p. 196 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits. p. 197 An error of up to one clock may occur in the time required for a match signal to be p. 198 generated after timer start. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count clock. User's Manual U15947EJ3V1UD APPENDIX D LIST OF CAUTIONS Soft Classification 16-bit timer/ event counters 00, 01 (TM00, TM01) Details of Function Cautions Page In the mode in which clear & start occurs on a match between TM0n and CR00n, set 16-bit timer capture/compare register 00n (CR00n) to other than 0000H. This means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 0n is used as an external event counter. p. 198 Capture register The values of 16-bit timer capture/compare registers 00n and 01n (CR00n and data retention CR01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped. timing p. 198 Valid edge setting p. 198 16-bit timer capture/ compare register 00n setting Set the valid edge of the TI00n pin after clearing bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control register 0n (TMC0n) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). One-shot pulse Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To p. 198 output: output the one-shot pulse again, wait until the current one-shot pulse output is Software trigger completed. Hard p. 198 One-shot pulse output function p. 198 When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI00n pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Soft One-shot pulse Do not input the external trigger again while the one-shot pulse is being output. output: External To output the one-shot pulse again, wait until the current one-shot pulse output is trigger completed. Operation of OVF0n flag The OVF0n flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM0n and CR00n, the mode in which clear & start occurs at the TI00n valid edge, or the free-running mode CR00n is set to FFFFH TM0n is counted up from FFFFH to 0000H. p. 199 Even if the OVF0n flag is cleared before the next count clock is counted (before TM0n becomes 0001H) after the occurrence of TM0n overflow, the OVF0n flag is re-set newly so this clear is invalid. p. 199 Conflicting operations p. 199 If a conflict occurs between the read period of the 16-bit timer capture/compare register (CR00n/CR01n) and capture trigger input (CR00n/CR01n used as capture register), the priority is given to the capture trigger input. The data read from CR00n/CR01n is undefined. Timer operation Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (CR01n). p. 200 Regardless of the CPU's operation mode, when the timer stops, the input signals to the TI00n/TI01n pins are not acknowledged. p. 200 Hard Chapter 7 Chapter (7/23) Function The one-shot pulse output mode operates correctly only in the free-running mode p. 200 and the mode in which clear & start occurs at the TI00n valid edge. In the mode in which clear & start occurs on a match between the TM0n register and CR00n register, one-shot pulse output is not possible because an overflow does not occur. Capture operation Compare operation If TI00n valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for TI00n is not possible. p. 200 To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0n (PRM0n). p. 200 The capture operation is performed at the falling edge of the count clock. An interrupt request input (INTTM00n/INTTM01n), however, is generated at the rise of the next count clock. p. 200 A capture operation may not be performed for CR00n/CR01n set in compare mode even if a capture trigger has been input. p. 200 User's Manual U15947EJ3V1UD 645 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 7 Chapter (8/23) Function 16-bit timer/ event counters 00, 01 (TM00, TM01) Details of Function Edge detection Cautions If the TI00n or TI01n pin is high level immediately after system reset and the rising p. 200 edge or both the rising and falling edges are specified as the valid edge of the TI00n or TI01n pin to enable the 16-bit timer counter 0n (TM0n) operation, a rising edge is detected immediately after the operation is enabled. Be careful therefore when pulling up the TI00n or TI01n pin. However, if the TI00n pin or TI01n pin is high level when re-enabling operation after the operation has been stopped, the rising edge is not detected. Soft CR5n: 8-bit timer compare register 5n TCL50: Timer clock selection register 50 Soft Hard Chapter 8 The sampling clock used to eliminate noise differs when the TI00n valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is only performed when a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width. 8-bit timer/ event counters 50, 51 (TM50, TM51) TCL51: Timer clock selection register 51 In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock (clock selected by TCL5n) or more. p. 204 p. 205 When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer/event counter 50 is not guaranteed. When rewriting TCL50 to other data, stop the timer operation beforehand. p. 205 Be sure to clear bits 3 to 7 to 0. p. 205 p. 206 When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer/event counter 51 is not guaranteed. p. 206 Be sure to clear bits 3 to 7 to 0. p. 206 The settings of LVS5n and LVR5n are valid in other than PWM mode. p. 208 Perform <1> to <4> below in the following order, not at the same time. <1> Set TMC5n1, TMC5n6: Operation mode setting <2> Set TOE5n to enable output: Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting <4> Set TCE5n p. 208 Stop operation before rewriting TMC5n6. p. 208 Interval timer/squarewave output Do not write other values to CR5n during operation. pp. 210, 213 PWM output In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock (clock selected by TCL5n) or more. p. 214 When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). p. 217 Timer start error An error of up to one clock may occur in the time required for a match signal to be p. 218 generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Hard Soft Chapter 9 646 p. 200 In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 p. 204 = 0), do not write other values to CR5n during operation. When rewriting TCL51 to other data, stop the timer operation beforehand. TMC5n: 8-bit timer mode control register 5n Page 8-bit timers H0, H1 (TMH0, TMH1) CMP0n: 8-bit timer H compare register 0n CMP0n cannot be rewritten during timer count operation. CMP1n: 8-bit timer H compare register 1n In the PWM output mode and carrier generator mode, be sure to set CMP1n when p. 222 starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). User's Manual U15947EJ3V1UD p. 222 APPENDIX D LIST OF CAUTIONS Hard Classification Details of Function 8-bit TMHMD0: 8-bit timers H0, timer H mode H1 register 0 (TMH0, TMH1) Cautions Page p. 225 When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer H0 is not guaranteed. When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited. p. 225 p. 225 In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). TMHMD1: 8-bit timer H mode register 1 Soft Hard Soft Chapter 9 Chapter (9/23) Function p. 227 When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the count clock is the internal oscillation clock, the operation of 8-bit timer H1 is 7 not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (fR/2 )). When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. p. 227 In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). p. 227 When the carrier generator mode is used, set so that the count clock frequency of p. 227 TMH1 becomes more than 6 times the count clock frequency of TM51. Hard PWM output In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register value after rewriting the register. p. 233 Soft Be sure to set the CMP1n register when starting the timer count operation p. 233 (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH p. 234 Carrier Do not rewrite the NRZB1 bit again until at least the second clock after it has been p. 239 generator mode rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not (TMH1 only) guaranteed. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. p. 239 Be sure to set the CMP11 register when starting the timer count operation p. 241 (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. p. 241 Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. p. 241 Soft Hard Chapter 10 In the carrier generator mode, three operating clocks (signal selected by CKS12 to p. 241 CKS10 bits of TMHMD1 register) or more are required from when the CMP11 register value is changed to when the value is transferred to the register. Watch timer Be sure to set the RMC1 bit before the count operation is started. p. 241 WTM: Watch timer operation mode register Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. p. 248 Interrupt request When operation of the watch timer and 5-bit counter is enabled by the watch timer p. 251 mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM. This is because there is a delay up to one 11-bit prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT signal is generated at the specified intervals. User's Manual U15947EJ3V1UD 647 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 11 Chapter (10/23) Function Details of Function Cautions Watchdog WDTM: If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM timer Watchdog timer when the CPU is operating on the subsystem clock and the X1 input clock is mode register stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. Page p. 256 Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Internal oscillator cannot be p. 256 stopped" is selected by a mask option, other values are ignored). After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. p. 256 WDTM cannot be set by a 1-bit memory manipulation instruction. p. 256 If "Internal oscillator can be stopped by software" is selected by the mask option and the watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not resume operation even if WDCS4 is cleared to 0. In addition, the internal reset signal is not generated. p. 256 WDTE: If a value other than ACH is written to WDTE, an internal reset signal is Watchdog timer generated. If the source clock to the watchdog timer is stopped, however, an enable register internal reset signal is generated when the source clock to the watchdog timer resumes operation. p. 257 If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset p. 257 signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. Soft Soft Hard Chapter 13 Hard The value read from WDTE is 9AH (this differs from the written value (ACH)). A/D converter In this mode, operation of the watchdog timer absolutely cannot be stopped even p. 258 during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. When "Internal oscillator can be stopped by software" is selected by mask option In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. p. 259 ADM: A/D A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other converter mode than the identical data. register For the sampling time of the A/D converter and the A/D conversion start delay time, see (11) in 13.6 Cautions for A/D Converter. p. 273 If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. ADS: Analog input channel specification register ADCR: A/D conversion result register p. 273 p. 273 Be sure to clear bits 3 to 7 of ADS to 0. p. 274 If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 274 When writing to the A/D converter mode register (ADM) and analog input channel p. 275 specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. 648 p. 257 When "Internal oscillator cannot be stopped" is selected by mask option User's Manual U15947EJ3V1UD p. 275 APPENDIX D LIST OF CAUTIONS Soft Classification Details of Function A/D converter PFM: Power-fail comparison mode register If data is written to PFM, a wait cycle is generated. Do not write data to PFM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 276 PFT: Power-fail comparison threshold register If data is written to PFT, a wait cycle is generated. Do not write data to PFT when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 276 A/D conversion operation Make sure the period of <1> to <3> is 14 s or more. p. 282 Power-fail detection function Cautions Page It is no problem if the order of <1> and <2> is reversed. p. 282 <1> can be omitted. However, do not use the first conversion result after <3> in this case. p. 282 The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0. p. 282 Make sure the period of <3> to <6> is 14 s or more. p. 282 It is no problem if order of <3>, <4>, and <5> is changed. p. 282 <3> must not be omitted if the power-fail function is used. p. 282 Soft Hard The period from <7> to <11> differs from the conversion time set using bits 5 to 3 p. 282 (FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0. Hard Chapter 13 Chapter (11/23) Function Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 (see Figure 13-2). p. 285 Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. p. 285 Conflicting operations ADCR read has priority. After the read operation, the new conversion result is written to ADCR. p. 285 ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal (INTAD) generated. p. 285 Noise To maintain the 10-bit resolution, attention must be paid to noise input to the countermeasures AVREF pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 13-19, to reduce noise. ANI0/P20 to ANI7/P27 p. 285 p. 286 The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. If a digital pulse is applied to the pins adjacent to the pins currently used for A/D p. 286 conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. Input impedance In this A/D converter, the internal sampling capacitor is charged and sampling is of ANI0 to ANI7 performed for approx. one sixth of the conversion time. pins Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 13-19). User's Manual U15947EJ3V1UD p. 286 649 APPENDIX D LIST OF CAUTIONS AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and p. 286 AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. Interrupt request flag (ADIF) p. 287 The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Conversion results just after A/D conversion start The A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 14 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. A/D conversion result register (ADCR) read operation p. 287 When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. Hard Hard Classification A/D converter A/D converter sampling time and A/D conversion start delay time p. 288 The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-21 and Table 13-3. Register generating wait cycle Do not read data from the ADCR register and do not write data to the ADM, ADS, PFM, and PFT registers while the CPU is operating on the subsystem clock and while oscillation of the clock input to X1 is stopped. UART mode If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), p. 290 normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TxD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. Soft Chapter 14 Soft Details of Function Soft Chapter 13 Chapter (12/23) Function Serial interface UART0 Cautions Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. Page p. 287 p. 288 p. 290 p. 290 TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. TXS0: Transmit Do not write the next transmit data to TXS0 before the transmission completion shift register 0 interrupt signal (INTST0) is generated. ASIM0: Asynchronous serial interface operation mode register 0 650 p. 293 At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear p. 295 TXE0 to 0, and then clear POWER0 to 0. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear p. 295 RXE0 to 0, and then clear POWER0 to 0. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. User's Manual U15947EJ3V1UD p. 295 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 14 Chapter (13/23) Function Serial interface UART0 Details of Function ASIM0: Asynchronous serial interface operation mode register 0 Cautions Page p. 295 TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. p. 295 Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. ASIS0: Asynchronous serial interface reception error status register 0 Be sure to set bit 0 to 1. p. 295 The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). p. 296 Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. p. 296 If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. p. 296 If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 296 Soft p. 298 Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. p. 298 Soft Hard Hard BRGC0: Baud When the internal oscillation clock is selected as the clock to be supplied to the rate generator CPU, the clock of the internal oscillator is divided and supplied as the count clock. control register 0 If the base clock is the internal oscillation clock, the operation of serial interface UART0 is not guaranteed. The baud rate value is the output clock of the 5-bit counter divided by 2. p. 298 POWER0, TXE0, RXE0: Bits 7, 6, and 5 of ASIM0 Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1. p. 299 UART mode Take relationship with the other party of communication when setting the port mode register and port register. p. 300 UART transmission After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. p. 303 UART reception Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. Error of baud rate Hard Serial interface UART6 UART mode p. 304 Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. p. 304 Be sure to read asynchronous serial interface reception error status register 0 (ASIS0) before reading RXB0. p. 304 Keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 307 Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. p. 307 Make sure that the baud rate error during reception is within the permissible error Permissible baud rate range range, by using the calculation expression shown below. during reception Chapter 15 p. 295 p. 309 The TXD6 output inversion function inverts only the transmission side and not the p. 311 reception side. To use this function, the reception side must be ready for reception of inverted data. User's Manual U15947EJ3V1UD 651 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 15 Chapter (14/23) Function Serial interface UART6 Details of Function UART mode Cautions If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), p. 311 normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if UART6 is used in the LIN communication operation. p. 317 Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). p. 317 ASIS6: Asynchronous serial interface reception error status register 6 Hard ASIF6: Asynchronous serial interface transmission status register 6 Soft p. 311 TXB6: Transmit Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface buffer register 6 transmission status register 6 (ASIF6) is 1. ASIM6: Asynchronous serial interface operation mode register 6 652 Page CKSR6: Clock selection register 6 At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear p. 319 TXE6 to 0, and then clear POWER6 to 0. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0, and then clear POWER6 to 0. p. 319 Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. p. 319 Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. p. 319 Fix the PS61 and PS60 bits to 0 when UART6 is used in the LIN communication operation. p. 319 Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. p. 319 Make sure that RXE6 = 0 when rewriting the ISRM6 bit. p. 319 The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). p. 320 The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. p. 320 If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. p. 320 If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 320 To transmit data continuously, write the first transmit data (first byte) to the TXB6 p. 321 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. To initialize the transmission unit upon completion of continuous transmission, be p. 321 sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. p. 323 When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. If the base clock is the internal oscillation clock, the operation of serial interface UART6 is not guaranteed. Make sure POWER6 = 0 when rewriting TPS63 to TPS60. User's Manual U15947EJ3V1UD p. 323 APPENDIX D LIST OF CAUTIONS Soft Classification Soft Hard Chapter 15 Chapter (15/23) Function Serial interface UART6 Details of Function Cautions BRGC6: Baud Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rate generator rewriting the MDL67 to MDL60 bits. control register 6 The baud rate is the output clock of the 8-bit counter divided by 2. ASICL6: Asynchronous serial interface control register 6 Page p. 323 p. 323 ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an interrupt signal is generated). p. 324 In the case of an SBF reception error, return the mode to the SBF reception mode. The status of the SBRF6 flag is held (1). p. 324 Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of p. 324 ASIM6 = 1. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 p. 324 after SBF reception has been correctly completed. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. p. 324 POWER6, TXE6, RXE6: Bits 7, 6, and 5 of ASIM6 Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode. To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. p. 326 UART mode Take relationship with the other party of communication when setting the port mode register and port register. p. 327 Parity types and Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. operation Continuous transmission p. 331 The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and p. 333 to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. p. 333 When the device is incorporated in a LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 during continuous transmission: Bit 1 of ASIF6 To transmit data continuously, write the first transmit data (first byte) to the TXB6 p. 333 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. TXSF6 during continuous transmission: Bit 1 of ASIF6 To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. p. 333 During continuous transmission, an overrun error may occur, which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame. An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. p. 333 Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p. 337 Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. p. 337 Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. p. 337 Normal reception User's Manual U15947EJ3V1UD 653 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 15 Chapter (16/23) Function Serial interface UART6 Details of Function Generation of serial clock Cautions Page Keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 344 Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. p. 344 Soft Serial SOTB1n: interfaces Transmit buffer CSI10, register 1n CSI11 SIO1n: Serial I/O shift register 1n p. 351 The SSI11 pin can be used in the slave mode. For details of the transmission/reception operation, see 16.4.2 (2) Communication operation. p. 351 p. 351 The SSI11 pin can be used in the slave mode. For details of the reception operation, see 16.4.2 (2) Communication operation. p. 351 CSIM10: Serial operation mode register 10 Be sure to clear bit 5 to 0. p. 352 CSIC10: Serial clock selection register 10 When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of the internal oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed. p. 355 Do not write to CSIC10 while CSIE10 = 1 (operation enabled). p. 355 Clear CKP10 to 0 to use P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 as general-purpose port pins. p. 355 CSIC11: Serial clock selection register 11 Soft Hard Do not access SOTB1n when CSOT1n = 1 (during serial communication). Do not access SIO1n when CSOT1n = 1 (during serial communication). Soft Hard Chapter 16 Permissible Make sure that the baud rate error during reception is within the permissible error p. 346 baud rate range range, by using the calculation expression shown below. during reception The phase type of the data clock is type 1 after reset. p. 355 When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of the internal oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI11 is not guaranteed. p. 356 Do not write to CSIC11 while CSIE11 = 1 (operation enabled). p. 356 Clear CKP11 to 0 to use P02/SO11, P03/SI11, and P04/SCK11 as generalpurpose port pins. p. 356 The phase type of the data clock is type 1 after reset. p. 359 Communication operation Do not access the control register and data register when CSOT1n = 1 (during serial communication). p. 362 When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. p. 362 If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. p. 368 Soft Chapter 17 SO1n output Serial interface CSIA0 SIOA0: Serial A communication operation is started by writing to SIOA0. Consequently, when p. 372 I/O shift register transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the 0 SIOA0 register to start the communication operation, and then perform a receive operation. CSIMA0: Serial operation mode specification register 0 Do not write data to SIOA0 while the automatic transmit/receive function is operating. p. 372 When CSIAE0 = 0, the buffer RAM cannot be accessed. p. 373 When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note p. 373 above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized registers. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. 654 p. 356 3-wire serial I/O Take relationship with the other party of communication when setting the port mode mode register and port register. User's Manual U15947EJ3V1UD p. 373 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 17 Chapter (17/23) Function Serial interface CSIA0 Details of Function Cautions Page CSIS0: Serial status register 0 Be sure to clear bit 7 to 0. CSIT0: Serial trigger register 0 Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1-byte transfer is complete. p. 376 ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is generated. p. 376 After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by ATSTA0 after re-setting the registers. p. 376 ADTP0: Automatic data transfer address point specification register 0 Be sure to clear bits 7 to 5 to 0. p. 377 ADTI0: Automatic data transfer interval specification register 0 Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register p. 379 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. 3-wire serial I/O mode Take relationship with the other party of communication when setting the port mode register and port register. pp. 382, 389 1-byte transmission/ reception The SOA0 pin becomes low level by an SIOA0 write. p. 384 Communication start If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. p. 386 Automatic transmission/ reception mode Because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). p. 390 If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. pp. 390, 394, 398 Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). p. 394 Automatic transmission mode p. 374 p. 375 When TSF0 is 1, rewriting serial operation mode specification register 0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer. User's Manual U15947EJ3V1UD 655 APPENDIX D LIST OF CAUTIONS Soft Classification Soft Chapter 18 Chapter 17 Chapter (18/23) Function Serial interface CSIA0 Details of Function Cautions Page Repeat transmission mode p. 398 Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). Automatic transmission/ reception suspension and restart If the HALT instruction is executed during automatic transmission/reception, communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. Busy control Busy control cannot be used simultaneously with the interval time control function p. 404 of automatic data transfer interval specification register 0 (ADTI0). Busy & strobe control When TSF0 is cleared, the SOA0 pin goes low. p. 406 The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. p. 411 Multiplier/ SDR0: divider Remainder data register 0 MDA0H, MDA0L: Multiplication/ division data register A0 p. 403 When suspending automatic transmission/reception, do not change the operating p. 403 mode to 3-wire serial I/O mode while TSF0 = 1. SDR0 is reset when the operation is started (when DMUE is set to 1). p. 411 MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). p. 412 Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. p. 412 The value read from MDA0 during operation processing (while DMUE is 1) is not p. 412 guaranteed. MDB0: Multiplication/ division data register B0 Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. p. 413 Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. p. 413 DMUC0: If DMUE is cleared to 0 during operation processing (when DMUE is 1), the Multiplier/divider operation result is not guaranteed. If the operation is completed while the control register 0 clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. p. 414 656 Soft Chapter 19 Do not change the value of DMUSEL0 during operation processing (while DMUE p. 414 is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). Interrupt IF1H: Interrupt request flag register If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). p. 414 Be sure to clear bits 5 to 7 of IF1H to 0. p. 425 IF0L, IF0H, IF1L, When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag IF1H: Interrupt may be set by noise. request flag registers User's Manual U15947EJ3V1UD p. 425 APPENDIX D LIST OF CAUTIONS Soft Classification Soft Cautions Page IF0L, IF0H, IF1L, IF1H: Interrupt request flag registers Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of p. 426 the interrupt request flag register. A 1-bit manipulation instruction such as "IF0L.0 = 0;" and "_asm("clr1 IF0L, 0");" should be used when describing in C language, because assembly instructions after compilation must be 1-bit memory manipulation instructions (CLR1). If an 8-bit memory manipulation instruction "IF0L & = 0xfe;" is described in C language, for example, it is converted to the following three assembly instructions after compilation: mov a, IF0L and a, #0FEH mov IF0L, a In this case, at the timing between "mov a, IF0L" and "mov IF0L, a", if the request flag of another bit of the identical interrupt request flag register (IF0L) is set to 1, it is cleared to 0 by "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. MK1H: Interrupt mask flag register Be sure to set bits 6 and 7 of MK1H to 1 and clear bit 5 to 0. p. 426 PR1H: Priority specification flag register Be sure to set bits 5 to 7 of PR1H to 1. p. 427 Select the port mode after clearing EGPn and EGNn to 0 because an edge may EGP, EGN: External interrupt be detected when the external interrupt function is switched to the port function. rising/falling edge enable registers p. 428 Software interrupt request acknowledgment Do not use the RETI instruction for restoring from the software interrupt. p. 432 Interrupt request hold The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. p. 436 Key interrupt function KRM: Key return mode register If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the corresponding pull-up resistor register 7 (PU7) to 1. p. 438 If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. After that, clear the interrupt request flag and then enable interrupts. p. 438 Standby function - The bits not used in the key interrupt mode can be used as normal ports. p. 438 The RSTOP setting is valid only when "Can be stopped by software" is set for internal oscillator by a mask option. p. 439 p. 440 STOP mode can be used only when CPU is operating on the X1 input clock or internal oscillation clock. HALT mode can be used when CPU is operating on the X1 input clock, internal oscillation clock, or subsystem clock. However, when the STOP instruction is executed during internal oscillation clock operation, the X1 oscillator stops, but internal oscillator does not stop. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction. p. 440 Soft Hard Soft Interrupt Details of Function STOP mode, HALT mode The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. p. 440 Hard Chapter 21 Chapter 20 Chapter 19 Chapter (19/23) Function STOP mode p. 440 If the internal oscillator is operating before the STOP mode is set, oscillation of the internal oscillation clock cannot be stopped in the STOP mode. However, when the internal oscillation clock is used as the CPU clock, the CPU operation is stopped for 17/fR (s) after STOP mode is released. User's Manual U15947EJ3V1UD 657 APPENDIX D LIST OF CAUTIONS Soft Classification Standby function Details of Function OSTC: Oscillation stabilization time counter status register Soft OSTS: Oscillation stabilization time select register Hard STOP mode setting and operating statuses Soft Hard Soft Page After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 441 If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. p. 441 To set the STOP mode while the X1 input clock is used as the CPU clock, set OSTS before executing the STOP instruction. p. 442 Before setting OSTS, confirm with OSTC that the desired oscillation stabilization time has elapsed. p. 442 If the STOP mode is entered and then released while the internal oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. p. 442 The wait time when STOP mode is released does not include the time after STOP p. 442 mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. Reset function Soft Chapter 22 Chapter 23 658 Cautions The wait time when STOP mode is released does not include the time after STOP p. 441 mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. Hard Chapter 21 Chapter (20/23) Function Clock monitor - Because the interrupt request signal is used to release the standby mode, if there p. 448 is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. For an external reset, input a low level for 10 s or more to the RESET pin. p. 452 During reset input, the X1 input clock and internal oscillation clock stop oscillating. p. 452 When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to low-level output. p. 452 An LVI circuit internal reset does not reset the LVI circuit. p. 453 Timing of reset due to watchdog timer overflow A watchdog timer internal reset resets the watchdog timer. p. 454 RESF: Reset control flag register Do not read data by a 1-bit memory manipulation instruction. p. 459 CLM: Clock monitor mode register Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal reset signal. p. 461 If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 p. 461 (CLMRF) of the reset control flag register (RESF) is set to 1. User's Manual U15947EJ3V1UD APPENDIX D LIST OF CAUTIONS Soft Classification Soft Chapter 25 Chapter 24 Chapter (21/23) Function Power-onclear circuit (POC) Details of Function Cautions Power-onclear circuit functions If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. p. 467 Cautions for power-onclear circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. p. 469 To stop LVI, follow either of the procedures below. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then clear LVIE to 0. p. 473 Low-voltage LVIM: Lowdetector voltage (LVI) detection register Be sure to clear bits 3 to 7 to 0. LVIS: Lowvoltage detection level selection register p. 474 When used as <1> must always be executed. When LVIMK = 0, an interrupt may occur reset immediately after the processing in <5>. p. 475 If "POC used" is selected by a mask option, procedures <3> and <4> are not required. p. 475 If supply voltage (VDD) > detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. p. 475 When used as If "POC used" is selected by a mask option, procedures <3> and <4> are not interrupt required. Hard - Hard PD78F0148 - p. 477 p. 479 In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (a) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take action (b) below. Directly connect the REGC pin of standard products and (A) grade products to VDD p. 483 when the regulator is not used. The regulator cannot be used with (A1) and (A2) grade products. Be sure to connect the REGC pin of these products directly to VDD. Soft Chapter 28 Chapter 26 Cautions for low-voltage detector Regulator Page p. 483 p. 486 There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. IMS: Internal memory size switching register The initial value of IMS is CFH. Be sure to set the value of the relevant mask ROM version at initialization. IXS: Internal expansion RAM size switching register The initial value of IXS is 0CH. Be sure to set the value of the relevant mask ROM version at initialization. p. 487 When using a mask ROM version, be sure to set the value indicated in Table 28-2 p. 487 to IMS. p. 488 When using a mask ROM version, be sure to set the value indicated in Table 28-3 p. 488 to IXS. User's Manual U15947EJ3V1UD 659 APPENDIX D LIST OF CAUTIONS Hard Classification Hard Chapters 30, 31, 32, 33 Soft Chapter 28 Chapter (22/23) Function Details of Function PD78F0148 REGC pin UART0, UART6 Electrical Absolute specifications maximum ratings X1 oscillator Subsystem clock oscillator 660 Cautions Page Be sure to connect the REGC pin in either of the following ways. * To GND via a 1 F capacitor * Directly to VDD pp. 489, 490 When connecting the REGC pin to GND via a 1 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the board to supply a clock. pp. 489, 490 When UART0 or UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the VPP pulse has been received. p. 505 Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. pp. 521, 546, 570, 571, 591, 592 When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. pp. 522, 547, 572, 593 Since the CPU is started by the internal oscillation clock after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time counter status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. pp. 522, 547, 572, 593 When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. pp. 523, 548, 573, 594 The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. pp. 523, 548, 573, 594 User's Manual U15947EJ3V1UD APPENDIX D LIST OF CAUTIONS Hard Classification Chapters 30, 31 Chapter (23/23) Function Electrical specifications (standard products, (A) grade products) Details of Function Recommended oscillator constants (X1 oscillation) Cautions For the resonator selection of the PD780143(A), 780144(A), 780146(A), 780148(A), and 78F0148(A) and oscillator constants, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. pp. 524, 549 The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. pp. 524, 525, 549, 550 AC TCY can only be used at 0.238 s (MIN). characteristics pp. 532, 557 pp. 533, 558 Be sure to connect the REGC pin of (A1) grade products directly to VDD. p. 570 The external bus interface function cannot be used with (A1) grade products. p. 570 Be sure to connect the REGC pin of (A2) grade products directly to VDD. p. 591 The external bus interface function cannot be used with (A2) grade products. p. 591 - Electrical specifications ((A2) grade products) - Recommended soldering conditions - Do not use different soldering methods together (except for partial heating). pp. 609, 610, 611 Wait - When the CPU is operating on the subsystem clock and the X1 input clock is stopped (MCC = 1), do not access the registers listed above using an access method in which a wait request is issued. p. 613 Hard Hard Electrical specifications ((A1) grade products) Hard TCY can only be used at 0.4 s (MIN). Soft Chapter 36 Chapter 35 Chapter 33 Chapter 32 Page User's Manual U15947EJ3V1UD 661 APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition (1/2) Page Description U15947EJ2V0UD00 U15947EJ3V0UD00 Throughout Addition of description on expanded-specification products of standard products and (A) grade products p. 7 Addition of Differences Between 78K0/KF1 and 78K0/KF1+ to INTRODUCTION p. 18 Addition of 1.1 Expanded-Specification Products and Conventional Products (Standard Products, (A) Grade Products Only) p. 26 Modification of 1.6 Kx1 Series Lineup p. 47 Modification of connection of RESET pin and XT1 pin when unused in Table 2-2 Pin I/O Circuit Types p. 133 Modification of Note 3 and addition of Note 5 to Figure 6-2 Format of Processor Clock Control Register (PCC) p. 134 Addition of minimum instruction execution time of X1 input clock at 12 MHz operation and addition of Notes 2 and 3 to Table 6-2 Relationship Between CPU Clock and Minimum Instruction Execution Time p. 137 Addition of oscillation stabilization time status when fXP = 12 MHz to Figure 6-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) p. 138 Addition of oscillation stabilization time when fXP = 12 MHz and addition of Cautions 1 and 2 to Figure 6-7 Format of Oscillation Stabilization Time Select Register (OSTS) p. 142 Modification of connection of XT1 pin when unused and addition of Note to 6.4.3 When subsystem clock is not used p. 150 Addition of Note and modification of Table 6-5 Maximum Time Required to Switch Between Internal Oscillation Clock and X1 Input Clock p. 151 p. 164 Addition of Caution 2 and modification of Table 6-6 Maximum Time Required for CPU Clock Switchover Addition of description on using capture register to Interrupt request generation column in Figure 7-6 Format of 16-Bit Timer Mode Control Register 00 (TMC00) p. 165 Addition of description on using capture register to Interrupt request generation column in Figure 7-7 Format of 16-Bit Timer Mode Control Register 01 (TMC01) p. 168 Addition of Caution 7 to Figure 7-10 Format of 16-Bit Timer Output Control Register 00 (TOC00) p. 169 Addition of Caution 7 to Figure 7-11 Format of 16-Bit Timer Output Control Register 01 (TOC01) p. 170 Addition of Note 1 to Figure 7-12 Format of Prescaler Mode Register 00 (PRM00) p. 172 Addition of Note 1 to Figure 7-13 Format of Prescaler Mode Register 01 (PRM01) p. 195 Modification of TMC0n set value in Figure 7-37 Timing of One-Shot Pulse Output Operation with Software Trigger p. 205 Addition of Note to Figure 8-5 Format of Timer Clock Selection Register 50 (TCL50) p. 206 Addition of Note to Figure 8-6 Format of Timer Clock Selection Register 51 (TCL51) p. 208 Modification of Caution 2 in Figure 8-7 Format of 8-Bit Timer Mode Control Register 50 (TMC50) and Figure 8-8 Format of 8-Bit Timer Mode Control Register 51 (TMC51) p. 224 Addition of Note 1 and modification of Note 2 in Figure 9-5 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) p. 226 Addition of Note to Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1) p. 256 Modification of Caution 3 and addition of Caution 5 to Figure 11-2 Format of Watchdog Timer Mode Register (WDTM) p. 257 662 Modification of Cautions 1 and 2 in Figure 11-3 Format of Watchdog Timer Enable Register (WDTE) User's Manual U15947EJ3V1UD APPENDIX E REVISION HISTORY (2/2) Page p. 257 Description Addition of Table 11-4 Relationship Between Watchdog Timer Operation and Internal Reset Signal Generated by Watchdog Timer p. 297 Addition of Note 1 and modification of Note 2 in Figure 14-4 Format of Baud Rate Generator Control Register 0 (BRGC0) p. 322 Addition of Note 1 and modification of Note 2 in Figure 15-8 Format of Clock Selection Register 6 (CKSR6) p. 354 Addition of Note to Figure 16-5 Format of Serial Clock Selection Register 10 (CSIC10) p. 356 Addition of Note to Figure 16-6 Format of Serial Clock Selection Register 11 (CSIC11) p. 374 Addition of CKS00 to Figure 17-4 Format of Serial Status Register 0 (CSIS0) p. 426 Modification of Caution 3 in Figure 19-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) p. 441 Addition of oscillation stabilization time status when fXP = 12 MHz to Figure 21-1 Format of Oscillation Stabilization Time Counter Status Register (OSTC) p. 442 Addition of oscillation stabilization time when fXP = 12 MHz and addition of Cautions 1 and 2 to Figure 21-2 Format of Oscillation Stabilization Time Select Register (OSTS) p. 453 Modification of Figure 22-1 Block Diagram of Reset Function p. 454 Modification of Figure 22-2 Timing of Reset by RESET Input p. 454 Modification of Figure 22-3 Timing of Reset Due to Watchdog Timer Overflow p. 455 Modification of Figure 22-4 Timing of Reset in STOP Mode by RESET Input p. 471 Modification of Note in 25.1 Functions of Low-Voltage Detector p. 474 Addition of Notes 3 and 4 to Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) p. 505 Modification of Table 28-7 Communication Modes p. 520 Addition of CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (EXPANDED-SPECIFICATION PRODUCTS) p. 545 Modification of description of target products in CHAPTER 31 ELECTRICAL SPECIFICATIONS p. 575 DC Characteristics in CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) * Addition of condition 4.0 V VDD 5.5 V for low-level output voltage (VOL2) pp. 576, 579 * Addition of value of supply current (IDD4) in internal oscillation, HALT mode p. 596 DC Characteristics in CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) * Addition of condition 4.0 V VDD 5.5 V for low-level output voltage (VOL2) p. 597 * Addition of value of supply current (IDD4) in internal oscillation, HALT mode (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (CONVENTIONAL PRODUCTS) p. 618 Addition of (3) When using the in-circuit emulator QB-78K0KX1H to Figure A-1 Development Tool Configuration p. 623 Addition of A.5.3 When using in-circuit emulator QB-78K0KX1H p. 630 Addition of B.2 When Using QB-78K0KX1H p. 639 Addition of APPENDIX D LIST OF CAUTIONS p. 664 Addition of E.2 Revision History up to Previous Edition U15947EJ3V0UD00 U15947EJ3V1UD00 p.21 Addition of lead-free products to 1.4 Ordering Information p.611 Addition of lead-free products to CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS User's Manual U15947EJ3V1UD 663 APPENDIX E REVISION HISTORY E.2 Revision History up to Previous Edition The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/5) Edition Description Applied to: 1st edition Modification of reset value of the following registers in Table 3-5 Special Function CHAPTER 3 CPU (Modified Register List ARCHITECTURE version) * Serial I/O shift register 10 (SIO10) * Serial I/O shift register 11 (SIO11) * Interrupt mask flag register 1H (MK1H) Modification of manipulatable bit unit of the following register in Table 3-5 Special Function Register List * Oscillation stabilization time counter status register (OSTC) Modification of manipulatable bit unit and clear condition in 6.3 (5) Oscillation CHAPTER 6 CLOCK stabilization time counter status register (OSTC) GENERATOR Modification of Figure 6-13 Status Transition Diagram Modification of Table 6-4 Oscillation Control Flags and Clock Oscillation Status Modification of reset value in 7.2 (2) 16-bit timer capture/compare register 00n CHAPTER 7 16-BIT (CR00n) and (3) 16-bit timer capture/compare register 01n (CR01n) TIMER/EVENT Modification of manipulatable bit unit in 7.3 (4) Prescaler mode register 0n (PRM0n) COUNTERS 00 AND 01 Addition of caution description in 13.6 (10) A/D conversion result register (ADCR) read CHAPTER 13 A/D operation CONVERTER Modification of reset value in 16.2 (2) Serial I/O shift register 1n (SIO1n) CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Modification of reset value in 19.3 (2) Interrupt mask flag register (MK1H) CHAPTER 19 INTERRUPT FUNCTIONS Modification of manipulatable bit unit and clear condition in 21.1.2 (1) Oscillation CHAPTER 21 stabilization time counter status register (OSTC) STANDBY FUNCTION Modification of A/D converter item in Table 21-2 Operating Statuses in HALT Mode Modification of stop condition of clock monitor in 23.1 Functions of Clock Monitor and CHAPTER 23 CLOCK 23.4 Operation of Clock Monitor MONITOR Addition of 24.4 Cautions for Power-on-Clear Circuit CHAPTER 24 POWERON-CLEAR CIRCUIT Modification of Figure 25-3 Format of Low-Voltage Detection Level Selection CHAPTER 25 LOW- Register (LVIS) VOLTAGE DETECTOR Addition of 25.5 Cautions for Low-Voltage Detector Modification of description in 26.1 Outline of Regulator CHAPTER 26 REGULATOR 664 User's Manual U15947EJ3V1UD APPENDIX E REVISION HISTORY (2/5) Edition Description Applied to: 1st edition Modification of the following contents in CHAPTER 30 ELECTRICAL SPECIFICATIONS CHAPTER 30 (Modified (TARGET VALUES) ELECTRICAL version) * Absolute Maximum Ratings SPECIFICATIONS * X1 Oscillator Characteristics (TARGET VALUES) * Subsystem Clock Oscillator Characteristics * DC Characteristics * A/D Converter Characteristics * POC Circuit Characteristics * LVI Circuit Characteristics * Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (deletion of data retention supply current) * Deletion of Internal Oscillator Characteristics * Flash Memory Programming Characteristics Modification from CHAPTER 32 RETRY to CHAPTER 32 CAUTIONS FOR WAIT CHAPTER 32 CAUTIONS FOR WAIT 2nd edition Addition of products PD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2) Throughout Under development Under mass production PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1) Modification of names of the following special function registers (SFRs) * Ports 0 to 7, and 12 to 14 Port registers 0 to 7, and 12 to 14 Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View) CHAPTER 1 OUTLINE Modification of 1.5 K1 Family Lineup Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions Addition of Table 2-1 Pin I/O Buffer Power Supplies CHAPTER 2 PIN Modification of descriptions in 2.2.12 AVREF, 2.2.15 REGC, and 2.2.20 VPP (flash FUNCTIONS memory versions only) Modification of the following contents in Table 2-2 Pin I/O Circuit Types * Modification of recommended connection when P60 to P63 are not used * Modification of I/O circuit type of P62 and P63 * Addition of Note to AVREF * Modification of recommended connection when VPP is not used Modification of Figure 3-1 Memory Map (PD780143) to Figure 3-5 Memory Map CHAPTER 3 CPU (PD78F0148) ARCHITECTURE Modification of Figure 3-14 Data to Be Saved to Stack Memory Modification of Figure 3-15 Data to Be Restored from Stack Memory Modification of [Description example] in 3.4.4 Short direct addressing Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack addressing Addition of Table 4-1 Pin I/O Buffer Power Supplies CHAPTER 4 PORT Modification of Table 4-3 Port Configuration FUNCTIONS Modification of Figure 4-11 Block Diagram of P20 to P27, Figure 4-14 Block Diagram of P40 to P47, Figure 4-15 Block Diagram of P50 to P57, Figure 4-17 Block Diagram of P64, P65, and P67, and Figure 4-18 Block Diagram of P66 Addition of Remark to Figure 4-21 Block Diagram of P130 User's Manual U15947EJ3V1UD 665 APPENDIX E REVISION HISTORY (3/5) Edition 2nd edition Description Applied to: Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, CHAPTER 4 PORT P12 to P14) to 4.3 Registers Controlling Port Function FUNCTIONS Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in and addition of Note 2 to Table 4-5 Settings of Port Mode Register and Output Latch When Using Alternate Function Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode Addition of Caution to 5.1 External Bus Interface CHAPTER 5 Addition of Note to Figure 5-2 Format of Memory Expansion Mode Register (MEM) EXTERNAL BUS Addition of Caution 2 to Figure 5-4 Format of Memory Expansion Wait Setting INTERFACE Register (MM) Addition of Remark to Figure 5-8 External Memory Read Modify Write Timing Modification of Figure 6-1 Block Diagram of Clock Generator CHAPTER 6 CLOCK Addition of Note to 6.3 (1) Processor clock control register (PCC) GENERATOR Addition of Cautions 2 and 3 to Figure 6-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Modification of Figure 6-8 Examples of External Circuit of X1 Oscillator, Figure 6-9 Examples of External Circuit of Subsystem Clock Oscillator, and Figure 6-10 Examples of Incorrect Resonator Connection Modification of Notes 4 and 5 in Figure 6-13 Status Transition Diagram (2) Modification of Note 4 and illustration in Figure 6-13 Status Transition Diagram (4) Modification of Table 6-3 Relationship Between Operation Clocks in Each Operation Status Modification of Note in Figure 6-14 Switching from Internal Oscillation Clock to X1 Input Clock (Flowchart) Addition of Note to Figure 6-16 Switching from X1 Input Clock to Subsystem Clock (Flowchart) Revision of CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Revision of CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Revision of CHAPTER 9 8-BIT TIMERS H0 AND H1 CHAPTER 9 8-BIT TIMERS H0 AND H1 Modification of Figure 10-1 Watch Timer Block Diagram CHAPTER 10 WATCH Addition of Figure 10-4 Example of Generation of Watch Timer Interrupt Request TIMER (INTWT) (When Interrupt Period = 0.5 s) Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer Output Controller CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Revision of CHAPTER 13 A/D CONVERTER CHAPTER 13 A/D CONVERTER Revision of CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 14 SERIAL INTERFACE UART0 666 User's Manual U15947EJ3V1UD APPENDIX E REVISION HISTORY (4/5) Edition 2nd edition Description Revision of CHAPTER 15 SERIAL INTERFACE UART6 Applied to: CHAPTER 15 SERIAL INTERFACE UART6 Revision of CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Revision of CHAPTER 17 SERIAL INTERFACE CSIA0 CHAPTER 17 SERIAL INTERFACE CSIA0 Revision of CHAPTER 18 MULTIPLIER/DIVIDER CHAPTER 18 MULTIPLIER/DIVIDER Addition of Note to INTVLI, POC, and LVI in Table 19-1 Interrupt Source List CHAPTER 19 Addition of Note 2 to Table 19-2 Flags Corresponding to Interrupt Request Sources INTERRUPT Addition of Caution 2 to Figure 19-2 Format of Interrupt Request Flag Registers FUNCTIONS (IF0L, IF0H, IF1L, IF1H) Addition of Caution to Table 19-3 Ports Corresponding to EGPn and EGNn Addition of software interrupt request item to Table 19-5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Modification of Figure 20-1 Block Diagram of Key Interrupt CHAPTER 20 KEY INTERRUPT FUNCTION Modification of Table 21-1 Relationship Between HALT Mode, STOP Mode, and CHAPTER 21 Clock in old edition to Table 21-1 Relationship Between Operation Clocks in Each STANDBY FUNCTION Operation Status Addition of Cautions 2 and 3 to Figure 21-1 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Modification of Table 21-2 Operating Statuses in HALT Mode Addition of (3) When subsystem clock is used as CPU clock to Figure 21-4 HALT Mode Release by RESET Input Modification of the following items in Table 21-4 Operating Statuses in STOP Mode * 8-bit timer H0 * Serial interfaces UART0 and UART6 Modification of Figure 22-1 Block Diagram of Reset Function to Figure 22-4 Timing CHAPTER 22 RESET of Reset in STOP Mode by RESET Input FUNCTION Modification of mask flag register 1H (MK1H) in Table 22-1 Hardware Statuses After Reset Acknowledgment Modification of Figure 23-1 Block Diagram of Clock Monitor CHAPTER 23 CLOCK Addition of normal operation mode to Table 23-2 Operation Status of Clock Monitor MONITOR (When CLME = 1) Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7) Clock monitor status after internal oscillation clock is stopped by software to Figure 23-3 Timing of Clock Monitor Addition of Note to description in 24.1 Functions of Power-on-Clear Circuit CHAPTER 24 POWER- Modification of Figure 24-1 Block Diagram of Power-on-Clear Circuit ON-CLEAR CIRCUIT Addition of Note to description in 25.1 Functions of Low-Voltage Detector CHAPTER 25 LOW- Modification of Figure 25-1 Block Diagram of Low-Voltage Detector VOLTAGE DETECTOR User's Manual U15947EJ3V1UD 667 APPENDIX E REVISION HISTORY (5/5) Edition 2nd edition Description Applied to: Modification of Note 5 in Figure 25-2 Format of Low-Voltage Detection Register CHAPTER 25 LOW- (LVIM) VOLTAGE DETECTOR Addition of Note 2 and Caution to Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Modification of Figure 25-4 Timing of Low-Voltage Detector Internal Reset Signal Generation and Figure 25-5 Timing of Low-Voltage Detector Interrupt Signal Generation Partial modification of description of (2) When used as interrupt under <Action> in 25.5 Cautions for Low-Voltage Detector Revision of CHAPTER 26 REGULATOR CHAPTER 26 REGULATOR Addition of Note to CHAPTER 27 MASK OPTIONS CHAPTER 27 MASK OPTIONS Revision of CHAPTER 28 PD78F0148 (no modification of 28.1 Internal Memory Size CHAPTER 28 Switching Register and 28.2 Internal Expansion RAM Size Switching Register) PD78F0148 Partial modification of operation of "RETI" in 29.2 Operation List CHAPTER 29 INSTRUCTION SET Revision of CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, CHAPTER 30 (A) GRADE PRODUCTS) ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Addition of CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Addition of CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Addition of CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Addition of A.3 Control Software APPENDIX A Addition of in-circuit emulator "IE-78K0K1-ET" to A.5 Debugging Tools (Hardware) DEVELOPMENT Modification of part number of RX78K0 in A.7 Embedded Software Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN TOOLS APPENDIX B NOTES ON TARGET SYSTEM DESIGN Addition of APPENDIX D REVISION HISTORY APPENDIX D REVISION HISTORY 668 User's Manual U15947EJ3V1UD