PIC32MX575F512H-80I/PT - Microchip Technology, Inc.

 2009-2013 Microchip Technology Inc. DS60001156H-page 1

PIC32MX5XX/6XX/7XX

Operating Conditions

• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz

Core: 80 MHz/105 DMIPS MIPS32® M4K®

• MIPS16e® mode for up to 40% smaller code size

• Code-efficient (C and Assembly) architecture

• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

Clock Management

• 0.9% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent W atchdog Timer

• Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep and Idle)

• Integrated Power-on Reset, Brown-out Reset

• 0.5 mA/MHz dynamic current (typical)

• 41 µA IPD current (typical)

Graphics Features

• External graphics interface with up to 34 Parallel Master

Port (PMP) pins:

- Interface to external graphics controller

- Capable of driving LCD directly with DMA and

internal or external memory

Analog Features

• ADC Module:

- 10-bit 1 Msps rate wit h one Sample and Hold (S&H)

- 16 analog inputs

- Can operate during Sleep mode

• Flexible and independent ADC trigger sources

•Comparators:

- Two dual-input Comparator modules

- Programmable references with 32 voltage points

Timers/Output Compare/Input Capture

• Five General Purpose Timers:

- Five 16-bit and up to two 32-bi t Timers/Counters

• Five Output Compare (OC) modules

• Five Input Capture (IC) modules

• Real-Time Clock and Calendar (RTCC) module

Communication Interfaces

• USB 2.0-compliant Full-S peed OTG controller

• 10/100 Mbps Ethernet MAC with MII and RMII interface

• CAN module:

- 2.0B Active with DeviceNet™ addressing support

• Six UART modules (20 Mbps):

- Supports LIN 1.2 protocols and IrDA® support

• Up to four 4-wire SPI modules (25 Mbps)

• Up to five I2C modules (up to 1 Mbaud) with SMBus

support

• Parallel Master Port (PMP)

Direct Memory Access (DMA)

• Up to eight channels of hardware DMA with automatic

data size detection

• 32-bit Programmable Cyclic Redundancy Check (CRC)

• Six additional channels dedicated to USB, Ethernet and

CAN modules

Input/Output

• 15 mA or 10 mA source/sink for standard VOH/VOL and

up to 22 mA for non-standard VOH1

• 5V-tolerant pins

• Selectable open drain and pull-ups

• External interrupts

Qualification and Class B Support

• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

•4-wire MIPS

® Enhanced JTAG interface

• Unlimited program and six complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

Packages

Type QFN TQFP TFBGA VTLA

Pin Count 64 64 100 100 121 124

I/O Pins (up to) 51 51 83 83 83 83

Contact/Lead Pitch 0.50 0.50 0.40 0.50 0.80 0.50

Dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1 10x10x1.1 9x9x0.9

Note: All dimensions are in millimeters (mm) unless specified.

32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)

with Graphics Interface, USB, CAN, and Ethernet

PIC32MX5XX/6XX/7XX

DS60001156H-page 2  2009-2013 Microchip Technology Inc.

TABLE 1: PIC32 USB AND CAN – FEATURES

USB and CAN

Device

Pins

Program Memory (KB)

Data Memory (KB)

USB

CAN

Timers/Capture/Compare

DMA Channels

(Programmable/Dedicated)

UART(2,3)

SPI(3)

I2C™(3)

10-bit 1 Msps ADC (Channels)

Comparators

PMP/PSP

JTAG

Trace

Packages(4)

PIC32MX534F064H 64 64 + 12(1) 16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX564F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX564F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX575F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX575F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX534F064L 100 64 + 12(1) 16 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT,

PF,

PIC32MX564F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT,

PF,

PIC32MX564F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT,

PF,

PIC32MX575F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT,

PF,

PIC32MX575F512L 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT,

PF,

Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5)

Note 1: This device features 12 KB boot Flash memory.

2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more

information.

3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more

information.

4: Refer to Section33.0 “Packaging Information” for more information.

5: 100-pin devices in the VTLA package are available upon request. Please contact your local Microchip Sales Office for

details.

 2009-2013 Microchip Technology Inc. DS60001156H-page 3

PIC32MX5XX/6XX/7XX

TABLE 2: PIC32 USB AND ETHERNET – FEATURES

USB and Ethernet

Device

Pins

Program Memory (KB)

Data Memory (KB)

USB

Ethernet

Timers/Capture/Compare

DMA Channels

(Programmable/Dedicated)

UART(2,3)

SPI(3)

I2C™(3)

10-bit 1 Msps ADC (Channels)

Comparators

PMP/PSP

JTAG

Trace

Packages(4)

PIC32MX664F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX664F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX675F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX675F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX695F512H 64 512 + 12(1) 128 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,

PIC32MX664F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF ,

PIC32MX664F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF,

PIC32MX675F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF,

PIC32MX675F512L 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF,

BG, TL

PIC32MX695F512L 100 512 + 12(1) 128 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT , PF,

BG, TL

Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5)

Note 1: This device features 12 KB boot Flash memory.

2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more

information.

3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more

information.

4: Refer to Section33.0 “Packaging Information” for more information.

5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local

Microchip Sales Office for details.

PIC32MX5XX/6XX/7XX

DS60001156H-page 4  2009-2013 Microchip Technology Inc.

TABLE 3: PIC32 USB, ETHERNET AND CAN – FEATURES

USB, Ethernet and CAN

Device

Pins

Program Memory (KB)

Data Memory (KB)

USB

Ethernet

CAN

Timers/Capture/Compare

DMA Channels

(Programmable/Dedicated)

UART(2,3)

SPI(3)

I2C™(3)

10-bit 1 Msps ADC (Channels)

Comparators

PMP/PSP

JTAG

Trace

Packages(4)

PIC32MX764F128H 64 128 + 12(1) 32 1 1 1 5/5/5 4/8 6 3 4 16 2 Yes Yes No PT,

PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT,

PIC32MX775F512H 64 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT,

PIC32MX795F512H 64 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT,

PIC32MX764F128L 100 128 + 12(1) 32 1 1 1 5/5/5 4/6 6 4 5 16 2 Yes Yes Yes PT, PF,

PIC32MX775F256L 100 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF,

PIC32MX775F512L 100 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF,

PIC32MX795F512L 100 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF,

BG, TL

Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5)

Note 1: This device features 12 KB boot Flash memory.

2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more

information.

3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more

information.

4: Refer to Section 33.0 “Packaging Information” for more information.

5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local

Microchip Sales Office for details.

 2009-2013 Microchip Technology Inc. DS60001156H-page 5

PIC32MX5XX/6XX/7XX

Pin Diagrams

64-Pin QFN(1) = Pins are up to 5V tolerant

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

PIC32MX575F256H

PMD5/RE5

PMD6/RE6

PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

VDD

AN5/C1IN+/VBUSON/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/VREF-/CVREF-/CN3/RB1

PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

VSS

64 63 62 61 60 59 58 57 56 55

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

53 52 51 50 49

AVDD

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CVREFOUT/PMA13/RB10

TDO/AN11/PMA12/RB11

VDD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

VSS

AVSS

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

SCK3/U4TX/U1RTS/OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

C1RX/RF0

VCAP

PMD0/RE0

C1TX/RF1

CN16/RD7

VDD

SOSCI/CN1/RC13

OC1/INT0/RD0

SCL1/IC3/PMCS2/PMA15/INT3/RD10

SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

D+/RG2

VUSB3V3

VBUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX575F512H

PIC32MX534F064H

PIC32MX564F064H

PIC32MX564F128H

PIC32MX5XX/6XX/7XX

DS60001156H-page 6  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin QFN(1) = Pins are up to 5V tolerant

PIC32MX675F512H

PIC32MX695F512H

PIC32MX675F256H

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

SOSCI/CN1/RC13

OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10

AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6

ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

AETXD1/ERXD3/RF0

CAP

ERXD1/PMD0/RE0

AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

PIC32MX664F064H

PIC32MX664F128H

 2009-2013 Microchip Technology Inc. DS60001156H-page 7

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

64-Pin QFN(1) = Pins are up to 5V tolerant

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6

ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLKPMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

CAP

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

PIC32MX795F512H

PIC32MX775F256H

PIC32MX775F512H

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

SOSCI/CN1/RC13

OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10

AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

PIC32MX5XX/6XX/7XX

DS60001156H-page 8  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin QFN(1) = Pins are up to 5V tolerant

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6

ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLKPMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

CAP

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

PIC32MX764F128H

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

SOSCI/CN1/RC13

OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10

AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be

connected to VSS externally.

 2009-2013 Microchip Technology Inc. DS60001156H-page 9

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

64-Pin TQFP = Pins are up to 5V tolerant

PIC32MX575F256H

PMD5/RE5

PMD6/RE6

PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

53 52 51 50 49

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

SCK3/U4TX/U1RTS/OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

C1RX/RF0

CAP

PMD0/RE0

C1TX/RF1

CN16/RD7

SOSCI/CN1/RC13

OC1/INT0/RD0

SCL1/IC3/PMCS2/PMA15/INT3/RD10

SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX575F512H

PIC32MX534F064H

PIC32MX564F064H

PIC32MX564F128H

PIC32MX5XX/6XX/7XX

DS60001156H-page 10  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin TQFP = Pins are up to 5V tolerant

PIC32MX675F512H

PIC32MX695F512H

PIC32MX675F256H

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6

ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

AETXD1/ERXD3/RF0

CAP

ERXD1/PMD0/RE0

AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

SOSCI/CN1/RC13

OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10

AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX664F064H

PIC32MX664F128H

 2009-2013 Microchip Technology Inc. DS60001156H-page 11

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

64-Pin TQFP = Pins are up to 5V tolerant

PIC32MX795F512H

PIC32MX775F256H

PIC32MX775F512H

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6

ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

CAP

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

SOSCI/CN1/RC13

OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10

AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

PIC32MX5XX/6XX/7XX

DS60001156H-page 12  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin TQFP = Pins are up to 5V tolerant

PIC32MX764F128H

ETXEN/PMD5/RE5

ETXD0/PMD6/RE6

ETXD1/PMD7/RE7

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

64 63 62 61 60 59 58 57 56 55

53 52 51 50 49

AETXEN/ETXERR/CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

SCL3/SDO3/U1TX/OC4/RD3

SDA3/SDI3/U1RXU1RX/OC3/RD2

EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1

ERXERR/PMD4/RE4

ERXCLK/EREFCLK/PMD3/RE3

ERXDV/ECRSDV/PMD2/RE2

ERXD0/PMD1/RE1

C1RX/AETXD1/ERXD3/RF0

CAP

ERXD1/PMD0/RE0

C1TX/AETXD0/ERXD2/RF1

ETXCLK/AERXERR/CN16/RD7

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

AN8/SS4/U5RX/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CV

REFOUT

/PMA13/RB10

TDO/AN11/PMA12/RB11

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5

AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14

AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15

SOSCI/CN1/RC13

OC1/INT0/RD0

ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10

AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9

RTCC/AERXD1/ETXD3/IC1/INT1/RD8

ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

Vss

 2009-2013 Microchip Technology Inc. DS60001156H-page 13

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

PMD13/CN19/RD13

IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

C1RX/PMD11/RF0

SOSCI/CN1/RC13

SDO1/OC1/INT0/RD0

SCK1/IC3/PMCS2/PMA15/RD10

SS1/IC2/RD9

RTCC/IC1/RD8

IC4/PMCS1/PMA14/RD11

SDA1/INT4/RA15

SCL1/INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

D+/RG2

VUSB3V3

VBUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2

USBID/RF3

VSS

SOSCO/T1CK/CN0/RC14

VREF+/CVREF+/PMA6/RA10

VREF-/CVREF-/PMA7/RA9

AVDD

AVSS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CVREFOUT/PMA13/RB10

AN11/PMA12/RB11

VDD

AC1RX/SS4/U5RX/U2CTS/RF12

AC1TX/SCK4/U5TX/U2RTS/RF13

SS3/U4RX/U1CTS/CN20/RD14

SCK3/U4TX/U1RTS/CN21/RD15

VDD

VSS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/SDI1/RC4

SCK2/U6TX/U3RTS/PMA5/CN8/RG6

VDD

TMS/RA0

INT1/RE8

INT2/RE9

AN5/C1IN+/VBUSON/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDA4/SDI2/U3RX/PMA4/CN9/RG7

SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1

PGED1/AN0/CN2/RB0

VDD

RG15

SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

AN12/PMA11/RB12

AN13/PMA10/RB13

AN14/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

PMD9/RG1

C1TX/PMD10/RF1

VDD

PMD14/CN15/RD6

TDO/RA5

SDA2/RA3

SCL2/RA2

VSS

VCAP

TDI/RA4

TCK/RA1

100-Pin TQF P

PMD15/CN16/RD7

= Pins are up to 5V tolerant

PIC32MX575F512L

100

PIC32MX575F256L

PIC32MX534F064L

PIC32MX564F064L

PIC32MX564F128L

PIC32MX5XX/6XX/7XX

DS60001156H-page 14  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

100-Pin TQFP

PIC32MX675F512L

PIC32MX695F512L

PIC32MX675F256L

= Pins are up to 5V tolerant

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

ETXD3/PMD13/CN19/RD13

ETXD2/IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

ETXD1/PMD11/RF0

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/SDI1/RC4

ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6

TMS/RA0

AERXD0/INT1/RE8

AERXD1/INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1

PGED1/AN0/CN2/RB0

AERXERR/RG15

ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

ETXERR/PMD9/RG1

ETXD0/PMD10/RF1

ETXEN/PMD14/CN15/RD6

CAP

DDCORE

ETXCLK/PMD15/CN16/RD7

100

SOSCI/CN1/RC13

SDO1/OC1/INT0/RD0

SS1/

IC2/RD9

RTCC/EMDIO/AEMDIO/IC1/RD8

EMDC/AEMDC/IC4/PMCS1/PMA14/RD11

AETXEN/SDA1/INT4/RA15

AETXCLK/SCL1/INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2

USBID/RF3

SOSCO/T1CK/CN0/RC14

REF

+/CV

REF

+/AERXD3/PMA6/RA10

REF

-/CV

REF

-/AERXD2/PMA7/RA9

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/ERXERR/AETXERR/PMA12/RB11

SS4/U5RX/U2CTS/RF12

SCK4/U5TX/U2RTS/RF13

AETXD0/SS3/U4RX/U1CTS/CN20/RD14

AETXD1/SCK3/U4TX/U1RTS/CN21/RD15

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

AN12/ERXD0/AECRS/PMA11/RB12

AN13/ERXD1/AECOL/PMA10/RB13

AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

TDO/RA5

SDA2/RA3

SCL2/RA2

TDI/RA4

TCK/RA1

SCK1/IC3/PMCS2/PMA15/RD10

PIC32MX664F064L

PIC32MX664F128L

PGEC2/AN6/OCFA/RB6 26

 2009-2013 Microchip Technology Inc. DS60001156H-page 15

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

100-Pin TQFP = Pins are up to 5V tolerant

PIC32MX795F512L

PIC32MX775F256L

PIC32MX775F512L

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

ETXD3/PMD13/CN19/RD13

ETXD2/IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

C2RX/PMD8/RG0

PMD4/RE4

PMD3/RE3

C1RX/ETXD1/PMD11/RF0

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/AC2TX/RC2

T4CK/AC2RX/RC3

T5CK/SDI1/RC4

ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6

TMS/RA0

AERXD0/INT1/RE8

AERXD1/INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1

PGED1/AN0/CN2/RB0

AERXERR/RG15

ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

C2TX/ETXERR/PMD9/RG1

C1TX/ETXD0/PMD10/RF1

ETXEN/PMD14/CN15/RD6

CAP

DDCORE

ETXCLK/PMD15/CN16/RD7

100

SOSCI/CN1/RC13

SDO1/OC1/INT0/RD0

SCK1/IC3/PMCS2/PMA15/RD10

SS1/

IC2

RD9

RTCC/EMDIO/AEMDIO/IC1/RD8

EMDC/AEMDC/IC4/PMCS1/PMA14/RD1

AETXEN/SDA1/INT4/RA15

AETXCLK/SCL1/INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2

USBID/RF3

SOSCO/T1CK/CN0/RC14

REF

+/CV

REF

+/AERXD3/PMA6/RA10

REF

-/CV

REF

-/AERXD2/PMA7/RA9

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/ERXERR/AETXERR/PMA12/RB11

AC1RX/SS4/U5RX/U2CTS/RF12

AC1TX/SCK4/U5TX/U2RTS/RF13

AETXD0/SS3/U4RX/U1CTS/CN20/RD14

AETXD1/SCK3/U4TX/U1RTS/CN21/RD15

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

AN12/ERXD0/AECRS/PMA11/RB12

AN13/ERXD1/AECOL/PMA10/RB13

AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

TDO/RA5

SDA2/RA3

SCL2/RA2

TDI/RA4

TCK/RA1

PIC32MX5XX/6XX/7XX

DS60001156H-page 16  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

100-Pin TQFP = Pins are up to 5V tolerant

PIC32MX764F128L

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

ETXD3/PMD13/CN19/RD13

ETXD2/IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

C1RX/ETXD1/PMD11/RF0

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/SDI1/RC4

ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6

TMS/RA0

AERXD0/INT1/RE8

AERXD1/INT2/RE9

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1

PGED1/AN0/CN2/RB0

AERXERR/RG15

ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9

MCLR

ETXERR/PMD9/RG1

C1TX/ETXD0/PMD10/RF1

ETXEN/PMD14/CN15/RD6

CAP

DDCORE

ETXCLK/PMD15/CN16/RD7

100

SOSCI/CN1/RC13

SDO1/OC1/INT0/RD0

SCK1/IC3/PMCS2/PMA15/RD10

SS1/

IC2

RD9

RTCC/EMDIO/AEMDIO/IC1/RD8

EMDC/AEMDC/IC4/PMCS1/PMA14/RD1

AETXEN/SDA1/INT4/RA15

AETXCLK/SCL1/INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

SCL3/SDO3/U1TX/RF8

D-/RG3

SDA3/SDI3/U1RX/RF2

USBID/RF3

SOSCO/T1CK/CN0/RC14

REF

+/CV

REF

+/AERXD3/PMA6/RA10

REF

-/CV

REF

-/AERXD2/PMA7/RA9

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CV

REFOUT

/PMA13/RB10

AN11/ERXERR/AETXERR/PMA12/RB11

AC1RX/SS4/U5RX/U2CTS/RF12

AC1TX/SCK4/U5TX/U2RTS/RF13

AETXD0/SS3/U4RX/U1CTS/CN20/RD14

AETXD1/SCK3/U4TX/U1RTS/CN21/RD15

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL5/SDO4/U2TX/PMA8/CN18/RF5

SDA5/SDI4/U2RX/PMA9/CN17/RF4

AN12/ERXD0/AECRS/PMA11/RB12

AN13/ERXD1/AECOL/PMA10/RB13

AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

TDO/RA5

SDA2/RA3

SCL2/RA2

TDI/RA4

TCK/RA1

 2009-2013 Microchip Technology Inc. DS60001156H-page 17

PIC32MX5XX/6XX/7XX

Pin Diagrams (Continued)

121-Pin TFBGA(1)

1234567891011

ARE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1

BNC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14

CRE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11

DRC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10

ERC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14

FMCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15

GRE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4

HRB5 RB4 VSS VDD NC VDD NC VBUS VUSB3V3RG2 RA2

JRB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3

KRB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2

LRB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

PIC32MX575F256L

Note 1: Refer to Table 4, Table 5 and Table 6 for full pin names.

= Pins are up to 5V tolerant

PIC32MX795F512L

PIC32MX575F512L

PIC32MX675F512L

PIC32MX695F512L

PIC32MX675F256L

PIC32MX775F256L

PIC32MX775F512L

PIC32MX534F064L

PIC32MX564F064L

PIC32MX564F128L

PIC32MX664F064L

PIC32MX664F128L

PIC32MX764F128L

PIC32MX5XX/6XX/7XX

DS60001156H-page 18  2009-2013 Microchip Technology Inc.

TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,

PIC32MX575F256L AND PIC32MX575F512L DEVICES

Number Full Pin Name Pin

Number Full Pin Name

A1 PMD4/RE4 E8 SDA1/INT4/RA15

A2 PMD3/RE3 E9 RTCC/IC1/RD8

A3 TRD0/RG13 E10 SS1/IC2/RD9

A4 PMD0/RE0 E11 SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR

A6 C1TX/PMD10/RF1 F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8

A7 VDD F3 SS2/U6RX/U3CTS/PMA2/CN11/RG9

A8 VSS F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC)

A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 VDD

B2 RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 INT1/RE8

B6 C1RX/PMD11/RF0 G2 INT2/RE9

B7 VCAP G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS

B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB3V3

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 PMD13/CN19/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11

D10 No Connect (NC) J6 TCK/RA1

D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC)

E2 T4CK/RC3 J9 No Connect (NC)

E3 SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

E4 T3CK/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/PMA6/RA10

 2009-2013 Microchip Technology Inc. DS60001156H-page 19

PIC32MX5XX/6XX/7XX

K4 AN8/C1OUT/RB8 L3 AVSS

K5 No Connect (NC) L4 AN9/C2OUT/RB9

K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13

K8 VDD L7 AN13/PMA10/RB13

K9 SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 SS3/U4RX/U1CTS/CN20/RD14

K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5

L2 VREF-/CVREF-/PMA7/RA9

TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,

PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

PIC32MX5XX/6XX/7XX

DS60001156H-page 20  2009-2013 Microchip Technology Inc.

TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L,

PIC32MX675F512L AND PIC32MX695F512L DEVICES

Number Fu ll Pi n Name Pin

Number Full Pin Name

A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15

A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8

A3 TRD0/RG13 E10 SS1/IC2/RD9

A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR

A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/

U3TX/PMA3/CN10/RG8

A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/

U3CTS/PMA2/CN11/RG9

A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 ETXD2/IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC)

A11 OC2/RD1 F7 No Conne ct (NC)

B1 No Connect (NC) F8 VDD

B2 AERXERR/RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 AERXD0/INT1/RE8

B6 ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9

B7 VCAP G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS

B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 ETXCLK/PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB3V3

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 ETXD3/PMD13/CN19/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11

D10 No Connect (NC) J6 TCK/RA1

D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC)

E2 T4CK/RC3 J9 No Connect (NC)

E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

E4 T3CK/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

 2009-2013 Microchip Technology Inc. DS60001156H-page 21

PIC32MX5XX/6XX/7XX

K4 AN8/C1OUT/RB8 L3 AVSS

K5 No Connect (NC) L4 AN9/C2OUT/RB9

K6 SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK4/U5TX/U2RTS/RF13

K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13

K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14

K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5

L2 VREF-/CVREF-/AERXD2/PMA7/RA9

TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L,

PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

PIC32MX5XX/6XX/7XX

DS60001156H-page 22  2009-2013 Microchip Technology Inc.

TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND

PIC32MX795F512L DEVICES

Number Full Pin Name Pin

Number Full Pin Name

A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15

A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8

A3 TRD0/RG13 E10 SS1/IC2/RD9

A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14

A5 C2RX/PMD8/RG0 F1 MCLR

A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/

U3TX/PMA3/CN10/RG8

A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/

U3CTS/PMA2/CN11/RG9

A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 ETXD2/IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC)

A11 OC2/RD1 F7 No Connect (NC)

B1 N o Connect (NC) F8 VDD

B2 AERXERR/RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 AERXD0/INT1/RE8

B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9

B7 VCAP G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS

B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 ETXCLK/PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB3V3

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 ETXD3/PMD13/CN19/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11

D10 No Connect (NC) J 6 TCK/RA1

D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12

E1 T 5CK/SDI1/RC4 J8 No Connect (NC)

E2 T 4CK/AC2RX/RC3 J9 No Connect (NC)

E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

E4 T3CK/AC2TX/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 C2TX/ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

 2009-2013 Microchip Technology Inc. DS60001156H-page 23

PIC32MX5XX/6XX/7XX

K4 AN8/C1OUT/RB8 L3 AVSS

K5 N o Connect (NC) L4 AN9/C2OUT/RB9

K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13

K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13

K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14

K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5

L2 VREF-/CVREF-/AERXD2/PMA7/RA9

TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND

PIC32MX795F512L DEVICES (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

PIC32MX5XX/6XX/7XX

DS60001156H-page 24  2009-2013 Microchip Technology Inc.

TABLE 7: PIN NAME: PIC32MX764F128L DEVICE

Number Full Pin Name Pin

Number Full Pin Name

A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15

A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8

A3 TRD0/RG13 E10 SS1/IC2/RD9

A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR

A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/

U3TX/PMA3/CN10/RG8

A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/

U3CTS/PMA2/CN11/RG9

A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

A9 ETXD2/IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC)

A11 OC2/RD1 F7 No Connect (NC)

B1 N o Connect (NC) F8 VDD

B2 AERXERR/RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 AERXD0/INT1/RE8

B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9

B7 VCAP G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS

B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 ETXCLK/PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB3V3

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 ETXD3/PMD13/CN19/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11

D10 No Connect (NC) J 6 TCK/RA1

D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12

E1 T 5CK/SDI1/RC4 J8 No Connect (NC)

E2 T 4CK/RC3 J9 No Connect (NC)

E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8

E4 T3CK/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10

 2009-2013 Microchip Technology Inc. DS60001156H-page 25

PIC32MX5XX/6XX/7XX

K4 AN8/C1OUT/RB8 L3 AVSS

K5 N o Connect (NC) L4 AN9/C2OUT/RB9

K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13

K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13

K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14

K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5

L2 VREF-/CVREF-/AERXD2/PMA7/RA9

TABLE 7: PIN NAME: PIC32MX764F128L DEVICE (CONT INUED)

Number Full Pin Name Pin

Number Full Pin Name

PIC32MX5XX/6XX/7XX

DS60001156H-page 26  2009-2013 Microchip Technology Inc.

Pin Diagrams (Continued)

124-Pin VTLA(1) = Pins are up to 5V tolerant

Note 1: Refer to Table 8 for the full list of pin names.

A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51

A1 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50

A2 B1 A49

A16 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 A35

A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34

A3 B2 B41 A48

A4 B3 B40 A47

A5 B4 B39 A46

A6 B5 B38 A45

A7 B6 B37 A44

A8 B7 B36 A43

A10 B9 B34 A41

A11 B10 B33 A40

A12 B11 B32 A39

A13 B12 B31 A38

A14 B13 B30 A37

A15 B29 A36

A9 B8 B35 A42

PIC32MX675F512L

PIC32MX695F512L

B32

B31

B30

PIC32MX795F512L

 2009-2013 Microchip Technology Inc. DS60001156H-page 27

PIC32MX5XX/6XX/7XX

TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES

Package

Bump # Full Pin Name Package

Bump # Full Pin Name

A1 No Connect (NC) A52 OC2/RD1

A2 AERXERR/RG15 A53 OC4/RD3

A3 VSS A54 ETXD3/PMD13/CN19/RD13

A4 PMD6/RE6 A55 PMRD/CN14/RD5

A5 T2CK/RC1 A56 ETXCLK/PMD15/CN16/RD7

A6 T4CK/AC2RX(1)/RC3 A57 No Connect (NC)

A7 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 A58 No Connect (NC)

A8 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/

U3TX/PMA3/CN10/RG8 A59 VDD

A9 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/

U3CTS/PMA2/CN11/RG9 A60 C1TX(1)/ETXD0/PMD10/RF1

A10 VDD A61 C2RX(1)/PMD8/RG0

A11 AERXD0/INT1/RE8 A62 TRD3/RA7

A12 AN5/C1IN+/VBUSON/CN7/RB5 A63 VSS

A13 AN3/C2IN+/CN5/RB3 A64 PMD1/RE1

A14 VDD A65 TRD1/RG12

A15 PGEC1/AN1/CN3/RB1 A66 PMD2/RE2

A16 No Connect (NC) A67 PMD4/RE4

A17 No Connect (NC) A68 No Connect (NC)

A18 No Connect (NC) B1 VDD

A19 No Connect (NC) B2 PMD5/RE5

A20 PGEC2/AN6/OCFA/RB6 B3 PMD7/RE7

A21 VREF-/CVREF-/AERXD2/PMA7/RA9 B4 T3CK/AC2TX/RC2

A22 AVDD B5 T5CK/SDI1/RC4

A23 AN8/C1OUT/RB8 B6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7

A24 AN10/CVREFOUT/PMA13/RB10 B7 MCLR

A25 VSS B8 VSS

A26 TCK/RA1 B9 TMS/RA0

A27 AC1RX(1)/SS4/U5RX/U2CTS/RF12 B10 AERXD1/INT2/RE9

A28 AN13/ERXD1/AECOL/PMA10/RB13 B11 AN4/C1IN-/CN6/RB4

A29 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 B12 VSS

A30 VDD B13 AN2/C2IN-/CN4/RB2

A31 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 B14 PGED1/AN0/CN2/RB0

A32 SCL5/SDO4/U2TX/PMA8/CN18/RF5 B15 No Connect (NC)

A33 No Connect (NC) B16 PGED2/AN7/RB7

A34 No Connect (NC) B17 VREF+/CVREF+/AERXD3/PMA6/RA10

A35 USBID/RF3 B18 AVSS

A36 SDA3/SDI3/U1RX/RF2 B19 AN9/C2OUT/RB9

A37 VBUS B20 AN11/ERXERR/AETXERR/PMA12/RB11

A38 D-/RG3 B21 VDD

A39 SCL2/RA2 B22 AC1TX(1)/SCK4/U5TX/U2RTS/RF13

A40 TDI/RA4 B23 AN12/ERXD0/AECRS/PMA11/RB12

A41 VDD B24 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14

A42 OSC2/CLKO/RC15 B25 VSS

A43 VSS B26 AETXD0/SS3/U4RX/U1CTS/CN20/RD14

A44 AETXEN/SDA1/INT4/RA15 B27 SDA5/SDI4/U2RX/PMA9/CN17/RF4

A45 SS1/IC2/RD9 B28 No Connect (NC)

A46 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 B29 SCL3/SDO3/U1TX/RF8

A47 SOSCI/CN1/RC13 B30 VUSB3V3

A48 VDD B31 D+/RG2

A49 No Connect (NC) B32 SDA2/RA3

A50 No Connect (NC) B33 TDO/RA5

A51 No Connect (NC) B34 OSC1/CLKI/RC12

Note 1: This pin is only available on PIC32MX795F512L devices.

PIC32MX5XX/6XX/7XX

DS60001156H-page 28  2009-2013 Microchip Technology Inc.

B35 No Connect (NC) B46 VSS

B36 AETXCLK/SCL1/INT3/RA14 B47 No Connect (NC)

B37 RTCC/EMDIO/AEMDIO/IC1/RD8 B48 VCAP

B38 SCK1/IC3/PMCS2/PMA15/RD10 B49 C1RX/ETXD1/PMD11/RF0

B39 SDO1/OC1/INT0/RD0 B50 C2TX/ETXERR/PMD9/RG1

B40 SOSCO/T1CK/CN0/RC14 B51 TRCLK/RA6

B41 VSS B52 PMD0/RE0

B42 OC3/RD2 B53 VDD

B43 ETXD2/IC5/PMD12/RD12 B54 TRD2/RG14

B44 OC5/PMWR/CN13/RD4 B55 TRD0/RG13

B45 ETXEN/PMD14/CN15/RD6 B56 PMD3/RE3

TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES

Package

Bump # Full Pin Name Package

Bump # Full Pin Name

Note 1: This pin is only available on PIC32MX795F512L devices.

 2009-2013 Microchip Technology Inc. DS60001156H-page 29
PIC32MX5XX/6XX/7XX
Table of Content s
0 Device Overview ........................................................................................................................................................................ 33
0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 45
0 CPU............................................................................................................................................................................................ 49
0 Memory Organization................................................................................................................................................................. 55
0 Flash Program Memory............................................................................................................................................................ 123
0 Resets...................................................................................................................................................................................... 127
0 Interrupt Controller ................................................................. .................................................................................................. 131
0 Oscillator Configuration............................................................................................................................................................ 141
0 Prefetch Cache......................................................................................................................................................................... 147
0 Direct Memory Access (DMA) Controller ................................................................................................................................. 157
0 USB On-The-Go (OTG)............................................................................................................................................................ 173
0 I/O Ports................................................................................................................................................................................... 193
0 Timer1...................................................................................................................................................................................... 197
0 Timer2/3, Timer4/5................................................................................................................................................................... 201
0 Input Capture............................................................................................................................................................................ 205
0 Output Compare....................................................................................................................................................................... 209
0 Serial Peripheral Interface (SPI)............................................................................................................................................... 211
0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 217
0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 223
0 Parallel Master Port (PMP)....................................................................................................................................................... 229
0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 237
0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................. 247
0 Controller Area Network (CAN)................................................................................................................................................ 255
0 Ethernet Controller................................................................................................................................................................... 289
0 Comparator .............................................................................................................................................................................. 331
0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 335
0 Power-Saving Features ........................................................................................................................................................... 337
0 Special Features ...................................................................................................................................................................... 339
0 Instruction Set .......................................................................................................................................................................... 353
0 Development Support............................................................................................................................................................... 355
0 Electrical Characteristics.......................................................................................................................................................... 359
0 DC and AC Device Characteristics Graphs.............................................................................................................................. 407
0 Packaging Information.............................................................................................................................................................. 409
The Microchip Web Site..................................................................................................................................................................... 443
Customer Change Notification Service.. ............................................................................................................................................ 443
Customer Support.............................................................................................................................................................................. 443
Reader Response.............................................................................................................................................................................. 444
Product Identification System ............................................................................................................................................................ 445

PIC32MX5XX/6XX/7XX

DS60001156H-page 30  2009-2013 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of

your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our pub-

lications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications

Department via E-mail at docerrors@microchip.com or fax the Reader Response F orm in the back of this data

sheet to (480) 792-4150 . We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner

of any page. The last character o f the literature numbe r is the version number, (e.g., DS3 0000000A is version A of

document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may

exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The

errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature

number) you ar e usi n g.

Customer Notific at ion Syst em

 2009-2013 Microchip Technology Inc. DS60001156H-page 31

PIC32MX5XX/6XX/7XX

Referenced Sources

This device data sheet is based on the following

individual chapters of the “PIC32 Family Reference

Manual”. These documents should be considered as

the general reference for the operation of a particular

module or device feature.

•Section 1. “Introduction” (DS60001127)

•Section 2. “CPU” (DS60001113)

•Section 4. “Prefetch Cache” (DS60001119)

•Section 3. “Memory Organization ” (DS60 001115)

•Section 5. “Flash Program Memory” (DS60001121)

•Section 6. “Oscillator Configuration” (DS60 001112)

•Section 7. “Resets” (DS60001118)

•Section 8. “Interrupt Controller” (DS600 01108)

•Section 9. “Watchdog Timer and Power-up Timer (DS60001114)

•Section 10. “Power-Saving Features” (DS60001130)

•Section 12. “I/O Ports” (DS60001120)

•Section 13. “Parallel Master Port (PMP)” (DS60001128)

•Section 14. “Timers” (DS60001105)

•Section 15. “Input Capture” (DS60001122)

•Section 16. “Output Capture” (DS60001111)

•Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)

•Section 19. “Compa rator” (DS6000 1110)

•Section 20. “Compa rator Voltage Reference (CVREF)” (DS60001109)

•Section 21. “Universal Asynchronous Rece iver Transmitter (UART)” (DS6 0001107 )

•Section 23. “Serial Peripheral Interface (SPI)” (DS60 001106)

•Section 24. “Inter-Integrated Circuit (I2C™)” (DS60001116)

•Section 27. “USB On-The-Go (OTG)” (DS60001126)

•Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)

•Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)

•Section 32. “Configuration” (DS60001124)

•Section 33. “Programming and Diagnostics” (DS60001129)

•Section 34. “Controller Area Network (CAN)” (DS60001154)

•Section 35. “Ethernet Controller” (DS60001155)

Note 1: To access the documents listed below,

browse to the documentation section of

the PIC32MX795F512L product page on

the Microchip web site

(www.microchip.com) or select a family

reference manual section from the

following list.

In addition to parameters, features, and

other documentation, the resulting page

provides links to the related family

reference manual sections.

PIC32MX5XX/6XX/7XX

DS60001156H-page 32  2009-2013 Microchip Technology Inc.

NOTES:

 2009-2013 Microchip Technology Inc. DS60001156H-page 33

PIC32MX5XX/6XX/7XX

1.0 DEVICE OVERVIEW This document contains device-specific information for

PIC32MX5XX/6XX/7XX devices.

Figure 1-1 illustrates a general block diagram of the

core and peripheral modules in the PIC32MX5XX/6XX/

7XX family of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

FIGURE 1-1: BLOCK DIAGRAM(1,2)

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section of the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note 1: Some features are not available on all devices.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

UART1-6

Comparators

PORTA

PORTD

PORTE

PORTF

PORTG

PORTB

CN1-22

JTAG Priority

DMAC

ICD

MIPS32® M4K®

IS DS

EJTAG INT

Bus Matrix

Prefetch Data RAM Peripheral Bridge

128

128-bit Wide

Flash

32 32 32 32

Peripheral Bus Clocked by PBCLK

Program Flash Memory

Controller

Module

32 32

Interrupt

Controller

BSCAN

PORTC

PMP

I2C1-5

SPI1-4

IC1-5

PWM

OC1-5

OSC1/CLKI

OSC2/CLKO VDD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators Regulator

Voltage

VCAP

OSC/SOSC

Oscillators

PLL

Dividers

SYSCLK

PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB USBCLK

RTCC

10-bit ADC

Timer1-5

CAN1, CAN2

ETHERNET

32 32

CPU Core

PIC32MX5XX/6XX/7XX

DS60001156H-page 34  2009-2013 Microchip Technology Inc.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

AN0 16 25 K2 B14 I Analog Analog input channels

AN1 15 24 K1 A15 I Analog

AN2 14 23 J2 B13 I Analog

AN3 13 22 J1 A13 I Analog

AN4 12 21 H2 B11 I Analog

AN5 11 20 H1 A12 I Analog

AN6 17 26 L1 A20 I Analog

AN7 18 27 J3 B16 I Analog

AN8 21 32 K4 A23 I Analog

AN9 22 33 L4 B19 I Analog

AN10 23 34 L5 A24 I Analog

AN11 24 35 J5 B20 I Analog

AN12 27 41 J7 B23 I Analog

AN13 28 42 L7 A28 I Analog

AN14 29 43 K7 B24 I Analog

AN15 30 44 L8 A29 I Analog

CLKI 39 63 F9 B34 I ST/

CMOS External clock source input. Always

associated with OSC1 pin function.

CLKO 40 64 F11 A42 O —

Oscillator crystal output. Connects to

crystal or resonator in Cryst al Oscillator

mode. Optionally functions as CLKO in

RC and EC modes. Always associated

with OSC2 pin function.

OSC1 39 63 F9 B34 I ST/

CMOS

Oscillator crystal input. ST buffer when

configured in RC mode; CMOS

otherwise.

OSC2 40 64 F11 A42 I/O —

Oscillator crystal output. Connects to

crystal or resonator in Cryst al Oscillator

mode. Optionally functions as CLKO in

RC and EC modes.

SOSCI 47 73 C10 A47 I ST/

CMOS 32.768 kHz low-power oscillator crystal

input; CMOS otherwise

SOSCO 48 74 B11 B40 O — 32.768 kHz low-power oscillator crystal

output

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethern et C on troller” for more information.

 2009-2013 Microchip Technology Inc. DS60001156H-page 35

PIC32MX5XX/6XX/7XX

CN0 48 74 B11 B40 I ST Change notification inputs. Can be

software programmed for internal weak

pull-ups on all inputs.

CN1 47 73 C10 A47 I ST

CN2 16 25 K2 B14 I ST

CN3 15 24 K1 A15 I ST

CN4 14 23 J2 B13 I ST

CN5 13 22 J1 A13 I ST

CN6 12 21 H2 B11 I ST

CN7 11 20 H1 A12 I ST

CN8 4 10 E3 A7 I ST

CN9 5 11 F4 B6 I ST

CN10 6 12 F2 A8 I ST

CN11 8 14 F3 A9 I ST

CN12 30 44 L8 A29 I ST

CN13 52 81 C8 B44 I ST

CN14 53 82 B8 A55 I ST

CN15 54 83 D7 B45 I ST

CN16 55 84 C7 A56 I ST

CN17 31 49 L10 B27 I ST

CN18 32 50 L11 A32 I ST

CN19 — 80 D8 A54 I ST

CN20 — 47 L9 B26 I ST

CN21 — 48 K9 A31 I ST

IC1 42 68 E9 B37 I ST Capture Inputs 1-5

IC2 43 69 E10 A45 I ST

IC3 44 70 D11 B38 I ST

IC4 45 71 C11 A46 I ST

IC5 52 79 A9 A60 I ST

OCFA 17 26 L1 A20 I ST Output Compare Fault A Input

OC1 46 72 D9 B39 O — Output Compare Output 1

OC2 49 76 A11 A52 O — Output Compare Output 2

OC3 50 77 A10 B42 O — Output Compare Output 3

OC4 51 78 B9 A53 O — Output Compare Output 4

OC5 52 81 C8 B44 O — Output Compare Output 5

OCFB 30 44 L8 A29 I ST Output Compare Fault B Input

INT0 46 72 D9 B39 I ST External Interrupt 0

INT1 42 18 G1 A11 I ST External Interrupt 1

INT2 43 19 G2 B10 I ST External Interrupt 2

INT3 44 66 E11 B36 I ST External Interrupt 3

INT4 45 67 E8 A44 I ST External Interrupt 4

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethernet Controller” for more information.

PIC32MX5XX/6XX/7XX

DS60001156H-page 36  2009-2013 Microchip Technology Inc.

RA0 — 17 G3 B9 I/O ST PORTA is a bidirectional I/O port

RA1 — 38 J6 A26 I/O ST

RA2 — 58 H11 A39 I/O ST

RA3 — 59 G10 B32 I/O ST

RA4 — 60 G11 A40 I/O ST

RA5 — 61 G9 B33 I/O ST

RA6 — 91 C5 B51 I/O ST

RA7 — 92 B5 A62 I/O ST

RA9 — 28 L2 A21 I/O ST

RA10 — 29 K3 B17 I/O ST

RA14 — 66 E11 B36 I/O ST

RA15 — 67 E8 A44 I/O ST

RB0 16 25 K2 B14 I/O ST PORTB is a bidirectional I/O port

RB1 15 24 K1 A15 I/O ST

RB2 14 23 J2 B13 I/O ST

RB3 13 22 J1 A13 I/O ST

RB4 12 21 H2 B11 I/O ST

RB5 11 20 H1 A12 I/O ST

RB6 17 26 L1 A20 I/O ST

RB7 18 27 J3 B16 I/O ST

RB8 21 32 K4 A23 I/O ST

RB9 22 33 L4 B19 I/O ST

RB10 23 34 L5 A24 I/O ST

RB11 24 35 J5 B20 I/O ST

RB12 27 41 J7 B23 I/O ST

RB13 28 42 L7 A28 I/O ST

RB14 29 43 K7 B24 I/O ST

RB15 30 44 L8 A29 I/O ST

RC1 — 6 D1 A5 I/O ST PORTC is a bidirectional I/O port

RC2 — 7 E4 B4 I/O ST

RC3 — 8 E2 A6 I/O ST

RC4 — 9 E1 B5 I/O ST

RC12 39 63 F9 B34 I/O ST

RC13 47 73 C10 A47 I/O ST

RC14 48 74 B11 B40 I/O ST

RC15 40 64 F11 A42 I/O ST

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethern et C on troller” for more information.

 2009-2013 Microchip Technology Inc. DS60001156H-page 37

PIC32MX5XX/6XX/7XX

RD0 46 72 D9 B39 I/O ST PORTD is a bidirectional I/O port

RD1 49 76 A11 A52 I/O ST

RD2 50 77 A10 B42 I/O ST

RD3 51 78 B9 A53 I/O ST

RD4 52 81 C8 B44 I/O ST

RD5 53 82 B8 A55 I/O ST

RD6 54 83 D7 B45 I/O ST

RD7 55 84 C7 A56 I/O ST

RD8 42 68 E9 B37 I/O ST

RD9 43 69 E10 A45 I/O ST

RD10 44 70 D11 B38 I/O ST

RD11 45 71 C11 A46 I/O ST

RD12 — 79 A9 B43 I/O ST

RD13 — 80 D8 A54 I/O ST

RD14 — 47 L9 B26 I/O ST

RD15 — 48 K9 A31 I/O ST

RE0 60 93 A4 B52 I/O ST PORTE i s a bidirectional I/O port

RE1 61 94 B4 A64 I/O ST

RE2 62 98 B3 A66 I/O ST

RE3 63 99 A2 B56 I/O ST

RE4 64 100 A1 A67 I/O ST

RE5 1 3 D3 B2 I/O ST

RE6 2 4 C1 A4 I/O ST

RE7 3 5 D2 B3 I/O ST

RE8 — 18 G1 A11 I/O ST

RE9 — 19 G2 B10 I/O ST

RF0 58 87 B6 B49 I/O ST PORTF is a bidirectional I/O port

RF1 59 88 A6 A60 I/O ST

RF2 — 52 K11 A36 I/O ST

RF3 33 51 K10 A35 I/O ST

RF4 31 49 L10 B27 I/O ST

RF5 32 50 L11 A32 I/O ST

RF8 — 53 J10 B29 I/O ST

RF12 — 40 K6 A27 I/O ST

RF13 — 39 L6 B22 I/O ST

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethernet Controller” for more information.

PIC32MX5XX/6XX/7XX

DS60001156H-page 38  2009-2013 Microchip Technology Inc.

RG0 — 90 A5 A61 I/O ST PORTG is a bidirectional I/O port

RG1 — 89 E6 B50 I/O ST

RG6 4 10 E3 A7 I/O ST

RG7 5 11 F4 B6 I/O ST

RG8 6 12 F2 A8 I/O ST

RG9 8 14 F3 A9 I/O ST

RG12 — 96 C3 A65 I/O ST

RG13 — 97 A3 B55 I/O ST

RG14 — 95 C4 B54 I/O ST

RG15 — 1 B2 A2 I/O ST

RG2 37 57 H10 B31 I ST PORTG input pins

RG3 36 56 J11 A38 I ST

T1CK 48 74 B11 B40 I ST Timer1 external clock input

T2CK — 6 D1 A5 I ST Timer2 external clock input

T3CK — 7 E4 B4 I ST Timer3 external clock input

T4CK — 8 E2 A6 I ST Timer4 external clock input

T5CK — 9 E1 B5 I ST Timer5 external clock input

U1CTS 43 47 L9 B26 I ST UART1 clear to send

U1RTS 49 48 K9 A31 O — UART1 ready to send

U1RX 50 52 K11 A36 I ST UART1 receive

U1TX 51 53 J10 B29 O — UART1 transmit

U3CTS 814F3

A9 I ST UART3 clear to send

U3RTS 410E3

A7 O — UART3 ready to send

U3RX 511F4B6

I ST UART3 receive

U3TX 612F2A8

O — UART3 transmit

U2CTS 21 40 K6 A27 I ST UART2 clear to send

U2RTS 29 39 L6 B22 O — UART2 ready to send

U2RX 31 49 L10 B27 I ST UART2 receive

U2TX 32 50 L11 A32 O — UART2 transmit

U4RX 43 47 L9 B26 I ST UART4 receive

U4TX 49 48 K9 A31 O — UART4 transmit

U6RX 814F3A9

I ST UART6 receive

U6TX 410E3A7

O — UART6 transmit

U5RX 21 40 K6 A27 I ST UART5 receive

U5TX 29 39 L6 B22 O — UART5 transmit

SCK1 — 70 D11 B38 I/O ST Synchronous serial clock input/output

for SPI1

SDI1 — 9 E1 B5 I ST SPI1 data in

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethern et C on troller” for more information.

 2009-2013 Microchip Technology Inc. DS60001156H-page 39

PIC32MX5XX/6XX/7XX

SDO1 — 72 D9 B39 O — SPI1 data out

SS1 —69E10

A45 I/O ST SPI1 slave synchronization or frame

pulse I/O

SCK3 49 48 K9 A31 I/O ST Synchronous serial clock input/output

for SPI3

SDI3 50 52 K11 A36 I ST SPI3 data in

SDO3 51 53 J10 B29 O — SPI3 data out

SS3 43 47 L9 B26 I/O ST SPI3 slave synchronization or frame

pulse I/O

SCK2 4 10 E3 A7 I/O ST Synchronous serial clock input/output

for SPI2

SDI2 5 11 F4 B6 I ST SPI2 data in

SDO2 6 12 F2 A8 O — SPI2 data out

SS2 814F3

A9 I/O ST SPI2 slave synchronization or frame

pulse I/O

SCK4 29 39 L6 B22 I/O ST Synchronous serial clock input/output

for SPI4

SDI4 31 49 L10 B27 I ST SPI4 data in

SDO4 32 50 L11 A32 O — SPI4 data out

SS4 21 40 K6 A27 I/O ST SPI4 slave synchronization or frame

pulse I/O

SCL1 44 66 E11 B36 I/O ST Synchronous serial clock input/output

for I2C1

SDA1 43 67 E8 A44 I/O ST Synchronous serial data input/outp ut

for I2C1

SCL3 51 53 J10 B29 I/O ST Synchronous serial clock input/output

for I2C3

SDA3 50 52 K11 A36 I/O ST Synchronous serial data input/output

for I2C3

SCL2 — 58 H11 A39 I/O ST Synchronous serial clock input/ou tput

for I2C2

SDA2 — 59 G10 B32 I/O ST Synchronous serial data input/output

for I2C2

SCL4 6 12 F2 A8 I/O ST Synchronous serial clock input/output

for I2C4

SDA4 5 11 F4 B6 I/O ST Synchronous serial data input/output

for I2C4

SCL5 32 50 L11 A32 I/O ST Synchronous serial clock input/output

for I2C5

SDA5 31 49 L10 B27 I/O ST Synchronous serial data input/output

for I2C5

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethernet Controller” for more information.

PIC32MX5XX/6XX/7XX

DS60001156H-page 40  2009-2013 Microchip Technology Inc.

TMS 23 17 G3 B9 I ST JTAG Test mode select pin

TCK 27 38 J6 A26 I ST JTAG test clock input pin

TDI 28 60 G11 A40 I ST JTAG test data input pin

TDO 24 61 G9 B33 O — JTAG test data output pin

RTCC 42 68 E9 B37 O — Real-Time Clock alarm output

CVREF-1528L2

A21 I Analog Comparator Voltage Reference (low)

CVREF+ 16 29 K3 B17 I Analog Comparator Vo ltage Reference (h igh)

CVREFOUT 23 34 L5 A24 O Analog Comparator Voltage Reference output

C1IN- 12 21 H2 B11 I Analog Comparator 1 negative input

C1IN+ 11 20 H1 A12 I Analog Comparator 1 positive input

C1OUT 21 32 K4 A23 O — Comparator 1 output

C2IN- 14 23 J2 B13 I Analog Comparator 2 negative input

C2IN+ 13 22 J1 A13 I Analog Comparator 2 positive input

C2OUT 22 33 L4 B19 O — Comparator 2 output

PMA0 30 44 L8 A29 I/O TTL/ST Parallel Master Port Address bit 0 input

(Buffered Slave modes) and output

(Master modes)

PMA1 29 43 K7 B24 I/O TTL/ST Parallel Master Port Address bit 1 input

(Buffered Slave modes) and output

(Master modes)

PMA2 8 14 F3 A9 O — Parallel Master Port address

(Demultiplexed Master modes)

PMA3 6 12 F2 A8 O —

PMA4 5 11 F4 B6 O —

PMA5 4 10 E3 A7 O —

PMA6 16 29 K3 B17 O —

PMA7 22 28 L2 A21 O —

PMA8 32 50 L11 A32 O —

PMA9 31 49 L10 B27 O —

PMA10 28 42 L7 A28 O —

PMA11 27 41 J7 B23 O —

PMA12 24 35 J5 B20 O —

PMA13 23 34 L5 A24 O —

PMA14 45 71 C11 A46 O —

PMA15 44 70 D11 B38 O —

PMCS1 45 71 C11 A46 O — Parallel Master Port Chip Select 1

strobe

PMCS2 44 70 D11 B38 O — Parallel Master Port Chip Select 2

strobe

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethern et C on troller” for more information.

 2009-2013 Microchip Technology Inc. DS60001156H-page 41

PIC32MX5XX/6XX/7XX

PMD0 60 93 A4 B52 I/O TTL/ST Parallel Master Port data

(Demultipl exe d Master mo de ) or

address/data (Multiplexed Master

modes)

PMD1 61 94 B4 A64 I/O TTL/ST

PMD2 62 98 B3 A66 I/O TTL/ST

PMD3 63 99 A2 B56 I/O TTL/ST

PMD4 64 100 A1 A67 I/O TTL/ST

PMD5 1 3 D3 B2 I/O TTL/ST

PMD6 2 4 C1 A4 I/O TTL/ST

PMD7 3 5 D2 B3 I/O TTL/ST

PMD8 — 90 A5 A61 I/O TTL/ST

PMD9 — 89 E6 B50 I/O TTL/ST

PMD10 — 88 A6 A60 I/O TTL/ST

PMD11 — 87 B6 B49 I/O TTL/ST

PMD12 — 79 A9 B43 I/O TTL/ST

PMD13 — 80 D8 A54 I/O TTL/ST

PMD14 — 83 D7 B45 I/O TTL/ST

PMD15 — 84 C7 A56 I/O TTL/ST

PMALL 30 44 L8 A29 O — Parallel Master Port address latch

enable low byte (Multiplexed Master

modes)

PMALH 29 43 K7 B24 O — Parallel Master Port address latch

enable high byte (Multiplexed Master

modes)

PMRD 53 82 B8 A55 O — Parallel Master Port read strobe

PMWR 52 81 C8 B44 O — Parallel Master Port write strobe

VBUS 34 54 H8 A37 I Analog USB bus power monitor

VUSB3V335 55 H9 B30 P — USB internal transceiver supply. If the

USB module is not used, this pin must

be connected to VDD.

VBUSON 11 20 H1 A12 O — USB Host and OTG bus power control

output

D+ 37 57 H10 B31 I/O Analog USB D+

D- 36 56 J11 A38 I/O Analog USB D-

USBID 33 51 K10 A35 I ST USB OTG ID detect

C1RX 58 87 B6 B49 I ST CAN1 bus receive pin

C1TX 59 88 A6 A60 O — CAN1 bus transmit pin

AC1RX 32 40 K6 A27 I ST Altern ate CAN1 bus receive pin

AC1TX 31 39 L6 B22 O — Alternate CAN1 bus transmit pin

C2RX 29 90 A5 A61 I ST CAN2 bus receive pin

C2TX 21 89 E6 B50 O — CAN2 bus transmit pin

AC2RX — 8 E2 A6 1 ST Alternate CAN2 bus receive pin

AC2TX — 7 E4 B4 O — Alternate CAN2 bus transmit pin

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethernet Controller” for more information.

PIC32MX5XX/6XX/7XX

DS60001156H-page 42  2009-2013 Microchip Technology Inc.

ERXD0 61 41 J7 B23 I ST Ethernet Receive Data 0(2)

ERXD1 60 42 L7 A28 I ST Ethernet Receive Data 1(2)

ERXD2 59 43 K7 B24 I ST Ethernet Receive Data 2(2)

ERXD3 58 44 L8 A29 I ST Ethernet Receive Data 3(2)

ERXERR 64 35 J5 B20 I ST Ethernet receive error input(2)

ERXDV 62 12 F2 A8 I ST Ethern et receive data valid(2)

ECRSDV 62 12 F2 A8 I ST Ethernet carrier sense data valid(2)

ERXCLK 63 14 F3 A9 I ST Ethernet receive clock(2)

EREFCLK 63 14 F3 A9 I ST Ethernet reference clock(2)

ETXD0 2 88 A6 A60 O — Ethernet Transmit Data 0(2)

ETXD1 3 87 B6 B49 O — Ethernet Transmit Data 1(2)

ETXD2 43 79 A9 B43 O — Ethernet Transmit Data 2(2)

ETXD3 42 80 D8 A54 O — Ethernet Transmit Data 3(2)

ETXERR 54 89 E6 B50 O — Ethernet transmit error(2)

ETXEN 1 83 D7 B45 O — Ethernet transmit enable(2)

ETXCLK 55 84 C7 A56 I ST Ethernet transmit clock(2)

ECOL 44 10 E3 A7 I ST Ethernet collision detect(2)

ECRS 45 11 F4 B6 I ST Ethernet carrier sense(2)

EMDC 30 71 C11 A46 O — Ethernet management data clock(2)

EMDIO 49 68 E9 B37 I/O — Ethernet management data(2)

AERXD0 43 18 G1 A11 I ST Alternate Ethernet Receive Data 0(2)

AERXD1 42 19 G2 B10 I ST Alternate Ethernet Receive Data 1(2)

AERXD2 — 28 L2 A21 I ST Alternate Ethernet Receive Data 2(2)

AERXD3 — 29 K3 B17 I ST Alternate Ethernet Receive Data 3(2)

AERXERR 55 1 B2 A2 I ST Alternate Ethernet receive error input(2)

AERXDV — 12 F2 A8 I ST Alternate Ethernet receive data valid(2)

AECRSDV 44 12 F2 A8 I ST Alternate Ethernet carrier sense data

valid(2)

AERXCLK — 14 F3 A9 I ST Alternate Ethernet receive clock(2)

AEREFCLK 45 14 F3 A9 I ST Alternate Ethernet reference clock(2)

AETXD0 59 47 L9 B26 O — Alternate Ethernet Transmit Data 0(2)

AETXD1 58 48 K9 A31 O — Alternate Ethernet Transmit Data 1(2)

AETXD2 — 44 L8 A29 O — Alternate Ethernet Transmit Data 2(2)

AETXD3 — 43 K7 B24 O — Alternate Ethernet Transmit Data 3(2)

AETXERR — 35 J5 B20 O — Alternate Ethernet transmit error(2)

AETXEN 54 67 E8 A44 O — Alternate Ethernet transmit enable(2)

AETXCLK — 66 E11 B36 I ST Alternate Ethernet transmit clock(2)

AECOL — 42 L7 A28 I ST Alternate Ethernet collision detect(2)

AECRS — 41 J7 B23 I ST Alternate Ethernet carrier sense(2)

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethern et C on troller” for more information.

 2009-2013 Microchip Technology Inc. DS60001156H-page 43

PIC32MX5XX/6XX/7XX

AEMDC 30 71 C11 A46 O — Alternate Ethernet Management Data

clock(2)

AEMDIO 49 68 E9 B37 I/O — Alternate Ethernet Management Data(2)

TRCLK — 91 C5 B51 O — Trace clock

TRD0 — 97 A3 B55 O — Trace Data bits 0-3

TRD1 — 96 C3 A65 O —

TRD2 — 95 C4 B54 O —

TRD3 — 92 B5 A62 O —

PGED1 16 25 K2 B14 I/O ST Data I/O pin for Programming/

Debugging Communication Channel 1

PGEC1 15 24 K1 A15 I ST Clock input pin for Programming/

Debugging Communication Channel 1

PGED2 18 27 J3 B16 I/O ST Data I/O pin for Programming/

Debugging Communication Channel 2

PGEC2 17 26 L1 A20 I ST Clock input pin for Programming/

Debugging Communication Channel 2

MCLR 713F1

B7 I/P ST Master Clear (Reset) input. This pin is

an active-low Reset to the device.

AVDD 19 30 J4 A22 P P Positive supply for analog modules.

This pin must be connected at all times.

AVSS 20 31 L3 B18 P P Ground re ference for analog modules

VDD 10, 26, 38,

57 2, 16, 37,

46, 62, 86

A7, C2,

C9, E5,

K8, F8,

G5, H4,

A10, A14,

A30, A41,

A48, A59,

B1, B21,

B53

P—

Positive supply for periph eral logic and

I/O pins

VCAP 56 85 B7 B48 P — Capacitor for Internal Voltage Regulator

VSS 9, 25, 41 15, 36, 45,

65, 75

A8, B10,

D4, D5,

E7, F5,

F10, G6,

G7, H3

A3, A25,

A43, A63,

B8, B12,

B25, B41,

B46

P—

Ground reference for logic and I/O pins.

This pin must be connected at all times.

VREF+ 16 29 K3 B17 I Analog Analog voltage reference (high) input

VREF- 15 28 L2 A21 I Analog Analog voltage reference (low) input

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number(1) Pin

Type Buffer

Type Description

64-Pin

QFN/TQFP 100-Pin

TQFP 121-Pin

TFBGA 124-pin

VTLA

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.

2: See Section 24.0 “Ethernet Controller” for more information.

PIC32MX5XX/6XX/7XX

DS60001156H-page 44  2009-2013 Microchip Technology Inc.

NOTES:

 2009-2013 Microchip Technology Inc. DS60001156H-page 45

PIC32MX5XX/6XX/7XX

2.0 GUIDELINES FOR GETTING

STARTED WITH 32-BIT MCUS

2.1 Basic Connection Requirements

Getting started with the PIC32MX5XX/6XX/7XX family

of 32-bit Microcontrollers (MCUs) requi res attention to

a minimal set of device pin connections before pro-

ceeding with development. The following is a list of pin

names, which must always be connected:

• All VDD and VSS pins (see 2.2 “Decoupling

Capacitors”)

• All AVDD and AVSS pins even if the ADC module is

not used (see 2.2 “Decoupling Capacitors”)

•VCAP pin (see 2.3 “Capacitor on Internal Voltage

Regulator (VCAP)”)

•MCLR

pin (see 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see 2.5 “ ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator

source is used (see 2.8 “External Oscillator Pins”)

The following pin may be required, as well: VREF+/

VREF- pins used when external voltage reference for

ADC module is implemented.

2.2 Decoupling Capacitors

The use of decoupling capacitors on power supply

pins, such as VDD, VSS, AVDD and AVSS is required.

See Figure 2-1.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: A value of 0.1 µF

(100 nF), 10-20V is recommended. The capacitor

should be a low Equivalent Series Resistance

(low-ESR) capacitor and have resonance fre-

quency in the range of 20 MHz and higher. It is

further recommended to use ceramic capacitors.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended that

the capacitors be placed on the same side of

the board as the device. If space is constricted,

the capacitor can be placed on another layer on

the PCB using a via; however, ensure that the

trace length from the pin to the capacitor is

within one-quarter inch (6 mm) in length.

•Handling high freque nc y nois e : If the board is

experiencing high frequency noise, upward of

tens of MHz, add a second ceramic-type capacitor

in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 µF to 0.001 µF. Pl ace this

second capacitor next to the primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible.

For example, 0.1 µF in parallel with 0.001 µF.

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB track

inductance.

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve

power supply stability . T ypical values range from 4.7 µF

to 47 µ F. This capacitor should be located as close to

the device as possible.

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section of the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: The AVDD and AVSS pins must be

connected, regardless of the ADC use

and the ADC voltage reference source.

PIC32MX

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

VDD

MCLR

0.1 µF

Ceramic

VCAP

10

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

CEFC

VUSB3V3(1)

Note 1: If the USB module is used, th is pi n must be

connected to VDD.

PIC32MX5XX/6XX/7XX

DS60001156H-page 46  2009-2013 Microchip Technology Inc.

2.3 Capacitor on Internal Voltage

Regulator (VCAP)

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (1 ohm) capacitor is required on the VCAP

pin, which is used to stabilize the internal voltage regu-

lator output. The VCAP pin must not be connected to

VDD, and must have a CEFC capacitor, with at least a

6V rating, connected to ground. The type can be

ceramic or tantalum . Refer to Section 31.0 “Electrical

Characteristics” for additional information on CEFC

specifications.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions:

• Device Reset

• Device Programming and Debugging

Pulling The MCLR pin low generates a device Reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R and C will need to be adjusted based on the

application and PCB requirements.

For example, as illustrated in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Place the components illustrated in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging pur-

poses. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/deb ugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

Ensure that the “Commu nication C hann el Sele ct” (i.e.,

PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB® ICD 3 or MPLAB® REAL ICE™.

For more information on ICD 3 and REAL ICE connec-

tion requirements, refer to the following documents that

are available on the Microchip web site.

•“Using MPLAB® ICD 3” (poster) (DS50001765)

•“MPLAB® ICD 3 Design Advisory” (DS50001764)

•“MPLAB® REAL ICE™ In-Circuit Emulator User’s

Guide” (DS50001616)

•“Using MPLAB® REAL ICE™ Emulator” (poster)

(DS50001749)

2.6 JTAG

The TMS, TDO, TDI and TCK pins are used for testing

and debugging according to the Joint Test Action

Group (JT AG) st andard. It is recommended to keep the

trace length between the JTAG connector and the

JTAG pins on the device as short as possible. If the

JTAG connector is expected to experience an ESD

event, a series resistor is recommended, with the value

in the range of a few tens of Ohms, not to exceed 100

Ohms.

Pull-up resistors, series diodes and capacitors on the

TMS, TDO, TDI and TCK pins are not recommended

as they will interfere with the programmer/debugger

communications to the device. If such discrete compo-

nents are an application requirement, they should be

removed from the circuit during programming and

debugging. Alternatively, refer to the AC/DC character-

istics and timing requirements information in the

respective device F lash programming specification for

information on capacitive loading limits and pin input

voltage high (VIH) and input low (VIL) requirements.

Note 1: R 10 k is recommended. A suggested

starting value is 10 k. Ensure that the MCLR

pin VIH and VIL specifications are met.

2: R1  470 will limit any current flowing into

MCLR from the external capacitor C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

3: The capacitor can be sized to prevent uninten-

tional Resets from brief glitches or to extend

the device Reset period during the POR.

C(3)

R1(2)

R(1)

VDD

MCLR

PIC32

 2009-2013 Microchip Technology Inc. DS60001156H-page 47

PIC32MX5XX/6XX/7XX

2.7 Trace

The trace pins can be connecte d to a hardware-trace-

enabled programmer to provide a compress real time

instruction trace. When used for trace the TRD3,

TRD2, TRD1, TRD0 and TRCLK pins should be

dedicated for this use. The trace hardware requires

a22 series resistor between the trace pins and the

trace connector.

2.8 External Oscillator Pins

Many MCUs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator. Refer to Section 8 .0 “Oscillator

Configuration” for details.

The oscillat or circuit should be p laced on the same side

of the board as the device. Also, place the oscillator cir-

cuit close to the respective oscillator pins, not exceed-

ing one-half inch (12 mm) distance between them. The

load capacitors should be placed next to the oscillator

itself, on the same side of the board. Use a grounded

copper pour around the oscillator circuit to isolate them

from surrounding circuits. The grounded copper pour

should be routed directly to the MCU ground. Do not

run any signal traces or power traces inside the ground

pour . Also, if using a two-sided board, avoid any traces

on the other side of the board where the crystal is

placed. A suggested layout is illustrated in Figure 2-3.

FIGURE 2-3: SUGGESTED OSCILLATOR

CIRCUIT PLACEMENT

2.9 Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 3 or REAL ICE is selected as a

debugger, it automatically initializes all of the Analog-

to-Digital input pins (ANx) as “digital” pins by setting

all bits in the AD1PCFG register .

The bits in this register that correspond to the Analog-

to-Digital pins that are initialized by MPLAB ICD 3 or

REAL ICE, must not be cleared by the user application

firmware; otherwise, communication errors will result

between the debugger and the device.

If your application needs to use certain ADC pins as

analog input pins during the debug session, the user

application must clear the corresponding bits in the

AD1PCFG register during initialization of the ADC

module.

When MPLAB ICD 3 or REAL ICE is used as a pro-

grammer, the user application firmwa re must correctly

configure the AD1PCFG register. Automatic initializa-

tion of this register is only done during debugge r oper-

ation. Failure to correctly configure the register(s) will

result in all ADC pins being recognized as analog input

pins, resulting in the port value being read as a logic ‘0’,

which may affect user application functionality.

2.10 Unused I/Os

Unused I/O pins should not be allowed to float as

inputs. They can be configured as outputs and driven

to a logic-low state.

Alternatively, inputs can be reserved by connecting the

pin to VSS through a 1k to 10k resistor and configuring

the pin as an input.

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

PIC32MX5XX/6XX/7XX

DS60001156H-page 48  2009-2013 Microchip Technology Inc.

NOTES:

 2009-2013 Microchip Technology Inc. DS60001156H-page 49

PIC32MX5XX/6XX/7XX

3.0 CPU

The MIPS32® M4K® Processor core is the heart of the

PIC32MX5XX/6XX/7XX family processor. The CPU

fetches instructions, decodes each instruction, fetches

source operands, executes each instruction and writes

the results of instruction execution to the proper

destinations.

3.1 Features

• 5-stage pipeline

• 32-bit address and data paths

• MIPS32® Enhanced Architecture (Release 2)

- Multiply-accumulate and multiply-subtract

instructions

- Targeted multiply instruction

- Zero/On e d et ect instructions

-WAIT instruction

- Conditional move instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- GPR shadow regist ers to minimize latency

for interrupt handlers

- Bit field manipulation instructions

• MIPS16e® code compression

- 16-bit encoding of 32-bit instructions to

improve code density

- Special PC-relative instructions for efficient

loading of addresses and constants

-SAVE and RESTORE macro instructions for

setting up and tearing down stack frames

within subroutines

- Improved support for handling 8-bit and 16-bit

data types

• S i mp l e Fi xe d Mapping Translation (FMT)

mechanism

• Simple dual bus interface

- Independent 32-bit address and data busses

- Transactions can be aborted to improve

interrupt latency

• Autonomous multiply/divide unit

- Maximum issue rate of one 32x16 multiply

per clock

- Maximum issue rate of one 32x32 multiply

every other clock

- Early-in iterative divide. Mini mum 11 and

maximum 33 clock latency (dividend (rs) sign

extension-dependent)

• Po w er co nt ro l

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT

instruction)

- Extensive use of local gated clocks

• EJTAG debug and instruction trace

- Support for single stepping

- Virtual instruction and data address/value

- Breakpoints

- PC tracing with trace comp ression

FIGURE 3-1: MIPS® M4 K® P ROCESSOR CORE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 2. “CPU”

(DS60001113) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site (www.micro-

chip.com/PIC32). Resources for the

MIPS32® M4K® Processor Core are

available at http://www.mips.com.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

CPU MDU

Execution Core

(RF/ALU/Shift) FMT

TAP

EJTAG

Bus Interface

Power

Management

System

Co-processor

Off-chip Debug Interface

Bus Matrix

Dual Bus Interface

PIC32MX5XX/6XX/7XX

DS60001156H-page 50  2009-2013 Microchip Technology Inc.

3.2 Architecture Overview

The MIPS® M4K® processor core contains several

logic blocks working together in parallel, providing an

efficient high-performance computing engine. The

following blocks are included with the core:

• Execution Unit

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Internal Bus interfaces

• Power Management

• MIPS16e® Support

• Enhanced JTAG (EJTAG) Controller

3.2.1 EXECUTION UNIT

The MIPS® M4K® processor core execution unit imple-

ments a load/store architecture with single-cycle ALU

operations (logical, shift, add, subtract) and an autono-

mous multiply/divide unit. The core contains thirty-two

32-bit General Purpose Registers (GPRs) used for

integer operations and address calc ulation. One addi-

tional register file shadow set (containing thirty-two reg-

isters) is added to minimize context switching overhead

during interrupt/exception processi ng. The register file

consists of two read ports and one write port and is fully

bypassed to minimize operation latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction

address

• Logic for branch determination and branch target

address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when

executing instruction streams where data

producing instructions are followed closely by

consumers of their results

• Leading Zero/One detect unit for implementing

the CLZ and CLO instructions

• Arithme tic Logic Unit (ALU ) for performing bit-wise

logical operations

• S h i fter and store aligner

3.2.2 MULTIPLY /DIVIDE UNIT (MDU)

MIPS® M4K® processor core includes a Multiply/Divide

Unit (MDU) that contains a separate pipeline for multi-

ply and divide operations. This pipeline operates in par-

allel with the Integer Unit (IU) pipeline and does not stall

when the IU pipeline stalls. This allows MDU opera-

tions to be partially masked by system stalls and/or

other integer unit instructions.

The high-performance MDU consists of a 32x16 booth

recoded multiplier, result/accumulation registers (HI

and LO), a divide state machine, and the necessary

multiplexers and control logic. The first number shown

(‘32’ of 32x16) repres ents the rs operand. The second

number (‘16’ of 32x16) represents the rt operan d. The

PIC32 core only checks the value of the latter (rt)

operand to determine how many times the operation

must pass through the multiplier . The 16x16 and 32x16

operations pass through the multiplier once. A 32x32

operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16

multiply operation every clock cycle; 32x32 multiply

operations can be issued every other clock cycle.

Appropriate interlocks are implemented to stall the

issuance of back-to-back 32x32 multiply operations.

The multiply operand size is automa tically determined

by logic built into the MDU.

Divide operations are implemented with a simple 1 bit

per clock iterative algorithm. An early-in detection

checks the sign extension of the dividend (rs) operand.

If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit

wide rs, 15 iterations are skipped and for a 24 bit wide rs,

7 iterations are skipped. Any attempt to issue a

subsequent MDU instruction while a divide is still active

causes an IU pipeline stall until the divide operation is

completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be reissu ed) and late ncy (num-

ber of cycles until a result is available) for the PIC32

core multiply and divide instructions. The approximate

latency and repeat rates are listed in terms of pipeline

clocks.

TABLE 3-1: MIPS® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT

LATENCIES AND REPEAT RATES

Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU 16 bits 1 1

32 bits 2 2

MUL 16 bits 2 1

32 bits 3 2

DIV/DIVU 8 bits 12 11

16 bits 19 18

24 bits 26 25

32 bits 33 32

 2009-2013 Microchip Technology Inc. DS60001156H-page 51

PIC32MX5XX/6XX/7XX

The MIPS® architecture defines that the result of a

multiply or divide operation be placed in the HI and LO

registers. Using the Move-From-HI (MFHI) and Move-

From-LO (MFLO) instructions, these values can be

transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the

MIPS32® architecture also defines a multiply instruc-

tion, MUL, which places the least significant results in

the primary register file instead of the HI/LO register

pair. By avoiding the explicit MFLO instruction required

when using the LO register , and by supporting multiple

destination registers, the throughput of multiply-inten-

sive operations is increased.

Two other instructions, Multiply-Add (MADD) and

Multiply-Subtract (MSUB), are used to perform the

multiply-accumulate and multiply-subtract operations.

The MADD instruction multiplies two numb ers and then

adds the product to th e current contents of the HI and

LO registers. Similarly, the MSUB instruction multiplies

two operands and then subtracts the product from the

HI and LO registers. The MADD and MSUB operations

are commonly used in DSP algorithms.

3.2.3 SYSTEM CONTROL

COPROCESSOR (CP0)

In the MIPS® architecture, CP0 is responsible for the

virtual-to-physical address translation, the exception

control system, the processor ’s diagnostics capability,

the operating modes (Kernel, User and Debug) and

whether interrupts are enabled or disabled. Config ura-

tion information, such as presence of options like

MIPS16e®, is also available by accessing the CP0

registers, listed in Table 3-2.

TABLE 3-2: COPROCESSOR 0 REGISTERS

Number Register

Name Function

0-6 Reserved Reserved.

7 HWREna Enable s access via the RDHWR instruction to selected hardware registers.

8 BadVAddr(1) Reports the address for the most recent address-related exception.

9 Count(1) Processor cycle count.

10 Reserved Reserved.

11 Compare(1) Timer interrupt control.

12 Status(1) Processor status and control.

12 IntCtl(1) Interrupt system status and control.

12 SRSCtl(1) Shadow register set status and control.

12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set.

13 Cause(1) Cause of last general exception.

14 EPC(1) Program counter at last exception.

15 PRId Processor identification and revision.

15 Ebase Exception vector base register.

16 Config Configuration register.

16 Config1 Configuration Register 1.

16 Config2 Configuration Register 2.

16 Config3 Configuration Register 3.

17-22 Reserved Reserved.

23 Debug(2) Debug control and exceptio n status.

24 DEPC(2) Program counter at last debug exception.

25-29 Reserved Reserved.

30 ErrorEPC(1) Program counter at last error.

31 DESAVE(2) Debug handler scratchpad register.

Note 1: Registers used in exception processing.

2: Registers used during debug.

PIC32MX5XX/6XX/7XX

DS60001156H-page 52  2009-2013 Microchip Technology Inc.

Coprocessor 0 also contains the logic for identifying

and managing exceptions. Exceptions can be caused

by a variety of sources, including alignment errors in

data, external events or program errors. Table 3-3 lists

the exception types in order of priority.

TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES

Exception Description

Reset Assertion MCLR or a Power-on Reset (POR).

DSS EJTAG debug single step.

DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT inpu t or by setting the

EjtagBrk bit in the ECR register.

NMI Assertion of NMI signal.

Interrupt Assertion of unmasked hardware or software interrupt signal.

DIB EJTAG debug hardware instruction break matched.

AdEL Fetch address alignmen t error.

Fetch reference to protected address.

IBE Instruction fetch bus error.

DBp EJTAG breakpoint (execution of SDBBP instruction).

Sys Execution of SYSCALL instruction.

Bp Execution of BREAK instruction.

RI Execution of a reserved instruction.

CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.

CEU Executi on of a CorExtend instruction when CorExtend is not enabled.

Ov Execution of an arithmetic instruction that overflowed.

Tr Execution of a trap (when trap condition is true).

DDBL/DDBS E JTAG Data Address Break (address only) or EJTAG data value break on store (address + value).

AdEL Load address alignment error.

Load reference to protected address.

AdES Store address alignment error.

Store to protected address.

DBE Load or store bus error.

DDBL EJTAG data hardware breakpoin t matched in load data compare .

 2009-2013 Microchip Technology Inc. DS60001156H-page 53

PIC32MX5XX/6XX/7XX

3.3 Power Management

The MIPS® M4K® Processor core offers a number of

power management features, including low-power

design, active power management and power-down

modes of operation. The core is a static design that

supports slowing or halting the clocks, which reduces

system power consumption during idle pe rio ds.

3.3.1 INSTRUCTION-CONTROLLED

POWER MANAGEMENT

The mechanism for invoking Power-Down mode is

through execution of the WAIT instruction. For more

information on power management, see Section 27.0

“Power-Saving Features”.

3.3.2 LOCAL CLOCK GATING

The majority of the power consumed by the PIC32MX-

5XX/6XX/7XX family core is in the clock tree and clock-

ing registers. The PIC32 family uses extensive use of

local gated clocks to reduce this dynamic power con-

sumption.

3.4 EJTAG Debug Support

The MIPS® M4K® Processor core provides for an

Enhanced JTAG (EJTAG) interface for use in the

software debug of application and kernel code. In

addition to standard User mode and Kernel modes of

operation, the MIPS® M4K® core provides a Debug

mode that is entered after a debug exception (derived

from a hardware breakpoint, single-step exception,

etc.) is taken and continues until a Debug Exception

Return (DERET) instruction is executed. During this

time, the processor executes the debug exception

handler routine.

The EJT AG interface operates through the Test Access

Port (TAP), a serial communication port used for

transferring test data in and out of the MIPS® M4K®

processor core. In addition to the standard JTAG

instructions, special instructions defined in the EJTAG

specification define which registers are selected and

how they are used.

PIC32MX5XX/6XX/7XX

DS60001156H-page 54  2009-2013 Microchip Technology Inc.

NOTES:

 2009-2013 Microchip Technology Inc. DS60001156H-page 55

PIC32MX5XX/6XX/7XX

4.0 MEMORY ORGANIZATION

PIC32MX5XX/6XX/7XX microcontrollers provid e 4 GB

of unified virtual memory address space. All memory

regions, including program, data memory, SFRs and

Configuration registers, reside in this address space at

their respective unique addresses. The program and

data memories can be optionally partitioned into user

and kernel memories. In addition, the data memory can

be made executable, allowing PIC32MX5XX/6XX/7XX

devices to execute from data memory.

Key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel (KSEG0/

KSEG1) mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and

program space

• S e parate boot Flash me mo ry for protected code

• Robust bus exception handling to intercept

runaway code

• Simple memory mapping with Fixed Mapping

Transla tion (FMT) unit

• Cacheable (KSEG0) and non-cacheable (KSEG1)

address regions

4.1 Memory Layout

PIC32MX5XX/6XX/7XX microcontrollers implement

two address schemes: virtual and physical. All

hardware resources, such as program memory, data

memory and peripherals, are located at their respective

physical addresses. Virtual addresses are exclusively

used by the CPU to fetch and execute instructions as

well as access peripherals. Physical addresses are

used by bus master peripherals, such as DMA and the

Flash controller, th at access memory inde pendently of

the CPU.

The memory maps for the PIC32MX5XX/6XX/7XX

devices are illustrated in Figure 4-1 through Figure 4-6.

4.1.1 PERIPHERAL REGISTERS

LOCATIONS

Table 4-1 through Table 4-44 contain the peripheral

address maps for the PIC32MX5XX/6XX/7XX

devices.

Note: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. For

detailed information, refer to Section 3.

“Memory Organization” (DS60001115)

in the “PIC32 Family Reference Manual” ,

which is available from the Microchip

web site ( www.microchip.com/PIC32).

PIC32MX5XX/6XX/7XX

DS60001156H-page 56  2009-2013 Microchip Technology Inc.

FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L,

PIC32MX664F064H AND PIC32MX664F064L DEVICES

Virtual

Memory Map(1) Physical

Memory Map(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF Program Flash(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FF0

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF Program Flash(2) Reserved

0x9D000000 0x1D010000

Reserved Program Flash(2) 0x1D00FFFF

0x80008000

0x80007FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM(2) 0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115)) and can be changed by initialization code provided by end user

development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

 2009-2013 Microchip Technology Inc. DS60001156H-page 57

PIC32MX5XX/6XX/7XX

FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L

DEVICES

Virtual

Memory Map(1) Physical

Memory Map(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF Program Flash(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FF0

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF Program Flash(2) Reserved

0x9D000000 0x1D010000

Reserved Program Flash(2) 0x1D00FFFF

0x80004000

0x80003FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM(2) 0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115)) and can be changed by initialization code provided by end user

development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX5XX/6XX/7XX

DS60001156H-page 58  2009-2013 Microchip Technology Inc.

FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L,

PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND

PIC32MX764F128L DEVICES

Virtual

Memory Map(1) Physical

Memory Map(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF Program Flash(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FF0

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF Program Flash(2) Reserved

0x9D000000 0x1D020000

Reserved Program Flash(2) 0x1D01FFFF

0x80008000

0x80007FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM(2) 0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115)) and can be changed by initialization code provided by end user

development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

 2009-2013 Microchip Technology Inc. DS60001156H-page 59

PIC32MX5XX/6XX/7XX

FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,

PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND

PIC32MX775F256L DEVICES

Virtual

Memory Map(1) Physical

Memory Map(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD040000

0xBD03FFFF Program Flash(2)

0xBD000000

Reserved

0xA0010000

0xA000FFFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FF0

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D040000 0x1F800000

0x9D03FFFF Program Flash(2) Reserved

0x9D000000 0x1D040000

Reserved Program Flash(2) 0x1D03FFFF

0x80008000

0x80007FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00010000

Reserved RAM(2) 0x0000FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115)) and can be changed by initialization code provided by end user

development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX5XX/6XX/7XX

DS60001156H-page 60  2009-2013 Microchip Technology Inc.

FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,

PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND

PIC32MX775F512L DEVICES

Virtual

Memory Map(1) Physical

Memory Map(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF Program Flash(2)

0xBD000000

Reserved

0xA0010000

0xA000FFFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FF0

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF Program Flash(2) Reserved

0x9D000000 0x1D080000

Reserved Program Flash(2) 0x1D07FFFF

0x80010000

0x8000FFFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00010000

Reserved RAM(2) 0x0000FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115)) and can be changed by initialization code provided by end user

development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

 2009-2013 Microchip Technology Inc. DS60001156H-page 61

PIC32MX5XX/6XX/7XX

FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,

PIC32MX795F512H AND PIC32MX795F512L DEVICES

Virtual

Memory Map(1) Physical

Memory Map(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF Program Flash(2)

0xBD000000

Reserved

0xA0020000

0xA001FFFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FF0

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF Program Flash(2) Reserved

0x9D000000 0x1D080000

Reserved Program Flash(2) 0x1D07FFFF

0x80020000

0x8001FFFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00020000

Reserved RAM(2) 0x0001FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115)) and can be changed by initialization code provided by end user

development tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX5XX/6XX/7XX

DS60001156H-page 62  2009-2013 Microchip Technology Inc.

TABLE 4-1: BUS MATRIX REGISTER MAP

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2000 BMXCON(1) 31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0 — — — — — — — — —BMXWSDRM — — — BMXARB<2:0> 0041

2010 BMXDKPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDKPBA<15:0> 0000

2020 BMXDUDBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUDBA<15:0> 0000

2030 BMXDUPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUPBA<15:0> 0000

2040 BMXDRMSZ 31:16 BMXDRMSZ<31:0> xxxx

15:0 xxxx

2050 BMXPUPBA(1) 31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000

15:0 BMXPUPBA<15:0> 0000

2060 BMXPFMSZ 31:16 BMXPFMSZ<31:0> xxxx

15:0 xxxx

2070 BMXBOOTSZ 31:16 BMXBOOTSZ<31:0> 0000

15:0 3000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12. 1.1 “CLR, SET and INV Registers” f or more information.

 2009-2013 Microchip Technology Inc. DS60001156H-page 63

PIC32MX5XX/6XX/7XX

TABLE 4-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND

PIC32MX575F512H DEVICES

Virtual Address

(BF88_#)

Name(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1000 INTCON 31:16 — — — — — — — — — — — — — — — SS0 0000

15:0 — — — MVEC —TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

1010 INTSTAT(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — —SRIPL<2:0>—— VEC<5:0> 0000

1020 IPTMR 31:16 IPTMR<31:0> 0000

15:0 0000

1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF

I2C3MIF I2C3SIF I2C3BIF

15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000

1040 IFS1

31:16 IC3EIF IC2EIF IC1EIF —— CAN1IF USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000

RTCCIF FSCMIF — — — U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF

I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF

1050 IFS2 31:16

15:0 — — — — — — — — — — — — — — — — 0000

— — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE

I2C3MIE I2C3SIE I2C3BIE

15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000

1070 IEC1

31:16 IC3EIE IC2EIE IC1EIE —— CAN1IE USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000

RTCCIE FSCMIE — — — U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE

I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE

1080 IEC2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000

1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000

15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000

10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000

15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offset s of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET

and INV Registers” for more information.

2: These bits are not available on PIC32MX534/564/664/764 devices.

3: This register does not have associated CLR, SET, and INV registers.

PIC32MX5XX/6XX/7XX

DS60001156H-page 64  2009-2013 Microchip Technology Inc.

10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000

10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000

15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000

10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000

10E0 IPC5 31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000

15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000

10F0 IPC6

31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000

— — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0>

000015:0 SPI3IP<2:0> SPI3IS<1:0>

I2C3IP<2:0> I2C3IS<1:0>

1100 IPC7 — — — U3IP<2:0> U3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>

I2C4IP<2:0> I2C4IS<1:0>

15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000

1110 IPC8

31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000

— — — — — — — — — — — U2IP<2:0> U2IS<1:0>

000015:0 SPI4IP<2:0> SPI4IS<1:0>

I2C5IP<2:0> I2C5IS<1:0>

1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000

15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000

1130 IPC10 31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000

15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000

1140 IPC11 31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000

15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000

1150 IPC12 31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000

15:0 — — — U4IP<2:0> U4IS<1:0> — — — — — — — — 0000

TABLE 4-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND

PIC32MX575F512H DEVICES (CONTINUED)

Virtual Address

(BF88_#)

Name(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

and INV Registers” for more information.

2: These bits are not available on PIC32MX534/564/664/764 devices.

3: This register does not have associated CLR, SET, and INV registers.

 2009-2013 Microchip Technology Inc. DS60001156H-page 65

PIC32MX5XX/6XX/7XX

TABLE 4-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND

PIC32MX695F512H DEVICES

Virtual Address

(BF88_#)

Name(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1000 INTCON 31:16 ——————————————— SS0 0000

15:0 — — — MVEC —TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

1010 INTSTAT(3) 31:16 ————————————————0000

15:0 — — — — —SRIPL<2:0>—— VEC<5:0> 0000

1020 IPTMR 31:16 IPTMR<31:0> 0000

15:0 0000

1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF ——— OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF

I2C3MIF I2C3SIF I2C3BIF

15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000

1040 IFS1

31:16 IC3EIF IC2EIF IC1EIF ETHIF —— USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000

RTCCIF FSCMIF ———U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF

I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF

1050 IFS2 31:16 — — — — — — — — — — — — — — 0000

15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE ——— OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE

I2C3MIE I2C3SIE I2C3BIE

15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000

1070 IEC1

31:16 IC3EIE IC2EIE IC1EIE ETHIE —— USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000

RTCCIE FSCMIE ———U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE

I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE

1080 IEC2 31:16 ————————————————0000