PIC32MX5XX/6XX/7XX 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet Operating Conditions Timers/Output Compare/Input Capture * 2.3V to 3.6V, -40C to +105C, DC to 80 MHz (R) Core: 80 MHz/105 DMIPS MIPS32 M4K * Five General Purpose Timers: - Five 16-bit and up to two 32-bit Timers/Counters * Five Output Compare (OC) modules * Five Input Capture (IC) modules * Real-Time Clock and Calendar (RTCC) module (R) * MIPS16e(R) mode for up to 40% smaller code size * Code-efficient (C and Assembly) architecture * Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Communication Interfaces Clock Management * * * * * * USB 2.0-compliant Full-Speed OTG controller * 10/100 Mbps Ethernet MAC with MII and RMII interface * CAN module: - 2.0B Active with DeviceNetTM addressing support * Six UART modules (20 Mbps): - Supports LIN 1.2 protocols and IrDA(R) support * Up to four 4-wire SPI modules (25 Mbps) * Up to five I2C modules (up to 1 Mbaud) with SMBus support * Parallel Master Port (PMP) 0.9% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer Fast wake-up and start-up Power Management * * * * Low-power management modes (Sleep and Idle) Integrated Power-on Reset, Brown-out Reset 0.5 mA/MHz dynamic current (typical) 41 A IPD current (typical) Direct Memory Access (DMA) * Up to eight channels of hardware DMA with automatic data size detection * 32-bit Programmable Cyclic Redundancy Check (CRC) * Six additional channels dedicated to USB, Ethernet and CAN modules Graphics Features * External graphics interface with up to 34 Parallel Master Port (PMP) pins: - Interface to external graphics controller - Capable of driving LCD directly with DMA and internal or external memory Input/Output * 15 mA or 10 mA source/sink for standard VOH/VOL and up to 22 mA for non-standard VOH1 * 5V-tolerant pins * Selectable open drain and pull-ups * External interrupts Analog Features * ADC Module: - 10-bit 1 Msps rate with one Sample and Hold (S&H) - 16 analog inputs - Can operate during Sleep mode * Flexible and independent ADC trigger sources * Comparators: - Two dual-input Comparator modules - Programmable references with 32 voltage points Qualification and Class B Support * AEC-Q100 REVG (Grade 2 -40C to +105C) planned * Class B Safety Library, IEC 60730 Debugger Development Support * * * * In-circuit and in-application programming 4-wire MIPS(R) Enhanced JTAG interface Unlimited program and six complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Packages Type QFN TFBGA VTLA Pin Count 64 64 100 100 121 124 I/O Pins (up to) 51 51 83 83 83 83 Contact/Lead Pitch 0.50 0.50 0.40 0.50 0.80 0.50 Dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1 10x10x1.1 9x9x0.9 Note: TQFP All dimensions are in millimeters (mm) unless specified. 2009-2013 Microchip Technology Inc. DS60001156H-page 1 PIC32MX5XX/6XX/7XX TABLE 1: PIC32 USB AND CAN - FEATURES Program Memory (KB) Data Memory (KB) USB CAN Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2CTM(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) PIC32MX534F064H 64 64 + 12(1) 16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX575F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX575F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX534F064L 100 64 + 12(1) 16 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX564F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX564F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX575F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX575F512L 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG Device Pins USB and CAN Legend: Note 1: 2: 3: 4: 5: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5) This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the "Pin Diagrams" section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the "Pin Diagrams" section for more information. Refer to Section33.0 "Packaging Information" for more information. 100-pin devices in the VTLA package are available upon request. Please contact your local Microchip Sales Office for details. DS60001156H-page 2 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 2: PIC32 USB AND ETHERNET - FEATURES Program Memory (KB) Data Memory (KB) USB Ethernet Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2CTM(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) PIC32MX664F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX664F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX675F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX675F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX695F512H 64 512 + 12(1) 128 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX664F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX664F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX675F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX675F512L 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG, TL PIC32MX695F512L 100 512 + 12(1) 128 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT, PF, BG, TL Device Pins USB and Ethernet Legend: Note 1: 2: 3: 4: 5: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5) This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the "Pin Diagrams" section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the "Pin Diagrams" section for more information. Refer to Section33.0 "Packaging Information" for more information. 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local Microchip Sales Office for details. 2009-2013 Microchip Technology Inc. DS60001156H-page 3 PIC32MX5XX/6XX/7XX TABLE 3: PIC32 USB, ETHERNET AND CAN - FEATURES Pins Program Memory (KB) Data Memory (KB) USB Ethernet CAN Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2CTM(3) 10-bit 1 Msps ADC (Channels) Comparators JTAG Trace Packages(4) PIC32MX764F128H 64 128 + 12(1) 32 1 1 1 5/5/5 4/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F512H 64 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX795F512H 64 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX764F128L 100 128 + 12(1) 32 1 1 1 5/5/5 4/6 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX775F256L 100 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX775F512L 100 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF, BG PIC32MX795F512L 100 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF, BG, TL Legend: Note 1: 2: 3: 4: 5: PMP/PSP Device USB, Ethernet and CAN PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5) This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the "Pin Diagrams" section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the "Pin Diagrams" section for more information. Refer to Section 33.0 "Packaging Information" for more information. 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local Microchip Sales Office for details. DS60001156H-page 4 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams 64-Pin QFN(1) PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX575F256H PIC32MX575F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2009-2013 Microchip Technology Inc. DS60001156H-page 5 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PIC32MX664F064H 42 41 PIC32MX664F128H 40 PIC32MX675F256H 39 PIC32MX675F512H 38 PIC32MX695F512H 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS60001156H-page 6 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX775F256H 8 40 PIC32MX775F512H 9 39 PIC32MX795F512H 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLKPMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2009-2013 Microchip Technology Inc. DS60001156H-page 7 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX764F128H 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLKPMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS60001156H-page 8 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX575F256H PIC32MX575F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2009-2013 Microchip Technology Inc. DS60001156H-page 9 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 PIC32MX664F064H 7 PIC32MX664F128H 8 PIC32MX675F256H 9 PIC32MX675F512H 10 PIC32MX695F512H 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS60001156H-page 10 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 PIC32MX775F256H 9 PIC32MX775F512H 10 PIC32MX795F512H 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant 2009-2013 Microchip Technology Inc. DS60001156H-page 11 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 PIC32MX764F128H 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RXU1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant DS60001156H-page 12 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F512L PIC32MX575F256L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB3V3 VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD SS3/U4RX/U1CTS/CN20/RD14 SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 C1TX/PMD10/RF1 C1RX/PMD11/RF0 VDD VCAP PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP 2009-2013 Microchip Technology Inc. DS60001156H-page 13 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 = Pins are up to 5V tolerant 2009-2013 Microchip Technology Inc. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 SCK4/U5TX/U2RTS/RF13 SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS3/U4RX/U1CTS/CN20/RD14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100-Pin TQFP VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB3V3 VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 PIC32MX5XX/6XX/7XX DS60001156H-page 14 Pin Diagrams (Continued) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DS60001156H-page 15 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS3/U4RX/U1CTS/CN20/RD14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 = Pins are up to 5V tolerant VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD1 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB3V3 VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 PIC32MX5XX/6XX/7XX AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 C2RX/PMD8/RG0 C2TX/ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 2009-2013 Microchip Technology Inc. Pin Diagrams (Continued) PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX764F128L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 = Pins are up to 5V tolerant PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS3/U4RX/U1CTS/CN20/RD14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 2009-2013 Microchip Technology Inc. AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100-Pin TQFP VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD1 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB3V3 VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 PIC32MX5XX/6XX/7XX DS60001156H-page 16 Pin Diagrams (Continued) PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 121-Pin TFBGA(1) = Pins are up to 5V tolerant PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 RB5 RB4 VSS VDD NC VDD NC VBUS VUSB3V3 RG2 RA2 RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 A B C D E F G H J K L Note 1: Refer to Table 4, Table 5 and Table 6 for full pin names. 2009-2013 Microchip Technology Inc. DS60001156H-page 17 PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 C1TX/PMD10/RF1 F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8 A7 VDD F3 SS2/U6RX/U3CTS/PMA2/CN11/RG9 A8 VSS F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 VDD B2 RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 INT1/RE8 B6 C1RX/PMD11/RF0 G2 INT2/RE9 B7 VCAP G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 C5 TRCLK/RA6 H1 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB3V3 D3 PMD5/RE5 H10 D+/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 PMD13/CN19/RD13 J4 AVDD D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12 E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8 E4 T3CK/RC2 J11 D-/RG3 PGEC1/AN1/CN3/RB1 E5 VDD K1 E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/PMA6/RA10 DS60001156H-page 18 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 SS3/U4RX/U1CTS/CN20/RD14 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/PMA7/RA9 2009-2013 Microchip Technology Inc. DS60001156H-page 19 PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 A2 PMD3/RE3 E9 AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 ETXD2/IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 VDD B2 AERXERR/RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 AERXD0/INT1/RE8 B6 ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9 B7 VCAP G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 ETXCLK/PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB3V3 D3 PMD5/RE5 H10 D+/RG2 SCL2/RA2 D4 VSS H11 D5 VSS J1 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7 AN3/C2IN+/CN5/RB3 D8 ETXD3/PMD13/CN19/RD13 J4 AVDD D9 SDO1/OC1/INT0/RD0 J5 AN11/ERXERR/AETXERR/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12 E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8 E4 T3CK/RC2 J11 D-/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10 DS60001156H-page 20 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 K10 USBID/RF3 L9 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/AERXD2/PMA7/RA9 2009-2013 Microchip Technology Inc. DS60001156H-page 21 PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 C2RX/PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 ETXD2/IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 VDD B2 AERXERR/RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 AERXD0/INT1/RE8 B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9 B7 VCAP G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) TDO/RA5 C2 VDD G9 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 ETXCLK/PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB3V3 D3 PMD5/RE5 H10 D+/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 ETXD3/PMD13/CN19/RD13 J4 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 D9 SDO1/OC1/INT0/RD0 J5 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12 E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/AC2RX/RC3 J9 No Connect (NC) E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8 E4 T3CK/AC2TX/RC2 J11 D-/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 C2TX/ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10 DS60001156H-page 22 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 K5 No Connect (NC) L4 AVSS AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 K10 USBID/RF3 L9 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/AERXD2/PMA7/RA9 2009-2013 Microchip Technology Inc. DS60001156H-page 23 PIC32MX5XX/6XX/7XX TABLE 7: PIN NAME: PIC32MX764F128L DEVICE Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 ETXD2/IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 VDD B2 AERXERR/RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 AERXD0/INT1/RE8 B6 C1RX/ETXD1/PMD11/RF0 G2 AERXD1/INT2/RE9 B7 VCAP G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) TDO/RA5 C2 VDD G9 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 ETXCLK/PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB3V3 D3 PMD5/RE5 H10 D+/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 ETXEN/PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 ETXD3/PMD13/CN19/RD13 J4 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 D9 SDO1/OC1/INT0/RD0 J5 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/ERXD0/AECRS/PMA11/RB12 E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 J10 SCL3/SDO3/U1TX/RF8 E4 T3CK/RC2 J11 D-/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 ETXERR/PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/AERXD3/PMA6/RA10 DS60001156H-page 24 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 7: PIN NAME: PIC32MX764F128L DEVICE (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 K11 SDA3/SDI3/U1RX/RF2 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/AERXD2/PMA7/RA9 2009-2013 Microchip Technology Inc. DS60001156H-page 25 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 124-Pin VTLA(1) A68 A67 A1 = Pins are up to 5V tolerant A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50 A2 B1 A49 A3 B2 B41 A48 A4 B3 B40 A47 A5 B4 B39 A46 A6 B5 B38 A45 A7 B6 B37 A44 A8 B7 B36 A43 A9 B8 B35 A42 A10 B9 B34 A41 A11 B10 B33 A40 A12 B11 B32 A39 A13 B12 B31 A38 A14 B13 B30 A37 B29 A36 PIC32MX675F512L PIC32MX695F512L PIC32MX795F512L A15 A16 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 Note 1: A35 A33 A34 Refer to Table 8 for the full list of pin names. DS60001156H-page 26 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES Package Bump # Full Pin Name Package Bump # Full Pin Name A1 No Connect (NC) A52 OC2/RD1 A2 AERXERR/RG15 A53 OC4/RD3 A3 VSS A54 ETXD3/PMD13/CN19/RD13 A4 PMD6/RE6 A55 PMRD/CN14/RD5 A5 T2CK/RC1 A56 ETXCLK/PMD15/CN16/RD7 A6 T4CK/AC2RX(1)/RC3 A57 No Connect (NC) A7 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 A58 No Connect (NC) A8 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A59 VDD A9 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 A60 C1TX(1)/ETXD0/PMD10/RF1 A10 VDD A61 C2RX(1)/PMD8/RG0 TRD3/RA7 A11 AERXD0/INT1/RE8 A62 A12 AN5/C1IN+/VBUSON/CN7/RB5 A63 VSS A13 AN3/C2IN+/CN5/RB3 A64 PMD1/RE1 A14 VDD A65 TRD1/RG12 A15 PGEC1/AN1/CN3/RB1 A66 PMD2/RE2 A16 No Connect (NC) A67 PMD4/RE4 A17 No Connect (NC) A68 No Connect (NC) A18 No Connect (NC) B1 VDD A19 No Connect (NC) B2 PMD5/RE5 A20 PGEC2/AN6/OCFA/RB6 B3 PMD7/RE7 A21 VREF-/CVREF-/AERXD2/PMA7/RA9 B4 T3CK/AC2TX/RC2 A22 AVDD B5 T5CK/SDI1/RC4 A23 AN8/C1OUT/RB8 B6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 A24 AN10/CVREFOUT/PMA13/RB10 B7 MCLR A25 VSS B8 VSS A26 TCK/RA1 B9 TMS/RA0 A27 AC1RX(1)/SS4/U5RX/U2CTS/RF12 B10 AERXD1/INT2/RE9 A28 AN13/ERXD1/AECOL/PMA10/RB13 B11 AN4/C1IN-/CN6/RB4 A29 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 B12 VSS A30 VDD B13 AN2/C2IN-/CN4/RB2 A31 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 B14 PGED1/AN0/CN2/RB0 A32 SCL5/SDO4/U2TX/PMA8/CN18/RF5 B15 No Connect (NC) A33 No Connect (NC) B16 PGED2/AN7/RB7 A34 No Connect (NC) B17 VREF+/CVREF+/AERXD3/PMA6/RA10 A35 USBID/RF3 B18 AVSS A36 SDA3/SDI3/U1RX/RF2 B19 AN9/C2OUT/RB9 A37 VBUS B20 AN11/ERXERR/AETXERR/PMA12/RB11 A38 D-/RG3 B21 VDD A39 SCL2/RA2 B22 AC1TX(1)/SCK4/U5TX/U2RTS/RF13 A40 TDI/RA4 B23 AN12/ERXD0/AECRS/PMA11/RB12 A41 VDD B24 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 A42 OSC2/CLKO/RC15 B25 VSS A43 VSS B26 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 A44 AETXEN/SDA1/INT4/RA15 B27 SDA5/SDI4/U2RX/PMA9/CN17/RF4 A45 SS1/IC2/RD9 B28 No Connect (NC) A46 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 B29 SCL3/SDO3/U1TX/RF8 A47 SOSCI/CN1/RC13 B30 VUSB3V3 A48 VDD B31 D+/RG2 A49 No Connect (NC) B32 SDA2/RA3 A50 No Connect (NC) B33 TDO/RA5 A51 No Connect (NC) B34 OSC1/CLKI/RC12 Note 1: This pin is only available on PIC32MX795F512L devices. 2009-2013 Microchip Technology Inc. DS60001156H-page 27 PIC32MX5XX/6XX/7XX TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES Package Bump # Full Pin Name Package Bump # Full Pin Name B35 No Connect (NC) B46 VSS B36 AETXCLK/SCL1/INT3/RA14 B47 No Connect (NC) B37 RTCC/EMDIO/AEMDIO/IC1/RD8 B48 VCAP B38 SCK1/IC3/PMCS2/PMA15/RD10 B49 C1RX/ETXD1/PMD11/RF0 B39 SDO1/OC1/INT0/RD0 B50 C2TX/ETXERR/PMD9/RG1 B40 SOSCO/T1CK/CN0/RC14 B51 TRCLK/RA6 B41 VSS B52 PMD0/RE0 B42 OC3/RD2 B53 VDD B43 ETXD2/IC5/PMD12/RD12 B54 TRD2/RG14 B44 OC5/PMWR/CN13/RD4 B55 TRD0/RG13 ETXEN/PMD14/CN15/RD6 B56 PMD3/RE3 B45 Note 1: This pin is only available on PIC32MX795F512L devices. DS60001156H-page 28 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 33 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 45 3.0 CPU............................................................................................................................................................................................ 49 4.0 Memory Organization ................................................................................................................................................................. 55 5.0 Flash Program Memory............................................................................................................................................................ 123 6.0 Resets ...................................................................................................................................................................................... 127 7.0 Interrupt Controller ................................................................................................................................................................... 131 8.0 Oscillator Configuration ............................................................................................................................................................ 141 9.0 Prefetch Cache......................................................................................................................................................................... 147 10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 157 11.0 USB On-The-Go (OTG)............................................................................................................................................................ 173 12.0 I/O Ports ................................................................................................................................................................................... 193 13.0 Timer1 ...................................................................................................................................................................................... 197 14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 201 15.0 Input Capture............................................................................................................................................................................ 205 16.0 Output Compare....................................................................................................................................................................... 209 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 211 18.0 Inter-Integrated CircuitTM (I2CTM).............................................................................................................................................. 217 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 223 20.0 Parallel Master Port (PMP)....................................................................................................................................................... 229 21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 237 22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 247 23.0 Controller Area Network (CAN) ................................................................................................................................................ 255 24.0 Ethernet Controller ................................................................................................................................................................... 289 25.0 Comparator .............................................................................................................................................................................. 331 26.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 335 27.0 Power-Saving Features ........................................................................................................................................................... 337 28.0 Special Features ...................................................................................................................................................................... 339 29.0 Instruction Set .......................................................................................................................................................................... 353 30.0 Development Support............................................................................................................................................................... 355 31.0 Electrical Characteristics .......................................................................................................................................................... 359 32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 407 33.0 Packaging Information.............................................................................................................................................................. 409 The Microchip Web Site ..................................................................................................................................................................... 443 Customer Change Notification Service .............................................................................................................................................. 443 Customer Support .............................................................................................................................................................................. 443 Reader Response .............................................................................................................................................................................. 444 Product Identification System ............................................................................................................................................................ 445 2009-2013 Microchip Technology Inc. DS60001156H-page 29 PIC32MX5XX/6XX/7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS60001156H-page 30 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Referenced Sources This device data sheet is based on the following individual chapters of the "PIC32 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX795F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. * * * * * * * * * * * * * * * * * * * * * * * * * * * * Section 1. "Introduction" (DS60001127) Section 2. "CPU" (DS60001113) Section 4. "Prefetch Cache" (DS60001119) Section 3. "Memory Organization" (DS60001115) Section 5. "Flash Program Memory" (DS60001121) Section 6. "Oscillator Configuration" (DS60001112) Section 7. "Resets" (DS60001118) Section 8. "Interrupt Controller" (DS60001108) Section 9. "Watchdog Timer and Power-up Timer (DS60001114) Section 10. "Power-Saving Features" (DS60001130) Section 12. "I/O Ports" (DS60001120) Section 13. "Parallel Master Port (PMP)" (DS60001128) Section 14. "Timers" (DS60001105) Section 15. "Input Capture" (DS60001122) Section 16. "Output Capture" (DS60001111) Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) Section 19. "Comparator" (DS60001110) Section 20. "Comparator Voltage Reference (CVREF)" (DS60001109) Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107) Section 23. "Serial Peripheral Interface (SPI)" (DS60001106) Section 24. "Inter-Integrated Circuit (I2CTM)" (DS60001116) Section 27. "USB On-The-Go (OTG)" (DS60001126) Section 29. "Real-Time Clock and Calendar (RTCC)" (DS60001125) Section 31. "Direct Memory Access (DMA) Controller" (DS60001117) Section 32. "Configuration" (DS60001124) Section 33. "Programming and Diagnostics" (DS60001129) Section 34. "Controller Area Network (CAN)" (DS60001154) Section 35. "Ethernet Controller" (DS60001155) 2009-2013 Microchip Technology Inc. DS60001156H-page 31 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 32 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX5XX/6XX/ 7XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. BLOCK DIAGRAM(1,2) FIGURE 1-1: VCAP OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators Power-up Timer FRC/LPRC Oscillators Oscillator Start-up Timer Voltage Regulator PLL PLL-USB Watchdog Timer USBCLK SYSCLK PBCLK Timing Generation MCLR Power-on Reset Precision Band Gap Reference Dividers VDD, VSS Brown-out Reset Peripheral Bus Clocked by SYSCLK CN1-22 PORTA 32 CPU Core PORTC IS 32 DS 32 32 32 32 32 32 32 PORTD Bus Matrix 32 32 IC1-5 SPI1-4 I2C1-5 32 PORTE Prefetch Module PWM OC1-5 Peripheral Bus Clocked by PBCLK MIPS32 M4K(R) ICD INT (R) DMAC EJTAG USB PORTB ETHERNET Timer1-5 Priority Interrupt Controller CAN1, CAN2 JTAG BSCAN 32 Data RAM Peripheral Bridge PMP 10-bit ADC PORTF PORTG 128-bit Wide Program Flash Memory Flash Controller 128 UART1-6 RTCC Comparators Note 1: 2: Some features are not available on all devices. BOR functionality is provided when the on-board voltage regulator is enabled. 2009-2013 Microchip Technology Inc. DS60001156H-page 33 PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Name Pin Type Buffer Type Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA AN0 16 25 K2 B14 I Analog Analog input channels AN1 15 24 K1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 23 22 21 20 26 27 32 33 34 35 41 42 43 44 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 A15 B13 A13 B11 A12 A20 B16 A23 B19 A24 B20 B23 A28 B24 A29 I I I I I I I I I I I I I I I CLKI 39 63 F9 B34 I CLKO 40 64 F11 A42 O Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog ST/ External clock source input. Always CMOS associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator -- mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 39 63 F9 B34 OSC2 40 64 F11 A42 SOSCI 47 73 C10 A47 SOSCO 48 74 B11 B40 Oscillator crystal input. ST buffer when ST/ configured in RC mode; CMOS CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator I/O -- mode. Optionally functions as CLKO in RC and EC modes. ST/ 32.768 kHz low-power oscillator crystal I CMOS input; CMOS otherwise 32.768 kHz low-power oscillator crystal O -- output Analog = Analog input P = Power O = Output I = Input I Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. DS60001156H-page 34 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2 INT3 INT4 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 -- -- -- 42 43 44 45 52 17 46 49 50 51 52 30 46 42 43 44 45 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70 71 79 26 72 76 77 78 81 44 72 18 19 66 67 B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 E9 E10 D11 C11 A9 L1 D9 A11 A10 B9 C8 L8 D9 G1 G2 E11 E8 B40 A47 B14 A15 B13 A13 B11 A12 A7 B6 A8 A9 A29 B44 A55 B45 A56 B27 A32 A54 B26 A31 B37 A45 B38 A46 A60 A20 B39 A52 B42 A53 B44 A29 B39 A11 B10 B36 A44 Pin Type Buffer Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O I I I I I I ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- -- -- -- -- ST ST ST ST ST ST Description Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture Inputs 1-5 Output Compare Fault A Input Output Compare Output 1 Output Compare Output 2 Output Compare Output 3 Output Compare Output 4 Output Compare Output 5 Output Compare Fault B Input External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. 2009-2013 Microchip Technology Inc. DS60001156H-page 35 PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA -- -- -- -- -- -- -- -- -- -- -- -- 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 G3 J6 H11 G10 G11 G9 C5 B5 L2 K3 E11 E8 K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 D1 E4 E2 E1 F9 C10 B11 F11 B9 A26 A39 B32 A40 B33 B51 A62 A21 B17 B36 A44 B14 A15 B13 A13 B11 A12 A20 B16 A23 B19 A24 B20 B23 A28 B24 A29 A5 B4 A6 B5 B34 A47 B40 A42 Pin Type Buffer Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST Description PORTA is a bidirectional I/O port PORTB is a bidirectional I/O port PORTC is a bidirectional I/O port Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. DS60001156H-page 36 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF8 RF12 RF13 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 58 59 -- 33 31 32 -- -- -- 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 53 40 39 D9 A11 A10 B9 C8 B8 D7 C7 E9 E10 D11 C11 A9 D8 L9 K9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 B6 A6 K11 K10 L10 L11 J10 K6 L6 B39 A52 B42 A53 B44 A55 B45 A56 B37 A45 B38 A46 B43 A54 B26 A31 B52 A64 A66 B56 A67 B2 A4 B3 A11 B10 B49 A60 A36 A35 B27 A32 B29 A27 B22 Pin Type Buffer Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST Description PORTD is a bidirectional I/O port PORTE is a bidirectional I/O port PORTF is a bidirectional I/O port Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. 2009-2013 Microchip Technology Inc. DS60001156H-page 37 PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTG is a bidirectional I/O port B50 A7 B6 A8 A9 A65 B55 B54 A2 B31 A38 B40 A5 B4 A6 B5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I B26 I ST UART1 clear to send 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA RG0 RG1 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RG2 RG3 T1CK T2CK T3CK T4CK T5CK -- -- 4 5 6 8 -- -- -- -- 37 36 48 -- -- -- -- 90 89 10 11 12 14 96 97 95 1 57 56 74 6 7 8 9 A5 E6 E3 F4 F2 F3 C3 A3 C4 B2 H10 J11 B11 D1 E4 E2 E1 A61 U1CTS 43 47 L9 Description PORTG input pins Timer1 external clock input Timer2 external clock input Timer3 external clock input Timer4 external clock input Timer5 external clock input U1RTS 49 48 K9 A31 O -- UART1 ready to send U1RX 50 52 K11 A36 I ST UART1 receive U1TX 51 53 J10 B29 O -- UART1 transmit U3CTS 8 14 F3 A9 I ST UART3 clear to send U3RTS 4 10 E3 A7 O -- UART3 ready to send U3RX 5 11 F4 B6 I ST UART3 receive U3TX 6 12 F2 A8 O -- UART3 transmit U2CTS 21 40 K6 A27 I ST UART2 clear to send U2RTS 29 39 L6 B22 O -- UART2 ready to send U2RX 31 49 L10 B27 I ST UART2 receive U2TX 32 50 L11 A32 O -- UART2 transmit U4RX 43 47 L9 B26 I ST UART4 receive U4TX 49 48 K9 A31 O -- UART4 transmit U6RX 8 14 F3 A9 I ST UART6 receive U6TX 4 10 E3 A7 O -- UART6 transmit U5RX 21 40 K6 A27 I ST UART5 receive U5TX 29 39 L6 B22 O -- SCK1 -- 70 D11 B38 I/O ST SDI1 -- 9 E1 B5 I ST UART5 transmit Synchronous serial clock input/output for SPI1 SPI1 data in Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. DS60001156H-page 38 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B39 O -- E10 A45 I/O ST 48 K9 A31 I/O ST 50 51 52 53 K11 J10 A36 B29 I O ST -- SS3 43 47 L9 B26 I/O ST SCK2 4 10 E3 A7 I/O ST SDI2 SDO2 5 6 11 12 F4 F2 B6 A8 I O ST -- SS2 8 14 F3 A9 I/O ST SCK4 29 39 L6 B22 I/O ST SDI4 SDO4 31 32 49 50 L10 L11 B27 A32 I O ST -- SS4 21 40 K6 A27 I/O SCL1 44 66 E11 B36 SDA1 43 67 E8 A44 SCL3 51 53 J10 B29 SDA3 50 52 K11 A36 SCL2 -- 58 H11 A39 SDA2 -- 59 G10 B32 SCL4 6 12 F2 A8 SDA4 5 11 F4 B6 SCL5 32 50 L11 A32 SDA5 31 49 L10 B27 Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA SDO1 -- 72 D9 SS1 -- 69 SCK3 49 SDI3 SDO3 Description SPI1 data out SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI3 SPI3 data in SPI3 data out SPI3 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out SPI2 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI4 SPI4 data in SPI4 data out SPI4 slave synchronization or frame pulse I/O Synchronous serial clock input/output I/O ST for I2C1 Synchronous serial data input/output I/O ST for I2C1 Synchronous serial clock input/output I/O ST for I2C3 Synchronous serial data input/output I/O ST for I2C3 Synchronous serial clock input/output I/O ST for I2C2 Synchronous serial data input/output I/O ST for I2C2 Synchronous serial clock input/output I/O ST for I2C4 Synchronous serial data input/output I/O ST for I2C4 Synchronous serial clock input/output I/O ST for I2C5 Synchronous serial data input/output I/O ST for I2C5 Analog = Analog input P = Power O = Output I = Input ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. 2009-2013 Microchip Technology Inc. DS60001156H-page 39 PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B9 A26 A40 B33 B37 I I I O O ST ST ST -- -- A21 B17 A24 B11 A12 A23 B13 A13 B19 I I O I I O I I O Analog Analog Analog Analog Analog -- Analog Analog -- L8 A29 I/O 43 K7 B24 I/O 8 6 5 4 16 22 32 31 28 27 24 23 45 44 14 12 11 10 29 28 50 49 42 41 35 34 71 70 F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 A9 A8 B6 A7 B17 A21 A32 B27 A28 B23 B20 A24 A46 B38 O O O O O O O O O O O O O O PMCS1 45 71 C11 A46 O PMCS2 44 70 D11 B38 O Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA TMS TCK TDI TDO RTCC 23 27 28 24 42 17 38 60 61 68 G3 J6 G11 G9 E9 CVREFCVREF+ CVREFOUT C1INC1IN+ C1OUT C2INC2IN+ C2OUT 15 16 23 12 11 21 14 13 22 28 29 34 21 20 32 23 22 33 L2 K3 L5 H2 H1 K4 J2 J1 L4 PMA0 30 44 PMA1 29 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 Description JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin Real-Time Clock alarm output Comparator Voltage Reference (low) Comparator Voltage Reference (high) Comparator Voltage Reference output Comparator 1 negative input Comparator 1 positive input Comparator 1 output Comparator 2 negative input Comparator 2 positive input Comparator 2 output Parallel Master Port Address bit 0 input TTL/ST (Buffered Slave modes) and output (Master modes) Parallel Master Port Address bit 1 input TTL/ST (Buffered Slave modes) and output (Master modes) -- Parallel Master Port address (Demultiplexed Master modes) -- -- -- -- -- -- -- -- -- -- -- -- -- Parallel Master Port Chip Select 1 -- strobe Parallel Master Port Chip Select 2 -- strobe Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. DS60001156H-page 40 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A64 A66 B56 A67 B2 A4 B3 A61 B50 A60 B49 B43 A54 B45 A56 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST L8 A29 O 43 K7 B24 O 53 52 34 82 81 54 B8 C8 H8 A55 B44 A37 O O I VUSB3V3 35 55 H9 B30 P VBUSON 11 20 H1 A12 O D+ DUSBID C1RX C1TX AC1RX AC1TX C2RX C2TX AC2RX AC2TX 37 36 33 58 59 32 31 29 21 -- -- 57 56 51 87 88 40 39 90 89 8 7 H10 J11 K10 B6 A6 K6 L6 A5 E6 E2 E4 B31 A38 A35 B49 A60 A27 B22 A61 B50 A6 B4 I/O I/O I I O I O I O 1 O Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 60 61 62 63 64 1 2 3 -- -- -- -- -- -- -- -- 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 A4 B4 B3 A2 A1 D3 C1 D2 A5 E6 A6 B6 A9 D8 D7 C7 B52 PMALL 30 44 PMALH 29 PMRD PMWR VBUS Description Parallel Master Port data (Demultiplexed Master mode) or address/data (Multiplexed Master modes) Parallel Master Port address latch enable low byte (Multiplexed Master modes) Parallel Master Port address latch -- enable high byte (Multiplexed Master modes) -- Parallel Master Port read strobe -- Parallel Master Port write strobe Analog USB bus power monitor USB internal transceiver supply. If the -- USB module is not used, this pin must be connected to VDD. -- USB Host and OTG bus power control output Analog USB D+ Analog USB DST USB OTG ID detect ST CAN1 bus receive pin -- CAN1 bus transmit pin ST Alternate CAN1 bus receive pin -- Alternate CAN1 bus transmit pin ST CAN2 bus receive pin -- CAN2 bus transmit pin ST Alternate CAN2 bus receive pin -- Alternate CAN2 bus transmit pin -- Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. 2009-2013 Microchip Technology Inc. DS60001156H-page 41 PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B23 A28 B24 I I I ST ST ST Ethernet Receive Data 0(2) Ethernet Receive Data 1(2) Ethernet Receive Data 2(2) A29 B20 A8 A8 A9 A9 I I I I I I ST ST ST ST ST ST Ethernet Receive Data 3(2) Ethernet receive error input(2) Ethernet receive data valid(2) Ethernet carrier sense data valid(2) Ethernet receive clock(2) Ethernet reference clock(2) A6 B6 A9 D8 A60 B49 B43 A54 O O O O -- -- -- -- Ethernet Transmit Data 0(2) Ethernet Transmit Data 1(2) Ethernet Transmit Data 2(2) Ethernet Transmit Data 3(2) 89 83 84 10 11 71 68 18 19 28 29 1 12 E6 D7 C7 E3 F4 C11 E9 G1 G2 L2 K3 B2 F2 B50 B45 A56 A7 B6 A46 B37 A11 B10 A21 B17 A2 A8 O O I I I O I/O I I I I I I -- -- ST ST ST -- -- ST ST ST ST ST ST Ethernet transmit error(2) Ethernet transmit enable(2) Ethernet transmit clock(2) Ethernet collision detect(2) Ethernet carrier sense(2) Ethernet management data clock(2) Ethernet management data(2) Alternate Ethernet Receive Data 0(2) Alternate Ethernet Receive Data 1(2) Alternate Ethernet Receive Data 2(2) Alternate Ethernet Receive Data 3(2) Alternate Ethernet receive error input(2) Alternate Ethernet receive data valid(2) 44 12 F2 A8 I ST AERXCLK -- 14 F3 A9 I ST Alternate Ethernet carrier sense data valid(2) Alternate Ethernet receive clock(2) AEREFCLK AETXD0 AETXD1 AETXD2 AETXD3 AETXERR AETXEN AETXCLK AECOL AECRS 45 59 58 -- -- -- 54 -- -- -- 14 47 48 44 43 35 67 66 42 41 F3 L9 K9 L8 K7 J5 E8 E11 L7 J7 A9 B26 A31 A29 B24 B20 A44 B36 A28 B23 I O O O O O O I I I ST -- -- -- -- -- -- ST ST ST Alternate Ethernet reference clock(2) Alternate Ethernet Transmit Data 0(2) Alternate Ethernet Transmit Data 1(2) Alternate Ethernet Transmit Data 2(2) Alternate Ethernet Transmit Data 3(2) Alternate Ethernet transmit error(2) Alternate Ethernet transmit enable(2) Alternate Ethernet transmit clock(2) Alternate Ethernet collision detect(2) Alternate Ethernet carrier sense(2) Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA ERXD0 ERXD1 ERXD2 61 60 59 41 42 43 J7 L7 K7 ERXD3 ERXERR ERXDV ECRSDV ERXCLK EREFCLK 58 64 62 62 63 63 44 35 12 12 14 14 L8 J5 F2 F2 F3 F3 ETXD0 ETXD1 ETXD2 ETXD3 2 3 43 42 88 87 79 80 ETXERR ETXEN ETXCLK ECOL ECRS EMDC EMDIO AERXD0 AERXD1 AERXD2 AERXD3 AERXERR AERXDV 54 1 55 44 45 30 49 43 42 -- -- 55 -- AECRSDV Description Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. DS60001156H-page 42 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A46 O -- E9 C5 B37 B51 I/O O -- -- 97 96 A3 C3 B55 A65 O O -- -- -- -- 95 92 C4 B5 B54 A62 O O -- -- PGED1 16 25 K2 B14 I/O ST PGEC1 15 24 K1 A15 I ST PGED2 18 27 J3 B16 I/O ST PGEC2 17 26 L1 A20 I ST MCLR 7 13 F1 B7 I/P ST AVDD 19 30 J4 A22 P P AVSS 20 31 L3 B18 P P A7, C2, C9, E5, K8, F8, G5, H4, H6 B7 A10, A14, A30, A41, A48, A59, B1, B21, B53 B48 Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA AEMDC 30 71 C11 AEMDIO TRCLK 49 -- 68 91 TRD0 TRD1 -- -- TRD2 TRD3 VDD VCAP VSS VREF+ VREF- 10, 26, 38, 2, 16, 37, 57 46, 62, 86 56 9, 25, 41 16 15 85 A8, B10, A3, A25, D4, D5, A43, A63, 15, 36, 45, E7, F5, B8, B12, 65, 75 F10, G6, B25, B41, G7, H3 B46 29 K3 B17 28 L2 A21 Description Alternate Ethernet Management Data clock(2) Alternate Ethernet Management Data(2) Trace clock Trace Data bits 0-3 Data I/O pin for Programming/ Debugging Communication Channel 1 Clock input pin for Programming/ Debugging Communication Channel 1 Data I/O pin for Programming/ Debugging Communication Channel 2 Clock input pin for Programming/ Debugging Communication Channel 2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules Positive supply for peripheral logic and I/O pins P -- P -- Capacitor for Internal Voltage Regulator Ground reference for logic and I/O pins. This pin must be connected at all times. P I I -- Analog Analog voltage reference (high) input Analog Analog voltage reference (low) input Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are only provided for reference. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information. 2009-2013 Microchip Technology Inc. DS60001156H-page 43 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 44 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 2-1: VDD 2.2 R1 MCLR C (1) PIC32MX VUSB3V3 The AVDD and AVSS pins must be connected, regardless of the ADC use and the ADC voltage reference source. Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A value of 0.1 F (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended to use ceramic capacitors. 2009-2013 Microchip Technology Inc. 0.1 F Ceramic CBP CEFC R The following pin may be required, as well: VREF+/ VREF- pins used when external voltage reference for ADC module is implemented. Note: RECOMMENDED MINIMUM CONNECTION VSS * All VDD and VSS pins (see 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins even if the ADC module is not used (see 2.2 "Decoupling Capacitors") * VCAP pin (see 2.3 "Capacitor on Internal Voltage Regulator (VCAP)") * MCLR pin (see 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see 2.5 "ICSP Pins") * OSC1 and OSC2 pins when external oscillator source is used (see 2.8 "External Oscillator Pins") 0.1 F Ceramic CBP VSS VDD VDD VSS 10 Note 2.2.1 1: 0.1 F Ceramic CBP VSS Basic Connection Requirements Getting started with the PIC32MX5XX/6XX/7XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: VDD 2.1 VDD 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. VCAP Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB track inductance. AVSS GUIDELINES FOR GETTING STARTED WITH 32-BIT MCUS AVDD 2.0 0.1 F Ceramic CBP 0.1 F Ceramic CBP If the USB module is used, this pin must be connected to VDD. BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible. DS60001156H-page 45 PIC32MX5XX/6XX/7XX 2.3 Capacitor on Internal Voltage Regulator (VCAP) 2.3.1 2.5 INTERNAL REGULATOR MODE A low-ESR (1 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 "Electrical Characteristics" for additional information on CEFC specifications. 2.4 Master Clear (MCLR) Pin The MCLR functions: pin provides two specific device * Device Reset * Device Programming and Debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R(1) R1(2) MCLR JP C PIC32 (3) Note 1: R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 3: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during the POR. DS60001156H-page 46 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 3 or MPLAB(R) REAL ICETM. For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. * "Using MPLAB(R) ICD 3" (poster) (DS50001765) * "MPLAB(R) ICD 3 Design Advisory" (DS50001764) * "MPLAB(R) REAL ICETM In-Circuit Emulator User's Guide" (DS50001616) * "Using MPLAB(R) REAL ICETM Emulator" (poster) (DS50001749) 2.6 JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.7 Trace 2.9 The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 series resistor between the trace pins and the trace connector. 2.8 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. Refer to Section 8.0 "Oscillator Configuration" for details. The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analogto-Digital input pins (ANx) as "digital" pins by setting all bits in the AD1PCFG register. The bits in this register that correspond to the Analogto-Digital pins that are initialized by MPLAB ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain ADC pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFG register during initialization of the ADC module. When MPLAB ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all ADC pins being recognized as analog input pins, resulting in the port value being read as a logic `0', which may affect user application functionality. 2.10 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2009-2013 Microchip Technology Inc. DS60001156H-page 47 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 48 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "CPU" (DS60001113) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32(R) M4K(R) Processor Core are available at http://www.mips.com. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The MIPS32(R) M4K(R) Processor core is the heart of the PIC32MX5XX/6XX/7XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 3.1 * * * * Features * 5-stage pipeline * 32-bit address and data paths * MIPS32(R) Enhanced Architecture (Release 2) - Multiply-accumulate and multiply-subtract instructions - Targeted multiply instruction - Zero/One detect instructions - WAIT instruction - Conditional move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base FIGURE 3-1: * * - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16e(R) code compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8-bit and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple dual bus interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous multiply/divide unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) Power control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG debug and instruction trace - Support for single stepping - Virtual instruction and data address/value - Breakpoints - PC tracing with trace compression MIPS(R) M4K(R) PROCESSOR CORE BLOCK DIAGRAM CPU EJTAG MDU TAP Execution Core (RF/ALU/Shift) System Co-processor 2009-2013 Microchip Technology Inc. FMT Bus Interface Off-chip Debug Interface Dual Bus Interface Bus Matrix Power Management DS60001156H-page 49 PIC32MX5XX/6XX/7XX 3.2 Architecture Overview 3.2.2 The MIPS(R) M4K(R) processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: * * * * * * * * Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e(R) Support Enhanced JTAG (EJTAG) Controller 3.2.1 EXECUTION UNIT The MIPS(R) M4K(R) processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. MIPS M4K(R) processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit wide rs, 15 iterations are skipped and for a 24 bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bit-wise logical operations * Shifter and store aligner TABLE 3-1: MULTIPLY/DIVIDE UNIT (MDU) (R) Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. MIPS(R) M4K(R) CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU DS60001156H-page 50 Operand Size (mul rt) (div rs) Latency Repeat Rate 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits 1 2 2 3 12 19 26 33 1 2 1 2 11 18 25 32 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The MIPS(R) architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32(R) architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS(R) architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e(R), is also available by accessing the CP0 registers, listed in Table 3-2. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. TABLE 3-2: Register Number COPROCESSOR 0 REGISTERS Register Name 0-6 7 8 9 10 11 12 12 12 12 13 14 Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) 15 15 16 16 16 16 17-22 23 24 25-29 30 31 PRId Ebase Config Config1 Config2 Config3 Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2) Note 1: 2: Function Reserved. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Processor cycle count. Reserved. Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception. Processor identification and revision. Exception vector base register. Configuration register. Configuration Register 1. Configuration Register 2. Configuration Register 3. Reserved. Debug control and exception status. Program counter at last debug exception. Reserved. Program counter at last error. Debug handler scratchpad register. Registers used in exception processing. Registers used during debug. 2009-2013 Microchip Technology Inc. DS60001156H-page 51 PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. NMI Assertion of NMI signal. Interrupt Assertion of unmasked hardware or software interrupt signal. DIB EJTAG debug hardware instruction break matched. AdEL Fetch address alignment error. Fetch reference to protected address. IBE Instruction fetch bus error. DBp EJTAG breakpoint (execution of SDBBP instruction). Sys Execution of SYSCALL instruction. Bp Execution of BREAK instruction. RI Execution of a reserved instruction. CpU Execution of a coprocessor instruction for a coprocessor that is not enabled. CEU Execution of a CorExtend instruction when CorExtend is not enabled. Ov Execution of an arithmetic instruction that overflowed. Tr Execution of a trap (when trap condition is true). DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). AdEL Load address alignment error. Load reference to protected address. AdES Store address alignment error. Store to protected address. DBE Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare. DS60001156H-page 52 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 3.3 Power Management (R) (R) The MIPS M4K Processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 27.0 "Power-Saving Features". 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX5XX/6XX/7XX family core is in the clock tree and clocking registers. The PIC32 family uses extensive use of local gated clocks to reduce this dynamic power consumption. 2009-2013 Microchip Technology Inc. 3.4 EJTAG Debug Support The MIPS(R) M4K(R) Processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the MIPS(R) M4K(R) core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the MIPS(R) M4K(R) processor core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. DS60001156H-page 53 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 54 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX5XX/6XX/7XX devices to execute from data memory. 4.1 Memory Layout PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX5XX/6XX/7XX devices are illustrated in Figure 4-1 through Figure 4-6. 4.1.1 PERIPHERAL REGISTERS LOCATIONS Table 4-1 through Table 4-44 contain the peripheral address maps for the PIC32MX5XX/6XX/7XX devices. Key features include: * 32-bit native data width * Separate User (KUSEG) and Kernel (KSEG0/ KSEG1) mode address space * Flexible program Flash memory partitioning * Flexible data RAM partitioning for data and program space * Separate boot Flash memory for protected code * Robust bus exception handling to intercept runaway code * Simple memory mapping with Fixed Mapping Translation (FMT) unit * Cacheable (KSEG0) and non-cacheable (KSEG1) address regions 2009-2013 Microchip Technology Inc. DS60001156H-page 55 PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L, PIC32MX664F064H AND PIC32MX664F064L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D010000 0x9D00FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS60001156H-page 56 Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D010000 0x9D00FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80004000 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00004000 0x00003FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2009-2013 Microchip Technology Inc. DS60001156H-page 57 PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D020000 0x9D01FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D020000 Reserved 0x1D01FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS60001156H-page 58 Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D040000 0x9D03FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D040000 Reserved 0x1D03FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00010000 0x0000FFFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2009-2013 Microchip Technology Inc. DS60001156H-page 59 PIC32MX5XX/6XX/7XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 KSEG1 0xBF8FFFFF Reserved Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D080000 0x9D07FFFF KSEG0 0x1F8FFFFF Reserved Program Flash(2) SFRs 0x1F800000 Reserved 0x9D000000 0x80010000 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x8000FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS60001156H-page 60 Reserved Reserved RAM(2) 0x00010000 0x0000FFFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 Reserved 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D080000 0x9D07FFFF KSEG0 0x1F8FFFFF Reserved Program Flash(2) SFRs 0x1F800000 Reserved 0x9D000000 0x80020000 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x8001FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00020000 0x0001FFFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2009-2013 Microchip Technology Inc. DS60001156H-page 61 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 -- -- -- -- -- BMXCHEDMA -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 2010 BMXDKPBA(1) 15:0 -- -- -- -- -- -- -- -- 31:16 2020 BMXDUDBA(1) 15:0 -- -- -- -- -- -- -- -- 31:16 -- 2030 BMXDUPBA(1) 2040 BMXDRMSZ 2060 BMXPFMSZ 2070 BMXBOOTSZ -- -- -- -- -- -- -- 31:16 15:0 19/3 18/2 17/1 -- -- -- -- BMXWSDRM -- 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F BMXARB<2:0> -- -- 0041 -- -- 0000 0000 0000 0000 -- -- -- -- -- BMXDUPBA<15:0> -- 0000 0000 xxxx BMXDRMSZ<31:0> 15:0 15:0 20/4 BMXDUDBA<15:0> 31:16 31:16 21/5 BMXDKPBA<15:0> 15:0 31:16 2050 BMXPUPBA(1) 15:0 22/6 All Resets Register Name BMXCON(1) Bit Range Virtual Address (BF88_#) 2000 BUS MATRIX REGISTER MAP xxxx -- -- -- -- -- -- -- -- -- -- BMXPUPBA<15:0> BMXPFMSZ<31:0> -- -- BMXPUPBA<19:16> 0000 0000 xxxx xxxx BMXBOOTSZ<31:0> 0000 3000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX5XX/6XX/7XX DS60001156H-page 62 TABLE 4-1: 2009-2013 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 DS60001156H-page 63 1090 IPC0 10A0 IPC1 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- 15:0 -- -- -- -- -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- INT4EP -- -- -- -- -- -- TPC<2:0> -- -- -- SRIPL<2:0> 31:16 19/3 18/2 17/1 16/0 -- -- -- SS0 INT3EP INT2EP INT1EP INT0EP -- -- -- -- VEC<5:0> 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI3TXIF SPI3RXIF SPI3EIF I2C3MIF I2C3SIF I2C3BIF -- -- 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF 31:16 IC3EIF IC2EIF IC1EIF -- -- CAN1IF USBIF FCEIF U2TXIF U2RXIF U2EIF 15:0 RTCCIF FSCMIF -- -- -- SPI4TXIF SPI4RXIF SPI4EIF I2C5MIF I2C5SIF I2C5BIF 0000 -- OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF U3TXIF U3RXIF SPI2TXIF SPI2RXIF I2C4MIF I2C4SIF CMP2IF CMP1IF PMPIF AD1IF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF U1TXIE U1RXIE U1EIE SPI3TXIE SPI3RXIE SPI3EIE -- -- -- OC5IE IC5IE T5IE INT4IE OC4IE I2C3MIE I2C3SIE I2C3BIE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 31:16 IC3EIE IC2EIE IC1EIE -- -- CAN1IE USBIE FCEIE U2TXIE U2RXIE U2EIE 15:0 RTCCIE FSCMIE -- -- -- SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4BIE 0000 -- 0000 IC4EIF 0000 IC4IE T4IE 0000 CS0IE CTIE PMPEIF IC5EIF I2C4SIE 0000 0000 U3EIE CMP2IE CMP1IE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> CNIF DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE U3RXIE 0000 0000 I2C4BIF -- U3TXIE 0000 U3EIF SPI2EIF -- I2C1BIE 0000 0000 -- 31:16 I2C1MIE I2C1SIE 0000 0000 0000 IPTMR<31:0> 15:0 31:16 15:0 20/4 CS1IP<2:0> PMPIE AD1IE -- -- PMPEIE IC5EIE CNIE 0000 -- 0000 IC4EIE 0000 CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX534/564/664/764 devices. This register does not have associated CLR, SET, and INV registers. 1: 2: 3: PIC32MX5XX/6XX/7XX 1060 31/15 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-2: Virtual Address (BF88_#) Register Name(1) 10B0 IPC2 INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES (CONTINUED) IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 2009-2013 Microchip Technology Inc. 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 -- -- -- INT2IP<2:0> 15:0 -- -- -- IC2IP<2:0> 31:16 -- -- -- 15:0 -- -- 31:16 -- 15:0 OC2IS<1:0> 0000 T2IP<2:0> T2IS<1:0> 0000 -- OC3IP<2:0> OC3IS<1:0> 0000 -- -- T3IP<2:0> T3IS<1:0> 0000 -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 -- -- -- T4IP<2:0> T4IS<1:0> 0000 -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 U1IP<2:0> U1IS<1:0> SPI3IP<2:0> SPI3IS<1:0> I2C3IP<2:0> I2C3IS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000 21/5 INT2IS<1:0> -- -- -- IC2IS<1:0> -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- IC4IP<2:0> IC4IS<1:0> 31:16 -- -- -- 15:0 -- -- -- IC5IP<2:0> 31:16 -- -- -- AD1IP<2:0> 31:16 -- -- -- -- -- -- 26/10 OC2IP<2:0> 22/6 -- 27/11 16/0 23/7 15:0 28/12 All Resets 10C0 Bit Range Bits -- I2C1IP<2:0> -- 25/9 -- 24/8 -- I2C1IS<1:0> U3IP<2:0> U3IS<1:0> SPI2IP<2:0> SPI2IS<1:0> I2C4IP<2:0> I2C4IS<1:0> -- -- 20/4 -- -- -- -- 19/3 18/2 17/1 0000 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U2IP<2:0> U2IS<1:0> SPI4IP<2:0> SPI4IS<1:0> I2C5IP<2:0> I2C5IS<1:0> 15:0 -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- DMA7IP<2:0>(2) DMA7IS<1:0>(2) -- -- -- DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000 15:0 -- -- -- DMA5IP<2:0>(2) DMA5IS<1:0>(2) -- -- -- DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000 31:16 -- -- -- -- -- -- CAN1IP<2:0> CAN1IS<1:0> 0000 0000 -- -- -- -- -- 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 31:16 -- -- -- U5IP<2:0> U5IS<1:0> -- -- -- U6IP<2:0> U6IS<1:0> 0000 15:0 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- -- 0000 -- -- -- -- Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX534/564/664/764 devices. This register does not have associated CLR, SET, and INV registers. 1: 2: 3: PIC32MX5XX/6XX/7XX DS60001156H-page 64 TABLE 4-2: Virtual Address (BF88_#) Register Name(1) 1000 INTCON 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 65 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 Legend: 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- 15:0 -- -- -- -- -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- 31:16 18/2 17/1 16/0 VEC<5:0> I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI3TXIF SPI3RXIF SPI3EIF I2C3MIF I2C3SIF I2C3BIF -- -- 0000 -- OC5IF IC5IF T5IF INT1IF OC1IF IC1IF T1IF 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF IC3EIF IC2EIF IC1EIF ETHIF -- -- USBIF FCEIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF RTCCIF FSCMIF 31:16 -- -- 15:0 -- -- 31:16 I2C1MIE I2C1SIE -- -- I2C1BIE -- -- DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) CMP2IF INT4IF OC4IF IC4IF T4IF 0000 INT0IF CS1IF CS0IF CTIF 0000 DMA3IF DMA2IF DMA1IF DMA0IF 0000 CMP1IF PMPIF AD1IF CNIF 0000 -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000 U1TXIE U1RXIE U1EIE -- -- -- OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 INT1IE OC1IE IC1IE T1IE SPI3TXIE SPI3RXIE SPI3EIE I2C3MIE I2C3SIE I2C3BIE 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 31:16 IC3EIE IC2EIE IC1EIE ETHIE -- -- USBIE FCEIE U2TXIE U2RXIE 15:0 RTCCIE FSCMIE -- -- -- U2EIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) U3TXIE U3RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE I2C5MIE I2C5BIE I2C4MIE I2C4BIE I2C4SIE CS1IE CS0IE CTIE 0000 DMA2IE DMA1IE DMA0IE 0000 CMP1IE PMPIE AD1IE CNIE 0000 0000 U3EIE SPI4TXIE SPI4RXIE I2C5SIE INT0IE DMA3IE CMP2IE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> CS1IP<2:0> 2: 3: 0000 CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 1: 0000 0000 0000 31:16 15:0 19/3 IPTMR<31:0> 15:0 31:16 -- SRIPL<2:0> 20/4 Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX664 devices. This register does not have associated CLR, SET, and INV registers. PIC32MX5XX/6XX/7XX 1060 31/15 All Resets Bits 1010 INTSTAT(3) Note INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-3: Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 U1IP<2:0> U1IS<1:0> SPI3IP<2:0> SPI3IS<1:0> I2C3IP<2:0> I2C3IS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000 15:0 31:16 -- -- -- -- -- -- -- -- I2C1IP<2:0> -- -- -- I2C1IS<1:0> U3IP<2:0> U3IS<1:0> SPI2IP<2:0> SPI2IS<1:0> I2C4IP<2:0> I2C4IS<1:0> -- -- -- -- -- -- 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U2IP<2:0> U2IS<1:0> SPI4IP<2:0> SPI4IS<1:0> I2C5IP<2:0> I2C5IS<1:0> 15:0 -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- DMA7IP<2:0>(2) DMA7IS<1:0>(2) -- -- -- DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000 15:0 -- -- -- DMA5IP<2:0>(2) DMA5IS<1:0>(2) -- -- -- DMA4IP<2:0>(2) DMA4IS<1:0>(2) 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 31:16 -- -- -- U5IP<2:0> U5IS<1:0> -- -- -- U6IP<2:0> U6IS<1:0> 0000 15:0 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- ETHIP<2:0> ETHIS<1:0> 0000 2009-2013 Microchip Technology Inc. x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX664 devices. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 31:16 Legend: 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 66 TABLE 4-3: Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS60001156H-page 67 10B0 IPC2 IPC3 10C0 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- SRIPL<2:0> 31:16 18/2 17/1 16/0 VEC<5:0> I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI3TXIF SPI3RXIF SPI3EIF I2C3MIF I2C3SIF I2C3BIF -- -- 0000 -- OC5IF IC5IF T5IF INT1IF OC1IF IC1IF T1IF 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF IC3EIF IC2EIF IC1EIF ETHIF CAN2IF(2) CAN1IF USBIF FCEIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF RTCCIF FSCMIF -- -- -- DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) CMP2IF INT4IF OC4IF IC4IF T4IF 0000 INT0IF CS1IF CS0IF CTIF 0000 DMA3IF DMA2IF DMA1IF DMA0IF 0000 CMP1IF PMPIF AD1IF CNIF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000 U1TXIE U1RXIE U1EIE -- -- -- OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 INT1IE OC1IE IC1IE T1IE 31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE I2C3MIE I2C3BIE I2C3SIE 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE(2) CAN1IE USBIE FCEIE U2TXIE U2RXIE 15:0 RTCCIE FSCMIE -- -- -- U2EIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) U3TXIE U3RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE I2C5MIE I2C5BIE I2C4MIE I2C4BIE I2C4SIE CS1IE CS0IE CTIE 0000 DMA2IE DMA1IE DMA0IE 0000 CMP1IE PMPIE AD1IE CNIE 0000 0000 U3EIE SPI4TXIE SPI4RXIE I2C5SIE INT0IE DMA3IE CMP2IE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> CS1IP<2:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This bit is unimplemented on PIC32MX764F128H device. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 CS1IS<1:0> Legend: 1: 0000 0000 0000 31:16 15:0 19/3 IPTMR<31:0> 15:0 31:16 -- 20/4 PIC32MX5XX/6XX/7XX 1060 31/15 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-4: Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 -- -- -- INT4IP<2:0> 15:0 -- -- -- IC4IP<2:0> 31:16 -- -- -- 15:0 -- -- -- IC5IP<2:0> 31:16 -- -- -- AD1IP<2:0> 15:0 31:16 -- -- -- -- 28/12 -- -- 27/11 -- 26/10 -- I2C1IP<2:0> -- 25/9 23/7 22/6 21/5 INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 U1IP<2:0> U1IS<1:0> SPI3IP<2:0> SPI3IS<1:0> I2C3IP<2:0> I2C3IS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000 -- 24/8 -- I2C1IS<1:0> U3IP<2:0> U3IS<1:0> SPI2IP<2:0> SPI2IS<1:0> I2C4IP<2:0> I2C4IS<1:0> -- -- -- -- -- -- 20/4 19/3 18/2 17/1 16/0 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U2IP<2:0> U2IS<1:0> SPI4IP<2:0> SPI4IS<1:0> I2C5IP<2:0> I2C5IS<1:0> 15:0 -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- DMA7IP<2:0>(2) DMA7IS<1:0>(2) -- -- -- DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000 15:0 -- -- -- DMA5IP<2:0>(2) DMA5IS<1:0>(2) -- -- -- DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000 31:16 -- -- -- CAN2IP<2:0>(2) CAN2IS<1:0>(2) -- -- -- CAN1IP<2:0> CAN1IS<1:0> 0000 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 31:16 -- -- -- U5IP<2:0> U5IS<1:0> -- -- -- U6IP<2:0> U6IS<1:0> 0000 15:0 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- ETHIP<2:0> ETHIS<1:0> 0000 2009-2013 Microchip Technology Inc. x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This bit is unimplemented on PIC32MX764F128H device. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 31:16 Legend: 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 68 TABLE 4-4: Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 69 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- -- SRIPL<2:0> 31:16 19/3 18/2 17/1 16/0 VEC<5:0> I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI3TXIF SPI3RXIF SPI3EIF I2C3MIF I2C3SIF I2C3BIF SPI1TXIF SPI1RXIF 0000 0000 SPI1EIF OC5IF IC5IF T5IF INT1IF OC1IF IC1IF T1IF 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF 31:16 IC3EIF IC2EIF IC1EIF -- -- CAN1IF USBIF FCEIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) CMP2IF INT4IF OC4IF IC4IF T4IF INT0IF CS1IF CS0IF CTIF 0000 DMA2IF DMA1IF DMA0IF 0000 CMP1IF PMPIF AD1IF CNIF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000 U1TXIE U1RXIE 31:16 I2C1MIE I2C1SIE I2C1BIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 INT1IE OC1IE IC1IE T1IE U1EIE SPI3TXIE SPI3RXIE SPI3EIE I2C3MIE I2C3SIE I2C3BIE SPI1TXIE SPI1RXIE 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 31:16 IC3EIE IC2EIE IC1EIE -- -- CAN1IE USBIE FCEIE U2TXIE U2RXIE 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2EIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) U3TXIE U3RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE I2C5MIE I2C5BIE I2C4MIE I2C4BIE I2C4SIE CS1IE CS0IE CTIE 0000 DMA2IE DMA1IE DMA0IE 0000 CMP1IE PMPIE AD1IE CNIE 0000 U3EIE SPI4TXIE SPI4RXIE I2C5SIE INT0IE DMA3IE CMP2IE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000 31:16 -- -- -- INT0IP<2:0> INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX534/564 devices. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 DMA3IF Legend: 1: 0000 0000 IPTMR<31:0> 15:0 31:16 20/4 PIC32MX5XX/6XX/7XX 1060 31/15 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-5: Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 -- -- -- INT4IP<2:0> 15:0 -- -- -- IC4IP<2:0> 31:16 -- -- -- 15:0 -- -- 31:16 -- -- 15:0 31:16 -- -- -- -- 28/12 23/7 22/6 21/5 INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 U1IP<2:0> U1IS<1:0> SPI3IP<2:0> SPI3IS<1:0> I2C3IP<2:0> I2C3IS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000 -- 27/11 26/10 I2C1IP<2:0> -- 25/9 24/8 I2C1IS<1:0> U3IP<2:0> U3IS<1:0> SPI2IP<2:0> SPI2IS<1:0> I2C4IP<2:0> I2C4IS<1:0> -- -- 20/4 -- -- -- -- 19/3 18/2 17/1 16/0 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U2IP<2:0> U2IS<1:0> SPI4IP<2:0> SPI4IS<1:0> I2C5IP<2:0> I2C5IS<1:0> 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- DMA7IP<2:0>(2) DMA7IS<1:0>(2) -- -- -- DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000 DMA5IS<1:0>(2) -- -- -- DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000 -- -- -- CAN1IP<2:0> CAN1IS<1:0> 0000 DMA5IP<2:0>(2) 0000 15:0 -- -- -- 31:16 -- -- -- 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 31:16 -- -- -- U5IP<2:0> U5IS<1:0> -- -- -- U6IP<2:0> U6IS<1:0> 0000 15:0 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- -- -- -- -- -- -- -- -- -- -- 2009-2013 Microchip Technology Inc. x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX534/564 devices. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 31:16 Legend: 1: All Resets Bit Range Bits 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 70 TABLE 4-5: Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 71 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- 15:0 -- -- -- -- -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- 31:16 18/2 17/1 16/0 VEC<5:0> I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI3TXIF SPI3RXIF SPI3EIF I2C3MIF I2C3SIF I2C3BIF SPI1TXIF SPI1RXIF 0000 SPI1EIF OC5IF IC5IF T5IF INT1IF OC1IF IC1IF T1IF 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF IC3EIF IC2EIF IC1EIF ETHIF -- -- USBIF FCEIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) CMP2IF INT4IF OC4IF IC4IF T4IF 0000 INT0IF CS1IF CS0IF CTIF 0000 DMA3IF DMA2IF DMA1IF DMA0IF 0000 CMP1IF PMPIF AD1IF CNIF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000 U1TXIE U1RXIE U1EIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 INT1IE OC1IE IC1IE T1IE 31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE I2C3MIE I2C3SIE I2C3BIE SPI1TXIE SPI1RXIE 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 31:16 IC3EIE IC2EIE IC1EIE ETHIE -- -- USBIE FCEIE U2TXIE U2RXIE 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2EIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) U3TXIE U3RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE I2C5MIE I2C5BIE I2C4MIE I2C4BIE I2C4SIE CS1IE CS0IE CTIE 0000 DMA2IE DMA1IE DMA0IE 0000 CMP1IE PMPIE AD1IE CNIE 0000 0000 U3EIE SPI4TXIE SPI4RXIE I2C5SIE INT0IE DMA3IE CMP2IE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> CS1IP<2:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX664 devices. This register does note have associated CLR, SET, and INV registers. 2: 3: 0000 CS1IS<1:0> Legend: 1: 0000 0000 0000 31:16 15:0 19/3 IPTMR<31:0> 15:0 31:16 -- SRIPL<2:0> 20/4 PIC32MX5XX/6XX/7XX 1060 31/15 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-6: Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 -- -- -- INT4IP<2:0> 15:0 -- -- -- IC4IP<2:0> 31:16 -- -- -- 15:0 -- -- 31:16 -- -- 15:0 31:16 -- -- -- -- 28/12 23/7 22/6 21/5 INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 U1IP<2:0> U1IS<1:0> SPI3IP<2:0> SPI3IS<1:0> I2C3IP<2:0> I2C3IS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000 -- 27/11 26/10 I2C1IP<2:0> -- 25/9 24/8 I2C1IS<1:0> U3IP<2:0> U3IS<1:0> SPI2IP<2:0> SPI2IS<1:0> I2C4IP<2:0> I2C4IS<1:0> -- -- 20/4 -- -- -- -- 19/3 18/2 17/1 16/0 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U2IP<2:0> U2IS<1:0> SPI4IP<2:0> SPI4IS<1:0> I2C5IP<2:0> I2C5IS<1:0> 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- DMA7IP<2:0>(2) DMA7IS<1:0>(2) -- -- -- DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000 15:0 -- -- -- DMA5IP<2:0>(2) DMA5IS<1:0>(2) -- -- -- DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000 31:16 -- -- -- -- -- -- 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- 31:16 -- -- -- U5IP<2:0> U5IS<1:0> -- -- -- 15:0 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- -- -- -- -- -- -- -- FCEIP<2:0> -- -- -- 0000 FCEIS<1:0> 0000 U6IP<2:0> U6IS<1:0> 0000 ETHIP<2:0> ETHIS<1:0> 0000 2009-2013 Microchip Technology Inc. x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX664 devices. This register does note have associated CLR, SET, and INV registers. 2: 3: 0000 31:16 Legend: 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 72 TABLE 4-6: Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 73 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- 15:0 -- -- -- -- -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- 0000 -- -- TPC<2:0> -- -- 31:16 19/3 18/2 17/1 16/0 VEC<5:0> 0000 0000 IPTMR<31:0> 15:0 31:16 -- SRIPL<2:0> 20/4 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI3TXIF SPI3RXIF SPI3EIF I2C3MIF I2C3SIF I2C3BIF SPI1TXIF SPI1RXIF 0000 SPI1EIF OC5IF IC5IF T5IF INT1IF OC1IF IC1IF T1IF 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF 31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF(2) CAN1IF USBIF FCEIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) CMP2IF INT4IF OC4IF IC4IF T4IF INT0IF CS1IF CS0IF CTIF 0000 DMA3IF DMA2IF DMA1IF DMA0IF 0000 CMP1IF PMPIF AD1IF CNIF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000 U1TXIE U1RXIE U1EIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 INT1IE OC1IE IC1IE T1IE 31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE I2C3MIE I2C3BIE I2C3SIE SPI1TXIE SPI1RXIE 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE(2) CAN1IE USBIE FCEIE U2TXIE U2RXIE 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2EIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) U3TXIE U3RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE I2C5MIE I2C5BIE I2C4MIE I2C4BIE I2C4SIE CS1IE CS0IE CTIE 0000 DMA2IE DMA1IE DMA0IE 0000 CMP1IE PMPIE AD1IE CNIE 0000 0000 U3EIE SPI4TXIE SPI4RXIE I2C5SIE INT0IE DMA3IE CMP2IE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> CS1IP<2:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This bit is unimplemented on PIC32MX764F128L device. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 CS1IS<1:0> Legend: 1: 0000 PIC32MX5XX/6XX/7XX 1060 31/15 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-7: Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 -- -- -- INT4IP<2:0> 15:0 -- -- -- IC4IP<2:0> 31:16 -- -- -- 15:0 -- -- 31:16 -- -- 15:0 31:16 -- -- -- -- 23/7 22/6 21/5 INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 U1IP<2:0> U1IS<1:0> SPI3IP<2:0> SPI3IS<1:0> I2C3IP<2:0> I2C3IS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000 -- -- 28/12 27/11 I2C1IP<2:0> 26/10 25/9 24/8 I2C1IS<1:0> U3IP<2:0> U3IS<1:0> SPI2IP<2:0> SPI2IS<1:0> I2C4IP<2:0> I2C4IS<1:0> -- -- -- -- -- -- 20/4 19/3 18/2 17/1 16/0 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U2IP<2:0> U2IS<1:0> SPI4IP<2:0> SPI4IS<1:0> I2C5IP<2:0> I2C5IS<1:0> 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- DMA7IP<2:0>(2) DMA7IS<1:0>(2) -- -- -- DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000 15:0 -- -- -- DMA5IP<2:0>(2) DMA5IS<1:0>(2) -- -- -- DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000 31:16 -- -- -- CAN2IP<2:0>(2) CAN2IS<1:0>(2) -- -- -- CAN1IP<2:0> CAN1IS<1:0> 0000 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 31:16 -- -- -- U5IP<2:0> U5IS<1:0> -- -- -- U6IP<2:0> U6IS<1:0> 0000 15:0 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- ETHIP<2:0> ETHIS<1:0> 0000 2009-2013 Microchip Technology Inc. x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This bit is unimplemented on PIC32MX764F128L device. This register does not have associated CLR, SET, and INV registers. 2: 3: 0000 31:16 Legend: 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 74 TABLE 4-7: Virtual Address (BF80_#) TIMER1-TIMER5 REGISTER MAP 0600 T1CON 0610 TMR1 0620 PR1 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- 15:0 ON -- SIDL 31:16 -- -- -- -- -- -- -- -- TWDIS TWIP -- -- -- -- -- 15:0 31:16 0810 TMR2 0820 PR2 TMR3 0A20 PR3 0C20 PR4 TMR5 0E20 PR5 -- -- -- -- TCKPS<1:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 0000 TSYNC TCS -- 0000 -- -- -- 0000 -- -- -- -- 0000 -- -- -- -- 0000 0000 FFFF T32 -- TCS(2) -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 TCKPS<2:0> -- 0000 PR2<15:0> 15:0 FFFF -- -- TCS(2) -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 TCKPS<2:0> TMR3<15:0> -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- -- 0000 PR3<15:0> 15:0 FFFF T32 -- TCS(2) -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 TCKPS<2:0> TMR4<15:0> -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- -- 0000 PR4<15:0> 15:0 15:0 16/0 TMR2<15:0> -- 31:16 17/1 PR1<15:0> 15:0 0E10 -- TGATE -- 31:16 0E00 T5CON -- -- 18/2 FFFF -- -- TCS(2) -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 TCKPS<2:0> TMR5<15:0> -- -- -- -- -- -- -- -- -- 0000 PR5<15:0> DS60001156H-page 75 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on 64-pin devices. 1: 2: FFFF PIC32MX5XX/6XX/7XX TMR4 -- -- 15:0 0C10 19/3 -- 31:16 0C00 T4CON 20/4 -- 15:0 0A10 21/5 -- 31:16 0A00 T3CON 22/6 TMR1<15:0> 15:0 0800 T2CON 23/7 All Resets Bit Range Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-8: Virtual Address (BF80_#) Register Name 2000 IC1CON(1) 2010 IC1BUF 2200 IC2CON(1) 2210 IC2BUF 2400 IC3CON(1) 2410 IC3BUF 2600 IC4CON(1) 2610 IC4BUF 2800 IC5CON(1) 2810 IC5BUF INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- 15:0 ON 25/9 -- -- -- -- -- -- -- SIDL -- -- -- FEDGE 31:16 24/8 23/7 22/6 21/5 -- -- -- -- C32 ICTMR 15:0 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- FEDGE C32 ICTMR 31:16 18/2 -- -- -- ICOV ICBNE 17/1 16/0 -- -- ICM<2:0> 15:0 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- FEDGE C32 ICTMR 31:16 0000 xxxx -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> 15:0 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- FEDGE C32 ICTMR 31:16 0000 xxxx -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> 15:0 -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- FEDGE C32 ICTMR 0000 xxxx -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> 0000 0000 xxxx xxxx -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> IC5BUF<31:0> Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: 0000 xxxx IC4BUF<31:0> 31:16 0000 xxxx IC3BUF<31:0> 31:16 0000 xxxx IC2BUF<31:0> 31:16 15:0 19/3 IC1BUF<31:0> 31:16 31:16 ICI<1:0> 20/4 All Resets Bit Range Bits 0000 0000 xxxx xxxx PIC32MX5XX/6XX/7XX DS60001156H-page 76 TABLE 4-9: 2009-2013 Microchip Technology Inc. Virtual Address (BF80_#) OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP 3000 OC1CON 3010 OC1R 3020 OC1RS 3200 OC2CON 3210 OC2R 3220 OC2RS 3400 OC3CON 3410 OC3R 3420 OC3RS 3610 OC4R 3620 OC4RS 3800 OC5CON 3810 OC5R 3820 OC5RS 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 -- 15:0 ON -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- OC32 31:16 21/5 20/4 19/3 18/2 -- -- -- OCFLT OCTSEL 31:16 0000 xxxx xxxx -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- -- -- OCM<2:0> 31:16 xxxx xxxx xxxx OC2RS<31:0> 15:0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- -- -- OCM<2:0> 31:16 15:0 xxxx xxxx xxxx OC3RS<31:0> xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- -- -- OCM<2:0> 31:16 15:0 xxxx xxxx xxxx OC4RS<31:0> xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL -- -- -- OCM<2:0> OC5R<31:0> OC5RS<31:0> DS60001156H-page 77 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: 0000 0000 OC4R<31:0> 15:0 0000 0000 OC3R<31:0> 15:0 0000 0000 OC2R<31:0> 15:0 0000 xxxx -- 15:0 -- OC1RS<31:0> 15:0 31:16 -- OCM<2:0> xxxx 31:16 15:0 16/0 OC1R<31:0> 15:0 31:16 17/1 All Resets 31/15 0000 0000 xxxx xxxx xxxx xxxx PIC32MX5XX/6XX/7XX 3600 OC4CON Bit Range Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-10: Virtual Address (BF80_#) Register Name(1) 2009-2013 Microchip Technology Inc. 5000 I2C3CON 5010 I2C3STAT 5020 I2C3ADD 5030 I2C3MSK 5040 I2C3BRG 5050 I2C3TRN 5060 I2C3RCV 5100 I2C4CON 5110 I2C4STAT 5120 I2C4ADD 5130 I2C4MSK 5140 I2C4BRG 5150 I2C4TRN 5160 I2C4RCV 5200 I2C5CON 5210 I2C5STAT I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 31/15 30/14 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 ADD<9:0> -- -- -- -- -- -- -- -- -- -- MSK<9:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- Transmit Register -- 0000 0000 Baud Rate Generator Register -- 0000 0000 -- -- 0000 0000 -- -- -- Receive Register 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 ADD<9:0> -- -- -- -- -- -- -- -- -- -- MSK<9:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- Transmit Register -- 0000 0000 Baud Rate Generator Register -- 0000 0000 -- -- 0000 0000 -- -- -- Receive Register 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: PIC32MX5XX/6XX/7XX DS60001156H-page 78 TABLE 4-11: Virtual Address (BF80_#) Register Name(1) 5220 I2C5ADD 5230 I2C5MSK 5240 I2C5BRG 5250 I2C5TRN 5260 I2C5RCV 5300 I2C1CON 5310 I2C1STAT 5320 I2C1ADD 5330 I2C1MSK 5340 I2C1BRG 5350 I2C1TRN 5360 I2C1RCV I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP (CONTINUED) All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-11: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 ADD<9:0> -- -- -- -- -- -- -- -- -- -- MSK<9:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- Transmit Register -- 0000 0000 Baud Rate Generator Register -- 0000 0000 -- -- 0000 0000 -- -- -- Receive Register 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- ADD<9:0> -- -- -- -- -- -- -- -- -- -- MSK<9:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Transmit Register -- -- -- 0000 0000 -- -- Receive Register 0000 0000 -- -- -- 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: DS60001156H-page 79 PIC32MX5XX/6XX/7XX -- 0000 0000 Baud Rate Generator Register -- 0000 0000 Virtual Address (BF80_#) 5410 I2C2STAT 5420 I2C2ADD 5430 I2C2MSK 5440 I2C2BRG I2C2TRN 5460 I2C2RCV 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Bits 5400 I2C2CON 5450 I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- ADD<9:0> -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 MSK<9:0> 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 0000 Baud Rate Generator Register 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 0000 Transmit Register -- -- Receive Register 0000 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: PIC32MX5XX/6XX/7XX DS60001156H-page 80 TABLE 4-12: 2009-2013 Microchip Technology Inc. Virtual Address (BF80_#) UART1 THROUGH UART6 REGISTER MAP 6000 U1MODE(1) 6010 U1STA(1) 6020 U1TXREG 6030 U1RXREG 6040 U1BRG(1) 6200 U4MODE(1) U4STA(1) 6220 U4TXREG 6230 U4RXREG 6240 U4BRG(1) 6400 U3MODE(1) 6410 U3STA(1) 6420 U3TXREG 6430 U3RXREG 6440 U3BRG(1) DS60001156H-page 81 6600 U6MODE(1) 6610 U6STA(1) 6620 U6TXREG 30/14 29/13 31:16 -- -- -- 15:0 ON -- SIDL 31:16 -- -- 15:0 UTXISEL<1:0> 31:16 -- 15:0 28/12 27/11 26/10 25/9 24/8 -- -- -- -- -- IREN RTSMD -- UEN<1:0> -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 23/7 22/6 21/5 20/4 19/3 18/2 17/1 -- -- 16/0 -- -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH ADDEN RIDLE PERR FERR OERR URXDA -- -- -- -- -- -- PDSEL<1:0> -- 0000 STSEL 0000 ADDR<7:0> URXISEL<1:0> -- -- 0000 Transmit Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- SIDL IREN -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH 31:16 -- -- -- -- -- -- -- ADM_EN UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- PDSEL<1:0> -- STSEL ADDR<7:0> URXISEL<1:0> -- -- ADDEN RIDLE PERR FERR OERR URXDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL IREN RTSMD -- 31:16 -- -- 15:0 UTXISEL<1:0> 31:16 -- 15:0 -- -- UEN<1:0> -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- LPBACK ABAUD RXINV BRGH ADDEN RIDLE -- -- PERR FERR OERR URXDA -- -- -- -- -- -- PDSEL<1:0> -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- SIDL IREN -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 -- -- -- -- -- PDSEL<1:0> -- STSEL 0000 URXISEL<1:0> -- 0000 0000 0000 ADDEN RIDLE PERR FERR OERR URXDA -- -- -- -- -- -- Transmit Register Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: 0000 0000 ADDR<7:0> -- 0000 0000 15:0 UTXISEL<1:0> 0110 0000 Receive Register 31:16 15:0 0000 0000 BRG<15:0> 31:16 0000 -- Transmit Register -- 0000 STSEL ADDR<7:0> URXISEL<1:0> -- 0110 0000 WAKE -- 0000 0000 BRG<15:0> 31:16 0000 0000 Receive Register -- 0000 0000 Transmit Register -- 0000 0000 31:16 15:0 15:0 0000 0000 BRG<15:0> 31:16 0110 0000 Receive Register -- All Resets 31/15 0110 0000 0000 PIC32MX5XX/6XX/7XX 6210 Bit Range Bits Register Name 2009-2013 Microchip Technology Inc. TABLE 4-13: Virtual Address (BF80_#) Register Name 6630 U6RXREG 6640 U6BRG(1) UART1 THROUGH UART6 REGISTER MAP (CONTINUED) 6800 U2MODE(1) U2STA(1) 6810 6820 U2TXREG 6830 U2RXREG 6840 U2BRG(1) 6A00 U5MODE(1) U5STA(1) 6A10 6A20 U5TXREG 6A30 U5RXREG 6A40 U5BRG(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- Receive Register -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL IREN RTSMD -- 31:16 -- -- 15:0 UTXISEL<1:0> 31:16 -- 15:0 -- -- UEN<1:0> -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- LPBACK ABAUD RXINV BRGH ADDEN RIDLE -- -- PERR FERR OERR URXDA -- -- -- -- -- -- PDSEL<1:0> -- 0000 STSEL 0000 ADDR<7:0> URXISEL<1:0> -- 0000 Transmit Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL IREN -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH 31:16 -- -- -- -- -- -- -- ADM_EN UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- PDSEL<1:0> -- STSEL ADDR<7:0> URXISEL<1:0> -- -- ADDEN RIDLE PERR FERR OERR URXDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0110 0000 0000 0000 -- -- -- BRG<15:0> 2009-2013 Microchip Technology Inc. Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: 0000 0000 Receive Register -- 0000 0000 Transmit Register -- 0000 0000 31:16 15:0 0000 0000 BRG<15:0> 31:16 0110 0000 Receive Register -- 0000 0000 WAKE -- 0000 0000 BRG<15:0> 31:16 All Resets Bit Range Bits 0000 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 82 TABLE 4-13: Virtual Address (BF80_#) 5800 SPI3CON 5810 SPI3STAT 5820 SPI3BUF 5830 SPI3BRG 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5C00 SPI4CON SPI4BUF 5C30 SPI4BRG 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL -- SIDL 31:16 -- -- -- 15:0 -- -- -- 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 SMP -- CKE SSEN -- -- -- SRMT SPIROV SPIRBE RXBUFELM<4:0> -- SPIBUSY -- -- SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 -- -- CKP MSTEN -- -- -- SPIFE -- STXISEL<1:0> 16/0 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> -- SPITBE -- -- 15:0 -- 31:16 FRMEN -- -- -- -- FRMSYNC FRMPOL 15:0 ON -- SIDL 31:16 -- -- -- 15:0 -- -- -- -- -- -- -- -- -- MSSEN FRMSYPW DISSDO MODE32 -- -- SPITBF SPIRBF -- SPIBUSY 0000 -- -- -- -- -- -- MODE16 SMP SSEN CKP MSTEN -- -- -- -- -- 31:16 SRMT SPIROV SPIRBE -- -- -- -- -- -- -- SPIFE -- STXISEL<1:0> -- BRG<8:0> CKE RXBUFELM<4:0> SPITUR 0000 SRXISEL<1:0> TXBUFELM<4:0> -- -- 15:0 -- 31:16 FRMEN -- -- -- -- FRMSYNC FRMPOL 15:0 ON -- SIDL 31:16 -- -- -- 15:0 -- -- -- -- -- -- -- -- -- MSSEN FRMSYPW DISSDO MODE32 -- -- SPITBE -- SPITBF SPIRBF MODE16 SMP CKE -- SPIBUSY -- -- 31:16 SPITUR -- -- -- -- -- SSEN CKP MSTEN -- -- -- SRMT SPIROV SPIRBE -- -- -- -- -- -- -- SPIFE -- STXISEL<1:0> -- 0000 SRXISEL<1:0> TXBUFELM<4:0> -- 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- 0000 ENHBUF 0000 SPITBE -- 0000 0000 SPITBF SPIRBF 0008 0000 DATA<31:0> 15:0 0008 0000 -- BRG<8:0> RXBUFELM<4:0> 0000 0000 0000 -- FRMCNT<2:0> 0000 ENHBUF 0000 DATA<31:0> 15:0 0008 0000 -- FRMCNT<2:0> 0000 0000 DATA<31:0> 15:0 31:16 23/7 FRMCNT<2:0> MODE16 31:16 31:16 24/8 All Resets Bit Range 31/15 0000 -- -- -- BRG<8:0> -- -- -- -- 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: DS60001156H-page 83 PIC32MX5XX/6XX/7XX 5C10 SPI4STAT 5C20 SPI2, SPI3 AND SPI4 REGISTER MAP Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-14: Virtual Address (BF80_#) 5E10 SPI1STAT SPI1BUF 5E30 SPI1BRG 31/15 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL -- SIDL 31:16 -- -- -- 15:0 -- -- -- 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 24/8 23/7 -- CKE SSEN -- -- -- SRMT SPIROV SPIRBE FRMCNT<2:0> MODE16 SMP RXBUFELM<4:0> -- SPIBUSY -- -- 31:16 SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 -- -- CKP MSTEN -- -- -- SPIFE -- STXISEL<1:0> 16/0 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> -- SPITBE -- 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- 0000 0000 SPITBF SPIRBF 0008 0000 DATA<31:0> 15:0 All Resets Bit Range Register Name(1) Bits 5E00 SPI1CON 5E20 SPI1 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 0000 -- -- -- BRG<8:0> -- -- -- -- 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table except SPI1BUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: PIC32MX5XX/6XX/7XX DS60001156H-page 84 TABLE 4-15: 2009-2013 Microchip Technology Inc. Virtual Address (BF80_#) ADC REGISTER MAP 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 DS60001156H-page 85 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB 30/14 29/13 28/12 27/11 26/10 31:16 -- 15:0 ON 31:16 -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- 15:0 VCFG2 VCFG1 VCFG0 OFFCAL -- CSCNA -- -- BUFS -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 ADRC -- -- 31:16 CH0NB -- -- -- 15:0 -- -- -- -- 25/9 24/8 23/7 -- -- -- 22/6 21/5 -- -- 18/2 17/1 16/0 -- -- -- -- -- -- ASAM SAMP DONE 0000 -- -- -- -- -- -- 0000 BUFM ALTS 0000 -- -- -- -- -- 0000 CH0NA -- -- -- -- -- -- -- SSRC<2:0> SMPI<3:0> -- -- ADCS<7:0> CH0SB<3:0> -- 19/3 CLRASAM FORM<2:0> SAMC<4:0> -- 20/4 -- -- -- 0000 0000 CH0SA<3:0> -- -- 0000 -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>) Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets 31/15 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MX5XX/6XX/7XX 90A0 ADC1BUF3 Bit Range Bits Register Name 2009-2013 Microchip Technology Inc. TABLE 4-16: Virtual Address (BF80_#) ADC REGISTER MAP (CONTINUED) 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Register Name Bits 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 86 TABLE 4-16: 2009-2013 Microchip Technology Inc. Virtual Address (BF88_#) 3000 DMACON(1) DMASTAT 3020 DMAADDR 30/14 29/13 31:16 -- -- -- 15:0 ON -- -- 31:16 -- -- -- -- 15:0 -- -- -- -- 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RDWR SUSPEND DMABUSY 31:16 DMACH<2:0>(2) 0000 DMAADDR<31:0> 15:0 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMACH<3> bit is not available on PIC32MX534/564/664/764 devices. Virtual Address (BF88_#) TABLE 4-18: 0000 0000 Legend: 1: 2: All Resets Bit Range 31/15 DMA CRC REGISTER MAP(1) 3040 DCRCDATA 3050 DCRCXOR 31/15 30/14 31:16 -- -- 15:0 -- -- 31:16 15:0 31:16 15:0 29/13 28/12 BYTO<1:0> -- 27/11 WBO 26/10 25/9 24/8 -- -- BITO PLEN<4:0> 23/7 22/6 21/5 20/4 19/3 18/2 -- -- -- -- -- -- CRCEN CRCAPP CRCTYP -- -- 17/1 16/0 -- -- CRCCH<2:0> DCRCDATA<31:0> DCRCXOR<31:0> Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: 0000 0000 0000 0000 0000 0000 DS60001156H-page 87 PIC32MX5XX/6XX/7XX 3030 DCRCCON Bit Range Register Name(1) Bits All Resets 3010 DMA GLOBAL REGISTER MAP Bits Register Name 2009-2013 Microchip Technology Inc. TABLE 4-17: Virtual Address (BF88_#) 3070 DCH0ECON 3090 DCH0INT DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 2009-2013 Microchip Technology Inc. 3130 DCH1ECON 3140 3150 DCH1INT DCH1SSA 3160 DCH1DSA 3170 DCH1SSIZ 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 15:0 CHSIRQ<7:0> 31:16 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18/2 17/1 16/0 -- -- CHCHN CHAEN -- -- -- -- -- CHEDET CHPRI<1:0> CHAIRQ<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- 0000 -- -- -- -- -- 0000 0000 0000 0000 0000 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 31:16 CHPRI<1:0> CHAIRQ<7:0> -- -- -- -- -- -- -- -- -- 0000 00FF 0000 0000 0000 0000 CHDSA<31:0> 15:0 15:0 0000 CHSSA<31:0> 15:0 31:16 CHPDAT<7:0> 0000 -- -- -- -- -- -- -- CHSSIZ<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices. 2: 0000 0000 Legend: 1: 0000 0000 CHCPTR<15:0> 31:16 0000 0000 CHCSIZ<15:0> -- 0000 00FF CHDPTR<15:0> 15:0 31:16 19/3 CHSPTR<15:0> 15:0 31:16 20/4 CHDSIZ<15:0> 15:0 31:16 21/5 CHSSIZ<15:0> 15:0 31:16 22/6 CHDSA<31:0> 15:0 31:16 23/7 CHSSA<31:0> 15:0 31:16 24/8 All Resets Bit Range Register Name(1) Bits 3060 DCH0CON 3080 DMA CHANNELS 0-7 REGISTER MAP 0000 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 88 TABLE 4-19: Virtual Address (BF88_#) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DCH2INT DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ DS60001156H-page 89 3280 DCH2CPTR 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 CHCSIZ<15:0> 15:0 -- -- 0000 CHCPTR<15:0> 31:16 -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 0000 0000 CHCPTR<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices. 2: 0000 0000 CHCSIZ<15:0> -- 0000 0000 CHDPTR<15:0> 15:0 31:16 0000 CHSPTR<15:0> 15:0 31:16 -- 0000 0000 CHDSIZ<15:0> 15:0 31:16 -- 0000 00FF CHSSIZ<15:0> 15:0 31:16 CHPRI<1:0> CHAIRQ<7:0> CHDSA<31:0> 15:0 31:16 0000 CHSSA<31:0> 15:0 31:16 31:16 CHPDAT<7:0> Legend: 1: 0000 0000 CHDPTR<15:0> 15:0 31:16 23/7 CHSPTR<15:0> 15:0 31:16 24/8 CHDSIZ<15:0> -- All Resets Bit Range 31:16 31/15 0000 0000 PIC32MX5XX/6XX/7XX 3210 DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-19: Virtual Address (BF88_#) Register Name(1) 3290 DCH2DAT 32B0 DCH3ECON DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT 2009-2013 Microchip Technology Inc. 3360 DCH4CON 3370 DCH4ECON 3380 3390 DCH4INT DCH4SSA 33A0 DCH4DSA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- 0000 -- CHEDET 0000 CHPRI<1:0> CHAIRQ<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 15:0 31:16 15:0 CHPDAT<7:0> 0000 CHPRI<1:0> CHAIRQ<7:0> 0000 00FF CHSSA<31:0> CHDSA<31:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices. 2: 0000 0000 CHCPTR<15:0> 31:16 0000 0000 CHCSIZ<15:0> -- 0000 00FF CHDPTR<15:0> 15:0 31:16 -- CHPDAT<7:0> CHSPTR<15:0> 15:0 31:16 16/0 CHDSIZ<15:0> 15:0 31:16 17/1 CHSSIZ<15:0> 15:0 31:16 18/2 CHDSA<31:0> 15:0 31:16 19/3 CHSSA<31:0> 15:0 31:16 20/4 Legend: 1: All Resets Bit Range Bits 32A0 DCH3CON 32C0 DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 90 TABLE 4-19: Virtual Address (BF88_#) 33B0 DCH4SSIZ 33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR 3410 DCH4DAT 3420 DCH5CON 3430 DCH5ECON 3450 DCH5INT DCH5SSA 3460 DCH5DSA 3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR 34A0 DCH5DPTR DS60001156H-page 91 34B0 DCH5CSIZ 34C0 DCH5CPTR 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- 0000 15:0 31:16 CHSSIZ15:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- 0000 -- -- -- -- -- -- -- -- -- 0000 CHDPTR<15:0> 15:0 31:16 -- CHSPTR<15:0> 15:0 31:16 -- CHDSIZ<15:0> 15:0 31:16 -- -- 0000 CHCSIZ<15:0> 15:0 -- -- 0000 CHCPTR<15:0> 31:16 -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 0000 0000 CHCPTR<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices. 2: 0000 0000 CHCSIZ<15:0> -- 0000 0000 CHDPTR<15:0> 15:0 31:16 0000 CHSPTR<15:0> 15:0 31:16 -- 0000 0000 CHDSIZ<15:0> 15:0 31:16 -- 0000 00FF CHSSIZ<15:0> 15:0 31:16 CHPRI<1:0> CHAIRQ<7:0> CHDSA<31:0> 15:0 31:16 0000 CHSSA<31:0> 15:0 31:16 31:16 CHPDAT<7:0> Legend: 1: All Resets Bit Range 31:16 31/15 0000 0000 PIC32MX5XX/6XX/7XX 3440 DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-19: Virtual Address (BF88_#) 34E0 DCH6CON 34F0 DCH6ECON 3510 DCH6INT DCH6SSA 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR 3590 DCH6DAT 2009-2013 Microchip Technology Inc. 35A0 DCH7CON 35B0 DCH7ECON 35C0 DCH7INT 35D0 DCH7SSA 35E0 DCH7DSA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- 0000 -- CHEDET 0000 CHPRI<1:0> CHAIRQ<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF CHSIRQ<7:0> 15:0 31:16 15:0 31:16 15:0 CHPDAT<7:0> 0000 CHPRI<1:0> CHAIRQ<7:0> 0000 00FF CHSSA<31:0> CHDSA<31:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices. 2: 0000 0000 CHCPTR<15:0> 31:16 0000 0000 CHCSIZ<15:0> -- 0000 00FF CHDPTR<15:0> 15:0 31:16 -- CHPDAT<7:0> CHSPTR<15:0> 15:0 31:16 16/0 CHDSIZ<15:0> 15:0 31:16 17/1 CHSSIZ<15:0> 15:0 31:16 18/2 CHDSA<31:0> 15:0 31:16 19/3 CHSSA<31:0> 15:0 31:16 20/4 Legend: 1: All Resets Bit Range Register Name(1) Bits 34D0 DCH5DAT 3500 DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 92 TABLE 4-19: Virtual Address (BF88_#) 35F0 DCH7SSIZ 3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR 3650 DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) DCH7DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- 0000 0000 0000 CHCPTR<15:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- 0000 CHPDAT<7:0> Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices. 1: 2: 0000 0000 CHCSIZ<15:0> -- 0000 0000 CHDPTR<15:0> 15:0 31:16 22/6 CHSPTR<15:0> 15:0 31:16 23/7 CHDSIZ<15:0> 15:0 31:16 24/8 CHSSIZ<15:0> -- All Resets Bit Range Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-19: 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 93 Virtual Address (BF80_#) COMPARATOR REGISTER MAP A000 CM1CON A010 CM2CON A060 CMSTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- 31:16 -- -- -- -- -- -- -- -- 15:0 ON COE CPOL -- -- -- -- COUT 31:16 -- -- -- -- -- -- -- -- 15:0 ON COE CPOL -- -- -- -- COUT 31:16 -- -- -- -- -- -- -- 15:0 -- -- SIDL -- -- -- -- 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- EVPOL<1:0> -- CREF -- -- -- CCH<1:0> -- -- All Resets Register Name(1) Bit Range Bits 0000 00C3 -- -- -- -- -- EVPOL<1:0> -- CREF -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- C2OUT C1OUT 0000 CCH<1:0> 0000 00C3 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Virtual Address (BF80_#) TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP 9800 CVRCON 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- -- -- -- -- 15:0 ON -- -- -- -- VREFSEL(2) 25/9 24/8 23/7 -- -- -- -- -- CVROE BGSEL<1:0>(2) 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- CVRR CVRSS CVR<3:0> All Resets Register Name(1) Bit Range Bits 0000 0100 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. These bits are not available on PIC32MX575/675/695/775/795 devices. On these devices, reset value for CVRCON is `0000'. 1: 2: PIC32MX5XX/6XX/7XX DS60001156H-page 94 TABLE 4-20: 2009-2013 Microchip Technology Inc. Virtual Address (BF80_#) FLASH CONTROLLER REGISTER MAP F410 F440 NVMSRC ADDR 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 WR WREN WRERR LVDERR LVDSTAT -- -- -- -- -- -- -- NVMOP<3:0> 31:16 0000 0000 0000 NVMADDR<31:0> 15:0 31:16 0000 0000 NVMDATA<31:0> 15:0 31:16 0000 0000 NVMSRCADDR<31:0> 15:0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: OSCTUN 0000 WDTCON F600 RCON F610 RSWRST DS60001156H-page 95 F230 SYSKEY Legend: Note Bit Range Register Name(1) Bits F000 OSCCON F010 SYSTEM CONTROL REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- 31:16 -- -- -- -- -- -- -- PLLODIV<2:0> COSC<2:0> -- 25/9 24/8 23/7 22/6 21/5 FRCDIV<2:0> -- SOSCRDY -- NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000 -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- 20/4 19/3 18/2 PBDIV<1:0> 17/1 16/0 PLLMULT<2:0> 0000 TUN<5:0> 0000 15:0 ON -- -- -- -- -- -- -- -- -- WDTCLR 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 SWDTPS<4:0> 15:0 -- -- -- -- -- -- CMR VREGS EXTR SWR -- WDTO SLEEP IDLE BOR POR 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SWRST 0000 31:16 15:0 SYSKEY<31:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 1: 2: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset. 0000 0000 PIC32MX5XX/6XX/7XX Virtual Address (BF80_#) TABLE 4-23: 0000 0000 NVMKEY<31:0> 15:0 F420 NVMADDR(1) NVMDATA 29/13 31:16 NVMKEY F430 30/14 All Resets(2) F400 NVMCON(1) 31/15 All Resets Bit Range Bits Register Name 2009-2013 Microchip Technology Inc. TABLE 4-22: Virtual Address (BF88_#) Register Name(1) 6000 TRISA 6010 PORTA 6020 LATA 6030 ODCA PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISA15 TRISA14 -- -- -- TRISA10 TRISA9 -- TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RA15 RA14 -- -- -- RA10 RA9 -- RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATA15 LATA14 -- -- -- LATA10 LATA9 -- LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCA15 ODCA14 -- -- -- ODCA10 ODCA9 -- ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: Virtual Address (BF88_#) Register Name(1) TABLE 4-25: 6040 TRISB 2009-2013 Microchip Technology Inc. 6050 All Resets Bit Range Bits PORTB REGISTER MAP PORTB 6060 LATB 6070 ODCB 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 96 TABLE 4-24: Virtual Address (BF88_#) Register Name(1) 6080 TRISC 6090 PORTC 60A0 LATC 60B0 ODCC PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 -- -- -- -- -- -- -- -- -- -- -- -- F000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RC15 RC14 RC13 RC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATC15 LATC14 LATC13 LATC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCC15 ODCC14 ODCC13 ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: Register Name(1) TRISC PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 6090 PORTC DS60001156H-page 97 60A0 LATC 60B0 ODCC 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 -- -- -- -- -- -- -- TRISC4 TRISC3 TRISC2 TRISC1 -- F00F 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RC15 RC14 RC13 RC12 -- -- -- -- -- -- -- RC4 RC3 RC2 RC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATC15 LATC14 LATC13 LATC12 -- -- -- -- -- -- -- LATC4 LATC3 LATC2 LATC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCC15 ODCC14 ODCC13 ODCC12 -- -- -- -- -- -- -- ODCC4 ODCC3 ODCC2 ODCC1 -- 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) TABLE 4-27: 6080 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-26: Virtual Address (BF88_#) Register Name(1) 60C0 TRISD 60D0 PORTD 60E0 LATD 60F0 ODCD PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: Register Name(1) 2009-2013 Microchip Technology Inc. Virtual Address (BF88_#) TABLE 4-29: 60C0 TRISD All Resets Bit Range Bits PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 60D0 PORTD 60E0 LATD 60F0 ODCD 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LAT15 LAT14 LAT13 LAT12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 98 TABLE 4-28: Virtual Address (BF88_#) Register Name(1) 6100 TRISE 6110 PORTE 6120 LATE 6130 ODCE PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: Register Name(1) TRISE 6110 PORTE 6120 LATE 6130 ODCE PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- -- -- -- RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- ODCE9 ODCE8 ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 99 Virtual Address (BF88_#) TABLE 4-31: 6100 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-30: Virtual Address (BF88_#) Register Name(1) 6140 TRISF PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 6150 PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- TRISF5 31:16 -- -- -- -- -- -- -- -- -- -- -- 20/4 17/1 16/0 19/3 18/2 -- -- -- -- -- TRISF4 TRISF3 -- TRISF1 TRISF0 003B -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- RF5 RF4 RF3 -- RF1 RF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- LATF5 LATF4 LATF3 -- LATF1 LATF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- ODCF5 ODCF4 ODCF3 -- ODCF1 ODCF0 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Register Name(1) 2009-2013 Microchip Technology Inc. Virtual Address (BF88_#) TABLE 4-33: 6140 TRISF 6150 PORTF 6160 LATF 6170 ODCF 0000 31:16 Legend: 1: All Resets Bit Range Bits PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 31:16 -- -- 15:0 -- -- 31:16 -- -- 15:0 -- -- 31:16 -- -- 15:0 -- -- 31:16 -- -- 15:0 -- -- 29/13 28/12 27/11 26/10 25/9 -- -- -- -- TRISF13 TRISF12 -- -- -- -- -- -- RF13 RF12 -- -- -- -- -- -- LATF13 LATF12 -- -- -- -- -- -- ODCF13 ODCF12 -- -- 21/5 20/4 19/3 18/2 17/1 16/0 24/8 23/7 22/6 -- -- -- -- -- -- -- -- -- -- 0000 -- TRISF8 -- -- TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F -- -- -- -- -- -- -- -- -- -- 0000 -- RF8 -- -- RF5 RF4 RF3 RF2 RF1 RF0 xxxx -- -- -- -- -- -- -- -- -- -- 0000 -- LATF8 -- -- LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx -- -- -- -- -- -- -- -- -- -- 0000 -- ODCF8 -- -- ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX DS60001156H-page 100 TABLE 4-32: Virtual Address (BF88_#) Register Name(1) 6180 TRISG PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 6190 PORTG 61A0 LATG 61B0 ODCG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- TRISG9 TRISG8 -- -- -- -- TRISG7 TRISG6 -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- RG9 RG8 RG7 RG6 -- 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- LATG9 LATG8 LATG7 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- ODCG9 ODCG8 19/3 18/2 17/1 16/0 -- -- -- -- 0000 TRISG3 TRISG2 -- -- 03CC -- -- -- -- 0000 -- RG3 RG2 -- -- xxxx -- -- -- -- -- -- 0000 LATG6 -- -- LATG3 LATG2 -- -- xxxx -- -- -- -- -- -- -- -- 0000 ODCG7 ODCG6 -- -- ODCG3 ODCG2 -- -- 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: Register Name(1) 6180 TRISG PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 6190 PORTG DS60001156H-page 101 61A0 LATG 61B0 ODCG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 TRISG15 TRISG14 TRISG13 TRISG12 -- -- TRISG9 TRISG8 TRISG7 TRISG6 -- -- TRISG3 TRISG2 TRISG1 TRISG0 F3CF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 RG15 RG14 RG13 RG12 -- -- RG9 RG8 RG7 RG6 -- -- RG3 RG2 RG1 RG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATG15 LATG14 LATG13 LATG12 -- -- LATG9 LATG8 LATG7 LATG6 -- -- LATG3 LATG2 LATG1 LATG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCG15 ODCG14 ODCG13 ODCG12 -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 ODCG1 ODCG0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Bits PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) TABLE 4-35: All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-34: Virtual Address (BF88_#) CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES 61C0 CNCON 61D0 CNEN 61E0 CNPUE 31/15 30/14 31:16 -- 15:0 ON 31:16 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 31:16 -- -- -- -- -- -- -- -- -- -- CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE2 CNPUE1 CNPUE0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: TABLE 4-37: Virtual Address (BF88_#) All Resets Register Name(1) Bit Range Bits 0000 0000 CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 61C0 CNCON 61D0 CNEN 2009-2013 Microchip Technology Inc. 61E0 CNPUE 31/15 30/14 31:16 -- 15:0 ON 31:16 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- CNEN18 CNEN17 CNEN16 0000 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 0000 CNPUE18 CNPUE17 CNPUE16 0000 CNPUE2 CNPUE1 CNPUE0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 1: All Resets Bit Range Register Name(1) Bits 0000 PIC32MX5XX/6XX/7XX DS60001156H-page 102 TABLE 4-36: Virtual Address (BF80_#) Register Name(1) 7000 PMCON PARALLEL MASTER PORT REGISTER MAP 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 PMDIN 7050 PMAEN 7060 PMSTAT 31/15 30/14 29/13 31:16 -- -- -- 15:0 ON -- SIDL 31:16 -- -- -- 15:0 BUSY 31:16 -- IRQM<1:0> -- -- 28/12 27/11 -- -- ADRMUX<1:0> -- -- INCM<1:0> -- -- 26/10 25/9 24/8 23/7 22/6 -- -- -- -- -- PMPTTL PTWREN PTRDEN -- -- -- MODE16 -- -- MODE<1:0> -- -- -- -- 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- ALP CS2P CS1P -- WRSP RDSP 0000 -- -- -- -- -- -- 0000 -- -- -- -- WAITB<1:0> -- 15:0 CS2EN/A15 CS1EN/A14 WAITM<3:0> -- WAITE<1:0> -- ADDR<13:0> 31:16 31:16 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 IBF IBOV -- -- IB3F IB2F IB1F IB0F 15:0 -- 0000 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 OBE OBUF -- -- OB3E OB2E OB1E OB0E 008F PTEN<15:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 19/3 16/0 All Resets Bit Range Register Name Virtual Address (BF80_#) Bits F200 DDPCON Legend: PROGRAMMING AND DIAGNOSTICS REGISTER MAP 18/2 17/1 -- -- -- -- 0000 JTAGEN TROEN -- TDOEN 0008 DS60001156H-page 103 PIC32MX5XX/6XX/7XX TABLE 4-39: 0000 0000 Legend: 1: 0000 0000 DATAIN<31:0> 15:0 0000 0000 DATAOUT<31:0> 15:0 31:16 CSF<1:0> 21/5 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-38: Virtual Address (BF88_#) 4010 CHEACC(1) CHETAG(1) 4030 CHEMSK(1) 4040 CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 4080 CHELRU 4090 CHEHIT 40A0 CHEMIS 40C0 CHEPFABT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 CHEWEN -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 LTAGBOOT 15:0 31:16 DCSZ<1:0> -- -- -- -- -- -- -- 31:16 31:16 31:16 31:16 15:0 -- -- -- PREFEN<1:0> -- -- -- -- -- -- -- -- -- -- -- -- CHECOH 0000 PFMWS<2:0> -- -- 0007 -- CHEIDX<3:0> -- -- -- -- -- -- -- -- -- -- 00xx LVALID LLOCK LTYPE -- xxx2 -- -- -- -- -- 0000 -- -- -- -- -- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx CHELRU<24:16> CHELRU<15:0> CHEHIT<31:0> CHEMIS<31:0> CHEPFABT<31:0> 2009-2013 Microchip Technology Inc. Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset value is dependent on DEVCFGx configuration. 1: 2: 0000 0000 LTAG<23:16> CHEW3<31:0> 15:0 15:0 -- -- 16/0 CHEW2<31:0> 15:0 31:16 -- 17/1 CHEW1<31:0> 15:0 15:0 18/2 CHEW0<31:0> 15:0 31:16 19/3 LMASK<15:5> 31:16 15:0 20/4 LTAG<15:4> 15:0 31:16 21/5 All Resets Bit Range Register Name Bits 4000 CHECON(1,2) 4020 PREFETCH REGISTER MAP 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx PIC32MX5XX/6XX/7XX DS60001156H-page 104 TABLE 4-40: Virtual Address (BF80_#) Register Name(1) 0200 RTCCON RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- 15:0 ON 31:16 15:0 -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- ALRMEN CHIME PIV ALRMSYNC 31:16 25/9 24/8 -- -- -- -- -- -- SEC10<3:0> SEC01<3:0> YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> 15:0 SEC10<3:0> -- -- DAY10<3:0> RTSECSEL RTCCLKON -- -- -- 19/3 18/2 17/1 16/0 -- -- DAY01<3:0> 0000 -- -- -- -- RTCWREN RTCSYNC HALFSEC -- MIN10<3:0> -- -- -- RTCOE 0000 -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- MONTH10<3:0> -- -- -- -- -- xxxx -- MONTH01<3:0> MIN10<3:0> -- 0000 MIN01<3:0> MONTH10<3:0> SEC01<3:0> -- 20/4 ARPT<7:0> HR01<3:0> 15:0 -- 21/5 AMASK<3:0> HR10<3:0> 15:0 22/6 CAL<9:0> 31:16 31:16 23/7 All Resets Bits 0210 RTCALRM 0220 RTCC REGISTER MAP Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-41: -- -- xx00 xxxx WDAY01<3:0> xx00 MIN01<3:0> xxxx -- -- -- xx00 MONTH01<3:0> 00xx WDAY01<3:0> xx0x x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX5XX/6XX/7XX DS60001156H-page 105 2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 -- -- -- FCANIO FETHIO FMIIEN -- -- -- -- -- FSRSSEL<2:0> -- -- -- -- FPLLODIV<2:0> xxxx -- FPLLIDIV<2:0> xxxx 31:16 FVBUSONIO FUSBIDIO 15:0 18/2 17/1 16/0 xxxx USERID<15:0> 31:16 -- -- -- -- -- 15:0 UPLLEN -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 FCKSM<1:0> FPBDIV<1:0> -- OSCIOFNC 31:16 -- -- -- -- -- -- -- -- 15:0 -- CP PWP<3:0> -- -- -- -- UPLLIDIV<2:0> -- xxxx -- -- FPLLMUL<2:0> FWDTEN -- -- IESO -- FSOSCEN -- BWP -- -- -- -- -- -- -- -- -- ICESEL -- 23/7 22/6 21/5 20/4 19/3 18/2 POSCMOD<1:0> WDTPS<4:0> -- xxxx FNOSC<2:0> xxxx PWP<7:4> xxxx DEBUG<1:0> xxxx x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Virtual Address (BF80_#) Register Name TABLE 4-43: F220 DEVID DEVICE AND REVISION ID SUMMARY Legend: Note 1: Bit Range Bits 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 VER<3:0> DEVID<27:16> DEVID<15:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. Refer to "PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification" (DS80000480) for more information. 17/1 16/0 All Resets(1) Legend: 31/15 All Resets Bit Range Bits Register Name Virtual Address (BFC0_#) DEVCFG: DEVICE CONFIGURATION WORD SUMMARY xxxx xxxx PIC32MX5XX/6XX/7XX DS60001156H-page 106 TABLE 4-42: 2009-2013 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 5040 U1OTGIR(2) 5050 U1OTGIE 5070 U1OTGCON 5080 U1PWRC U1IR(2) 5200 5210 U1IE U1EIR(2) 5240 U1EIE U1STAT(3) 5250 5260 5270 DS60001156H-page 107 5280 U1CON U1ADDR U1BDTP1 U1FRML Legend: Note 1: 2: 3: 4: (3) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 22/6 21/5 -- -- 20/4 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- IDIF 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- IDIE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- ID -- LSTATE -- SESVD SESEND -- VBUSVD 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 OTGEN VBUSCHG VBUSDIS 0000 -- -- -- 0000 -- 15:0 -- -- -- -- -- -- -- -- DPPULUP -- -- -- -- -- -- -- -- -- -- -- 17/1 ACTVIF -- -- -- SESVDIF SESENDIF -- T1MSECIE LSTATEIE 31:16 18/2 -- T1MSECIF LSTATEIF -- 19/3 -- ACTVIE -- SESVDIE SESENDIE DMPULUP DPPULDWN DMPULDWN VBUSON 15:0 -- -- -- -- -- -- -- -- UACTPND(4) -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- STALLIF 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- STALLIE 31:16 -- -- -- -- -- -- -- -- -- -- USLPGRD USBBUSY ATTACHIF RESUMEIF -- -- ATTACHIE RESUMEIE -- -- -- -- -- -- -- 16/0 -- -- -- -- -- IDLEIF TRNIF SOFIF UERRIF -- -- -- -- IDLEIE TRNIE SOFIE UERRIE -- -- -- -- CRC5EF 0000 VBUSVDIE 0000 USUSPEND USBPWR -- 0000 VBUSVDIF 0000 0000 0000 -- 0000 URSTIF 0000 DETACHIF 0000 -- 0000 URSTIE 0000 DETACHIE 0000 -- 0000 0000 15:0 -- -- -- -- -- -- -- -- BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- DIR PPBI -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 0000 USBEN 0000 ENDPT<3:0>(4) -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- JSTATE -- (4) (4) SE0 -- PKTDIS TOKBUSY -- -- -- -- -- -- LSPDEN -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- PPBRST -- -- -- -- -- -- -- EOFEE RESUME -- -- CRC5EE HOSTEN -- 15:0 -- USBRST -- 31:16 31:16 -- EOFEF PIDEF -- PIDEE 0000 0000 -- -- 0000 -- -- -- 0000 -- 0000 -- -- -- 0000 0000 BDTPTRL<7:1> FRML<7:0> 0000 SOFEN DEVADDR<6:0> -- 0000 0000 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX5XX/6XX/7XX 5230 23/7 All Resets Bits 5060 U1OTGSTAT(3) 5220 USB REGISTER MAP Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-44: Virtual Address (BF88_#) Register Name(1) 5290 U1FRMH(3) U1TOK 52B0 52D0 52E0 U1SOF U1BDTP2 U1BDTP3 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 2009-2013 Microchip Technology Inc. 5370 U1EP7 5380 U1EP8 5390 U1EP9 53A0 U1EP10 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 17/1 16/0 -- -- 0000 -- -- 0000 -- -- -- 0000 -- -- -- 0000 -- -- -- 0000 -- 0000 FRMH<2:0> PID<3:0> 0000 EP<3:0> 0000 CNT<7:0> 0000 BDTPTRH<7:0> -- All Resets Bit Range Bits 52A0 52C0 USB REGISTER MAP (CONTINUED) -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BDTPTRU<7:0> 0000 15:0 -- -- -- -- -- -- -- -- UTEYE UOEMON -- USBSIDL -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UASUSPND 0001 -- 15:0 -- -- -- -- -- -- -- -- LSPD RETRYDIS -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX5XX/6XX/7XX DS60001156H-page 108 TABLE 4-44: Virtual Address (BF88_#) Register Name(1) 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 USB REGISTER MAP (CONTINUED) 53E0 U1EP14 53F0 U1EP15 Legend: Note 1: 2: 3: 4: 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-44: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX5XX/6XX/7XX DS60001156H-page 109 Virtual Address (BF88_#) Register Name(1) B000 C1CON C1CFG B020 C1INT B030 B050 B060 C1VEC C1TREC C1FSTAT C1RXOVF B070 C1TMR B080 C1RXM0 B090 B0A0 2009-2013 Microchip Technology Inc. B0B0 C1RXM1 C1RXM2 C1RXM3 B0C0 C1FLTCON0 B0D0 C1FLTCON1 B0E0 C1FLTCON2 B0F0 C1FLTCON3 Legend: Note 1: 31/15 30/14 31:16 -- 15:0 ON 31:16 -- 15:0 SEG2PHTS 29/13 28/12 -- -- -- ABAT -- SIDLE -- CANBUSY -- -- -- -- -- -- SAM 27/11 26/10 25/9 24/8 23/7 -- -- -- -- -- -- -- -- WAKFIL -- -- -- REQOP<2:0> SEG1PH<2:0> 22/6 21/5 OPMOD<2:0> PRSEG<2:0> 20/4 19/3 CANCAP -- 18/2 17/1 16/0 -- -- -- DNCNT<4:0> SJW<1:0> All Resets Bit Range Bits B010 B040 CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 0480 0000 SEG2PH<2:0> 0000 BRP<5:0> 0000 31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE -- -- -- -- -- -- -- MODIE CTMRIE RBIE TBIE 15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF -- -- -- -- -- -- -- MODIF CTMRIF RBIF TBIF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- TXBO TXBP FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 15:0 FILHIT<4:0> -- ICODE<6:0> TERRCNT<7:0> 0040 TXWARN RXWARN EWARN 0000 RERRCNT<7:0> 31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 15:0 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP15 RXBP FIFOIP8 0000 0000 FIFOIP1 FIFOIP0 0000 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF8 RXOVF7 31:16 RXOVF9 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 CANTS<15:0> 15:0 0000 CANTSPRE<15:0> 31:16 0000 SID<10:0> 15:0 --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> xxxx EID<15:0> 31:16 xxxx SID<10:0> 15:0 EID<15:0> 31:16 xxxx SID<10:0> 15:0 EID<15:0> 31:16 xxxx SID<10:0> 15:0 EID<15:0> xxxx 31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000 15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000 31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000 15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000 31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000 15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000 15:0 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000 FLTEN13 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX5XX/6XX/7XX DS60001156H-page 110 TABLE 4-45: Virtual Address (BF88_#) B100 C1FLTCON4 B110 C1FLTCON5 B120 C1FLTCON6 B130 C1FLTCON7 B140 B340 CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) C1RXFn (n = 0-31) C1FIFOBA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-45: 31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0> 0000 31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000 15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000 31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000 15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000 31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000 15:0 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> FLTEN29 31:16 SID<10:0> --- 15:0 EXID -- 0000 EID<17:16> EID<15:0> 31:16 xxxx 0000 C1FIFOBA<31:0> 15:0 xxxx 0000 C1FIFOCONn 31:16 B350 (n = 0-31) 15:0 -- -- -- -- -- -- -- -- -- -- -- -- FRESET UINC DONLY -- -- -- -- TXEN TXABAT TXLARB TXERR 31:16 -- -- -- -- -- TXNFULLIE TXHALFIE TXEMPTYIE -- -- -- -- RXOVFLIE RXFULLIE RXHALFIE RXN 0000 EMPTYIE 15:0 -- -- -- -- -- TXNFULLIF TXHALFIF TXEMPTYIF -- -- -- -- RXOVFLIF RXFULLIF RXHALFIF RXN 0000 EMPTYIF C1FIFOINTn (n = 0-31) B370 C1FIFOUAn 31:16 (n = 0-31) 15:0 B380 C1FIFOCIn 31:16 (n = 0-31) 15:0 Legend: Note 1: TXREQ RTREN 0000 TXPRI<1:0> 0000 0000 C1FIFOUA<31:0> 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C1FIFOCI<4:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 0000 0000 DS60001156H-page 111 PIC32MX5XX/6XX/7XX B360 FSIZE<4:0> Virtual Address (BF88_#) Register Name(1) C000 C2CON C010 C2CFG C020 C030 C040 C050 C060 C070 C2INT C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C2RXM0 C0A0 C2RXM1 2009-2013 Microchip Technology Inc. C0B0 C2RXM2 C2RXM3 C0C0 C2FLTCON0 C0D0 C2FLTCON1 C0E0 C2FLTCON2 C0F0 C2FLTCON3 Legend: Note 1: 31/15 30/14 31:16 -- 15:0 ON 31:16 -- 15:0 SEG2PHTS 29/13 28/12 -- -- -- ABAT -- SIDLE -- CANBUSY -- -- -- -- -- -- SAM 27/11 26/10 25/9 24/8 23/7 -- -- -- -- -- -- -- -- WAKFIL -- REQOP<2:0> SEG1PH<2:0> 22/6 21/5 OPMOD<2:0> PRSEG<2:0> 20/4 19/3 CANCAP -- 18/2 17/1 16/0 -- -- -- DNCNT<4:0> -- SJW<1:0> -- All Resets Bit Range Bits C080 C0B0 CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 0480 0000 SEG2PH<2:0> 0000 BRP<5:0> 0000 31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE -- -- -- -- -- -- -- MODIE CTMRIE RBIE TBIE 0000 0000 15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF -- -- -- -- -- -- -- MODIF CTMRIF RBIF TBIF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- 31:16 -- -- -- 15:0 FILHIT<4:0> -- -- -- -- -- -- -- ICODE<6:0> -- TXBO TERRCNT<7:0> RXBP TXWARN RXWARN EWARN RERRCNT<7:0> 31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 15:0 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP15 TXBP FIFOIP24 FIFOIP8 0000 0040 0000 0000 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF8 RXOVF7 31:16 RXOVF9 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 CANTS<15:0> 15:0 0000 CANTSPRE<15:0> 31:16 0000 SID<10:0> 15:0 --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> xxxx --- MIDE -- EID<17:16> xxxx EID<15:0> 31:16 xxxx SID<10:0> 15:0 EID<15:0> 31:16 xxxx SID<10:0> 15:0 EID<15:0> 31:16 xxxx SID<10:0> 15:0 0000 EID<15:0> xxxx 31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000 15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000 31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000 15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000 31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000 15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000 15:0 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000 FLTEN13 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX5XX/6XX/7XX DS60001156H-page 112 TABLE 4-46: Virtual Address (BF88_#) C100 C2FLTCON4 C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C140 C340 CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) C2RXFn (n = 0-31) C2FIFOBA C2FIFOINTn (n = 0-31) 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000 31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000 15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000 31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000 15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000 31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000 15:0 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> FLTEN29 31:16 --- SID<10:0> 15:0 EXID -- 0000 EID<17:16> EID<15:0> 31:16 xxxx xxxx 0000 C2FIFOBA<31:0> 15:0 0000 -- -- -- -- -- -- -- -- -- -- -- -- FRESET UINC DONLY -- -- -- -- TXEN TXABAT TXLARB FSIZE<4:0> TXERR TXREQ RTREN 0000 TXPRI<1:0> 0000 -- -- -- -- -- TXNFULLIE TXHALFIE TXEMPTYIE -- -- -- -- 15:0 -- -- -- -- -- TXNFULLIF TXHALFIF TXEMPTYIF -- -- -- -- RXOVFLIF RXFULLIF RXHALFIF C2FIFOUAn 31:16 (n = 0-31) 15:0 C380 C2FIFOCIn 31:16 (n = 0-31) 15:0 RXN 0000 EMPTYIF 0000 C2FIFOUA<31:0> 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C2FIFOCI<4:0> x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 0000 0000 DS60001156H-page 113 PIC32MX5XX/6XX/7XX 31:16 RXN 0000 RXOVFLIE RXFULLIE RXHALFIE EMPTYIE C370 Legend: Note 1: 30/14 31:16 FLTEN19 C2FIFOCONn 31:16 C350 (n = 0-31) 15:0 C360 31/15 All Resets Bit Range Bits Register Name(1) 2009-2013 Microchip Technology Inc. TABLE 4-46: Virtual Address (BF88_#) Register Name(1) 9000 ETHCON1 9010 ETHCON2 9020 9030 9040 9050 9060 9070 9080 9090 90A0 ETHTXST ETHRXST ETHHT0 ETHHT1 ETHPMM0 ETHPMM1 ETHPMCS ETHPMO ETHRXFC 2009-2013 Microchip Technology Inc. 90D0 ETHIEN ETHIRQ Legend: Note 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 15:0 ON -- SIDL -- -- -- TXRTS RXEN 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- 31:16 21/5 20/4 19/3 18/2 17/1 AUTOFC -- -- MANFC -- -- -- 16/0 -- -- -- -- -- -- -- -- 0000 -- -- -- -- 0000 -- -- -- -- 0000 RXBUFSZ<6:0> BUFCDEC 0000 TXSTADDR<31:16> 15:0 0000 TXSTADDR<15:2> 31:16 RXSTADDR<31:16> 15:0 31:16 0000 0000 HT<63:32> 15:0 31:16 0000 0000 PMM<31:0> 15:0 31:16 0000 0000 PMM<63:32> 15:0 -- -- -- -- -- -- -- 15:0 -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CRC ERREN CRC OKEN RUNT ERREN RUNTEN UCEN NOT MEEN MCEN BCEN 0000 PMCS<15:0> -- -- -- -- -- -- -- 15:0 -- -- -- -- -- 0000 0000 31:16 -- -- -- -- 15:0 HTEN MPEN -- NOTPM 31:16 -- -- -- -- -- -- -- -- RXFWM<7:0> 15:0 -- -- -- -- -- -- -- -- RXEWM<7:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- RX BUSEIE FW MARKIE RX DONEIE PK TPENDIE PMMODE<3:0> 0000 0000 PMO<15:0> -- 0000 0000 HT<31:0> 15:0 0000 0000 RXSTADDR<15:2> 31:16 31:16 22/6 PTV<15:0> 31:16 31:16 23/7 All Resets Bit Range Bits 90B0 ETHRXWM 90C0 ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 0000 0000 -- -- -- -- RX ACTIE -- TX DONEIE TX ABORTIE RX BUFNAIE 15:0 -- TX BUSEIE -- -- -- EW MARKIE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- TXBUSE RXBUSE -- -- -- EWMARK FWMARK RXDONE PKTPEND RXACT -- TXDONE TXABORT RXBUFNA -- 0000 RX 0000 OVFLWIE -- 0000 RXOVFLW 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 1: 2: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values default to the factory programmed value. PIC32MX5XX/6XX/7XX DS60001156H-page 114 TABLE 4-47: Virtual Address (BF88_#) Register Name(1) 90E0 ETHSTAT ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 ETH 9100 RXOVFLOW 15:0 -- -- -- -- -- -- -- 9110 31:16 ETH FRMTXOK 15:0 -- 9120 31:16 ETH SCOLFRM 15:0 -- 9130 31:16 ETH MCOLFRM 15:0 -- 9140 31:16 ETH FRMRXOK 15:0 -- 31:16 -- 9150 9160 21/5 20/4 -- BUSY TXBUSY RXBUSY -- -- -- -- -- -- -- 17/1 16/0 -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXPAUSE PASSALL -- -- BUFCNT<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- 31:16 -- -- 15:0 SOFT RESET SIM RESET 31:16 -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RESET RMCS RESET RFUN RESET TMCS RESET TFUN -- -- -- -- -- -- -- -- -- -- -- -- -- EXCESS DFR BP NOBKOFF NOBKOFF -- -- LONGPRE PUREPRE AUTOPAD VLANPAD PAD ENABLE CRC ENABLE -- -- -- DS60001156H-page 115 9220 EMAC1 IPGT 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- 9230 EMAC1 IPGR 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- 9240 EMAC1 CLRT 31:16 -- -- 15:0 -- -- 9250 EMAC1 MAXF 31:16 -- -- NB2BIPKTGP1<6:0> -- -- -- -- -- CWINDOW<5:0> -- -- -- LOOPBACK TXPAUSE -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 RXENABLE 800D -- 0000 DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082 -- -- -- -- -- -- -- -- -- -- -- -- 0000 0C12 RETX<3:0> -- 0000 0012 NB2BIPKTGP2<6:0> -- MACMAXF<15:0> -- B2BIPKTGP<6:0> -- -- 0000 0000 -- EMAC1 CFG2 0000 0000 ALGNERRCNT<15:0> -- 0000 0000 FCSERRCNT<15:0> -- 0000 0000 FRMRXOKCNT<15:0> -- 0000 0000 MCOLFRMCNT<15:0> -- 0000 0000 SCOLFRMCNT<15:0> 9210 Note 18/2 FRMTXOKCNT<15:0> -- Legend: 19/3 RXOVFLWCNT<15:0> 31:16 ETH ALGNERR 15:0 EMAC1 CFG1 22/6 -- -- 0000 370F -- 0000 05EE x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 1: 2: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values default to the factory programmed value. PIC32MX5XX/6XX/7XX 9200 ETH FCSERR 23/7 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc. TABLE 4-47: Register Name(1) 2009-2013 Microchip Technology Inc. Virtual Address (BF88_#) ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 9260 EMAC1 SUPP 9270 EMAC1 TEST 9280 EMAC1 MCFG 9290 EMAC1 MCMD 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCAN READ 0000 92A0 EMAC1 MADR 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- 92B0 EMAC1 MWTD 31:16 -- -- -- -- -- -- -- -- -- -- -- 92C0 EMAC1 MRDD 31:16 -- -- -- -- -- -- -- 92D0 EMAC1 MIND 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- LINKFAIL NOTVALID SCAN 9300 EMAC1 SA0(2) 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9310 EMAC1 SA1(2) 31:16 -- -- -- 9320 EMAC1 SA2(2) 31:16 -- -- -- Legend: Note 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 -- -- -- 15:0 -- -- -- -- -- -- -- RESET RMII -- 31:16 -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- 15:0 RESET MGMT -- -- -- -- -- -- 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- 0000 -- SPEED RMII -- -- -- -- -- -- -- -- 1000 -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- TESTBP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PHYADDR<4:0> -- -- -- -- 15:0 -- -- -- -- -- -- 15:0 CLKSEL<3:0> -- NOPRE -- -- -- REGADDR<4:0> 0100 -- -- 15:0 -- -- -- -- -- -- -- STNADDR4<7:0> -- -- -- -- -- -- -- -- STNADDR2<7:0> -- -- -- -- -- -- STNADDR1<7:0> 0000 MIIMBUSY 0000 xxxx xxxx STNADDR3<7:0> -- 0000 0000 STNADDR5<7:0> -- 0000 0000 STNADDR6<7:0> -- 0000 SCANINC 0020 MRDD<15:0> 15:0 15:0 -- TESTPAUSE SHRTQNTA 0000 MWTD<15:0> -- All Resets Bit Range Bits xxxx xxxx xxxx xxxx x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 1: 2: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values default to the factory programmed value. PIC32MX5XX/6XX/7XX DS60001156H-page 116 TABLE 4-47: PIC32MX5XX/6XX/7XX 4.2 Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code. REGISTER 4-1: Bit Range BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- -- BMX ERRIXI BMX ERRICD BMX ERRDMA BMX ERRDS BMX ERRIS U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 -- BMX WSDRM -- -- -- 31:24 23:16 15:8 7:0 BMXARB<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-21 Unimplemented: Read as `0' bit 20 BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD bit 18 BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access bit 15-7 Unimplemented: Read as `0' bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup bit 5-3 Unimplemented: Read as `0' bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111 = Reserved (using these Configuration modes will produce undefined behavior) * * * 011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 (default) 000 = Arbitration Mode 0 2009-2013 Microchip Technology Inc. DS60001156H-page 117 PIC32MX5XX/6XX/7XX REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 R-0 BMXDKPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM bit 9-0 BMXDKPBA<9:0>: DRM Kernel Program Base Address Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: DS60001156H-page 118 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 4-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUDBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM, the value must be greater than BMXDKPBA. bit 9-0 BMXDUDBA<9:0>: DRM User Data Base Address Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: 2009-2013 Microchip Technology Inc. DS60001156H-page 119 PIC32MX5XX/6XX/7XX REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 R-0 BMXDUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM, BMXDUPBA must be greater than BMXDUDBA. bit 9-0 BMXDUPBA<9:0>: DRM User Program Base Address Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: DS60001156H-page 120 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 4-5: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R R R R BMXDRMSZ<23:16> R R R R R BMXDRMSZ<15:8> R 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER R R R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: 0x00004000 = device has 16 KB RAM 0x00008000 = device has 32 KB RAM 0x00010000 = device has 64 KB RAM REGISTER 4-6: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER(1,2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 BMXPUPBA<19:16> R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXPUPBA<15:8> R-0 R-0 BMXPUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as `0' bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits bit 10-0 BMXPUPBA<10:0>: Program Flash (PFM) User Program Base Address Read-Only bits Value is always `0', which forces 2 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXPFMSZ. 2: 2009-2013 Microchip Technology Inc. DS60001156H-page 121 PIC32MX5XX/6XX/7XX REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R BMXPFMSZ<23:16> R R R R R R R R BMXPFMSZ<15:8> R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00010000 = device has 64 KB Flash 0x00020000 = device has 128 KB Flash 0x00040000 = device has 256 KB Flash 0x00080000 = device has 512 KB Flash REGISTER 4-8: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXBOOTSZ<31:24> R R R R R BMXBOOTSZ<23:16> R R R R R BMXBOOTSZ<15:8> R R R R R BMXBOOTSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00003000 = device has 12 KB boot Flash DS60001156H-page 122 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Program Memory" (DS60001121) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX5XX/6XX/7XX devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: * Run-Time Self-Programming (RTSP) * EJTAG Programming * In-Circuit Serial ProgrammingTM (ICSPTM) RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. "Flash Program Memory" (DS60001121) in the "PIC32 Family Reference Manual". EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. The EJTAG and ICSP methods are described in the "PIC32 Flash Programming Specification" (DS60001145), which can be downloaded from the Microchip web site. Note: 2009-2013 Microchip Technology Inc. For PIC32MX5XX/6XX/7XX devices, the Flash page size is 4 KB and the row size is 512 bytes (1024 IW and 128 IW, respectively). DS60001156H-page 123 PIC32MX5XX/6XX/7XX 5.1 Control Registers REGISTER 5-1: Bit Range NVMCON: PROGRAMMING CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 -- -- -- -- R/W-0, HC R/W-0 R-0, HS R-0, HS WR WREN U-0 U-0 U-0 U-0 -- -- -- -- Legend: R = Readable bit -n = Value at POR -- R-0, HSC (1) WRERR(1) LVDERR(1) LVDSTAT R/W-0 U = Unimplemented bit, read as `0' W = Writable bit HS = Set by hardware `1' = Bit is set `0' = Bit is cleared -- -- -- U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 NVMOP<3:0> HSC = Set and Cleared by hardware HC = Cleared by hardware x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 WR: Write Control bit This bit is writable when WREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes 0 = Flash operation complete or inactive bit 14 WREN: Write Enable bit 1 = Enable writes to WR bit and enables LVD circuit 0 = Disable writes to WR bit and disables LVD circuit bit 13 bit 12 bit 11 bit 10-4 bit 3-0 Note: This is the only bit in this register that is reset by a device Reset. WRERR: Write Error bit(1) This bit is read-only and is automatically set by hardware. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set by hardware. 1 = Low-voltage detected (possible data corruption, if WRERR is set) 0 = Voltage level is acceptable for programming LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set, and cleared, by hardware. 1 = Low-voltage event is active 0 = Low-voltage event is not active Unimplemented: Read as `0' NVMOP<3:0>: NVM Operation bits These bits are writable when WREN = 0. 1111 = Reserved * * * 0111 = Reserved 0110 = No operation 0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR). DS60001156H-page 124 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: NVMKEY<31:0>: Unlock Register bits These bits are write-only, and read as `0' on any read. This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. REGISTER 5-3: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown NVMADDR: FLASH ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<15:8> R/W-0 NVMADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown NVMADDR<31:0>: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored. Page Erase: Address identifies the page to erase. Row Program: Address identifies the row to program. Word Program: Address identifies the word to program. 2009-2013 Microchip Technology Inc. DS60001156H-page 125 PIC32MX5XX/6XX/7XX REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: NVMDATA<31:0>: Flash Programming Data bits The bits in this register are only reset by a Power-on Reset (POR). REGISTER 5-5: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<23:16> R/W-0 R/W-0 NVMSRCADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown NVMSRCADDR<31:0>: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming. DS60001156H-page 126 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS60001118) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 6-1: The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * Power-on Reset (POR) Master Clear Reset pin (MCLR) Software Reset (SWR) Watchdog Timer Reset (WDTR) Brown-out Reset (BOR) Configuration Mismatch Reset (CMR) A simplified block diagram of the Reset module is illustrated in Figure 6-1. SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle MCLR WDTR WDT Time-out Voltage Regulator Enabled Power-up Timer POR Brown-out Reset BOR SYSRST VDD VDD Rise Detect Configuration Mismatch Reset Software Reset 2009-2013 Microchip Technology Inc. CMR SWR DS60001156H-page 127 PIC32MX5XX/6XX/7XX 6.1 Control Registers REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 -- -- -- -- -- -- CMR VREGS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR -- WDTO SLEEP IDLE R/W-1, HS (1) R/W-1, HS (1) BOR Legend: HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared POR x = Bit is unknown bit 31-10 Unimplemented: Read as `0' bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during Sleep mode 0 = Regulator is disabled and is off during Sleep mode bit 7 EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset was not executed bit 5 Unimplemented: Read as `0' bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred bit 3 SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode bit 2 IDLE: Wake From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred Note 1: User software must clear this bit to view the next detection. DS60001156H-page 128 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC -- -- -- -- -- -- -- SWRST(1) Legend: HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-1 Unimplemented: Read as `0' bit 0 SWRST: Software Reset Trigger bit(1) 1 = Enable software Reset event 0 = No effect Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2009-2013 Microchip Technology Inc. DS60001156H-page 129 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 130 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupts" (DS60001108) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX5XX/6XX/7XX devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. FIGURE 7-1: The Interrupt Controller module includes the following features: * * * * * * * * * * * Up to 96 interrupt sources Up to 64 interrupt vectors Single and multi-vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Dedicated shadow set for user-selectable priority level Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing A simplified block diagram of the Interrupt Controller module is illustrated in Figure 7-1. INTERRUPT CONTROLLER MODULE Vector Number Interrupt Requests Interrupt Controller Priority Level CPU Core Shadow Set Number 2009-2013 Microchip Technology Inc. DS60001156H-page 131 PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority IEC0<0> IPC0<4:2> Sub-Priority Highest Natural Order Priority CT - Core Timer Interrupt 0 0 IFS0<0> IPC0<1:0> CS0 - Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 - Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 - External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> T1 - Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> IC1 - Input Capture 1 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> OC1 - Output Compare 1 6 6 IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16> INT1 - External Interrupt 1 7 7 IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24> T2 - Timer2 8 8 IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0> IC2 - Input Capture 2 9 9 IFS0<9> IEC0<9> IPC2<12:10> IPC2<9:8> OC2 - Output Compare 2 10 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16> INT2 - External Interrupt 2 11 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24> T3 - Timer3 12 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0> IC3 - Input Capture 3 13 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8> OC3 - Output Compare 3 14 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16> INT3 - External Interrupt 3 15 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24> T4 - Timer4 16 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0> IC4 - Input Capture 4 17 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8> OC4 - Output Compare 4 18 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16> INT4 - External Interrupt 4 19 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24> T5 - Timer5 20 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0> IC5 - Input Capture 5 21 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8> OC5 - Output Compare 5 22 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16> SPI1E - SPI1 Fault 23 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24> SPI1RX - SPI1 Receive Done 24 23 IFS0<24> IEC0<24> IPC5<28:26> IPC5<25:24> SPI1TX - SPI1 Transfer Done 25 23 IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24> 26 24 IFS0<26> IEC0<26> IPC6<4:2> IPC6<1:0> 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0> 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0> U1E - UART1 Error SPI3E - SPI3 Fault I2C3B - I2C3 Bus Collision Event U1RX - UART1 Receiver SPI3RX - SPI3 Receive Done I2C3S - I2C3 Slave Event U1TX - UART1 Transmitter SPI3TX - SPI3 Transfer Done I2C3M - I2C3 Master Event I2C1B - I2C1 Bus Collision Event 29 25 IFS0<29> IEC0<29> IPC6<12:10> IPC6<9:8> I2C1S - I2C1 Slave Event 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> I2C1M - I2C1 Master Event 31 25 IFS0<31> IEC0<31> IPC6<12:10> IPC6<9:8> CN - Input Change Interrupt 32 26 IFS1<0> IEC1<0> IPC6<20:18> IPC6<17:16> Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32 USB and CAN - Features", TABLE 2: "PIC32 USB and Ethernet - Features" and TABLE 3: "PIC32 USB, Ethernet and CAN - Features" for the list of available peripherals. DS60001156H-page 132 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority AD1 - ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24> PMP - Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 - Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 - Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> U3E - UART2A Error SPI2E - SPI2 Fault I2C4B - I2C4 Bus Collision Event 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24> U3RX - UART2A Receiver SPI2RX - SPI2 Receive Done I2C4S - I2C4 Slave Event 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> U3TX - UART2A Transmitter SPI2TX - SPI2 Transfer Done IC4M - I2C4 Master Event 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> U2E - UART3A Error SPI4E - SPI4 Fault I2C5B - I2C5 Bus Collision Event 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> U2RX - UART3A Receiver SPI4RX - SPI4 Receive Done I2C5S - I2C5 Slave Event 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> U2TX - UART3A Transmitter SPI4TX - SPI4 Transfer Done IC5M - I2C5 Master Event 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> I2C2B - I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8> I2C2S - I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> I2C2M - I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> FSCM - Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16> RTCC - Real-Time Clock and Calendar 47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24> DMA0 - DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0> DMA1 - DMA Channel 1 49 37 IFS1<17> IEC1<17> IPC9<12:10> IPC9<9:8> DMA2 - DMA Channel 2 50 38 IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16> DMA3 - DMA Channel 3 51 39 IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24> DMA4 - DMA Channel 4 52 40 IFS1<20> IEC1<20> IPC10<4:2> IPC10<1:0> DMA5 - DMA Channel 5 53 41 IFS1<21> IEC1<21> IPC10<12:10> IPC10<9:8> DMA6 - DMA Channel 6 54 42 IFS1<22> IEC1<22> IPC10<20:18> IPC10<17:16> DMA7 - DMA Channel 7 55 43 IFS1<23> IEC1<23> IPC10<28:26> IPC10<25:24> FCE - Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> USB - USB Interrupt 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8> CAN1 - Control Area Network 1 58 46 IFS1<26> IEC1<26> IPC11<20:18> IPC11<17:16> CAN2 - Control Area Network 2 59 47 IFS1<27> IEC1<27> IPC11<28:26> IPC11<25:24> ETH - Ethernet Interrupt 60 48 IFS1<28> IEC1<28> IPC12<4:2> IPC12<1:0> IC1E - Input Capture 1 Error 61 5 IFS1<29> IEC1<29> IPC1<12:10> IPC1<9:8> IC2E - Input Capture 2 Error 62 9 IFS1<30> IEC1<30> IPC2<12:10> IPC2<9:8> Note 1: IPC11<1:0> Not all interrupt sources are available on all devices. See TABLE 1: "PIC32 USB and CAN - Features", TABLE 2: "PIC32 USB and Ethernet - Features" and TABLE 3: "PIC32 USB, Ethernet and CAN - Features" for the list of available peripherals. 2009-2013 Microchip Technology Inc. DS60001156H-page 133 PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority IC3E - Input Capture 3 Error 63 13 IFS1<31> IEC1<31> IPC3<12:10> IPC3<9:8> IC4E - Input Capture 4 Error 64 17 IFS2<0> IEC2<0> IPC4<12:10> IPC4<9:8> IC4E - Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8> PMPE - Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1:0> U4E - UART4 Error 67 49 IFS2<3> IEC2<3> IPC12<12:10> IPC12<9:8> U4RX - UART4 Receiver 68 49 IFS2<4> IEC2<4> IPC12<12:10> IPC12<9:8> U4TX - UART4 Transmitter 69 49 IFS2<5> IEC2<5> IPC12<12:10> IPC12<9:8> U6E - UART6 Error 70 50 IFS2<6> IEC2<6> IPC12<20:18> IPC12<17:16> U6RX - UART6 Receiver 71 50 IFS2<7> IEC2<7> IPC12<20:18> IPC12<17:16> U6TX - UART6 Transmitter 72 50 IFS2<8> IEC2<8> IPC12<20:18> IPC12<17:16> U5E - UART5 Error 73 51 IFS2<9> IEC2<9> IPC12<28:26> IPC12<25:24> U5RX - UART5 Receiver 74 51 IFS2<10> IEC2<10> IPC12<28:26> IPC12<25:24> U5TX - UART5 Transmitter 75 51 IFS2<11> IEC2<11> IPC12<28:26> IPC12<25:24> (Reserved) -- -- -- -- -- -- Lowest Natural Order Priority Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32 USB and CAN - Features", TABLE 2: "PIC32 USB and Ethernet - Features" and TABLE 3: "PIC32 USB, Ethernet and CAN - Features" for the list of available peripherals. DS60001156H-page 134 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 7.1 Control Registers REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SS0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- MVEC -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set TPC<2:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-17 Unimplemented: Read as `0' bit 16 SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow register set 0 = Single vector is not presented with a shadow register set bit 15-13 Unimplemented: Read as `0' bit 12 MVEC: Multiple Vector Configuration bit 1 = Interrupt controller configured for Multi-vector mode 0 = Interrupt controller configured for Single-vector mode bit 11 bit 10-8 bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as `0' TPC<2:0>: Interrupt Proximity Timer Control bits 111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer 110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer 101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer 100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer 011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer 010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer 001 = Interrupts of group priority 1 start the Interrupt Proximity timer 000 = Disables Interrupt Proximity timer Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge 2009-2013 Microchip Technology Inc. DS60001156H-page 135 PIC32MX5XX/6XX/7XX REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- Legend: R = Readable bit -n = Value at POR RIPL<2:0>(1) R/W-0 R/W-0 R/W-0 VEC<5:0>(1) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as `0' bit 10-8 RIPL<2:0>: Requested Priority Level bits(1) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-6 Unimplemented: Read as `0' bit 5-0 VEC<5:0>: Interrupt Vector bits(1) 11111-00000 = The interrupt vector that is presented to the CPU Note 1: This value should only be used when the interrupt controller is configured for Single-vector mode. REGISTER 7-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<15:8> R/W-0 TPTMR<7:0> Legend: R = Readable bit -n = Value at POR bit 31-0 TPTMR: TEMPORAL PROXIMITY TIMER REGISTER W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TPTMR<31:0>: Temporal Proximity Timer Reload bits Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by an interrupt event. DS60001156H-page 136 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 R/W-0 IFS31 IFS30 IFS29 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 Note: 31:24 23:16 15:8 7:0 Note: Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS14 IFS13 IFS12 IFS11 IFS10 IFS09 IFS08 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IFS31-IFS00: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = Interrupt request has not occurred This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit definitions. Bit 31/23/15/7 IECx: INTERRUPT ENABLE CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC09 IEC08 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC07 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 IEC00 Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 25/17/9/1 R/W-0 REGISTER 7-5: Bit Range Bit 26/18/10/2 IFS15 Legend: R = Readable bit -n = Value at POR bit 31-0 Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IEC31-IEC00: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit definitions. 2009-2013 Microchip Technology Inc. DS60001156H-page 137 PIC32MX5XX/6XX/7XX REGISTER 7-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 31:24 23:16 15:8 7:0 -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit `1' = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP03<2:0> R/W-0 R/W-0 IS03<1:0> R/W-0 R/W-0 R/W-0 R/W-0 IP02<2:0> R/W-0 R/W-0 IS02<1:0> IP01<2:0> R/W-0 R/W-0 IP00<2:0> R/W-0 R/W-0 IS01<1:0> R/W-0 R/W-0 R/W-0 IS00<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as `0' bit 28-26 IP03<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS03<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpiority is 0 bit 23-21 Unimplemented: Read as `0' bit 20-18 IP02<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS02<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as `0' Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. DS60001156H-page 138 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) bit 12-10 IP01<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * bit 9-8 bit 7-5 bit 4-2 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS01<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' IP00<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * bit 1-0 Note: 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS00<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. 2009-2013 Microchip Technology Inc. DS60001156H-page 139 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 140 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 8.0 OSCILLATOR CONFIGURATION The Oscillator module has the following features: * A total of four external and internal oscillator options as clock sources * On-chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources * On-chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 8-1: * Dedicated On-Chip PLL for USB peripheral Figure 8-1shows the Oscillator module block diagram. OSCILLATOR BLOCK DIAGRAM USB PLL UFIN div x 4 MHz FIN 5 MHz XTPLL, HSPLL, FIN ECPLL, FRCPLL div x div y PLL RP(1) Enable RS(1) C2(3) PLL Input Divider FPLLIDIV<2:0> OSC2(4) FRC Oscillator 8 MHz typical UFRCEN UPLLEN XT, HS, EC RF(2) XTAL div 2 UFIN 4 MHz UPLLIDIV<2:0> Primary Oscillator To Internal (POSC) Logic OSC1 C1(3) USB Clock (48 MHz) PLL x24 COSC<2:0> PLL Output Divider PLLODIV<2:0> PLL Multiplier PLLMULT<2:0> div 16 TUN<5:0> Postscaler Postscaler Peripherals div x PBCLK PBDIV<1:0> FRC FRC/16 FRCDIV CPU and Select Peripherals SYSCLK FRCDIV<2:0> LPRC LPRC Oscillator 31.25 kHz typical Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSCEN and FSOSCEN SOSCI Notes: 1. 2. 3. 4. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP, with a value of 1 M The internal feedback resistor, RF, is typically in the range of 2 to 10 M Refer to the "PIC32 Family Reference Manual" Section 6. "Oscillator Configuration" (DS60001112) for help determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. 2009-2013 Microchip Technology Inc. SOSC Clock Control Logic Fail-Safe Clock Monitor FSCM INT FSCM Event NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC DS60001156H-page 141 PIC32MX5XX/6XX/7XX 8.1 Control Registers REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 R/W-y -- -- U-0 -- U-0 R-0 R/W-y R-0 Bit 26/18/10/2 R/W-y R/W-0 PLLODIV<2:0> R-1 SOSCRDY PBDIVRDY -- Bit Bit 28/20/12/4 27/19/11/3 R-0 R/W-y R-0 Bit 24/16/8/0 R/W-0 R/W-1 FRCDIV<2:0> R/W-y R/W-y PBDIV<1:0> COSC<2:0> Bit 25/17/9/1 U-0 R/W-y R/W-y PLLMULT<2:0> R/W-y -- R/W-y R/W-y NOSC<2:0> R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0 CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN Legend: R = Readable bit -n = Value at POR y = Value set from Configuration bits on POR W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-27 PLLODIV<2:0>: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 bit 23 Unimplemented: Read as `0' bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary Oscillator is still warming up or is turned off bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit 1 = PBDIV<1:0> bits can be written 0 = PBDIV<1:0> bits cannot be written bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits 11 = PBCLK is SYSCLK divided by 8 (default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note: Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001156H-page 142 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as `0' bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC (FRC) Oscillator divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast RC (FRC) Oscillator bit 11 Unimplemented: Read as `0' bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC Oscillator (FRC) divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast Internal RC Oscillator (FRC) bit 7 bit 6 bit 5 bit 4 bit 3 Note: On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If clock switching and monitoring is disabled (FCKSM<1:0> = 1x): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified If clock switching and monitoring is enabled (FCKSM<1:0> = 0x): Clock and PLL selections are never locked and may be modified. ULOCK: USB PLL Lock Status bit 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2009-2013 Microchip Technology Inc. DS60001156H-page 143 PIC32MX5XX/6XX/7XX REGISTER 8-1: bit 2 bit 1 bit 0 Note: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) UFRCEN: USB FRC Clock Enable bit 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001156H-page 144 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- R/W-0 (1) TUN<5:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 100000 = Center frequency -12.5% 100001 = * * * 111111 = 000000 = Center frequency; Oscillator runs at minimal frequency (8 MHz) 000001 = * * * 011110 = 011111 = Center frequency +12.5% x = Bit is unknown Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested. Note: Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2009-2013 Microchip Technology Inc. DS60001156H-page 145 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 146 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 9.0 PREFETCH CACHE Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. "Prefetch Cache" (DS60001119) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 9.1 * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 9-1: * * * * 16 fully-associative lockable cache lines 16-byte cache lines Up to four cache lines allocated to data Two cache lines with address mask to hold repeated instructions Pseudo-LRU replacement policy All cache lines are software writable 16-byte parallel memory fetch Predictive instruction prefetch A simplified block diagram of the Prefetch Cache module is illustrated in Figure 9-1. PREFETCH CACHE MODULE BLOCK DIAGRAM CTRL FSM Cache Line Tag Logic CTRL BMX/CPU BMX/CPU Features Bus Control Cache Control Prefetch Control Cache Line Address Encode Hit LRU Miss LRU RDATA Hit Logic Prefetch Prefetch CTRL RDATA PFM 2009-2013 Microchip Technology Inc. DS60001156H-page 147 PIC32MX5XX/6XX/7XX 9.2 Control Registers REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 CHECON: CACHE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- CHECOH U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 -- -- PREFEN<1:0> -- DCSZ<1:0> R/W-1 R/W-1 PFMWS<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-17 Unimplemented: Write `0'; ignore read bit 16 CHECOH: Cache Coherency Setting on a PFM Program Cycle bit 1 = Invalidate all data and instruction lines 0 = Invalidate all data lnes and instruction lines that are not locked bit 15-10 Unimplemented: Write `0'; ignore read bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits Changing these bits causes all lines to be reinitialized to the "invalid" state. 11 = Enable data caching with a size of 4 lines 10 = Enable data caching with a size of 2 lines 01 = Enable data caching with a size of 1 line 00 = Disable data caching bit 7-6 Unimplemented: Write `0'; ignore read bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits 11 = Enable predictive prefetch for both cacheable and non-cacheable regions 10 = Enable predictive prefetch only for non-cacheable regions 01 = Enable predictive prefetch only for cacheable regions 00 = Disable predictive prefetch bit 3 Unimplemented: Write `0'; ignore read bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits 111 = Seven Wait states 110 = Six Wait states 101 = Five Wait states 100 = Four Wait states 011 = Three Wait states 010 = Two Wait states 001 = One Wait state 000 = Zero Wait state DS60001156H-page 148 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 CHEACC: CACHE ACCESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CHEWEN -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- CHEIDX<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown CHEWEN: Cache Access Enable bits These bits apply to registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3. 1 = The cache line selected by CHEIDX<3:0> is writeable 0 = The cache line selected by CHEIDX<3:0> is not writeable bit 30-4 Unimplemented: Write `0'; ignore read bit 3-0 CHEIDX<3:0>: Cache Line Index bits The value selects the cache line for reading or writing. 2009-2013 Microchip Technology Inc. DS60001156H-page 149 PIC32MX5XX/6XX/7XX REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 CHETAG: CACHE TAG REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 LTAGBOOT -- -- -- -- -- -- -- R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LTAG<19:12> R/W-x R/W-x R/W-x R/W-x R/W-x LTAG<11:4> R/W-x R/W-x R/W-x R/W-x LTAG<3:0> R/W-0 R/W-0 R/W-1 U-0 LVALID LLOCK LTYPE -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown LTAGBOOT: Line Tag Address Boot bit 1 = The line is in the 0x1D000000 (physical) area of memory 0 = The line is in the 0x1FC00000 (physical) area of memory bit 30-24 Unimplemented: Write `0'; ignore read bit 23-4 LTAG<19:0>: Line Tag Address bits LTAG<19:0> bits are compared against physical address to determine a hit. Because its address range and position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses, (system) physical addresses, and PFM physical addresses. bit 3 LVALID: Line Valid bit 1 = The line is valid and is compared to the physical address for hit detection 0 = The line is not valid and is not compared to the physical address for hit detection bit 2 LLOCK: Line Lock bit 1 = The line is locked and will not be replaced 0 = The line is not locked and can be replaced bit 1 LTYPE: Line Type bit 1 = The line caches instruction words 0 = The line caches data words bit 0 Unimplemented: Write `0'; ignore read DS60001156H-page 150 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 CHEMSK: CACHE TAG MASK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LMASK<10:3> R/W-0 R/W-0 R/W-0 LMASK<2:0> U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Write `0'; ignore read bit 15-5 LMASK<10:0>: Line Mask bits 1 = Enables mask logic to force a match on the corresponding bit position in LTAG<19:0> bits (CHETAG<23:4>) and the physical address 0 = Only writeable for values of CHEIDX<3:0> bits (CHEACC<3:0>) equal to 0x0A and 0x0B (disables mask logic) bit 4-0 Unimplemented: Write `0'; ignore read REGISTER 9-5: Bit Range 31:24 23:16 15:8 7:0 CHEW0: CACHE WORD 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW0<31:24> R/W-x R/W-x CHEW0<23:16> R/W-x CHEW0<15:8> R/W-x CHEW0<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. 2009-2013 Microchip Technology Inc. DS60001156H-page 151 PIC32MX5XX/6XX/7XX REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 CHEW1: CACHE WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. REGISTER 9-7: Bit Range 31:24 23:16 15:8 7:0 CHEW2: CACHE WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW2<31:24> R/W-x R/W-x CHEW2<23:16> R/W-x CHEW2<15:8> R/W-x CHEW2<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. DS60001156H-page 152 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 9-8: Bit Range 31:24 23:16 15:8 7:0 CHEW3: CACHE WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW3<31:0>: Word 3 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. Note: This register is a window into the cache data array and is only readable if the device is not code-protected. REGISTER 9-9: Bit Range 31:24 23:16 15:8 7:0 CHELRU: CACHE LRU REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 -- -- -- -- -- -- -- CHELRU<24> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHELRU<23:16> R-0 R-0 R-0 R-0 R-0 CHELRU<15:8> R-0 R-0 R-0 R-0 R-0 CHELRU<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Write `0'; ignore read bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits Indicates the pseudo-LRU state of the cache. 2009-2013 Microchip Technology Inc. DS60001156H-page 153 PIC32MX5XX/6XX/7XX REGISTER 9-10: Bit Range 31:24 23:16 15:8 7:0 CHEHIT: CACHE HIT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEHIT<31:0>: Cache Hit Count bits Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable accesses do not modify this value. REGISTER 9-11: Bit Range 31:24 23:16 15:8 7:0 CHEMIS: CACHE MISS STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEMIS<31:24> R/W-x R/W-x CHEMIS<23:16> R/W-x CHEMIS<15:8> R/W-x CHEMIS<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEMIS<31:0>: Cache Miss Count bits Incremented each time the processor issues an instruction fetch from a cacheable region that misses the prefetch cache. Non-cacheable accesses do not modify this value. DS60001156H-page 154 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 9-12: Bit Range 31:24 23:16 15:8 7:0 CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load or store. 2009-2013 Microchip Technology Inc. DS60001156H-page 155 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 156 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS60001117) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32 (such as SPI, UART, PMP, etc.) or memory itself. Following are some of the key features of the DMA controller module: * Four identical channels, each featuring: - Auto-increment source and destination address registers - Source and destination pointers - Memory to memory and memory to peripheral transfers FIGURE 10-1: INT Controller Peripheral Bus * Automatic word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination * Fixed priority channel arbitration * Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA channel status interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA debug support features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable DMA BLOCK DIAGRAM System IRQ SE Address Decoder Channel 0 Control I0 Channel 1 Control I1 L Y Bus Interface Device Bus + Bus Arbitration I2 Global Control (DMACON) Channel `n' Control In SE L Channel Priority Arbitration 2009-2013 Microchip Technology Inc. DS60001156H-page 157 PIC32MX5XX/6XX/7XX 10.1 Control Registers REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 U-0 U-0 U-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 -- -- SUSPEND DMABUSY -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- ON Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as `0' bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally bit 11 DMABUSY: DMA Module Busy bit 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data bit 10-0 Unimplemented: Read as `0' Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001156H-page 158 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- RDWR DMACH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3 RDWR: Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write bit 2-0 DMACH<2:0>: DMA Channel bits These bits contain the value of the most recent active DMA channel. REGISTER 10-3: Bit Range 31:24 23:16 15:8 7:0 DMAADDR: DMA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<31:24> R-0 R-0 R-0 R-0 R-0 DMAADDR<23:16> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<15:8> R-0 R-0 DMAADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR<31:0>: DMA Module Address bits These bits contain the address of the most recent DMA access. 2009-2013 Microchip Technology Inc. DS60001156H-page 159 PIC32MX5XX/6XX/7XX REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 BYTO<1:0> Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 R/W-0 (1) -- -- WBO -- -- BITO U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 U-0 U-0 PLEN<4:0> CRCEN CRCAPP(1) CRCTYP -- -- R/W-0 CRCCH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (reverse source byte order) 00 = No swapping (source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO<1:0> 0 = Source data is written to the destination unaltered bit 26-25 Unimplemented: Read as `0' bit 24 BITO: CRC Bit Order Selection bit When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (not reflected) When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (reflected) 0 = The LFSR CRC is calculated Most Significant bit first (not reflected) bit 23-13 Unimplemented: Read as `0' bit 12-8 PLEN<4:0>: Polynomial Length bits(1) When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial - 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS60001156H-page 160 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but not to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination bit 5 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC bit 4-3 Unimplemented: Read as `0' bit 2-0 CRCCH<2:0>: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. 2009-2013 Microchip Technology Inc. DS60001156H-page 161 PIC32MX5XX/6XX/7XX REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA<31:0>: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return `0' on any read. When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always `0'. Data written to this register is converted and read back in 1's complement form (current IP header checksum value). When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return `0' on any read. REGISTER 10-6: Bit Range 31:24 23:16 15:8 7:0 DCRCXOR: DMA CRCXOR ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<15:8> R/W-0 R/W-0 DCRCXOR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register DS60001156H-page 162 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL `x' CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY -- -- -- -- -- -- CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED CHCHN CHAEN -- CHEDET CHPRI<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14-9 Unimplemented: Read as `0' bit 8 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) bit 7 CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled bit 6 CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled bit CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete bit 3 Unimplemented: Read as `0' bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI<1:0>: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 Note 1: 2: The chain selection bit takes effect when chaining is enabled (CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. 2009-2013 Microchip Technology Inc. DS60001156H-page 163 PIC32MX5XX/6XX/7XX REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL `x' EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- Legend: R = Readable bit -n = Value at POR S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag * * * bit 15-8 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer * * * bit 2-0 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a `1' 0 = This bit always reads `0' CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a `1' 0 = This bit always reads `0' PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as `0' Note 1: See Table 7-1: "Interrupt IRQ, Vector and Bit Location" for the list of available interrupt IRQ sources. bit 7 bit 6 bit 5 bit 4 bit 3 DS60001156H-page 164 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL `x' INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 15-8 Unimplemented: Read as `0' bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ) 0 = No interrupt is pending bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2) 0 = No interrupt is pending 2009-2013 Microchip Technology Inc. DS60001156H-page 165 PIC32MX5XX/6XX/7XX REGISTER 10-9: DCHxINT: DMA CHANNEL `x' INTERRUPT CONTROL REGISTER (CONTINUED) bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected (either the source or the destination address is invalid) 0 = No interrupt is pending DS60001156H-page 166 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-10: DCHxSSA: DMA CHANNEL `x' SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> 23:16 R/W-0 R/W-0 CHSSA<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<15:8> 7:0 R/W-0 CHSSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 10-11: DCHxDSA: DMA CHANNEL `x' DESTINATION START ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<23:16> R/W-0 R/W-0 CHDSA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination. 2009-2013 Microchip Technology Inc. DS60001156H-page 167 PIC32MX5XX/6XX/7XX REGISTER 10-12: DCHxSSIZ: DMA CHANNEL `x' SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> 7:0 R/W-0 CHSSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHSSIZ<15:0>: Channel Source Size bits 1111111111111111 = 65,535 byte source size * * * 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 10-13: DCHxDSIZ: DMA CHANNEL `x' DESTINATION SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSIZ<15:8> 7:0 R/W-0 CHDSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size * * * 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS60001156H-page 168 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-14: DCHxSPTR: DMA CHANNEL `x' SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source * * * 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source Note: When in Pattern Detect mode, this register is reset on a pattern detect. REGISTER 10-15: DCHxDPTR: DMA CHANNEL `x' DESTINATION POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHDPTR<15:8> 7:0 R-0 R-0 CHDPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination * * * 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination 2009-2013 Microchip Technology Inc. DS60001156H-page 169 PIC32MX5XX/6XX/7XX REGISTER 10-16: DCHxCSIZ: DMA CHANNEL `x' CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> 7:0 R/W-0 CHCSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event * * * 0000000000000010 = 2 bytes transferred on an event 0000000000000001 = 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 10-17: DCHxCPTR: DMA CHANNEL `x' CELL POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHCPTR<15:8> 7:0 R-0 R-0 CHCPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event * * * 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note: When in Pattern Detect mode, this register is reset on a pattern detect. DS60001156H-page 170 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 10-18: DCHxDAT: DMA CHANNEL `x' PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All other modes: Unused. 2009-2013 Microchip Technology Inc. DS60001156H-page 171 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 172 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 11.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. "USB OnThe-Go (OTG)" (DS60001126) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded Host, full-speed Device or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 11-1. 2009-2013 Microchip Technology Inc. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. The USB module includes the following features: * * * * * * * * * USB Full-speed support for host and device Low-speed host support USB OTG support Integrated signaling resistors Integrated analog comparators for VBUS monitoring Integrated USB transceiver Transaction handshaking performed by hardware Endpoint buffering anywhere in system RAM Integrated DMA to access system RAM and Flash Note: The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. DS60001156H-page 173 PIC32MX5XX/6XX/7XX FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) UFIN(5) Div x PLL Div 2 UFRCEN(3) OSC1 UPLLEN(6) UPLLIDIV(6) USB Suspend OSC2 To Clock Generator for Core and Peripherals Sleep or Idle (PB Out)(1) USB Module SRP Charge Bus USB Voltage Comparators SRP Discharge 48 MHz USB Clock(7) Full-Speed Pull-up D+(2) Registers and Control Interface Host Pull-down SIE Transceiver Low-Speed Pull-up D-(2) DMA System RAM Host Pull-down ID Pull-up ID(8) VBUSON(8) Transceiver Power 3.3V VUSB3V3 Note 1: 2: 3: 4: 5: 6: 7: 8: PB clock is only available on this pin for select EC modes. Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled. DS60001156H-page 174 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 11.1 Control Registers REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF -- VBUSVDIF Legend: WC = Write `1' to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No change in ID state detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = A change on the session end input was detected 0 = No change on the session end input was detected bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = Change on the session valid input detected 0 = No change on the session valid input detected 2009-2013 Microchip Technology Inc. DS60001156H-page 175 PIC32MX5XX/6XX/7XX REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE -- VBUSVDIE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt enabled 0 = ID interrupt disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled bit 5 LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt enabled 0 = Line state interrupt disabled bit 4 ACTVIE: Bus ACTIVITY Interrupt Enable bit 1 = ACTIVITY interrupt enabled 0 = ACTIVITY interrupt disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt enabled 0 = Session valid interrupt disabled bit 2 SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt enabled 0 = B-session end interrupt disabled bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit 1 = A-VBUS valid interrupt enabled 0 = A-VBUS valid interrupt disabled DS60001156H-page 176 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID -- LSTATE -- SESVD SESEND -- VBUSVD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a "type B" cable has been inserted into the USB receptacle 0 = A "type A" OTG cable has been inserted into the USB receptacle bit 6 Unimplemented: Read as `0' bit 5 LSTATE: Line State Stable Indicator bit 1 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has been stable for the previous 1 ms 0 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has not been stable for the previous 1 ms bit 4 Unimplemented: Read as `0' bit 3 SESVD: Session Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A or B device 0 = VBUS voltage is below Session Valid on the A or B device bit 2 SESEND: B-Device Session End Indicator bit 1 = VBUS voltage is below Session Valid on the B device 0 = VBUS voltage is above Session Valid on the B device bit 1 Unimplemented: Read as `0' bit 0 VBUSVD: A-Device VBUS Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A device 0 = VBUS voltage is below Session Valid on the A device 2009-2013 Microchip Technology Inc. DS60001156H-page 177 PIC32MX5XX/6XX/7XX REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 DPPULUP DMPULUP DPPULDWN DMPULDWN R/W-0 R/W-0 R/W-0 R/W-0 VBUSON OTGEN VBUSCHG VBUSDIS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control bit 1 VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor bit 0 VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor DS60001156H-page 178 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-5: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U1PWRC: USB POWER CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND -- -- USLPGRD USBBUSY -- USUSPEND USBPWR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = An interrupt is not pending bit 6-5 Unimplemented: Read as `0' bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry bit 3 USBBUSY: USB Module Busy bit 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results. bit 2 Unimplemented: Read as `0' bit 1 USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.) 0 = USB module operates normally bit 0 USBPWR: USB Operation Enable bit 1 = USB module is turned on 0 = USB module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) 2009-2013 Microchip Technology Inc. DS60001156H-page 179 PIC32MX5XX/6XX/7XX REGISTER 11-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 IDLEIF TRNIF(3) SOFIF UERRIF(4) R/WC-0, HS (5) STALLIF Legend: R = Readable bit -n = Value at POR ATTACHIF(1) RESUMEIF(2) WC = Write `1' to clear W = Writable bit `1' = Bit is set URSTIF DETACHIF(6) HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 STALLIF: STALL Handshake Interrupt bit 1 = In Host mode a STALL handshake was received during the handshake phase of the transaction. In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction. 0 = STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected bit 5 RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 s 0 = K-State is not observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete bit 2 SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected Note 1: 2: 3: 4: 5: 6: This bit is only valid if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for 2.5 s, and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode. DS60001156H-page 180 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1) R/W-0 URSTIE(2) DETACHIE(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled bit 6 ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt enabled 0 = ATTACH interrupt disabled bit 5 RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt enabled 0 = RESUME interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt enabled 0 = Idle interrupt disabled bit 3 TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt enabled 0 = TRNIF interrupt disabled bit 2 SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt enabled 0 = SOFIF interrupt disabled bit 1 UERRIE: USB Error Interrupt Enable bit(1) 1 = USB Error interrupt enabled 0 = USB Error interrupt disabled bit 0 URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt enabled 0 = URSTIF interrupt disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt enabled 0 = DATTCHIF interrupt disabled Note 1: 2: 3: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. Device mode. Host mode. 2009-2013 Microchip Technology Inc. DS60001156H-page 181 PIC32MX5XX/6XX/7XX REGISTER 11-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS BTSEF BMXEF DMAEF(1) BTOEF(2) R/WC-0, HS (4) DFN8EF CRC16EF Legend: R = Readable bit -n = Value at POR WC = Write `1' to clear W = Writable bit `1' = Bit is set CRC5EF EOFEF(3,5) PIDEF HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Packet rejected due to bit stuff error 0 = Packet accepted bit 6 BMXEF: Bus Matrix Error Flag bit 1 = Invalid base address of the BDT, or the address of an individual buffer pointed to by a BDT entry 0 = No address error bit 5 DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted bit 1 CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(3,5) 1 = EOF error condition detected 0 = No EOF error condition bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note 1: 2: 3: 4: 5: This type of error occurs when the module's request for the DMA bus is not granted in time to service the module's demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. DS60001156H-page 182 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE(1) EOFEE(2) PIDEE Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt enabled 0 = BTSEF interrupt disabled bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt enabled 0 = BMXEF interrupt disabled bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt enabled 0 = DMAEF interrupt disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt enabled 0 = BTOEF interrupt disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt enabled 0 = DFN8EF interrupt disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt enabled 0 = CRC16EF interrupt disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(1) 1 = CRC5EF interrupt enabled 0 = CRC5EF interrupt disabled EOFEE: EOF Error Interrupt Enable bit(2) 1 = EOF interrupt enabled 0 = EOF interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt enabled 0 = PIDEF interrupt disabled Note 1: 2: Note: Device mode. Host mode. For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. 2009-2013 Microchip Technology Inc. DS60001156H-page 183 PIC32MX5XX/6XX/7XX REGISTER 11-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI -- -- ENDPT<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits (Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 * * * 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last Buffer Descriptor Direction Indicator bit 1 = Last transaction was a transmit transfer (TX) 0 = Last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit 1 = The last transaction was to the Odd buffer descriptor bank 0 = The last transaction was to the Even buffer descriptor bank bit 1-0 Unimplemented: Read as `0' Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register is invalid when U1IR<TRNIF> = 0. DS60001156H-page 184 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE PKTDIS(4) SE0 TOKBUSY(1,5) USBRST HOSTEN(2) RESUME(3) PPBRST R/W-0 USBEN(4) SOFEN(5) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE was detected on the USB 0 = JSTATE was not detected bit 6 SE0: Live Single-Ended Zero flag bit 1 = Single-ended zero was detected on the USB 0 = Single-ended zero was not detected bit 5 PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing disabled (set upon SETUP token received) 0 = Token and packet processing enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token being executed by the USB module 0 = No token being executed bit 4 USBRST: Module Reset bit(5) 1 = USB reset generated 0 = USB reset terminated bit 3 HOSTEN: Host Mode Enable bit(2) 1 = USB host capability enabled 0 = USB host capability disabled bit 2 RESUME: RESUME Signaling Enable bit(3) 1 = RESUME signaling activated 0 = RESUME signaling disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 11-15). All host control logic is reset any time that the value of this bit is toggled. Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. 2009-2013 Microchip Technology Inc. DS60001156H-page 185 PIC32MX5XX/6XX/7XX REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the Even buffer descriptor banks 0 = Even/Odd buffer pointers are not reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 11-15). All host control logic is reset any time that the value of this bit is toggled. Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. DS60001156H-page 186 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 LSPDEN: Low-Speed Enable Indicator bit 1 = Next token command to be executed at low-speed 0 = Next token command to be executed at full-speed bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits REGISTER 11-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FRML<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 FRML<7:0>: 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. 2009-2013 Microchip Technology Inc. DS60001156H-page 187 PIC32MX5XX/6XX/7XX REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- -- -- FRMH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as `0' bit 2-0 FRMH<2:0>: Upper 3 bits of the Frame Numbers bits These register bits are updated with the current frame number whenever a SOF TOKEN is received. REGISTER 11-15: U1TOK: USB TOKEN REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID<3:0> EP<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-4 PID<3:0>: Token Type Indicator bits(1) 1101 = SETUP (TX) token type transaction 1001 = IN (RX) token type transaction 0001 = OUT (TX) token type transaction Note: All other values not listed, are Reserved and must not be used. bit 3-0 EP<3:0>: Token Command Endpoint Address bits The four bit value must specify a valid endpoint. DS60001156H-page 188 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 CNT<7:0>: SOF Threshold Value bits Typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet REGISTER 11-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BDTPTRL<15:9> -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-1 BDTPTRL<15:9>: BDT Base Address bits This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. bit 0 Unimplemented: Read as `0' 2009-2013 Microchip Technology Inc. DS60001156H-page 189 PIC32MX5XX/6XX/7XX REGISTER 11-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 BDTPTRH<23:16>: BDT Base Address bits This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. REGISTER 11-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRU<31:24> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 BDTPTRU<31:24>: BDT Base Address bits This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. DS60001156H-page 190 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 UTEYE UOEMON -- USBSIDL -- -- -- UASUSPND Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern Test enabled 0 = Eye-Pattern Test disabled bit 6 UOEMON: USB OE Monitor Enable bit 1 = OE signal active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal inactive bit 5 Unimplemented: Read as `0' bit 4 USBSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 3-1 Unimplemented: Read as `0' bit 0 UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (U1PWRC<1>) in Register 11-5. 0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock. 2009-2013 Microchip Technology Inc. DS60001156H-page 191 PIC32MX5XX/6XX/7XX REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled; hub required with PRE_PID bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NACK'd transactions disabled 0 = Retry NACK'd transactions enabled; retry done in hardware bit 5 Unimplemented: Read as `0' bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN = 1 and EPRXEN = 1: 1 = Disable Endpoint `n' from control transfers; only TX and RX transfers are allowed 0 = Enable Endpoint `n' for control (SETUP) transfers; TX and RX transfers are also allowed Otherwise, this bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint 'n' receive enabled 0 = Endpoint 'n' receive disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint 'n' transmit enabled 0 = Endpoint 'n' transmit disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint 'n' was stalled 0 = Endpoint 'n' was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint Handshake enabled 0 = Endpoint Handshake disabled (typically used for isochronous endpoints) DS60001156H-page 192 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC32 MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS60001120) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Following are some of the key features of this module: * Individual output pin open-drain enable/disable * Individual input pin weak pull-up enable/disable * Monitor selective inputs and generate interrupt when change in pin state is detected * Operation during Sleep and Idle modes * Fast bit manipulation using CLR, SET and INV registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus D SYSCLK Q ODC CK EN Q WR ODC 1 RD TRIS 0 I/O Cell 0 1 D Q 1 TRIS CK EN Q 0 WR TRIS Output Multiplexers D Q I/O Pin LAT CK EN Q WR LAT WR PORT RD LAT 1 RD PORT 0 Sleep Q Q D CK Q Q D CK SYSCLK Synchronization R Peripheral Input Peripheral Input Buffer Legend: Note: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure is only for illustration purposes. The actual structure for any specific port/peripheral combination may be different than it is shown here. 2009-2013 Microchip Technology Inc. DS60001156H-page 193 PIC32MX5XX/6XX/7XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a Data Direction or Tri-State Control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1, configures the corresponding I/O pin as an input; setting a TRISx register bit = 0, configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog peripherals and default to analog inputs after a device Reset. PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins. LAT is a register used to write data to the port I/O pins. The LATx Latch register holds the data written to either the LATx or PORTx registers. Reading the LATx Latch register reads the last value written to the corresponding PORT or Latch register. Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros. 12.1.1 CLR, SET AND INV REGISTERS Every I/O module register has a corresponding Clear (CLR), Set (SET) and Invert (INV) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. Note: 12.1.2 The maximum input voltage allowed on the input pins is the same as the maximum VIH specification. Refer to Section 31.0 "Electrical Characteristics" for VIH specification details. Note: 12.1.3 12.1.4 DIGITAL OUTPUTS Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open-drain outputs by setting the corresponding bits in the Open-Drain Configuration (ODCx) register. The open-drain feature allows generation of outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the "Pin Diagrams" section for the available pins and their functionality. 12.1.5 DIGITAL INPUTS 12.1.6 DS60001156H-page 194 ANALOG INPUTS Certain pins can be configured as analog inputs used by the ADC and comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level (VOH or VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read `0'. The AD1PCFG register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default. Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions, as compared to the traditional read-modify-write method, as follows: PORTC ^ = 0x0001; Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. ANALOG OUTPUTS Certain pins can be configured as analog outputs, such as the CVREF output voltage used by the comparator module. Configuring the comparator reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin. INPUT CHANGE NOTIFICATION The input change notification function of the I/O ports (CNx) allows devices to generate interrupt requests in response to change-of-state on selected pin. Each CNx pin also has a weak pull-up, which acts as a current source connected to the pin. The pull-ups are enabled by setting the corresponding bit in the CNPUE register. 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 12.2 Control Register REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 CNCON: CHANGE NOTICE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON -- SIDL -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = Idle mode halts CN operation 0 = Idle mode does not affect CN operation bit 12-0 Unimplemented: Read as `0' 2009-2013 Microchip Technology Inc. DS60001156H-page 195 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 196 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 13.0 TIMER1 This family of PIC32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the low-power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer 13.1 Additional Supported Features * Selectable clock prescaler * Timer operation during Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) A simplified block diagram of the Timer1 module is illustrated in Figure 13-1. FIGURE 13-1: TIMER1 BLOCK DIAGRAM PR1 Equal 16-bit Comparator TSYNC (T1CON<2>) 1 Sync TMR1 Reset T1IF Event Flag 0 0 1 Q TGATE (T1CON<7>) D Q TCS (T1CON<1>) TGATE (T1CON<7>) ON (T1CON<15>) SOSCO/T1CK x1 SOSCEN(1) Gate Sync 10 Prescaler 1, 8, 64, 256 SOSCI PBCLK 00 2 TCKPS<1:0> (T1CON<5:4>) Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1. 2009-2013 Microchip Technology Inc. DS60001156H-page 197 PIC32MX5XX/6XX/7XX 13.2 Control Register REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON(1) -- SIDL TWDIS TWIP -- -- -- R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE -- -- TSYNC TCS -- TCKPS<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Timer On bit(1) 1 = Timer is enabled 0 = Timer is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation when device is in Idle mode bit 12 TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) bit 11 TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as `0'. bit 10-8 Unimplemented: Read as `0' bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Unimplemented: Read as `0' Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001156H-page 198 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 Unimplemented: Read as `0' bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored. bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as `0' Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2009-2013 Microchip Technology Inc. DS60001156H-page 199 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 200 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * Synchronous Internal 32-bit Timer * Synchronous Internal 32-bit Gated Timer * Synchronous External 32-bit Timer Note: 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 14.1 Additional Supported Features * Selectable clock prescaler * Timers operational during CPU idle * Time base for Input Capture and Output Compare modules (only Timer2 and Timer3) * ADC event trigger (only Timer3) * Fast bit manipulation using CLR, SET and INV registers This family of PIC32 devices features four synchronous 16-bit timers (default) that can operate as a freerunning interval timer for various timing applications and counting external events. The following modes are supported: * Synchronous Internal 16-bit Timer * Synchronous Internal 16-bit Gated Timer * Synchronous External 16-bit Timer FIGURE 14-1: In this chapter, references to registers, TxCON, TMRx and PRx, use `x' to represent Timer2 through Timer5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or Timer4; `y' represents Timer3 or Timer5. TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (16-BIT) Sync TMRx ADC Event Trigger(1) Equal Comparator x 16 PRx Reset TxIF Event Flag 0 1 Q TGATE (TxCON<7>) D Q TCS (TxCON<1>) TGATE (TxCON<7>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: ADC event trigger is only available on Timer3. 2: TxCK pins are not available on 64-pin devices. 2009-2013 Microchip Technology Inc. DS60001156H-page 201 PIC32MX5XX/6XX/7XX FIGURE 14-2: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MS Half Word ADC Event Trigger(3) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) TGATE (TxCON<7>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of `x' in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of `y' in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is only available on the Timer2/3 pair. DS60001156H-page 202 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 14.2 Control Register REGISTER 14-1: Bit Range 31:24 23:16 TXCON: TYPE B TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- 15:8 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1,3) -- SIDL(4) -- -- -- -- -- 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 TGATE(3) T32(2) -- TCS(3) -- TCKPS<2:0>(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-16 Unimplemented: Read as `0' bit 15 ON: Timer On bit(1,3) 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit(4) 1 = Discontinue operation when device enters Idle mode 0 = Continue operation when device is in Idle mode x = Bit is unknown bit 12-8 Unimplemented: Read as `0' bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS = 1: This bit is ignored and is read as `0'. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is only available on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: 2009-2013 Microchip Technology Inc. DS60001156H-page 203 PIC32MX5XX/6XX/7XX REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 3 bit 2 Unimplemented: Read as `0' bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as `0' Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is only available on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: DS60001156H-page 204 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 15.0 INPUT CAPTURE * Capture timer value on every edge (rising and falling) * Capture timer value on every edge (rising and falling), specified edge first. * Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS60001122) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. Other operational features include: The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events: * Device wake-up from capture pin during Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Input Capture module can also be used to provide additional sources of external interrupts * Simple capture event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM ICx Input Timer3 Timer2 ICTMR 0 1 C32 FIFO Control ICxBUF<31:16> Prescaler 1, 4, 16 ICM<2:0> ICxBUF<15:0> Edge Detect ICM<2:0> FEDGE ICBNE ICOV ICxCON ICI<1:0> Interrupt Event Generation Data Space Interface Interrupt 2009-2013 Microchip Technology Inc. Peripheral Data Bus DS60001156H-page 205 PIC32MX5XX/6XX/7XX 15.1 Control Register REGISTER 15-1: Bit Range Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE `X' CONTROL REGISTER Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 -- SIDL -- -- -- FEDGE C32 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 ICOV ICBNE ON ICTMR ICI<1:0> ICM<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Input Capture Module Enable bit(1) 1 = Module enabled 0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = Halt in Idle mode 0 = Continue to operate in Idle mode bit 12-10 Unimplemented: Read as `0' bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110) 1 = Capture rising edge first 0 = Capture falling edge first bit 8 C32: 32-bit Capture Select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is `1') 1 = Timer2 is the counter source for capture 0 = Timer3 is the counter source for capture bit 6-5 ICI<1:0>: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001156H-page 206 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 15-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE `X' CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode - every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode - every sixteenth rising edge 100 = Prescaled Capture Event mode - every fourth rising edge 011 = Simple Capture Event mode - every rising edge 010 = Simple Capture Event mode - every falling edge 001 = Edge Detect mode - every edge (rising and falling) 000 = Input Capture module is disabled When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2009-2013 Microchip Technology Inc. DS60001156H-page 207 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 208 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 16.0 OUTPUT COMPARE The Output Compare module is used to generate a single pulse or a series of pulses in response to selected time base events. For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the Output Compare module generates an event based on the selected mode of operation. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Compare" (DS60001111) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Some of the key features of the Output Compare module are: * Multiple Output Compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Programmable selection of 16-bit or 32-bit time bases * Can operate from either of two available 16-bit time bases or a single 32-bit time base 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) Output Logic OCxR(1) 3 OCM<2:0> Mode Select Comparator 0 16 OCTSEL 1 0 S R Output Enable Q OCx(1) Output Enable Logic OCFA or OCFB(2) 1 16 TMR Register Inputs from Time Bases(3) Period Match Signals from Time Bases(3) Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. 2009-2013 Microchip Technology Inc. DS60001156H-page 209 PIC32MX5XX/6XX/7XX 16.1 Control Register REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE `x' CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 -- SIDL -- -- -- -- -- U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- OC32 OCFLT(2) OCTSEL ON OCM<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Output Compare Module On bit(1) 1 = Output Compare module is enabled 0 = Output Compare module is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation when CPU is in Idle mode bit 12-6 Unimplemented: Read as `0' bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source bit 4 OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (only cleared in hardware) 0 = PWM Fault condition has not occurred bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this Output Compare module 0 = Timer2 is the clock source for this Output Compare module bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is only used when OCM<2:0> = 111. It is read as `0' in all other modes. 2: DS60001156H-page 210 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters, etc. The PIC32 SPI module is compatible with Motorola(R) SPI and SIOP interfaces. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (SPI)" (DS60001106) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Some of the key features of this module include: * * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 17-1: * * * Master mode and Slave mode support Four different clock formats Enhanced Framed SPI protocol support User-configurable 8-bit, 16-bit and 32-bit data width Separate SPI FIFO buffers for receive and transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer Operation during Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write FIFOs Share Address SPIxBUF SPIxRXB FIFO SPIxTXB FIFO Transmit Receive SPIxSR SDIx bit 0 SDOx SSx/FSYNC Slave Select and Frame Sync Control Shift Control Clock Control Edge Select Baud Rate Generator PBCLK SCKx Enable Master Clock Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. 2009-2013 Microchip Technology Inc. DS60001156H-page 211 PIC32MX5XX/6XX/7XX 17.1 Control Registers REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- SPIFE ENHBUF(2) FRMCNT<2:0> R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON(1) -- SIDL DISSDO MODE32 MODE16 SMP CKE(3) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set STXISEL<1:0> SRXISEL<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (only Framed SPI mode) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) bit 29 FRMPOL: Frame Sync Polarity bit (only Framed SPI mode) 1 = Frame pulse is active-high 0 = Frame pulse is active-low bit 28 MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit. 0 = Slave select SPI support is disabled. bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in Framed Sync mode. 111 = Reserved 110 = Reserved 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character bit 23-18 Unimplemented: Read as `0' bit 17 SPIFE: Frame Sync Pulse Edge Select bit (only Framed SPI mode) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock Note 1: 2: 3: When using the 1:1 PBCLK divisor, the user's software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). DS60001156H-page 212 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module (pin is controlled by associated PORT register) 0 = SDOx pin is controlled by the module bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits MODE16 Communication MODE32 1 x 32-bit 0 1 16-bit 0 0 8-bit bit 9 SMP: SPI Data Input Sample Phase bit Master mode (MSTEN = 1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time bit 16 Slave mode (MSTEN = 0): SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode (pin is controlled by port function) CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Unimplemented: Read as `0' STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) bit 8 bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1-0 Note 1: 2: 3: When using the 1:1 PBCLK divisor, the user's software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). 2009-2013 Microchip Technology Inc. DS60001156H-page 213 PIC32MX5XX/6XX/7XX REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 R-0 SPITUR -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 RXBUFELM<4:0> R-0 TXBUFELM<4:0> U-0 R-0 U-0 -- -- -- -- SPIBUSY -- -- R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE -- SPITBE -- SPITBF SPIRBF Legend: C = Clearable bit HS = Set in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as `0' bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (only valid when ENHBUF = 1) bit 23-21 Unimplemented: Read as `0' bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (only valid when ENHBUF = 1) bit 15-12 Unimplemented: Read as `0' bit 11 SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle bit 10-9 Unimplemented: Read as `0' bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 SRMT: Shift Register Empty bit (only valid when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can only be cleared (= 0) in software. bit 5 SPIRBE: RX FIFO Empty bit (only valid when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR SWPTR) bit 4 Unimplemented: Read as `0' bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. bit 2 Unimplemented: Read as `0' DS60001156H-page 214 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 17-2: bit 1 SPIxSTAT: SPI STATUS REGISTER SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode: Set when CWPTR + 1 = SRPTR; cleared otherwise bit 0 SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Set when SWPTR + 1 = CRPTR; cleared otherwise 2009-2013 Microchip Technology Inc. DS60001156H-page 215 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 216 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 18.0 INTER-INTEGRATED CIRCUITTM (I2CTM) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. "InterIntegrated CircuitTM (I2CTM)" (DS60001116) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 2009-2013 Microchip Technology Inc. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 18-1 illustrates the I2C module block diagram. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module offers the following key features: * I2C interface supporting both master and slave operation * I2C Slave mode supports 7-bit and 10-bit addressing * I2C Master mode supports 7-bit and 10-bit addressing * I2C port allows bidirectional transfers between master and slaves * Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) * I2C supports multi-master operation; detects bus collision and arbitrates accordingly * Provides support for address bit masking DS60001156H-page 217 PIC32MX5XX/6XX/7XX FIGURE 18-1: I2CTM BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop bit Detect Write Start and Stop bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001156H-page 218 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 18.1 Control Registers REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2CTM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 -- SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN ON Legend: HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: I2C Enable bit(1) 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation when device enters Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (software can write `0' to initiate stretch and write `1' to release clock). Cleared by hardware at the beginning of a slave transmission and at the end of slave reception. If STREN = 0: Bit is R/S (software can only write `1' to release clock). Cleared by hardware at the beginning of slave transmission. bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C reserved address rule is not enabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2009-2013 Microchip Technology Inc. DS60001156H-page 219 PIC32MX5XX/6XX/7XX REGISTER 18-1: I2CXCON: I2CTM CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an acknowledge sequence. 1 = Send NACK during an acknowledge 0 = Send ACK during an acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition is not in progress Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001156H-page 220 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2CTM STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF Legend: HS = Set by hardware HSC = Hardware set/cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as `0' bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) This bit is set or cleared by hardware at the end of a slave Acknowledge. 1 = NACK received from slave 0 = ACK received from slave bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) This bit is set by hardware at the beginning of a master transmission, and is cleared by hardware at the end of a slave Acknowledge. 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress bit 13-11 Unimplemented: Read as `0' bit 10 BCL: Master Bus Collision Detect bit This bit is set by hardware at the detection of a bus collision. 1 = A bus collision has been detected during a master operation 0 = No collision bit 9 GCSTAT: General Call Status bit This bit is set by hardware when the address matches the general call address, and is cleared by hardware clear at a Stop detection. 1 = General call address was received 0 = General call address was not received bit 8 ADD10: 10-bit Address Status bit This bit is set by hardware upon a match of the 2nd byte of the matched 10-bit address, and is cleared by hardware at a Stop detection. 1 = 10-bit address was matched 0 = 10-bit address was not matched bit 7 IWCOL: Write Collision Detect bit This bit is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software). 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision bit 6 I2COV: Receive Overflow Flag bit This bit is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow 2009-2013 Microchip Technology Inc. DS60001156H-page 221 PIC32MX5XX/6XX/7XX REGISTER 18-2: I2CXSTAT: I2CTM STATUS REGISTER (CONTINUED) bit 5 D_A: Data/Address bit (when operating as I2C slave) This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the slave byte. 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address bit 4 P: Stop bit This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected. 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected. 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last bit 2 R_W: Read/Write Information bit (when operating as I2C slave) This bit is set or cleared by hardware after reception of an I 2C device address byte. 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave bit 1 RBF: Receive Buffer Full Status bit This bit is set by hardware when the I2CxRCV register is written with a received byte, and is cleared by hardware when software reads I2CxRCV. 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty bit 0 TBF: Transmit Buffer Full Status bit This bit is set by hardware when software writes to the I2CxTRN register, and is cleared by hardware upon completion of data transmission. 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty DS60001156H-page 222 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The UART module is one of the serial I/O modules available in PIC32MX5XX/6XX/7XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN 1.2 and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. FIGURE 19-1: The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, Odd or No Parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 76 bps to 20 Mbps at 80 MHz 8-level deep First-In-First-Out (FIFO) transmit data buffer 8-level deep FIFO receive data buffer Parity, framing and buffer overrun error detection Support for interrupt-only on address detect (ninth bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support * LIN 1.2 Protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 19-1 illustrates a simplified block diagram of the UART module. UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) BCLKx UxRTS Hardware Flow Control UxCTS Note: UARTx Receiver UxRX UARTx Transmitter UxTX Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information (see "Pin Diagrams"). 2009-2013 Microchip Technology Inc. DS60001156H-page 223 PIC32MX5XX/6XX/7XX Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module. FIGURE 19-2: UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Read to UxRXREG UxRX Start 1 Stop Start 2 Start 5 Stop 4 Stop 10 Start 11 Stop 13 RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00 Cleared by Software UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 19-3: TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF Write to UxTXREG TSR Pull from Buffer BCLK/16 (Shift Clock) UxTX Start Bit 0 Bit 1 Stop Start Bit 1 UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS60001156H-page 224 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 19.1 Control Registers REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 -- SIDL IREN RTSMD -- R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH ON Legend: UEN<1:0> R/W-0 PDSEL<1:0> R/W-0 STSEL HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: UARTx Enable bit(1) 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits. 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal. bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation when device enters Idle mode bit 12 IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as `0' bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up is enabled 0 = Wake-up is disabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2009-2013 Microchip Technology Inc. DS60001156H-page 225 PIC32MX5XX/6XX/7XX REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode - 4x baud clock enabled 0 = Standard Speed mode - 16x baud clock enabled bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001156H-page 226 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 TRMT ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0, HC R/W-0 UTXINV URXEN UTXBRK UTXEN UTXBF R/W-0 R-1 R-0 R-0 R/W-0, HS R-0 ADDEN RIDLE PERR FERR OERR URXDA Legend: HS = Set by hardware HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as `0' bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR<7:0>: Automatic Address Mask bits When the ADM_EN bit is `1', this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is `0'): 1 = UxTX Idle state is `0' 0 = UxTX Idle state is `1' If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is `1'): 1 = IrDA encoded UxTX Idle state is `1' 0 = IrDA encoded UxTX Idle state is `0' bit 12 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port. bit 11 UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion. 0 = Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by port. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written 2009-2013 Microchip Technology Inc. DS60001156H-page 227 PIC32MX5XX/6XX/7XX REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (has 4 or more data characters) 00 = Interrupt flag bit is asserted while receive buffer is not empty (has at least 1 data character) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect. 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is idle 0 = Data is being received bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to an empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty DS60001156H-page 228 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS60001128) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. Figure 20-1 shows the PMP module pinout and its connections to external devices. FIGURE 20-1: Key features of the PMP module include: * * * * * * * * * * * 8-bit and 16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options - Individual read and write strobes, or - Read/Write strobe with enable strobe Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable wait states Operates during Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Note: On 64-pin devices, the PMD<15:8> data pins are not available. PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus PIC32MX5XX/6XX/7XX Parallel Master Port Control Lines PMA<0> PMALL PMA<1> PMALH Flash EEPROM SRAM Up to 16-bit Address PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 PMRD PMRD/PMWR PMWR PMENB Microcontroller LCD FIFO Buffer PMD<7:0> PMD<15:8>(1) 16/8-bit Data (with or without multiplexed addressing) Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-bit Master modes. 2009-2013 Microchip Technology Inc. DS60001156H-page 229 PIC32MX5XX/6XX/7XX 20.1 Control Registers REGISTER 20-1: Bit Range 31:24 23:16 15:8 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN R/W-0 R/W-0 (2) R/W-0 (2) U-0 U-0 R/W-0 R/W-0 -- WRSP RDSP ON 7:0 CSF<1:0> ALP -- R/W-0 (2) CS1P Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Parallel Master Port Enable bit(1) 1 = PMP is enabled 0 = PMP is disabled, no off-chip access performed bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation when device enters Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and PMA<14> 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled bit 7-6 CSF<1:0>: Chip Select Function bits(2) 11 = Reserved 10 = PMCS1 functions as Chip Select 01 = PMCS1 functions as address bit 14 00 = PMCS1 functions as address bit 14 Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. DS60001156H-page 230 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 5 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 Unimplemented: Read as `0' bit 3 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Unimplemented: Read as `0' bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. 2009-2013 Microchip Technology Inc. DS60001156H-page 231 PIC32MX5XX/6XX/7XX REGISTER 20-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 (1) R/W-0 WAITB<1:0> INCM<1:0> R/W-0 R/W-0 (1) -- MODE<1:0> R/W-0 R/W-0 R/W-0 WAITE<1:0>(1) WAITM<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 BUSY: Busy bit (only Master mode) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> =11 (only Addressable Slave mode) 01 = Interrupt generated at the end of the read/write cycle 00 = Interrupt is not generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (only PMMODE<1:0> = 00) 10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2) 01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2) 00 = No increment or decrement of address bit 10 Unimplemented: Read as `0' bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. DS60001156H-page 232 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB * * * 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. 2009-2013 Microchip Technology Inc. DS60001156H-page 233 PIC32MX5XX/6XX/7XX REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- CS1 -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<10:8> R/W-0 R/W-0 R/W-0 ADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as `0' bit 14 CS1: Chip Select 1 bit 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (pin functions as PMA<14>) bit 13-11 Unimplemented: Read as `0' bit 10-0 ADDR<10:0>: Destination Address bits DS60001156H-page 234 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- PTEN14 -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<10:8> R/W-0 R/W-0 R/W-0 PTEN<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as `0' bit 15-14 PTEN14: PMCS1 Strobe Enable bits 1 = PMA14 functions as either PMA14 or PMCS1(1) 0 = PMA14 functions as port I/O bit 13-11 Unimplemented: Read as `0' bit 10-2 PTEN<10:2>: PMP Address Port Enable bits 1 = PMA<10:2> function as PMP address lines 0 = PMA<10:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads function as port I/O Note 1: 2: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register. The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX<1:0> in the PMCON register. 2009-2013 Microchip Technology Inc. DS60001156H-page 235 PIC32MX5XX/6XX/7XX REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0 IB0F IBF IBOV -- -- IB3F IB2F IB1F R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF -- -- OB3E OB2E OB1E OB0E Legend: HSC = Set by Hardware; Cleared by Software R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = An overflow has not occurred bit 13-12 Unimplemented: Read as `0' bit 11-8 IBxF: Input Buffer `x' Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = An underflow has not occurred bit 5-4 Unimplemented: Read as `0' bit 3-0 OBxE: Output Buffer `x' Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted DS60001156H-page 236 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Key features of the RTCC module include: * * * * * Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS60001125) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32 RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. A simplified block diagram of the RTCC module is illustrated in Figure 21-1. FIGURE 21-1: * * * * Time: hours, minutes and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year Alarm repeat with decrementing counter Alarm with indefinite repeat: Chime Year range: 2000 to 2099 Leap year correction BCD format for smaller firmware overhead Optimized for long-term battery operation Fractional second synchronization User calibration of the clock crystal frequency with auto-adjust Calibration range: 0.66 seconds error per month Calibrates up to 260 ppm of crystal error Requirements: External 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin RTCC BLOCK DIAGRAM 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers 0.5s YEAR, MTH, DAY RTCVAL RTCC Timer Alarm Event WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks ALRMVAL WKDAY HR, MIN, SEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin RTCOE 2009-2013 Microchip Technology Inc. DS60001156H-page 237 PIC32MX5XX/6XX/7XX 21.1 Control Registers REGISTER 21-1: Bit Range 31:24 23:16 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit 29/21/13/5 28/20/12/4 U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CAL<9:8> CAL<7:0> 15:8 7:0 RTCCON: RTC CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 ON(1,2) -- SIDL -- -- -- -- -- R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 -- -- RTSECSEL(3) RTCCLKON Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set RTCWREN(4) RTCSYNC HALFSEC(5) RTCOE U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as `0' bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value 1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute * * * 1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute 0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute * * * bit 15 bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5-4 Note 1: 2: 3: 4: 5: Note: 0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000 = No adjustment ON: RTCC On bit(1,2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode 0 = Continue normal operation in Idle mode Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(3) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin RTCCLKON: RTCC Clock Enable Status bit 1 = RTCC Clock is actively running 0 = RTCC Clock is not running Unimplemented: Read as `0' The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Requires RTCOE = 1 (RTCCON<0>) for the output to be active. The RTCWREN bit can only be set when the write sequence is enabled. This bit is read-only. It is cleared to `0' on a write to the seconds bit fields (RTCTIME<14:8>). This register is only reset on a Power-on Reset (POR). DS60001156H-page 238 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTC Value registers can be read without concern about a rollover ripple HALFSEC: Half-Second Status bit(5) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output is enabled (clock presented onto an I/O) 0 = RTCC clock output is disabled bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: 4: 5: Note: The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Requires RTCOE = 1 (RTCCON<0>) for the output to be active. The RTCWREN bit can only be set when the write sequence is enabled. This bit is read-only. It is cleared to `0' on a write to the seconds bit fields (RTCTIME<14:8>). This register is only reset on a Power-on Reset (POR). 2009-2013 Microchip Technology Inc. DS60001156H-page 239 PIC32MX5XX/6XX/7XX REGISTER 21-2: Bit Range 31:24 23:16 15:8 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (2) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 PIV ALRMSYNC(3) R/W-0 AMASK<3:0> R/W-0 ARPT<7:0>(2) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ALRMEN: Alarm Enable bit(1,2) 1 = Alarm is enabled 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit(2) 1 = Chime is enabled - ARPT<7:0> is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled - ARPT<7:0> stops once it reaches 0x00 bit 13 PIV: Alarm Pulse Initial Value bit(3) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. bit 12 ALRMSYNC: Alarm Sync bit(3) 1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain. 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC clocks away from a half-second rollover bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(2) 1111 = Reserved * * * 1010 = 1001 = 1000 = 0111 = 0110 = 0101 = 0100 = 0011 = 0010 = 0001 = 0000 = Note 1: 2: 3: Note: Reserved Once a year (except when configured for February 29, once every four years) Once a month Once a week Once a day Every hour Every 10 minutes Every minute Every 10 seconds Every second Every half-second Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = `1' (RTCCON<15>) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. This register is only reset on a Power-on Reset (POR). DS60001156H-page 240 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times bit 7-0 * * * 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = `1' (RTCCON<15>) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. This register is only reset on a Power-on Reset (POR). 2009-2013 Microchip Technology Inc. DS60001156H-page 241 PIC32MX5XX/6XX/7XX REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 -- -- R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- SEC10<3:0> R/W-x R/W-x SEC01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as `0' Note: This register is only writable when RTCWREN = 1 (RTCCON<3>). DS60001156H-page 242 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x YEAR01<3:0> MONTH10<3:0> R/W-x R/W-x U-0 U-0 -- -- R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x -- -- DAY10<3:0> R/W-x R/W-x DAY01<3:0> R/W-x R/W-x WDAY01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as `0' bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6 Note: This register is only writable when RTCWREN = 1 (RTCCON<3>). 2009-2013 Microchip Technology Inc. DS60001156H-page 243 PIC32MX5XX/6XX/7XX REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 -- -- R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- SEC10<3:0> R/W-x R/W-x SEC01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as `0' DS60001156H-page 244 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 21-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 R/W-x R/W-x -- -- -- -- MONTH10<3:0> R/W-x MONTH01<3:0> DAY10<1:0> R/W-x R/W-x DAY01<3:0> R/W-x R/W-x WDAY01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as `0' bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6 2009-2013 Microchip Technology Inc. DS60001156H-page 245 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 246 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital Converter (ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 1 Msps conversion speed * Up to 16 analog input pins * External voltage reference input pins * One unipolar, differential Sample and Hold (S&H) circuit FIGURE 22-1: * * * * * * Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable buffer fill modes Eight conversion result format options Operation during Sleep and Idle modes A block diagram of the 10-bit ADC is illustrated in Figure 22-1. The 10-bit ADC has up to 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The analog inputs are connected through two multiplexers (MUXs) to one S&H. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1). The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight 32-bit output formats when it is read from the result buffer. ADC1 MODULE BLOCK DIAGRAM VREF+(1) AVDD VREF-(1) AVSS VCFG<2:0> AN0 ADC1BUF0 ADC1BUF1 AN15 S&H Channel Scan VREFH VREFL ADC1BUF2 + CH0SB<4:0> CH0SA<4:0> - SAR ADC CSCNA AN1 ADC1BUFE VREFL ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs. 2009-2013 Microchip Technology Inc. DS60001156H-page 247 PIC32MX5XX/6XX/7XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC 2 1 TAD ADCS<7:0> 0 8 TPB ADC Conversion Clock Multiplier 2, 4,..., 512 DS60001156H-page 248 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 22.1 Control Registers REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- SIDL -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CLRASAM -- ASAM ON SSRC<2:0> FORM<2:0> R/W-0, HSC (2) SAMP R/C-0, HSC (3) DONE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: ADC Operating Mode bit(1) 1 = ADC module is operating 0 = ADC module is not operating bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as `0' bit 10-8 FORM<2:0>: Data Output Format bits 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. If ASAM = 0, software can write a `1' to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC<2:0> = 000, software can write a `0' to end sampling and start conversion. If SSRC<2:0> `000', this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a `0' to clear this bit (a write of `1' is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. 2: 3: 2009-2013 Microchip Technology Inc. DS60001156H-page 249 PIC32MX5XX/6XX/7XX REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing the SAMP bit ends sampling and starts conversion bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 Unimplemented: Read as `0' bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit(2) 1 = The ADC S&H circuit is sampling 0 = The ADC S&H circuit is holding When ASAM = 0, writing `1' to this bit starts sampling. When SSRC<2:0> = 000, writing `0' to this bit will end sampling and start conversion. bit 0 DONE: Analog-to-Digital Conversion Status bit(3) Clearing this bit will not affect any operation in progress. 1 = Analog-to-digital conversion is done 0 = Analog-to-digital conversion is not done or has not started Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. If ASAM = 0, software can write a `1' to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC<2:0> = 000, software can write a `0' to end sampling and start conversion. If SSRC<2:0> `000', this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a `0' to clear this bit (a write of `1' is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. 2: 3: DS60001156H-page 250 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 22-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL -- CSCNA -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS -- R/W-0 SMPI<3:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5-2 Bit Value VREFH VREFL 1xx 011 010 001 AVDD External VREF+ pin AVDD External VREF+ pin AVss External VREF- pin External VREF- pin AVSS 000 AVDD AVss OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode Positive and negative inputs of the S&H circuit are connected to VREFL. 0 = Disable Offset Calibration mode The inputs to the S&H circuit are controlled by AD1CHS or AD1CSSL. Unimplemented: Read as `0' CSCNA: Input Scan Select bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit Only valid when BUFM = 1. 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as `0' SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence * * * bit 1 bit 0 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses Sample A input multiplexer settings for first sample, and then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples 0 = Always use Sample A input multiplexer settings 2009-2013 Microchip Technology Inc. DS60001156H-page 251 PIC32MX5XX/6XX/7XX REGISTER 22-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 U-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC -- -- R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ADRC: ADC Conversion Clock Source bit 1 = Clock derived from FRC 0 = Clock derived from Peripheral Bus Clock (PBCLK) bit 14-13 Unimplemented: Read as `0' bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 = 31 TAD * * * 00001 = 1 TAD 00000 = 0 TAD (Not allowed) bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 =TPB * 2 * (ADCS<7:0> + 1) = 512 * TPB = TAD * * * 00000001 =TPB * 2 * (ADCS<7:0> + 1) = 4 * TPB = TAD 00000000 =TPB * 2 * (ADCS<7:0> + 1) = 2 * TPB = TAD Note 1: 2: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111. This bit is not used if the ADRC bit (AD1CON3<15>) = 1. DS60001156H-page 252 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 22-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 U-0 U-0 U-0 CH0NB -- -- -- R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 CH0SB<3:0> R/W-0 U-0 U-0 U-0 CH0NA -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- CH0SA<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 CH0NB: Negative Input Select bit for Sample B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 30-28 Unimplemented: Read as `0' bit 27-24 CH0SB<3:0>: Positive Input Select bits for Sample B 1111 = Channel 0 positive input is AN15 * * * 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 22-20 Unimplemented: Read as `0' bit 19-16 CH0SA<3:0>: Positive Input Select bits for Sample A Multiplexer Setting 1111 = Channel 0 positive input is AN15 * * * 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 bit 15-0 Unimplemented: Read as `0' 2009-2013 Microchip Technology Inc. x = Bit is unknown DS60001156H-page 253 PIC32MX5XX/6XX/7XX REGISTER 22-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits(1) 1 = Select ANx for input scan 0 = Skip ANx for input scan Note 1: CSSL = ANx, where `x' = 0-15. DS60001156H-page 254 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 23.0 CONTROLLER AREA NETWORK (CAN) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. "Controller Area Network (CAN)" (DS60001154) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Controller Area Network (CAN) module supports the following key features: * Standards Compliance: - Full CAN 2.0B compliance - Programmable bit rate up to 1 Mbps * Message Reception and Transmission: - 32 message FIFOs - Each FIFO can have up to 32 messages for a total of 1024 messages - FIFO can be a transmit message FIFO or a receive message FIFO - User-defined priority levels for message FIFOs used for transmission - 32 acceptance filters for message filtering - Four acceptance filter mask registers for message filtering - Automatic response to remote transmit request - DeviceNetTM addressing support * Additional Features: - Loopback, Listen All Messages, and Listen Only modes for self-test, system diagnostics and bus monitoring - Low-power operating modes - CAN module is a bus master on the PIC32 system bus - Use of DMA is not required - Dedicated time-stamp timer - Dedicated DMA channels - Data-only Message Reception mode Figure 23-1 illustrates the general structure of the CAN module. FIGURE 23-1: PIC32 CAN MODULE BLOCK DIAGRAM CxTX 32 Filters 4 Masks CPU CxRX CAN Module Up to 32 Message Buffers System Bus Message Buffer Size 2 or 4 Words System RAM Message Buffer 31 Message Buffer 31 Message Buffer 31 Message Buffer 1 Message Buffer 1 Message Buffer 1 Message Buffer 0 Message Buffer 0 Message Buffer 0 FIFO1 FIFO31 FIFO0 CAN Message FIFO (up to 32 FIFOs) 2009-2013 Microchip Technology Inc. DS60001156H-page 255 PIC32MX5XX/6XX/7XX REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 CiCON: CAN MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 S/HC-0 R/W-1 -- -- -- -- ABAT R-0 R-0 R-1 OPMOD<2:0> R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 REQOP<2:0> R/W-0 U-0 U-0 U-0 CANCAP -- -- -- U-0 -- U-0 R-0 U-0 U-0 U-0 U-0 R/W-0 ON(1) -- SIDLE -- CANBUSY -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- Legend: HC = Hardware Clear DNCNT<4:0> S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 Unimplemented: Read as `0' bit 27 ABAT: Abort All Pending Transmissions bit 1 = Signal all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions aborted bit 26-24 REQOP<2:0>: Request Operation Mode bits 111 = Set Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Set Configuration mode 011 = Set Listen Only mode 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode bit 23-21 OPMOD<2:0>: Operation Mode Status bits 111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit 1 = CANTMR value is stored on valid message reception and is stored with the message 0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power bit 19-16 Unimplemented: Read as `0' bit 15 ON: CAN On bit(1) 1 = CAN module is enabled 0 = CAN module is disabled bit 14 Unimplemented: Read as `0' Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the current transaction and responds to this request. The user application should poll the CANBUSY bit to verify that the request has been honored. DS60001156H-page 256 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED) bit 13 SIDLE: CAN Stop in Idle bit 1 = CAN Stops operation when system enters Idle mode 0 = CAN continues operation when system enters Idle mode bit 12 Unimplemented: Read as `0' bit 11 CANBUSY: CAN Module is Busy bit 1 = The CAN module is active 0 = The CAN module is completely disabled bit 10-5 Unimplemented: Read as `0' bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits 10011-11111 = Invalid Selection (compare up to 18-bits of data with EID) 10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>) * * * 00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>) 00000 = Do not compare data bytes Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the current transaction and responds to this request. The user application should poll the CANBUSY bit to verify that the request has been honored. 2009-2013 Microchip Technology Inc. DS60001156H-page 257 PIC32MX5XX/6XX/7XX REGISTER 23-2: Bit Range 31:24 23:16 15:8 7:0 CiCFG: CAN BAUD RATE CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- WAKFIL -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) SEG2PHTS R/W-0 SAM (2) R/W-0 SEG1PH<2:0> R/W-0 R/W-0 SJW<1:0>(3) Legend: SEG2PH<2:0>(1,4) R/W-0 R/W-0 PRSEG<2:0> R/W-0 R/W-0 BRP<5:0> HC = Hardware Clear S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-23 Unimplemented: Read as `0' bit 22 WAKFIL: CAN Bus Line Filter Enable bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 21-19 Unimplemented: Read as `0' bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits(1,4) 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ bit 15 SEG2PHTS: Phase Segment 2 Time Select bit(1) 1 = Freely programmable 0 = Maximum of SEG1PH or Information Processing Time, whichever is greater bit 14 SAM: Sample of the CAN Bus Line bit(2) 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits(4) 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ Note 1: 2: 3: 4: Note: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically. 3 Time bit sampling is not allowed for BRP < 2. SJW SEG2PH. The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7). This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (CiCON<23:21>) = 100). DS60001156H-page 258 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED) bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4) 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3) 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FSYS 111110 = TQ = (2 x 63)/FSYS * * * 000001 = TQ = (2 x 2)/FSYS 000000 = TQ = (2 x 1)/FSYS Note 1: 2: 3: 4: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically. 3 Time bit sampling is not allowed for BRP < 2. SJW SEG2PH. The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7). Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (CiCON<23:21>) = 100). 2009-2013 Microchip Technology Inc. DS60001156H-page 259 PIC32MX5XX/6XX/7XX REGISTER 23-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 CiINT: CAN INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 IVRIE WAKIE CERRIE SERRIE RBOVIE -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- MODIE CTMRIE RBIE TBIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SERRIF (1) IVRIF WAKIF CERRIF RBOVIF -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- MODIF CTMRIF RBIF TBIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 29 CERRIE: CAN Bus Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 28 SERRIE: System Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled x = Bit is unknown bit 26-20 Unimplemented: Read as `0' bit 19 MODIE: Mode Change Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 17 RBIE: Receive Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 16 TBIE: Transmit Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 15 IVRIF: Invalid Message Received Interrupt Flag bit 1 = An invalid messages interrupt has occurred 0 = An invalid message interrupt has not occurred Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit (CiCON<15>). DS60001156H-page 260 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED) bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = A bus wake-up activity interrupt has occurred 0 = A bus wake-up activity interrupt has not occurred bit 13 CERRIF: CAN Bus Error Interrupt Flag bit 1 = A CAN bus error has occurred 0 = A CAN bus error has not occurred bit 12 SERRIF: System Error Interrupt Flag bit 1 = A system error occurred (typically an illegal address was presented to the system bus) 0 = A system error has not occurred bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit 1 = A receive buffer overflow has occurred 0 = A receive buffer overflow has not occurred bit 10-4 Unimplemented: Read as `0' bit 3 MODIF: CAN Mode Change Interrupt Flag bit 1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP) 0 = A CAN module mode change has not occurred bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit 1 = A CAN timer (CANTMR) overflow has occurred 0 = A CAN timer (CANTMR) overflow has not occurred bit 1 RBIF: Receive Buffer Interrupt Flag bit 1 = A receive buffer interrupt is pending 0 = A receive buffer interrupt is not pending bit 0 TBIF: Transmit Buffer Interrupt Flag bit 1 = A transmit buffer interrupt is pending 0 = A transmit buffer interrupt is not pending Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit (CiCON<15>). 2009-2013 Microchip Technology Inc. DS60001156H-page 261 PIC32MX5XX/6XX/7XX REGISTER 23-4: Bit Range CiVEC: CAN INTERRUPT CODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 23:16 15:8 7:0 -- -- -- U-0 R-1 R-0 FILHIT<4:0> R-0 ICODE<6:0>(1) -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as `0' bit 12-8 FILHIT<4:0>: Filter Hit Number bit 11111 = Filter 31 11110 = Filter 30 * * * 00001 = Filter 1 00000 = Filter 0 bit 7 Unimplemented: Read as `0' bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1) 1111111 = Reserved * * * 1001001 = Reserved 1001000 = Invalid message received (IVRIF) 1000111 = CAN module mode change (MODIF) 1000110 = CAN timestamp timer (CTMRIF) 1000101 = Bus bandwidth error (SERRIF) 1000100 = Address error interrupt (SERRIF) 1000011 = Receive FIFO overflow interrupt (RBOVIF) 1000010 = Wake-up interrupt (WAKIF) 1000001 = Error Interrupt (CERRIF) 1000000 = No interrupt 0111111 = Reserved * * * 0100000 = Reserved 0011111 = FIFO31 Interrupt (CiFSTAT<31> set) 0011110 = FIFO30 Interrupt (CiFSTAT<30> set) * * * 0000001 = FIFO1 Interrupt (CiFSTAT<1> set) 0000000 = FIFO0 Interrupt (CiFSTAT<0> set) Note 1: These bits are only updated for enabled interrupts. DS60001156H-page 262 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-5: Bit Range 31:24 23:16 15:8 7:0 CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 -- -- TXBO TXBP RXBP TXWARN RXWARN EWARN R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> R-0 RERRCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-22 Unimplemented: Read as `0' bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT 256) bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT 128) bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT 128) bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT 96) bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT 96) bit 16 EWARN: Transmitter or Receiver is in Error State Warning bit 15-8 TERRCNT<7:0>: Transmit Error Counter bit 7-0 RERRCNT<7:0>: Receive Error Counter REGISTER 23-6: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 CiFSTAT: CAN FIFO STATUS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 FIFOIP<31:0>: FIFOn Interrupt Pending bits 1 = One or more enabled FIFO interrupts are pending 0 = No FIFO interrupts are pending 2009-2013 Microchip Technology Inc. DS60001156H-page 263 PIC32MX5XX/6XX/7XX REGISTER 23-7: Bit Range CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R-0 R-0 R-0 R-0 R-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 Bit 26/18/10/2 Bit 25/17/9/1 R-0 R-0 RXOVF26 RXOVF25 R-0 Bit 24/16/8/0 R-0 RXOVF24 R-0 R-0 R-0 R-0 R-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 RXOVF18 RXOVF17 R-0 RXOVF16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown RXOVF<31:0>: FIFOn Receive Overflow Interrupt Pending bit 1 = FIFO has overflowed 0 = FIFO has not overflowed REGISTER 23-8: Bit Range 31:24 CiTMR: CAN TIMER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CANTS<15:8> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 CANTS<7:0> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CANTSPRE<15:8> 7:0 R/W-0 R/W-0 CANTSPRE<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit (CiCON<20>) is set. bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits 1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks * * * 0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock Note 1: 2: CiTMR will be paused when CANCAP = 0. The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected). DS60001156H-page 264 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-9: Bit Range 31:24 23:16 15:8 7:0 CiRXMn: CAN ACCEPTANCE FILTER MASK `n' REGISTER (n = 0, 1, 2 OR 3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SID<10:3> R/W-0 R/W-0 R/W-0 SID<2:0> U-0 R/W-0 U-0 -- MIDE -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EID<17:16> EID<15:8> R/W-0 EID<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-21 SID<10:0>: Standard Identifier bits 1 = Include the SIDx bit in filter comparison 0 = The SIDx bit is a `don't care' in filter operation x = Bit is unknown bit 20 Unimplemented: Read as `0' bit 19 MIDE: Identifier Receive Mode bit 1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter 0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID)) bit 18 Unimplemented: Read as `0' bit 17-0 EID<17:0>: Extended Identifier bits 1 = Include the EIDx bit in filter comparison 0 = The EIDx bit is a `don't care' in filter operation Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (CiCON<23:21>) = 100). 2009-2013 Microchip Technology Inc. DS60001156H-page 265 PIC32MX5XX/6XX/7XX REGISTER 23-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN3 R/W-0 23:16 FLTEN2 R/W-0 15:8 FLTEN1 R/W-0 7:0 FLTEN0 MSEL3<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL2<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL1<1:0> R/W-0 Bit 25/17/9/1 FSEL3<4:0> MSEL2<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL1<4:0> MSEL0<1:0> R/W-0 FSEL0<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN3: Filter 3 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL3<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 x = Bit is unknown * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN2: Filter 2 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL2<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 266 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED) bit 15 FLTEN1: Filter 1 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL1<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN0: Filter 0 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL0<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 267 PIC32MX5XX/6XX/7XX REGISTER 23-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN7 R/W-0 23:16 FLTEN6 R/W-0 15:8 FLTEN5 R/W-0 7:0 FLTEN4 MSEL7<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL6<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL5<1:0> R/W-0 Bit 25/17/9/1 FSEL7<4:0> MSEL6<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL5<4:0> MSEL4<1:0> R/W-0 FSEL4<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown FLTEN7: Filter 7 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL7<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN6: Filter 6 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL6<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 268 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED) bit 15 FLTEN5: Filter 17 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL5<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN4: Filter 4 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL4<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 269 PIC32MX5XX/6XX/7XX REGISTER 23-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN11 R/W-0 23:16 FLTEN10 R/W-0 15:8 FLTEN9 R/W-0 7:0 FLTEN8 MSEL11<1:0> R/W-0 FSEL11<4:0> R/W-0 R/W-0 R/W-0 MSEL10<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL9<1:0> R/W-0 R/W-0 FSEL10<4:0> R/W-0 FSEL9<4:0> R/W-0 MSEL8<1:0> R/W-0 FSEL8<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN11: Filter 11 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL11<1:0>: Filter 11 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL11<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 x = Bit is unknown * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN10: Filter 10 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL10<1:0>: Filter 10 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL10<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 270 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED) bit 15 FLTEN9: Filter 9 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL9<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN8: Filter 8 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL8<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 271 PIC32MX5XX/6XX/7XX REGISTER 23-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN15 R/W-0 23:16 FLTEN14 R/W-0 15:8 FLTEN13 R/W-0 7:0 FLTEN12 MSEL15<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL14<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL13<1:0> R/W-0 Bit 25/17/9/1 FSEL15<4:0> MSEL14<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL13<4:0> R/W-0 MSEL12<1:0> R/W-0 FSEL12<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN15: Filter 15 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL15<1:0>: Filter 15 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL15<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 x = Bit is unknown * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN14: Filter 14 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL14<1:0>: Filter 14 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL14<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 272 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED) bit 15 FLTEN13: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL13<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN12: Filter 12 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL12<1:0>: Filter 12 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL12<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 273 PIC32MX5XX/6XX/7XX ,4 REGISTER 23-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 FLTEN19 R/W-0 23:16 FLTEN18 R/W-0 15:8 FLTEN17 R/W-0 7:0 FLTEN16 MSEL19<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL18<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL17<1:0> R/W-0 Bit 25/17/9/1 FSEL19<4:0> MSEL18<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL17<4:0> R/W-0 MSEL16<1:0> R/W-0 FSEL16<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN19: Filter 19 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL19<1:0>: Filter 19 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL19<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 x = Bit is unknown * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN18: Filter 18 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL18<1:0>: Filter 18 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL18<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 274 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED) bit 15 FLTEN17: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL17<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN16: Filter 16 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL16<1:0>: Filter 16 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL16<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 275 PIC32MX5XX/6XX/7XX REGISTER 23-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN23 R/W-0 23:16 FLTEN22 R/W-0 15:8 FLTEN21 R/W-0 7:0 FLTEN20 MSEL23<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL22<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL21<1:0> R/W-0 Bit 25/17/9/1 FSEL23<4:0> MSEL22<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL21<4:0> R/W-0 MSEL20<1:0> R/W-0 FSEL20<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 FLTEN23: Filter 23 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL23<1:0>: Filter 23 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL23<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 x = Bit is unknown * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN22: Filter 22 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL22<1:0>: Filter 22 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL22<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 276 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED) bit 15 FLTEN21: Filter 21 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL21<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN20: Filter 20 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL20<1:0>: Filter 20 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL20<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 277 PIC32MX5XX/6XX/7XX REGISTER 23-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN27 R/W-0 23:16 FLTEN26 R/W-0 15:8 FLTEN25 R/W-0 7:0 FLTEN24 MSEL27<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL26<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL25<1:0> R/W-0 Bit 25/17/9/1 FSEL27<4:0> MSEL26<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL25<4:0> R/W-0 MSEL24<1:0> R/W-0 FSEL24<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown FLTEN27: Filter 27 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL27<1:0>: Filter 27 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL27<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN26: Filter 26 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL26<1:0>: Filter 26 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL26<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 278 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED) bit 15 FLTEN25: Filter 25 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL25<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN24: Filter 24 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL24<1:0>: Filter 24 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL24<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 279 PIC32MX5XX/6XX/7XX REGISTER 23-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN31 R/W-0 23:16 FLTEN30 R/W-0 15:8 FLTEN29 R/W-0 7:0 FLTEN28 MSEL31<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL30<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL29<1:0> R/W-0 Bit 25/17/9/1 FSEL31<4:0> MSEL30<1:0> R/W-0 Bit 26/18/10/2 R/W-0 FSEL29<4:0> R/W-0 MSEL28<1:0> R/W-0 FSEL28<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown FLTEN31: Filter 31 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 30-29 MSEL31<1:0>: Filter 31 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL31<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN30: Filter 30Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL30<1:0>: Filter 30Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL30<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. DS60001156H-page 280 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED) bit 15 FLTEN29: Filter 29 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL29<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 7 FLTEN28: Filter 28 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 6-5 MSEL28<1:0>: Filter 28 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 4-0 FSEL28<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 * * * 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is `0'. 2009-2013 Microchip Technology Inc. DS60001156H-page 281 PIC32MX5XX/6XX/7XX REGISTER 23-18: CiRXFn: CAN ACCEPTANCE FILTER `n' REGISTER 7 (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<10:3> R/W-x R/W-x R/W-x SID<2:0> U-0 R/W-0 U-0 -- EXID -- R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<17:16> EID<15:8> R/W-x EID<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-21 SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be `1' to match filter 0 = Message address bit SIDx must be `0' to match filter bit 20 Unimplemented: Read as `0' bit 19 EXID: Extended Identifier Enable bits 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses bit 18 Unimplemented: Read as `0' bit 17-0 EID<17:0>: Extended Identifier bits 1 = Message address bit EIDx must be `1' to match filter 0 = Message address bit EIDx must be `0' to match filter Note: This register can only be modified when the filter is disabled (FLTENn = 0). DS60001156H-page 282 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1) CiFIFOBA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<15:8> R/W-0 CiFIFOBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits These bits define the base address of all message buffers. Individual message buffers are located based on the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-only and read as `0', forcing the messages to be 32-bit word-aligned in device RAM. Note 1: This bit is unimplemented and will always read `0', which forces word-alignment of messages. Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (CiCON<23:21>) = 100). 2009-2013 Microchip Technology Inc. DS60001156H-page 283 PIC32MX5XX/6XX/7XX REGISTER 23-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER `n' (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- U-0 S/HC-0 S/HC-0 U-0 U-0 FSIZE<4:0>(1) R/W-0 DONLY U-0 (1) U-0 -- FRESET UINC -- -- -- -- R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as `0' bit 20-16 FSIZE<4:0>: FIFO Size bits(1) 11111 = FIFO is 32 messages deep * * * 00010 = FIFO is 3 messages deep 00001 = FIFO is 2 messages deep 00000 = FIFO is 1 message deep bit 15 Unimplemented: Read as `0' bit 14 FRESET: FIFO Reset bits 1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should poll whether this bit is clear before taking any action. 0 = No effect bit 13 UINC: Increment Head/Tail bit TXEN = 1: (FIFO configured as a Transmit FIFO) When this bit is set the FIFO head will increment by a single message TXEN = 0: (FIFO configured as a Receive FIFO) When this bit is set the FIFO tail will increment by a single message bit 12 DONLY: Store Message Data Only bit(1) TXEN = 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect. TXEN = 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO 0 = Full message is stored, including identifier bit 11-8 Unimplemented: Read as `0' bit 7 TXEN: TX/RX Buffer Selection bit 1 = FIFO is a Transmit FIFO 0 = FIFO is a Receive FIFO Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits (CiCON<23:21>) = 100). This bit is updated when a message completes (or aborts) or when the FIFO is reset. This bit is reset on any read of this register or when the FIFO is reset. 2: 3: DS60001156H-page 284 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER `n' (n = 0 THROUGH 31) bit 6 TXABAT: Message Aborted bit(2) 1 = Message was aborted 0 = Message completed successfully bit 5 TXLARB: Message Lost Arbitration bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Error Detected During Transmission bit(3) 1 = A bus error occured while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Message Send Request TXEN = 1: (FIFO configured as a Transmit FIFO) Setting this bit to `1' requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to `0' while set (`1') will request a message abort. TXEN = 0: (FIFO configured as a receive FIFO) This bit has no effect. bit 2 RTREN: Auto RTR Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXPR<1:0>: Message Transmit Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits (CiCON<23:21>) = 100). This bit is updated when a message completes (or aborts) or when the FIFO is reset. This bit is reset on any read of this register or when the FIFO is reset. 2: 3: 2009-2013 Microchip Technology Inc. DS60001156H-page 285 PIC32MX5XX/6XX/7XX REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER `n' (n = 0 THROUGH 31) Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 31:24 23:16 15:8 7:0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- TXNFULLIE TXHALFIE TXEMPTYIE U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- -- -- TXNFULLIF(1) TXHALFIF TXEMPTYIF(1) U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0 -- -- -- -- RXOVFLIF RXFULLIF(1) RXHALFIF(1) RXNEMPTYIF(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as `0' bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit 1 = Interrupt enabled for FIFO not full 0 = Interrupt disabled for FIFO not full bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO empty 0 = Interrupt disabled for FIFO empty bit 23-20 Unimplemented: Read as `0' bit 19 RXOVFLIE: Overflow Interrupt Enable bit 1 = Interrupt enabled for overflow event 0 = Interrupt disabled for overflow event bit 18 RXFULLIE: Full Interrupt Enable bit 1 = Interrupt enabled for FIFO full 0 = Interrupt disabled for FIFO full bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full bit 16 RXNEMPTYIE: Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO not empty 0 = Interrupt disabled for FIFO not empty bit 15-11 Unimplemented: Read as `0' bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is not full 0 = FIFO is full TXEN = 0: (FIFO configured as a receive buffer) Unused, reads `0' Note 1: This bit is read-only and reflects the status of the FIFO. DS60001156H-page 286 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER `n' (n = 0 THROUGH 31) bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is half full 0 = FIFO is > half full TXEN = 0: (FIFO configured as a receive buffer) Unused, reads `0' bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is empty 0 = FIFO is not empty, at least 1 message queued to be transmitted TXEN = 0: (FIFO configured as a receive buffer) Unused, reads `0' bit 7-4 Unimplemented: Read as `0' bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = Overflow event has occurred 0 = No overflow event occured bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = FIFO is full 0 = FIFO is not full bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = FIFO is half full 0 = FIFO is < half full bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) Unused, reads `0' TXEN = 0: (FIFO configured as a receive buffer) 1 = FIFO is not empty, has at least 1 message 0 = FIFO is empty Note 1: This bit is read-only and reflects the status of the FIFO. 2009-2013 Microchip Technology Inc. DS60001156H-page 287 PIC32MX5XX/6XX/7XX REGISTER 23-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER `n' (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-x R-x R-x Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-0(1) R-0(1) CiFIFOUAn<31:24> R-x R-x R-x R-x R-x CiFIFOUAn<23:16> R-x R-x R-x R-x R-x CiFIFOUAn<15:8> R-x R-x R-x R-x R-x CiFIFOUAn<7:0> Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 28/20/12/4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CiFIFOUAn<31:0>: CAN FIFO User Address bits TXEN = 1: (FIFO configured as a transmit buffer) A read of this register will return the address where the next message is to be written (FIFO head). TXEN = 0: (FIFO configured as a receive buffer) A read of this register will return the address where the next message is to be read (FIFO tail). Note 1: Note: This bit will always read `0', which forces byte-alignment of messages. This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when the module is not in Configuration mode. REGISTER 23-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER `n' (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 -- -- -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set CiFIFOCI<4:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-5 Unimplemented: Read as `0' bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits TXEN = 1: (FIFO configured as a transmit buffer) A read of this register will return an index to the message that the FIFO will next attempt to transmit. TXEN = 0: (FIFO configured as a receive buffer) A read of this register will return an index to the message that the FIFO will use to save the next message. DS60001156H-page 288 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 24.0 ETHERNET CONTROLLER Key features of the Ethernet Controller include: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. "Ethernet Controller" (DS60001155) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Ethernet controller is a bus master module that interfaces with an off-chip Physical Layer (PHY) to implement a complete Ethernet node in a system. Figure 24-1 illustrates a block diagram of the Ethernet controller. ETHERNET CONTROLLER BLOCK DIAGRAM TX FIFO FIGURE 24-1: * * Supports 10/100 Mbps data transfer rates Supports full-duplex and half-duplex operation Supports RMII and MII PHY interface Supports MIIM PHY management interface Supports both manual and automatic Flow Control RAM descriptor-based DMA operation for both receive and transmit path Fully configurable interrupts Configurable receive packet filtering - CRC check - 64-byte pattern match - Broadcast, multicast and unicast packets - Magic PacketTM - 64-bit hash table - Runt packet Supports packet payload checksum calculation Supports various hardware statistics counters TX DMA TX BM TX Bus Master TX Function TX Flow Control System Bus RX DMA RX FIFO MII/RMII IF RX Flow Control RX BM External PHY MAC RX Bus Master RX Filter RX Function Checksum Fast Peripheral Bus DMA Control Registers Ethernet DMA MIIM IF MAC Control and Configuration Registers Host IF Ethernet Controller 2009-2013 Microchip Technology Inc. DS60001156H-page 289 PIC32MX5XX/6XX/7XX Table 24-1, Table 24-2, Table 24-3 and Table 24-4 show four interfaces and the associated pins that can be used with the Ethernet Controller. TABLE 24-1: MII MODE DEFAULT INTERFACE SIGNALS (FMIIEN = 1, FETHIO = 1) Pin Name Description TABLE 24-3: Pin Name MII MODE ALTERNATE INTERFACE SIGNALS (FMIIEN = 1, FETHIO = 0) Description AEMDC Management Clock AEMDIO Management I/O AETXCLK Transmit Clock Management Clock AETXEN Transmit Enable EMDIO Management I/O AETXD0 Transmit Data ETXCLK Transmit Clock AETXD1 Transmit Data ETXEN Transmit Enable AETXD2 Transmit Data ETXD0 Transmit Data AETXD3 Transmit Data ETXD1 Transmit Data AETXERR Transmit Error ETXD2 Transmit Data AERXCLK Receive Clock ETXD3 Transmit Data AERXDV Receive Data Valid ETXERR Transmit Error AERXD0 Receive Data ERXCLK Receive Clock AERXD1 Receive Data ERXDV Receive Data Valid AERXD2 Receive Data ERXD0 Receive Data AERXD3 Receive Data ERXD1 Receive Data AERXERR Receive Error ERXD2 Receive Data AECRS Carrier Sense ERXD3 Receive Data AECOL Collision Indication EMDC ERXERR Receive Error ECRS Carrier Sense ECOL Collision Indication TABLE 24-2: RMII MODE DEFAULT INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 1) Pin Name EMDC Description Management Clock EMDIO Management I/O ETXEN Transmit Enable ETXD0 Transmit Data ETXD1 Transmit Data EREFCLK Reference Clock ECRSDV Carrier Sense - Receive Data Valid ERXD0 Receive Data ERXD1 Receive Data ERXERR Note: Receive Error Note: The MII mode Alternate Interface is not available on 64-pin devices. TABLE 24-4: Pin Name RMII MODE ALTERNATE INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 0) Description AEMDC Management Clock AEMDIO Management I/O AETXEN Transmit Enable AETXD0 Transmit Data AETXD1 Transmit Data AEREFCLK Reference Clock AECRSDV Carrier Sense - Receive Data Valid AERXD0 Receive Data AERXD1 Receive Data AERXERR Receive Error Ethernet controller pins that are not used by selected interface can be used by other peripherals. DS60001156H-page 290 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 24.1 Control Registers REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 Bit 31/23/15/7 R/W-0 Bit Bit 30/22/14/6 29/21/13/5 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTV<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTV<7:0> R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ON -- SIDL -- -- -- TXRTS RXEN(1) R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 AUTOFC -- -- MANFC -- -- -- BUFCDEC Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-16 x = Bit is unknown PTV<15:0>: PAUSE Timer Value bits PAUSE Timer Value used for Flow Control. This register should only be written when RXEN (ETHCON1<8>) is not set. These bits are only used for Flow Control operations. bit 15 ON: Ethernet ON bit 1 = Ethernet module is enabled 0 = Ethernet module is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Ethernet Stop in Idle Mode bit 1 = Ethernet module transfers are paused during Idle mode 0 = Ethernet module transfers continue during Idle mode bit 12-10 Unimplemented: Read as `0' bit 9 TXRTS: Transmit Request to Send bit 1 = Activate the TX logic and send the packet(s) defined in the TX EDT 0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware) After the bit is written with a `1', it will clear to a `0' whenever the transmit logic has finished transmitting the requested packets in the Ethernet Descriptor Table (EDT). If a `0' is written by the CPU, the transmit logic finishes the current packet's transmission and then stops any further. This bit only affects TX operations. bit 8 RXEN: Receive Enable bit(1) 1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter configuration 0 = Disable RX logic, no packets are received in the RX buffer This bit only affects RX operations. Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The Ethernet Controller must be reinitialized (ON cleared to `0'), and then the RX changes applied. 2009-2013 Microchip Technology Inc. DS60001156H-page 291 PIC32MX5XX/6XX/7XX REGISTER 24-1: bit 7 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED) AUTOFC: Automatic Flow Control bit 1 = Automatic Flow Control is enabled 0 = Automatic Flow Control is disabled Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to automatically enable and disable the Flow Control, respectively. When the number of received buffers BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled. When the BUFCNT falls to the empty watermark, Flow Control is automatically disabled. This bit is only used for Flow Control operations and affects both TX and RX operations. bit 6-5 Unimplemented: Read as `0' bit 4 MANFC: Manual Flow Control bit 1 = Manual Flow Control is enabled 0 = Manual Flow Control is disabled Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 * PTV<15:0>/2 TX clock cycles until the bit is cleared. Note: For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at 25 MHz. When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000 PAUSE timer value to disable Flow Control. This bit is only used for Flow Control operations and affects both TX and RX operations. bit 3-1 Unimplemented: Read as `0' bit 0 BUFCDEC: Descriptor Buffer Count Decrement bit The BUFCDEC bit is a write-1 bit that reads as `0'. When written with a `1', the Descriptor Buffer Counter, BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bit is written, the BUFCNT value will remain unchanged. Writing a `0' will have no effect. This bit is only used for RX operations. Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The Ethernet Controller must be reinitialized (ON cleared to `0'), and then the RX changes applied. DS60001156H-page 292 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-2: Bit Range ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2 Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- -- -- -- RXBUFSZ<3:0> RXBUFSZ<6:4> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as `0' bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits 1111111 = RX data Buffer size for descriptors is 2032 bytes * * * 1100000 = RX data Buffer size for descriptors is 1536 bytes * * * 0000011 = RX data Buffer size for descriptors is 48 bytes 0000010 = RX data Buffer size for descriptors is 32 bytes 0000001 = RX data Buffer size for descriptors is 16 bytes 0000000 = Reserved bit 3-0 Note 1: 2: Unimplemented: Read as `0' This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0. 2009-2013 Microchip Technology Inc. DS60001156H-page 293 PIC32MX5XX/6XX/7XX REGISTER 24-3: Bit Range 31:24 23:16 15:8 7:0 ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 -- -- TXSTADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<7:2> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-2 TXSTADDR<31:2>: Starting Address of First Transmit Descriptor bits This register should not be written while any transmit, receive or DMA operations are in progress. This address must be 4-byte aligned (bits 1-0 must be `00'). bit 1-0 Unimplemented: Read as `0' Note 1: 2: This register is only used for TX operations. This register will be updated by hardware with the last descriptor used by the last successfully transmitted packet. REGISTER 24-4: Bit Range 31:24 23:16 15:8 7:0 ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 -- -- RXSTADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXSTADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXSTADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 RXSTADDR<7:2> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set R/W-0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits This register should not be written while any transmit, receive or DMA operations are in progress. This address must be 4-byte aligned (bits 1-0 must be `00'). bit 1-0 Unimplemented: Read as `0' Note 1: 2: This register is only used for RX operations. This register will be updated by hardware with the last descriptor used by the last successfully transmitted packet. DS60001156H-page 294 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-5: Bit Range ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 HT<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 HT<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<15:8> 7:0 R/W-0 HT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note 1: 2: HT<31:0>: Hash Table Bytes 0-3 bits This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit (ETHRXFC<15>) = 0. REGISTER 24-6: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<63:56> R/W-0 HT<55:48> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<47:40> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<39:32> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note 1: 2: x = Bit is unknown HT<63:32>: Hash Table Bytes 4-7 bits This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit (ETHRXFC<15>) = 0. 2009-2013 Microchip Technology Inc. DS60001156H-page 295 PIC32MX5XX/6XX/7XX REGISTER 24-7: Bit Range 31:24 ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 31-24 bit 23-16 bit 15-8 bit 7-0 Note 1: 2: R/W-0 R/W-0 R/W-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER Bit 24/16/8/0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<63:56> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<55:48> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<47:40> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<39:32> Legend: R = Readable bit -n = Value at POR bit 31-24 bit 23-16 bit 15-8 bit 7-0 R/W-0 This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0. Bit Range 7:0 R/W-0 PMM<31:24>: Pattern Match Mask 3 bits PMM<23:16>: Pattern Match Mask 2 bits PMM<15:8>: Pattern Match Mask 1 bits PMM<7:0>: Pattern Match Mask 0 bits REGISTER 24-8: 15:8 R/W-0 PMM<7:0> Legend: R = Readable bit -n = Value at POR 23:16 R/W-0 PMM<15:8> 7:0 31:24 R/W-0 PMM<23:16> 15:8 Note 1: 2: R/W-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PMM<63:56>: Pattern Match Mask 7 bits PMM<55:48>: Pattern Match Mask 6 bits PMM<47:40>: Pattern Match Mask 5 bits PMM<39:32>: Pattern Match Mask 4 bits This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0. DS60001156H-page 296 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-9: Bit Range 31:24 23:16 15:8 7:0 ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Note 1: 2: U-0 PMCS<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMCS<7:0> Legend: R = Readable bit -n = Value at POR bit 31-16 bit 15-8 bit 7-0 Bit 24/16/8/0 Bit 31/23/15/7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PMCS<15:8>: Pattern Match Checksum 1 bits PMCS<7:0>: Pattern Match Checksum 0 bits This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0. REGISTER 24-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMO<15:8> Legend: R = Readable bit -n = Value at POR bit 31-16 bit 15-0 Note 1: 2: R/W-0 PMO<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PMO<15:0>: Pattern Match Offset 1 bits This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0. 2009-2013 Microchip Technology Inc. DS60001156H-page 297 PIC32MX5XX/6XX/7XX REGISTER 24-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit Bit 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HTEN MPEN -- NOTPM R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCERREN CRCOKEN RUNTERREN RUNTEN UCEN NOTMEEN MCEN BCEN Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set PMMODE<3:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 HTEN: Enable Hash Table Filtering bit 1 = Enable Hash Table Filtering 0 = Disable Hash Table Filtering bit 14 MPEN: Magic PacketTM Enable bit 1 = Enable Magic Packet Filtering 0 = Disable Magic Packet Filtering bit 13 Unimplemented: Read as `0' bit 12 NOTPM: Pattern Match Inversion bit 1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur 0 = The Pattern Match Checksum must match for a successful Pattern Match to occur This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match to occur. bit 11-8 PMMODE<3:0>: Pattern Match Mode bits 1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Packet = Magic Packet)(1,3) 1000 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Hash Table Filter match)(1,2) 0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Broadcast Address)(1) 0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Broadcast Address)(1) 0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Unicast Address)(1) 0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Unicast Address)(1) 0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Station Address)(1) 0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Station Address)(1) 0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1) 0000 = Pattern Match is disabled; pattern match is always unsuccessful Note 1: 2: 3: XOR = True when either one or the other conditions are true, but not both. This Hash Table Filter match is active regardless of the value of the HTEN bit. This Magic Packet Filter match is active regardless of the value of the MPEN bit. Note 1: 2: This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0. DS60001156H-page 298 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER (CONTINUED) bit 7 bit 6 bit 5 bit 4 CRCERREN: CRC Error Collection Enable bit 1 = The received packet CRC must be invalid for the packet to be accepted 0 = Disable CRC Error Collection filtering This bit allows the user to collect all packets that have an invalid CRC. CRCOKEN: CRC OK Enable bit 1 = The received packet CRC must be valid for the packet to be accepted 0 = Disable CRC filtering This bit allows the user to reject all packets that have an invalid CRC. RUNTERREN: Runt Error Collection Enable bit 1 = The received packet must be a runt packet for the packet to be accepted 0 = Disable Runt Error Collection filtering This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as any packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than 64 bytes that has a valid CRC (when CRCOKEN = 1). RUNTEN: Runt Enable bit 1 = The received packet must not be a runt packet for the packet to be accepted 0 = Disable Runt filtering bit 3 This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a size of less than 64 bytes. UCEN: Unicast Enable bit 1 = Enable Unicast Filtering 0 = Disable Unicast Filtering bit 2 This bit allows the user to accept all unicast packets whose Destination Address matches the Station Address. NOTMEEN: Not Me Unicast Enable bit 1 = Enable Not Me Unicast Filtering 0 = Disable Not Me Unicast Filtering bit 1 This bit allows the user to accept all unicast packets whose Destination Address does not match the Station Address. MCEN: Multicast Enable bit 1 = Enable Multicast Filtering 0 = Disable Multicast Filtering bit 0 This bit allows the user to accept all Multicast Address packets. BCEN: Broadcast Enable bit 1 = Enable Broadcast Filtering 0 = Disable Broadcast Filtering This bit allows the user to accept all Broadcast Address packets. Note 1: 2: 3: XOR = True when either one or the other conditions are true, but not both. This Hash Table Filter match is active regardless of the value of the HTEN bit. This Magic Packet Filter match is active regardless of the value of the MPEN bit. Note 1: 2: This register is only used for RX operations. The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0. 2009-2013 Microchip Technology Inc. DS60001156H-page 299 PIC32MX5XX/6XX/7XX REGISTER 24-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 31:24 23:16 RXFWM<7:0> U-0 15:8 7:0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXEWM<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-24 Unimplemented: Read as `0' bit 23-16 RXFWM<7:0>: Receive Full Watermark bits x = Bit is unknown The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when automatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the Empty Watermark Pointer. bit 15-8 Unimplemented: Read as `0' bit 7-0 RXEWM<7:0>: Receive Empty Watermark bits The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full Watermark Pointer. Note: This register is only used for RX operations. DS60001156H-page 300 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- R/W-0 R/W-0 -- R/W-0 TXBUSEIE(1) RXBUSEIE(2) R/W-0 R/W-0 RXDONEIE(2) PKTPENDIE(2) RXACTIE(2) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U-0 -- EWMARKIE(2) FWMARKIE(2) R/W-0 R/W-0 TXDONEIE(1) TXABORTIE(1) RXBUFNAIE(2) RXOVFLWIE(2) U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as `0' bit 14 TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit(1) 1 = Enable TXBUS Error Interrupt 0 = Disable TXBUS Error Interrupt bit 13 RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit(2) 1 = Enable RXBUS Error Interrupt 0 = Disable RXBUS Error Interrupt bit 12-10 Unimplemented: Read as `0' bit 9 EWMARKIE: Empty Watermark Interrupt Enable bit(2) 1 = Enable EWMARK Interrupt 0 = Disable EWMARK Interrupt bit 8 FWMARKIE: Full Watermark Interrupt Enable bit(2) 1 = Enable FWMARK Interrupt 0 = Disable FWMARK Interrupt bit 7 RXDONEIE: Receiver Done Interrupt Enable bit(2) 1 = Enable RXDONE Interrupt 0 = Disable RXDONE Interrupt bit 6 PKTPENDIE: Packet Pending Interrupt Enable bit(2) 1 = Enable PKTPEND Interrupt 0 = Disable PKTPEND Interrupt bit 5 RXACTIE: RX Activity Interrupt Enable bit 1 = Enable RXACT Interrupt 0 = Disable RXACT Interrupt bit 4 Unimplemented: Read as `0' bit 3 TXDONEIE: Transmitter Done Interrupt Enable bit(1) 1 = Enable TXDONE Interrupt 0 = Disable TXDONE Interrupt bit 2 TXABORTIE: Transmitter Abort Interrupt Enable bit(1) 1 = Enable TXABORT Interrupt 0 = Disable TXABORT Interrupt bit 1 RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit(2) 1 = Enable RXBUFNA Interrupt 0 = Disable RXBUFNA Interrupt bit 0 RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit(2) 1 = Enable RXOVFLW Interrupt 0 = Disable RXOVFLW Interrupt Note 1: 2: This bit is only used for TX operations. This bit is only used for RX operations. 2009-2013 Microchip Technology Inc. DS60001156H-page 301 PIC32MX5XX/6XX/7XX REGISTER 24-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 -- TXBUSE RXBUSE -- -- -- EWMARK FWMARK R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 RXDONE PKTPEND RXACT -- TXDONE TXABORT RXBUFNA RXOVFLW Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-15 Unimplemented: Read as `0' bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit 1 = BVCI Bus Error has occurred 0 = BVCI Bus Error has not occurred x = Bit is unknown This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by either a Reset or CPU write of a `1' to the CLR register. bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit 1 = BVCI Bus Error has occurred 0 = BVCI Bus Error has not occurred This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by either a Reset or CPU write of a `1' to the CLR register. bit 12-10 Unimplemented: Read as `0' bit 9 EWMARK: Empty Watermark Interrupt bit 1 = Empty Watermark pointer reached 0 = No interrupt pending This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>) being incremented by hardware. Writing a `0' or a `1' has no effect. bit 8 FWMARK: Full Watermark Interrupt bit 1 = Full Watermark pointer reached 0 = No interrupt pending This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement the BUFCNT counter. Writing a `0' or a `1' has no effect. bit 7 RXDONE: Receive Done Interrupt bit 1 = RX packet was successfully received 0 = No interrupt pending This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU write of a `1' to the CLR register. Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. DS60001156H-page 302 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER bit 6 PKTPEND: Packet Pending Interrupt bit 1 = RX packet pending in memory 0 = RX packet is not pending in memory This bit is set when the BUFCNT counter has a value other than `0'. It is cleared by either a Reset or by writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a `0' or a `1' has no effect. bit 5 RXACT: Receive Activity Interrupt bit 1 = RX packet data was successfully received 0 = No interrupt pending This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset or CPU write of a `1' to the CLR register. bit 4 Unimplemented: Read as `0' bit 3 TXDONE: Transmit Done Interrupt bit 1 = TX packet was successfully sent 0 = No interrupt pending This bit is set when the currently transmitted TX packet completes transmission, and the Transmit Status Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write of a `1' to the CLR register. bit 2 TXABORT: Transmit Abort Condition Interrupt bit 1 = TX abort condition occurred on the last TX packet 0 = No interrupt pending This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons: * * * * * Jumbo TX packet abort Underrun abort Excessive defer abort Late collision abort Excessive collisions abort This bit is cleared by either a Reset or CPU write of a `1' to the CLR register. bit 1 RXBUFNA: Receive Buffer Not Available Interrupt bit 1 = RX Buffer Descriptor Not Available condition has occurred 0 = No interrupt pending This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU write of a `1' to the CLR register. bit 0 RXOVFLW: Receive FIFO Over Flow Error bit 1 = RX FIFO Overflow Error condition has occurred 0 = No interrupt pending RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset or CPU write of a `1' to the CLR register. Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. 2009-2013 Microchip Technology Inc. DS60001156H-page 303 PIC32MX5XX/6XX/7XX REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 BUFCNT<7:0> U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ETHBUSY(1) TXBUSY(2) RXBUSY(2) -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits Number of packet buffers received in memory. Once a packet has been successfully received, this register is incremented by hardware based on the number of descriptors used by the packet. Software decrements the counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet has been read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to increment the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF) when software tries to decrement the register and the register is already at 0x0000. When software attempts to decrement the counter at the same time that the hardware attempts to increment the counter, the counter value will remain unchanged. When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled) awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF. If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at a value of 0xFF. When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated, depending on the value of the ETHIEN bit <PKTPENDIE> register. When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00. Note: BUFCNT will not be cleared when ON is set to `0'. This enables software to continue to utilize and decrement this count. bit 15-8 Unimplemented: Read as `0' bit 7 ETHBUSY: Ethernet Module busy bit(1) 1 = Ethernet logic has been turned on (ON (ETHCON1<15>) = 1) or is completing a transaction 0 = Ethernet logic is idle This bit indicates that the module has been turned on or is completing a transaction after being turned off. bit 6 TXBUSY: Transmit Busy bit(2) 1 = TX logic is receiving data 0 = TX logic is idle This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC. Note 1: 2: This bit will be set when the ON bit (ETHCON1<15>) = 1. This bit will be cleared when the ON bit (ETHCON1<15>) = 0. DS60001156H-page 304 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED) bit 5 RXBUSY: Receive Busy bit(2) 1 = RX logic is receiving data 0 = RX logic is idle This bit indicates that a packet is currently being received. A change in this status bit is not necessarily reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter. bit 4-0 Unimplemented: Read as `0' Note 1: 2: This bit will be set when the ON bit (ETHCON1<15>) = 1. This bit will be cleared when the ON bit (ETHCON1<15>) = 0. 2009-2013 Microchip Technology Inc. DS60001156H-page 305 PIC32MX5XX/6XX/7XX REGISTER 24-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 RXOVFLWCNT<15:8> R/W-0 R/W-0 RXOVFLWCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ<0>) interrupt flag. Note 1: 2: 3: This register is only used for RX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. DS60001156H-page 306 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMTXOKCNT<15:8> R/W-0 R/W-0 FRMTXOKCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits Increment counter for frames successfully transmitted. Note 1: 2: This register is only used for TX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. 3: 2009-2013 Microchip Technology Inc. DS60001156H-page 307 PIC32MX5XX/6XX/7XX REGISTER 24-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 SCOLFRMCNT<15:8> R/W-0 R/W-0 SCOLFRMCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits Increment count for frames that were successfully transmitted on the second try. Note 1: 2: 3: This register is only used for TX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. DS60001156H-page 308 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES STATISTICS REGISTER Bit Range 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MCOLFRMCNT<15:8> R/W-0 7:0 Bit 24/16/8/0 Bit 31/23/15/7 R/W-0 R/W-0 R/W-0 R/W-0 MCOLFRMCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits Increment count for frames that were successfully transmitted after there was more than one collision. Note 1: 2: This register is only used for TX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. 3: 2009-2013 Microchip Technology Inc. DS60001156H-page 309 PIC32MX5XX/6XX/7XX REGISTER 24-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMRXOKCNT<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMRXOKCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 FRMRXOKCNT<15:0>: Frames Received OK Count bits Increment count for frames received successfully by the RX Filter. This count will not be incremented if there is a Frame Check Sequence (FCS) or Alignment error. Note 1: 2: This register is only used for RX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes. 3: DS60001156H-page 310 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FCSERRCNT<15:8> R/W-0 R/W-0 FCSERRCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 FCSERRCNT<15:0>: FCS Error Count bits Increment count for frames received with FCS error and the frame length in bits is an integral multiple of 8 bits. Note 1: 2: This register is only used for RX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should be only done for debug/test purposes. 3: 2009-2013 Microchip Technology Inc. DS60001156H-page 311 PIC32MX5XX/6XX/7XX REGISTER 24-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALGNERRCNT<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 ALGNERRCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 ALGNERRCNT<15:0>: Alignment Error Count bits Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble) Note 1: 2: This register is only used for RX operations. This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are `0'. It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should be only done for debug/test purposes. 3: DS60001156H-page 312 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 RESET RFUN RESET TMCS RESET TFUN R/W-1 R/W-0 SOFT RESET SIM RESET -- -- RESET RMCS U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 LOOPBACK TX PAUSE RX PAUSE PASSALL RX ENABLE -- -- Legend: R = Readable bit -n = Value at POR -- W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 SOFTRESET: Soft Reset bit Setting this bit will put the MACMII in reset. Its default value is `1'. bit 14 SIMRESET: Simulation Reset bit Setting this bit will cause a reset to the random number generator within the Transmit Function. bit 13-12 Unimplemented: Read as `0' bit 11 RESETRMCS: Reset MCS/RX bit Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset. bit 10 RESETRFUN: Reset RX Function bit Setting this bit will put the MAC Receive function logic in reset. bit 9 RESETTMCS: Reset MCS/TX bit Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset. bit 8 RESETTFUN: Reset TX Function bit Setting this bit will put the MAC Transmit function logic in reset. bit 7-5 Unimplemented: Read as `0' bit 4 LOOPBACK: MAC Loopback mode bit 1 = MAC Transmit interface is loop backed to the MAC Receive interface 0 = MAC normal operation bit 3 TXPAUSE: MAC TX Flow Control bit 1 = PAUSE Flow Control frames are allowed to be transmitted 0 = PAUSE Flow Control frames are blocked bit 2 RXPAUSE: MAC RX Flow Control bit 1 = The MAC acts upon received PAUSE Flow Control frames 0 = Received PAUSE Flow Control frames are ignored bit 1 PASSALL: MAC Pass all Receive Frames bit 1 = The MAC will accept all frames regardless of type (Normal vs. Control) 0 = The received Control frames are ignored bit 0 RXENABLE: MAC Receive Enable bit 1 = Enable the MAC receiving of frames 0 = Disable the MAC receiving of frames Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. 2009-2013 Microchip Technology Inc. DS60001156H-page 313 PIC32MX5XX/6XX/7XX REGISTER 24-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 25/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 -- EXCESS DFR BPNOBK OFF NOBK OFF -- -- LONGPRE PUREPRE R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 AUTO PAD(1,2) VLAN PAD(1,2) PAD ENABLE(1,3) CRC ENABLE DELAYCRC HUGEFRM LENGTHCK FULLDPLX Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as `0' bit 14 EXCESSDER: Excess Defer bit 1 = The MAC will defer to carrier indefinitely as per the Standard 0 = The MAC will abort when the excessive deferral limit is reached bit 13 BPNOBKOFF: Backpressure/No Backoff bit 1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit without backoff reducing the chance of further collisions and ensuring transmit packets get sent 0 = The MAC will not remove the backoff bit 12 NOBKOFF: No Backoff bit 1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Backoff algorithm as specified in the Standard 0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm bit 11-10 Unimplemented: Read as `0' bit 9 LONGPRE: Long Preamble Enforcement bit 1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length 0 = The MAC allows any length preamble as per the Standard bit 8 PUREPRE: Pure Preamble Enforcement bit 1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with errors in its preamble is discarded 0 = The MAC does not perform any preamble checking bit 7 AUTOPAD: Automatic Detect Pad Enable bit(1,2) 1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly 0 = The MAC does not perform automatic detection Note 1: 2: 3: Note: Table 24-5 provides a description of the pad function based on the configuration of this register. This bit is ignored if the PADENABLE bit is cleared. This bit is used in conjunction with the AUTOPAD and VLANPAD bits. Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware DS60001156H-page 314 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER bit 6 VLANPAD: VLAN Pad Enable bit(1,2) 1 = The MAC will pad all short frames to 64 bytes and append a valid CRC 0 = The MAC does not perform padding of short frames bit 5 PADENABLE: Pad/CRC Enable bit(1,3) 1 = The MAC will pad all short frames 0 = The frames presented to the MAC have a valid length bit 4 CRCENABLE: CRC Enable1 bit 1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the PADENABLE bit is set. 0 = The frames presented to the MAC have a valid CRC bit 3 DELAYCRC: Delayed CRC bit This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the IEEE 802.3 frames. 1 = Four bytes of header (ignored by the CRC function) 0 = No proprietary header bit 2 HUGEFRM: Huge Frame enable bit 1 = Frames of any length are transmitted and received 0 = Huge frames are not allowed for receive or transmit bit 1 LENGTHCK: Frame Length checking bit 1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported on the transmit/receive statistics vector. 0 = Length/Type field check is not performed bit 0 FULLDPLX: Full-Duplex Operation bit 1 = The MAC operates in Full-Duplex mode 0 = The MAC operates in Half-Duplex mode Note 1: 2: 3: Note: Table 24-5 provides a description of the pad function based on the configuration of this register. This bit is ignored if the PADENABLE bit is cleared. This bit is used in conjunction with the AUTOPAD and VLANPAD bits. Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware TABLE 24-5: PAD OPERATION Type AUTOPAD VLANPAD PADENABLE Any x x 0 No pad, check CRC Any 0 0 1 Pad to 60 Bytes, append CRC Any x 1 1 Pad to 64 Bytes, append CRC Any 1 0 1 If untagged: Pad to 60 Bytes, append CRC If VLAN tagged: Pad to 64 Bytes, append CRC 2009-2013 Microchip Technology Inc. Action DS60001156H-page 315 PIC32MX5XX/6XX/7XX REGISTER 24-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 -- B2BIPKTGP<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-7 Unimplemented: Read as `0' bit 6-0 B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 0.96 s (in 100 Mbps) or 9.6 s (in 10 Mbps). In Half-Duplex mode, the recommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 s (in 100 Mbps) or 9.6 s (in 10 Mbps). Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. DS60001156H-page 316 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 -- U-0 NB2BIPKTGP1<6:0> -- R/W-0 NB2BIPKTGP2<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as `0' bit 14-8 NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits This is a programmable field representing the optional carrierSense window referenced in section 4.2.3.2.1 "Deference" of the IEEE 80.23 Specification. If the carrier is detected during the timing of IPGR1, the MAC defers to the carrier. If, however, the carrier comes after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to the medium. Its range of values is 0x0 to IPGR2. Its recommend value is 0xC (12d). bit 7 Unimplemented: Read as `0' bit 6-0 NB2BIPKTGP2<6:0>: Non-Back-to-Back Interpacket Gap Part 2 bits This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value is 0x12 (18d), which represents the minimum IPG of 0.96 s (in 100 Mbps) or 9.6 s (in 10 Mbps). Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. 2009-2013 Microchip Technology Inc. DS60001156H-page 317 PIC32MX5XX/6XX/7XX REGISTER 24-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY LIMIT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U-0 U-0 U-0 U-0 CWINDOW<5:0> -- -- -- -- R/W-1 R/W-1 RETX<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as `0' bit 13-8 CWINDOW<5:0>: Collision Window bits This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of the window. bit 7-4 Unimplemented: Read as `0' bit 3-0 RETX<3:0>: Retransmission Maximum bits This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts (attemptLimit) to be 0xF (15d). Its default is `0xF'. Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. DS60001156H-page 318 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 MACMAXF<15:8>(1) R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 MACMAXF<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 MACMAXF<15:0>: Maximum Frame Length bits(1) These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter/longer maximum length restriction is desired, program this 16-bit field. Note 1: If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN tagged frame plus the 4-byte header. Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. 2009-2013 Microchip Technology Inc. DS60001156H-page 319 PIC32MX5XX/6XX/7XX REGISTER 24-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit Bit 26/18/10/2 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 -- -- -- -- RESETRMII(1) -- -- SPEEDRMII(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-12 Unimplemented: Read as `0' bit 11 RESETRMII: Reset RMII Logic bit(1) 1 = Reset the MAC RMII module 0 = Normal operation. bit 10-9 Unimplemented: Read as `0' bit 8 SPEEDRMII: RMII Speed bit(1) This bit configures the Reduced MII logic for the current operating speed. 1 = RMII is running at 100 Mbps 0 = RMII is running at 10 Mbps bit 7-0 Unimplemented: Read as `0' Note 1: Note: This bit is only used for the RMII module. Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. DS60001156H-page 320 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- TESTBP TESTPAUSE(1) SHRTQNTA(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as `0' bit 2 TESTBP: Test Backpressure bit 1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. 0 = Normal operation bit 1 TESTPAUSE: Test PAUSE bit(1) 1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a non-zero pause time parameter was received 0 = Normal operation bit 0 SHRTQNTA: Shortcut PAUSE Quanta bit(1) 1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time 0 = Normal operation Note 1: Note: This bit is only for testing purposes. Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. 2009-2013 Microchip Technology Inc. DS60001156H-page 321 PIC32MX5XX/6XX/7XX REGISTER 24-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT CONFIGURATION REGISTER Bit Range Bit 31/23/15/7 31:24 23:16 15:8 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 RESETMGMT -- -- -- -- -- -- -- U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- NOPRE SCANINC 7:0 Legend: R = Readable bit -n = Value at POR CLKSEL<3:0>(1) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 RESETMGMT: Test Reset MII Management bit 1 = Reset the MII Management module 0 = Normal Operation bit 14-6 Unimplemented: Read as `0' bit 5-2 CLKSEL<3:0>: MII Management Clock Select 1 bits(1) These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE 802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz. bit 1 NOPRE: Suppress Preamble bit 1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs support suppressed preamble 0 = Normal read/write cycles are performed bit 0 SCANINC: Scan Increment bit 1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start from address 1 through the value set in EMAC1MADR<PHYADDR> 0 = Continuous reads of the same PHY Note 1: Note: Table 24-6 provides a description of the clock divider encoding. Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. TABLE 24-6: MIIM CLOCK SELECTION MIIM Clock Select EMAC1MCFG<5:2> SYSCLK divided by 4 000x SYSCLK divided by 6 0010 SYSCLK divided by 8 0011 SYSCLK divided by 10 0100 SYSCLK divided by 14 0101 SYSCLK divided by 20 0110 SYSCLK divided by 28 0111 SYSCLK divided by 40 1000 Undefined Any other combination DS60001156H-page 322 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- SCAN READ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-2 Unimplemented: Read as `0' bit 1 SCAN: MII Management Scan Mode bit 1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring the Link Fail) 0 = Normal Operation bit 0 READ: MII Management Read Command bit 1 = The MII Management module will perform a single read cycle. The read data is returned in the EMAC1MRDD register 0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD register Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. 2009-2013 Microchip Technology Inc. DS60001156H-page 323 PIC32MX5XX/6XX/7XX REGISTER 24-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PHYADDR<4:0> R/W-0 REGADDR<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as '0' bit 12-8 PHYADDR<4:0>: MII Management PHY Address bits This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed (0 is reserved). bit 7-5 Unimplemented: Read as '0' bit 4-0 REGADDR<4:0>: MII Management Register Address bits This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be accessed. Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. DS60001156H-page 324 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MWTD<15:8> R/W-0 R/W-0 MWTD<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as '0' bit 15-0 MWTD<15:0>: MII Management Write Data bits When written, a MII Management write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the EMAC1MADR register. Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. REGISTER 24-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MRDD<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MRDD<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 Note: MRDD<15:0>: MII Management Read Data bits Following a MII Management Read Cycle, the 16-bit data can be read from this location. Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. 2009-2013 Microchip Technology Inc. DS60001156H-page 325 PIC32MX5XX/6XX/7XX REGISTER 24-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- LINKFAIL NOTVALID SCAN MIIMBUSY Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3 LINKFAIL: Link Fail bit When `1' is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY status register. bit 2 NOTVALID: MII Management Read Data Not Valid bit When `1' is returned - indicates an MII management read cycle has not completed and the Read Data is not yet valid. bit 1 SCAN: MII Management Scanning bit When `1' is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress. bit 0 MIIMBUSY: MII Management Busy bit When `1' is returned - indicates MII Management module is currently performing an MII Management Read or Write cycle. Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. DS60001156H-page 326 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- R/W-P R/W-P R/W-P R/W-P -- R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR6<7:0> R/W-P R/W-P STNADDR5<7:0> Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-8 STNADDR6<7:0>: Station Address Octet 6 bits These bits hold the sixth transmitted octet of the station address. bit 7-0 STNADDR5<7:0>: Station Address Octet 5 bits These bits hold the fifth transmitted octet of the station address. Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. This register is loaded at reset from the factory preprogrammed station address. 2: 2009-2013 Microchip Technology Inc. DS60001156H-page 327 PIC32MX5XX/6XX/7XX REGISTER 24-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR4<7:0> R/W-P R/W-P STNADDR3<7:0> Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-8 STNADDR4<7:0>: Station Address Octet 4 bits These bits hold the fourth transmitted octet of the station address. bit 7-0 STNADDR3<7:0>: Station Address Octet 3 bits These bits hold the third transmitted octet of the station address. Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. This register is loaded at reset from the factory preprogrammed station address. 2: DS60001156H-page 328 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 24-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- R/W-P R/W-P R/W-P R/W-P -- R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR2<7:0> R/W-P R/W-P STNADDR1<7:0> Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Reserved: Maintain as `0'; ignore read bit 15-8 STNADDR2<7:0>: Station Address Octet 2 bits These bits hold the second transmitted octet of the station address. bit 7-0 STNADDR1<7:0>: Station Address Octet 1 bits These bits hold the most significant (first transmitted) octet of the station address. Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware. This register is loaded at reset from the factory preprogrammed station address. 2: 2009-2013 Microchip Technology Inc. DS60001156H-page 329 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 330 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 25.0 COMPARATOR The Comparator module contains two comparators that can be configured in a variety of ways. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. "Comparator" (DS60001110) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 25-1: Key features of the Comparator module include: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be inverted * Selectable interrupt generation A block diagram of the Comparator module is illustrated in Figure 25-1. COMPARATOR MODULE BLOCK DIAGRAM Comparator 1 CREF ON CPOL C1IN+(1) COUT (CM1CON<8>) C1OUT (CMSTAT<0>) CVREF(2) C1OUT CCH<1:0> C1 C1INCOE C1IN+ C2IN+ IVREF(2) Comparator 2 CREF ON CPOL C2IN+ CVREF COUT (CM2CON<8>) C2OUT (CMSTAT<1>) (2) C2OUT CCH<1:0> C2 C2INCOE C2IN+ C1IN+ IVREF(2) Note 1: 2: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module, and therefore, is not available as a comparator input. Internally connected. See Section 26.0 "Comparator Voltage Reference (CVREF)". 2009-2013 Microchip Technology Inc. DS60001156H-page 331 PIC32MX5XX/6XX/7XX 25.1 Control Registers REGISTER 25-1: Bit Range 31:24 23:16 15:8 7:0 CMxCON: COMPARATOR `x' CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- R/W-0 (1) R/W-0 ON COE R/W-1 R/W-1 EVPOL<1:0> Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 -- R/W-0 (2) CPOL Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 R-0 COUT -- -- -- -- U-0 R/W-0 U-0 U-0 R/W-1 -- CREF -- -- W = Writable bit `1' = Bit is set R/W-1 CCH<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Comparator ON bit(1) Clearing this bit does not affect the other bits in this register. 1 = Module is enabled. Setting this bit does not affect the other bits in this register 0 = Module is disabled and does not consume current. bit 14 COE: Comparator Output Enable bit 1 = Comparator output is driven on the output CxOUT pin 0 = Comparator output is not driven on the output CxOUT pin bit 13 CPOL: Comparator Output Inversion bit(2) 1 = Output is inverted 0 = Output is not inverted bit 12-9 Unimplemented: Read as `0' bit 8 COUT: Comparator Output bit 1 = Output of the Comparator is a `1' 0 = Output of the Comparator is a `0' bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled bit 5 Unimplemented: Read as `0' bit 4 CREF: Comparator Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the CXIN+ pin bit 3-2 Unimplemented: Read as `0' bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the C2IN+ pin for C1 and C1IN+ pin for C2 01 = Comparator inverting input is connected to the C1IN+ pin for C1 and C2IN+ pin for C2 00 = Comparator inverting input is connected to the C1IN- pin for C1 and C2IN- pin for C2 Note 1: 2: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>. DS60001156H-page 332 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 25-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 -- -- R/W-0 U-0 U-0 U-0 U-0 U-0 SIDL -- -- -- -- -- U-0 U-0 -- -- U-0 U-0 U-0 U-0 R-0 R-0 -- -- -- -- C2OUT C1OUT Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = All Comparator modules are disabled while in Idle mode 0 = All Comparator modules continue to operate while in Idle mode bit 12-2 Unimplemented: Read as `0' bit 1 C2OUT: Comparator Output bit 1 = Output of Comparator 2 is a `1' 0 = Output of Comparator 2 is a `0' bit 0 C1OUT: Comparator Output bit 1 = Output of Comparator 1 is a `1' 0 = Output of Comparator 1 is a `0' 2009-2013 Microchip Technology Inc. DS60001156H-page 333 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 334 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 26.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. "Comparator Voltage Reference (CVREF)" (DS60001109) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). A block diagram of the module is illustrated in Figure 26-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 26-1: Key features of the CVREF module include: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin COMPARATOR VOLTAGE REFERENCE MODULE BLOCK DIAGRAM BGSEL<1:0>(1) 1.2V IVREF 0.6V VREFSEL(1) VREF+ AVDD CVRSS = 1 CVRSRC CVREF 8R CVRSS = 0 CVR<3:0> R CVREN R 16-to-1 MUX R R 16 Steps CVREFOUT CVROE (CVRCON<6>) R R R CVRR VREFAVSS Note 1: 8R CVRSS = 1 CVRSS = 0 This bit is not available on PIC32MX575/675/695/775/795 devices. On these devices CVREF is generated by the Register network and IVREF is connected to 0.6V. 2009-2013 Microchip Technology Inc. DS60001156H-page 335 PIC32MX5XX/6XX/7XX 26.1 Control Register REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- VREFSEL(2) R/W-1 (2) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- CVROE CVRR CVRSS ON Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set BGSEL<1:0> R/W-0 R/W-0 CVR<3:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Comparator Voltage Reference On bit(1) Setting or clearing this bit does not affect the other bits in this register. 1 = Module is enabled 0 = Module is disabled and does not consume current bit 14-11 Unimplemented: Read as `0' bit 10 VREFSEL: Voltage Reference Select bit(2) 1 = CVREF = VREF+ 0 = CVREF is generated by the resistor network bit 9-8 BGSEL<1:0>: Band Gap Reference Source bits(2) 11 = IVREF = VREF+ 10 = Reserved 01 = IVREF = 0.6V (nominal, default) 00 = IVREF = 1.2V (nominal) bit 7 Unimplemented: Read as `0' bit 6 CVROE: CVREFOUT Enable bit 1 = Voltage level is output on CVREFOUT pin 0 = Voltage level is disconnected from CVREFOUT pin bit 5 CVRR: CVREF Range Selection bit 1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: CVREF Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator voltage reference source, CVRSRC = AVDD - AVSS bit 3-0 CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1: CVREF = (CVR<3:0>/24) (CVRSRC) When CVRR = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC) Note 1: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2: These bits are not available on PIC32MX575/675/775/795 devices. On these devices, the reset value for CVRON is `0000'. DS60001156H-page 336 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 27.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "PowerSaving Features" (DS60001130) in the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. This section describes power-saving features for the PIC32MX5XX/6XX/7XX family of devices. These devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-saving is controlled by software. 27.1 Power-Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the Peripheral Bus Clock (PBCLK) and by individually disabling modules. These methods are grouped into the following categories: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. In addition, the Peripheral Bus Scaling mode is available where peripherals are clocked at the programmable fraction of the CPU clock (SYSCLK). 27.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which Halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. 2009-2013 Microchip Technology Inc. * SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. * LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. * Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. 27.3 Power-Saving Operation Peripherals and the CPU can be halted or disabled to further reduce power consumption. 27.3.1 SLEEP MODE Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics: * The CPU is halted * The system clock source is typically shutdown. See Section 27.3.3 "Peripheral Bus Scaling Method" for specific information. * There can be a wake-up delay based on the oscillator selection * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode * The BOR circuit, if enabled, remains operative during Sleep mode * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode * Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture). * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep * Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption DS60001156H-page 337 PIC32MX5XX/6XX/7XX The processor will exit, or `wake-up', from Sleep on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset * On a WDT time-out If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. 27.3.2 IDLE MODE In Idle mode, the CPU is Halted but the System Clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted. Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. Note 1: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in the PB divisor ratio. 2: Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator startup delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator start-up/lock delays would be applied. DS60001156H-page 338 The device enters Idle mode when the SLPEN bit (OSCCON<4>) is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode. * On any form of device Reset * On a WDT time-out interrupt 27.3.3 PERIPHERAL BUS SCALING METHOD Most of the peripherals on the device are clocked using the PBCLK. The Peripheral Bus (PB) can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, interrupt controller, DMA, bus matrix and prefetch cache are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes. Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power, the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 28.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Watchdog Timer and Power-up Timer" (DS60001114), Section 24. "Configuration" (DS60001124) and Section 33. "Programming and Diagnostics" (DS60001129) in the "PIC32 Family Reference Manual", which are available from the Microchip web site (www.microchip.com/PIC32). 28.1 Configuration Bits The Configuration bits can be programmed using the following registers to select various device configurations. * * * * * DEVCFG0: Device Configuration Word 0 DEVCFG1: Device Configuration Word 1 DEVCFG2: Device Configuration Word 2 DEVCFG3: Device Configuration Word 3 DEVID: Device and Revision ID Register PIC32MX5XX/6XX/7XX devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. Key features include: * * * * Flexible device configuration Watchdog Timer (WDT) Joint Test Action Group (JTAG) interface In-Circuit Serial ProgrammingTM (ICSPTM) 2009-2013 Microchip Technology Inc. DS60001156H-page 339 PIC32MX5XX/6XX/7XX REGISTER 28-1: Bit Range DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 26/18/10/2 Bit 25/17/9/1 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P -- -- CP -- -- -- BWP r-1 r-1 r-1 r-1 R/P R/P R/P R/P r-1 r-1 r-1 r-1 -- -- -- -- R/P R/P -- -- -- -- R/P R/P R/P R/P PWP<7:4> r-1 r-1 r-1 r-1 R/P r-1 -- -- -- -- ICESEL -- DEBUG<1:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 Bit 24/16/8/0 -- PWP<3:0> 7:0 Bit 27/19/11/3 x = Bit is unknown Reserved: Write `0' bit 30-29 Reserved: Write `1' bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection is disabled 0 = Protection is enabled bit 27-25 Reserved: Write `1' bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write `1' bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the 1's complement of the number of write-protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF * * * 01111111 = 0xBD07_FFFF bit 11-4 Reserved: Write `1' DS60001156H-page 340 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 28-1: bit 3 DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used bit 2 Reserved: Write `1' bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 11 = Debugger is disabled 10 = Debugger is enabled 01 = Reserved (same as `11' setting) 00 = Reserved (same as `11' setting) 2009-2013 Microchip Technology Inc. DS60001156H-page 341 PIC32MX5XX/6XX/7XX REGISTER 28-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- R/P r-1 r-1 R/P R/P R/P R/P R/P R/P r-1 R/P R/P R/P FWDTEN -- -- R/P R/P R/P FCKSM<1:0> WDTPS<4:0> -- OSCIOFNC R/P r-1 R/P FPBDIV<1:0> r-1 r-1 R/P IESO -- FSOSCEN -- -- POSCMOD<1:0> R/P R/P FNOSC<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Reserved: Write `1' bit 23 FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software bit 22-21 Reserved: Write `1' bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. DS60001156H-page 342 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write `1' bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output is disabled 0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured for External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00) bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6 Reserved: Write `1' bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable the Secondary Oscillator 0 = Disable the Secondary Oscillator bit 4-3 Reserved: Write `1' bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. 2009-2013 Microchip Technology Inc. DS60001156H-page 343 PIC32MX5XX/6XX/7XX REGISTER 28-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- r-1 r-1 r-1 r-1 r-1 R/P R/P R/P -- -- -- -- -- R/P r-1 r-1 r-1 r-1 UPLLEN -- -- -- -- r-1 R/P-1 R/P R/P-1 r-1 -- FPLLMUL<2:0> FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0> R/P -- R/P R/P FPLLIDIV<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-19 Reserved: Write `1' bit 18-16 FPLLODIV<2:0>: PLL Output Divider bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write `1' bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write `1' bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write `1' DS60001156H-page 344 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 28-3: bit 2-0 DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider 2009-2013 Microchip Technology Inc. DS60001156H-page 345 PIC32MX5XX/6XX/7XX REGISTER 28-4: Bit Range 31:24 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 R/P R/P FVBUSONIO FUSBIDIO 23:16 15:8 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 R/P R/P R/P -- -- -- FCANIO(1) FETHIO(2) FMIIEN(2) R/P R/P R/P r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- R/P R/P R/P R/P R/P FSRSSEL<2:0> R/P R/P R/P R/P R/P R/P USERID<15:8> R/P 7:0 R/P R/P R/P R/P USERID<7:0> Legend: R = Readable bit -n = Value at POR r = Reserved bit W = Writable bit `1' = Bit is set P = Programmable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FVBUSONIO: USB VBUSON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function bit 30 FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function bit 29-27 Reserved: Write `1' bit 26 FCANIO: CAN I/O Pin Selection bit(1) 1 = Default CAN I/O Pins 0 = Alternate CAN I/O Pins bit 25 FETHIO: Ethernet I/O Pin Selection bit(2) 1 = Default Ethernet I/O Pins 0 = Alternate Ethernet I/O Pins bit 24 FMIIEN: Ethernet MII Enable bit(2) 1 = MII is enabled 0 = RMII is enabled bit 23-19 Reserved: Write `1' bit 18-16 FSRSSEL<2:0>: SRS Select bits 111 = Assign Interrupt Priority 7 to a shadow register set 110 = Assign Interrupt Priority 6 to a shadow register set bit 31 * * * bit 15-0 Note 1: 2: 001 = Assign Interrupt Priority 1 to a shadow register set 000 = All interrupt priorities are assigned to a shadow register set USERID<15:0>: User ID bits This is a 16-bit value that is user-defined and is readable via ICSPTM and JTAG. This bit is Reserved and reads `1' on PIC32MX664/675/695 devices. This bit is Reserved and reads `1' on PIC32MX534/564/575 devices. DS60001156H-page 346 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 28-5: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R R Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R R R R R R R (1) R R R R R (1) R R R R R R R VER<3:0> R Bit 24/16/8/0 R (1) (1) R Bit 25/17/9/1 DEVID<27:24> DEVID<23:16> R R R R R R R DEVID<15:8> R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID bits(1) Note 1: See the "PIC32 Flash Programming Specification" (DS60001145) for a list of Revision and Device ID values. 2009-2013 Microchip Technology Inc. DS60001156H-page 347 PIC32MX5XX/6XX/7XX 28.2 Watchdog Timer (WDT) Key features of the WDT module include: This section describes the operation of the WDT and Power-up Timer of the PIC32MX5XX/6XX/7XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. FIGURE 28-1: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle WATCHDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable LPRC Control PWRT Enable 1:64 Output LPRC Oscillator PWRT 1 Clock 25-bit Counter WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 25 0 1 WDT Counter Reset Device Reset NMI (Wake-up) Power Save Decoder FWDTPS<4:0> (DEVCFG1<20:16>) DS60001156H-page 348 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 28-6: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ON(1,2) -- -- -- -- -- -- -- U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0 -- SWDTPS<4:0> WDTWINEN WDTCLR Legend: y = Values set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Watchdog Timer Enable bit(1,2) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software bit 14-7 Unimplemented: Read as `0' bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS <4:0> Configuration bits. bit 1 WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer bit 0 WDTCLR: Watchdog Timer Reset bit 1 = Writing a `1' will clear the WDT 0 = Software cannot force this bit to a `0' Note 1: 2: A read of this bit results in a `1' if the Watchdog Timer is enabled by the device configuration or software. When using the 1:1 PBCLK divisor, the user's software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2009-2013 Microchip Technology Inc. DS60001156H-page 349 PIC32MX5XX/6XX/7XX 28.3 On-Chip Voltage Regulator All PIC32MX5XX/6XX/7XX devices' core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 28-2). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 31.1 "DC Characteristics". Note: It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. 28.3.1 ON-CHIP REGULATOR AND POR It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. 28.3.2 28.4 Programming and Diagnostics PIC32MX5XX/6XX/7XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire In-Circuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. FIGURE 28-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS ON-CHIP REGULATOR AND BOR PIC32MX5XX/6XX/7XX devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset (BOR). This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specified in Section 31.1 "DC Characteristics". PGEC1 PGED1 ICSPTM Controller PGEC2 PGED2 ICESEL FIGURE 28-2: CONNECTIONS FOR THE ON-CHIP REGULATOR TDI TDO 3.3V(1) TCK PIC32 VDD JTAG Controller Core TMS JTAGEN DEBUG<1:0> VCAP CEFC(2) (10 F typical) TRCLK VSS TRD0 TRD1 Note 1: 2: These are typical operating voltages. Refer to Section 31.1 "DC Characteristics" for the full operating ranges of VDD. It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. DS60001156H-page 350 Instruction Trace Controller TRD2 TRD3 DEBUG<1:0> 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX REGISTER 28-7: Bit Range 31:24 23:16 15:8 7:0 DDPCON: DEBUG DATA PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-1 R/W-0 U-0 R/W-0 -- -- -- -- JTAGEN TROEN -- TDOEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3 JTAGEN: JTAG Port Enable bit 1 = Enable the JTAG port 0 = Disable the JTAG port bit 2 TROEN: Trace Output Enable bit 1 = Enable the trace port 0 = Disable the trace port bit 1 Unimplemented: Read as `0' bit 0 TDOEN: TDO Enable for 2-Wire JTAG 1 = 2-wire JTAG protocol uses TDO 0 = 2-wire JTAG protocol does not use TDO 2009-2013 Microchip Technology Inc. DS60001156H-page 351 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 352 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 29.0 INSTRUCTION SET The PIC32MX5XX/6XX/7XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. The PIC32 device family does not support the following features: * Core Extend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions Note: Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.mips.com for more information. 2009-2013 Microchip Technology Inc. DS60001156H-page 353 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 354 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 30.0 DEVELOPMENT SUPPORT (R) (R) The PIC microcontrollers and dsPIC digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C(R) for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 30.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2009-2013 Microchip Technology Inc. DS60001156H-page 355 PIC32MX5XX/6XX/7XX 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 30.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 30.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS60001156H-page 356 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 30.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2009-2013 Microchip Technology Inc. 30.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 30.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full-speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. DS60001156H-page 357 PIC32MX5XX/6XX/7XX 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 30.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS60001156H-page 358 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias.............................................................................................................-40C to +105C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: See the "Pin Diagrams" section for the 5V tolerant pins. 2009-2013 Microchip Technology Inc. DS60001156H-page 359 PIC32MX5XX/6XX/7XX 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts)(1) Characteristic Max. Frequency Temp. Range (in C) PIC32MX5XX/6XX/7XX DC5 2.3-3.6V -40C to +85C 80 MHz DC5b 2.3-3.6V -40C to +105C 80 MHz Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values. TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Operating Junction Temperature Range TJ -40 -- +125 C Operating Ambient Temperature Range TA -40 -- +85 C Operating Junction Temperature Range TJ -40 -- +140 C Operating Ambient Temperature Range TA -40 -- +105 C Industrial Temperature Devices V-Temp Temperature Devices Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) PD PINT + PI/O W PDMAX (TJ - TA)/JA W I/O Pin Power Dissipation: I/O = S (({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation TABLE 31-3: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical Max. Unit See Note Package Thermal Resistance, 121-Pin TFBGA (10x10x1.1 mm) JA 40 -- C/W 1 Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm) JA 43 -- C/W 1 Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) JA 43 -- C/W 1 Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) JA 47 -- C/W 1 Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) JA 28 -- C/W 1 Package Thermal Resistance, 124-Pin VTLA (9x9x0.9 mm) JA 21 -- C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS60001156H-page 360 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions Operating Voltage Supply Voltage 2.3 -- 3.6 V -- DC10 VDD (1) RAM Data Retention Voltage 1.75 -- -- V -- DC12 VDR VDD Start Voltage to Ensure 1.75 -- 2.1 V -- DC16 VPOR Internal Power-on Reset Signal VDD Rise Rate to Ensure 0.00005 -- 0.115 V/s -- DC17 SVDD Internal Power-on Reset Signal Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for BOR values. 2009-2013 Microchip Technology Inc. DS60001156H-page 361 PIC32MX5XX/6XX/7XX TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max. Units Conditions Operating Current (IDD)(1,2) for PIC32MX575/675/695/775/795 Family Devices DC20 6 9 mA DC20b 7 Code executing from Flash 10 4 -- Code executing from SRAM DC21 37 40 Code executing from Flash DC21a 25 -- DC22 64 70 DC22a 61 -- DC23 85 98 mA mA mA 90 120 DC23a 85 -- DC25a 125 150 Note 1: 2: 3: 4: -- 4 MHz -- -- 25 MHz (Note 4) -- -- 60 MHz (Note 4) -40C, +25C, +85C -- 80 MHz 3.3V LPRC (31 kHz) (Note 4) +105C DC20a DC23b -40C, +25C, +85C Code executing from SRAM Code executing from Flash Code executing from SRAM Code executing from Flash -- +105C A Code executing from SRAM -- -- +25C A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0) * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * CPU executing while(1) statement from Flash * RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. DS60001156H-page 362 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max. Units Conditions Operating Current (IDD)(1,2) for PIC32MX534/564/664/764 Family Devices DC20c 6 9 mA DC20d 7 Code executing from Flash 10 2 -- Code executing from SRAM DC21b 19 32 Code executing from Flash DC21c 14 -- DC22b 31 50 DC22c 29 -- DC23c 39 65 mA mA mA 49 70 DC23e 39 -- DC25b 100 150 Note 1: 2: 3: 4: -- 4 MHz -- -- 25 MHz (Note 4) -- -- 60 MHz (Note 4) -40C, +25C, +85C -- 80 MHz 3.3V LPRC (31 kHz) (Note 4) +105C DC20e DC23d -40C, +25C, +85C Code executing from SRAM Code executing from Flash Code executing from SRAM Code executing from Flash -- +105C A Code executing from SRAM -- -- +25C A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0) * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * CPU executing while(1) statement from Flash * RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 363 PIC32MX5XX/6XX/7XX TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE)(1) for PIC32MX575/675/695/775/795 Family Devices DC30 4.5 6.5 DC30b 5 7 DC31 13 15 mA DC32 28 30 mA mA -40C, +25C, +85C -- 4 MHz -40C, +25C, +85C -- 25 MHz (Note 3) -40C, +25C, +85C -- 60 MHz (Note 3) -- 80 MHz +105C DC33 36 42 mA -40C, +25C, +85C DC33b 39 45 mA +105C DC34 40 -40C DC34a 75 +25C DC34b -- DC34c 800 A 1000 +85C +105C DC35 35 -40C DC35a 65 +25C DC35b 600 DC35c 800 -- A +85C 43 -40C DC36a 106 +25C -- DC36c Note 1: 2: 3: 3.3V LPRC (31 kHz) (Note 3) +105C DC36 DC36b 2.3V 800 1000 A +85C 3.6V +105C The test conditions for IIDLE current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0) * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. DS60001156H-page 364 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE)(1) for PIC32MX534/564/664/764 Family Devices DC30a 1.5 5 DC30c 3.5 6 DC31a 7 11 DC32a 13 20 DC33a 17 25 DC33c 20 27 DC34c DC34d DC34e -- 55 230 DC35f 800 DC36c DC36f Note 1: 2: 3: mA 75 800 A 4 MHz -40C, +25C, +85C -- 25 MHz (Note 3) -40C, +25C, +85C -- 60 MHz (Note 3) -- 80 MHz -40C, +25C, +85C +105C +25C +85C 2.3V +105C -40C -- A +25C +85C 3.3V LPRC (31 kHz) (Note 3) +105C 43 -- -- +105C -40C 1000 DC35e DC36e mA 30 DC35d DC36d mA 40 DC34f DC35c -40C, +25C, +85C 106 800 1000 -40C A +25C +85C 3.6V +105C The test conditions for IIDLE current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0) * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 365 PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Units Conditions Power-Down Current (IPD)(1) for PIC32MX575/675/695/775/795 Family Devices DC40 10 40 -40C DC40a 36 100 +25C DC40b 400 720 +85C DC40h 900 1800 +105C DC40c 41 120 DC40d 22 80 A +25C 2.3V Base Power-Down Current (Note 6) 3.3V Base Power-Down Current 3.6V Base Power-Down Current -40C DC40e 42 120 +25C DC40g 315 400(5) +70C DC40f 410 800 +85C DC40i 1000 2000 +105C Module Differential Current for PIC32MX575/675/695/775/795 Family Devices DC41 -- 10 DC41a 5 -- DC41b -- 20 DC42 -- 40 DC42a 23 -- DC42b -- DC43 -- DC43a 1100 -- DC43b -- 1300 Note 1: 2: 3: 4: 5: 6: 2.3V A -- Watchdog Timer Current: IWDT (Notes 3,6) 3.3V Watchdog Timer Current: IWDT (Note 3) 3.6V Watchdog Timer Current: IWDT (Note 3) 2.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6) 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 50 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 1300 2.5V ADC: IADC (Notes 3,4,6) 3.3V ADC: IADC (Notes 3,4) 3.6V ADC: IADC (Notes 3,4) A A -- -- The test conditions for IPD current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0) * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing. DS60001156H-page 366 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Units Conditions Power-Down Current (IPD)(1) for PIC32MX534/564/664/764 Family Devices DC40g 12 40 -40C DC40h 20 120 +25C DC40i 210 600 +85C DC40o 400 1000 +105C DC40j 20 120 A +25C DC40k 15 80 DC40l 20 120 DC40m 113 350(5) +70C DC40n 220 650 +85C DC40p 500 1000 +105C 2.3V Base Power-Down Current (Note 6) 3.3V Base Power-Down Current 3.6V Base Power-Down Current -40C +25C Module Differential Current for PIC32MX534/564/664/764 Family Devices DC41c -- 10 DC41d 5 -- A -- 2.5V Watchdog Timer Current: IWDT (Notes 3,6) 3.3V Watchdog Timer Current: IWDT (Note 3) DC41e -- 20 3.6V Watchdog Timer Current: IWDT (Note 3) DC42c -- 40 2.5V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6) DC42d 23 -- 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) DC42e -- 50 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) DC43c -- 1300 2.5V ADC: IADC (Notes 3,4,6) DC43d 1100 -- 3.3V ADC: IADC (Notes 3,4) DC43e -- 1300 3.6V ADC: IADC (Notes 3,4) Note 1: 2: 3: 4: 5: 6: A A -- -- The test conditions for IPD current measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0) * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 367 PIC32MX5XX/6XX/7XX TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Min. Typical(1) Max. Units DI15 DI16 DI17 DI18 Input Low Voltage I/O Pins: with TTL Buffer with Schmitt Trigger Buffer MCLR(2) OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD V V V V V V DI19 SDAx, SCLx VSS -- 0.8 V 0.65 VDD 0.25 VDD + 0.8V -- -- VDD 5.5 V V 0.65 VDD 0.65 VDD -- -- 5.5 5.5 V V 2.1 -- 5.5 V VIL DI10 VIH DI28 Input High Voltage I/O Pins not 5V-tolerant(5) I/O Pins 5V-tolerant with PMP(5) I/O Pins 5V-tolerant(5) SDAx, SCLx DI29 SDAx, SCLx DI20 Conditions (Note 4) (Note 4) SMBus disabled (Note 4) SMBus enabled (Note 4) (Note 4,6) (Note 4,6) SMBus disabled (Note 4,6) SMBus enabled, 2.3V VPIN 5.5 (Note 4,6) VDD = 3.3V, VPIN = VSS (Note 3,6) VDD = 3.3V, VPIN = VDD Change Notification -- -- -50 A Pull-up Current DI31 ICNPD Change Notification -- 50 -- A Pull-down Current(4) Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the "Pin Diagrams" section for the 5V-tolerant pins. 6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-selectable pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pullups are guaranteed to be recognized as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the maximum value of ICNPU. 7: VIL source < (VSS - 0.3). Characterized but not tested. 8: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any "positive" input injection current. 10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)). 11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0. DI30 ICNPU DS60001156H-page 368 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. IIL Characteristics Input Leakage Current(3) I/O Ports Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical(1) Max. Units Conditions VSS VPIN VDD, Pin at high-impedance DI51 Analog Input Pins -- -- +1 A VSS VPIN VDD, Pin at high-impedance -- -- +1 A VSS VPIN VDD DI55 MCLR(2) DI56 OSC1 -- -- +1 A VSS VPIN VDD, XT and HS modes This parameter applies to all pins, with the Input Low Injection exception of RB10. (7,10) DI60a IICL 0 -- -5 mA Current Maximum IICH current for this exception is 0 mA. This parameter applies to all pins, with the exception of all 5V tolerInput High Injection DI60b IICH 0 -- +5(8,9,10) mA ant pins, SOSCI, and Current RB10. Maximum IICH current for these exceptions is 0 mA. DI60c IICT Total Input Injection -20(11) -- +20(11) mA Absolute instantaneous Current (sum of all I/O sum of all input and control pins) injection currents from all I/O pins ( | IICL + | IICH | ) IICT Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the "Pin Diagrams" section for the 5V-tolerant pins. 6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-selectable pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pullups are guaranteed to be recognized as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the maximum value of ICNPU. 7: VIL source < (VSS - 0.3). Characterized but not tested. 8: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any "positive" input injection current. 10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)). 11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0. DI50 2009-2013 Microchip Technology Inc. -- -- +1 A DS60001156H-page 369 PIC32MX5XX/6XX/7XX TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH DO20A VOH1 Note 1: 2: 3: Characteristic Output Low Voltage I/O Pins: 4x Sink Driver Pins - All I/O output pins not defined as 8x Sink Driver pins Output Low Voltage I/O Pins: 8x Sink Driver Pins - RC15 Output High Voltage I/O Pins: 4x Source Driver Pins - All I/O output pins not defined as 8x Source Driver pins Output High Voltage I/O Pins: 8x Source Driver Pins - RC15 Output High Voltage I/O Pins: 4x Source Driver Pins - All I/O output pins not defined as 8x Sink Driver pins Output High Voltage I/O Pins: 8x Source Driver Pins - RC15 Min. Typ. Max. Units Conditions -- -- 0.4 V IOL 10 mA, VDD = 3.3V -- -- 0.4 V IOL 15 mA, VDD = 3.3V 2.4 -- -- V IOH -10 mA, VDD = 3.3V 2.4 -- -- V IOH -15 mA, VDD = 3.3V 1.5(1) -- -- 2.0(1) -- -- 3.0(1) -- -- IOH -7 mA, VDD = 3.3V 1.5(1) -- -- IOH -22 mA, VDD = 3.3V 2.0(1) -- -- 3.0(1) -- -- IOH -14 mA, VDD = 3.3V IOH -12 mA, VDD = 3.3V V IOH -18 mA, VDD = 3.3V V IOH -10 mA, VDD = 3.3V Parameters are characterized, but not tested. This driver pin only applies to devices with less than 64 pins. This driver pin only applies to devices with 64 pins. TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. No. Characteristics Min.(1) Typical Max. Units Conditions BOR Event on VDD transition high-to-low (Note 2) 2.0 -- 2.3 V -- Symbol BO10 VBOR Note 1: 2: Parameters are for design guidance only and are not tested in manufacturing. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. DS60001156H-page 370 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max. Units Conditions -- Program Flash Memory(3) D130 EP Cell Endurance 1000 -- -- E/W D130a EP Cell Endurance 20,000 -- -- E/W See Note 4 D131 VPR VDD for Read 2.3 -- 3.6 V -- D132 VPEW VDD for Erase or Write 3.0 -- 3.6 V -- D132a VPEW VDD for Erase or Write 2.3 -- 3.6 D134 TRETD Characteristic Retention 20 -- -- Year Provided no other specifications are violated D135 IDDP Supply Current during Programming -- 10 -- mA TWW Word Write Cycle Time 20 -- 40 s -- D136 TRW Row Write Cycle Time(2) 3 4.5 -- ms -- D137 TPE Page Erase Cycle Time 20 -- -- ms -- TCE Chip Erase Cycle Time 80 -- -- ms -- Note 1: 2: 3: 4: V See Note 4 -- Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to "PIC32 Flash Programming Specification" (DS60001145) for operating conditions during programming and erase cycles. This parameter only applies to PIC32MX534/564/664/764 devices. TABLE 31-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Required Flash Wait States SYSCLK Units Comments 0 Wait State 0 to 30 MHz -- 1 Wait State 31 to 60 2 Wait States 61 to 80 2009-2013 Microchip Technology Inc. DS60001156H-page 371 PIC32MX5XX/6XX/7XX TABLE 31-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 3): 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage -- 7.5 25 mV AVDD = VDD, AVSS = VSS D301 VICM Input Common Mode Voltage 0 -- VDD V AVDD = VDD, AVSS = VSS (Note 2) D302 CMRR Common Mode Rejection Ratio 55 -- -- dB Max VICM = (VDD - 1)V (Note 2) D303 TRESP Response Time -- 150 400 ns AVDD = VDD, AVSS = VSS (Notes 1, 2) D304 ON2OV Comparator Enabled to Output Valid -- -- 10 s Comparator module is configured before setting the comparator ON bit (Note 2) D305 IVREF Internal Voltage Reference 0.57 0.6 0.63 V For devices without BGSEL<1:0> 1.14 1.2 1.26 V BGSEL<1:0> = 00 0.57 0.6 0.63 V BGSEL<1:0> = 01 Note 1: 2: 3: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested. The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001156H-page 372 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-14: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics D310 VRES Resolution D311 VRAA Absolute Accuracy (1) D312 TSET Settling Time D313 VIREF Internal Voltage Reference Note 1: Min. Typical Max. Units Comments VDD/24 -- VDD/32 LSb -- -- -- 1/2 LSb -- -- -- 10 s -- -- 0.6 -- V -- Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing. TABLE 31-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp DC CHARACTERISTICS Param. No. Symbol Characteristics Min. Typical Max. Units Comments D321 CEFC External Filter Capacitor Value 8 10 -- F Capacitor must be low series resistance (1 ohm) D322 TPWRT Power-up Timer Period -- 64 -- ms -- 2009-2013 Microchip Technology Inc. DS60001156H-page 373 PIC32MX5XX/6XX/7XX 31.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX5XX/6XX/7XX AC characteristics and timing parameters. FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) VSS TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Param. Symbol No. Min. Typical(1) Characteristics Max. Units Conditions DO56 CIO All I/O pins and OSC2 -- -- 50 pF EC mode DO58 CB SCLx, SDAx -- -- 400 pF In I2CTM mode Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 31-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 DS60001156H-page 374 OS31 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max. Units Conditions External CLKI Frequency (External clocks only allowed in EC and ECPLL modes) DC 4 -- -- 50 50 MHz MHz EC (Note 4) ECPLL (Note 3) Oscillator Crystal Frequency 3 -- 10 MHz XT (Note 4) OS12 4 -- 10 MHz XTPLL (Notes 3,4) OS13 10 -- 25 MHz HS (Note 5) OS14 10 -- 25 MHz HSPLL (Notes 3,4) 32 32.768 100 kHz SOSC (Note 4) -- -- -- -- See parameter OS10 for FOSC value OS10 FOSC OS11 Characteristics OS15 OS20 TOSC TOSC = 1/FOSC = TCY(2) OS30 TOSL, TOSH External Clock In (OSC1) High or Low Time 0.45 x TOSC -- -- ns EC (Note 4) OS31 TOSR, TOSF External Clock In (OSC1) Rise or Fall Time -- -- 0.05 x TOSC ns EC (Note 4) OS40 TOST Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) -- 1024 -- TOSC (Note 4) OS41 TFSCM Primary Clock Fail Safe Time-out Period -- 2 -- ms (Note 4) OS42 GM External Oscillator Transconductance -- 12 -- Note 1: 2: 3: 4: mA/V VDD = 3.3V, TA = +25C (Note 4) Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but is only tested at 10 MHz at manufacturing. This parameter is characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 375 PIC32MX5XX/6XX/7XX TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 3.92 -- 5 MHz OS51 FSYS On-Chip VCO System Frequency 60 -- 120 MHz OS52 TLOCK PLL Start-up Time (Lock Time) -- -- 2 ms OS53 DCLK CLKO Stability(2) (Period Jitter or Cumulative) -0.25 -- +0.25 % Note 1: 2: Conditions ECPLL, HSPLL, XTPLL, FRCPLL modes -- -- Measured over 100 ms period These parameters are characterized, but not tested in manufacturing. This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D CLK EffectiveJitter = -------------------------------------------------------------SYSCLK --------------------------------------------------------CommunicationClock For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: D CLK D CLK - = ------------EffectiveJitter = ------------2 80 -----20 TABLE 31-19: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX575/675/695/775/795 Family Devices F20a FRC -2 -- +2 % -- Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX534/564/664/764 Family Devices F20b Note 1: FRC -0.9 -- +0.9 % -- Frequency calibrated at 25C and 3.3V. The TUN bits can be used to compensate for temperature drift. DS60001156H-page 376 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-20: INTERNAL RC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Characteristics Min. Typical Max. Units Conditions -15 -- +15 % -- LPRC @ 31.25 kHz(1) F21 LPRC Note 1: Change of LPRC frequency as VDD changes. FIGURE 31-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 31-1 for load conditions. DO31 DO32 TABLE 31-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(2) Min. Typical(1) Max. Units -- 5 15 ns VDD < 2.5V Conditions DO31 TIOR Port Output Rise Time -- 5 10 ns VDD > 2.5V DO32 TIOF Port Output Fall Time -- 5 15 ns VDD < 2.5V -- 5 10 ns VDD > 2.5V DI35 TINP INTx Pin High or Low Time 10 -- -- ns -- DI40 TRBP CNx High or Low Time (input) 2 -- -- TSYSCLK -- Note 1: 2: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 377 PIC32MX5XX/6XX/7XX FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). Includes interval voltage regulator stabilization delay. DS60001156H-page 378 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 31-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions SY00 TPU Power-up Period Internal Voltage Regulator Enabled -- 400 600 s -40C to +85C SY02 TSYSDLY System Delay Period: Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched. -- 1 s + 8 SYSCLK cycles -- -- -40C to +85C SY20 TMCLR MCLR Pulse Width (low) -- 2 -- s -40C to +85C SY30 TBOR BOR Pulse Width (low) -- 1 -- s -40C to +85C Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. 2009-2013 Microchip Technology Inc. DS60001156H-page 379 PIC32MX5XX/6XX/7XX FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 31-1 for load conditions. TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. TA10 TA11 TA15 Characteristics(2) Symbol TTXH TTXL TTXP TxCK High Time TxCK Low Time Typical Max. Units Conditions Synchronous, with prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- -- ns Must also meet parameter TA15 Asynchronous, with prescaler 10 -- -- ns -- Synchronous, with prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- -- ns Must also meet parameter TA15 Asynchronous, with prescaler 10 -- -- ns -- [(Greater of 25 ns or 2 TPB)/N] + 30 ns -- -- ns VDD > 2.7V [(Greater of 25 ns or 2 TPB)/N] + 50 ns -- -- ns VDD < 2.7V 20 -- -- ns VDD > 2.7V (Note 3) 50 -- -- ns VDD < 2.7V (Note 3) 32 -- 100 kHz -- -- -- 1 TPB -- TxCK Synchronous, Input Period with prescaler Asynchronous, with prescaler OS60 FT1 TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: 2: 3: Min. SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. N = Prescale Value (1, 8, 64, 256). DS60001156H-page 380 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- ns TB11 TTXL TxCK Synchronous, with Low Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Conditions Must also meet N = prescale parameter value TB15 (1, 2, 4, 8, Must also meet 16, 32, 64, 256) parameter TB15 TB15 TB20 Note 1: TTXP TxCK Input Period Synchronous, with prescaler TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment [(Greater of [(25 ns or 2 TPB)/N] + 30 ns -- ns VDD > 2.7V [(Greater of [(25 ns or 2 TPB)/N] + 50 ns -- ns VDD < 2.7V -- 1 TPB -- These parameters are characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 381 PIC32MX5XX/6XX/7XX FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 31-1 for load conditions. TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet parameter IC15. IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet parameter IC15. IC15 TCCP ICx Input Period [(25 ns or 2 TPB)/N] + 50 ns -- ns Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 31-8: N = prescale value (1, 4, 16) -- OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 31-1 for load conditions. TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical(2) Max. Units Conditions OC10 TCCF OCx Output Fall Time -- -- -- ns See parameter DO32 OC11 TCCR OCx Output Rise Time -- -- -- ns See parameter DO31 Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS60001156H-page 382 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure 31-1 for load conditions. TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param No. Symbol Characteristics(1) Min Typical(2) Max Units Conditions OC15 TFD Fault Input to PWM I/O Change -- -- 50 ns -- OC20 TFLT Fault Input Pulse Width 50 -- -- ns -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2009-2013 Microchip Technology Inc. DS60001156H-page 383 PIC32MX5XX/6XX/7XX FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions ns -- -- TSCL SCKx Output Low Time(3) TSCK/2 SP11 TSCH SCKx Output High Time(3) TSCK/2 -- -- ns SP20 TSCF SCKx Output Fall Time(4) -- -- -- ns See parameter DO32 SP21 TSCR SCKx Output Rise Time(4) -- -- -- ns See parameter DO31 SP10 (4) -- -- SP30 TDOF SDOx Data Output Fall Time -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 ns VDD > 2.7V -- -- 20 ns VDD < 2.7V SP40 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 10 -- -- ns -- SP41 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 10 -- -- ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS60001156H-page 384 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions -- -- ns -- TSCL SCKx Output Low Time(3) TSCK/2 SP11 TSCH SCKx Output High Time(3) TSCK/2 -- -- ns -- SP20 TSCF SCKx Output Fall Time(4) -- -- -- ns See parameter DO32 SP21 TSCR SCKx Output Rise Time(4) -- -- -- ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time(4) -- -- -- ns See parameter DO32 SP10 (4) SP31 TDOR SDOx Data Output Rise Time -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 ns VDD > 2.7V -- -- 20 ns VDD < 2.7V SP36 TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge 15 -- -- ns SP40 TDIV2SCH, Setup Time of SDIx Data Input to TDIV2SCL SCKx Edge 15 -- -- ns VDD > 2.7V 20 -- -- ns VDD < 2.7V SP41 TSCH2DIL, TSCL2DIL 15 -- -- ns VDD > 2.7V 20 -- -- ns VDD < 2.7V Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge -- These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. 2009-2013 Microchip Technology Inc. DS60001156H-page 385 PIC32MX5XX/6XX/7XX FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Characteristics(1) Symbol SP70 SP71 SP72 SP73 SP30 SP31 SP35 TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, TSCL2DOV SCKx Input Low Time(3) SCKx Input High Time(3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time(4) SDOx Data Output Rise Time(4) SDOx Data Output Valid after SCKx Edge SP40 TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SP41 Min. Typ.(2) Max. Units Conditions TSCK/2 TSCK/2 -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 20 -- ns ns ns ns ns ns ns ns ns -- -- See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V -- 10 -- -- ns -- 175 -- -- ns -- 5 -- 25 ns -- SP50 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL SP51 TSSH2DOZ SSx to SDOx Output High-Impedance(3) SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 -- -- ns -- TSCL2SSH These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins. Note 1: 2: 3: 4: DS60001156H-page 386 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDIx MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions -- ns -- -- TSCL SCKx Input Low Time(3) TSCK/2 -- SP71 TSCH (3) SCKx Input High Time TSCK/2 -- -- ns SP72 TSCF SCKx Input Fall Time -- 5 10 ns -- SP73 TSCR SCKx Input Rise Time -- 5 10 ns -- SP30 TDOF SDOx Data Output Fall Time(4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 20 ns VDD > 2.7V -- -- 30 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 10 -- -- ns -- SP41 TSCH2DIL, TSCL2DIL 10 -- -- ns -- SP50 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 175 -- -- ns -- SP70 Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins. 2009-2013 Microchip Technology Inc. DS60001156H-page 387 PIC32MX5XX/6XX/7XX TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP51 TSSH2DOZ SSx to SDOX Output High-Impedance(4) 5 -- 25 ns -- SP52 TSCH2SSH SSx after SCKx Edge TSCL2SSH TSCK + 20 -- -- ns -- SP60 TSSL2DOV SDOx Data Output Valid after SSx Edge -- -- 25 ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins. DS60001156H-page 388 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 31-1 for load conditions. 2009-2013 Microchip Technology Inc. DS60001156H-page 389 PIC32MX5XX/6XX/7XX TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. IM10 IM11 Min.(1) Max. Units Conditions TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode(2) TPB * (BRG + 2) -- s -- Clock High Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- mode(2) TPB * (BRG + 2) -- s -- 300 ns THI:SCL Characteristics 1 MHz IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) IM21 IM25 IM26 IM30 IM31 TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time IM34 TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time IM40 IM45 TAA:SCL Output Valid from Clock TBF:SDA Bus Free Time 300 ns -- 100 ns -- 1000 ns 20 + 0.1 CB 300 ns 1 MHz mode(2) -- 300 ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode(2) 100 -- ns 100 kHz mode 0 -- s 400 kHz mode 0 0.9 s 1 MHz mode(2) 0 0.3 s 100 kHz mode TPB * (BRG + 2) -- ns 400 kHz mode TPB * (BRG + 2) -- ns 1 MHz mode(2) TPB * (BRG + 2) -- ns 100 kHz mode TPB * (BRG + 2) -- ns 400 kHz mode ns TPB * (BRG + 2) -- (2) TPB * (BRG + 2) -- ns 100 kHz mode TPB * (BRG + 2) -- ns 1 MHz mode IM33 20 + 0.1 CB -- CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF -- -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- 400 kHz mode TPB * (BRG + 2) -- ns 1 MHz mode(2) TPB * (BRG + 2) -- ns 100 kHz mode TPB * (BRG + 2) -- ns 400 kHz mode TPB * (BRG + 2) -- ns 1 MHz mode(2) TPB * (BRG + 2) -- ns 100 kHz mode -- 3500 ns -- 400 kHz mode -- 1000 ns -- 1 MHz mode(2) -- 350 ns -- 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode(2) 0.5 -- s The amount of time the bus must be free before a new transmission can start -- IM50 CB Bus Capacitive Loading -- 400 pF -- IM51 TPGD Pulse Gobbler Delay(3) 52 312 ns -- Note 1: 2: BRG is the value of the I2CTM Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode). DS60001156H-page 390 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 31-1 for load conditions. 2009-2013 Microchip Technology Inc. DS60001156H-page 391 PIC32MX5XX/6XX/7XX TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Note 1: Symbol TLO:SCL THI:SCL TF:SCL TR:SCL TSU:DAT THD:DAT TSU:STA THD:STA TSU:STO THD:STO TAA:SCL TBF:SDA CB Characteristics Clock Low Time Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time Data Input Setup Time Data Input Hold Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Stop Condition Hold Time Min. Max. Units 100 kHz mode 4.7 -- s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.3 -- s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode(1) 0.5 -- s 100 kHz mode 4.0 -- s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 0.6 -- s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode(1) 0.5 -- s 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 100 ns 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 300 ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode(1) 100 -- ns 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s 100 kHz mode 4700 -- ns 400 kHz mode 600 -- ns 1 MHz mode(1) 250 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode(1) 250 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode(1) 600 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode(1) 250 Output Valid from 100 kHz mode Clock 400 kHz mode Bus Free Time Conditions -- CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF -- -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- -- ns 0 3500 ns 0 1000 ns 1 MHz mode(1) 0 350 ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode(1) 0.5 -- s -- 400 pF Bus Capacitive Loading -- -- The amount of time the bus must be free before a new transmission can start -- Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode). DS60001156H-page 392 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-18: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions CA10 TioF Port Output Fall Time -- -- -- ns See parameter DO32 CA11 TioR Port Output Rise Time -- -- -- ns See parameter DO31 CA20 Tcwf Pulse Width to Trigger CAN Wake-up Filter 700 -- -- ns Note 1: 2: -- These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2009-2013 Microchip Technology Inc. DS60001156H-page 393 PIC32MX5XX/6XX/7XX TABLE 31-35: ETHERNET MODULE SPECIFICATIONS Standard Operating Conditions (see Note 1): 2.9V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Characteristic Min. Typical Max. Units Conditions MIIM Timing Requirements ET1 MDC Duty Cycle 40 -- 60 % -- ET2 MDC Period 400 -- -- ns -- ET3 MDIO Output Setup and Hold 10 -- 10 ns See Figure 31-19 ET4 MDIO Input Setup and Hold 0 -- 300 ns See Figure 31-20 MII Timing Requirements ET5 TX Clock Frequency -- 25 -- MHz -- ET6 TX Clock Duty Cycle 35 -- 65 % -- ET7 ETXDx, ETEN, ETXERR Output Delay 0 -- 25 ns See Figure 31-21 ET8 RX Clock Frequency -- 25 -- MHz -- ET9 RX Clock Duty Cycle 35 -- 65 % -- ET10 ERXDx, ERXDV, ERXERR Setup and Hold 10 -- 30 ns See Figure 31-22 RMII Timing Requirements ET11 Reference Clock Frequency -- 50 -- MHz -- ET12 Reference Clock Duty Cycle 35 -- 65 % -- ET13 ETXDx, ETEN, Setup and Hold 2 -- 16 ns -- ET14 ERXDx, ERXDV, ERXERR Setup and Hold 2 -- 16 ns -- Note 1: The Ethernet module is functional at VBORMIN < VDD < 2.9V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. FIGURE 31-19: MDIO SOURCED BY THE PIC32 DEVICE VIHMIN MDC VILMAX VIHMIN MDIO VILMAX ET3 (Hold) (Setup) ET3 FIGURE 31-20: MDIO SOURCED BY THE PHY VIHMIN MDC VILMAX VIHMIN MDIO VILMAX ET4 DS60001156H-page 394 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-21: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN VILMAX TX Clock VIHMIN ETXD<3:0>, ETEN, ETXERR FIGURE 31-22: VILMAX ET7 RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN RX Clock VILMAX VIHMIN ERXD<3:0>, ERXDV, ERXERR VILMAX (Setup) ET10 ET10 (Hold) 2009-2013 Microchip Technology Inc. DS60001156H-page 395 PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Greater of VDD - 0.3 or 2.5 -- Lesser of VDD + 0.3 or 3.6 V VSS -- VSS + 0.3 V Conditions Device Supply AD01 AD02 AVDD AVSS Module VDD Supply Module VSS Supply -- -- Reference Inputs AD05 VREFH AD05a Reference Voltage High AVSS + 2.0 2.5 -- -- AVDD 3.6 V V (Note 1) VREFH = AVDD (Note 3) AD06 VREFL Reference Voltage Low AVSS -- VREFH - 2.0 V (Note 1) AD07 VREF Absolute Reference Voltage (VREFH - VREFL) 2.0 -- AVDD V (Note 3) Current Drain -- -- 250 -- 400 3 A A ADC operating ADC off AD08 IREF AD08a Analog Input AD12 VINH-VINL Full-Scale Input Span VREFL -- VREFH V -- AD13 VINL Absolute VINL Input Voltage AVSS - 0.3 -- AVDD/2 V -- AD14 VIN Absolute Input Voltage AVSS - 0.3 -- AVDD + 0.3 V -- Leakage Current -- 0.001 0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 k Recommended Impedance of Analog Voltage Source -- -- 5K (Note 1) AD15 AD17 RIN ADC Accuracy - Measurements with External VREF+/VREFAD20c Nr Resolution AD21c INL Integral Nonlinearity > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD22c DNL Differential Nonlinearity > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) AD23c GERR Gain Error > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD24c EOFF Offset Error > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 3.3V AD25c Monotonicity -- -- -- Note 1: 2: 3: 4: 5: -- 10 data bits bits -- -- Guaranteed These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sine wave. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001156H-page 396 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions ADC Accuracy - Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD22d DNL Differential Nonlinearity > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) AD23d GERR Gain Error > -4 -- <4 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD24d EOFF Offset Error > -2 -- <2 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD25d Monotonicity -- -- -- -- Guaranteed -- 10 data bits bits (Note 3) Dynamic Performance AD31b SINAD Signal to Noise and Distortion 55 58.5 -- dB (Notes 3,4) AD34b ENOB Effective Number of Bits 9.0 9.5 -- bits (Notes 3,4) Note 1: 2: 3: 4: 5: These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sine wave. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. 2009-2013 Microchip Technology Inc. DS60001156H-page 397 PIC32MX5XX/6XX/7XX TABLE 31-37: 10-BIT ADC CONVERSION RATE PARAMETERS Standard Operating Conditions (see Note 3): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp ADC Speed(2) 1 Msps to 400 ksps(1) TAD Minimum 65 ns Sampling RS Time Maximum Minimum 132 ns 500 VDD ADC Channels Configuration 3.0V to 3.6V VREF- VREF+ ANx CHX S&H Up to 400 ksps 200 ns 200 ns 5.0 k ADC 2.5V to 3.6V VREF- VREF+ or or AVSS AVDD ANx CHX S&H ADC ANx or VREF- Note 1: 2: 3: External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001156H-page 398 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions (see Note 4): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max. Units Analog-to-Digital Clock Period(2) 65 -- -- ns Conditions Clock Parameters AD50 TAD See Table 31-37 Conversion Rate AD55 TCONV Conversion Time -- 12 TAD -- -- AD56 FCNV Throughput Rate (Sampling Speed) -- -- 1000 ksps AVDD = 3.0V to 3.6V AVDD = 2.5V to 3.6V AD57 TSAMP Sample Time -- -- -- 400 ksps 1 TAD -- -- -- TSAMP must be 132 ns -- 1.0 TAD -- -- Auto-Convert Trigger (SSRC<2:0> = 111) not selected 0.5 TAD -- 1.5 TAD -- -- Timing Parameters AD60 TPCS Conversion Start from Sample Trigger(3) AD61 TPSS Sample Start from Setting Sample (SAMP) bit AD62 TCSS Conversion Completion to Sample Start (ASAM = 1)(3) -- 0.5 TAD -- -- -- AD63 TDPU Time to Stabilize Analog Stage from Analog-to-Digital Off to Analog-to-Digital On(3) -- -- 2 s -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested. The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. 2009-2013 Microchip Technology Inc. DS60001156H-page 399 PIC32MX5XX/6XX/7XX FIGURE 31-23: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit A/D Converter" (DS60001104) of the "PIC32 Family Reference Manual". - Software clears ADxCON. SAMP to start conversion. 3 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. DS60001156H-page 400 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-24: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP TSAMP AD55 TCONV AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit A/D Converter" (DS60001104) of the "PIC32 Family Reference Manual. 6 - One TAD for end of conversion. 3 - Convert bit 9. 8 - Sample for time specified by SAMC<4:0>. 7 - Begin conversion of next channel. 4 - Convert bit 8. 2009-2013 Microchip Technology Inc. DS60001156H-page 401 PIC32MX5XX/6XX/7XX FIGURE 31-25: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Characteristics(1) Symbol Min. Typical Max. Units Conditions 20 -- -- ns -- PS1 TdtV2wrH Data In Valid before WR or CS Inactive (setup time) PS2 TwrH2dtI WR or CS Inactive to Data-In Invalid (hold time) 40 -- -- ns -- PS3 TrdL2dtV RD and CS Active to Data-Out Valid -- -- 60 ns -- PS4 TrdH2dtI RD Activeor CS Inactive to Data-Out Invalid 0 -- 10 ns -- PS5 Tcs CS Active Time TPB + 40 -- -- ns -- PS6 TWR WR Active Time TPB + 25 -- -- ns -- PS7 TRD RD Active Time TPB + 25 -- -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. DS60001156H-page 402 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 31-26: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions PM1 TLAT PMALL/PMALH Pulse Width -- 1 TPB -- -- -- PM2 TADSU Address Out Valid to PMALL/ PMALH Invalid (address setup time) -- 2 TPB -- -- -- PM3 TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) -- 1 TPB -- -- -- PM4 TAHOLD PMRD Inactive to Address Out Invalid (address hold time) 5 -- -- ns -- PM5 TRD PMRD Pulse Width -- 1 TPB -- -- -- PM6 TDSU PMRD or PMENB Active to Data In Valid (data setup time) 15 -- -- ns -- PM7 TDHOLD PMRD or PMENB Inactive to Data In Invalid (data hold time) -- 80 -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 403 PIC32MX5XX/6XX/7XX FIGURE 31-27: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions PM11 TWR PMWR Pulse Width -- 1 TPB -- -- -- PM12 TDVSU Data Out Valid before PMWR or PMENB goes Inactive (data setup time) -- 2 TPB -- -- -- PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time) -- 1 TPB -- -- -- Note 1: These parameters are characterized, but not tested in manufacturing. DS60001156H-page 404 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 31-42: USB OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions USB313 VUSB3V3 USB Voltage 3.0 -- 3.6 V Voltage on VUSB3V3 must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer -- -- 0.8 V -- USB316 VIHUSB Input High Voltage for USB Buffer 2.0 -- -- V -- USB318 VDIFS Differential Input Sensitivity -- -- 0.2 V The difference between D+ and D- must exceed this value while VCM is met USB319 VCM Differential Common Mode Range 0.8 -- 2.5 V -- USB320 ZOUT Driver Output Impedance 28.0 -- 44.0 USB321 VOL Voltage Output Low 0.0 -- 0.3 V 14.25 k load connected to 3.6V USB322 VOH Voltage Output High 2.8 -- 3.6 V 14.25 k load connected to ground Note 1: -- These parameters are characterized, but not tested in manufacturing. 2009-2013 Microchip Technology Inc. DS60001156H-page 405 PIC32MX5XX/6XX/7XX FIGURE 31-28: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Undefined Trf TABLE 31-43: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max. Units Conditions EJ1 TTCKCYC TCK Cycle Time 25 -- ns -- EJ2 TTCKHIGH TCK High Time 10 -- ns -- EJ3 TTCKLOW TCK Low Time 10 -- ns -- EJ4 TTSETUP TAP Signals Setup Time Before Rising TCK 5 -- ns -- EJ5 TTHOLD TAP Signals Hold Time After Rising TCK 3 -- ns -- EJ6 TTDOOUT TDO Output Delay Time from Falling TCK -- 5 ns -- EJ7 TTDOZSTATE TDO 3-State Delay Time from Falling TCK -- 5 ns -- EJ8 TTRSTLOW TRST Low Time 25 -- ns -- EJ9 TRF TAP Signals Rise/Fall Time, All Input and Output -- -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. DS60001156H-page 406 2009-2013 Microchip Technology Inc. Note: DC AND AC DEVICE CHARACTERISTICS GRAPHS The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 32-1: VOH - 4x DRIVER PINS FIGURE 32-3: -0.045 0.045 -0.030 IOH(A) -0.025 -0.020 Absolute Maximum 0.025 0.020 0.015 -0.005 0.005 0.000 0.000 FIGURE 32-2: -0.080 1.50 2.00 2.50 3.00 3.50 0.00 4.00 VOH - 8x DRIVER PINS FIGURE 32-4: VOH(V) -0.070 DS60001156H-page 407 IOH(A) -0.040 Absolute Maximum 0.010 0.000 0.000 1.50 2.00 2.50 3.00 3.50 4.00 3.00 3.50 4.00 VOL - 8x DRIVER PINS 8X VOL(V) 3.6V 3.3V 3V 0.030 -0.010 1.00 2.50 0.040 0 020 0.020 0.50 2.00 0.050 -0.020 0.00 1.50 0.060 3V 0 030 -0.030 1.00 0.070 3.3V -0.050 0.50 0.080 3.6V -0.060 Absolute Maximum Absolute Maximum 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 PIC32MX5XX/6XX/7XX 0.010 1.00 3V 0.030 -0.010 0.50 3.3V 0.035 3V -0.015 3.6V 0.040 3.3V -0.035 0.00 VOL(V) 0.050 3.6V -0.040 IOH(A) VOL - 4x DRIVER PINS VOH (V) -0.050 IOH(A) 2009-2013 Microchip Technology Inc. 32.0 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 408 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX575F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: Example Example PIC32MX575F 512L-80I/PF e3 0510017 Example PIC32MX575F 512L-80I/PT e3 0510017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e) 3 can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2009-2013 Microchip Technology Inc. DS60001156H-page 409 PIC32MX5XX/6XX/7XX 33.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX575F 512H-80I/MR e3 0510017 121-Lead TFBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: DS60001156H-page 410 Example PIC32MX575F 512H-80I/BG e3 0510017 124-Lead VTLA (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Example Example PIC32MX795F 512L-80I/TL e3 0510017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e) 3 can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 33.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2009-2013 Microchip Technology Inc. DS60001156H-page 411 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 412 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX /HDG3ODVWLF7KLQ4XDG)ODWSDFN 3) [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E1 E b N NOTE 1 1 23 A NOTE 2 c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2009-2013 Microchip Technology Inc. DS60001156H-page 413 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 414 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 c A L A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2009-2013 Microchip Technology Inc. DS60001156H-page 415 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 416 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2013 Microchip Technology Inc. DS60001156H-page 417 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 418 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2013 Microchip Technology Inc. DS60001156H-page 419 PIC32MX5XX/6XX/7XX DS60001156H-page 420 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2009-2013 Microchip Technology Inc. DS60001156H-page 421 PIC32MX5XX/6XX/7XX DS60001156H-page 422 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2009-2013 Microchip Technology Inc. DS60001156H-page 423 PIC32MX5XX/6XX/7XX DS60001156H-page 424 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below. For example, to clear a UART receive interrupt, the user application must first read the UART Receive register to clear the interrupt condition and then clear the associated UxIF flag to clear the pending UART interrupt. In other words, the UxIF flag cannot be cleared by software until the UART Receive register is read. A.1 Table A-1 outlines the peripherals and associated interrupts that are implemented differently on PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX devices. DMA PIC32MX5XX/6XX/7XX devices do stopping DMA transfers in Idle mode. A.2 not support Interrupts PIC32MX5XX/6XX/7XX devices have persistent interrupts for some of the peripheral modules. This means that the interrupt condition for these peripherals must be cleared before the interrupt flag can be cleared. TABLE A-1: In addition, on the SPI module, the IRQ numbers for the receive done interrupts were changed from 25 to 24 and the transfer done interrupts were changed from 24 to 25. PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION DIFFERENCES Module Interrupt Implementation Input Capture To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits). SPI Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits, respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF register to obtain the number of data to receive/transmit below the level specified by the SRXISEL<1:0> and STXISEL<1:0> bits. UART TX interrupt will be generated as soon as the UART module is enabled. Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits, respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or UxTXREG registers to obtain the number of data to receive/transmit below the level specified by the URXISEL<1:0> and UTXISEL<1:0> bits. ADC All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source. PMP To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT) register. 2009-2013 Microchip Technology Inc. DS60001156H-page 425 PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision A (August 2009) This is the initial released version of this document. Revision B (November 2009) The revision includes the following global update: Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. Other major changes are referenced by their respective chapter/section in Table B-1. TABLE B-1: MAJOR SECTION UPDATES Section Name Update Description "High-Performance, USB, CAN and Added the following devices: Ethernet 32-bit Flash - PIC32MX575F256L Microcontrollers" - PIC32MX695F512L - PIC32MX695F512H The 100-pin TQFP pin diagrams have been updated to reflect the current pin name locations (see the "Pin Diagrams" section). Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table 1: "PIC32 USB and CAN - Features" Added the following tables: - Table 4: "Pin Names: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L and PIC32MX575F512L Devices" - Table 5: "Pin Names: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L Devices" - Table 6: "Pin Names: PIC32MX775F256L, PIC32MX775F512L and PIC32MX795F512L Devices" Updated the following pins as 5V tolerant: - 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2) 1.0 "Guidelines for Getting Started with 32-bit Microcontrollers" DS60001156H-page 426 Removed the last sentence of 1.3.1 "Internal Regulator Mode". Removed Section 2.3.2 "External Regulator Mode" 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.0 "Memory Organization" Update Description Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-4 to include the PIC32MX575F256L device. Updated the title of Figure 4-6 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device. Updated the title of Table 4-5 to include the PIC32MX575F5256L device. Updated the title of Table 4-6 to include the PIC32MX695F512L device. Reversed the order of Table 4-11 and Table 4-12. Reversed the order of Table 4-14 and Table 4-15. Updated the title of Table 4-15 to include the PIC32MX575F256L and PIC32MX695F512L devices. Updated the title of Table 4-45 to include the PIC32MX575F256L device. Updated the title of Table 4-47 to include the PIC32MX695F512H and PIC32MX695F512L devices. 1.0 "I/O Ports" Updated the second paragraph of 1.1.2 "Digital Inputs" and removed Table 12-1. 22.0 "10-bit Analog-to-Digital Converter (ADC)" Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2). 1.0 "Special Features" Removed references to the ENVREG pin in 1.3 "On-Chip Voltage Regulator". Updated the first sentence of 1.3.1 "On-Chip Regulator and POR" and 1.3.2 "On-Chip Regulator and BOR". Updated the Connections for the On-Chip Regulator (see Figure 1-2). 1.0 "Electrical Characteristics" Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 1-3). Updated the Operating Current (IDD) DC Characteristics (see Table 1-5). Updated the Idle Current (IIDLE) DC Characteristics (see Table 1-6). Updated the Power-Down Current (IPD) DC Characteristics (see Table 1-7). Removed Note 1 from the Program Flash Memory Wait State Characteristics (see Table 1-12). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 113). 1.0 "Packaging Information" Added the 121-pin XBGA package marking information and package details. "Product Identification System" Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed. 2009-2013 Microchip Technology Inc. DS60001156H-page 427 PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Section Name "High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers" Update Description Added the following devices: * PIC32MX675F256H * PIC32MX775F256H * PIC32MX775F512H * PIC32MX675F256L * PIC32MX775F256L * PIC32MX775F512L Added the following pins: * EREFCLK * ECRSDV * AEREFCLK * AECRSDV 1.0 "Device Overview" Added the EREFCLK and ECRSDV pins to Table 5 and Table 6. Updated the pin number pinout I/O descriptions for the following pin names in Table 1-1: * SCL3 * SCL5 * RTCC * C1OUT * SDA3 * SDA5 * CVREF- * C2IN- * SCL2 * TMS * CVREF+ * C2IN+ * SDA2 * TCK * CVREFOUT * C2OUT * SCL4 * TDI * C1IN- * PMA0 * SDA4 * TDO * C1IN+ * PMA1 Added the following pins to the Pinout I/O Descriptions table (Table 1-1): 4.0 "Memory Organization" * EREFCLK * ECRSDV * AEREFCLK * AECRSDV Added new devices and updated the virtual and physical memory map values in Figure 4-4. Added new devices to Figure 4-5. Added new devices to the following register maps: * * * * * * * * 1.0 "Special Features" Appendix A: "Migrating from PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX Devices" DS60001156H-page 428 Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps) Table 4-12 (I2C2 Register Map) Table 4-15 (SPI1 Register Map) Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps) Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps) Table 4-45 (CAN1 Register Map) Table 4-46 (CAN2 Register Map) Table 4-47 (Ethernet Controller Register Map) Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device Configuration Word Summary). Changed all references of POSCMD to POSCMOD in the Device Configuration Word 1 register (see Register 1-2). Added the new section Appendix . 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Revision D (May 2010) The revision includes the following updates, as described in Table B-3: TABLE B-3: MAJOR SECTION UPDATES Section Name "High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers" Update Description Updated the initial Flash memory range to 64K. Updated the initial SRAM memory range to 16K. Added the following devices (see Table 1, Table 2, Table 3 and the Pin Diagrams): * * * * * * * * * * * * 4.0 "Memory Organization" PIC32MX534F064H PIC32MX564F064H PIC32MX664F064H PIC32MX564F128H PIC32MX664F128H PIC32MX764F128H PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3). The bit named I2CSIF was changed to I2C1SIF and the bit named I2CBIF was changed to I2C1BIF in the Interrupt Register Map tables (Table 4-2, Table 4-3, Table 4-4, Table 4-5, Table 4-6 and Table 4-7) Added the following devices to the Interrupt Register Map (Table 4-2): * PIC32MX534F064H * PIC32MX564F064H * PIC32MX564F128H Added the following devices to the Interrupt Register Map (Table 4-3): * PIC32MX664F064H * PIC32MX664F128H Added the following device to the Interrupt Register Map (Table 4-4): * PIC32MX764F128H Added the following devices to the Interrupt Register Map (Table 4-5): * PIC32MX534F064L * PIC32MX564F064L * PIC32MX564F128L Added the following devices to the Interrupt Register Map (Table 4-6): * PIC32MX664F064L * PIC32MX664F128L Added the following device to the Interrupt Register Map (Table 4-7): * PIC32MX764F128L 2009-2013 Microchip Technology Inc. DS60001156H-page 429 PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.0 "Memory Organization" (Continued) Update Description Made the following bit name changes in the I2C1, I2C3, I2C4 and I2C5 Register Map (Table 4-11): * * * * * * * I2C3BRG SFR: I2C1BRG was changed to I2C3BRG I2C4BRG SFR: I2C1BRG was changed to I2C4BRG I2C5BRG SFR: I2C1BRG was changed to I2C5BRG I2C4TRN SFR: I2CT1DATA was changed to I2CT2ADATA I2C4RCV SFR: I2CR2DATA was changed to I2CR2ADATA I2C5TRN SFR: I2CT1DATA was changed to I2CT3ADATA I2C5RCV SFR: I2CR1DATA was changed to I2CR3ADATA Added the RTSMD bit and UEN<1:0> bits to the UART1A, UART1B, UART2A, UART2B, UART3A and UART3B Register Map (Table 4-13) Added the SIDL bit to the DMA Global Register Map (Table 4-17). Changed the CM bit to CMR in the System Control Register Map (Table 4-23). Added the following devices to the I2C2, SPI1, PORTA, PORTC, PORTD, PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-12, Table 4-14, Table 4-24, Table 4-27, Table 4-29, Table 4-31, Table 4-33, Table 4-35 and Table 4-36): * * * * * * PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX664F064L PIC32MX664F128L PIC32MX764F128L Added the following devices to the PORTC, PORTD, PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-26, Table 4-28, Table 4-30, Table 4-32, Table 4-34 and Table 4-37): * * * * * * PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX664F064H PIC32MX664F128H PIC32MX764F128H Added the following devices to the CAN1 Register Map (Table 4-45): * * * * * * * * PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX764F128H PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX764F128L Added the following devices to the Ethernet Controller Register Map (Table 4-47): * * * * * * DS60001156H-page 430 PIC32MX664F064H PIC32MX664F128H PIC32MX764F128H PIC32MX664F064L PIC32MX664F128L PIC32MX764F128L 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description 1.0 "Electrical Characteristics" Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in Table 1-5. Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in Table 1-6. Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD) in Table 1-7. Added DC Characteristics: Program Memory parameters D130a and D132a in Table 1-11. Added the Internal Voltage Reference parameter (D305) to the Comparator Specifications in Table 1-13. 2009-2013 Microchip Technology Inc. DS60001156H-page 431 PIC32MX5XX/6XX/7XX Revision E (July 2010) Revision F (December 2010) Minor corrections were incorporated throughout the document. The revision includes the following global update: VCAP/VDDCORE has been changed to: VCAP/VCORE Other major changes are referenced by their respective chapter/section in Table B-4: TABLE B-4: SECTION UPDATES Section Name Update Description High-Performance, USB, CAN and Removed the following Analog Feature: FV tolerant input pins Ethernet 32-bit Flash Microcontrollers (digital pins only) 1.0 "Device Overview" 4.0 "Memory Organization" Updated the term LIN 1.2 support as LIN support for the peripheral feature: Six UART modules with: RS-232, RS-485, and LIN support Updated the value of 64-pin QFN/TQFP pin number for the following pin names: PMA0, PMA1 and ECRSDV The following register map tables were updated: * Table 4-2: - Changed bits 24/8 to I2C5BIF in IFS1 - Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT - Changed bits 25/9/-24/8 to U5IS<1:0> in IPC12 - Added note 2 * Table 4-3 through Table 4-7: - Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT - Changed bits 25/9-24/8 to U5IS<1:0> in IPC12 * Table 4-3: - Changed bits 24/8 to I2C5BIF in IFS1 - Added note 2 * Table 4-4: - Changed bits 24/8 to I2C5BIF in IFS1 - Changed bits 24/8 to I2C5BIE in IEC1 - Added note 2 references * Table 4-5: - Changed bits 24/8 to I2C5BIF in IFS1 - Changed bits 24/8 to I2C5BIE in IEC1 - Added note 2 references * Table 4-6: - Changed bit 24/8 to I2C5BIF in IFS1 - Updated the bit value of bit 24/8 as I2C5BIE for the IEC1 register. - Added note 2 * Table 4-7: - Changed bit 25/9 to I2C5SIF in IFS1 - Changed bit 24/8 as I2C5BIF in IFS1 - Changed bit 25/9 as I2C5SIE in IEC1 - Changed bit 24/8 as I2C5BIE in IEC1 - Added note 2 references * Added note 2 to Table 4-8 * Updated the All Resets values for the following registers in Table 4-11: I2C3CON, I2C4CON, I2C5CON and I2C1CON. * Updated the All Resets values for the I2C2CON register in Table 4-12 DS60001156H-page 432 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 4.0 "Memory Organization" (Continued) 2009-2013 Microchip Technology Inc. Update Description * Table 4-13: - Changed register U4RG to U1BRG - Changed register U5RG to U3BRG - Changed register U6RG to U2BRG * Table 4-14: - Updated the All Resets values for the following registers: SPI3STAT, SPI2STAT and SPI4STAT * Table 4-15: Updated the All Resets values for the SPI1STAT register * Table 4-17: Added note 2 * Table 4-19: Added note 2 * Table 4-20: Updated the All Resets values for the CM1CON and CM2CON registers * Table 4-21: - Updated the All Resets values as 0000 for the CVRCON register - Updated note 2 * Table 4-38: Updated the All Resets values for the PMSTAT register * Table 4-40: Updated the All Resets values for the CHECON and CHETAG registers * Table 4-42: Updated the bit value of bit 29/13 as `--' for the DEVCFG3 register * Table 4-44: - Updated the note references in the entire table - Changed existing note 1 to note 4 - Added notes 1, 2 and 3 - Changed bits 23/7 in U1PWRC to UACTPND - Changed register U1DDR to U1ADDR - Changed register U4DTP1 to U1BDTP1 - Changed register U4DTP2 to U1BDTP2 - Changed register U4DTP3 to U1BDTP3 * Table 4-45: - Updated the All Resets values for the C1CON and C1VEC registers - Changed bits 30/14 in C1CON to FRZ - Changed bits 27/11 in C1CON to CANBUSY - Changed bits 22/6-16/0 in C1VEC to ICODE<6:0> - Changed bits 22/6-16/0 in C1TREC to RERRCNT<7:0> - Changed bits 31/15-24/8 in C1TREC to TERRCNT<7:0> * Table 4-46: - Updated the All Resets values for the C2CON and C2VEC registers - Changed bits 30/14 in C1CON to FRZ - Changed bits 27/11 in C1CON to CANBUSY - Changed bits 22/6-16/0 in C1VEC register to ICODE<6:0> - Changed bits 22/6-16/0 in C1TREC register to RERRCNT<7:0> - Changed bits 31/15-24/8 in C1TREC to TERRCNT<7:0> DS60001156H-page 433 PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 7.0 "Interrupt Controller" 1.0 "Oscillator Configuration" 1.0 "Output Compare" 1.0 "Ethernet Controller" 1.0 "Comparator Voltage Reference (CVREF)" 1.0 "Special Features" 1.0 "Electrical Characteristics" Update Description * Updated the following Interrupt Sources in Table 7-1: - Changed IC2AM - I2C4 Master Event to: IC4M - I2C4 Master Event - Changed IC3AM - I2C5 Master Event to: IC5M - I2C4 Master Event - Changed U1E - UART1A Error to: U1E - UART1 Error - Changed U4E - UART1B Error to: U4E - UART4 Error - Changed U1RX - UART1A Receiver to: U1RX - UART1 Receiver - Changed U4RX - UART1B Receiver to: U4RX - UART4 Receiver - Changed U1TX - UART1A Transmitter to: U1TX - UART1 Transmitter - Changed U4TX - UART1B Transmitter to: U4TX - UART4 Transmitter - Changed U6E - UART2B Error to: U6E - UART6 Error - Changed U6RX - UART2B Receiver to: U6RX - UART6 Receiver - Changed U6TX - UART2B Transmitter to: U6TX - UART6 Transmitter - Changed U5E - UART3B Error to: U5E - UART5 Error - Changed U5RX - UART3B Receiver to: U5RX - UART5 Receiver - Changed U5TX - UART3B Transmitter to: U5TX - UART5 Transmitter Updated Figure 1-1 Updated Figure 1-1 Added a note on using the Ethernet controller pins (see note above Table 1-3) Updated the note in Figure 1-1 Updated the bit description for bit 10 in Register 1-2 Added notes 1 and 2 to Register 1-4 Updated the Absolute Maximum Ratings: * Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V 0.3V to +3.6V was updated * Voltage on VBUS with respect to VSS - 0.3V to +5.5V was added Updated the maximum value of DC16 as 2.1 in Table 1-4 Updated the Typical values for the following parameters: DC20b, DC20c, DC21c, DC22c and DC23c (see Table 1-5) Updated Table 1-11: * Removed the following DC Characteristics: Programming temperature 0C TA +70C (25C recommended) * Updated the Minimum value for the Parameter number D131 as 2.3 * Removed the Conditions for the following Parameter numbers: D130, D131, D132, D135, D136 and D137 * Updated the condition for the parameter number D130a and D132a Updated the Minimum, Typical and Maximum values for parameter D305 in Table 1-13 Added note 2 to Table 1-18 Updated the Minimum and Maximum values for parameter F20b (see Table 1-19) Updated the following figures: Appendix A: "Migrating from PIC32MX3XX/4XX to PIC32MX5XX/ 6XX/7XX Devices" DS60001156H-page 434 * Figure 1-4 * Figure 1-9 * Figure 1-22 * Figure 1-23 Removed the A.3 Pin Assignments sub-section. 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Revision G (May 2011) The revision includes the following global update: * All references to VDDCORE/VCAP have been changed to: VCORE/VCAP * Added references to the new V-Temp temperature range: -40C to +105C TABLE B-5: This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in Table B-5. MAJOR SECTION UPDATES Section Name Update Description High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers Removed the shading for all D- and D+ pins in all pin diagrams. 1.0 "Device Overview" Updated the VBUS description in Table 1-1. 1.0 "Guidelines for Getting Started with Added "Alternatively, inputs can be reserved by connecting the pin 32-bit Microcontrollers" to Vss through a 1k to 10k resistor and configuring the pin as an input.". 4.0 "Memory Organization" Added Note 3 to the Interrupt Register Map tables (see Table 4-2 through Table 4-7. 22.0 "10-bit Analog-to-Digital Converter Updated the ADC Conversion Clock Period Block Diagram (see (ADC)" Figure 22-2). 1.0 "Comparator Voltage Reference (CVREF)" Updated the Comparator Voltage Reference Block Diagram (see Figure 1-1). 1.0 "Special Features" Removed the second paragraph from 1.3.1 "On-Chip Regulator and POR". 1.0 "Electrical Characteristics" Added the new V-Temp temperature range (-40C to +105C) to the heading of all specification tables. Updated the Ambient temperature under bias, updated the Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added Voltage on VBUS with respect to Vss in Absolute Maximum Ratings. Added the characteristic, DC5a to Operating MIPS vs. Voltage (see Table 1-1). Updated or added the following parameters to the Operating Current (IDD) DC Characteristics: DC20, DC20b, DC23, and DC23b (see Table 15). Added the following parameters to the Idle Current (IIDLE) DC Characteristics: DC30b, DC33b, DC34c, DC35c, and DC36c (see Table 1-6). Added the following parameters to the Power-down Current (IPD) DC Characteristics: DC40g, DC40h, DC40i, and DC41g, (see Table 1-7). Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table 1-32). Updated the 10-bit ADC Conversion Rate Parameters (see Table 1-37). Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion Timing Requirements (see Table 1-38). 1.0 "Packaging Information" Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) - 9x9x0.9 mm Body [QFN] packing diagram. Product Identification System Added the new V-Temp (V) temperature information. 2009-2013 Microchip Technology Inc. DS60001156H-page 435 PIC32MX5XX/6XX/7XX Revision H (March 2013) This revision includes the following global updates: * Where applicable, control register tables have been added to the document * All references to VCORE were removed * All occurrences of XBGA have been updated to: TFBGA * All occurrences of VUSB have been updated to: VUSB3V3 TABLE B-6: This revision also includes minor typographical and formatting changes throughout the data sheet text. All other significant changes are referenced by their respective section in Table B-6. MAJOR SECTION UPDATES Section Name Update Description "32-bit Microcontrollers (up to Updated Core features. 512 KB Flash and 128 KB Added the VTLA to the Packages table. SRAM) with Graphics Interface, USB, CAN, and Added Note 5 to the Feature tables (see Table 1, Table 2, and Table 3). Ethernet" Section 2.0 "Guidelines for Getting Started with 32-bit MCUs" The Recommended Minimum Connection was updated (see Figure 2-1). Section 5.0 "Flash Program Memory" A note regarding Flash page size and row size was added. Section 8.0 "Oscillator Configuration" The RP resistor was added and Note 1 was updated in the Oscillator Diagram (see Figure 8-1). Section 31.0 "Electrical Characteristics" Added Note 1 to Operating MIPS vs. Voltage (see Table 31-1). Added the VTLA package to Thermal Packaging Characteristics (see Table 31-3). Added Note 2 to DC Temperature and Voltage Specifications (see Table 31-4). Updated Note 2 in the Operating Current DC Characteristics (see Table 31-5). Updated Note 1 in the Idle Current DC Characteristics (see Table 31-6). Updated Note 1 in the Power-Down Current DC Characteristics (see Table 31-7). Updated the I/O Pin Output Specifications (see Table 31-9). Added Note 2 to the BOR Electrical Characteristics (see Table 31-10). Added Note 3 to the Comparator Specifications (see Table 31-13). Parameter D320 (VCORE) was removed (see Table 31-15). Updated the Minimum value for parameter OS50 (see Table 31-18). Parameter SY01 (TPWRT) was removed (see Table 31-22). Note 1 was added and the conditions for parameters ET3, ET4, ET7, and ET9 were updated in the Ethernet Module Specifications (see Table 31-35). Added Note 6 to the ADC Module Specifications (see Table 31-36). Added Note 3 to the 10-bit ADC Conversion Rate Parameter (see Table 31-37). Added Note 4 to the Analog-to-Digital Conversion Timing Requirements (see Table 31-38). The following figures were added: * Figure 31-19: "MDIO Sourced by the PIC32 Device" * Figure 31-21: "Transmit Signal Timing Relationships at the MII" * Figure 31-22: "Receive Signal Timing Relationships at the MII" DS60001156H-page 436 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-6: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 32.0 "DC and AC Device Characteristics Graphs" This new chapter was added. Section 33.0 "Packaging Information" Added the 124-lead VTLA package information (see Section 33.1 "Package Marking Information" and Section 33.2 "Package Details"). "Product Identification System" Added the TL definition for VTLA packages. 2009-2013 Microchip Technology Inc. DS60001156H-page 437 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 438 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX INDEX A D AC Characteristics ............................................................ 374 10-bit Conversion Rate Parameters.......................... 398 ADC Specifications ................................................... 396 Analog-to-Digital Conversion Requirements............. 399 EJTAG Timing Requirements ................................... 406 Ethernet .................................................................... 394 Internal FRC Accuracy.............................................. 376 Internal RC Accuracy ................................................ 377 OTG Electrical Specifications ................................... 405 Parallel Master Port Read Requirements ................. 403 Parallel Master Port Write ......................................... 404 Parallel Master Port Write Requirements.................. 404 Parallel Slave Port Requirements ............................. 402 PLL Clock Timing...................................................... 376 Analog-to-Digital Converter (ADC).................................... 247 Assembler MPASM Assembler................................................... 356 DC and AC Characteristics Graphs and Tables ................................................... 407 DC Characteristics............................................................ 360 I/O Pin Input Specifications ...................................... 368 I/O Pin Output Specifications.................................... 370 Idle Current (IIDLE) .................................................... 364 Power-Down Current (IPD)........................................ 366 Program Memory...................................................... 371 Temperature and Voltage Specifications.................. 361 Development Support ....................................................... 355 Direct Memory Access (DMA) Controller.......................... 157 B Block Diagrams ADC1 Module............................................................ 247 Comparator I/O Operating Modes............................. 331 Comparator Voltage Reference ................................ 335 Connections for On-Chip Voltage Regulator............. 350 Core and Peripheral Modules ..................................... 33 DMA .......................................................................... 157 Ethernet Controller.................................................... 289 I2C Circuit ................................................................. 218 Input Capture ............................................................ 205 Interrupt Controller .................................................... 131 JTAG Programming, Debugging and Trace Ports .... 350 MCU............................................................................ 49 Output Compare Module........................................... 209 PIC32 CAN Module................................................... 255 PMP Pinout and Connections to External Devices ... 229 Prefetch Module........................................................ 147 Reset System............................................................ 127 RTCC ........................................................................ 237 SPI Module ............................................................... 211 Timer1....................................................................... 197 Timer2/3/4/5 (16-Bit) ................................................. 201 Typical Multiplexed Port Structure ............................ 193 UART ........................................................................ 223 WDT and Power-up Timer ........................................ 348 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 350 C C Compilers MPLAB C18 .............................................................. 356 Clock Diagram .................................................................. 141 Comparator Specifications............................................................ 372 Comparator Module .......................................................... 331 Comparator Voltage Reference (CVref ............................. 335 Configuration Bits.............................................................. 339 Controller Area Network (CAN)......................................... 255 CPU Module........................................................................ 45 Customer Change Notification Service ............................. 443 Customer Notification Service........................................... 443 Customer Support ............................................................. 443 2009-2013 Microchip Technology Inc. E Electrical Characteristics .................................................. 359 AC............................................................................. 374 Errata .................................................................................. 30 Ethernet Controller............................................................ 289 ETHPMM0 (Ethernet Controller Pattern Match Mask 0)... 296 ETHPMM1 (Ethernet Controller Pattern Match Mask 1)... 296 External Clock Timer1 Timing Requirements ................................... 380 Timer2, 3, 4, 5 Timing Requirements ....................... 381 Timing Requirements ............................................... 375 F Flash Program Memory .................................................... 123 RTSP Operation ....................................................... 123 I I/O Ports ........................................................................... 193 Parallel I/O (PIO) ...................................................... 194 Input Capture .................................................................... 205 Instruction Set................................................................... 353 Inter-Integrated Circuit (I2C) ............................................. 217 Internal Voltage Reference Specifications........................ 373 Internet Address ............................................................... 443 Interrupt Controller............................................................ 131 IRG, Vector and Bit Location .................................... 132 M MCU Architecture Overview ................................................ 50 Coprocessor 0 Registers ............................................ 51 Core Exception Types ................................................ 52 EJTAG Debug Support............................................... 53 Power Management ................................................... 53 MCU Module....................................................................... 49 Memory Map....................................................................... 60 Memory Maps ............................................. 56, 57, 58, 59, 61 Memory Organization ......................................................... 55 Layout......................................................................... 55 Microchip Internet Web Site.............................................. 443 Migration PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 425 MPLAB ASM30 Assembler, Linker, Librarian ................... 356 MPLAB Integrated Development Environment Software.. 355 MPLAB PM3 Device Programmer .................................... 358 MPLAB REAL ICE In-Circuit Emulator System ................ 357 MPLINK Object Linker/MPLIB Object Librarian ................ 356 O Open-Drain Configuration................................................. 194 Oscillator Configuration .................................................... 141 DS60001156H-page 439 PIC32MX5XX/6XX/7XX Output Compare................................................................ 209 P Packaging ......................................................................... 409 Details ....................................................................... 411 Marking ..................................................................... 409 Parallel Master Port (PMP) ............................................... 229 PIC32 Family USB Interface Diagram............................... 174 Pinout I/O Descriptions (table) ............................................ 34 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 350 Power-Saving Features..................................................... 337 CPU Halted Methods ................................................ 337 Operation .................................................................. 337 with CPU Running..................................................... 337 Prefetch Cache ................................................................. 147 Program Flash Memory Wait State Characteristics......................................... 371 R Reader Response ............................................................. 444 Real-Time Clock and Calendar (RTCC)............................ 237 Register Maps ............................................................. 62-116 Registers AD1CHS (ADC Input Select) .................................... 253 AD1CON1 (ADC Control 1) ...................................... 249 AD1CON2 (ADC Control 2) ...................................... 251 AD1CON3 (ADC Control 3) ...................................... 252 AD1CSSL (ADC Input Scan Select) ......................... 254 ALRMDATE (Alarm Date Value) ............................... 245 ALRMTIME (Alarm Time Value) ............................... 244 BMXBOOTSZ (Boot Flash (IFM) Size) ..................... 122 BMXCON (Bus Matrix Configuration) ....................... 117 BMXDKPBA (Data RAM Kernel Program Base Address) .................................................. 118 BMXDRMSZ (Data RAM Size) ................................. 121 BMXDUDBA (Data RAM User Data Base Address) . 119 BMXDUPBA (Data RAM User Program Base Address) .................................................. 120 BMXPFMSZ (Program Flash (PFM) Size) ................ 122 BMXPUPBA (Program Flash (PFM) User Program Base Address) .................................................. 121 CHEACC (Cache Access) ........................................ 149 CHECON (Cache Control) ........................................ 148 CHEHIT (Cache Hit Statistics) .................................. 154 CHELRU (Cache LRU) ............................................. 153 CHEMIS (Cache Miss Statistics) .............................. 154 CHEMSK (Cache TAG Mask) ................................... 151 CHETAG (Cache TAG) ............................................. 150 CHEW0 (Cache Word 0)........................................... 151 CHEW1 (Cache Word 1)........................................... 152 CHEW2 (Cache Word 2)........................................... 152 CHEW3 (Cache Word 3)........................................... 153 CiCFG (CAN Baud Rate Configuration).................... 258 CiCON (CAN Module Control) .................................. 256 CiFIFOBA (CAN Message Buffer Base Address) ..... 283 CiFIFOCINn (CAN Module Message Index Register `n') 288 CiFIFOCONn (CAN FIFO Control Register `n')......... 284 CiFIFOINTn (CAN FIFO Interrupt Register `n') ......... 286 CiFIFOUAn (CAN FIFO User Address Register `n').. 288 CiFLTCON0 (CAN Filter Control 0)........................... 266 CiFLTCON1 (CAN Filter Control 1)........................... 268 CiFLTCON2 (CAN Filter Control 2)........................... 270 CiFLTCON3 (CAN Filter Control 3)........................... 272 DS60001156H-page 440 CiFLTCON4 (CAN Filter Control 4) .......................... 274 CiFLTCON5 (CAN Filter Control 5) .......................... 276 CiFLTCON6 (CAN Filter Control 6) .......................... 278 CiFLTCON7 (CAN Filter Control 7) .......................... 280 CiFSTAT (CAN FIFO Status).................................... 263 CiINT (CAN Interrupt) ............................................... 260 CiRXFn (CAN Acceptance Filter `n')......................... 282 CiRXMn (CAN Acceptance Filter Mask `n') .............. 265 CiRXOVF (CAN Receive FIFO Overflow Status) ..... 264 CiTMR (CAN Timer) ................................................. 264 CiTREC (CAN Transmit/Receive Error Count) ......... 263 CiVEC (CAN Interrupt Code) .................................... 262 CMSTAT (Comparator Control Register).................. 333 CMxCON (Comparator 'x' Control) ........................... 332 CNCON (Change Notice Control)............................. 195 CVRCON (Comparator Voltage Reference Control) 336 DCHxCON (DMA Channel 'x' Control) ..................... 163 DCHxCPTR (DMA Channel 'x' Cell Pointer)............. 170 DCHxCSIZ (DMA Channel 'x' Cell-Size) .................. 170 DCHxDAT (DMA Channel 'x' Pattern Data).............. 171 DCHxDPTR (Channel 'x' Destination Pointer).......... 169 DCHxDSA (DMA Channel 'x' Destination Start Address)................................................... 167 DCHxDSIZ (DMA Channel 'x' Destination Size)....... 168 DCHxECON (DMA Channel 'x' Event Control)......... 164 DCHxINT (DMA Channel 'x' Interrupt Control) ......... 165 DCHxSPTR (DMA Channel 'x' Source Pointer)........ 169 DCHxSSA (DMA Channel 'x' Source Start Address) 167 DCHxSSIZ (DMA Channel 'x' Source Size).............. 168 DCRCCON (DMA CRC Control)............................... 160 DCRCDATA (DMA CRC Data) ................................. 162 DCRCXOR (DMA CRCXOR Enable) ....................... 162 DDPCON (Debug Data Port Control) ....................... 351 DEVCFG0 (Device Configuration Word 0................. 340 DEVCFG1 (Device Configuration Word 1................. 342 DEVCFG2 (Device Configuration Word 2................. 344 DEVCFG3 (Device Configuration Word 3................. 346 DEVID (Device and Revision ID) .............................. 347 DMAADDR (DMA Address) ...................................... 159 DMACON (DMA Controller Control) ......................... 158 DMASTAT (DMA Status) .......................................... 159 EMAC1CFG1 (Ethernet Controller MAC Configuration 1) 313 EMAC1CFG2 (Ethernet Controller MAC Configuration 2) 314 EMAC1CLRT (Ethernet Controller MAC Collision Window/Retry Limit)................................................ 318 EMAC1IPGR (Ethernet Controller MAC Non-Back-toBack Interpacket Gap)...................................... 317 EMAC1IPGT (Ethernet Controller MAC Back-to-Back Interpacket Gap).................................................. 316 EMAC1MADR (Ethernet Controller MAC MII Management Address) .................................................. 324 EMAC1MAXF (Ethernet Controller MAC Maximum Frame Length) .................................................. 319 EMAC1MCFG (Ethernet Controller MAC MII Management Configuration) .......................................... 322 EMAC1MCMD (Ethernet Controller MAC MII Management Command)............................................... 323 EMAC1MIND (Ethernet Controller MAC MII Management Indicators)................................................ 326 EMAC1MRDD (Ethernet Controller MAC MII Management Read Data) .............................................. 325 EMAC1MWTD (Ethernet Controller MAC MII Management Write Data) .............................................. 325 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX EMAC1SA0 (Ethernet Controller MAC Station Address 0)....................................................................... 327 EMAC1SA1 (Ethernet Controller MAC Station Address 1)....................................................................... 328 EMAC1SA2 (Ethernet Controller MAC Station Address 2)....................................................................... 329 EMAC1SUPP (Ethernet Controller MAC PHY Support) . 320 EMAC1TEST (Ethernet Controller MAC Test).......... 321 ETHALGNERR (Ethernet Controller Alignment Errors Statistics) .......................................................... 312 ETHCON1 (Ethernet Controller Control 1)................ 291 ETHCON2 (Ethernet Controller Control 2)................ 293 ETHFCSERR (Ethernet Controller Frame Check Sequence Error Statistics) .................................... 311 ETHFRMRXOK (Ethernet Controller Frames Received OK Statistics) .................................................... 310 ETHFRMTXOK (Ethernet Controller Frames Transmitted OK Statistics) .............................................. 307 ETHHT0 (Ethernet Controller Hash Table 0) ............ 295 ETHHT1 (Ethernet Controller Hash Table 1) ............ 295 ETHIEN (Ethernet Controller Interrupt Enable)......... 301 ETHIRQ (Ethernet Controller Interrupt Request) ...... 302 ETHMCOLFRM (Ethernet Controller Multiple Collision Frames Statistics) ............................................. 309 ETHPM0 (Ethernet Controller Pattern Match Offset) 297 ETHPMCS (Ethernet Controller Pattern Match Checksum) .................................................................. 297 ETHRXFC (Ethernet Controller Receive Filter Configuration) ................................................................... 298 ETHRXOVFLOW (Ethernet Controller Receive Overflow Statistics) .......................................................... 306 ETHRXST (Ethernet Controller RX Packet Descriptor Start Address) ................................................... 294 ETHRXWM (Ethernet Controller Receive Watermarks) . 300 ETHSCOLFRM (Ethernet Controller Single Collision Frames Statistics) ............................................. 308 ETHSTAT (Ethernet Controller Status)..................... 304 ETHTXST (Ethernet Controller TX Packet Descriptor Start Address) ................................................... 294 I2CxCON (I2C Control) ............................................. 219 I2CxSTAT (I2C Status) ............................................. 221 ICxCON (Input Capture 'x' Control) .......................... 206 IECx (Interrupt Enable Control)................................. 137 IFSx (Interrupt Flag Status)....................................... 137 INTCON (Interrupt Control)....................................... 135 INTSTAT (Interrupt Status) ....................................... 136 IPCx (Interrupt Priority Control)................................. 138 NVMADDR (Flash Address) ..................................... 125 NVMCON (Programming Control) ............................ 124 NVMDATA (Flash Program Data)............................. 126 NVMKEY (Programming Unlock).............................. 125 NVMSRCADDR (Source Data Address)................... 126 OCxCON (Output Compare 'x' Control).................... 210 OSCCON (Oscillator Control) ................................... 142 OSCTUN (FRC Tuning) ............................................ 145 PFABT (Prefetch Cache Abort Statistics) ................. 155 PMADDR (Parallel Port Address) ............................. 234 PMAEN (Parallel Port Pin Enable)............................ 235 PMCON (Parallel Port Control) ................................. 230 PMMODE (Parallel Port Mode)................................. 232 PMSTAT (Parallel Port Status (Slave Modes only)... 236 RCON (Reset Control) .............................................. 128 RSWRST (Software Reset) ...................................... 129 2009-2013 Microchip Technology Inc. RTCCON (RTC Control)........................................... 238 RTCDATE (RTC Date Value) ................................... 243 RTCTIME (RTC Time Value).................................... 242 SPIxCON (SPI Control) ............................................ 212 SPIxSTAT (SPI Status) ............................................ 214 T1CON (Type A Timer Control)................................ 198 TPTMR (Temporal Proximity Timer)......................... 136 TxCON (Type B Timer Control) ................................ 203 U1ADDR (USB Address).......................................... 187 U1BDTP1 (USB BDT Page 1) .................................. 189 U1BDTP2 (USB BDT Page 2) .................................. 190 U1BDTP3 (USB BDT Page 3) .................................. 190 U1CNFG1 (USB Configuration 1)............................. 191 U1CON (USB Control).............................................. 185 U1EIE (USB Error Interrupt Enable)......................... 183 U1EIR (USB Error Interrupt Status).......................... 182 U1EP0-U1EP15 (USB Endpoint Control) ................. 192 U1FRMH (USB Frame Number High) ...................... 188 U1FRML (USB Frame Number Low)........................ 187 U1IE (USB Interrupt Enable) .................................... 181 U1IR (USB Interrupt) ................................................ 180 U1OTGCON (USB OTG Control) ............................. 178 U1OTGIE (USB OTG Interrupt Enable).................... 176 U1OTGIR (USB OTG Interrupt Status) .................... 175 U1OTGSTAT (USB OTG Status) ............................. 177 U1PWRC (USB Power Control) ............................... 179 U1SOF (USB SOF Threshold) ................................. 189 U1STAT (USB Status).............................................. 184 U1TOK (USB Token)................................................ 188 UxMODE (UARTx Mode) ......................................... 225 UxSTA (UARTx Status and Control) ........................ 227 WDTCON (Watchdog Timer Control) ....................... 349 Resets .............................................................................. 127 Revision History................................................................ 426 RTCALRM (RTC ALARM Control).................................... 240 S Serial Peripheral Interface (SPI) ....................................... 211 Software Simulator (MPLAB SIM) .................................... 357 Special Features............................................................... 339 T Timer1 Module.................................................................. 197 Timer2/3, Timer4/5 Modules............................................. 201 Timing Diagrams 10-bit Analog-to-Digital Conversion (ASAM = 0, SSRC<2:0> = 000)................................................ 400 10-bit Analog-to-Digital Conversion (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) ............ 401 CAN I/O .................................................................... 393 EJTAG ...................................................................... 406 External Clock .......................................................... 374 I/O Characteristics .................................................... 377 I2Cx Bus Data (Master Mode) .................................. 389 I2Cx Bus Data (Slave Mode) .................................... 391 I2Cx Bus Start/Stop Bits (Master Mode)................... 389 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 391 Input Capture (CAPx) ............................................... 382 OCx/PWM................................................................. 383 Output Compare (OCx) ............................................ 382 Parallel Master Port Read ........................................ 403 Parallel Master Port Write......................................... 404 Parallel Slave Port .................................................... 402 SPIx Master Mode (CKE = 0) ................................... 384 SPIx Master Mode (CKE = 1) ................................... 385 SPIx Slave Mode (CKE = 0) ..................................... 386 DS60001156H-page 441 PIC32MX5XX/6XX/7XX SPIx Slave Mode (CKE = 1)...................................... 387 Timer1, 2, 3, 4, 5 External Clock............................... 380 UART Reception ....................................................... 224 UART Transmission (8-bit or 9-bit Data)................... 224 Timing Requirements CLKO and I/O ........................................................... 377 Timing Specifications CAN I/O Requirements ............................................. 393 I2Cx Bus Data Requirements (Master Mode) ........... 390 I2Cx Bus Data Requirements (Slave Mode) ............. 392 Input Capture Requirements ..................................... 382 Output Compare Requirements ................................ 382 Simple OCx/PWM Mode Requirements.................... 383 SPIx Master Mode (CKE = 0) Requirements ............ 384 SPIx Master Mode (CKE = 1) Requirements ............ 385 SPIx Slave Mode (CKE = 1) Requirements .............. 387 SPIx Slave Mode Requirements (CKE = 0) .............. 386 U UART ................................................................................ 223 USB On-The-Go (OTG) .................................................... 173 V VCAP pin ............................................................................ 350 Voltage Reference Specifications ..................................... 373 Voltage Regulator (On-Chip)............................................. 350 W Watchdog Timer (WDT) .................................................... 348 WWW Address.................................................................. 443 WWW, On-Line Support...................................................... 30 DS60001156H-page 442 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2009-2013 Microchip Technology Inc. DS60001156H-page 443 PIC32MX5XX/6XX/7XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC32MX5XX/6XX/7XX Literature Number: DS60001156H Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS60001156H-page 444 2009-2013 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example: PIC32MX575F256H-80I/PT: General purpose PIC32, 32-bit RISC MCU, 256 KB program memory, 64-pin, Industrial temperature, TQFP package. Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Flash Memory Family Architecture MX = 32-bit RISC MCU core Product Groups 5XX = General purpose microcontroller family 6XX = General purpose microcontroller family 7XX = General purpose microcontroller family Flash Memory Family F = Flash program memory Program Memory Size 256 = 256K 512 = 512K Pin Count H L = 64-pin = 100-pin Speed 80 = 80 MHz Temperature Range I V = -40C to +85C (Industrial) = -40C to +105C (V-Temp) Package PT PT PF MR BG TL = = = = = = Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) 121-Lead (10x10x1.1 mm) TFBGA (Plastic Thin Profile Ball Grid Array) 124-Lead (9x9x0.9 mm) VTLA (Very Thin Leadless Array) 2009-2013 Microchip Technology Inc. DS60001156H-page 445 PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 446 2009-2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-162077-125-9 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2009-2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS60001156H-page 447 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7828 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS60001156H-page 448 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 11/29/12 2009-2013 Microchip Technology Inc.