SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 DisplayPort 1:2 Switch FEATURES APPLICATIONS * * * * * 1 2 * * * One Input Port to One of Two Output Ports Supports Data Rates up to 2.7Gbps Supports Dual-Mode DisplayPort Output Waveform Mimics Input Waveform Characteristics Enhanced ESD: - 12kV on all Main Link Pins - 10kV on all Auxiliary Pins Enhanced Commercial Temperature Range: 0C to 85C 56 Pin 8 x 8 QFN Package Personal Computer Market - Desktop PC - Notebook PC - Docking Station - Standalone Video Card DESCRIPTION The SN75DP128 is a one Dual-Mode DisplayPort input to one of two Dual-Mode DisplayPort outputs. The outputs will follow the input signal in a manner that provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking. Through the SN75DP128 data rates of up to 2.7Gbps through each link for a total throughput of up to 10.8Gbps can be realized. In addition to the switching of the DisplayPort high speed signal lines, the SN75DP128 also supports the switching of the bi-directional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD) channels. The Auxiliary differential pair supports Dual-Mode DisplayPort operation with the ability to be configured as a bi-directional differential bus while in DisplayPort mode or an I2CTM bus while in TMDS mode The SN75DP128 is characterized for operation over ambient air temperature of 0C to 85C. TYPICAL APPLICATION DisplayPort Enabled Monitor or HDTV DP++ GPU DP++ SN75DP128 DP++ DisplayPort Enabled Monitor or HDTV Computer/Notebook/Docking Station 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008, Texas Instruments Incorporated SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DATA FLOW BLOCK DIAGRAM DPVadj ML _ A 0 ( p ) Driver ML _ A 0 ( n ) V BIAS 50 50 Driver ML _ IN 0 (p ) Receiver ML _ IN 0 (n ) Driver 2-to-1 MUX V BIAS 50 ML _ A 3 ( p ) 50 Driver ML _ IN 1 (p ) ML _ A 3 ( n ) Receiver ML _ IN 1 (n ) ML _ B 0 (p ) Driver V BIAS 50 ML _ B 0 (n ) 50 ML _ IN 2 (p ) Driver Receiver ML _ IN 2 (n ) Driver V BIAS 50 50 ML _ B 3 (p ) ML _ IN 3 (p ) Driver ML _ B 3 (n ) Receiver ML _ IN 3 (n ) HPD _ A HPD Switching Logic CAD _ A Priority HPD _ B CAD __ CAD _ B LP AUX _ A (p ) AUX _ A (n ) 2 AUX (p ) AUX _ B (p ) AUX (n ) AUX _ B (n ) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com Priority LP GND CAD_B HPD_B VDD AUX (n) AUX (p) HPD CAD VDD*1 HPD_A GND AUX_A (n) CAD_A SLLS893 - FEBRUARY 2008 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 43 AUX_B (p) GND 44 27 GND AUX_A (p) 45 26 AUX_B(n) ML_A 3(n) 46 25 ML_B 0(p) ML_A 3(p) 47 24 ML_B 0(n) VDD 48 23 VDD ML_A 2(n) 49 22 ML_B 1(p) ML_A 2(p) 50 21 ML_B 1(n) GND 51 20 GND ML_A 1(n) 52 19 ML_B 2(p) ML_A 1(p) 53 18 ML_B 2(n) VDD 54 17 VDD ML_A 0(n) 55 16 ML_B 3(p) ML_A 0(p) 56 ML_B 3(n) 15 10 11 12 13 14 ML_IN 2(p) ML_IN 2(n) VDD 9 ML_IN 3(n) 8 GND 7 ML_IN 3(p) 6 VDD ML_IN 0(p) 5 ML_IN 1(p) VDD 4 ML_IN 1(n) 3 GND 2 ML_IN 0(n) 1 DP Vadj SN75DP128 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION MAIN LINK INPUT PINS ML_IN 0 3, 4 I DisplayPort Main Link Channel 0 Differential Input ML_IN 1 6, 7 I DisplayPort Main Link Channel 1 Differential Input ML_IN 2 9, 10 I DisplayPort Main Link Channel 2 Differential Input ML_IN 3 12, 13 I DisplayPort Main Link Channel 3 Differential Input MAIN LINK PORT A OUTPUT PINS ML_A 0 56, 55 O DisplayPort Main Link Port A Channel 0 Differential Output ML_A 1 53, 52 O DisplayPort Main Link Port A Channel 1 Differential Output ML_A 2 50, 49 O DisplayPort Main Link Port A Channel 2 Differential Output ML_A 3 47, 46 O DisplayPort Main Link Port A Channel 3 Differential Output MAIN LINK PORT B OUTPUT PINS ML_B 0 25, 24 O DisplayPort Main Link Port B Channel 0 Differential Output ML_B 1 22, 21 O DisplayPort Main Link Port B Channel 1 Differential Output ML_B 2 19, 18 O DisplayPort Main Link Port B Channel 2 Differential Output ML_B 3 16, 15 O DisplayPort Main Link Port B Channel 3 Differential Output HOT PLUG DETECT PINS HPD 37 O Hot Plug Detect Output to the DisplayPort Source HDP_A 40 I Port A Hot Plug Detect Input HPD_B 32 I Port B hot Plug Detect Input AUX 36, 35 I/O Source Side Bidirectional DisplayPort Auxiliary Data Line AUX_A 45, 43 I/O Port A Bidirectional DisplayPort Auxiliary Data Line AUXILIARY DATA PINS Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 3 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. AUX_B 28, 26 I/O DESCRIPTION I/O Port B Bidirectional DisplayPort Auxiliary Data Line CABLE ADAPTER DETECT PINS CAD 39 O Cable Adapter Detect Output to the DisplayPort Source CAD_A 41 I Port A Cable Adapter Detect Input CAD_B 33 I Port B Cable Adapter Detect Input LP 30 I Low Power Select Bar Priority 29 I Output Port Priority selection DPVadj 1 I DisplayPort Main Link Output Gain Adjustment CONTROL PINS SUPPLY and GROUND PINS 2, 8, 14, 17, 23, 34, 48, 54 VDD VDD*1 38 GND 5, 11, 20, 27, 42, 44, 51 Primary Supply Voltage HPD and CAD Output Voltage Ground Table 1. Control Pin Lookup Table SIGNAL LP Priority DPVadj (1) LEVEL (1) STATE H Normal Mode L Low Power Mode Device is forced into a Low Power state causing the outputs to go to a high impedance state. All other inputs are ignored H Port B has Priority If both HPD_A and HPD_B are high, Port B will be selected L Port A has Priority If both HPD_A and HPD_B are high, Port A will be selected 4.53 k Increased Gain 6.49 k Normal Gain 10 k Decreased Gain DESCRIPTION Normal operational mode for device Main Link DisplayPort Output will have an increased voltage swing Main Link DisplayPort Output will have a nominal voltage swing Main Link DisplayPort Output will have a decreased voltage swing (H) Logic High; (L) Logic Low Explanation of the internal switching logic of the SN75DP128 is located in the Application Information section at the end of the data sheet. ORDERING INFORMATION (1) (1) 4 PART NUMBER PART MARKING PACKAGE SN75DP128RTQR DP128 56-pin QFN Reel (large) SN75DP128RTQT DP128 56-pin QFN Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT -0.3 to 5.25 V 1.5 V HPD and CAD I/O -0.3 to VDD + 0.3 V Auxiliary I/O -0.3 to VDD + 0.3 V Control I/O -0.3 to VDD + 0.3 V Auxiliary I/O (AUX +/-, AUX_A +/-, & AUX_B +/-) 10000 V All Other Pins 12000 Supply Voltage Range (2) VDD, VDD*1 Main Link I/O (ML_IN x, ML_A x, ML_B x) Differential Voltage Voltage Range Human body model Electrostatic discharge (3) Charged-device model (3) Machine model (4) Continuous power dissipation (1) (2) (3) (4) 1000 V 200 V See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS PACKAGE PCB JEDEC STANDARD TA 25C DERATING FACTOR (1) ABOVE TA = 25C Low-K 3623 mW 36.23 mW/C 1449 mW High-K 1109 mW 11.03 mW/C 443.9 mW 56-pin QFN (RTQ) (1) TA = 85C POWER RATING This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS RJB Junction-to-board thermal resistance RJC Junction-to-case thermal resistance PD Device power dissipation DisplayPort selected PSD Device power dissipation under low LP = 0V, HPD/CAD A and B = 5V; VDD*1 = VDD power (1) MIN 4x4 Thermal vias under powerpad LP = 5V, ML: VID = 600 mV, 2.7 Gbps PRBS; AUX: VID = 500 mV, 1Mbps PRBS; HPD/CAD A and B = 5V; VDD*1 = VDD TYP MAX (1) UNIT 11.03 C/W 20.4 C/W 300 340 mW 85 W The maximum rating is simulated under 5.25 V VDD. RECOMMENDED OPERATING CONDITIONS VDD VDD Supply Voltage *1 TA HPD and CAD Output reference voltage Operating free-air temperature MIN NOM MAX UNIT 4.5 5 5.25 V 1.62 5.25 V 0 85 C 0.15 1.4 V 2.7 Gbps 55 2 V MAIN LINK DIFFERENTIAL PINS VID Peak-to-peak input differential voltage dR Data rate Rt Termination resistance VOterm Output termination voltage 45 0 50 AUXILIARY PINS Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 5 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 RECOMMENDED OPERATING CONDITIONS (continued) MIN VI Input voltage dR Data rate NOM 0 MAX 3.6 1 UNIT V MHz HPD, CAD, AND CONTROL PINS VIH High-level input voltage 2 5.25 V VIL Low-level input voltage 0 0.8 V DEVICE POWER The SN75DP128 is designed to operate off a single 5V supply. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 60 65 mA 0.1 4 mA 1 16 A *1 IDD Supply current LP = 5V, VDD = VDD ML: VID = 600 mV, 2.7 Gbps PRBS AUX: VID = 500 mV, 1 Mbps PRBS HPD/CAD A and B = 5 V IDD*1 Supply current VDD*1 = 5.25 V ISD Shutdown current LP = 0 V HOT PLUG AND CABLE ADAPTER DETECT The SN75DP128 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals. The SN75DP128 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD and CAD pins is defined by the voltage level of the VDD*1 pin. Explanation of HPD and the internal logic of the SN75DP128 is located in the application section at the end of the data sheet. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOH5 High-level output voltage IOH = -100 A, VDD*1 = 5 V VOH3.3 High-level output voltage IOH = -100 A, VDD*1 = 3.3 V VOH2.5 High-level output voltage IOH = -100 A, VOH1.8 High-level output voltage IOH = -100 A, VOL Low-level output voltage IOH = 100 A IH High-level input current VIH = 2.0 V, IL Low-level input current VIL = 0.8 V, MIN TYP MAX UNIT 4.5 5 V 3 3.3 V VDD = 2.5 V 2.25 2.5 V VDD*1 = 1.8 V 1.62 1.8 V 0 0.4 V VDD = 5.25 V -10 10 A VDD = 5.25 V -10 10 A *1 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPD(CAD) Propagation delay VDD*1 = 5 V 5 30 ns tPD(HPD) Propagation delay VDD*1 = 5 V 30 110 ns *1 tT1(HPD) HPD logic switch pause time VDD = 5 V 2 4.7 ms tT2(HPD) HPD logic switch time VDD*1 = 5 V 170 400 ms tM(HPD) Minimum output pulse duration VDD*1 = 5 V 100 tZ(HPD) Low Power to High-level propagation delay VDD*1 = 5 V 30 6 Submit Documentation Feedback ns 50 110 ns Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 HPD Input HPD Output DP128 100K 100K Figure 1. HPD Test Circuit 0V VDD HPD_B HPD_A Sink Hot Plug Detect Pulse Duration 50% 0V tPD(HPD) VDD*1 HPD Minimum Hot Plug Detect Output Pulse Duration 50% tm(HPD) 0V Figure 2. HPD Timing Diagram #1 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 7 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 HPD_A & HPD_B VDD VDD Priority 0V Sink Hot Plug Detect Timeout tT2(HPD) t1(HPD) VDD*1 HPD 0V Port B Selected Port A Selected Figure 3. HPD Timing Diagram #2 HPD_B 0V VDD HPD_A 50 % 0V tZ(HPD) VDD*1 HPD 50 % 0V Figure 4. HPD Timing Diagram #3 Auxiliary Pins The SN75DP128 is designed to support the 1:2 switching of the bidirectional auxiliary signals in both a differential (DisplayPort) mode and an I2C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimized based on the status of the selected output port's CAD pin. 8 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VPass1 Maximum passthrough voltage (CAD=1) VDD = 4.5 V, VI = 5 V, IO = 100 A 2.4 3.6 V IOZ Output current from unselected output VDD = 5.25 V, VO = 0-3.6 V, VI = 0 V -5 5 A CIO(off) I/O capacitance when in low power DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, 9 12 pF CIO(on) DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, CAD = I/O capacitance when in normal operation High 18 25 pF rON(C0) On resistance VDD = 4.5 V, VI = 0 - 3.6 V, IO = 5 mA, CAD = Low 3.5 10 rON On resistance VDD = 4.5 V, VI = 0 - 3.6 V, IO = 5 mA, CAD = Low 1 5 rON(C1) On resistance VDD = 4.5 V, VI = 0.4 V, IO = 3 mA, CAD = High 10 18 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tsk(AUX) Intra-pair skew VID = 400 mV, VIC = 2 V IL(AUX) Single Line Insertion Loss VID = 500 mV, VIC = 2 V, F = 1 MHz, CAD = Low tPLH(AUXC0) Propagation delay time, low to high tPHL(AUXC0) Propagation delay time, high to low tPLH(AUXC1) tPHL(AUXC1) TYP MAX UNIT 80 ps 0.4 dB CAD = Low, F = 1 MHz 3 ps CAD = Low, F = 1 MHz 3 ps Propagation delay time, low to high CAD = High, F = 100 kHz 3 ns Propagation delay time, high to low CAD = High, F = 100 kHz 3 ns 3.3V 50 40 3.3V 100K 50 AUX+ 10 pF 0.5 pF AUX- 100 SN 75 DP 128 CAD = 0 Figure 5. Auxiliary Channel Test Circuit (CAD = LOW) 3.3 V 3.3 V SN75DP128 2 K 10 pF AUX + or - 100 K 50 pF CAD = 1 Figure 6. Auxiliary Channel Test Circuit (CAD = HIGH) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 9 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 2. 2 V 50 % 1. 8 V Tsk(AUX) Figure 7. Auxiliary Channel Skew Measurement 2.2V AUX Input 1.8V Differential 0V AUX Input tPHL(AUXC0) tPLH(AUXC0) Differential AUX Output 0 V Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW) 2V AUX Input + or - 1V 0V tPHL(AUX1) tPLH(AUX1) 2V AUX Output + or - 1V 0V Figure 9. Auxiliary Channel Delay Measurement (CAD = HIGH) Main Link Pins The SN75DP128 is designed to support the 1:2 switching of DisplayPort's high speed differential main link. The main link I/O of the SN75DP128 are designed to track the magnitude and frequency characteristics of the input waveform and replicate them on the output. A feature has also been incorporated in the SN75DP128 to either increase or decrease the output amplitude via the resistor connected between the DPVADJ pin and ground. 10 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VI/O(2) VI/O(3) VI/O(4) Difference between input and output) voltages (VOD - VID) VI/O(6) RINT Input termination impedance VIterm Input termination voltage TEST CONDITIONS MIN TYP MAX VID = 200 mV, DPVadj = 6.5 k 0 30 60 mV VID = 300 mV, DPVadj = 6.5 k -24 11 36 mV VID = 400 mV, DPVadj = 6.5 k -45 -15 15 mV VID = 600 mV, DPVadj = 6.5 k -87 -47 -22 mV 45 50 55 2 V TYP MAX UNIT 115 160 ps 240 280 ps 20 ps 40 ps 35 ps 0 UNIT SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tR/F(DP) Output edge rate (20%-80%) Input edge rate = 80 ps (20%-80%) tPD Propagation delay time F= 1 MHz, VID = 400 mV tSK(1) Intra-pair skew F= 1 MHz, VID = 400 mV tSK(2) Inter-pair skew F= 1 MHz, VID = 400 mV tDPJIT(PP) Peak-to-peak output residual jitter dR = 2.7 Gbps, VID = 400 mV, PRBS 27-1 200 VIterm 25 0V to 2V 50 W 50 W 50 W D+ V VD+ ID 50 W 0.5 pF Receiver Driver D- Y 100 pF VY Z VD- 100 pF VZ VOD = VY - VZ VOC = (VY + VZ) 2 VID = VD+ - VDVICM = (VD+ + VD- ) 2 Figure 10. Main Link Test Circuit tR/FDP Input DVI/O Output Input Edge Rate 20% to 80% 80 ps DVI/O Figure 11. Main Link VI/O and Edge Rate Measurements Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 11 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 ML_IN x+ ML_IN x- Main Link Input 0V tPD(ML) tPD(ML) Main Link Output 0V Figure 12. Main Link Delay Measurements 2.2 V ML x+ 50 % ML x- 1.8 V Tsk1 Tsk2 2.2 V ML y+ 50 % ML y- 1.8 V Tsk1 Figure 13. Main Link Skew Measurements 12 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 TYPICAL CHARACTERISTICS INPUT/OUTPUT VOLTAGE vs RESISTANCE INPUT/OUTPUT VOLTAGE vs SUPPLY VOLTAGE 80 100 VID = 300 mV 50 VID = 400 mV 0 -50 VID = 600 mV -100 Temp = 25oC 2k 4k 60 VID = 300 mV 50 40 VID = 400 mV 30 20 10 VID = 600 mV 0 6k 8k 10k 12k -20 4.4 14k 4.6 DPVadj - Resistance - W Figure 15. INPUT EDGE RATE vs OUTPUT EDGE RATE POWER DISSIPATION vs DATA RATE 290 o VDD = 5 V, 25 C 140 120 o 100 VDD = 4.5 V, 0 C 80 60 40 20 0 0 5.4 300 VDD = 5.25 V, 85oC PD - Power Dissipation - mW Output Edge Rate 20% - 80% (ps) 160 4.8 5 5.2 VDD - Supply Voltage - V Figure 14. 200 180 VID = 200 mV -10 -150 0 Temp = 25oC 70 VID = 200 mV DVI/O - Input/Output Voltage - mV DVI\O - Input/Output Voltage - mV 150 280 270 85oC 260 250 240 o 0C 25oC 230 220 210 200 50 100 150 Input Edge Rate 20% - 80% (ps) 200 0 Figure 16. 500M 1G 1.5G 2G 2.5G Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 3G Data Rate - Bps Figure 17. 13 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 APPLICATION INFORMATION SWITCHING LOGIC The switching logic of the SN75DP128 is tied to the state of the HPD input pins as well as the priority pin and low power pin. When both HPD_A and HPD_B input pins are LOW, the SN75DP128 enters the low power state. In this state the outputs are high impedance, and the device is shutdown to optimize power conservation. When either HPD_A or HPD_B goes high, the device enters the normal operational state, and the port associated with the HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH, the port selection is determined by the state of the priority pin. Several key factors were taken into consideration with this digital logic implementation of channel selection as well as HPD repeating. This logic has been divided into the following four scenarios. 1. Low power state to active state. There are two possible cases for this scenario depending on the state of the low power pin: - Case one: In this case both HPD inputs are initially LOW and the low power pin is also LOW. In this initial state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device remains in the low power mode with both the main link and auxiliary I/O in a high impedance state. However, the port associated with the HPD input that went HIGH is still selected and the HPD output to the source is enabled and follows the logic state of the input HPD (see Figure 18). The state of the Priority pin has no effect in this scenario as only one HPD input port is active. 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 HI-Z Channel A 0 1 HI-Z Channel B 0 Figure 18. - Case two: In this case both HPD inputs are initially LOW and the low power pin is HIGH. In this initial state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device comes out of the low power mode and enters active mode enabling the main link and auxiliary I/O. The port associated with the HPD input that went HIGH is selected and the HPD output to the source is enabled and follows the logic state of the input HPD (see Figure 19). This is specified as tZ(HPD). Again,the state of the Priority pin has no effect in this scenario as only one HPD input port is active. 14 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 HI-Z Channel A DATA 0 1 HI-Z Channel B 0 Figure 19. 2. HPD Changes on the selected port. There are also two possible starting cases for this scenario: - Case one: In this case only one HPD input is initially HIGH. The HPD output logic state follows the state of the HPD input. If the HPD input pulses LOW, as may be the case if the Sink device is requesting an interrupt, the HPD output to the source also pulses LOW for the same duration of time with a slight delay (see Figure 20). The delay of this signal through the SN75DP128 is specified as tPD(HPD). If the duration of the LOW pulse is less then tM(HPD), it may not be accurately repeated to the source. If the duration of the LOW pulse exceeds tT2(HPD), the device assumes that an unplug event has occurred and enters the low power state (see Figure 21). Once the HPD input goes high again, the device returns to the active state as indicated in scenario 1. The state of the Priority pin has no effect in this scenario as only one HPD input port is active. 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 20. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 15 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A HI-Z 0 1 HI-Z Channel B 0 Figure 21. - Case two: In this case both HPD inputs are initially HIGH and the selected port has been determined by the state of the priority pin. The HPD output logic state follows the state of the selected HPD input. If the HPD input pulses LOW, the HPD output to the source also pulses LOW for the same duration of time, again with a slight delay (see Figure 22). If the duration of the LOW pulse exceeds tT2(HPD), the device assumes that an unplug event has occurred and the other port is selected (see Figure 23). The case in which the previously selected port with priority goes high again is covered in scenario 3. 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 22. 16 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 Channel A DATA HI-Z HI-Z DATA 0 1 Channel B 0 Figure 23. 3. One channel becomes active while other channel is already selected. There are also two possible starting cases for this scenario: - Case one: In this case the HPD input that is initially HIGH is from the port that has priority. Since the port with priority is already selected, any activity on the HPD input from the other port doesnot have any effect on the switch whatsoever (see Figure 24). 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 24. - Case two: In this case the HPD input that is initially HIGH is not the port with priority. When the HPD input of the port that has priority goes high, the HPD output is forced LOW for some time in order to simulate an unplug event to the source device. The duration of this LOW output is defined as tT2(HPD). If the HPD input of the port with priority pulses LOW for a short duration while the tT2(HPD) timer is counting down, the timer is reset. Once this time has passed the switch switches to the port with priority and the output HPD Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 17 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 once again follows the state of the newly selected channel's HPD input (see Figure 25). 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 Channel A DATA HI-Z HI-Z DATA 0 1 Channel B 0 Figure 25. 4. 4. Priority pin is toggled. There are also two possible starting cases for this scenario: - Case one: In this case only one HPD input is HIGH. A port whose HPD input is LOW cannot be selected. In this case, the state of the priority pin has no effect on the switch (see Figure 26). 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 26. - Case two: In this case both HPD inputs are HIGH. Changing the state of the priority pin when both HPD inputs are high forces the device to switch which channel is selected. When a state change is detected on the priority pin, the device waits for a short period of time tT1(HPD) before responding (see Figure 27). The purpose for this pause is to allow for the priority signal to settle and also to allow the device to ignore potential glitches on the priority pin. Once tT1(HPD) has expired, the HPD output is forced LOW for tT2(HPD) and the device follows the chain of events outlined in scenario 3 case 2. 18 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 SN75DP128 www.ti.com SLLS893 - FEBRUARY 2008 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 Channel A DATA HI-Z HI-Z DATA 0 1 Channel B 0 Figure 27. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP128 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) SN75DP128RTQR NRND QFN RTQ 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 DP128 SN75DP128RTQRG4 NRND QFN RTQ 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 DP128 SN75DP128RTQT NRND QFN RTQ 56 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 DP128 SN75DP128RTQTG4 NRND QFN RTQ 56 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 DP128 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75DP128RTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 SN75DP128RTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75DP128RTQR QFN RTQ 56 2000 367.0 367.0 38.0 SN75DP128RTQT QFN RTQ 56 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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