CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
General-Purpose and PCI-X 1:4 Clock
Buffer
D
Operating Frequency: 0 MHz to 140 MHz
D
Low Output Skew: <100 ps
D
Distributes One Clock Input to One Bank of
Four Outputs
D
Output Enable Control That Drives Outputs
Low When OE Is Low
D
Operates From Single 3.3-V Supply
D
8-Pin TSSOP Package
description
The CDCV304 is a high-performance, low-skew, general-purpose and PCI-X clock buffer. It distributes one input
clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications.
The CDCV304 operates at 3.3 V.
The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications.
FUNCTION TABLE
INPUTS OUTPUT
CLKIN OE 1Y (0:3)
L
H
L
H
L
L
H
H
L
L
L
H
functional block diagram
3
5
7
8
1Y0
1Y1
1Y2
1Y3
Logic
Control
2
1
OE
CLKIN
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
CLKIN
OE
1Y0
GND
1Y3
1Y2
VDD3.3V
1Y1
TSSOP
PW PACKAGE
(TOP VIEW)
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
1Y[0–3] 3, 5, 7, 8 OBuffered output clocks
CLKIN 1 I Input reference frequency
GND 4 Power Ground
OE 2 I Outputs enable control
VDD3.3V 6 Power 3.3-V supply
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD –0.5 V to 4.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Notes 1 and 2) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VDD) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDD) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total output current, IO (VO = 0 to VDD) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): PW package 230.5°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD 3 3.3 3.6 V
High-level input voltage, VIH 0.7×VDD V
Low-level input voltage, VIL 0.3×VDD V
Input voltage, VI0 VDD V
High-level output current, IOH –24 mA
Low-level output current, IOL 24 mA
Operating free-air temperature, TA–40 85 °C
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN NOM MAX UNIT
fclk Clock frequency 0 140 MHz
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input voltage VDD = 3 V, II = –18 mA –1.2 V
VDD = min to max, IOH = –1 mA VDD–0.2
VOH High-level output voltage VDD = 3 V, IOH = –24 mA 2V
VDD = 3 V, IOH = –12 mA 2.4
VDD = min to max, IOL = 1 mA 0.2
VOL Low-level output voltage VDD = 3 V, IOL = 24 mA 0.8 V
VDD = 3 V, IOL = 12 mA 0.55
IOH
High level out
p
ut current
VDD = 3 V, VO = 1 V –50
mA
I
OH
High
-
level
output
current
VDD = 3.3 V, VO = 1.65 V –55
mA
IOL
Low level out
p
ut current
VDD = 3 V, VO = 2 V 60
mA
I
OL
Low
-
level
output
current
VDD = 3.3 V, VO = 1.65 V 70
mA
IIInput current VI = VO or VDD ±5µA
IDD Dynamic current, See Figure 5 f = 67 MHz 37 mA
CiInput capacitance VDD = 3.3 V, VI = 0 V or VDD 3 pF
CoOutput capacitance VDD = 3.3 V, VI = 0 V or VDD 3.2 pF
†All typical values are at respective nominal VDD and 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 10 pF, VDD = 3.3 V ± 0.3 V (see Note 6 and Figures 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
tPLH High-to-low propagation delay
See Figures 1 and 2
1.8 2.5 3 ns
tPHL Low-to-high propagation delay
See
Figures
1
and
2
1.8 2.4 3 ns
tsk(o) Output skew (see Note 4) 50 100 ps
tsk(p) Pulse skew VIH = VDD, VIL = 0 V 150 ps
tsk(pr) Process skew 0.2 0.3 ns
tsk(pp) Part-to-part skew 0.25 0.4 ns
Thi h
CLK high time See Figure 4
66 MHz 6
ns
T
high
CLK
high
time
,
See
Figure
4
140 MHz 3
ns
Tl
CLK low time See Figure 4
66 MHz 6
ns
T
low
CLK
low
time
,
See
Figure
4
140 MHz 3
ns
trOutput rise slew rate‡0.2VDD to 0.6VDD 1.5 2.7 4 V/ns
tfOutput fall slew rate‡0.6VDD to 0.2VDD 1.5 2.7 4 V/ns
†All typical values are at respective nominal VDD.
‡This symbol is according to PCI-X terminology.
NOTE 4: The tsk(o) specification is only valid for equal loading of all outputs.
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
140 Ω
Yn
VDD
10 pF
140 Ω
Figure 1. Test Load Circuit
0.6 VDD
1Y0 – 1Y3
50% VDD
0.2 VDD
tf
VOL
VOH
tr
CLKIN 0 V
VDD
tPHL
50% VDD
tPLH
0.6 VDD
50% VDD
0.2 VDD
Figure 2. Voltage Thresholds for Propagation Delay (tpd) Measurements
50% VDD
Any Y
Any Y
tsk(0)
50% VDD
Figure 3. Output Skew
thigh
VIH(Min)
Vtest
VIL(Max)
tlow
tcyc
0.4 VDD
Peak to Peak (Minimum)
0.2 VDD
0.6 VDD
PARAMETER VALUE UNIT
VIH(Min)
VIL(Max)
Vtest
0.5 VDD
0.35 VDD
0.4 VDD
V
V
V
NOTE: All parameters in Figure 4 are according to PCI-X 1.0 specifications.
Figure 4. Clock Waveform
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
f – Frequency – MHz
20
30
40
50
60
0 20 40 60 80 100 120 140 160
SUPPLY CURRENT
vs
FREQUENCY
VDD = 3.6 V
TA = 85°C
ICC – Supply Current – mA
Figure 5
IOH – High-Level Output Current – mA
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 3.3 V
TA = 25°C
VOH– High-Level Output Voltage – V
Figure 6
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
IOL – Low-Level Output Current – mA
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–20 0 20 40 60 80 100 120
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 3.3 V
TA = 25°C
OL
V– Low-Level Output Voltage – V
Figure 7
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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Copyright 2002, Texas Instruments Incorporated