September 2009 Doc ID 15056 Rev 3 1/69
1
STM32F102x8
STM32F102xB
Medium-density USB access line, ARM-based 32-bit MCU with 64/128KB
Flash, USB FS interface, 6 timers, ADC & 8 communication interfaces
Features
■Core: ARM 32-bit Cortex™-M3 CPU
– 48 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 WS memory access
– Single-cycle multiplication and hardware
division
■Memories
– 64 or 128 Kbytes of Flash memory
– 10 or 16 Kbytes of SRAM
■Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■Low power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC and backup registers
■Debug mode
– Serial wire debug (SWD) and JTAG
interfaces
■DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
■1 × 12-bit, 1.2 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
■Up to 51 fast I/O ports
– 37/51 IOs all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
■Up to 6 timers
– Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 2 watchdog timers (Independent and
Window)
– SysTick timer: 24-bit downcounter
■Up to 8 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (12 Mbit/s)
– USB 2.0 full speed interface
■CRC calculation unit, 96-bit unique ID
■ECOPACK® packages
Table 1. Device summary
Reference Part number
STM32F102x8 STM32F102C8, STM32F102R8
STM32F102xB STM32F102CB, STM32F102RB
LQFP48
7 × 7 mm
LQFP64
10 × 10 mm
www.st.com
Contents STM32F102x8, STM32F102xB
2/69 Doc ID 15056 Rev 3
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 46
5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F102x8, STM32F102xB Contents
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5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.1 Evaluating the maximum junction temperature for an application . . . . . 66
7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
List of tables STM32F102x8, STM32F102xB
4/69 Doc ID 15056 Rev 3
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F102x8 and STM32F102xB medium-density USB access line
features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. STM32F102xx USB access line family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Medium-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 32
Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 32
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 36
Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 33. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 34. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 35. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 36. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 37. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 38. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 39. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 40. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 41. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 42. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 43. USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 44. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STM32F102x8, STM32F102xB List of tables
Doc ID 15056 Rev 3 5/69
Table 45. RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 46. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 47. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 48. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 49. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 63
Table 50. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 64
Table 51. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 52. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
List of figures STM32F102x8, STM32F102xB
6/69 Doc ID 15056 Rev 3
List of figures
Figure 1. STM32F102xx medium-density USB access line block diagram . . . . . . . . . . . . . . . . . . . . 10
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 18
Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 18
Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 31
Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 31
Figure 12. Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 23. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 24. SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 27. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 29. Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 30. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 63
Figure 31. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 32. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 64
Figure 33. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 34. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
STM32F102x8, STM32F102xB Introduction
Doc ID 15056 Rev 3 7/69
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F102x4 and STM32F102x6 medium-density USB access line microcontrollers.
For more details on the whole STMicroelectronics STM32F102xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F102xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Description STM32F102x8, STM32F102xB
8/69 Doc ID 15056 Rev 3
2 Description
The STM32F102xx medium-density USB access line incorporates the high-performance
ARM Cortex™-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed
embedded memories (Flash memory of 64 or 128 Kbytes and SRAM of 10 or 16 Kbytes),
and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All
devices offer standard communication interfaces (two I2Cs, two SPIs, one USB and three
USARTs), one 12-bit ADC and three general-purpose 16-bit timers.
The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to
3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-
power applications.
The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm
and LQFP64 10 × 10 mm packages.
The STM32F102xx medium-density USB access line microcontrollers are suitable for a
wide range of applications:
●Application control and user interface
●Medical and handheld equipment
●PC peripherals, gaming and GPS platforms
●Industrial applications: PLC, inverters, printers, and scanners
●Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
STM32F102x8, STM32F102xB Description
Doc ID 15056 Rev 3 9/69
2.1 Device overview
Table 2. STM32F102x8 and STM32F102xB medium-density USB access line
features and peripheral counts
Peripheral STM32F102Cx STM32F102Rx
Flash - Kbytes 64 128 64 128
SRAM - Kbytes 10 16 10 16
Timers General-purpose 33 3 3
Communication
interfaces
SPI 22 2 2
I2C22 2 2
USART 33 3 3
USB 11 1 1
12-bit synchronized ADC
number of channels
1
10 channels
1
16 channels
GPIOs 37 51
CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperatures Ambient temperature: –40 to +85 °C (see Ta ble 8)
Junction temperature: –40 to +105 °C (see Ta b l e 8 )
Packages LQFP48 LQFP64
Description STM32F102x8, STM32F102xB
10/69 Doc ID 15056 Rev 3
Figure 1. STM32F102xx medium-density USB access line block diagram
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C).
Temp sen sor
PA[15:1]
EXTI
W W D G
NVIC
12bit ADC1
SWD
16 AF
JTDI
JTCK/SWCLK
JTMS/SWDIO
JNTRST
JTDO
NRST
V
DD
= 2 to 3.6V
51AF
PB[15:0]
PC[15:0]
AHB2
MOSI,MISO,SCK,NSS
SRAM
x16bit)
WAKEUP
GPIOA
GPIOB
GPIOC
F
max
: 48 MHz
V
SS
SCL,SDA, SMBA
I2C2
GP DMA
TIM2
TIM3
XTAL OSC
4-16 MHz
XTAL 32 kHz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
PLL &
APB1: F
max
= 24 MHz
PCLK1
HCLK CLOCK
MANAGT
PCLK 2
as AF
as AF
VOLT. REG.
3.3V TO 1.8V
POWER
Backup interface
as AF
16 KB
RTC
RC 8 MHz
Cortex M3 CPU
USART1
USART2
SPI2
7 channels
Backup
reg
SCL,SDA,SMBA
I2C1
as AF
RX,TX, CTS, RTS,
USART3
PD[2:0] GPIOD
AHB: Fmax=48 MHz
4 Chann els
4 Chann els
FCLK
RC 40 kHz
Stand by
IWDG
@VDD
@VBAT
POR / PDR
SUPPLY
@VDDA
VDDA
VSSA
@VDDA
V
BAT
CK, Smartcard as AF
RX,TX, CTS, RTS,
Smart Card as AF
RX,TX, CTS, RTS,
APB2 : F
max
= 48 MHz
NVIC
SPI1
MOSI,MISO,
SCK,NSS as AF
IF
interface
@VDDA
SUPERVISION
PVD
Rst
Int
@VDD
AHB2
APB2 APB 1 AWU TAMPER-RTC
Flash 128 KB
BusMatrix
64 bit
Interface
Ibus
Dbus
pbus
obl
Flash
Trace
Controlleront
System
TIM4 4 Channels
ai14868f
TRACECLK
TRACED[0:3]
as AS
SW/JTAG
TPIU
Trace/trig
CK, Smartcard as AF
USB 2.0 FS
USBDP, USBDM as AF
STM32F102x8, STM32F102xB Description
Doc ID 15056 Rev 3 11/69
Figure 2. Clock tree
1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at
48 MHz.
2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.
HSE OSC
4-16 MHz
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
HSI RC
8 MHz
LSI RC
40 kHz
to Independent Watchdog (IWDG)
PLL
x2, x3, x4
PLLMUL
Legend:
MCO
Clock Output
Main
PLLXTPRE
/2
..., x16 AHB
Prescaler
/1, 2..512
/2 PLLCLK
HSI
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADC
Prescaler
/2, 4, 6, 8 ADCCLK
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
USBCLK
to USB interface
to TIM2, 3
and 4
USB
Prescaler
/1, 1.5
to ADC
LSE
LSI
HSI
/128
/2
HSI
HSE
peripherals
to APB1
Peripheral Clock
Enable (13 bits)
Enable (3 bits)
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
peripherals
to APB2
Peripheral Clock
Enable (11 bits)
48 MHz
48 MHz max
48 MHz
48 MHz max
24 MHz max
to RTC
PLLSRC SW
MCO
CSS
to Cortex System timer
/8
Clock
Enable (3 bits)
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TIMXCLK
IWDGCLK
SYSCLK
FCLK Cortex
free running clock
TIM2,3, 4
If (APB1 prescaler =1) x1
else x2
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
ai14994
Description STM32F102x8, STM32F102xB
12/69 Doc ID 15056 Rev 3
2.2 Full compatibility throughout the family
The STM32F102xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are
referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred to
as medium-density devices.
Low-density devices are an extension of the STM32F102x8/B devices, they are specified in
the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM
capacities, a timer and a few communication interfaces less.
The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B
medium-density devices, allowing the user to try different memory densities and providing a
greater degree of freedom during the development cycle.
Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx
access line and STM32F103xx performance line devices.
2.3 Overview
ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F102xx medium-density USB access line having an embedded ARM core, is
therefore compatible with all ARM tools and software.
Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
Table 3. STM32F102xx USB access line family
Pinout
Low-density STM32F102xx devices Medium-density STM32F102xx devices
16 KB Flash 32 KB Flash(1)
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F102x8/B medium-density devices.
64 KB Flash 128 KB Flash
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
64 2 × USARTs, 2 × 16-bit timers
1 × SPI, 1 × I2C, 1 × ADC, 1 × USB
3 × USARTs, 3 × 16-bit timers
2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB
48
STM32F102x8, STM32F102xB Description
Doc ID 15056 Rev 3 13/69
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Embedded SRAM
10 or 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F102xx medium-density USB access line embeds a nested vectored interrupt
controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
●Closely coupled NVIC gives low latency interrupt processing
●Interrupt entry vector table address passed directly to the core
●Closely coupled NVIC core interface
●Allows early processing of interrupts
●Processing of late arriving higher priority interrupts
●Support for tail-chaining
●Processor state automatically saved
●Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16
external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 48 MHz. See Figure 2 for details on the clock tree.
Description STM32F102x8, STM32F102xB
14/69 Doc ID 15056 Rev 3
Boot modes
At startup, boot pins are used to select one of five boot options:
●Boot from User Flash
●Boot from System Memory
●Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
●VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 8: Power supply scheme.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●MR is used in the nominal regulation mode (Run)
●LPR is used in the Stop mode
●Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
STM32F102x8, STM32F102xB Description
Doc ID 15056 Rev 3 15/69
Low-power modes
The STM32F102xx medium-density USB access line supports three low-power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
●Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
●Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and registers content are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers
TIMx and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
Description STM32F102x8, STM32F102xB
16/69 Doc ID 15056 Rev 3
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
●A 24-bit down counter
●Autoreload capability
●Maskable system interrupt generation when the counter reaches 0.
●Programmable clock source
General-purpose timers (TIMx)
There are 3 synchronizable general-purpose timers embedded in the STM32F102xx
medium-density USB access line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
capture, output compare, PWM or one-pulse mode output. This gives up to 12 input
captures / output compares / PWMs on the LQFP48 and LQFP64 packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode.
Any of the general-purpose timers can be used to generate PWM outputs. They all have
independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
I²C bus
Two I²C bus interfaces can operate in multi-master and slave modes. They can support
standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit
addressing in master mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
STM32F102x8, STM32F102xB Description
Doc ID 15056 Rev 3 17/69
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-duplex
and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
Universal serial bus (USB)
The STM32F102xx medium-density USB access line embeds a USB device peripheral
compatible with the USB Full-speed 12 Mbs. The USB interface implements a full-speed (12
Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator).
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
Temperature sensor
The temperature sensor has to generate a a voltage that varies linearly with temperature.
The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Pinouts and pin description STM32F102x8, STM32F102xB
18/69 Doc ID 15056 Rev 3
3 Pinouts and pin description
Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout
Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
LQFP48
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VDD_2
VSS_2
PA1 3
PA1 2
PA1 1
PA1 0
PA9
PA8
PB15
PB14
PB13
PB12
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA 0 - W K U P
PA 1
PA 2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA 1 5
PA 1 4
ai14378d
PC13-TAMPER-RTC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA 0 - W K U P
PA1
PA2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA 15
PA 14
VDD_2
VSS_2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
LQFP64
ai14387c
PC13-TAMPER-RTC
STM32F102x8, STM32F102xB Pinouts and pin description
Doc ID 15056 Rev 3 19/69
Table 4. Medium-density STM32F102xx pin definitions
Pins
Pin name
Type(1)
I / O level(2)
Main
function(3)
(after reset)
Alternate functions(3) (4)
LQFP48
LQFP64
Default Remap
11 V
BAT SV
BAT
2 2 PC13-TAMPER-RTC(5) I/O PC13(6) TAMPER-RTC
3 3 PC14-OSC32_IN(5) I/O PC14(6) OSC32_IN
4 4 PC15-OSC32_OUT(5) I/O PC15(6) OSC32_OUT
5 5 PD0 I/O FT OSC_IN(7)
6 6 PD1 I/O FT OSC_OUT(7)
7 7 NRST I/O NRST
- 8 PC0 I/O PC0 ADC_IN10
- 9 PC1 I/O PC1 ADC_IN11
- 10 PC2 I/O PC2 ADC_IN12
- 11 PC3 I/O PC3 ADC_IN13
812 V
SSA SV
SSA
913 V
DDA SV
DDA
10 14 PA0-WKUP I/O PA0
WKUP/USART2_CTS/
ADC_IN0/
TIM2_CH1_ETR(8)
11 15 PA1 I/O PA1 USART2_RTS/
ADC_IN1/TIM2_CH2(8)
12 16 PA2 I/O PA2 USART2_TX/
ADC_IN2/TIM2_CH3(8)
13 17 PA3 I/O PA3 USART2_RX/
ADC_IN3/TIM2_CH4(8)
-18 V
SS_4 SV
SS_4
-19 V
DD_4 SV
DD_4
14 20 PA4 I/O PA4 SPI1_NSS(8)/ADC_IN4
USART2_CK/
15 21 PA5 I/O PA5 SPI1_SCK(8)/ADC_IN5
16 22 PA6 I/O PA6 SPI1_MISO(8)/ADC_IN6/
TIM3_CH1(8)
17 23 PA7 I/O PA7 SPI1_MOSI(8)/ADC_IN7/
TIM3_CH2(8)
- 24 PC4 I/O PC4 ADC_IN14
- 25 PC5 I/O PC5 ADC_IN15
18 26 PB0 I/O PB0 ADC_IN8/TIM3_CH3(8)
19 27 PB1 I/O PB1 ADC_IN9/TIM3_CH4(8)
20 28 PB2 I/O FT PB2/BOOT1
Pinouts and pin description STM32F102x8, STM32F102xB
20/69 Doc ID 15056 Rev 3
21 29 PB10 I/O FT PB10 I2C2_SCL/ USART3_TX(8) TIM2_CH3
22 30 PB11 I/O FT PB11 I2C2_SDA/ USART3_RX(8) TIM2_CH4
23 31 VSS_1 SV
SS_1
24 32 VDD_1 SV
DD_1
25 33 PB12 I/O FT PB12 SPI2_NSS / I2C2_SMBA/
USART3_CK(8)
26 34 PB13 I/O FT PB13 SPI2_SCK(8)/
USART3_CTS
27 35 PB14 I/O FT PB14 SPI2_MISO/
USART3_RTS
28 36 PB15 I/O FT PB15 SPI2_MOSI
- 37 PC6 I/O FT PC6 TIM3_CH1
- 38 PC7 I/O FT PC7 TIM3_CH2
- 39 PC8 I/O FT PC8 TIM3_CH3
- 40 PC9 I/O FT PC9 TIM3_CH4
29 41 PA8 I/O FT PA8 USART1_CK/MCO
30 42 PA9 I/O FT PA9 USART1_TX(8)
31 43 PA10 I/O FT PA10 USART1_RX(8)
32 44 PA11 I/O FT PA11 USART1_CTS/USBDM
33 45 PA12 I/O FT PA12 USART1_RTS/USBDP
34 46 PA13 I/O FT JTMS-SWDIO PA13
35 47 VSS_2 SV
SS_2
36 48 VDD_2 SV
DD_2
37 49 PA14 I/O FT JTCK/SWCLK PA14
38 50 PA15 I/O FT JTDI TIM2_CH1_ETR/
PA15 /SPI1_NSS
- 51 PC10 I/O FT PC10 USART3_TX
- 52 PC11 I/O FT PC11 USART3_RX
- 53 PC12 I/O FT PC12 USART3_CK
- 54 PD2 I/O FT PD2 TIM3_ETR
39 55 PB3 I/O FT JTDO
TIM2_CH2/ PB3/
TRACESWO/
SPI1_SCK
40 56 PB4 I/O FT JNTRST TIM3_CH1 / PB4
SPI1_MISO
Table 4. Medium-density STM32F102xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O level(2)
Main
function(3)
(after reset)
Alternate functions(3) (4)
LQFP48
LQFP64
Default Remap
STM32F102x8, STM32F102xB Pinouts and pin description
Doc ID 15056 Rev 3 21/69
41 57 PB5 I/O PB5 I2C1_SMBA TIM3_CH2 /
SPI1_MOSI
42 58 PB6 I/O FT PB6 I2C1_SCL(8)/ TIM4_CH1 USART1_TX
43 59 PB7 I/O FT PB7 I2C1_SDA(8)/ TIM4_CH2 USART1_RX
44 60 BOOT0 I BOOT0
45 61 PB8 I/O FT PB8 TIM4_CH3 I2C1_SCL
46 62 PB9 I/O FT PB9 TIM4_CH4 I2C1_SDA
47 63 VSS_3 SV
SS_3
48 64 VDD_3 SV
DD_3
1. I = input, O = output, S = supply.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 9Table 3 on page 12.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the
STMicroelectronics website: www.st.com.
7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function
I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
Table 4. Medium-density STM32F102xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O level(2)
Main
function(3)
(after reset)
Alternate functions(3) (4)
LQFP48
LQFP64
Default Remap
Memory mapping STM32F102x8, STM32F102xB
22/69 Doc ID 15056 Rev 3
4 Memory mapping
The memory map is shown in Figure 5.
Figure 5. Memory map
1K
APB memory space
DMA
RTC
WWDG
IWDG
SPI2
USART2
USART3
ADC1
USART1
SPI1
1K
35K
1K
1K
2K
1K
1K
2K
1K
1K
1K
1K
1K
7K
1K
1K
1K
1K
3K
1K
1K
1K
1K
1K
1K
1K
1K
2K
1K
1K
1K
I2C2
EXTI
RCC
1K
1K
1K
1K
1K
1K
1K
1K
3K
1K
3K
1K
4K
0
1
2
3
4
5
6
7
Peripherals
SRAM
reserved
reserved
Option Bytes
Reserved
0x4000 0000
0x4000 0400
0x4000 0800
0x4000 0C00
0x4000 2800
0x4000 2C00
0x4000 3000
0x4000 3400
0x4000 3800
0x4000 3C00
0x4000 4400
0x4000 4800
0x4000 4C00
0x4000 5400
0x4000 5800
0x4000 5C00
0x4000 6000
0x4000 6400
0x4000 6800
0x4000 6C00
0x4000 7000
0x4000 7400
0x4001 0000
0x4001 0400
0x4001 0800
0x4001 0C00
0x4001 1000
0x4001 1400
0x4001 1800
0x4001 1C00
0x4001 2400
0x4001 2800
0x4001 2C00
0x4001 3000
0x4001 3400
0x4001 3800
0x4001 3C00
0x4002 0000
0x4002 0400
0x4002 1000
0x4002 1400
0x4002 2000
0x4002 2400
0x4002 3000
0x4002 3400
0x6000 0000
0xE010 0000
0xFFFF FFFF
reserved
reserved
reserved
CRC
reserved
reserved
Flash interface
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Port D
Port C
Port B
Port A
AFIO
PWR
BKP
reserved
reserved
512 byte USB SRAM
USB registers
I2C1
reserved
reserved
reserved
reserved
TIM4
TIM3
TIM2
0xFFFF FFFF
0xE010 0000
0xE000 0000
0xC000 0000
0xA000 0000
0x8000 0000
0x6000 0000
0x4000 0000
0x2000 0000
0x0000 0000
0x1FFF FFFF
0x1FFF F80F
0x1FFF F800
0x1FFF F000
0x0801FFFF
0x0800 0000
System memory
Flash memory
Cortex-M3 internal
peripherals
ai14971c
0x2000 3FFF
0xE000 0000
Cortex-M3 internal
peripherals
0x0000 0000
Aliased to Flash or
system memory
depending on
BOOT pins
reserved
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 23/69
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2VVDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Electrical characteristics STM32F102x8, STM32F102xB
24/69 Doc ID 15056 Rev 3
5.1.6 Power supply scheme
Figure 8. Power supply scheme
Caution: In Figure 8, the 4.7 µF capacitor must be connected to VDD3.
Figure 6. Pin loading conditions Figure 7. Pin input voltage
ai14972
C = 50 pF
STM32F102 pin
ai14973
STM32F102 pin
VIN
ai14882c
VDD
1/2/3/4
Analo g:
RCs, PLL,
...
Power switch
VBAT
GP I/O s
OUT
IN
Kernel logic
(CPU,
Digital
& Memories)
Backup circuitry
(OSC32K,RTC,
Backup registers)
Wake-up logic
3 × 100 nF
+ 1 × 4.7 µF
1.8-3.6 V
Regulator
VSS
1/2/3/4
VDDA
VSSA
ADC
Level shifter
IO
Logic
VDD
10 nF
+ 1 µF
VDD
V
REF+
V
REF-
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 25/69
5.1.7 Current consumption measurement
Figure 9. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 5. Voltage characteristics
Symbol Ratings Min Max Unit
VDD VSS
External main supply voltage (including
VDDA and VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN
Input voltage on five volt tolerant pin(2)
2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is
induced by VIN<VSS.
VSS 0.3 +5.5
Input voltage on any other pin(2) VSS 0.3 VDD+0.3
|VDDx| Variations between different VDD power pins 50
mV
|VSSX VSS|Variations between all the different ground
pins 50
VESD(HBM)
Electrostatic discharge voltage (human body
model)
see Section 5.3.11: Absolute
maximum ratings (electrical
sensitivity)
Electrical characteristics STM32F102x8, STM32F102xB
26/69 Doc ID 15056 Rev 3
Table 6. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD/VDDA power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
150
mA
IVSS Total current out of VSS ground lines (sink)(1) 150
IIO
Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin 25
IINJ(PIN) (2)(3)
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC
characteristics.
Injected current on NRST pin ± 5
Injected current on High-speed external OSC_IN and Low-
speed external OSC_IN pins ± 5
Injected current on any other pin(4)
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
± 5
IINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25
Table 7. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 27/69
5.3 Operating conditions
5.3.1 General operating conditions
5.3.2 Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 9. Operating conditions at power-up / power-down
Table 8. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 48
MHzfPCLK1 Internal APB1 clock frequency 0 24
fPCLK2 Internal APB2 clock frequency 0 48
VDD Standard operating voltage 2 3.6 V
VDDA(1)
1. When the ADC is used, refer to Table 44: ADC characteristics.
Analog operating voltage
(ADC not used) Must be the same potential
as VDD(2)
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
23.6
V
Analog operating voltage
(ADC used) 2.4 3.6
VBAT Backup operating voltage 1.8 3.6 V
PD
Power dissipation at TA =
85 °C(3)
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 65).
LQFP48 363 mW
LQFP64 444
TA Ambient temperature Maximum power dissipation –40 85 °C
Low power dissipation(4)
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 65).
–40 105 °C
TJ Junction temperature range –40 105 °C
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate 0
µs/V
VDD fall time rate 20
Electrical characteristics STM32F102x8, STM32F102xB
28/69 Doc ID 15056 Rev 3
5.3.3 Embedded reset and power control block characteristics
The parameters given in Ta b l e 1 0 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 8 .
.
5.3.4 Embedded reference voltage
The parameters given in Ta b l e 1 1 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 8 .
Table 10. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
VPVDhyst(2) PVD hysteresis 100 mV
VPOR/PDR
Power on/power down
reset threshold
Falling edge 1.8(1)
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
VPDRhyst PDR hysteresis 40 mV
tRSTTEMPO(2)
2. Guaranteed by design, not tested in production.
Reset temporization 1.5 2.5 4.5 ms
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 29/69
5.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 9: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●All I/O pins are in input mode with a static value at VDD or VSS (no load)
●All peripherals are disabled except if it is explicitly mentioned
●The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz)
●Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
●When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Ta b l e 1 2 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 8 .
Table 11. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +85 °C 1.16 1.20 1.24 V
TS_vrefint(1)
1. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading
the internal reference voltage 5.1 17.1(2)
2. Guaranteed by design, not tested in production.
µs
VRERINT(2) Internal reference voltage spread
over the temperature range VDD = 3 V ±10 mV 10 mV
TCoeff(2) Temperature coefficient 100 ppm/
°C
Electrical characteristics STM32F102x8, STM32F102xB
30/69 Doc ID 15056 Rev 3
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions fHCLK
Max(1)
1. Based on characterization results, not tested in production.
Unit
TA = 85 °C
IDD
Supply current
in Run mode
External clock (2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 36.1
mA
36 MHz 28.6
24 MHz 19.9
16 MHz 14.7
8 MHz 8.6
External clock (2), all
peripherals Disabled
48 MHz 24.4
36 MHz 19.8
24 MHz 13.9
16 MHz 10.7
8 MHz 6.8
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM
Symbol Parameter Conditions fHCLK
Max
Unit
TA = 85 °C(1)
1. Based on characterization, tested in production at VDD max, fHCLK max.
IDD
Supply current in
Run mode
External clock (2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 31.5
mA
36 MHz 24
24 MHz 17.5
16 MHz 12.5
8 MHz 7.5
External clock(2) all
peripherals disabled
48 MHz 20.5
36 MHz 16
24 MHz 11.5
16 MHz 8.5
8 MHz 5.5
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 31/69
Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
0
2
4
6
8
10
12
14
16
18
20
–40 0 25 70 85
Temperature (°C)
Consumption (mA)
48 MHz
36 MHz
16 MHz
8 MHz
Electrical characteristics STM32F102x8, STM32F102xB
32/69 Doc ID 15056 Rev 3
Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM
Symbol Parameter Conditions fHCLK
Max(1)
Unit
TA = 85 °C
IDD
Supply current in
Sleep mode
External clock(2) all
peripherals enabled
48 MHz 20
mA
36 MHz 15.5
24 MHz 11.5
16 MHz 8.5
8 MHz 5.5
External clock(2), all
peripherals disabled
48 MHz 6
36 MHz 5
24 MHz 4.5
16 MHz 4
8 MHz 3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15. Typical and maximum current consumptions in Stop and Standby modes
Symbol Parameter Conditions
Typ(1) Max
Unit
VDD/ VBAT
= 2.4 V
VDD/VBAT
= 3.3 V
VDD/VBAT
= 2.0 V
TA =
85 °C
IDD
Supply current
in Stop mode
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
23.5 24 - 200
µA
Regulator in Low Power mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
13.5 14 - 180
Supply current
in Standby
mode(2)
Low-speed internal RC oscillator and
independent watchdog ON 2.6 3.4 - TBD(3)
Low-speed internal RC oscillator ON,
independent watchdog OFF 2.4 3.2 - TBD(3)
Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF
1.7 2 - 4
IDD_VBAT
Backup domain
supply current Low-speed oscillator and RTC ON 1.1 1.4 0.9 1.9(4)
1. Typical values are measured at TA = 25 °C.
2. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).
3. TBD stands for to be determined.
4. Based on characterization, not tested in production.
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 33/69
Figure 12. Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values
Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V
0
0.5
1
1.5
2
2.5
–40 °C 25 °C 70 °C 85 °C 105 °C
Temperature (°C)
Consumption ( µA )
2 V
2.4 V
3 V
3.6 V
ai17351
0
20
40
60
80
100
120
140
-45 25 70 90
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
Electrical characteristics STM32F102x8, STM32F102xB
34/69 Doc ID 15056 Rev 3
Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V
Figure 15. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V
0
20
40
60
80
100
120
140
-40 0 25 70 85
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
Standby mode
0
0.5
1
1.5
2
2.5
3
-45 25 70 90
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 35/69
Typical current consumption
The MCU is placed under the following conditions:
●All I/O pins are in input mode with a static value at VDD or VSS (no load)
●All peripherals are disabled except if it is explicitly mentioned
●The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz)
●Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
●When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
The parameters given in Ta b l e 1 6 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 8 .
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions fHCLK
Typ(1)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Typ(1)
Unit
All peripherals
enabled(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
IDD
Supply
current in
Run mode
External
clock(3)
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 24.2 18.6
mA
36 MHz 19 14.8
24 MHz 12.9 10.1
16 MHz 9.3 7.4
8 MHz 5.5 4.6
4 MHz 3.3 2.8
2 MHz 2.2 1.9
1 MHz 1.6 1.45
500 kHz 1.3 1.25
125 kHz 1.08 1.06
Running on
high speed
internal RC
(HSI), AHB
prescaler
used to
reduce the
frequency
48 MHz 23.5 17.9
36 MHz 18.3 14.1
24 MHz 12.2 9.5
16 MHz 8.5 6.8
8 MHz 4.9 4
4 MHz 2.7 2.2
2 MHz 1.6 1.4
1 MHz 1.02 0.9
500 kHz 0.73 0.67
125 kHz 0.5 0.48
Electrical characteristics STM32F102x8, STM32F102xB
36/69 Doc ID 15056 Rev 3
Table 17. Typical current consumption in Sleep mode, code running from Flash or
RAM
Symbol Parameter Conditions fHCLK
Typ(1)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Typ(1)
Unit
All peripherals
enabled(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
IDD
Supply
current in
Sleep mode
External clock(3)
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
48 MHz 9.9 3.9
mA
36 MHz 7.6 3.1
24 MHz 5.3 2.3
16 MHz 3.8 1.8
8 MHz 2.1 1.2
4 MHz 1.6 1.1
2 MHz 1.3 1
1 MHz 1.11 0.98
500 kHz 1.04 0.96
125 kHz 0.98 0.95
Running on High
Speed Internal
RC (HSI), AHB
prescaler used to
reduce the
frequency
48 MHz 9.3 3.3
36 MHz 7 2.5
24 MHz 4.8 1.8
16 MHz 3.2 1.2
8 MHz 1.6 0.6
4 MHz 1 0.5
2 MHz 0.72 0.47
1 MHz 0.56 0.44
500 kHz 0.49 0.42
125 kHz 0.43 0.41
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 37/69
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Ta bl e 1 8 . The MCU is placed
under the following conditions:
●all I/O pins are in input mode with a static value at VDD or VSS (no load)
●all peripherals are disabled unless otherwise mentioned
●the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
●ambient operating temperature and VDD supply voltage conditions summarized in
Ta b le 5 .
Table 18. Peripheral current consumption
Peripheral Typical consumption at 25 °C(1)
1. fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
Unit
APB1
TIM2 0.90
mA
TIM3 0.86
TIM4 0.88
SPI2 0.26
USART2 0.45
USART3 0.43
USB 0.57
I2C1 0.24
I2C2 0.25
APB2
GPIO A 0.45
GPIO B 0.32
GPIO C 0.49
GPIO D 0.32
ADC1(2)
2. Specific conditions for ADC: fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fHCLK/4, ADON bit
in the ADC_CR2 register is set to 1.
1.51
SPI1 0.21
USART1 0.72
Electrical characteristics STM32F102x8, STM32F102xB
38/69 Doc ID 15056 Rev 3
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Ta b le 1 9 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 8 .
Low-speed external user clock generated from an external source
The characteristics given in Ta b le 2 0 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 8 .
Table 19. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext User external clock source frequency(1) 1825MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD VDD V
VHSEL OSC_IN input pin low level voltage VSS 0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1) 16
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) 20
Cin(HSE) OSC_IN input capacitance(1) 5pF
DuCy(HSE) Duty cycle 45 55 %
ILOSC_IN Input leakage current VSS VIN VDD ±1 µA
1. Guaranteed by design, not tested in production.
Table 20. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User external clock source frequency(1) 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage 0.7VDD VDD V
VLSEL OSC32_IN input pin low level voltage VSS 0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1) 450
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) 50
Cin(LSE) OSC32_IN input capacitance(1) 5pF
DuCy(LSE) Duty cycle 30 70 %
ILOSC32_IN Input leakage current VSS VIN VDD ±1 µA
1. Guaranteed by design, not tested in production.
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 39/69
Figure 16. High-speed external clock source AC timing diagram
Figure 17. Low-speed external clock source AC timing diagram
ai14975b
OSC _I N
STM32F102xx
VHSEH
tf(HSE) tW(HSE)
IL
90%
10%
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
External
clock source
ai14976b
OSC32_IN
STM32F102xx
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
External
clock source
Electrical characteristics STM32F102x8, STM32F102xB
40/69 Doc ID 15056 Rev 3
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 21 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Table 21. HSE 4-16 MHz oscillator characteristics(1)(2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency 4 8 16 MHz
RFFeedback resistor 200 k
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
RS = 30 30 pF
i2HSE driving current VDD = 3.3 V
VIN = VSS with 30 pF load 1mA
gmOscillator transconductance Startup 25 mA/V
tSU(HSE)
(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized 2 ms
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 41/69
Figure 18. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 22 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol Parameter Conditions Min Typ Max Unit
RFFeedback resistor 5 M
C(1)
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(2)
2. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
RS = 30 k15 pF
I2LSE driving current VDD = 3.3 V
VIN = VSS
1.4 µA
gmOscillator transconductance 5 µA/V
tSU(LSE)(3)
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Startup time VDD is stabilized 3 s
ai14977b
OSC_OU T
OSC_IN fHSE
CL1
RF
STM32F102xx
8 MHz
resonator
Bias
controlled
gain
REXT(1)
CL2
Resonator with
integrated capacitors
Electrical characteristics STM32F102x8, STM32F102xB
42/69 Doc ID 15056 Rev 3
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL
7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 19. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
The parameters given in Ta b l e 2 3 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 8 .
High-speed internal (HSI) RC oscillator
ai14978b
OSC32_OU T
OSC32_IN fLSE
CL1
RF
STM32F102xx
32.768 KHz
resonator
Bias
controlled
gain
CL2
Resonator with
integrated capacitors
Table 23. HSI oscillator characteristics(1)
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency 8 MHz
ACCHSI
Accuracy of the HSI
oscillator
User-trimmed with the RCC_CR
register(2)
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
1(3)
3. Guaranteed by design, not tested in production.
%
Factory-
calibrated(4)
4. Based on characterization, not tested in production.
TA = –40 to 105 °C –2 2.5 %
TA = –10 to 85 °C –1.5 2.2 %
TA = 0 to 70 °C –1.3 2 %
TA = 25 °C –1.1 1.8 %
tsu(HSI)(4) HSI oscillator
startup time 12µs
IDD(HSI)(4) HSI oscillator power
consumption 80 100 µA
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 43/69
low-speed internal (LSI) RC oscillator
Wakeup time from low-power mode
The wakeup times given in Ta bl e 2 5 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●Stop or Standby mode: the clock source is the RC oscillator
●Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Ta b le 8 .
5.3.8 PLL characteristics
The parameters given in Ta b l e 2 6 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 8 .
Table 24. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = 40 to 85 °C unless otherwise specified.
Symbol Parameter Min(2)
2. Based on characterization, not tested in production.
Typ Max Unit
fLSI Frequency 30 40 60 kHz
tsu(LSI)(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time 85 µs
IDD(LSI)(3) LSI oscillator power consumption 0.65 1.2 µA
Table 25. Low-power mode wakeup timings
Symbol Parameter Typ Unit
tWUSLEEP(1)
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
Wakeup from Sleep mode 1.8 µs
tWUSTOP(1)
Wakeup from Stop mode (regulator in run mode) 3.6
µs
Wakeup from Stop mode (regulator in low-power
mode) 5.4
tWUSTDBY(1) Wakeup from Standby mode 50 µs
Table 26. PLL characteristics
Symbol Parameter
Value
Unit
Min(1) Typ Max(1)
fPLL_IN
PLL input clock(2) 18.025MHz
PLL input clock duty cycle 40 60 %
fPLL_OUT PLL multiplier output clock 16 48 MHz
Electrical characteristics STM32F102x8, STM32F102xB
44/69 Doc ID 15056 Rev 3
5.3.9 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 85 °C unless otherwise specified.
Table 28. Flash memory endurance and data retention
5.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
tLOCK PLL lock time 200 µs
Jitter Cycle-to-cycle jitter 300 ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
Table 26. PLL characteristics (continued)
Symbol Parameter
Value
Unit
Min(1) Typ Max(1)
Table 27. Flash memory characteristics
Symbol Parameter Conditions Min(1)
1. Guaranteed by design, not tested in production.
Typ Max(1) Unit
tprog 16-bit programming time TA–40 to +85 °C 40 52.5 70 µs
tERASE Page (1 KB) erase time TA –40 to +85 °C 20 40 ms
tME Mass erase time TA –40 to +85 °C 20 40 ms
IDD Supply current
Read mode
fHCLK = 48 MHz with 2
wait states, VDD = 3.3 V
20 mA
Write / Erase modes
fHCLK = 48 MHz, VDD =
3.3 V
5mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V 50 µA
Vprog Programming voltage 2 3.6 V
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Based on characterization not tested in production.
Typ Max
NEND Endurance 10 kcycles
tRET Data retention TA = 85 °C, 1000 cycles 30 Years
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 45/69
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Ta bl e 2 9 . They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations: the software flowchart must include the management of
runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical Data corruption (control registers, etc.)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 29. EMS characteristics
Symbol Parameter Conditions Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD 3.3 V, TA +25 °C,
fHCLK 48 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS pins
to induce a functional disturbance
VDD3.3 V, TA +25 °C,
fHCLK 48 MHz
conforms to IEC 61000-4-4
4A
Electrical characteristics STM32F102x8, STM32F102xB
46/69 Doc ID 15056 Rev 3
5.3.11 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●A supply overvoltage is applied to each power supply pin
●A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 30. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
SEMI Peak level VDD 3.3 V, TA 25 °C,
0.1 MHz to 30 MHz 7
dBµV30 MHz to 130 MHz 8
130 MHz to 1GHz 13
SAE EMI Level 3.5 -
Table 31. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1)
1. Based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA +25 °C, conforming
to JESD22-A114 2 2000
V
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA +25 °C, conforming
to JESD22-C101 II 500
Table 32. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA +105 °C conforming to JESD78A II level A
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 47/69
5.3.12 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta bl e 3 3 are derived from tests
performed under the conditions summarized in Ta bl e 8 . All I/Os are CMOS and TTL
compliant.
All I/Os are CMOS and TTL compliant (no software configuration required), their
characteristics consider the most strict CMOS-technology or TTL parameters:
●For VIH:
–if V
DD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included
–if V
DD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included
●For VIL:
–if V
DD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included
–if V
DD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included
Table 33. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage
TTL ports
–0.5 0.8
V
VIH
Standard IO input high level
voltage 2V
DD+0.5
IO FT(1) input high level voltage
1. FT = Five-volt tolerant.
25.5V
VIL Input low level voltage CMOS ports –0.5 0.35 VDD V
VIH Input high level voltage 0.65 VDD VDD+0.5
Vhys
Standard IO Schmitt trigger
voltage hysteresis(2)
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested
in production.
200 mV
IO FT Schmitt trigger voltage
hysteresis(2) 5% VDD(3) mV
Ilkg Input leakage current (3)
3. With a minimum of 100 mV.
VSS VIN VDD
Standard I/Os 1µA
VIN = 5 V, I/O FT 3
RPU
Weak pull-up equivalent
resistor(4)
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
VIN VSS 30 40 50 k
RPD
Weak pull-down equivalent
resistor(5)
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
VIN VDD 30 40 50 k
CIO I/O pin capacitance 5 pF
Electrical characteristics STM32F102x8, STM32F102xB
48/69 Doc ID 15056 Rev 3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed VOL).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Ta b le 6 ).
●The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Ta b l e 6 ).
Output voltage levels
Unless otherwise specified, the parameters given in Ta bl e 3 4 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 8 . All I/Os are CMOS and TTL compliant.
Table 34. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time TTL port,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
0.4
V
VOH(2)
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time VDD–0.4
VOL(1) Output low level voltage for an I/O pin
when 8 pins are sunk at the same time CMOS port
IIO = +8 mA
2.7 V < VDD < 3.6 V
0.4
V
VOH(2) Output high level voltage for an I/O pin
when 8 pins are sourced at the same time 2.4
VOL(1) Output low level voltage for an I/O pin
when 8 pins are sunk at the same time IIO = +20 mA(3)
2.7 V < VDD < 3.6 V
3. Based on characterization data, not tested in production.
1.3
V
VOH (2) Output high level voltage for an I/O pin
when 8 pins are sourced at the same time VDD–1.3
VOL(1) Output low level voltage for an I/O pin
when 8 pins are sunk at the same time IIO = +6 mA(3)
2 V < VDD < 2.7 V
0.4
V
VOH(2) Output high level voltage for an I/O pin
when 8 pins are sourced at the same time VDD–0.4
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 49/69
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 20 and
Ta bl e 3 5 , respectively.
Unless otherwise specified, the parameters given in Ta bl e 3 5 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 8 .
Table 35. I/O AC characteristics(1)
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
MODEx
[1:0] bit
value(1)
Symbol Parameter Conditions Max Unit
10
fmax(IO)out Maximum frequency(2)
2. The maximum frequency is defined in Figure 20.
CL = 50 pF, VDD = 2 V to 3.6 V 2 MHz
tf(IO)out
Output high to low level fall
time CL = 50 pF, VDD = 2 V to 3.6 V
125(3)
3. Guaranteed by design, not tested in production.
ns
tr(IO)out
Output low to high level rise
time 125(3)
01
fmax(IO)out Maximum frequency(2) CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz
tf(IO)out
Output high to low level fall
time CL= 50 pF, VDD = 2 V to 3.6 V
25(3)
ns
tr(IO)out
Output low to high level rise
time 25(3)
11
Fmax(IO)out Maximum Frequency(2)
CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz
CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz
tf(IO)out
Output high to low level fall
time
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
ns
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
tr(IO)out
Output low to high level rise
time
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
-t
EXTIpw
Pulse width of external
signals detected by the
EXTI controller
10 ns
Electrical characteristics STM32F102x8, STM32F102xB
50/69 Doc ID 15056 Rev 3
Figure 20. I/O AC characteristics definition
5.3.13 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Ta b le 3 3 ).
Unless otherwise specified, the parameters given in Ta bl e 3 6 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 8 .
Figure 21. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 36. Otherwise the reset will not be taken into account by the device.
ai14131
10%
90%
50%
tr(IO)out
OUTPUT
EXTERNAL
ON 50pF
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50pF
T
tr(IO)out
Table 36. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage –0.5 0.8 V
VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis 200 mV
RPU Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
VIN VSS 30 40 50 k
VF(NRST)(1) NRST Input filtered pulse 100 ns
VNF(NRST)(1) NRST Input not filtered pulse 300 ns
ai14132c
STM32F10xxx
RPU
NRST
(2)
VDD
Filter
Internal Reset
0.1 µF
External
reset circuit
(1)
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 51/69
5.3.14 TIM timer characteristics
The parameters given in Ta b l e 3 7 are guaranteed by design.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
5.3.15 Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Ta bl e 3 8 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Ta b l e 8 .
The STM32F102xx medium-density USB access line I2C interface meets the requirements
of the standard I2C communication protocol with the following restrictions: the I/O pins SDA
and SCL are mapped to are not “true” open-drain. When configured as open-drain, the
PMOS connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Ta b l e 3 8 . Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 37. TIMx(1) characteristics
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
1tTIMxCLK
fTIMxCLK = 48 MHz 20.84 ns
fEXT Timer external clock
frequency on CH1 to CH4
0
fTIMxCLK/2 MHz
fTIMxCLK = 48 MHz 024MHz
ResTIM Timer resolution 16 bit
tCOUNTER
16-bit counter clock period
when internal clock is
selected
1 65536 tTIMxCLK
fTIMxCLK = 48 MHz 0.0208 1365 µs
tMAX_COUNT Maximum possible count
65536 × 65536 tTIMxCLK
fTIMxCLK = 48 MHz 89.48 s
Electrical characteristics STM32F102x8, STM32F102xB
52/69 Doc ID 15056 Rev 3
Table 38. I2C characteristics
Symbol Parameter
Standard mode I2C(1)
1. Values guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
ns
th(SDA) SDA data hold time 0(3)
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
0(4)
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time 1000 20+0.1Cb300
tf(SDA)
tf(SCL)
SDA and SCL fall time 300 300
th(STA) Start condition hold time 4.0 0.6
µs
tsu(STA)
Repeated Start condition setup
time 4.7 0.6
tsu(STO) Stop condition setup time 4.0 0.6 µs
tw(STO:STA)
Stop to Start condition time (bus
free) 4.7 1.3 µs
CbCapacitive load for each bus line 400 400 pF
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 53/69
Figure 22. I2C bus AC waveforms and measurement circuit(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL
(kHz)
I2C_CCR value
RP = 4.7 k
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
ai14979
START
SD A
100 Ω
4.7kΩ
I²C bus
4.7kΩ
100 Ω
VDD
VDD
STM32F102xx
SDA
SCL
tf(SDA) tr(SDA)
SCL
th(STA)
tw(SCKH)
tw(SCKL)
tsu(SDA)
tr(SCK) tf(SCK)
th(SDA)
S TART REPEATED
START
tsu(STA)
tsu(STO)
S TOP tsu(STA:STO)
Electrical characteristics STM32F102x8, STM32F102xB
54/69 Doc ID 15056 Rev 3
SPI interface characteristics
Unless otherwise specified, the parameters given in Ta bl e 4 0 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Ta b l e 8 .
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI characteristics(1)
1. Remapped SPI1 characteristics to be determined.
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency Master mode 18 MHz
Slave mode 18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time Capacitive load: C = 30 pF 8 ns
DuCy(SCK) SPI slave input clock
duty cycle Slave mode 30 70 %
tsu(NSS)(2)
2. Based on characterization, not tested in production.
NSS setup time Slave mode 4tPCLK
ns
th(NSS)(2) NSS hold time Slave mode 2tPCLK
tw(SCKH)(2)
tw(SCKL)(2) SCK high and low time Master mode, fPCLK = 36 MHz,
presc = 4 50 60
tsu(MI) (2)
tsu(SI)(2) Data input setup time Master mode 5
Slave mode 5
th(MI) (2)
Data input hold time Master mode 5
th(SI)(2) Slave mode 4
ta(SO)(2)(3)
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK
tdis(SO)(2)(4)
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode 2 10
tv(SO) (2)(1) Data output valid time Slave mode (after enable edge) 25
tv(MO)(2)(1) Data output valid time Master mode (after enable
edge) 5
th(SO)(2)
Data output hold time
Slave mode (after enable edge) 15
th(MO)(2) Master mode (after enable
edge) 2
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 55/69
Figure 23. SPI timing diagram - slave mode and CPHA=0
Figure 24. SPI timing diagram - slave mode and CPHA=1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14134c
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI) th(SI)
NSS input
Electrical characteristics STM32F102x8, STM32F102xB
56/69 Doc ID 15056 Rev 3
Figure 25. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 41. USB startup time
Symbol Parameter Max Unit
tSTARTUP USB transceiver startup time 1 µs
ai14136
SCK Input
CPHA= 0
MOSI
OUTUT
MISO
INP UT
CPHA= 0
MS BIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 57/69
Figure 26. USB timings: definition of data signal rise and fall time
5.3.16 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Ta bl e 4 4 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Ta b l e 8 .
Note: It is recommended to perform a calibration after each power-up.
Table 42. USB DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input
levels
VDD USB operating voltage(2)
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range.
3.0(3)
3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3.6 V
VDI(4)
4. Guaranteed by design, not tested in production.
Differential input sensitivity I(USBDP, USBDM) 0.2
VVCM(4) Differential common mode range Includes VDI range 0.8 2.5
VSE(4) Single ended receiver threshold 1.3 2.0
Output
levels
VOL Static output level low RL of 1.5 k to 3.6
V(5)
5. RL is the load connected on the USB drivers
0.3 V
VOH Static output level high RL of 15 k to VSS(5) 2.8 3.6
Table 43. USB: Full speed electrical characteristics of the driver(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
ai14137
tf
Differen tial
Data L ines
VSS
V
CR S
tr
Crossover
points
Electrical characteristics STM32F102x8, STM32F102xB
58/69 Doc ID 15056 Rev 3
Equation 1: RAIN max formula:
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 44. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply 2.4 3.6 V
fADC ADC clock frequency 0.6 12 MHz
fS(1)
1. Guaranteed by design, not tested in production.
Sampling rate 0.05 1 MHz
fTRIG(1) External trigger frequency fADC = 12 MHz 823 kHz
17 1/fADC
VAIN Conversion voltage range(2)
2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA,
0 (VSSA or
VREF- tied to
ground)
VREF+ V
RAIN(1) External input impedance
See Equation 1
and Ta bl e 4 5
for details
50 k
RADC(1) Sampling switch resistance 1 k
CADC(1) Internal sample and hold
capacitor 8pF
tCAL(1) Calibration time fADC = 12 MHz 5.9 µs
83 1/fADC
tlat(1) Injection trigger conversion
latency
fADC = 12 MHz 0.214 µs
3(3)
3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 44.
1/fADC
tlatr(1) Regular trigger conversion
latency
fADC = 12 MHz 0.143 µs
2(3) 1/fADC
tS(1) Sampling time fADC = 12 MHz 0.107 17.1 µs
1.5 239.5 1/fADC
tSTAB(1) Power-up time 0 0 1 µs
tCONV(1) Total conversion time
(including sampling time)
fADC = 12 MHz 1.2 18 µs
14 to 252 (tS for sampling +12.5
for successive approximation) 1/fADC
RAIN
TS
fADC CADC 2N2+
ln
--------------------------------------------------------------RADC
–
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 59/69
Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the
standard (non-robust) analog pins should be avoided as this significantly reduces the
accuracy of the conversion being performed on another analog pin. It is recommended to
add a Schottky diode (pin to ground) to standard analog pins that may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and
IINJ(PIN) in
Section 5.3.12 does not affect the ADC accuracy.
Table 45. RAIN max for fADC = 12 MHz(1)
1. Data guaranteed by design, not tested in production.
Ts (cycles) tS (µs) RAIN max (k)
1.5 0.13 0.4
7.5 0.63 5.9
13.5 1.13 11.4
28.5 2.38 25.2
41.5 3.46 37.2
55.5 4.63 50
71.5 5.96 NA
239.5 19.96 NA
Table 46. ADC accuracy - limited test conditions(1)
1. ADC DC accuracy values are measured after internal calibration.
Symbol Parameter Test conditions Typ Max(2)
2. Based on characterization, not tested in production.
Unit
ET Total unadjusted error fPCLK2 = 48 MHz,
fADC = 12 MHz, RAIN < 10 k,
VDDA = 3 V to 3.6 V
TA = 25 °C
Measurements made after
ADC calibration
±1.3 ±2
LSB
EO Offset error ±1 ±1.5
EG Gain error ±0.5 ±1.5
ED Differential linearity error ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
Table 47. ADC accuracy(1) (2)
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
Symbol Parameter Test conditions Typ Max(3)
3. Based on characterization, not tested in production.
Unit
ET Total unadjusted error
fPCLK2 = 48 MHz,
fADC = 12 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
Electrical characteristics STM32F102x8, STM32F102xB
60/69 Doc ID 15056 Rev 3
Figure 27. ADC accuracy characteristics
Figure 28. Typical connection diagram using the ADC
1. Refer to Table 44 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
EO
EG
1LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total u nadjusted er ror: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset error: deviation between the first actual
transition and the first ideal one.
EG=Gain er ror: deviation between the last ideal
transition and the last actual one.
ED=Differential linearity error: maximum deviation
between actual steps and the ideal one.
EL=Integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1234567 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai15497
VDDA
4096
[1LSBIDEAL =
ai14974b
STM32F102
VDD
AINx
IL±1 µA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1) 12-bit
converter
CADC(1)
Sample and hold ADC
converter
STM32F102x8, STM32F102xB Electrical characteristics
Doc ID 15056 Rev 3 61/69
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 29. The 10 nF capacitors
should be ceramic (good quality). They should be placed as close as possible to the chip.
Figure 29. Power supply and reference decoupling
5.3.17 Temperature sensor characteristics
VDDA
STM32F102xx
1 µF // 10 nF
VSSA
ai14980b
Table 48. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by characterization, not tested in production.
VSENSE linearity with temperature 1.5 °C
Avg_Slope(1) Average slope 4.35 mV/°C
V25(1) Voltage at 25°C 1.42 V
tSTART(2)
2. Data guaranteed by design, not tested in production.
Startup time 4 10 µs
TS_temp(3)(2)
3. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature 17.1 µs
Package characteristics STM32F102x8, STM32F102xB
62/69 Doc ID 15056 Rev 3
6 Package characteristics
6.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
STM32F102x8, STM32F102xB Package characteristics
Doc ID 15056 Rev 3 63/69
Figure 30. LQFP64 – 10 x 10 mm, 64 pin low-profile quad
flat package outline(1) Figure 31. Recommended
footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
A
A2
A1
c
L1
L
EE1
D
D1
e
b
ai14398b
48
3249
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909
Table 49. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.60 0.0630
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 12.00 0.4724
D1 10.00 0.3937
E 12.00 0.4724
E1 10.00 0.3937
e 0.50 0.0197
0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
Number of pins
N64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F102x8, STM32F102xB
64/69 Doc ID 15056 Rev 3
Figure 32. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat
package outline(1) Figure 33. Recommended
footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D
D1
D3 A1
L1
L
k
c
b
ccc C
A1
A2A
C
Seating plane
0.25 mm
Gage plane
E3 E1 E
12
13
24
25
48
1
36
37
Pin 1
identification
5B_ME
9.70 5.80 7.30
12
24
0.20
7.30
1
37
36
1.20
5.80
9.70
0.30
25
1.20
0.50
ai14911b
1348
Table 50. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0°3.5°7° 0°3.5°7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F102x8, STM32F102xB Package characteristics
Doc ID 15056 Rev 3 65/69
6.2 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 8: General operating conditions on page 27.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × JA)
Where:
●TA max is the maximum ambient temperature in C,
●JA is the package junction-to-ambient thermal resistance, in C/W,
●PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
6.3 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 51. Package thermal characteristics
Symbol Parameter Value Unit
JA
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch 55
°C/W
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch 45
Package characteristics STM32F102x8, STM32F102xB
66/69 Doc ID 15056 Rev 3
6.3.1 Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 52: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F102xx junction temperature range.
Example: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Ta bl e 5 1 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the junction temperature range of the STM32F102xx (–40 < TJ < 105 °C).
Figure 34. LQFP64 PD max vs. TA
0
100
200
300
400
500
600
700
65 75 85 95 105 115
TA (°C)
PD (mW)
Suffix 6
STM32F102x8, STM32F102xB Ordering information scheme
Doc ID 15056 Rev 3 67/69
7 Ordering information scheme
Table 52. Ordering information scheme
Example: STM32 F 102 C 8 T 6 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
102 = USB access line, USB 2.0 full-speed interface
Pin count
C = 48 pins
R = 64 pins
Flash memory size
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Options
xxx = programmed parts
TR = tape and real
Revision history STM32F102x8, STM32F102xB
68/69 Doc ID 15056 Rev 3
8 Revision history
Table 53. Document revision history
Date Revision Changes
23-Sep-2008 1 Initial release.
23-Apr-2009 2
I/O information clarified on page 1. Figure 1: STM32F102xx medium-
density USB access line block diagram and Figure 5: Memory map
modified.
In Table 4: Medium-density STM32F102xx pin definitions: PB4, PB13,
PB14, PB15, PB3/TRACESWO moved from Default column to Remap
column.
PD value added for LQFP64 package in Table 8: General operating
conditions.
Note modified in Table 12: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 14: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 13, Figure 14 and Figure 15 show typical curves.
Figure 27: ADC accuracy characteristics modified.
Figure 29: Power supply and reference decoupling modified.
Table 19: High-speed external user clock characteristics and Table 20:
Low-speed external user clock characteristics modified.
ACCHSI max values modified in Table 23: HSI oscillator characteristics.
Small text changes.
22-Sep-2009 3
Note 5 updated in Table 4: Medium-density STM32F102xx pin definitions.
VRERINT and TCoeff added to Table 11: Embedded internal reference
voltage. Typical IDD_VBAT value added in Table 15: Typical and maximum
current consumptions in Stop and Standby modes. Figure 12: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 19: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator
characteristics and Table 22: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables. Table 23: HSI
oscillator characteristics modified. Conditions removed from Table 25:
Low-power mode wakeup timings.
Note 1 modified below Figure 18: Typical application with an 8 MHz
crystal.
Figure 21: Recommended NRST pin protection modified.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 44.
Jitter added to Table 26: PLL characteristics.
Table 40: SPI characteristics modified.
CADC and RAIN parameters modified in Table 44: ADC characteristics.
RAIN max values modified in Table 45: RAIN max for fADC = 12 MHz.
Small text changes.
STM32F102x8, STM32F102xB
Doc ID 15056 Rev 3 69/69
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