STM32F102x8 STM32F102xB Medium-density USB access line, ARM-based 32-bit MCU with 64/128KB Flash, USB FS interface, 6 timers, ADC & 8 communication interfaces Features Core: ARM 32-bit CortexTM-M3 CPU - 48 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 WS memory access - Single-cycle multiplication and hardware division Memories - 64 or 128 Kbytes of Flash memory - 10 or 16 Kbytes of SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR and programmable voltage detector (PVD) - 4-to-16 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC - PLL for CPU clock - 32 kHz oscillator for RTC with calibration LQFP64 10 x 10 mm LQFP48 7 x 7 mm Up to 6 timers - Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter - 2 watchdog timers (Independent and Window) - SysTick timer: 24-bit downcounter Up to 8 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 SPIs (12 Mbit/s) - USB 2.0 full speed interface Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers CRC calculation unit, 96-bit unique ID ECOPACK(R) packages Debug mode - Serial wire debug (SWD) and JTAG interfaces Table 1. Reference DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 1 x 12-bit, 1.2 s A/D converter (up to 16 channels) - Conversion range: 0 to 3.6 V - Temperature sensor Up to 51 fast I/O ports - 37/51 IOs all mappable on 16 external interrupt vectors and almost all 5 V-tolerant September 2009 Device summary Part number STM32F102x8 STM32F102C8, STM32F102R8 STM32F102xB STM32F102CB, STM32F102RB Doc ID 15056 Rev 3 1/69 www.st.com 1 Contents STM32F102x8, STM32F102xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 2/69 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 46 5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB 6 Contents 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.1 Evaluating the maximum junction temperature for an application . . . . . 66 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15056 Rev 3 3/69 List of tables STM32F102x8, STM32F102xB List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 4/69 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F102x8 and STM32F102xB medium-density USB access line features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM32F102xx USB access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Medium-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 32 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 32 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 36 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. List of tables RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 63 LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 64 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15056 Rev 3 5/69 List of figures STM32F102x8, STM32F102xB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. 6/69 STM32F102xx medium-density USB access line block diagram . . . . . . . . . . . . . . . . . . . . 10 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 18 STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 18 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 31 Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 31 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 63 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 64 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F102x4 and STM32F102x6 medium-density USB access line microcontrollers. For more details on the whole STMicroelectronics STM32F102xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F102xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. Doc ID 15056 Rev 3 7/69 Description 2 STM32F102x8, STM32F102xB Description The STM32F102xx medium-density USB access line incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory of 64 or 128 Kbytes and SRAM of 10 or 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, one USB and three USARTs), one 12-bit ADC and three general-purpose 16-bit timers. The STM32F102xx family operates in the -40 to +85 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of lowpower applications. The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 x 7 mm and LQFP64 10 x 10 mm packages. The STM32F102xx medium-density USB access line microcontrollers are suitable for a wide range of applications: Application control and user interface Medical and handheld equipment PC peripherals, gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. 8/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB 2.1 Description Device overview Table 2. STM32F102x8 and STM32F102xB medium-density USB access line features and peripheral counts Peripheral STM32F102Cx STM32F102Rx Flash - Kbytes 64 128 64 128 SRAM - Kbytes 10 16 10 16 General-purpose 3 3 3 3 SPI 2 2 2 2 I2C 2 2 2 2 USART 3 3 3 3 USB 1 1 1 1 Timers Communication interfaces 12-bit synchronized ADC number of channels 1 10 channels 1 16 channels 37 51 GPIOs CPU frequency 48 MHz Operating voltage Operating temperatures Packages 2.0 to 3.6 V Ambient temperature: -40 to +85 C (see Table 8) Junction temperature: -40 to +105 C (see Table 8) LQFP48 Doc ID 15056 Rev 3 LQFP64 9/69 Description STM32F102x8, STM32F102xB STM32F102xx medium-density USB access line block diagram TPIU SW/JTAG Trace/trig SWD Trace Controller ont pbus Ibus Cortex M3 CPU Fmax: 48 MHz NVIC Dbus NVIC Syst em AHB: Fmax =48 MHz 7 channels SUPPLY SUPERVISION NRST VDDA VSSA POR / PDR Rst PVD Int @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz PB[ 15:0] GPIOB PC[15:0] GPIOC PD[2:0] GPIOD MOSI,MISO, SCK,NSS as AF OSC_IN OSC_OUT RC 8 MHz IWDG RC 40 kHz Stand by in terface @VDDA VBAT @VBAT RTC AWU AHB2 APB 1 Backup reg OSC32_IN OSC32_OUT TAMPER-RTC Backup interface APB2 : Fmax = 48 MHz GPIOA SPI1 USART1 @VDDA 16 AF PCLK1 PCLK 2 HCLK FCLK VDD = 2 to 3.6V VSS @VDD 64 bit EXTI WAKEUP PA[ 15:1] RX,TX, CTS, RTS, Smart Card as AF Flash 128 KB XTAL 32 kHz AHB2 APB2 51AF VOLT. REG. 3.3V TO 1.8V SRAM 16 KB GP DMA @VDDA POWER 12bit ADC1 IF APB 1: Fmax = 24 MHz JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF Flash obl Inte rface TRACECLK TRACED[0:3] as AS BusM atrix Figure 1. TIM2 4 Chann els TIM3 4 Chann els TIM4 4 Channels USART2 USART3 x16bit)SPI2 RX,TX, CTS, RTS, CK, Smartcard as AF MOSI,MISO,SCK,NSS as AF I2C1 SCL,SDA,SMBA as AF I2C2 SCL,SDA, SMBA as AF USB 2.0 FS Temp sen so r RX,TX, CTS, RTS, CK, Smartcard as AF USBDP, USBDM as AF WWDG ai14868f 1. AF = alternate function on I/O port pin. 2. TA = -40 C to +85 C (junction temperature up to 105 C). 10/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Figure 2. Description Clock tree 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz 48 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 48 MHz /1, 2..512 max PLLCLK Clock Enable (3 bits) APB1 Prescaler /1, 2, 4, 8, 16 HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock 24 MHz max PCLK1 to APB1 peripherals Peripheral Clock HSE Enable (13 bits) to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock CSS Enable (3 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz 48 MHz max HSE OSC /2 ADC Prescaler /2, 4, 6, 8 /128 OSC32_IN OSC32_OUT Peripheral Clock Enable (11 bits) PCLK2 to APB2 peripherals LSE OSC 32.768 kHz to ADC ADCCLK to RTC LSE RTCCLK RTCSEL[1:0] LSI RC 40 kHz to Independent Watchdog (IWDG) LSI IWDGCLK Main Clock Output /2 MCO PLLCLK HSI Legend: HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal HSE SYSCLK MCO ai14994 1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at 48 MHz. 2. To have an ADC conversion time of 1.2 s, APB2 must be at 12 MHz, 24 MHz or 48 MHz. Doc ID 15056 Rev 3 11/69 Description 2.2 STM32F102x8, STM32F102xB Full compatibility throughout the family The STM32F102xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred to as medium-density devices. Low-density devices are an extension of the STM32F102x8/B devices, they are specified in the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM capacities, a timer and a few communication interfaces less. The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx access line and STM32F103xx performance line devices. Table 3. STM32F102xx USB access line family Low-density STM32F102xx devices Pinout 64 48 Medium-density STM32F102xx devices 16 KB Flash 32 KB Flash(1) 64 KB Flash 128 KB Flash 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 2 x USARTs, 2 x 16-bit timers 1 x SPI, 1 x I2C, 1 x ADC, 1 x USB 3 x USARTs, 3 x 16-bit timers 2 x SPIs, 2 x I2Cs, 1 x ADC, 1 x USB 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F102x8/B medium-density devices. 2.3 Overview ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F102xx medium-density USB access line having an embedded ARM core, is therefore compatible with all ARM tools and software. Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data. 12/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Description CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. Embedded SRAM 10 or 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F102xx medium-density USB access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 48 MHz. See Figure 2 for details on the clock tree. Doc ID 15056 Rev 3 13/69 Description STM32F102x8, STM32F102xB Boot modes At startup, boot pins are used to select one of five boot options: Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. Power supply schemes VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 8: Power supply scheme. Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 14/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Description Low-power modes The STM32F102xx medium-density USB access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC. RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare Doc ID 15056 Rev 3 15/69 Description STM32F102x8, STM32F102xB register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source General-purpose timers (TIMx) There are 3 synchronizable general-purpose timers embedded in the STM32F102xx medium-density USB access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one-pulse mode output. This gives up to 12 input captures / output compares / PWMs on the LQFP48 and LQFP64 packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. IC bus Two IC bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 16/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Description Universal synchronous/asynchronous receiver transmitter (USART) The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) Two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. Universal serial bus (USB) The STM32F102xx medium-density USB access line embeds a USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. ADC (analog to digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. Temperature sensor The temperature sensor has to generate a a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Doc ID 15056 Rev 3 17/69 Pinouts and pin description 3 STM32F102x8, STM32F102xB Pinouts and pin description STM32F102xx medium-density USB access line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 3. 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 STM32F102xx medium-density USB access line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 4. ai14378d 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 ai14387c 18/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Medium-density STM32F102xx pin definitions LQFP64 Pin name 1 1 VBAT 2 3 Type(1) LQFP48 Pins (5) 2 PC13-TAMPER-RTC 3 PC14-OSC32_IN(5) PC15-OSC32_OUT (5) I / O level(2) Table 4. Pinouts and pin description Main function(3) (after reset) Alternate functions(3) (4) Default S VBAT I/O PC13(6) I/O (6) OSC32_IN (6) OSC32_OUT PC14 I/O PC15 TAMPER-RTC 4 4 5 5 PD0 I/O FT OSC_IN(7) 6 6 PD1 I/O FT OSC_OUT(7) 7 7 NRST I/O NRST - 8 PC0 I/O PC0 ADC_IN10 - 9 PC1 I/O PC1 ADC_IN11 - 10 PC2 I/O PC2 ADC_IN12 - 11 PC3 I/O PC3 ADC_IN13 8 12 VSSA S VSSA 9 13 VDDA S VDDA 10 14 PA0-WKUP I/O PA0 WKUP/USART2_CTS/ ADC_IN0/ TIM2_CH1_ETR(8) 11 15 PA1 I/O PA1 USART2_RTS/ ADC_IN1/TIM2_CH2(8) 12 16 PA2 I/O PA2 USART2_TX/ ADC_IN2/TIM2_CH3(8) 13 17 PA3 I/O PA3 USART2_RX/ ADC_IN3/TIM2_CH4(8) - 18 VSS_4 S VSS_4 - 19 VDD_4 S VDD_4 14 20 PA4 I/O PA4 SPI1_NSS(8)/ADC_IN4 USART2_CK/ 15 21 PA5 I/O PA5 SPI1_SCK(8)/ADC_IN5 16 22 PA6 I/O PA6 SPI1_MISO(8)/ADC_IN6/ TIM3_CH1(8) 17 23 PA7 I/O PA7 SPI1_MOSI(8)/ADC_IN7/ TIM3_CH2(8) - 24 PC4 I/O PC4 ADC_IN14 - 25 PC5 I/O PC5 ADC_IN15 18 26 PB0 I/O PB0 ADC_IN8/TIM3_CH3(8) 19 27 PB1 I/O PB1 ADC_IN9/TIM3_CH4(8) 20 28 PB2 I/O FT Remap PB2/BOOT1 Doc ID 15056 Rev 3 19/69 Pinouts and pin description LQFP48 LQFP64 Pins Pin name 21 29 PB10 I / O level(2) Medium-density STM32F102xx pin definitions (continued) Type(1) Table 4. STM32F102x8, STM32F102xB Main function(3) (after reset) I/O FT PB10 Default Remap I2C2_SCL/ USART3_TX(8) TIM2_CH3 PB11 USART3_RX(8) TIM2_CH4 22 30 PB11 I/O 23 31 VSS_1 S VSS_1 24 32 VDD_1 S VDD_1 25 33 PB12 I/O FT PB12 SPI2_NSS / I2C2_SMBA/ USART3_CK(8) 26 34 PB13 I/O FT PB13 SPI2_SCK(8)/ USART3_CTS 27 35 PB14 I/O FT PB14 SPI2_MISO/ USART3_RTS 28 36 PB15 I/O FT PB15 SPI2_MOSI - 37 PC6 I/O FT PC6 TIM3_CH1 - 38 PC7 I/O FT PC7 TIM3_CH2 - 39 PC8 I/O FT PC8 TIM3_CH3 - 40 PC9 I/O FT PC9 TIM3_CH4 29 41 PA8 I/O FT PA8 USART1_CK/MCO 30 42 PA9 I/O FT PA9 USART1_TX(8) 31 43 PA10 I/O FT PA10 USART1_RX(8) 32 44 PA11 I/O FT PA11 USART1_CTS/USBDM 33 45 PA12 I/O FT PA12 USART1_RTS/USBDP 34 46 PA13 I/O FT JTMS-SWDIO 35 47 VSS_2 S VSS_2 36 48 VDD_2 S VDD_2 37 49 PA14 I/O FT JTCK/SWCLK PA14 38 50 PA15 I/O FT JTDI TIM2_CH1_ETR/ PA15 /SPI1_NSS - 51 PC10 I/O FT PC10 USART3_TX - 52 PC11 I/O FT PC11 USART3_RX - 53 PC12 I/O FT PC12 USART3_CK - 54 PD2 I/O FT PD2 39 55 PB3 I/O FT JTDO TIM2_CH2/ PB3/ TRACESWO/ SPI1_SCK 40 56 PB4 I/O FT JNTRST TIM3_CH1 / PB4 SPI1_MISO 20/69 FT Alternate functions(3) (4) Doc ID 15056 Rev 3 I2C2_SDA/ PA13 TIM3_ETR STM32F102x8, STM32F102xB LQFP48 LQFP64 Pins Pin name 41 57 PB5 I/O 42 58 PB6 I/O I / O level(2) Medium-density STM32F102xx pin definitions (continued) Type(1) Table 4. Pinouts and pin description FT FT Alternate functions(3) (4) Main function(3) (after reset) Default Remap PB5 I2C1_SMBA TIM3_CH2 / SPI1_MOSI PB6 I2C1_SCL(8)/ TIM4_CH1 USART1_TX PB7 I2C1_SDA(8) USART1_RX 43 59 PB7 I/O 44 60 BOOT0 I 45 61 PB8 I/O FT PB8 TIM4_CH3 I2C1_SCL 46 62 PB9 I/O FT PB9 TIM4_CH4 I2C1_SDA 47 63 VSS_3 S VSS_3 48 64 VDD_3 S VDD_3 / TIM4_CH2 BOOT0 1. I = input, O = output, S = supply. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 9Table 3 on page 12. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the STMicroelectronics website: www.st.com. 7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. Doc ID 15056 Rev 3 21/69 Memory mapping 4 STM32F102x8, STM32F102xB Memory mapping The memory map is shown in Figure 5. Figure 5. Memory map APB memory space 0xFFFF FFFF 0xE010 0000 0xE000 0000 0x6000 0000 0x4002 3400 0xFFFF FFFF 0x4002 3000 0xE010 0000 0xE000 0000 Cortex-M3 internal peripherals 6 3K 1K 0x4002 1400 reserved 3K 0x4002 1000 RCC 1K 0x4002 0400 reserved 3K 0x4002 0000 DMA 1K 0x4001 3400 0x4001 3000 0x4001 2C00 0x4001 2800 0x4001 2400 0xA000 0000 1K reserved 0x4001 3800 5 4K CRC Flash interface 0x4001 3C00 0xC000 0000 reserved 0x4002 2000 0x4002 2400 7 reserved Cortex-M3 internal peripherals reserved reserved 1K USART1 1K reserved 1K SPI1 1K reserved 1K reserved 1K ADC1 1K reserved 2K 0x4001 1C00 4 0x1FFF FFFF 0x1FFF F80F 0x8000 0000 Option Bytes 0x1FFF F800 3 reserved 1K 0x4001 1400 Port D 1K 0x4001 1000 Port C 1K 0x4001 0C00 Port B 1K 0x4001 0800 Port A 1K 0x4001 0400 EXTI 1K 0x4001 0000 AFIO 1K reserved 35K 0x4001 1800 reserved System memory 0x1FFF F000 0x6000 0000 0x4000 7400 0x4000 7000 2 0x4000 0000 0x4000 6C00 reserved Peripherals 0x4000 6800 0x4000 6400 0x4000 6000 0x2000 3FFF 0x2000 0000 SRAM 0x0801FFFF 0 Flash memory 0x0800 0000 Reserved Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins 1K reserved 1K reserved 1K 512 byte USB SRAM 1K USB registers 1K I2C2 1K 0x4000 5400 I2C1 1K 0x4000 4C00 reserved 2K 0x4000 4800 USART3 1K 0x4000 4400 USART2 1K reserved 2K SPI2 1K 0x4000 3400 reserved 1K 0x4000 3000 IWDG 1K 0x4000 2C00 WWDG 1K 0x4000 2800 RTC 1K reserved 7K 0x4000 0800 TIM4 1K 0x4000 0400 TIM3 1K 0x4000 0000 TIM2 1K 0x4000 3C00 0x0000 0000 1K BKP 0x4000 5800 0x4000 5C00 1 PWR 0x4000 3800 0x4000 0C00 ai14971c 22/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Doc ID 15056 Rev 3 23/69 Electrical characteristics Figure 6. STM32F102x8, STM32F102xB Pin loading conditions Figure 7. Pin input voltage STM32F102 pin STM32F102 pin C = 50 pF VIN ai14973 ai14972 5.1.6 Power supply scheme Figure 8. Power supply scheme VBAT GP I/Os IN VDD VDD VDD 1/2/3/4 Level shifter OUT 3 x 100 nF + 1 x 4.7 F Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) Po wer swi tch 1.8-3.6 V IO Logic Kernel logic (CPU, Digital & Memories) Regulator VSS 1/2/3/4 VDDA VREF+ 10 nF + 1 F ADC VREF- Analog: RCs, PLL, ... VSSA ai14882c Caution: 24/69 In Figure 8, the 4.7 F capacitor must be connected to VDD3. Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB 5.1.7 Electrical characteristics Current consumption measurement Figure 9. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Symbol VDD VSS VIN |VDDx| |VSSX VSS| VESD(HBM) Voltage characteristics Ratings Min Max External main supply voltage (including VDDA and VDD)(1) -0.3 4.0 Input voltage on five volt tolerant pin(2) VSS 0.3 +5.5 Input voltage on any other pin(2) VSS 0.3 VDD+0.3 Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN<VSS. Doc ID 15056 Rev 3 25/69 Electrical characteristics Table 6. STM32F102x8, STM32F102xB Current characteristics Symbol Ratings Max. Total current into VDD/VDDA power lines (source)(1) IVDD Total current out of VSS ground lines (sink) IVSS 150 (1) 150 Output current sunk by any I/O and control pin IIO IINJ(PIN) (2)(3) IINJ(PIN) (2) 25 Output current source by any I/Os and control pin 25 Injected current on NRST pin 5 Injected current on High-speed external OSC_IN and Lowspeed external OSC_IN pins 5 Injected current on any other pin(4) 5 Total injected current (sum of all I/O and control Unit pins)(4) mA 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 7. Thermal characteristics Symbol TSTG TJ 26/69 Ratings Storage temperature range Maximum junction temperature Doc ID 15056 Rev 3 Value Unit -65 to +150 C 150 C STM32F102x8, STM32F102xB Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 8. General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 48 fPCLK1 Internal APB1 clock frequency 0 24 fPCLK2 Internal APB2 clock frequency 0 48 VDD Standard operating voltage 2 3.6 2 3.6 VDDA(1) VBAT Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Conditions Must be the same potential as VDD(2) Backup operating voltage PD Power dissipation at TA = 85 C(3) TA Ambient temperature MHz V V 2.4 3.6 1.8 3.6 LQFP48 363 LQFP64 444 V mW Maximum power dissipation (4) Low power dissipation TJ Unit Junction temperature range -40 85 C -40 105 C -40 105 C 1. When the ADC is used, refer to Table 44: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 65). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 65). 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 9. Symbol tVDD Operating conditions at power-up / power-down Parameter Conditions Min Max VDD rise time rate 0 VDD fall time rate 20 Doc ID 15056 Rev 3 Unit s/V 27/69 Electrical characteristics 5.3.3 STM32F102x8, STM32F102xB Embedded reset and power control block characteristics The parameters given in Table 10 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. . Table 10. Symbol VPVD Embedded reset and power control block characteristics Parameter Conditions Programmable voltage detector level selection VPVDhyst(2) PVD hysteresis VPOR/PDR Power on/power down reset threshold VPDRhyst PDR hysteresis tRSTTEMPO(2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V 100 mV Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V 40 Reset temporization 1.5 2.5 mV 4.5 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. 5.3.4 Embedded reference voltage The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. 28/69 Doc ID 15056 Rev 3 ms STM32F102x8, STM32F102xB Table 11. Symbol VREFINT Electrical characteristics Embedded internal reference voltage Parameter Internal reference voltage TS_vrefint(1) ADC sampling time when reading the internal reference voltage VRERINT(2) Internal reference voltage spread over the temperature range TCoeff(2) Conditions Min Typ Max Unit -40 C < TA < +85 C 1.16 1.20 1.24 V 5.1 17.1(2) s 10 mV 100 ppm/ C VDD = 3 V 10 mV Temperature coefficient 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 9: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz) Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Doc ID 15056 Rev 3 29/69 Electrical characteristics Table 12. STM32F102x8, STM32F102xB Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 C External clock (2), all peripherals enabled IDD Supply current in Run mode 48 MHz 36.1 36 MHz 28.6 24 MHz 19.9 16 MHz 14.7 8 MHz 8.6 48 MHz 24.4 36 MHz 19.8 24 MHz 13.9 16 MHz 10.7 8 MHz 6.8 mA External clock (2), all peripherals Disabled 1. Based on characterization results, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 13. Maximum current consumption in Run mode, code with data processing running from RAM Max Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode fHCLK 48 MHz 31.5 36 MHz 24 24 MHz 17.5 16 MHz 12.5 8 MHz 7.5 48 MHz 20.5 36 MHz 16 24 MHz 11.5 16 MHz 8.5 8 MHz 5.5 Unit mA External clock(2) all peripherals disabled 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 30/69 TA = 85 C(1) Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals enabled 30 Consumption (mA) 25 20 48 MHz 36 MHz 15 16 MHz 8 MHz 10 5 0 -40 0 25 70 85 Temperature (C) Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals disabled 20 18 Consumption (mA) 16 14 48 MHz 12 36 MHz 10 16 MHz 8 8 MHz 6 4 2 0 -40 0 25 70 85 Temperature (C) Doc ID 15056 Rev 3 31/69 Electrical characteristics Table 14. STM32F102x8, STM32F102xB Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 C External clock(2) all peripherals enabled Supply current in Sleep mode IDD 48 MHz 20 36 MHz 15.5 24 MHz 11.5 16 MHz 8.5 8 MHz 5.5 48 MHz 6 36 MHz 5 24 MHz 4.5 16 MHz 4 8 MHz 3 mA External clock(2), all peripherals disabled 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 15. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/ VBAT VDD/VBAT VDD/VBAT TA = = 2.4 V = 3.3 V = 2.0 V 85 C Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, IDD Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator ON, independent watchdog OFF in Standby mode(2) Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF IDD_VBAT Max Backup domain Low-speed oscillator and RTC ON supply current 23.5 24 - 200 13.5 14 - 180 2.6 3.4 - TBD(3) 2.4 3.2 - TBD(3) 1.7 2 - 4 1.1 1.4 0.9 1.9(4) Unit A 1. Typical values are measured at TA = 25 C. 2. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when VDD is present the Backup Domain is powered by VDD supply). 3. TBD stands for to be determined. 4. Based on characterization, not tested in production. 32/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics Figure 12. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values Consumption ( A ) 2.5 2 2V 1.5 2.4 V 1 3V 0.5 3.6 V 0 -40 C 25 C 70 C 85 C 105 C Temperature (C) ai17351 Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 140 Consumption (A) 120 100 80 3.3 V 3.6 V 60 40 20 0 -45 25 70 90 Temperature (C) Doc ID 15056 Rev 3 33/69 Electrical characteristics STM32F102x8, STM32F102xB Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 140 Consumption (A) 120 100 80 3.3 V 3.6 V 60 40 20 0 -40 0 25 70 85 Temperature (C) Figure 15. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V Standby mode 3 Consumption (A) 2.5 2 3.3 V 1.5 3.6 V 1 0.5 0 -45 25 70 Temperature (C) 34/69 Doc ID 15056 Rev 3 90 STM32F102x8, STM32F102xB Electrical characteristics Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz) Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 The parameters given in Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 16. Symbol Typical current consumption in Run mode, code with data processing running from Flash Parameter Conditions External clock(3) IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK Typ(1) Typ(1) All peripherals enabled(2) All peripherals disabled 48 MHz 24.2 18.6 36 MHz 19 14.8 24 MHz 12.9 10.1 16 MHz 9.3 7.4 8 MHz 5.5 4.6 4 MHz 3.3 2.8 2 MHz 2.2 1.9 1 MHz 1.6 1.45 500 kHz 1.3 1.25 125 kHz 1.08 1.06 48 MHz 23.5 17.9 36 MHz 18.3 14.1 24 MHz 12.2 9.5 16 MHz 8.5 6.8 8 MHz 4.9 4 4 MHz 2.7 2.2 2 MHz 1.6 1.4 1 MHz 1.02 0.9 500 kHz 0.73 0.67 125 kHz 0.5 0.48 Unit mA 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 15056 Rev 3 35/69 Electrical characteristics Table 17. STM32F102x8, STM32F102xB Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock(3) IDD Supply current in Sleep mode fHCLK Typ(1) All peripherals All peripherals enabled(2) disabled 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.98 0.95 48 MHz 9.3 3.3 36 MHz 7 2.5 24 MHz 4.8 1.8 16 MHz 3.2 1.2 8 MHz 1.6 0.6 4 MHz 1 0.5 2 MHz 0.72 0.47 1 MHz 0.56 0.44 500 kHz 0.49 0.42 125 kHz 0.43 0.41 mA Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 36/69 Unit Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 5. Table 18. Peripheral current consumption Peripheral APB1 Typical consumption at 25 C(1) TIM2 0.90 TIM3 0.86 TIM4 0.88 SPI2 0.26 USART2 0.45 USART3 0.43 USB 0.57 I2C1 0.24 I2C2 0.25 GPIO A 0.45 GPIO B 0.32 GPIO C 0.49 GPIO D 0.32 (2) 1.51 Unit mA APB2 ADC1 1. SPI1 0.21 USART1 0.72 fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fHCLK/4, ADON bit in the ADC_CR2 register is set to 1. Doc ID 15056 Rev 3 37/69 Electrical characteristics 5.3.6 STM32F102x8, STM32F102xB External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 19. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 25 MHz (1) fHSE_ext User external clock source frequency VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) OSC_IN rise or fall time(1) Cin(HSE) DuCy(HSE) IL V 16 ns 20 OSC_IN input capacitance(1) 5 Duty cycle pF 45 VSS VIN VDD OSC_IN Input leakage current 55 % 1 A 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 20. Low-speed external user clock characteristics Symbol Parameter Conditions Min frequency(1) Typ Max Unit 32.768 1000 kHz fLSE_ext User external clock source VLSEH OSC32_IN input pin high level voltage 0.7VDD VDD VLSEL OSC32_IN input pin low level voltage VSS 0.3VDD tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) Cin(LSE) DuCy(LSE) IL ns 50 OSC32_IN input capacitance(1) 5 Duty cycle OSC32_IN Input leakage current 30 VSS VIN VDD 1. Guaranteed by design, not tested in production. 38/69 V Doc ID 15056 Rev 3 pF 70 % 1 A STM32F102x8, STM32F102xB Electrical characteristics Figure 16. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External clock source fHSE_ext OSC _IN IL STM32F102xx ai14975b Figure 17. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F102xx ai14976b Doc ID 15056 Rev 3 39/69 Electrical characteristics STM32F102x8, STM32F102xB High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 21. Symbol fOSC_IN HSE 4-16 MHz oscillator characteristics(1)(2) Parameter Conditions Oscillator frequency Min Typ Max Unit 4 8 16 MHz RF Feedback resistor 200 k C Recommended load capacitance versus equivalent serial RS = 30 resistance of the crystal (RS)(3) 30 pF i2 HSE driving current VDD = 3.3 V VIN = VSS with 30 pF load gm Oscillator transconductance Startup Startup time VDD is stabilized tSU(HSE) (4) 1 25 mA mA/V 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. 40/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics Figure 18. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator REXT(1) CL2 RF Bias controlled gain STM32F102xx OSC_OU T ai14977b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. Symbol LSE oscillator characteristics (fLSE = 32.768 kHz) Parameter Conditions Min Typ Max Unit RF Feedback resistor C(1) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(2) RS = 30 k 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.4 A gm Oscillator transconductance tSU(LSE)(3) Startup time 5 5 VDD is stabilized M A/V 3 s 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 2. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 3. Note: tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Doc ID 15056 Rev 3 41/69 Electrical characteristics Caution: STM32F102x8, STM32F102xB To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 KH z resonator CL2 RF Bias controlled gain OSC32_OU T STM32F102xx ai14978b 5.3.7 Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. High-speed internal (HSI) RC oscillator Table 23. Symbol fHSI HSI oscillator characteristics(1) Parameter Conditions Min Frequency Typ 8 User-trimmed with the RCC_CR register(2) ACCHSI Accuracy of the HSI oscillator Factorycalibrated(4) tsu(HSI)(4) HSI oscillator startup time IDD(HSI)(4) HSI oscillator power consumption Max MHz 1(3) % TA = -40 to 105 C -2 2.5 % TA = -10 to 85 C -1.5 2.2 % TA = 0 to 70 C -1.3 2 % TA = 25 C -1.1 1.8 % 1 2 s 100 A 80 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. 42/69 Unit Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics low-speed internal (LSI) RC oscillator Table 24. LSI oscillator characteristics (1) Symbol fLSI Parameter Frequency tsu(LSI)(3) LSI oscillator startup time IDD(LSI)(3) LSI oscillator power consumption Min(2) Typ Max Unit 30 40 60 kHz 85 s 1.2 A 0.65 1. VDD = 3 V, TA = 40 to 85 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 25. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 s Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low-power mode) 5.4 Wakeup from Standby mode 50 s s 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 26. PLL characteristics Value Symbol fPLL_IN fPLL_OUT Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 60 % PLL multiplier output clock 16 48 MHz Doc ID 15056 Rev 3 43/69 Electrical characteristics Table 26. STM32F102x8, STM32F102xB PLL characteristics (continued) Value Symbol Parameter Min(1) Unit Max(1) Typ tLOCK PLL lock time 200 s Jitter Cycle-to-cycle jitter 300 ps 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = -40 to 85 C unless otherwise specified. Table 27. Symbol Flash memory characteristics Parameter Conditions Min(1) Typ Max(1) Unit 52.5 70 s tprog 16-bit programming time TA-40 to +85 C 40 tERASE Page (1 KB) erase time TA -40 to +85 C 20 40 ms Mass erase time TA -40 to +85 C 20 40 ms Read mode fHCLK = 48 MHz with 2 wait states, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 48 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 A 3.6 V tME IDD Vprog Supply current Programming voltage 2 1. Guaranteed by design, not tested in production. Table 28. Flash memory endurance and data retention Value Symbol Parameter NEND Endurance tRET Data retention Conditions TA = 85 C, 1000 cycles Min(1) Unit Typ Max 10 kcycles 30 Years 1. Based on characterization not tested in production. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. 44/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29. EMS characteristics Symbol Parameter Conditions Level/Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD 3.3 V, TA +25 C, fHCLK 48 MHz conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, TA +25 C, fHCLK 48 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations: the software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers, etc.) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Doc ID 15056 Rev 3 45/69 Electrical characteristics Table 30. STM32F102x8, STM32F102xB EMI characteristics Symbol Parameter SEMI 5.3.11 Peak level Conditions VDD 3.3 V, TA 25 C, Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/48 MHz 0.1 MHz to 30 MHz 7 30 MHz to 130 MHz 8 130 MHz to 1GHz 13 SAE EMI Level 3.5 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage TA +25 C, conforming (human body model) to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge voltage TA +25 C, conforming (charge device model) to JESD22-C101 II 500 Unit V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 32. Symbol LU 46/69 Electrical sensitivities Parameter Static latch-up class Conditions TA +105 C conforming to JESD78A Doc ID 15056 Rev 3 Class II level A STM32F102x8, STM32F102xB 5.3.12 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 33. I/O static characteristics Symbol VIL VIH Parameter Conditions Input low level voltage Standard IO input high level voltage Input low level voltage VIH Input high level voltage Ilkg IO FT Schmitt trigger voltage hysteresis(2) Input leakage current (3) Max -0.5 0.8 2 VDD+0.5 2 5.5V -0.5 0.35 VDD 0.65 VDD VDD+0.5 CMOS ports Standard IO Schmitt trigger voltage hysteresis(2) Vhys Typ Unit V TTL ports IO FT(1) input high level voltage VIL Min V 200 mV 5% VDD(3) mV VSS VIN VDD Standard I/Os 1 VIN = 5 V, I/O FT 3 A RPU Weak pull-up equivalent resistor(4) VIN VSS 30 40 50 k RPD Weak pull-down equivalent resistor(5) VIN VDD 30 40 50 k CIO I/O pin capacitance 5 pF 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: For VIH: - if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included - if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included For VIL: - if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included - if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included Doc ID 15056 Rev 3 47/69 Electrical characteristics STM32F102x8, STM32F102xB Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 6). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 6). Output voltage levels Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 34. Output voltage characteristics Symbol Parameter VOL(1) Output Low level voltage for an I/O pin when 8 pins are sunk at the same time VOH(2) Output High level voltage for an I/O pin when 8 pins are sourced at the same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at the same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOH (2) Output high level voltage for an I/O pin when 8 pins are sourced at the same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions TTL port, IIO = +8 mA, 2.7 V < VDD < 3.6 V CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA(3) 2.7 V < VDD < 3.6 V IIO = +6 mA(3) 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. 48/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 20 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 35. MODEx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter fmax(IO)out Maximum frequency(2) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw Frequency(2) Output high to low level fall time Output low to high level rise time Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns (3) 125 CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz 25(3) CL= 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 20. 3. Guaranteed by design, not tested in production. Doc ID 15056 Rev 3 49/69 Electrical characteristics STM32F102x8, STM32F102xB Figure 20. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33). Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage -0.5 0.8 VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis V Weak pull-up equivalent resistor(2) RPU Unit VF(NRST)(1) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse 200 VIN VSS 30 40 mV 50 k 100 ns 300 ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 21. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset Filter 0.1 F STM32F10xxx ai14132c 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device. 50/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB 5.3.14 Electrical characteristics TIM timer characteristics The parameters given in Table 37 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 37. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 20.84 ns Timer resolution time fTIMxCLK = 48 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 48 MHz 0 fTIMxCLK/2 MHz 0 24 MHz 16 bit 65536 tTIMxCLK 1365 s 65536 x 65536 tTIMxCLK 89.48 s Timer resolution 16-bit counter clock period when internal clock is selected tMAX_COUNT Maximum possible count Unit 1 fTIMxCLK = 48 MHz 0.0208 fTIMxCLK = 48 MHz 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. 5.3.15 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 8. The STM32F102xx medium-density USB access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Doc ID 15056 Rev 3 51/69 Electrical characteristics Table 38. STM32F102x8, STM32F102xB I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 (3) 0(4) 900(3) 20+0.1Cb 300 s th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time 1000 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line 0 300 s 400 400 1. Values guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 52/69 ns Doc ID 15056 Rev 3 pF STM32F102x8, STM32F102xB Electrical characteristics Figure 22. I2C bus AC waveforms and measurement circuit(1) VDD 4 .7 k VDD 4 .7 k 100 100 IC bus STM32F102xx SDA SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCKH) tsu(SDA) tw(SCKL) tr(SCK) tsu(STA:STO) S TOP th(SDA) tsu(STO) tf(SCK) ai14979 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 39. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2) fSCL I2C_CCR value (kHz) RP = 4.7 k 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 15056 Rev 3 53/69 Electrical characteristics STM32F102x8, STM32F102xB SPI interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40. Symbol fSCK 1/tc(SCK) SPI characteristics(1) Parameter Conditions Min 18 Slave mode 18 8 ns 70 % MHz SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 tsu(NSS)(2) NSS setup time Slave mode 4tPCLK th(NSS)(2) NSS hold time Slave mode 2tPCLK SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 Master mode 5 Slave mode 5 Master mode 5 Slave mode 4 tsu(MI) (2) tsu(SI)(2) th(MI) ta(SO) (2)(3) 60 Data input setup time (2) th(SI)(2) Data input hold time Data output access time Slave mode, fPCLK = 20 MHz tdis(SO)(2)(4) Data output disable time Slave mode ns 0 3tPCLK 2 10 (2)(1) Data output valid time Slave mode (after enable edge) 25 tv(MO)(2)(1) Data output valid time Master mode (after enable edge) 5 tv(SO) th(SO)(2) th(MO)(2) Unit Master mode SPI clock frequency tr(SCK) tf(SCK) tw(SCKH)(2) tw(SCKL)(2) Max Data output hold time Slave mode (after enable edge) 15 Master mode (after enable edge) 2 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 54/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics Figure 23. SPI timing diagram - slave mode and CPHA=0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 24. SPI timing diagram - slave mode and CPHA=1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15056 Rev 3 55/69 Electrical characteristics STM32F102x8, STM32F102xB Figure 25. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 41. USB startup time Symbol tSTARTUP 56/69 Parameter USB transceiver startup time Doc ID 15056 Rev 3 Max Unit 1 s STM32F102x8, STM32F102xB Table 42. Electrical characteristics USB DC electrical characteristics Symbol Parameter VDD Input levels VDI (4) VCM(4) Min.(1) Conditions USB operating voltage(2) 3.0(3) VOL VOH 3.6 V V Differential input sensitivity I(USBDP, USBDM) 0.2 Differential common mode range Includes VDI range 0.8 2.5 1.3 2.0 VSE(4) Single ended receiver threshold Output levels Max.(1) Unit RL of 1.5 k to 3.6 V(5) Static output level low RL of 15 k to Static output level high VSS(5) 0.3 V 2.8 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 26. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S Table 43. tf trfm VCRS ai14137 USB: Full speed electrical characteristics of the driver(1) Symbol tr tr tf Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.16 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8. Note: It is recommended to perform a calibration after each power-up. Doc ID 15056 Rev 3 57/69 Electrical characteristics STM32F102x8, STM32F102xB Table 44. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V fADC ADC clock frequency 0.6 12 MHz fS(1) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V 50 k fTRIG(1) VAIN External trigger frequency fADC = 12 MHz 0 (VSSA or VREF- tied to ground) Conversion voltage range(2) See Equation 1 and Table 45 for details RAIN(1) External input impedance RADC(1) Sampling switch resistance 1 k CADC(1) Internal sample and hold capacitor 8 pF tCAL(1) Calibration time fADC = 12 MHz tlat(1) Injection trigger conversion latency fADC = 12 MHz tlatr(1) Regular trigger conversion latency fADC = 12 MHz tS(1) Sampling time tSTAB(1) Power-up time tCONV(1) Total conversion time (including sampling time) 5.9 s 83 1/fADC 0.214 s 3(3) 1/fADC 0.143 s (3) 2 fADC = 12 MHz 0.107 17.1 s 1.5 239.5 1/fADC 1 s 18 s 0 fADC = 12 MHz 1/fADC 1.2 0 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Guaranteed by design, not tested in production. 2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA, 3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 44. Equation 1: RAIN max formula: TS R AIN ------------------------------------------------------------- - R ADC N+2 f ADC C ADC ln 2 The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). 58/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Table 45. Electrical characteristics RAIN max for fADC = 12 MHz(1) Ts (cycles) tS (s) RAIN max (k) 1.5 0.13 0.4 7.5 0.63 5.9 13.5 1.13 11.4 28.5 2.38 25.2 41.5 3.46 37.2 55.5 4.63 50 71.5 5.96 NA 239.5 19.96 NA 1. Data guaranteed by design, not tested in production. Table 46. Symbol ADC accuracy - limited test conditions(1) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(2) fPCLK2 = 48 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration 1.3 2 1 1.5 0.5 1.5 0.7 1 0.8 1.5 Typ Max(3) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Table 47. ADC accuracy(1) (2) Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 48 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. Based on characterization, not tested in production. Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog pin. It is recommended to add a Schottky diode (pin to ground) to standard analog pins that may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Doc ID 15056 Rev 3 59/69 Electrical characteristics STM32F102x8, STM32F102xB Figure 27. ADC accuracy characteristics [1LSBIDEAL = VDDA 4096 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET 7 (1) 6 5 4 ET=Total u nadjusted er ror: maximum deviation between the actual and the ideal transfer curves. EO=Offset e rror: deviation between the first actual transition and the first ideal one. EG=Gain er ror: deviation between the last ideal transition and the last actual one. ED=Differential linearity error: maximum deviation between actual steps and the ideal one. EL=Integral linearity error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai15497 Figure 28. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL1 A STM32F102 Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14974b 1. Refer to Table 44 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 60/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 29. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 29. Power supply and reference decoupling STM32F102xx VDDA 1 F // 10 nF VSSA ai14980b 5.3.17 Temperature sensor characteristics Table 48. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min Typ Max Unit VSENSE linearity with temperature 1.5 C Average slope 4.35 mV/C Voltage at 25C 1.42 V Startup time 4 ADC sampling time when reading the temperature 10 s 17.1 s 1. Guaranteed by characterization, not tested in production. 2. Data guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Doc ID 15056 Rev 3 61/69 Package characteristics STM32F102x8, STM32F102xB 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 62/69 Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Package characteristics Figure 30. LQFP64 - 10 x 10 mm, 64 pin low-profile quad Figure 31. Recommended flat package outline(1) footprint(1)(2) A A2 48 A1 33 0.3 49 E 32 0.5 b E1 12.7 10.3 10.3 e 64 17 1.2 1 16 7.8 D1 c 12.7 L1 D ai14909 L ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 49. LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15056 Rev 3 63/69 Package characteristics STM32F102x8, STM32F102xB Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Figure 33. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 0.25 mm Gage plane C 1.20 D 36 0.30 25 37 24 D1 k D3 A1 L 25 36 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 E3 E1 5.80 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 50. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max A Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 5.500 0.0059 0.0079 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 e L k ccc 0.2165 0.500 0.450 L1 0.600 0.0197 0.750 0.0177 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 1. Values in inches are converted from mm and rounded to 4 decimal digits. 64/69 Min Doc ID 15056 Rev 3 0 3.5 0.0031 7 STM32F102x8, STM32F102xB 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions on page 27. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 51. Symbol JA 6.3 Package thermal characteristics Parameter Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch Value Unit 55 C/W Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 15056 Rev 3 65/69 Package characteristics 6.3.1 STM32F102x8, STM32F102xB Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 52: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (-40 to 85 C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F102xx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 51 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 82 C + (45 C/W x 447 mW) = 82 C + 20.1 C = 102.1 C This is within the junction temperature range of the STM32F102xx (-40 < TJ < 105 C). Figure 34. LQFP64 PD max vs. TA 700 PD (mW) 600 500 400 Suffix 6 300 200 100 0 65 75 85 95 TA (C) 66/69 Doc ID 15056 Rev 3 105 115 STM32F102x8, STM32F102xB 7 Ordering information scheme Ordering information scheme Table 52. Ordering information scheme Example: STM32 F 102 C 8 T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 102 = USB access line, USB 2.0 full-speed interface Pin count C = 48 pins R = 64 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, -40 to 85 C. Options xxx = programmed parts TR = tape and real Doc ID 15056 Rev 3 67/69 Revision history 8 Revision history Table 53. Document revision history Date Revision 23-Sep-2008 1 Initial release. 2 I/O information clarified on page 1. Figure 1: STM32F102xx mediumdensity USB access line block diagram and Figure 5: Memory map modified. In Table 4: Medium-density STM32F102xx pin definitions: PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column. PD value added for LQFP64 package in Table 8: General operating conditions. Note modified in Table 12: Maximum current consumption in Run mode, code with data processing running from Flash and Table 14: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 13, Figure 14 and Figure 15 show typical curves. Figure 27: ADC accuracy characteristics modified. Figure 29: Power supply and reference decoupling modified. Table 19: High-speed external user clock characteristics and Table 20: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 23: HSI oscillator characteristics. Small text changes. 3 Note 5 updated in Table 4: Medium-density STM32F102xx pin definitions. VRERINT and TCoeff added to Table 11: Embedded internal reference voltage. Typical IDD_VBAT value added in Table 15: Typical and maximum current consumptions in Stop and Standby modes. Figure 12: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. fHSE_ext min modified in Table 19: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator characteristics and Table 22: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 23: HSI oscillator characteristics modified. Conditions removed from Table 25: Low-power mode wakeup timings. Note 1 modified below Figure 18: Typical application with an 8 MHz crystal. Figure 21: Recommended NRST pin protection modified. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 44. Jitter added to Table 26: PLL characteristics. Table 40: SPI characteristics modified. CADC and RAIN parameters modified in Table 44: ADC characteristics. RAIN max values modified in Table 45: RAIN max for fADC = 12 MHz. Small text changes. 23-Apr-2009 22-Sep-2009 68/69 STM32F102x8, STM32F102xB Changes Doc ID 15056 Rev 3 STM32F102x8, STM32F102xB Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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