Features
TECHNICAL NOTE
Description
BR93L-W series is a serial EEPROM of serial 3-line interface method.
BR93L Series
y 3-line communications of chip select, serial clock, serial data input / output (the case where input and output are shared)
y Actions available at high speed 2MHz clock (2.5 ~ 5.5V)
y Speed write available (write time 5 ms max.)
y Same package and pin layout from 1Kbit to 16Kbit
y 1.8 ~ 5.5V single power source action
y Highly reliable connection by Au pad and Au wire
y Address auto increment function at read action
y Write mistake prevention function
Write prohibition at power on
Write prohibition by command code
Write mistake prevention function at low voltage
y Program cycle auto delete and auto end function
y Program condition display by READY / BUSY
y Low current consumption
At write action (at 5V) : 1.2mA (Typ.)
At read action (at 5V) : 0.3mA (Typ.)
At standby action (at 5V) : 0.1µA (Typ.) (CMOS input)
y TTL compatible input / output
y Compact package SOP8, SOP-J8, SSOP-B8, TSSOP-B8, MSOP8, TSSOP-B8J
y Data retention for 40 years
y Data rewrite up to 1,000,000 times
y Data at shipment all addresses FFFFh
Capacity Bit format
Packagetype
Type
Power source voltage
SOP8
FRFFJRFJ FV RFV FVT RFVT RFVM RFVJ
●
●
●
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
●
●
●
●
●
SSOP-B8
●
●
●
●
●
●
●
●
●
●
MSOP8
●
●
●
TSSOP-B8
●
●
●
●
●
●
●
●
TSSOP-B8J
●
●
●
●
●
1.8 ~ 5.5V
1.8 ~ 5.5V
1.8 ~ 5.5V
1.8 ~ 5.5V
1.8 ~ 5.5V
BR93L46-W
BR93L66-W
BR93L56-W
BR93L86-W
BR93L76-W
64 × 16
128 × 16
256 × 16
512 × 16
1K × 16
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
Microwire
BUS
Serial
EEPROMs
BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W
HIGH GRADE Specification HIGH RELIABILITY series
Supply voltage 1.8V~5.5V
Operating temperature –40°C~+85°C type
Ver.B Oct.2005
2/16
Absolute Maximum Ratings (Ta=25˚C) Recommended action conditions
Parameter Limits Unit
-0.3 ~ +6.5 V
mW
-65 ~ +125 ˚C
˚C
V
-40 ~ +85
-0.3 ~ VCC+0.3
Symbol
-
VCC
Pd
Tstg
Topr
SOP8 (F, RF) 450 (*1)
SOP-J8 (FJ, RFJ) 450 (*2)
TSSOP-B8 (FVT, RFVT)
330 (*4)
SSOP-B8 (FV, RFV) 300 (*3)
TSSOP-B8J (RFVJ) 310 (*6)
MSOP8 (RFVM) 310 (*5)
Impressed voltage
Permissible dissipation
Storage temperature range
Action temperature range
Terminal voltage
* When using at Ta = 25˚C or higher, 4.5mW (*1, *2), 3.0mW (*3), 3.3mW (*4),3.1mW (*5, *6)
to be reduced per 1˚C.
Parameter Unit
V
V
Symbol
VIN
VCC
Limits
0 ~ VCC
1.8 ~ 5.5
Power source voltage
Input voltage
Electrical characteristics (Unless otherwise specified, Ta=-40 ~ +85˚C, Vcc=2.5 ~ 5.5V)
(Unless otherwise specified, Ta=-40 ~ +85˚C, Vcc=1.8 ~ 2.5V)
Parameter Symbol Min. Typ. Max. Unit Conditions
"H" output voltage 1 VOH1 -VCC VIOH=-0.4mA, 4.0V≤VCC≤5.5V
2.4
"H" output voltage 2 VOH2 -VCC VIOH=-100µA
VCC-0.2
Input leak current ILI -+1 µA VIN=0~VCC
-1
Current consumption at
action
ICC3 -4.5 mA
Standby current ISB -
-
ICC1 -3.0 mA
-
ICC2 -1.5 mA
-
-2µA
Output leak current ILO -1 - +1 µA VOUT=0~VCC, CS=0V
VIH1 -VCC+0.3 V
2.0 4.0V≤VCC≤5.5V
"H" input voltage 1
VIL1 -0.3 - +0.8 V 4.0V≤VCC≤5.5V
"L" input voltage 1
VIH2 -VCC+0.3 V0.7xVCC VCC≤4.0V
"H" input voltage 2
VIL2 -0.3 - 0.2xVCC VVCC≤4.0V
"L" input voltage 2
VOL2 0-0.2 V IOL=100µA
"L" output voltage 2
VOL1 0-0.4 V IOL=2.1mA, 4.0V≤VCC≤5.5V
"L" output voltage 1
CS=0V, DO=OPEN
fSK=2MHz, tE/W=5ms (WRITE)
fSK=2MHz, tE/W=5ms (WRAL,ERAL)
fSK=2MHz (READ)
Radiation resistance design is not made.
Parameter Symbol Min. Typ. Max. Unit Conditions
"H" output voltage VOH -VCC VIOH=-100µA
VCC-0.2
Input leak current ILI -+1 µA VIN=0~VCC
-1
Current consumption at
action
ICC3 -2mA
Standby current ISB -
-
ICC1 -1.5 mA
-
ICC2 -0.5 mA
-
-2µA
Output leak current ILO -1 - +1 µA VOUT=0~VCC, CS=0V
VIH -VCC+0.3 V
0.7xVCC
"H" input voltage
VIL -0.3 - 0.2xVCC V"L" input voltage
VOL 0-0.2 V IOL=100µA
"L" output voltage
CS=0V, DO=OPEN
fSK=500kHz, tE/W=5ms (WRITE)
fSK=500kHz (WRAL,ERAL)
fSK=500kHz (READ)
Radiation resistance design is not made.
Memory cell characteristics (Ta=25˚C, Vcc=1.8 ~ 5.5V)
Parameter Min. Typ. Max. Unit
-Years
40
1,000,000 -
-
-Times
Number of data rewrite times
*1
Data hold years *1
*1 Not 100% TESTED
3/16
Action timing characteristics (Ta=-40 ~ +85˚C, Vcc=2.5 ~ 5.5V)
Parameter Symbol Min. Typ. Max. Unit
fSK --2MHz
tSKH 230 - - ns
tSKL 230 - - ns
tCS 200 - - ns
tCSS 50 - - ns
tDIS 100 - - ns
tCSH 0--ns
tDIH 100 - - ns
tPD1 --200 ns
tPD0 --200 ns
tSV --150 ns
tDF --150 ns
--5mstE/W
SK frequency
Data "1" output delay time
Data "0" output delay time
Write cycle time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
SK "H" time
Time from CS to output establishment
Time from CS to High-Z
Parameter Symbol Min. Typ. Max. Unit
fSK --500 kHz
tSKH 0.8 - - µs
tSKL 0.8 - - µs
tCS 1--µs
tCSS 200 - - ns
tDIS 100 - - ns
tCSH 0--ns
tDIH 100 - - ns
tPD1 --0.7 µs
tPD0 --0.7 µs
tSV --0.7 µs
tDF --200 ns
--5ms
tE/W
(Ta=-40 ~ +85˚C, Vcc=1.8 ~ 2.5V)
Sync data input / output timing
Fig.1 Sync data input / output timing
CS
SK
DI
DO (READ)
DO (WRITE) STATUS VALID
tDF
tPD1tPD0
tDIHtDIS
tCSS tCSH
tSKH tSKL
SK frequency
Data "1" output delay time
Data "0" output delay time
Write cycle time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
SK "H" time
Time from CS to output establishment
Time from CS to High-Z
Data is taken by DI in sync with the rise of SK.
At read action, data is output from DO in sync with the rise of SK.
The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is "H", and valid until the next command start bit is input. And, while CS is "L", DO becomes High-Z.
After completion of each mode execution, set CS "L" once for internal circuit reset, and execute the following action
mode.
4/16
Characteristic data
2
6
5
4
3
2
1
001 34 65
H INPUT VOLTAGE : VIH (V)
Fig. 2 H input voltage VIH (CS,SK,DI)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
6
5
4
3
2
1
001 34 65
L INPUT VOLTAGE : VIL (V)
Fig. 3 H input voltage VIL(CS,SK,DI)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.8
0.6
0.4
0.2
001 345
L OUTPUT VOLTAGE : VOL (V)
Fig. 4 L output voltage VOL-IOL(VCC=1.8V)
L OUTPUT CURRENT : IOL (mA)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.8
0.6
0.4
0.2
001 345
L OUTPUT VOLTAGE : VOL (V)
Fig. 5 L output voltage VOL-IOL(VCC=2.5V)
L OUTPUT CURRENT : IOL (mA)
SPEC Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.8
0.6
0.4
0.2
001 345
L OUTPUT VOLTAGE : VOL (V)
Fig. 6 L output voltage VOL-IOL(VCC=4.0V)
L OUTPUT CURRENT : IOL (mA)
SPEC
Ta=85˚CTa=25˚C
Ta=-40˚C
0.8
5
4
3
2
1
000.4 1.21.6
H OUTPUT VOLTAGE : VOH (V)
Fig. 7 H output voltage VOH-IOH(VCC=1.8V)
H OUTPUT CURRENT : IOH (mA)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
0.8
5
4
3
2
1
000.4 1.21.6
H OUTPUT VOLTAGE : VOH (V)
Fig. 8 H output voltage VOH-IOH(VCC=2.5V)
H OUTPUT CURRENT : IOH (mA)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
0.8
5
4
3
2
1
000.4 1.2 1.6
H OUTPUT VOLTAGE : VOH (V)
Fig. 9 H output voltage VOH-IOH(VCC=4.0V)
H OUTPUT CURRENT : IOH (mA)
SPEC Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1.2
1
0.8
0.6
0.4
0.2
001 34 65
INPUT LEAK CURRENT : ILI (µA)
Fig. 10 Input leak current ILI (CS,SK,DI)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1.2
1
0.8
0.6
0.4
0.2
001 34 65
OUTPUT LEAK CURRENT : ILO (µA)
Fig. 11 Output leak current ILO (DO)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
5
4
3
2
1
001 34 65
CURRENT CONSUMPTION
AT WRITING : ICC1 (WRITE) (mA)
Fig. 12 Current consumption at WRITE action
ICC1(WRITE,fSK=2MHz)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
fSK=2MHz
DATA=0000h
2
2.5
2
1.5
1
0.5
001 34 65
CURRENT CONSUMPTION
AT READING : ICC2 (READ) (mA)
Fig. 13 Consumption current at READ action
ICC2(READ,fSK=2MHz)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
fSK=2MHz
DATA=0000h
2
5
4
3
2
1
001 34 65
CURRENT CONSUMPTION
AT OPERATING : ICC3 (WRAL) (mA)
Fig. 14 Consumption current at WRAL action
ICC3(WRAL,fSK=2MHz)
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
fSK=2MHz
DATA=0000h
2
5
4
3
2
1
001 34 65
CURRENT CONSUMPTION
AT WRITING : ICC1 (WRITE) (mA)
Fig. 15 Current consumption at WRITE action
ICC1(WRITE,fSK=500kHz)
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
fSK=500kHz
DATA=0000h
2
2.5
2
1.5
1
0.5
001 34 65
CURRENT CONSUMPTION
AT READING : ICC2 (READ) (mA)
Fig. 16 Consumption current at READ action
ICC2(READ,fSK=500kHz)
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC Ta=85˚C
Ta=25˚C
Ta=-40˚C
fSK=500kHz
DATA=0000h
5/16
2
5
4
3
2
1
001 34 65
CURRENT CONSUMPTION
AT OPERATING : ICC3 (WRAL) (mA)
Fig. 17 Consumption current at WRAL action
ICC3(WRAL,fSK=500kHz)
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
fSK=500kHz
DATA=0000h
2
2.5
2
1.5
1
0.5
001 34 65
STAND BY CURRENT : ISB (µA)
Fig. 18 Consumption current at standby action ISB
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚CTa=25˚C
Ta=-40˚C
2
100
10
1
0.1
0.0101 34 65
SK FREQUENCY : fSK (MHz)
Fig. 19 SK frequency fSK
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.6
0.8
0.4
0.2
001 34 65
H SK TIME : tSKH (µs)
Fig. 20 SK high time tSKH
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.6
0.8
0.4
0.2
001 34 65
L SK TIME : tSKL (µs)
Fig. 21 SK low time tSKL
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1.2
1
0.6
0.8
0.4
0.2
001 34 65
L CS TIME : tCS (µs)
Fig. 22 CS low time tCS
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
50
-50
0
-100
-150
-200
01 34 65
CS HOLD TIME : tCSH (ns)
Fig. 23 CS hold time tCSH
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
300
100
200
0
-100
-200
01 34 65
CS SETUP TIME : tCSS (ns)
Fig. 24 CS setup time tCSS
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
150
50
100
0
-50
01 34 65
DI HOLD TIME : tDIH (ns)
Fig. 25 DI hold time tDIH
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
150
50
100
0
-50
01 34 65
DI SETUP TIME : tDIS (ns)
Fig. 26 DI setup time tDIS
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.6
0.8
0.4
0.2
001 34 65
DATA "0" OUTPUT DELAY TIME : tPD0 (µs)
Fig. 27 Data "0" output delay time tPD0
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.6
0.8
0.4
0.2
001 34 65
DATA "1" OUTPUT DELAY TIME : tPD1 (µs)
Fig. 28 Output data "1" delay time tPD1
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
1
0.6
0.8
0.4
0.2
001 34 65
TIME BETWEEN CS AND OUTPUT : tSV (µs)
Fig. 29 Time from CS to output establishment tSV
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
250
150
200
100
50
001 34 65
TIME BETWEEN CS AND
OUTPUT HIGH-Z : tDF (ns)
Fig. 30 Time from CS to High-Z tDF
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
2
6
5
3
4
2
1
001 34 65
WRITE CYCLE TIME : tE/W (ms)
Fig. 31 Write cycle time tE/W
SUPPLY VOLTAGE : VCC (V)
SPEC
Ta=85˚C
Ta=25˚C
Ta=-40˚C
6/16
Block diagram
Power source voltage detection
High voltage occurrence
Write
prohibition
Command
register
Dummy bit
Data
register
R/W
amplifier
1,024 bit
2,048 bit
4,096 bit
8,192 bit
16,384 bit
EEPROM
Command decode
Control
Clock generation
Address
buffer
6bit
7bit
8bit
9bit
10bit
6bit
7bit
8bit
9bit
10bit
16bit 16bit
Address
decoder
CS
SK
DI
DO
Fig. 32 Block diagram
Pin assignment and function
BR93LXXF-W:SOP8
BR93LXXFJ-W:SOP-J8
BR93LXXFV-W:SSOP-B8*
BR93LXXFVT-W:TSSOP-B8*
NC VCC CS SK
DIDOGNDNC
BR93LXXRF-W:SOP8
BR93LXXRFJ-W:SOP-J8
BR93LXXRFV-W:SSOP-B8
BR93LXXRFVT-W:TSSOP-B8
BR93LXXRFVM-W:MSOP8
BR93LXXRFVJ-W:TSSOP-B8J
CS SK DI DO
GNDNCNCVCC
Serial data output, READY / BUSY internal condition display output
Power source
Function
All input / output reference voltage, 0V
Chip select input
Serial clock input
DI
VCC
CS
Pin name
GND
DO
SK
I / O
-
-
Input
Input
Output
Non connected terminal, Vcc, GND or OPEN
NC -
Input Start bit, ope code, address, and serial data input
Fig. 33 Pin assignment diagram
* BR93L46/56/66-W
7/16
Description of operations
Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input), DO (serial data output), and CS
(chip select) for device selection.
When to connect one EEPROM to a microcontroller, connect it as shown in Fig. 34 (a) or Fig. 34 (b). When to use the input and
output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig. 34 (b) (Refer to pages 13/16.),
and connection by 3 lines is available.
In the case of plural connections, refer to Fig. 34 (c).
Fig. 34 Connection method with microcontroller
Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After
input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners.
"0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the
microcontroller, input "0" before the start bit input, to control the bit width.
Micro-
controller
Fig. 34-(a) Connection by 4 lines
CS
SK
DO
DI
BR93LXX
CS
SK
DI
DO
Fig. 34-(b) Connection by 3 lines Fig. 34-(c) Connection example of plural devices
CS
SK
DIO
BR93LXX
CS
SK
DI
DO Device 1
CS3
CS1
CS0
SK
DO
DI
CS
SK
DI
DO
Device 2
CS
SK
DI
DO
Device 3
CS
SK
DI
DO
Command mode
* Start bit
Acceptance of all the commands of this IC starts at recognition of the start bit.
The start bit means the first "1" input after the rise of CS.
y Input the address and the data in MSB first manners.
y As for , input either VIH or VIL.
A7 of BR93L56-W becomes Don't Care.
A9 of BR93L76-W becomes Don't Care.
Command Start bit Ope code
Address Data
Read (READ) *1
Write enable (WEN)
Write (WRITE) *2
Write all (WRAL) *2
Erase (ERASE)
Write disable (WDS)
Chip erase (ERAL)
110
00
01
00
00
11
00
1
1
1
1
1
1
A5,A4,A3,A2,A1,A0
A5,A4,A3,A2,A1,A0
A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
BR93L46-W BR93L56/66-W BR93L76/86-W
D15 ~ D0
(READ DATA)
D15 ~ D0
(WRITE DATA)
D15 ~ D0
(WRITE DATA)
Micro-
controller
Micro-
controller
*1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are
sequentially output continuously. (Auto increment function)
*2 When the read, and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written.
8/16
Timing chart
1) Read cycle (READ)
2) Write cycle (WRITE)
3) Write all cycle (WRAL)
CS
SK
DI
DO
*1
*2
D14
D15
D0
D1
D14
D15
0
High-Z
110Am A1 A0
124n
n+1
BR93L46-W : n=25, m=5
BR93L56/66-W : n=27, m=7
BR93L76/86-W : n=29, m=9
BR93L46-W : n=25, m=5
BR93L56/66-W : n=27, m=7
BR93L76/86-W : n=29, m=9
*1 Start bit
Fig. 35 Read cycle
Fig. 36 Write cycle
BR93L46-W : n=25
BR93L56/66-W : n=27
BR93L76/86-W : n=29
CS
SK
DI
DO
High-Z
011Am A1 A0 D15 D14 D1 D0
STATUStCS
READYBUSY
tSV
tE/W
Fig. 37 Write all cycle
12 4 n
tCS
CS
SK
DI
DO
High-Z
00110D15 D14 D1 D0
12 5 n
STATUS
READYBUSY
tSV
tE/W
When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input, it is recognized as a start
bit, and the following operation is started. This is common to all the commands to described hereafter.
When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0,
in sync with the rise of SK, "0" (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has address auto increment function valid only at read command. This is the function where after the above
read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto
increment, keep CS at "H".
In this command, input 16bit data (D15 ~ D0) are written to designated addresses (Am ~ A0). The actual write starts by
the fall of CS of D0 taken SK clock.
When STATUS is not detected, (CS = "L" fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected (CS
= "H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any
command.
In this command, input 16bit data is written simultaneously to all addresses. Data is not written continuously per one
word but is written in bulk, the write time is only Max. 5ms in conformity with tE/W.
9/16
4) Write enable (WEN) / disable (WDS) cycle
100
CS
DI
DO
High-Z
ENABLE = 1 1
DISABLE= 0 0
12345678n
SK BR93L46-W : n=9
BR93L56/66-W : n=11
BR93L76/86-W : n=13
BR93L46-W : n=9, m=5
BR93L56/66-W : n=11, m=7
BR93L76/86-W : n=13, m=9
Fig. 38 Write enable (WEN) / disable (WDS) cycle
Fig. 39 Erase cycle timing
Fig. 40 Chip erase cycle timing
5) Erase cycle timing (ERASE)
CS
SK
DI
DO
High-Z
A1A2A3Am A0
STATUStCS
READYBUSY
tSV
tE/W
12 4 n
111
6) Chip erase cycle timing (ERAL)
CS
SK
DI
DO
High-Z
STATUStCS
READYBUSY
tSV
tE/W
12 4 n
01010
BR93L46-W : n=9
BR93L56/66-W : n=11
BR93L76/86-W : n=13
At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid until the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
disable command. Input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it.
When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
canceled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
In this command, data of the designated address is made into "1". The data of the designated address becomes
"FFFFh". Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, status can be detected in the same manner as in WRITE command.
In this command, data of all addresses is erased. Data of all addresses becomes "FFFFh". Actual ERASE starts at the
fall of CS after the fall of the n-th clock from the start bit input.
In ERAL, status can be detected in the same manner as in WRITE command.
10/16
Application
1) Method to cancel each command
*1 Address is 8 bits in BR93L56-W, and BR93L66-W.
Address is 10 bits in BR93L76-W, and BR93L86-W.
READ
2) At standby
WRITE, WRAL
(In the case of BR93L46-W)
ERASE, ERAL
Fig. 41 READ cancel available timing
1 bit 2 bits 6 bits 16 bits
Start bit Ope code Address Data
Cancel is available in all areas in read mode.
*1
*1
*2
*3
*3
*1
*3
(In the case of BR93L46-W)
ab
tE/W
Fig. 42 WRITE, WRAL cancel available timing
1 bit 2 bits 6 bits 16 bits
Start bit Ope code Address Data
SK
DI D1
24 25
D0
Enlarged figure
y 25 Rise of clock
ab
1/2
tE/W
Fig. 43 ERASE, ERAL cancel available timing
1 bit 2 bits 6 bits
Start bit Ope code Address
a : From start bit to 9 clock rise
b : 9 clock rise and after
SK
DI A1 A0
Enlarged figure
y 9 Rise of clock
CS
SK
DI
Start bit input
CS = SK = DI = "H"
Wrong recognition as a start but
CS
SK
DI
Fig. 44 Wrong action timing Fig. 45 Normal action timing
Start bit input
If CS is started when SK = "L" or DI = "L", a start
bit is recognized correctly.
89
Cancel by CS = "L"
*2
*2
a : From start bit to 25 clock rise
b : 25 clock rise and after
Cancel by CS = "L"
y Method to cancel : cancel by CS = "L"
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
*1 Address is 8 bits in BR93L56-W, and BR93L66-W.
Address is 10 bits in BR93L76-W, and BR93L86-W.
*2 27 clocks in BR93L56-W, and BR93L66-W
29 clocks in BR93L76-W, and BR93L86-W
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
*1 Address is 8 bits in BR93L56-W, and BR93L66-W.
Address is 10 bits in BR93L76-W, and BR93L86-W.
*2 11 clocks in BR93L56-W, and BR93L66-W
13 clocks in BR93L76-W, and BR93L86-W
Standby current
When CS is "L", SK input is "L", DI input is "H", and even with middle electric potential, current does not increase.
Timing
As shown in Fig. 44, when SK at standby is "H", if CS is started, DI status may be read at the rise edge.
At standby and at power ON/OFF, when to start CS, set SK input or DI input to "L" status. (Refer to Fig. 45.)
11/16
Fig. 50 CS pull down resistance
Fig. 51 READY output timing at DO = OPEN
Fig. 46 Output circuit (DO) Fig. 47 Input circuit (CS)
3) Equivalent circuit
4) I/O peripheral circuit
DO
OEint.
CS
RESETint.
CSint.
SK
CSint.
DI
CSint.
Output circuit
Fig. 48 Input circuit (DI) Fig. 49 Input circuit (SK)
Input circuit Input circuit
Input circuit
4-1) Pull down CS.
By making CS = "L" at power ON/OFF, mistake in operation and mistake write are prevented.
4-2) DO is available in both pull up and pull down.
VOHM
IOHM Rpd
2.4
2×10-3
Rpd ≥
VOHM
IOHM
Rpd ≥. . .
Example) When Vcc = 5V, VIHE = 2V, VOHM = 2.4V, IOHM = 2mA,
from the equation ,
VOHM VIHE
≥. . .
With the value of Rpd to satisfy the above equation, VOHM becomes
2.4V or higher, and with VIHE (= 2.0V), the equation is also satisfied.
Rpd 1.2 (K)
≥
Microcontroller EEPROM
VIHE
"H" output "L" input
y VIHE : EEPROM VIH specifications
y VOHM : Microcontroller VOH specifications
y IOHM : Microcontroller IOH specifications
DI
SK
CS
DO
DI
SK
CS
DO
DO
D0
High-Z High-Z
READY
READY
Improvement by DO pull up
"H"
Enlarged
BUSY
BUSY
BUSY CS = SK = DI = "H"
When DO = pull up
CS = SK = DI = "H"
When DO = OPEN
Pull down resistance Rpd of CS pin
To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an
appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
DO output become "High-Z" in other READY / BUSY output timing than after data output at read command and write
command.
When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and
pull up DO.
When there is no influence upon the microcontroller actions, DO may be OPEN.
If DO is OPEN, and at timing to output status READY, at timing of CS = "H", SK = "H", DI = "H", EEPROM recognizes this
as a start bit, resets READY output, and DO = "High-Z", therefore, READY signal cannot be detected. To avoid such
output, pull up DO pin for improvement.
12/16
Pull up resistance Rpu and pull down resistance Rpd of DO pin
5) READY / BUSY status display (DO terminal) (common to BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W)
VILM IOLE
Rpu
5-0.4
2.1×10-3
VCC-VOLE
IOLE
. . .
Example) When Vcc = 5V, VOLE = 0.4V, IOLE = 2.1mA, VILM = 0.8V,
from the equation ,
VILM . . .
With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V
or below, and with VILM (= 0.8V), the equation is also satisfied.
Rpu ≥
Rpu ≥
VOLE ≤
Rpu ≥2.2 (K)
Microcontroller EEPROM
VOLE
"L" output
"L" input
Fig. 52 DO pull up resistance
Fig. 54 R/B status output timing chart
Fig. 53 DO pull down resistance
y VOLE : EEPROM VOL specifications
y IOLE : EEPROM IOL specifications
y VILM : Microcontroller VIL specifications
VIHM
5-0.2
0.1×10-3
Rpd ≥
VOHE
IOHE
. . .
Rpd ≥
VOHE ≥VIHM . . .
Rpd ≥48 (K)
Microcontroller
EEPROM
VOHE
"H" output
"H" input
y VOHE : EEPROM VOH specifications
y IOHE : EEPROM IOH specifications
y VIHM : Microcontroller VIH specifications
IOHE
Rpd
This display outputs the internal status signal. When CS is started after tCS (Min. 200ns)
from CS fall after write command input, "H" or "L" is output.
R/B display = "L" (BUSY) = write under execution
R/B display = "H" (READY) = command wait status
CS
SK
DI
DO High-Z READY
BUSY
tSV
CLOCK
STATUS
WRITE
INSTRUCTION
(D0 status)
(D0 status)
As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller
VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC.
Example) When Vcc = 5V, VOHE = Vcc - 0.2V, IOHE = 0.1mA, VIHM =
Vcc × 0.7V from the equation ,
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V
or below, and with VIHM (= 3.5V), the equation is also satisfied.
After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically.
And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted.
Even after tE/W (Max. 5ms) from write of the memory cell, the following command is accepted.
Therefore, CS = "H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI = "L" in
the area CS = "H". (Especially, in the case of shared input port, attention is required.)
* Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted. Therefore,
status READY output is cancelled, and malfunction and mistake write may be made.
13/16
6) When to directly connect DI and DO
Microcontroller EEPROM
DI / O PORT
DI
DO
R
(1) 1 clock cycle to take in A0 address data at read command
Dummy bit "0" is output to DO terminal.
→When address data A0 = "1" input, through current route occurs.
EEPROM CS input
EEPROM SK input
EEPROM DI input
EEPROM DO output
Microcontroller DI/O port
D13
D14
D15
Collision of DI input and DO output
Microcontroller input
High-Z
"H"
High-Z
Microcontroller output
A1 A0
A1 A0
0
Fig. 55 DI, DO control line common connection
Fig. 56 Collision timing at read data output at DI, DO direct connection
Fig. 57 Collision timing at DI, DO direct connection
Fig. 58 Start bit input timing at DI, DO direct connection
(1) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output.
When the next start bit input is recognized, "HIGH-Z" gets in.
→Especially, at command input after write, when CS input is started with microcontroller DI/O output "L",
READY output "H" is output from DO terminal, and through current route occurs.
EEPROM CS input
EEPROM SK input
EEPROM DI input
EEPROM DO output
Microcontroller DI/O port
Collision of DI input and DO output
Microcontroller input
High-Z
READY
Microcontroller output Microcontroller output
BUSY
READY
BUSY
Write command
Write command
Write command
Write command
Write command
READY
Note) As for the case (2), attention must be paid to the following.
DI
SK
CS
DO High-Z
READY
Start bit
This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart,
meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1
control line.
Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input
Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the
same time in the following points.
Feedback input at timing of these (1) and (2) does not cause disorder in basic operations, if resistance R is inserted.
When status READY is output, DO and DO are shared, DI = "H" and the microcontroller DI/O = "High-Z" or the microcontroller
DI/O = "H", if SK clock is input, DO output is input to DI and is recognized as a start bit, and malfunction may occur. As a
method to avoid malfunction, at status READY output, set SK = "L", or start CS within 4 clocks after "H" of READY signal is
output.
Because DI = "H", set
SK = "L" at CS rise.
14/16
Fig. 59 Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output)
Fig. 60 Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output)
Selection of resistance value R
(1) Address data A0 = "1" input, dummy bit "0" output timing
(When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI)
y Make the through current to EEPROM 10mA or below.
y See to it that the input level VIH of EEPROM should satisfy the following.
(2) DO status READY output timing
(When the microcontroller DI/O is "L", EEPROM DO outputs "H", and "L" is input to DI)
y Set the EEPROM input level VIL so as to satisfy the following.
VOHM
VOLE
DI/O PORT DI
IOHM R
At this moment, if VOLE = 0V,
VOHM IOHM × R + VOLE
≤
VOHM IOHM × R
≤
VOHM VIHE
≤
Microcontroller EEPROM
"H" output
"L" output
y VIHE : EEPROM VIH specifications
y VOLE : EEPROM VOL specifications
y VOHM : Microcontroller VOH specifications
y IOHM : Microcontroller IOH specifications
DO
Conditions
VOHM
IOHM
R≥. . .
VOHE
VOLM
DI/O PORT DI
IOHM R
At this moment, VOHE=VCC,
VOLM VOHE - IOLM × R
≥
VOLM VCC - IOLM × R
≥
VOLM VILE
≥
Microcontroller EEPROM
"H" output
"L" output
y VILE : EEPROM VIL specifications
y VOHE : EEPROM VOH specifications
y VOLM : Microcontroller VOL specifications
y IOLM : Microcontroller IOL specifications
DO VCC - VOLM
IOLM
R≥. . .
Example) When Vcc = 5V, VOHM = 5V, IOHM = 0.4mA, VOLM = 5V, IOLM = 0.4mA,
R ≥VOHM
IOHM
R ≥5
0.4×10-3
From the equation ,
. . .
R ≥12.5 [k]
R ≥VCC - VOLM
IOLM
R ≥5 - 0.4
2.1×10-3
From the equation ,
. . .
R ≥2.2 [k]
R ≥12.5 [k]
The resistance R becomes through current limit resistance at data collision. When through current flows, noises of
power source line and instantaneous stop of power source may occur. When allowable through current is defined as I,
the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so
forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL
even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence
upon basic operations.
Conditions
Therefore, from the equations and ,
Recommended conditions of tR, tOFF, Vbot
10ms or below
tRtOFF Vbot
100ms or below
0.3V or below
0.2V or below
10ms or higher
10ms or higher
15/16
7) Notes on power ON/OFF
8) Noise countermeasures
POR circuit
LVCC circuit
y At power ON/OFF, set CS "L".
Good example
Bad example
GND
VCC
GND
VCC
VCC
CS
Fig. 61 Timing at power ON/OFF
(Bad example) CS pin is pulled up to Vcc. (Good example) It is "L" at power ON/OFF.
1 Set CS = "L".
2 Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
tR
tOFF
Vbot
Fig. 62 Rise waveform diagram
VCC
0
Cautions on use
When CS is "H", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause
malfunction, mistake write or so. To prevent these, at power ON, set CS "L". (When CS is in "L" status, all inputs are cancelled.) And at
power decline, owing to power line capacity and so forth, low power status may continue long. At this case too, owing to the same
reason, malfunction, mistake write may occur, therefore, at power OFF too, set CS "L".
In this case, CS becomes "H" (active status), and EEPROM may have malfunction,
mistake write owing to noises and the likes.
Even when CS input is High-Z, the status becomes like this case, which please note.
Set 10ms or higher to recharge at power OFF.
When power is turned on without observing this condition, IC
internal circuit may not be reset, which please note.
This IC has a POR (Power On Reset) circuit as mistake write countermeasure.
After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF.
However, if CS is "H" at power ON/OFF, it may become write enable status owing to noises and the likes.
For secure actions, observe the following conditions.
LVCC (Vcc - Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. = 1.2V) or below, it prevent data rewrite.
Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach
a by pass capacitor (0.1µF) between IC Vcc and GND, At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
SK noise
When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit
displacement. To avoid this, a Schmitt trigger circuit is built in SK input. the hysteresis width of this circuit is set about 0.2V, if noises
exist at SK input, set the noise amplitude 0.2Vp-p or below.
And it is recommended to set the rise time (tR) of SK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient
noise countermeasures. Make the clock rise, fall time as small as possible.
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In
the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static
characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute Maximum Ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be
destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute
maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum
ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that of GND
terminal in consideration of transition status.
(5) Heat design
In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Selection of order type
BR
ROHM
type name
93
BUS type
93 : Microwire
L
Capacity
Microwire BUS
46=1K
56=2K
66=4K
76=8K
86=16K
46
Package type
F : SOP8
FJ : SOP-J8
RF : SOP8
RFJ : SOP-J8
FV : SSOP-B8
RFV : SSOP-B8
FVT : TSSOP-B8
RFVT : TSSOP-B8
RFVM : MSOP8
RFVJ : TSSOP-B8J
F
Double cell
W-
Taping type name
E2 : reel shape emboss taping
TR : reel shape emboss taping
(MSOP8 package only)
E2
Package specifications
Package type
Package quantity
Package direction
Emboss taping
3000pcs
TR
(When the reel is gripped by the left hand, and the tape is pulled out by
the right hand, No.1 pin of the product is at the right top.)
<External appearance>
* For ordering, specify a number of multiples of the package quantity.
<Package specifications>
MSOP8
Reel
Pin No.1 Pulling side
(Unit:mm)
<External appearance> <Package specifications>
* For ordering, specify a number of multiples of the package quantity.
Reel
Pin No.1 Pulling side
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J
1234
1234
1234
1234
1234
1234
1234
1234
Package type
Package quantity
Package direction
Emboss taping
2500pcs
E2
(When the reel is gripped by the left hand, and the tape is pulled
out by the right hand, No.1 pin of the product is at the left top.)
(Unit:mm)
Operating
temperature
Ｌ：−40℃〜＋85℃
A：−40℃〜＋105℃
H：−40℃〜＋125℃
41
58
2.9 ± 0.1
0.475
0.22
0.65
4.0 ± 0.2
0.6 ± 0.2
0.29 ± 0.15
2.8 ± 0.1
0.75 ± 0.05
0.08 ± 0.05
0.9Max.
0.08 S
+0.05
-
0.04
0.145
+0.05
-
0.03
0.08
M
• SOP-J8• SOP8 • SSOP-B8 • TSSOP-B8 • TSSOP-B8J
0.1
0.45Min.
0.42±0.1
4.9±0.2
85
4123
1.27
76
0.2±0.1
0.175 6.0±0.3
3.9±0.2
1.375±0.1
5
4
8
1
0.1
6.4±0.3
4.4
±
0.2
3.0±0.2
0.22±0.1
1.15±0.1
0.65
(0.52)
0.15±0.1
0.3Min.
0.1 0.08 S
5
4
8
1
0.1
±0.05
6.4
±0.2
4.4±0.1
3.0
±0.1
1.0
±0.1
0.65
+0.05
-
0.04
0.245
+0.05
-
0.03
0.145
0.5±0.15
1.0±0.2
0.08 S
+0.05
-
0.04
5
4
+0.05
-
0.03
8
1
0.1±0.05
4.9±0.2
3.0
±0.1
3.0±0.1
0.145
0.85±0.05
0.65
0.45±0.15
0.95±0.2
0.32
0.3Min.
0.42±0.1
0.11 6.2±0.3
4.4±0.2
5.0±0.2
85
41
1.27
1.5±0.1
0.1
0.17
+0.1
-
0.05
Catalog No. 05T816Ae '05.10 ROHM© 2000 TSU
The contents described herein are correct as of October, 2005
The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.
Any part of this application note must not be duplicated or copied without our permission.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding
upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any
warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such
infringement, or arising from or connected with or related to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other
proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.
The products described herein utilize silicon as the main material.
The products described herein are not designed to be X ray proof.
Published by
Application Engineering Group
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
Appendix1-Rev2.0
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Copyright © 2007 ROHM CO.,LTD.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121
FAX : +81-75-315-0172
Appendix