74AC74SCQR - National Semiconductor

TL/F/9920

54AC/74AC74 #54ACT/74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

February 1993

54AC/74AC74 #54ACT/74ACT74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The ’AC/’ACT74 is a dual D-type flip-flop with Asynchro-

nous Clear and Set inputs and complementary (Q, Q) out-

puts. Information at the input is transferred to the outputs on

the positive edge of the clock pulse. Clock triggering occurs

at a voltage level of the clock pulse and is not directly relat-

ed to the transition time of the positive-going pulse. After

the Clock Pulse input threshold voltage has been passed,

the Data input is locked out and information present will not

be transferred to the outputs until the next rising edge of the

Clock Pulse input.

Asynchronous Inputs:

LOW input to SD(Set) sets Q to HIGH level

LOW input to CD(Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CDand SDmakes both Q and Q

HIGH

Features

YICC reduced by 50%

YOutput source/sink 24 mA

Y’ACT74 has TTL-compatible inputs

YStandard Military Drawing (SMD)

Ð ’AC74: 5962-88520

Ð ’ACT74: 5962-87525

Logic Symbols

TL/F/9920–1

IEEE/IEC

TL/F/9920–3

Pin Names Description

D1,D

2Data Inputs

CP1,CP

2Clock Pulse Inputs

CD1,C

D2 Direct Clear Inputs

SD1,S

D2 Direct Set Inputs

Q1,Q

2Outputs

TL/F/9920–2

Connection Diagrams

Pin Assignment

for DIP, Flatpak and SOIC

TL/F/9920–4

Pin Assignment for LCC

TL/F/9920–5

FACTTM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Truth Table (Each Half)

Inputs Outputs

SDCDCP D Q Q

LH XXHL

HL XXLH

LL XXHH

HHLHH L

HHLLL H

HH LXQ

HIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

LeLOW-to-HIGH Clock Transition

Q0(Q0)ePrevious Q(Q) before LOW-to-HIGH Transition of Clock

Logic Diagram

TL/F/9920–6

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Rating (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)b0.5V to a7.0V

DC Input Diode Current (IIK)

VIeb

0.5V b20 mA

VIeVCC a0.5V a20 mA

DC Input Voltage (VI)b0.5V to VCC a0.5V

DC Output Diode Current (IOK)

VOeb

0.5V b20 mA

VOeVCC a0.5V a20 mA

DC Output Voltage (VO)b0.5V to VCC a0.5V

DC Output Source

or Sink Current (IO)g50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)g50 mA

Storage Temperature (TSTG)b65§Ctoa

150§C

Junction Temperature (TJ)

CDIP 175§C

PDIP 140§C

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of FACTTM circuits outside databook specifications.

Recommended Operating

Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V

’ACT 4.5V to 5.5V

Input Voltage (VI) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

74AC/ACT b40§Ctoa

85§C

54AC/ACT b55§Ctoa

125§C

Minimum Input Edge Rate (DV/Dt)

’AC Devices

VIN from 30% to 70% of VCC

VCC @3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (DV/Dt)

’ACT Devices

VIN from 0.8V to 2.0V

VCC @4.5V, 5.5V 125 mV/ns

DC Characteristics for ’AC Family Devices

74AC 54AC 74AC

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 3.0 1.5 2.1 2.1 2.1 VOUT e0.1V

Input Voltage 4.5 2.25 3.15 3.15 3.15 V or VCC b0.1V

5.5 2.75 3.85 3.85 3.85

VIL Maximum Low Level 3.0 1.5 0.9 0.9 0.9 VOUT e0.1V

Input Voltage 4.5 2.25 1.35 1.35 1.35 V or VCC b0.1V

5.5 2.75 1.65 1.65 1.65

VOH Minimum High Level 3.0 2.99 2.9 2.9 2.9 IOUT eb

50 mA

Output Voltage 4.5 4.49 4.4 4.4 4.4 V

5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

3.0 2.56 2.4 2.46 b12 mA

4.5 3.86 3.7 3.76 V IOH b24 mA

5.5 4.86 4.7 4.76 b24 mA

VOL Maximum Low Level 3.0 0.002 0.1 0.1 0.1 IOUT e50 mA

Output Voltage 4.5 0.001 0.1 0.1 0.1 V

5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

3.0 0.36 0.5 0.44 12 mA

4.5 0.36 0.5 0.44 V IOL 24 mA

5.5 0.36 0.5 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAVIeVCC, GND

Leakage Current

*All outputs loaded; thresholds on input associated with output under test.

DC Characteristics for ’AC Family Devices (Continued)

74AC 54AC 74AC

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 2.0 40.0 20.0 mAVIN eVCC

Supply Current or GND

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.

ICC for 54AC @25§C is identical to 74AC @25§C.

DC Characteristics for ’ACT Family Devices

74ACT 54ACT 74ACT

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 4.5 1.5 2.0 2.0 2.0 VVOUT e0.1V

Input Voltage 5.5 1.5 2.0 2.0 2.0 or VCC b0.1V

VIL Maximum Low Level 4.5 1.5 0.8 0.8 0.8 VVOUT e0.1V

Input Voltage 5.5 1.5 0.8 0.8 0.8 or VCC b0.1V

VOH Minimum High Level 4.5 4.49 4.4 4.4 4.4 VIOUT eb

50 mA

Output Voltage 5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

4.5 3.86 3.70 3.76 VI

b24 mA

5.5 4.86 4.70 4.76 b24 mA

VOL Maximum Low Level 4.5 0.001 0.1 0.1 0.1 VIOUT e50 mA

Output Voltage 5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

4.5 0.36 0.50 0.44 VI

24 mA

5.5 0.36 0.50 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAVIeVCC, GND

Leakage Current

ICCT Maximum 5.5 0.6 1.6 1.5 mA VIeVCC b2.1V

ICC/Input

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 2.0 40.0 20.0 mAVIN eVCC

Supply Current or GND

*All outputs loaded; thresholds on input associated with output under test.

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: ICC for 54ACT @25§C is identical to 74ACT @25§C.

AC Electrical Characteristics

74AC 54AC 74AC

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Clock 3.3 100 125 70 95 MHz

Frequency 5.0 140 160 95 125

tPLH Propagation Delay 3.3 3.5 8.0 12.0 1.0 13.0 2.5 13.0 ns

CDn or SDn to Qnor Qn5.0 2.5 6.0 9.0 1.0 9.5 2.0 10.0

tPHL Propagation Delay 3.3 4.0 10.5 12.0 1.0 14.0 3.5 13.5 ns

CDn or SDn to Qnor Qn5.0 3.0 8.0 9.5 1.0 10.5 2.5 10.5

tPLH Propagation Delay 3.3 4.5 8.0 13.5 1.0 17.5 4.0 16.0 ns

CPnto Qnor Qn5.0 3.5 6.0 10.0 1.0 12.0 3.0 10.5

tPHL Propagation Delay 3.3 3.5 8.0 14.0 1.0 13.5 3.5 14.5 ns

CPnto Qnor Qn5.0 2.5 6.0 10.0 1.0 10.0 2.5 10.5

*Voltage Range 3.3 is 3.3V g0.3V

Voltage Range 5.0 is 5.0V g0.5V

AC Operating Requirements

74AC 54AC 74AC

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Typ Guaranteed Minimum

tsSet-up Time, HIGH or LOW 3.3 1.5 4.0 5.0 4.5 ns

Dnto CPn5.0 1.0 3.0 4.0 3.0

thHold Time, HIGH or LOW 3.3 b2.0 0.5 0.5 0.5 ns

Dnto CPn5.0 b1.5 0.5 0.5 0.5

twCPnor CDn or SDn 3.3 3.0 5.5 8.0 7.0 ns

Pulse Width 5.0 2.5 4.5 5.5 5.0

trec Recovery Time 3.3 b2.5 0 0.5 0 ns

CDn or SDn to CP 5.0 b2.0 0 0.5 0

*Voltage Range 3.3 is 3.3V g0.3V

Voltage Range 5.0 is 5.0V g0.5V

AC Electrical Characteristics

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Clock 5.0 145 210 85 125 MHz

Frequency

tPLH Propagation Delay 5.0 3.0 5.5 9.5 1.0 11.5 2.5 10.5 ns

CDn or SDn to Qnor Qn

tPHL Propagation Delay 5.0 3.0 6.0 10.0 1.0 12.5 3.0 11.5 ns

CDn or SDn to Qnor Qn

tPLH Propagation Delay 5.0 4.0 7.5 11.0 1.0 14.0 4.0 13.0. ns

CPnto Qnor Qn

tPHL Propagation Delay 5.0 3.5 6.0 10.0 1.0 12.0 3.0 11.5 ns

CPnto Qnor Qn

*Voltage Range 5.0 is 5.0V g0.5V

AC Operating Requirements

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Typ Guaranteed Minimum

tsSet-up Time, HIGH or LOW 5.0 1.0 3.0 4.0 3.5 ns

Dnto CPn

thHold Time, HIGH or LOW 5.0 b0.5 1.0 1.0 1.0 ns

Dnto CPn

twCPnor CDn or SDn 5.0 3.0 5.0 7.0 6.0 ns

Pulse Width

trec Recovery Time 5.0 b2.5 0 0.5 0 ns

CDn or SDn to CP

*Voltage Range 5.0 is 5.0V g0.5V

Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC eOPEN

CPD Power Dissipation 35.0 pF VCC e5.0V

Capacitance

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74AC 74 P C QR

Temperature Range Family Special Variations

74AC eCommercial X eDevices shipped in 13×reels

54AC eMilitary QR eCommercial grade device

74ACT eCommercial TTL-Compatible with burn-in

54ACT eMilitary TTL-Compatible QB eMilitary grade device with

environmental and burn-in

Device Type processing shipped in tubes

Package Code Temperature Range

PePlastic DIP CeCommercial (b40§Ctoa

85§C)

DeCeramic DIP MeMilitary (b55§Ctoa

125§C)

FeFlatpak

LeLeadless Ceramic Chip Carrier (LCC)

SeSmall Outline (SOIC)

Physical Dimensions inches (millimeters)

20 Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

14 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J14A

Physical Dimensions inches (millimeters) (Continued)

14 Lead Small Outline Integrated Circuit (S)

NS Package Number M14A

14 Lead Plastic Dual-In-Line Package (P)

NS Package Number N14A

54AC/74AC74 #54ACT/74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions inches (millimeters) (Continued)

14 Lead Ceramic Flatpak (F)

NS Package Number W14B

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SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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