Freescale Semiconductor Data Sheet: Technical Data K70 Sub-Family Document Number K70P256M150SF3 Rev. 6, 09/2015 K70P256M150SF3 Supports the following: MK70FX512VMJ15, MK70FN1M0VMJ15 Key features * Operating Characteristics - Voltage range: 1.71 to 3.6 V - Flash write voltage range: 1.71 to 3.6 V - Temperature range (ambient): -40 to 105C * Performance - Up to 150 MHz ARM(R) Cortex(R)-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz * Memories and memory interfaces - Up to 1024 KB program flash memory on nonFlexMemory devices - Up to 512 KB program flash memory on FlexMemory devices - Up to 512 KB FlexNVM on FlexMemory devices - 16 KB FlexRAM on FlexMemory devices - Up to 128 KB RAM - Serial programming interface (EzPort) - FlexBus external bus interface - DDR controller interface - NAND flash controller interface * Clocks - 3 to 32 MHz crystal oscillator - 32 kHz crystal oscillator - Multi-purpose clock generator * System peripherals - Multiple low-power modes to provide power optimization based on application requirements - Memory protection unit with multi-master protection - 32-channel DMA controller, supporting up to 128 request sources - External watchdog monitor - Software watchdog - Low-leakage wakeup unit * Security and integrity modules - Hardware CRC module to support fast cyclic redundancy checks - Tamper detect and secure storage - Hardware random-number generator - Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms - 128-bit unique identification (ID) number per chip * Human-machine interface - Graphic LCD controller - Low-power hardware touch sensor interface (TSI) - General-purpose input/output * Analog modules - Four 16-bit SAR ADCs - Programmable gain amplifier (PGA) (up to x64) integrated into each ADC - Two 12-bit DACs - Four analog comparators (CMP) containing a 6bit DAC and programmable reference input - Voltage reference * Timers - Programmable delay block - Two 8-channel motor control/general purpose/PWM timers - Two 2-channel quadrature decoder/general purpose timers - IEEE 1588 timers - Periodic interrupt timers - 16-bit low-power timer - Carrier modulator transmitter - Real-time clock Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) 2012-2015 Freescale Semiconductor, Inc. * Communication interfaces - Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability - USB high-/full-/low-speed On-the-Go controller with ULPI interface - USB full-/low-speed On-the-Go controller with on-chip transceiver - USB Device Charger detect (USBDCD) - Two Controller Area Network (CAN) modules - Three SPI modules - Two I2C modules - Six UART modules - Secure Digital Host Controller (SDHC) - Two I2S modules K70 Sub-Family, Rev.6, 09/2015. 2 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts........................................................................... 5 6.1.2 JTAG electricals..................................................26 1.1 Determining valid orderable parts......................................5 6.2 System modules................................................................ 29 2 Part identification...................................................................... 5 6.3 Clock modules................................................................... 29 2.1 Description.........................................................................5 6.3.1 MCG specifications.............................................29 2.2 Format............................................................................... 5 6.3.2 Oscillator electrical specifications....................... 32 2.3 Fields................................................................................. 5 6.3.3 32 kHz oscillator electrical characteristics.......... 34 2.4 Example............................................................................ 6 6.4 Memories and memory interfaces..................................... 34 3 Terminology and guidelines...................................................... 6 6.4.1 Flash (FTFE) electrical specifications.................34 3.1 Definitions..........................................................................6 6.4.2 EzPort switching specifications...........................39 3.2 Examples...........................................................................6 6.4.3 NFC specifications..............................................40 3.3 Typical-value conditions.................................................... 7 6.4.4 DDR controller specifications..............................43 3.4 Relationship between ratings and operating 6.4.5 Flexbus switching specifications.........................46 requirements......................................................................7 3.5 Guidelines for ratings and operating requirements............8 4 Ratings...................................................................................... 8 6.5 Security and integrity modules.......................................... 48 6.5.1 DryIce Tamper Electrical Specifications............. 48 6.6 Analog............................................................................... 49 4.1 Thermal handling ratings................................................... 8 6.6.1 ADC electrical specifications.............................. 49 4.2 Moisture handling ratings.................................................. 9 6.6.2 CMP and 6-bit DAC electrical specifications...... 56 4.3 ESD handling ratings.........................................................9 6.6.3 12-bit DAC electrical characteristics................... 58 4.4 Voltage and current operating ratings............................... 9 6.6.4 Voltage reference electrical specifications..........61 5 General..................................................................................... 10 6.7 Timers................................................................................62 5.1 AC electrical characteristics.............................................. 10 6.8 Communication interfaces................................................. 62 5.2 Nonswitching electrical specifications............................... 10 6.8.1 Ethernet switching specifications........................62 5.2.1 Voltage and current operating requirements...... 10 6.8.2 USB electrical specifications...............................64 5.2.2 LVD and POR operating requirements............... 12 6.8.3 USB DCD electrical specifications......................65 5.2.3 Voltage and current operating behaviors............13 6.8.4 USB VREG electrical specifications................... 65 5.2.4 Power mode transition operating behaviors....... 16 6.8.5 ULPI timing specifications...................................66 5.2.5 Power consumption operating behaviors............17 6.8.6 CAN switching specifications..............................67 5.2.6 EMC radiated emissions operating behaviors.... 20 6.8.7 DSPI switching specifications (limited voltage 5.2.7 Designing with radiated emissions in mind.........21 5.2.8 Capacitance attributes........................................ 21 range)................................................................. 67 6.8.8 5.3 Switching specifications.....................................................21 DSPI switching specifications (full voltage range)................................................................. 68 5.3.1 Device clock specifications................................. 21 6.8.9 Inter-Integrated Circuit Interface (I2C) timing..... 70 5.3.2 General switching specifications.........................22 6.8.10 UART switching specifications............................71 5.4 Thermal specifications.......................................................24 6.8.11 SDHC specifications........................................... 71 6.8.12 I2S/SAI switching specifications......................... 72 5.4.1 Thermal operating requirements.........................24 5.4.2 Thermal attributes...............................................24 6.9 Human-machine interfaces (HMI)......................................79 5.5 Power sequencing............................................................. 25 6.9.1 TSI electrical specifications................................ 79 6 Peripheral operating requirements and behaviors.................... 26 6.9.2 LCDC electrical specifications............................ 80 6.1 Core modules.................................................................... 26 6.1.1 Debug trace timing specifications....................... 26 7 Dimensions............................................................................... 83 7.1 Obtaining package dimensions......................................... 83 K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 3 8 Pinout........................................................................................ 83 8.3 K70 Pinouts....................................................................... 93 8.1 Pins with active pull control after reset.............................. 83 9 Revision History........................................................................ 94 8.2 K70 Signal Multiplexing and Pin Assignments.................. 83 K70 Sub-Family, Rev.6, 09/2015. 4 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK70 and MK70 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification K## Kinetis family * K70 A Key attribute * F = Cortex-M4 w/ DSP and FPU M Flash memory type * N = Program flash only * X = Program flash and FlexMemory FFF Program flash memory size * 512 = 512 KB * 1M0 = 1 MB Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 5 Terminology and guidelines Field Description Values T Temperature range (C) * V = -40 to 105 * C = -40 to 85 PP Package identifier * MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) * 15 = 150 MHz N Packaging type * R = Tape and reel * (Blank) = Trays 2.4 Example This is an example part number: MK70FN1M0VMJ15 3 Terminology and guidelines 3.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. K70 Sub-Family, Rev.6, 09/2015. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.2 Examples EX A M PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 3.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 C VDD 3.3 V supply voltage 3.3 V K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 7 Ratings 3.4 Relationship between ratings and operating requirements e Op ing rat r ( ng ati n. mi ) ing rat e Op e re ir qu ) in. t (m n me ing rat e Op e ir qu re t (m n me ax .) ing rat e Op (m ng ati .) ax r Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) ng dli n Ha n.) mi g( in rat ma g( ng dli n Ha in rat x.) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 3.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. K70 Sub-Family, Rev.6, 09/2015. 8 Freescale Semiconductor, Inc. Ratings 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.4 Voltage and current operating ratings Symbol Description Min. Max. Unit Digital supply voltage1 -0.3 3.8 V VDD_INT Core supply voltage -0.3 3.8 V VDD_DDR DDR I/O supply voltage -0.3 3.8 V Digital supply current -- 300 mA IDD_INT Core supply current -- 185 mA IDD_DDR DDR supply current -- 220 mA Digital input voltage (except RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1) 2 -0.3 5.5 V DDR input voltage -0.3 VDD_DDR + 0.3 V Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input voltage -0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) -25 25 mA VDD - 0.3 VDD + 0.3 V VDD IDD VDIO VDDDR VAIO ID VDDA Analog supply voltage VUSB0_DP USB0_DP input voltage -0.3 3.63 V VUSB1_DP USB1_DP input voltage -0.3 3.63 V Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 9 General Symbol Description Min. Max. Unit VUSB0_DM USB0_DM input voltage -0.3 3.63 V VUSB1_DM USB1_DM input voltage -0.3 3.63 V VREGIN USB regulator input -0.3 6.0 V RTC battery supply voltage -0.3 3.8 V VBAT 1. It applies for all port pins except Tamper pins. 2. It covers digital pins except Tamper pins and DDR pins. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins * have CL=30pF loads, * are configured for fast slew rate (PORTx_PCRn[SRE]=0), and * are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins * have their passive filter disabled (PORTx_PCRn[PFE]=0) 5.2 Nonswitching electrical specifications K70 Sub-Family, Rev.6, 09/2015. 10 Freescale Semiconductor, Inc. General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage max [VDD_DDR, 1.71 V] 3.6 V 1.71 VDD V * DDR1 2.3 2.7 V * DDR2/LPDDR1 1.71 1.9 V 0.49 x VDD_DDR VDD_DDR V 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V 1.71 3.6 V 0.7 x VDD -- V 0.75 x VDD -- V -- 0.35 x VDD V -- 0.3 x VDD V VREF_DDR + 0.15 -- V VREF_DDR + 0.125 -- V 0.7 x VDD_DDR -- V -- VREF_DDR - 0.15 V -- VREF_DDR - 0.125 V VDD_INT Core supply voltage VDD_DDR DDR voltage -- memory I/O buffers VREF_DDR VDDA VBAT VIH Input reference voltage (DDR1/DDR2/ LPDDR1) Analog supply voltage RTC battery supply voltage Input high voltage (digital pins except Tamper pins and DDR pins) * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VIL Input low voltage (digital pins except Tamper pins and DDR pins) * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VIH_DDR Input high voltage (DDR pins) * DDR1 * DDR2 * LPDDR1 VIL_DDR Input low voltage (DDR pins) * DDR1 * DDR2 * LPDDR1 VHYS Input hysteresis (digital pins except Tamper pins and DDR pins) IICDIO Digital pin (except Tamper pins) negative DC injection current -- single pin -- 0.3 x VDD_DDR V 0.06 x VDD -- V -5 -- mA Notes 1 2 * VIN < VSS-0.3V IICAIO Analog3, EXTAL0/XTAL0, and EXTAL1/ XTAL1 pin DC injection current -- single pin * VIN < VSS-0.3V (Negative current injection) * VIN > VDD+0.3V (Positive current injection) 4 mA -5 -- -- +5 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 11 General Table 1. Voltage and current operating requirements (continued) Symbol IICcont Description Contiguous pin DC injection current -- regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins * Negative current injection Min. Max. -25 -- -- +25 Unit Notes mA * Positive current injection VODPU Open drain pullup voltage level VDD VDD V VRAM VDD (VDD_INT) voltage required to retain RAM 1.2 -- V VPOR_VBAT -- V VRFVBAT VBAT voltage required to retain the VBAT register file 5 1. For DDR1/DDR2, connect VREF_DDR to the same reference voltage used for the memory. For LPDDR1, connect VREF_DDR to the VDD_DDR voltage. 2. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 4. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 5. Open drain outputs must be pulled to VDD. 5.2.2 LVD and POR operating requirements Table 2. LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold -- high range (LVDV=01) 2.48 2.56 2.64 V 2.62 2.70 2.78 V 2.72 2.80 2.88 V 2.82 2.90 2.98 V 2.92 3.00 3.08 V -- 80 -- mV 1.54 1.60 1.66 V 1.74 1.80 1.86 V 1.84 1.90 1.96 V VLVW1H VLVW2H VLVW3H VLVW4H Low-voltage warning thresholds -- high range * Level 1 falling (LVWV=00) * Level 2 falling (LVWV=01) * Level 3 falling (LVWV=10) Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) VLVW2L 1 * Level 4 falling (LVWV=11) VHYSH VLVW1L Notes Low-voltage warning thresholds -- low range * Level 1 falling (LVWV=00) 1 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 12 Freescale Semiconductor, Inc. General Table 2. LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit VLVW3L * Level 2 falling (LVWV=01) 1.94 2.00 2.06 V VLVW4L * Level 3 falling (LVWV=10) 2.04 2.10 2.16 V -- 60 -- mV Notes * Level 4 falling (LVWV=11) VHYSL Low-voltage inhibit reset/recover hysteresis -- low range VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period 900 1000 1100 s factory trimmed 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol Min. Typ. * 2.7 V VDD 3.6 V, IOH = -9mA VDD - 0.5 -- * 1.71 V VDD 2.7 V, IOH = -3mA VDD - 0.5 -- * 2.7 V VDD 3.6 V, IOH = -2mA VDD - 0.5 -- * 1.71 V VDD 2.7 V, IOH = -0.6mA VDD - 0.5 -- Output high current total for all ports -- -- 100 mA IOHT_io60 Output high current total for fast digital ports -- -- 100 mA VOH_DDR Output high voltage for DDR pins VDD_DDR 0.36 -- -- V -- -- V -- -- V -- -- V -- -- V VOH Description Output high voltage -- high drive strength * DDR1 (IOH = -16.2 mA) * DDR2 half strength (IOH = -5.36 mA) * DDR2 full strength (IOH = -13.4 mA) * LPDDR1 half strength (IOH = -0.1 mA) * LPDDR1 full strength (IOH = -0.1 mA) Unit Notes -- Output high voltage -- low drive strength IOHT Max. -- V V -- VDD_DDR 0.28 VDD_DDR 0.28 -- V V 0.9 x VDD_DDR 0.9 x VDD_DDR Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 13 General Table 4. Voltage and current operating behaviors (continued) Symbol Description IOHT_DDR Output high current total for DDR pins * DDR1 * DDR2 Min. Typ. Max. Unit -- -- 100 mA -- -- 56 mA -- -- 39 mA VBAT - 0.5 -- -- V VBAT - 0.5 -- -- V VBAT - 0.5 -- -- V VBAT - 0.5 -- -- V -- -- 100 mA 0.5 V 0.5 V 0.5 V 0.5 V Notes * LPDDR1 VOH_Tamper Output high voltage -- high drive strength * 2.7 V VBAT 3.6 V, IOH = -10mA * 1.71 V VBAT 2.7 V, IOH = -3mA Output high voltage -- low drive strength * 2.7 V VBAT 3.6 V, IOH = -2mA * 1.71 V VBAT 2.7 V, IOH = -0.6mA IOH_Tamper Output high current total for Tamper pins VOL Output low voltage -- high drive strength -- * 2.7 V VDD 3.6 V, IOL = 10 mA -- * 1.71 V VDD 2.7 V, IOL = 5 mA -- Output low voltage -- low drive strength IOLT -- -- * 2.7 V VDD 3.6 V, IOL = 2 mA -- * 1.71 V VDD 2.7 V, IOL = 1 mA -- -- Output low current total for all ports -- -- 100 mA IOLT_io60 Output low current total for fast digital ports -- -- 100 mA VOL_DDR Output low voltage for DDR pins -- -- 0.37 V * DDR1 (IOL = 16.2 mA) -- -- 0.28 V * DDR2 half strength (IOL = 5.36 mA) -- -- 0.28 V * DDR2 full strength (IOL = 13.4 mA) -- -- -- -- 0.1 x VDD_DDR V * LPDDR1 half strength (IOL = 0.1 mA) * LPDDR1 full strength (IOL = 0.1 mA) IOLT_DDR Output low current total for DDR pins V 0.1 x VDD_DDR -- -- * DDR1 * DDR2 100 mA 56 mA 39 mA * LPDDR1 VOL_Tamper Output low voltage -- high drive strength * 2.7 V VBAT 3.6 V, IOL = 10mA -- -- 0.5 V -- -- 0.5 V -- -- 0.5 V -- -- 0.5 V * 1.71 V VBAT 2.7 V, IOL = 3mA Output low voltage -- low drive strength * 2.7 V VBAT 3.6 V, IOL = 2mA * 1.71 V VBAT 2.7 V, IOL = 0.6mA Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 14 Freescale Semiconductor, Inc. General Table 4. Voltage and current operating behaviors (continued) Symbol Description IOL_Tamper Output low current total for Tamper pins IINA Min. Typ. Max. Unit -- -- 100 mA Notes 1, 2 Input leakage current, analog pins and digital pins configured as analog inputs * VSS VIN VDD * All pins except EXTAL32, XTAL32, EXTAL, XTAL * EXTAL (PTA18) and XTAL (PTA19) * EXTAL32, XTAL32 IIND -- 0.002 0.5 A -- 0.004 1.5 A -- 0.075 10 A Input leakage current, digital pins 2, 3 * VSS VIN VIL * All digital pins -- 0.002 0.5 A -- 0.002 0.5 A -- 0.004 1 A * VIN = VDD * All digital pins except PTD7 * PTD7 IIND 2, 3, Input leakage current, digital pins 4 * VIL < VIN < VDD IIND * VDD = 3.6 V -- 18 26 A * VDD = 3.0 V -- 12 19 A * VDD = 2.5 V -- 8 13 A * VDD = 1.7 V -- 3 6 A Input leakage current, digital pins * VDD < VIN < 5.5 V ZIND 2, 3 -- 1 50 A 2, Input impedance examples, digital pins * VDD = 3.6 V -- -- 48 k * VDD = 3.0 V -- -- 55 k * VDD = 2.5 V -- -- 57 k * VDD = 1.7 V -- -- 85 k IIN_DDR Input leakage current (per DDR pin) for full temperature range -- -- 1 A IIN_DDR Input leakage current (per DDR pin) at 25C -- -- 0.025 A IIN_Tamper Input leakage current (per Tamper pin) for full temperature range -- -- 1 A IIN_Tamper 5 Input leakage current (per Tamper pin) at 25C -- -- 0.025 A RPU Internal pullup resistors (except Tamper pins) 20 -- 50 k 6 RPD Internal pulldown resistors (except Tamper pins) 20 -- 50 k 7 RODT On-die termination (ODT) resistance for DDR2 60 -- 90 120 -- 180 * Rtt1(eff) - 75 * Rtt2(eff) - 150 K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 15 General 1. 2. 3. 4. 5. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. Internal pull-up/pull-down resistors disabled. Characterized, not tested in production. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See Figure 2. 6. Measured at VDD supply voltage = VDD min and Vinput = VSS 7. Measured at VDD supply voltage = VDD min and Vinput = VDD Figure 2. 5 V Tolerant Input IIND Parameter 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSxRUN recovery times in the following table assume this clock configuration: * * * * * CPU and system clocks = 100 MHz Bus clock = 50 MHz FlexBus clock = 50 MHz Flash clock = 25 MHz MCG mode: FEI Table 5. Power mode transition operating behaviors Symbol tPOR Description Min. Max. Unit After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. * VDD slew rate 5.7 kV/s * VDD slew rate < 5.7 kV/s * VLLS1 RUN * VLLS2 RUN Notes 1 s -- 300 -- 1.7 V / (VDD slew rate) -- 160 s -- 114 s Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 16 Freescale Semiconductor, Inc. General Table 5. Power mode transition operating behaviors (continued) Symbol Description * VLLS3 RUN * LLS RUN * VLPS RUN * STOP RUN Min. Max. Unit -- 114 s -- 5.0 s -- 5 s -- 4.8 s Notes 1. Normal boot (FTFE_FOPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN IDD_RUN Description Analog supply current Min. Typ. Max. Unit Notes -- -- See note mA 1 Run mode current -- all peripheral clocks disabled, code executing from flash 2 * @ 1.8V -- 58.01 83.95 mA * @ 3.0V -- 57.93 84.14 mA Run mode current -- all peripheral clocks enabled, code executing from flash 3 * @ 1.8V -- 89.26 116.53 mA * @ 3.0V -- 89.23 117.26 mA IDD_WAIT Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled -- 40.18 65.25 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V -- all peripheral clocks disabled -- 18.08 42.96 mA 4 IDD_STOP Stop mode current at 3.0 V * @ -40 to 25C -- 1.25 1.62 mA * @ 70C -- 2.93 4.39 mA * @ 105C -- 7.08 10.74 mA IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled -- 1.03 4.48 mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled -- 1.58 4.96 mA 5 IDD_VLPW Very-low-power wait mode current at 3.0 V -- 0.64 4.29 mA 5 IDD_VLPS Very-low-power stop mode current at 3.0 V -- 0.22 0.38 mA -- 0.78 1.33 mA * @ -40 to 25C Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 17 General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 2.18 3.56 mA * @ -40 to 25C -- 0.22 0.37 mA * @ 70C -- 0.78 1.33 mA * @ 105C -- 2.16 3.52 mA * @ -40 to 25C -- 4.09 5.58 A * @ 70C -- 20.98 28.93 A * @ 105C -- 84.95 111.15 A * @ -40 to 25C -- 2.68 4.22 A * @ 70C -- 8.8 10.74 A * @ 105C -- 37.28 43.61 A * @ -40 to 25C -- 2.46 4.02 A * @ 70C -- 7.04 8.99 A * @ 105C -- 30.68 37.04 A * @ 70C Notes * @ 105C IDD_LLS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VBAT Low leakage stop mode current at 3.0 V Very low-leakage stop mode 3 current at 3.0 V Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current when CPU is not accessing RTC registers at 3.0 V 6 * @ -40 to 25C -- 0.89 1.10 A * @ 70C -- 1.28 1.85 A * @ 105C -- 3.10 4.30 A 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 6. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies. K70 Sub-Family, Rev.6, 09/2015. 18 Freescale Semiconductor, Inc. General * * * * USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFE Figure 3. Run mode supply current vs. core frequency K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 19 General Figure 4. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 256MAPBGA Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2, 3 VRE1 Radiated emissions voltage, band 1 0.15-50 21 dBV VRE2 Radiated emissions voltage, band 2 50-150 24 dBV VRE3 Radiated emissions voltage, band 3 150-500 29 dBV VRE4 Radiated emissions voltage, band 4 500-1000 28 dBV 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 C, fOSC = 12 MHz (crystal), fSYS = 72 MHz, fBUS = 72 MHz 3. Determined according to IEC Standard JESD78, IC Latch-Up Test K70 Sub-Family, Rev.6, 09/2015. 20 Freescale Semiconductor, Inc. General 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for "EMC design." 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins -- 7 pF CIN_D Input capacitance: digital pins -- 7 pF Input capacitance: fast digital pins -- 9 pF CIN_D_io60 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit System and core clock -- 150 MHz fSYS_USBFS System and core clock when Full Speed USB in operation 20 -- MHz fSYS_USBHS System and core clock when High Speed USB in operation 60 -- MHz fENET System and core clock when ethernet in operation Notes Normal run mode fSYS * 10 Mbps * 100 Mbps MHz 5 -- 50 -- Bus clock -- 75 MHz FlexBus clock -- 50 MHz fFLASH Flash clock -- 25 MHz fDDR DDR clock -- 150 MHz -- 25 MHz fBUS FB_CLK fLPTMR LPTMR clock VLPR mode1 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 21 General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit fSYS System and core clock -- 4 MHz fBUS Bus clock -- 4 MHz FlexBus clock -- 4 MHz fFLASH Flash clock -- 0.5 MHz fLPTMR LPTMR clock -- 4 MHz FB_CLK Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General switching specifications These general purpose specifications apply to all pins configured for: * GPIO signaling * Other peripheral module signaling not explicitly stated elsewhere Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) -- Asynchronous path 100 -- ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) -- Asynchronous path 16 -- ns 3 External reset pulse width (digital glitch filter disabled) 100 -- ns 3 2 -- Bus clock cycles Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) 4 * Slew disabled * 1.71 VDD 2.7V -- 14 ns * 2.7 VDD 3.6V -- 8 ns * 1.71 VDD 2.7V -- 36 ns * 2.7 VDD 3.6V -- 24 ns * Slew enabled Port rise and fall time (low drive strength) 5 * Slew disabled * 1.71 VDD 2.7V -- 14 ns * 2.7 VDD 3.6V -- 8 ns -- 36 ns * Slew enabled Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 22 Freescale Semiconductor, Inc. General Table 10. General switching specifications (continued) Symbol Description * 1.71 VDD 2.7V Min. Max. Unit -- 24 ns Notes * 2.7 VDD 3.6V tio50 6 Port rise and fall time (high drive strength) * Slew disabled * 1.71 VDD 2.7V -- 7 ns -- * 2.7 VDD 3.6V -- 3 ns -- * 1.71 VDD 2.7V -- 28 ns -- * 2.7 VDD 3.6V -- 14 ns -- * Slew enabled tio50 7 Port rise and fall time (low drive strength) * Slew disabled * 1.71 VDD 2.7V -- 18 ns -- * 2.7 VDD 3.6V -- 9 ns -- * 1.71 VDD 2.7V -- 48 ns -- * 2.7 VDD 3.6V -- 24 ns -- * Slew enabled tio60 6 Port rise and fall time (high drive strength) * Slew disabled * 1.71 VDD 2.7V -- 6 ns -- * 2.7 VDD 3.6V -- 3 ns -- * 1.71 VDD 2.7V -- 28 ns -- * 2.7 VDD 3.6V -- 14 ns -- * Slew enabled tio60 7 Port rise and fall time (low drive strength) * Slew disabled * 1.71 VDD 2.7V -- 18 ns -- * 2.7 VDD 3.6V -- 6 ns -- * 1.71 VDD 2.7V -- 48 ns -- * 2.7 VDD 3.6V -- 24 ns -- * Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 6. 25 pF load K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 23 General 7. 15 pF load 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol TJ TA Description Min. Max. Unit Die junction temperature -40 125 C -40 105 C Ambient temperature1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RJA x chip power dissipation 5.4.2 Thermal attributes Board type Symbol Description 256 MAPBGA Unit Notes Single-layer (1s) RJA Thermal 43 resistance, junction to ambient (natural convection) C/W 1, 2 Four-layer (2s2p) RJA Thermal 28 resistance, junction to ambient (natural convection) C/W 1,2, 3 Single-layer (1s) RJMA Thermal 36 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 Four-layer (2s2p) RJMA Thermal 25 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 -- RJB Thermal 17 resistance, junction to board C/W 4 -- RJC Thermal 8 resistance, junction to case C/W 5 -- JT Thermal 2 characterization parameter, junction to package top outside center C/W 6 K70 Sub-Family, Rev.6, 09/2015. 24 Freescale Semiconductor, Inc. General Board type Symbol Description 256 MAPBGA Unit Notes (natural convection) NOTES: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification. 3. Determined according to JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air) with the board horizontal. 4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. Board temperature is measured on the top surface of the board near the package. 5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 5.5 Power sequencing Voltage supplies must be sequenced in the proper order to avoid damaging internal diodes. There is no limit on how long after one supply powers up before the next supply must power up. Note that VDD and VDD_INT can use the same power source. The power-up sequence is: 1. VDD/VDDA 2. VDD_INT 3. VDD_DDR The power-down sequence is the reverse: 1. VDD_DDR 2. VDD_INT 3. VDD/VDDA K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 -- ns Twh High pulse width 2 -- ns Tr Clock and data rise time -- 3 ns Tf Clock and data fall time -- 3 ns Ts Data setup 3 -- ns Th Data hold 2 -- ns TRACECLK Tr Tf Twh Twl Tcyc Figure 5. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 6. Trace data specifications K70 Sub-Family, Rev.6, 09/2015. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 25 * Serial Wire Debug 0 50 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 20 -- ns * Serial Wire Debug 10 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 2.4 -- ns J7 TCLK low to boundary scan output data valid -- 25 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1 -- ns J11 TCLK low to TDO data valid -- 17 ns J12 TCLK low to TDO high-Z -- 17 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 TCLK cycle period J3 TCLK clock pulse width Table 14. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation * Boundary Scan 0 10 * JTAG and CJTAG 0 20 * Serial Wire Debug 0 40 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 25 -- ns * Serial Wire Debug 12.5 -- ns -- 3 ns J2 TCLK cycle period J3 TCLK clock pulse width J4 MHz TCLK rise and fall times Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 2.4 -- ns J7 TCLK low to boundary scan output data valid -- 25 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1.4 -- ns J11 TCLK low to TDO data valid -- 22.1 ns J12 TCLK low to TDO high-Z -- 22.1 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 J3 J3 TCLK (input) J4 J4 Figure 7. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing K70 Sub-Family, Rev.6, 09/2015. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing TCLK J14 J13 TRST Figure 10. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit -- 32.768 -- kHz 31.25 -- 39.0625 kHz fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM -- 0.3 0.6 %fdco 1 fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM only -- 0.2 0.5 %fdco 1 Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C -- 4.5 -- %fdco 1 fintf_ft Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C -- 4 -- MHz fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C fints_t Internal reference frequency (slow clock) -- user trimmed fdco_t floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz -- 23.99 -- MHz -- 47.97 -- MHz -- 71.99 -- MHz -- 95.98 -- MHz -- 180 -- Notes FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 2, 3 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX32 DCO output frequency Low range (DRS=00) 4, 5 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll FLL period jitter ps Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description * fVCO = 48 MHz * fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time Min. Typ. Max. Unit Notes -- 150 -- -- -- 1 ms 6 8 -- 16 MHz PLL0,1 fpll_ref PLL reference frequency range fvcoclk_2x VCO output frequency fvcoclk PLL output frequency fvcoclk_90 180 90 PLL quadrature output frequency Ipll PLL0 operating current * VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) Ipll PLL0 operating current * VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) Ipll PLL1 operating current * VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) Ipll PLL1 operating current * VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) tpll_lock Lock detector detection time Jcyc_pll PLL period jitter (RMS) Jacc_pll 90 -- -- -- 360 180 180 MHz MHz MHz -- 2.8 -- mA -- 4.7 -- mA -- 2.3 -- mA -- 3.6 -- mA -- -- 100 x 10-6 + 1075(1/ fpll_ref) s 7 7 7 8 9 * fvco = 180 MHz -- 100 -- ps * fvco = 360 MHz -- 75 -- ps PLL accumulated jitter over 1s (RMS) 10 * fvco = 180 MHz -- 600 -- ps * fvco = 360 MHz -- 300 -- ps 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. Accumulated jitter depends on VCO frequency and VDIV. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors 6.3.2 Oscillator electrical specifications 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high-gain mode (HGO=1) 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA * 24 MHz -- 3 -- mA * 32 MHz -- 4 -- mA Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol Vpp5 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V Notes VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx and Cy can be provided by using either integrated capacitors or external components. When low-power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other device. 6.3.2.2 Symbol Oscillator frequency specifications Table 17. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- highfrequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 60 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 1000 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 500 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1 2, 3 4, 5 1. Frequencies less than 8 MHz are not in the PLL range. 2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors 4. Proper PC board layout procedures must be followed to achieve specifications. 5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 kHz oscillator electrical characteristics 6.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 -- 3.6 V Internal feedback resistor -- 100 -- M Cpara Parasitical capacitance of EXTAL32 and XTAL32 -- 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation -- 0.6 -- V RF 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 Symbol fosc_lo tstart 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal -- 32.768 -- kHz Crystal start-up time -- 1000 -- ms 1 700 -- VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 6.4 Memories and memory interfaces 6.4.1 Flash (FTFE) electrical specifications This section describes the electrical characteristics of the FTFE module. K70 Sub-Family, Rev.6, 09/2015. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 thversscr Notes Program Phrase high-voltage time -- 7.5 18 s Erase Flash Sector high-voltage time -- 13 113 ms 1 thversblk128k Erase Flash Block high-voltage time for 128 KB -- 104 1808 ms 1 thversblk256k Erase Flash Block high-voltage time for 256 KB -- 208 3616 ms 1 Notes 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol Flash timing specifications -- commands Table 21. Flash command timing specifications Description Min. Typ. Max. Unit Read 1s Block execution time trd1blk128k * 128 KB data flash -- -- 0.5 ms trd1blk256k * 256 KB program flash -- -- 1.0 ms 256 KB data flash trd1sec4k Read 1s Section execution time (4 KB flash) -- -- 100 s 1 tpgmchk Program Check execution time -- -- 80 s 1 trdrsrc Read Resource execution time -- -- 40 s 1 tpgm8 Program Phrase execution time -- 70 150 s Erase Flash Block execution time 2 tersblk128k * 128 KB data flash -- 110 925 ms tersblk256k * 256 KB program flash -- 220 1850 ms Erase Flash Sector execution time -- 15 115 ms Program Section execution time (4KB flash) -- 20 -- ms 256 KB data flash tersscr tpgmsec4k 2 Read 1s All Blocks execution time trd1allx * FlexNVM devices -- -- 3.4 ms trd1alln * Program flash only devices -- -- 3.4 ms Read Once execution time -- -- 30 s Program Once execution time -- 70 -- s tersall Erase All Blocks execution time -- 650 5600 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 trdonce tpgmonce 1 Swap Control execution time Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit tswapx01 * control code 0x01 -- 200 -- s tswapx02 * control code 0x02 -- 70 150 s tswapx04 * control code 0x04 -- 70 150 s tswapx08 * control code 0x08 -- -- 30 s Notes Program Partition for EEPROM execution time tpgmpart64k * 64 KB EEPROM backup -- 235 -- ms tpgmpart256k * 256 KB EEPROM backup -- 240 -- ms * Control Code 0xFF -- 205 -- s tsetram64k * 64 KB EEPROM backup -- 1.6 2.5 ms tsetram128k * 128 KB EEPROM backup -- 2.7 3.8 ms tsetram256k * 256 KB EEPROM backup -- 4.8 6.2 ms -- 140 225 s Set FlexRAM Function execution time: tsetramff t eewr8bers Byte-write to erased FlexRAM location execution time 3 Byte-write to FlexRAM execution time: teewr8b64k * 64 KB EEPROM backup -- 400 1700 s teewr8b128k * 128 KB EEPROM backup -- 450 1800 s teewr8b256k * 256 KB EEPROM backup -- 525 2000 s -- 140 225 s t eewr16bers 16-bit write to erased FlexRAM location execution time 16-bit write to FlexRAM execution time: teewr16b64k * 64 KB EEPROM backup -- 400 1700 s teewr16b128k * 128 KB EEPROM backup -- 450 1800 s teewr16b256k * 256 KB EEPROM backup -- 525 2000 s -- 180 275 s teewr32bers 32-bit write to erased FlexRAM location execution time 32-bit write to FlexRAM execution time: teewr32b64k * 64 KB EEPROM backup -- 475 1850 s teewr32b128k * 128 KB EEPROM backup -- 525 2000 s teewr32b256k * 256 KB EEPROM backup -- 600 2200 s 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. K70 Sub-Family, Rev.6, 09/2015. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 3.5 7.5 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 23. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycp Cycling endurance 10 K 50 K -- cycles tnvmretd10k Data retention after up to 10 K cycles 5 50 -- years tnvmretd1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycd Cycling endurance 10 K 50 K -- cycles 2 Data Flash 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 -- years tnvmretee10 Data retention up to 10% of write endurance 20 100 -- years 20 K 50 K -- cycles nnvmcycee Cycling endurance for EEPROM backup Write endurance 2 3 nnvmwree16 * EEPROM backup to FlexRAM ratio = 16 70 K 175 K -- writes nnvmwree128 * EEPROM backup to FlexRAM ratio = 128 630 K 1.6 M -- writes nnvmwree512 * EEPROM backup to FlexRAM ratio = 512 2.5 M 6.4 M -- writes nnvmwree2k * EEPROM backup to FlexRAM ratio = 2,048 10 M 25 M -- writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 3. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = EEPROM - 2 x EEESPLIT x EEESIZE EEESPLIT x EEESIZE x Write_efficiency x n nvmcycee where * Writes_subsystem -- minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) * EEPROM -- allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command * EEESPLIT -- FlexRAM split factor for subsystem; entered with the Program Partition command * EEESIZE -- allocated FlexRAM based on DEPART; entered with the Program Partition command * Write_efficiency -- * 0.25 for 8-bit writes to FlexRAM * 0.50 for 16-bit or 32-bit writes to FlexRAM * nnvmcycee -- EEPROM-backup cycling endurance K70 Sub-Family, Rev.6, 09/2015. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 11. EEPROM backup writes to FlexRAM 6.4.2 EzPort switching specifications Table 24. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except READ) -- fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) -- fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK -- ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 -- ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 -- ns EP5 EZP_D input valid to EZP_CK high (setup) 2 -- ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 -- ns EP7 EZP_CK low to EZP_Q output valid -- 16 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 -- ns EP9 EZP_CS negation to EZP_Q tri-state -- 12 ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 12. EzPort Timing Diagram 6.4.3 NFC specifications The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes the timing parameters of the NFC. In the following table: * TH is the flash clock high time and * TL is flash clock low time, which are defined as: T NFC = T L + T H = T input clock SCALER The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means TH = TL. In case the reciprocal of SCALER is not an integer: T L = (1 + SCALER / 2) x T NFC 2 K70 Sub-Family, Rev.6, 09/2015. 40 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors T H = (1 - SCALER / 2) x T NFC 2 For example, if SCALER is 0.2, then TH = TL = TNFC/2. TNFC TH TL However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC. TNFC TH TL NOTE The reciprocal of SCALER must be a multiple of 0.5. For example, 1, 1.5, 2, 2.5, etc. Table 25. NFC specifications Num Description Min. Max. Unit tCLS NFC_CLE setup time 2TH + TL - 1 -- ns tCLH NFC_CLE hold time TH + TL - 1 -- ns tCS NFC_CEn setup time 2TH + TL - 1 -- ns tCH NFC_CEn hold time TH + TL -- ns tWP NFC_WP pulse width TL - 1 -- ns tALS NFC_ALE setup time 2TH + TL -- ns tALH NFC_ALE hold time TH + TL -- ns tDS Data setup time TL - 1 -- ns tDH Data hold time TH - 1 -- ns tWC Write cycle time TH + TL - 1 -- ns tWH NFC_WE hold time TH - 1 -- ns tRR Ready to NFC_RE low 4TH + 3TL + 90 -- ns tRP NFC_RE pulse width TL + 1 -- ns tRC Read cycle time TL + TH - 1 -- ns tREH NFC_RE high hold time TH - 1 -- ns tIS Data input setup time 11 -- ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 41 Peripheral operating requirements and behaviors NFC_CLE tCLS tCLH NFC_CEn tCS tWP tCH NFC_WE tDS tDH NFC_IOn Figure 13. Command latch cycle timing NFC_ALE tALS tALH NFC_CEn tCS tWP tCH NFC_WE tDS NFC_IOn tDH address Figure 14. Address latch cycle timing tCS tCH tWC NFC_CEn tWP tWH tDS tDH NFC_WE NFC_IOn data data data Figure 15. Write data latch cycle timing K70 Sub-Family, Rev.6, 09/2015. 42 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors tCH tRC NFC_CEn tREH tRP NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 16. Read data latch cycle timing in non-fast mode tCH tRC NFC_CEn tRP tREH NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 17. Read data latch cycle timing in fast mode 6.4.4 DDR controller specifications The following timing numbers must be followed to properly latch or drive data onto the DDR memory bus. All timing numbers are relative to the DQS byte lanes. Table 26. DDR controller -- AC timing specifications Symbol Description Min. Max. Unit Frequency of operation tDDRCK 2 * DDR1 83.3 150 MHz * DDR2 1251 150 MHz 50 150 MHz 6.6 12 ns 6.6 8 ns * LPDDR Notes Clock period * DDR1 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 43 Peripheral operating requirements and behaviors Table 26. DDR controller -- AC timing specifications (continued) Symbol Description * DDR2 Min. Max. Unit 6.6 20 ns 0.5 x VDD_DDR - 0.2 V 0.5 x VDD_DDR + 0.2 V V 0.5 x VDD_DDR - 0.125 V 0.5 x VDD_DDR + 0.125 V 0.4 x VDD_DDR 0.4 x VDD_DDR Notes * LPDDR VOX-AC DDRCK AC differential cross point voltage * DDR1 * DDR2 * LPDDR 1. 2. 3. 4. 5. 6. 7. 8. V V tDDRCKH Pulse width high 0.45 0.55 tDDRCK 3 tDDRCKL Pulse width low 0.45 0.55 tDDRCK 3 4 tCMV Address, DDR_CKE, DDR_CAS, DDR_RAS, DDR_WE, DDR_CSn -- output setup 0.5 x tDDRCK - 1 -- ns tCMH Address, DDR_CKE, DDR_CAS, DDR_RAS, DDR_WE, DDR_CSn -- output hold 0.5 x tDDRCK - 1 -- ns tDQSS DQS rising edge to CK rising edge -0.2 x tDDRCK 0.2 x tDDRCK ns tQS Data and data mask output setup (DQDQS) relative to DQS (DDR write mode) 0.25 x tDDRCK - 1 -- ns 5, 6 tQH Data and data mask output hold (DQSDQ) relative to DQS (DDR write mode) 0.25 x tDDRCK - 1 -- ns 7 tDQSQ DQS-DQ skew for DQS and associated DQ signals - (0.25 x tDDRCK - 1) 0.25 x tDDRCK - 1 ns 8 This is minimum frequency of operation according to JEDEC DDR2 specification. DDR data rate = 2 x DDR clock frequency Pulse width high plus pulse width low cannot exceed min and max clock period. Command output setup should be 1/2 the memory bus clock (tDDRCK) plus some minor adjustments for process, temperature, and voltage variations. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0]. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0] Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). K70 Sub-Family, Rev.6, 09/2015. 44 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 2 3 4 5 6 7 8 tDDRCKH tDDRCK 9 10 tDDRCKL DDR_CLK DDR__CLK tCMH tCMV DDR_CSn, DDR_WE DDR_CAS, DDR_RAS DDR_An CMD CMD ROW COL tDQSS DDR_DQSn tQH tQS DDR_DMn DDR_DQn WD1 WD2 WD3 WD4 Figure 18. DDR write timing 1 2 3 4 5 tDDRCK 6 7 8 tDDRCHH 9 10 11 12 10 11 12 tDDRCKL DDR_CLK tCMH DDR__CLK tCMV DDR_CSn, DDR_WE DDR_CAS, DDR_RAS DDR_An CMD CMD ROW COL CL=2.5 DDR_DQS DQS read preamble (CL=2.5 ) RD2 RD3 RD4 RD3RD4 RD1 DDR_DQn CL=3.0 DDR_DQS DQS read preamble RD1 RD1 DDR_DQn 2 3 4 5 6 7 RD2 RD3 8 RD4 9 RD3 1 RD2RD3RD4 (CL=3.0 ) Figure 19. DDR read timing K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 45 Peripheral operating requirements and behaviors Figure 20. DDR read timing, DQ vs. DQS 6.4.5 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 27. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation -- FB_CLK MHz FB1 Clock period 20 -- ns FB2 Address, data, and control output valid -- 11.5 ns 1 FB3 Address, data, and control output hold 0.5 -- ns 1 FB4 Data and FB_TA input setup 8.5 -- ns 2 FB5 Data and FB_TA input hold 0.5 -- ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 28. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V -- FB_CLK MHz Frequency of operation Notes FB1 Clock period 1/FB_CLK -- ns FB2 Address, data, and control output valid -- 13.5 ns 1 FB3 Address, data, and control output hold 0 -- ns 1 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 46 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 28. Flexbus full voltage range switching specifications (continued) Num Description Min. Max. Unit Notes FB4 Data and FB_TA input setup 13.7 -- ns 2 FB5 Data and FB_TA input hold 0.5 -- ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 21. FlexBus read timing diagram K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 47 Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 22. FlexBus write timing diagram 6.5 Security and integrity modules 6.5.1 DryIce Tamper Electrical Specifications Information about security-related modules is not included in this document and is available only after a nondisclosure agreement (NDA) has been signed. To request an NDA, please contact your local Freescale sales representative. K70 Sub-Family, Rev.6, 09/2015. 48 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on the differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 31 and Table 32. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 29. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage * 16-bit differential mode VREFL -- 31/32 x VREFH V * All other modes VREFL -- * 16-bit mode -- 8 10 * 8-bit / 10-bit / 12-bit modes -- 4 5 -- 2 5 CADIN RADIN RAS Input capacitance Input series resistance Notes VREFH pF k Analog source resistance (external) 13-bit / 12-bit modes 3 fADCK < 4 MHz -- -- 5 k fADCK ADC conversion clock frequency 13-bit mode 1.0 -- 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 -- 12.0 MHz 4 Crate ADC conversion rate 13-bit modes 5 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 49 Peripheral operating requirements and behaviors Table 29. 16-bit ADC operating conditions (continued) Symbol Description Min. Typ.1 Max. Unit 20.000 -- 818.330 ksps Conditions No ADC hardware averaging Notes Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode 5 No ADC hardware averaging 37.037 -- 461.467 ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN Pad leakage due to input protection ZAS RAS SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VADIN VAS CAS RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 23. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics K70 Sub-Family, Rev.6, 09/2015. 50 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 * ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz * ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK * ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz * ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 IDDA_ADC Supply current ADC asynchronous clock source fADACK Sample Time TUE DNL INL EFS EQ ENOB See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 * <12-bit modes -- 0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 16-bit modes -- -1 to 0 -- * 13-bit modes -- -- 0.5 Integral non-linearity Full-scale error Quantization error Effective number of bits -0.3 to 0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 16-bit differential mode 6 * Avg = 32 12.8 14.5 * Avg = 4 11.9 13.8 -- -- bits bits 16-bit single-ended mode * Avg = 32 * Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode 12.2 13.9 11.4 13.1 -- -- 6.02 x ENOB + 1.76 * Avg = 32 bits bits dB dB -- -94 7 -- dB 16-bit single-ended mode * Avg = 32 SFDR Spurious free dynamic range -- -85 82 95 16-bit differential mode * Avg = 32 16-bit single-ended mode 78 -- -- dB -- dB 7 90 Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 51 Peripheral operating requirements and behaviors Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Conditions1 Symbol Description Typ.2 Min. Max. Unit Notes mV IIn = leakage current * Avg = 32 EIL Input leakage error IIn x RAS (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device VTEMP25 Temp sensor voltage 25 C 1.55 1.62 1.69 mV/C 8 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 24. Typical ENOB vs. ADC_CLK for 16-bit differential mode K70 Sub-Family, Rev.6, 09/2015. 52 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 25. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 31. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VREFPGA PGA ref voltage VADIN VCM RPGAD VREF_OU VREF_OU VREF_OU T T T V Notes 2, 3 Input voltage VSSA -- VDDA V Input Common Mode range VSSA -- VDDA V Gain = 1, 2, 4, 8 -- 128 -- k IN+ to IN-4 Gain = 16, 32 -- 64 -- Gain = 64 -- 32 -- Differential input impedance RAS Analog source resistance -- 100 -- 5 TS ADC sampling time 1.25 -- -- s 6 18.484 -- 450 Ksps 7 37.037 -- 250 Ksps 8 Crate ADC conversion rate 13 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 53 Peripheral operating requirements and behaviors Table 31. 16-bit ADC with PGA operating conditions Symbol Description Conditions Typ.1 Min. Max. Unit Notes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREF_OUT) 3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedance of the driven input is RPGAD/2 5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 6.6.1.4 16-bit ADC with PGA characteristics Table 32. 16-bit ADC with PGA characteristics Symbol Description Conditions IDDA_PGA Supply current Low power (ADC_PGA[PGALPb]=0) IDC_PGA Input DC current G BW PSRR Gain4 Input signal bandwidth Power supply rejection ratio Min. Typ.1 Max. Unit Notes -- 420 644 A 2 A 3 Gain =1, VREFPGA=1.2V, VCM=0.5V -- 1.54 -- A Gain =64, VREFPGA=1.2V, VCM=0.1V -- 0.57 -- A * PGAG=0 0.95 1 1.05 * PGAG=1 1.9 2 2.1 * PGAG=2 3.8 4 4.2 * PGAG=3 7.6 8 8.4 * PGAG=4 15.2 16 16.6 * PGAG=5 30.0 31.6 33.2 * PGAG=6 58.8 63.3 67.8 -- -- 4 kHz -- -- 40 kHz -- -84 -- dB * 16-bit modes * < 16-bit modes Gain=1 RAS < 100 VDDA= 3V 100mV, Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 54 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 32. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes fVDDA= 50Hz, 60Hz CMRR VOFS Common mode rejection ratio * Gain=1 -- -84 -- dB * Gain=64 -- -85 -- dB Input offset voltage * Chopping disabled (ADC_PGA[PGACHPb] =1) * Chopping enabled (ADC_PGA[PGACHPb] =0) -- 2.4 -- mV -- 0.2 -- mV -- -- 10 s * Gain=1 * Gain=64 -- 6 10 ppm/C -- 31 42 ppm/C * Gain=1 * Gain=64 -- 0.07 0.21 %/V -- 0.14 0.31 %/V TGSW Gain switching settling time dG/dT Gain drift over full temperature range dG/dVDDA Gain drift over supply voltage EIL Input leakage error All modes IIn x RAS mV VCM= 500mVpp, fVCM= 50Hz, 100Hz Output offset = VOFS*(Gain+1) 5 VDDA from 1.71 to 3.6V IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF Maximum differential input signal swing SNR Signal-to-noise ratio * Gain=1 80 90 * Gain=64 52 Total harmonic distortion * Gain=1 THD SFDR ENOB V 6 -- dB 66 -- dB 16-bit differential mode, Average=32 85 100 -- dB * Gain=64 49 95 -- dB Spurious free dynamic range * Gain=1 85 105 -- dB * Gain=64 53 88 -- dB Effective number of bits * Gain=1, Average=4 11.6 13.4 -- bits * Gain=1, Average=8 8.0 13.6 -- bits * Gain=64, Average=4 7.2 9.6 -- bits * Gain=64, Average=8 6.3 9.6 -- bits 12.8 14.5 -- bits where VX = VREFPGA x 0.583 16-bit differential mode, Average=32, fin=100Hz 16-bit differential mode, Average=32, fin=100Hz 16-bit differential mode,fin=100Hz Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 55 Peripheral operating requirements and behaviors Table 32. 16-bit ADC with PGA characteristics (continued) Symbol Description Min. Typ.1 Max. Unit * Gain=1, Average=32 11.0 14.3 -- bits * Gain=2, Average=32 7.9 13.8 -- bits * Gain=4, Average=32 7.3 13.1 -- bits * Gain=8, Average=32 6.8 12.5 -- bits * Gain=16, Average=32 6.8 11.5 -- bits * Gain=32, Average=32 7.5 10.6 -- bits Conditions Notes * Gain=64, Average=32 SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 x ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications Table 33. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns -- -- 40 s -- 7 -- A Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 56 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 33. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 57 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 34. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.6 V 1 2 CL Output load capacitance -- 100 pF IL Output load current -- 1 mA Notes 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. K70 Sub-Family, Rev.6, 09/2015. 58 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 35. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 150 A -- -- 700 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 -- 0.7 1 s 1 -- -- 100 mV tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode Vdacoutl DAC output voltage range low -- high-speed mode, no load, DAC set to 0x000 Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C Rop Output resistance (load = 3 k) -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR 1. 2. 3. 4. 5. 6. V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- -- -- -80 CT Channel to channel cross talk BW 3dB bandwidth 6 dB kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 59 Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 28. Typical INL error vs. digital code K70 Sub-Family, Rev.6, 09/2015. 60 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 25 -40 55 85 105 125 Temperature C Figure 29. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 36. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 61 Peripheral operating requirements and behaviors Table 37. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V 1 Vout Voltage reference output -- factory trim 1.1584 -- 1.2376 V 1 Vout Voltage reference output -- user trim 1.193 -- 1.197 V 1 Vstep Voltage reference trim step -- 0.5 -- mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) -- -- 80 mV 1 Ibg Bandgap only current -- -- 80 A 1 Ihp High-power buffer current -- -- 1 mA 1 mV 1, 2 VLOAD Load regulation * current = + 1.0 mA -- 2 -- * current = - 1.0 mA -- 5 -- Tstup Buffer startup time -- -- 100 s Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) -- 2 -- mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 38. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 50 C Notes Table 39. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit 1.173 1.225 V Notes 6.7 Timers See General switching specifications. 6.8 Communication interfaces K70 Sub-Family, Rev.6, 09/2015. 62 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 40. MII signal switching specifications Symbol -- Description RXCLK frequency Min. Max. Unit -- 25 MHz MII1 RXCLK pulse width high 35% 65% RXCLK MII2 RXCLK pulse width low 35% 65% RXCLK MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 -- ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 -- ns TXCLK frequency -- 25 MHz 35% 65% TXCLK period period -- MII5 TXCLK pulse width high period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 -- ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid -- 25 ns MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 30. RMII/MII transmit signal timing diagram K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 63 Peripheral operating requirements and behaviors MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 31. RMII/MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 41. RMII signal switching specifications Num -- Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max. Unit -- 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 -- ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 -- ns RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 -- ns RMII8 RMII_CLK to TXD[1:0], TXEN valid -- 15 ns 6.8.2 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. NOTE The MCGPLLCLK meets the USB jitter specifications for certification with the use of an external clock/crystal for both Device and Host modes. K70 Sub-Family, Rev.6, 09/2015. 64 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors The MCGFLLCLK does not meet the USB jitter specifications for certification. 6.8.3 USB DCD electrical specifications Table 42. USB0 DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 A) 0.5 -- 0.7 V Threshold voltage for logic high 0.8 -- 2.0 V VLGC IDP_SRC USB_DP source current 7 10 13 A IDM_SINK USB_DM sink current 50 100 150 A RDM_DWN D- pulldown resistance for data pin contact detect 14.25 -- 24.8 k VDAT_REF Data detect voltage 0.25 0.325 0.4 V 6.8.4 USB VREG electrical specifications Table 43. USB VREG electrical specifications Symbol Description Min. VREGIN Typ.1 Max. Unit Input supply voltage 2.7 -- 5.5 V IDDon Quiescent current -- Run mode, load current equal zero, input supply (VREGIN) > 3.6 V -- 125 186 A IDDstby Quiescent current -- Standby mode, load current equal zero -- 1.1 10 A IDDoff Quiescent current -- Shutdown mode -- 650 -- nA -- -- 4 A * VREGIN = 5.0 V and temperature=25 C * Across operating voltage and temperature ILOADrun Maximum load current -- Run mode -- -- 120 mA ILOADstby Maximum load current -- Standby mode -- -- 1 mA VReg33out Regulator output voltage -- Input supply (VREGIN) > 3.6 V 3 3.3 3.6 V 2.1 2.8 3.6 V Regulator output voltage -- Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 -- 3.6 V COUT External output capacitor 1.76 2.2 8.16 F ESR External output capacitor equivalent series resistance 1 -- 100 m ILIM Short circuit current -- 290 -- mA * Run mode * Standby mode VReg33out Notes 2 1. Typical values assume VREGIN = 5.0 V, Temp = 25 C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 65 Peripheral operating requirements and behaviors 6.8.5 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin. Table 44. ULPI timing specifications Num Description Min. Typ. Max. Unit USB_CLKIN operating frequency -- 60 -- MHz USB_CLKIN duty cycle -- 50 -- % U1 USB_CLKIN clock period -- 16.67 -- ns U2 Input setup (control and data) 5 -- -- ns U3 Input hold (control and data) 1 -- -- ns U4 Output valid (control and data) -- -- 9.5 ns U5 Output hold (control and data) 1 -- -- ns U1 USB_CLKIN U2 U3 ULPI_DIR/ULPI_NXT (control input) ULPI_DATAn (input) U4 U5 ULPI_STP (control output) ULPI_DATAn (output) Figure 32. ULPI timing diagram K70 Sub-Family, Rev.6, 09/2015. 66 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.6 CAN switching specifications See General switching specifications. 6.8.7 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 45. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 30 MHz 2 x tBUS -- ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 2 -- ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 2 -- ns 2 DS5 DSPI_SCK to DSPI_SOUT valid -- 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -2 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 15 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK DS7 (CPOL=0) DSPI_SIN DS4 DS8 First data DSPI_SOUT DS1 DS2 First data Data Last data DS5 DS6 Data Last data Figure 33. DSPI classic SPI timing -- master mode K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 67 Peripheral operating requirements and behaviors Table 46. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit 2.7 3.6 V 15 MHz 4 x tBUS -- ns (tSCK/2) - 2 (tSCK/2) + 2 ns Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 10 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 14 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 34. DSPI classic SPI timing -- slave mode 6.8.8 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 47. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation DS1 DSPI_SCK output cycle time Min. Max. Unit Notes 1.71 -- 3.6 V 1 15 MHz 4 x tBUS -- ns Table continues on the next page... K70 Sub-Family, Rev.6, 09/2015. 68 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 47. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 4 -- ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 4 -- ns 3 DS5 DSPI_SCK to DSPI_SOUT valid -- 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 20.5 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK DSPI_SIN DS4 DS8 DS7 (CPOL=0) DS1 DS2 First data DSPI_SOUT Data Last data DS5 First data DS6 Data Last data Figure 35. DSPI classic SPI timing -- master mode Table 48. Slave mode DSPI timing (full voltage range) Num Description Min. Max. Unit 1.71 3.6 V -- 7.5 MHz 8 x tBUS -- ns (tSCK/2) - 4 (tSCK/2) + 4 ns Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 19 ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 69 Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 36. DSPI classic SPI timing -- slave mode 6.8.9 Inter-Integrated Circuit Interface (I2C) timing Table 49. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency fSCL 0 100 0 400 1 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.25 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Data hold time for I2C bus devices tHD; DAT 02 3.453 04 0.92 s tSU; DAT 2505 -- 1003,6 Data set-up time -- ns 7 Rise time of SDA and SCL signals tr -- 1000 20 +0.1Cb 300 ns Fall time of SDA and SCL signals tf -- 300 20 +0.1Cb6 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using a pin configured for high drive across the full voltage range and when using the a pin configured for low drive with VDD 2.7 V. 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a K70 Sub-Family, Rev.6, 09/2015. 70 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF. SDA tf tLOW tSU; DAT tr tf tHD; STA tSP tr tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 37. Timing definition for fast and standard mode devices on the I2C bus 6.8.10 UART switching specifications See General switching specifications. 6.8.11 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 50. SDHC switching specifications over a limited operating voltage range Num Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz tWL Clock low time 7 -- ns SD3 tWH Clock high time 7 -- ns SD4 tTLH Clock rise time -- 3 ns SD5 tTHL Clock fall time -- 3 ns SD2 SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 6.5 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 -- ns SD8 tIH SDHC input hold time 0 -- ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 71 Peripheral operating requirements and behaviors Table 51. SDHC switching specifications over the full operating voltage range Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 -- ns SD3 tWH Clock high time 7 -- ns SD4 tTLH Clock rise time -- 3 ns SD5 tTHL Clock fall time -- 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 6.5 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 -- ns SD8 tIH SDHC input hold time 1.3 -- ns SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 38. SDHC timing 6.8.12 I2S/SAI switching specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] K70 Sub-Family, Rev.6, 09/2015. 72 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 6.8.12.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes. Table 52. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 15 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 73 Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 39. I2S/SAI timing -- master modes Table 53. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 4.5 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 21 -- 15 * Multiple SAI Synchronous mode * All other modes ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns -- 25 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K70 Sub-Family, Rev.6, 09/2015. 74 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 40. I2S/SAI timing -- slave modes 6.8.12.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 54. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid -1.0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 20.5 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 75 Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 41. I2S/SAI timing -- master modes Table 55. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 5.8 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 24 -- 20.6 * Multiple SAI Synchronous mode * All other modes ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 5.8 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns -- 25 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K70 Sub-Family, Rev.6, 09/2015. 76 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 42. I2S/SAI timing -- slave modes 6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 56. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid -1.6 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 45 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 77 Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 43. I2S/SAI timing -- master modes Table 57. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 3 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 63 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 30 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns -- 72 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K70 Sub-Family, Rev.6, 09/2015. 78 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 44. I2S/SAI timing -- slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 58. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 -- 3.6 V 1 20 500 pF CELE fREFmax fELEmax CREF VDELTA IREF IELE Target electrode capacitance range Reference oscillator frequency -- 8 15 Notes 1 MHz 2, 3 2, 4 5 Electrode oscillator frequency -- 1 1.8 MHz Internal reference capacitor -- 1 -- pF Oscillator delta voltage -- 600 -- mV 2, -- 2 3 A 2, 6 -- 36 50 -- 2 3 A 2, 7 -- 36 50 Reference oscillator current source base current * 2 A setting (REFCHRG = 0) * 32 A setting (REFCHRG = 15) Electrode oscillator current source base current * 2 A setting (EXTCHRG = 0) * 32 A setting (EXTCHRG = 15) Pres5 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 10 0.008 1.46 -- fF/count 11 Resolution -- -- 16 bits Response time @ 20 pF 8 15 25 s Current added in run mode -- 55 -- A Low power mode current adder -- 1.3 2.5 A MaxSens Maximum sensitivity Res TCon20 ITSI_RUN ITSI_LP 12 13 K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 79 Peripheral operating requirements and behaviors 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) The typical value is calculated with the following configuration: Iext = 6 A (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 A (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 A (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 A (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. 6.9.2 LCDC electrical specifications Table 59. GLCD_LSCLK Timing Num Description Min. Max. Unit T1 GLCD_LSCLK Period 25 2000 ns T2 Pixel data setup time 8 -- ns T3 Pixel data up time 8 -- ns NOTE The pixel clock is equal to GLCD_LSCLK / (PCD + 1). When it is in CSTN, TFT, or monochrome mode with bus width = 1, GLCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, GLCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of GLCD_LSCLK and GLCD_D signals can also be programmed. K70 Sub-Family, Rev.6, 09/2015. 80 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors T1 GLCD_LSCLK GLCD_D[17:0] T2 T3 Figure 45. GLCD_LSCLK to GLCD_D[17:0] Timing Non-display region T1 GLCD_VSYNC T3 Display region T4 T2 GLCD_HSYNC GLCD_OE GLCD_D[17:0] Line 1 Line Y T5 T6 XMAX Line Y T7 GLCD_HSYNC GLCD_LSCLK GLCD_OE GLCD_D[15:0] (1,1) (1,2) (1,X) Figure 46. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 60. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Num Description Min. Max. Unit T5 + T6 + T7 -1 (VWAIT1 x T2) + T5 + T6 + T7 - 1 Ts T1 End of GLCD_OE to beginning of GLCD_VSYNC T2 GLCD_HSYNC period -- XMAX + T5 + T6 + T7 Ts T3 GLCD_VSYNC pulse width T2 VWIDTH x T2 Ts T4 End of GLCD_VSYNC to beginning of GLCD_OE 1 (VWAIT2 x T2) + 1 Ts T5 GLCD_HSYNC pulse width 1 HWIDTH + 1 Ts T6 End of GLCD_HSYNC to beginning to GLCD_OE 3 HWAIT2 + 3 Ts T7 End of GLCD_OE to beginning of GLCD_HSYNC 1 HWAIT1 + 1 Ts K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 81 Peripheral operating requirements and behaviors NOTE * Ts is the GLCD_LSCLK period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_OE can be programmed as active high or active low. In the preceding figure, all 3 signals are active low. GLCD_LSCLK can be programmed to be deactivated during the GLCD_VSYNC pulse or the GLCD_OE deasserted period. In the preceding figure, GLCD_LSCLK is always active. * XMAX is defined in number of pixels in one line. T1 T1 GLCD_VSYNC T2 T3 XMAX T4 T2 GLCD_HSYNC GLCD_LSCLK TS GLCD_D[15:0] Figure 47. Non-TFT Mode Panel Timing Table 61. Non-TFT Mode Panel Timing Num Description Min. Max. Unit T1 GLCD_HSYNC to GLCD_VSYNC delay 2 HWAIT2 + 2 Tpix T2 GLCD_HSYNC pulse width 1 HWIDTH + 1 Tpix T3 GLCD_VSYNC to GLCD_LSCLK -- 0 T3 Ts -- T4 GLCD_LSCLK to GLCD_HSYNC 1 HWAIT1 + 1 Tpix NOTE Ts is the GLCD_LSCLK period while Tpix is the pixel clock period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_LSCLK can be programmed as active high or active low. In the preceding figure, all these 3 signals are active high. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively. K70 Sub-Family, Rev.6, 09/2015. 82 Freescale Semiconductor, Inc. Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing's document number: If you want the drawing for this package 256-pin MAPBGA Then use this document number 98ASA00346D 8 Pinout 8.1 Pins with active pull control after reset The following pins are actively pulled up or down after reset: Table 62. Pins with active pull control after reset Pin Active pull direction after reset PTA0 pulldown PTA1 pullup PTA3 pullup PTA4 pullup RESET_b pullup 8.2 K70 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 83 Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E2 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 GLCD_D0 I2C1_SDA RTC_ CLKOUT F2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 GLCD_D1 I2C1_SCL SPI1_SIN F3 PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_ SDHC0_DCLK GLCD_D2 b G2 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_ SDHC0_CMD GLCD_D3 b G7 VDD VDD VDD H7 VDDINT VDDINT VDDINT H8 VSS VSS VSS F1 PTF17 DISABLED PTF17 SPI2_SCK FTM0_CH4 UART0_RX GLCD_D13 G1 PTF18 DISABLED PTF18 SPI2_SOUT FTM1_CH0 UART0_TX GLCD_D14 G3 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 GLCD_D4 G4 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 GLCD_D5 FTM3_CH0 H2 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_ I2S0_MCLK b GLCD_D6 FTM3_CH1 H1 PTF19 DISABLED PTF19 SPI2_SIN FTM1_CH1 UART5_RX GLCD_D15 H5 PTF20 DISABLED PTF20 SPI2_PCS1 FTM2_CH0 UART5_TX GLCD_D16 H3 PTE7 DISABLED PTE7 H4 PTE8 ADC2_SE16 ADC2_SE16 PTE8 J1 PTE9 ADC2_SE17 ADC2_SE17 PTE9 J2 PTE10 DISABLED K1 PTE11 ADC3_SE16 K3 PTE12 G8 SPI1_SOUT UART3_RTS_ I2S0_RXD0 b GLCD_D7 FTM3_CH2 I2S0_RXD1 UART5_TX I2S0_RX_FS GLCD_D8 FTM3_CH3 I2S0_TXD1 UART5_RX I2S0_RX_ BCLK GLCD_D9 FTM3_CH4 PTE10 UART5_CTS_ I2S0_TXD0 b GLCD_D10 FTM3_CH5 ADC3_SE16 PTE11 UART5_RTS_ I2S0_TX_FS b GLCD_D11 FTM3_CH6 ADC3_SE17 ADC3_SE17 PTE12 GLCD_D12 FTM3_CH7 VDD VDD VDD H9 VSS VSS VSS J3 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3 K2 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_ ALT3 L4 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_ I2C0_SDA b M3 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_ I2C0_SCL b L2 VSS VSS VSS M1 USB0_DP USB0_DP USB0_DP M2 USB0_DM USB0_DM USB0_DM L1 VOUT33 VOUT33 VOUT33 I2S0_TX_ BCLK EzPort USB_SOF_ OUT CMP3_OUT K70 Sub-Family, Rev.6, 09/2015. 84 Freescale Semiconductor, Inc. Pinout 256 MAP BGA Pin Name Default ALT0 L3 VREGIN VREGIN VREGIN N1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 N2 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 P1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 P2 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 R1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 R2 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 T1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 T2 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 N5 VDDA VDDA VDDA P4 VREFH VREFH VREFH M4 VREFL VREFL VREFL N4 VSSA VSSA VSSA P3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 N3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 T3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 R3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 R4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 85 Pinout 256 MAP BGA Pin Name Default ALT0 M5 TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B L5 TAMPER1 TAMPER1 TAMPER1 L6 TAMPER2 TAMPER2 TAMPER2 R5 TAMPER3 TAMPER3 TAMPER3 P6 TAMPER4 TAMPER4 TAMPER4 R6 TAMPER5 TAMPER5 TAMPER5 T6 XTAL32 XTAL32 XTAL32 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort T5 EXTAL32 EXTAL32 EXTAL32 P5 VBAT VBAT VBAT N6 TAMPER6 TAMPER6 TAMPER6 M6 TAMPER7 TAMPER7 TAMPER7 G9 VDD VDD VDD H10 VDDINT VDDINT VDDINT J8 VSS VSS VSS P7 PTE24 ADC0_SE17/ EXTAL1 ADC0_SE17/ EXTAL1 PTE24 CAN1_TX UART4_TX I2S1_TX_FS GLCD_D13 EWM_OUT_b I2S1_RXD1 R7 PTE25 ADC0_SE18/ XTAL1 ADC0_SE18/ XTAL1 PTE25 CAN1_RX UART4_RX I2S1_TX_ BCLK GLCD_D14 EWM_IN I2S1_TXD1 M7 PTE26 ADC3_SE5b ADC3_SE5b PTE26 ENET_1588_ CLKIN UART4_CTS_ I2S1_TXD0 b GLCD_D15 RTC_ CLKOUT USB_CLKIN K7 PTE27 ADC3_SE4b ADC3_SE4b PTE27 UART4_RTS_ I2S1_MCLK b GLCD_D16 L7 PTE28 ADC3_SE7a ADC3_SE7a PTE28 T7 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 b/ UART0_COL_ b JTAG_TCLK/ SWD_CLK EZP_CLK N8 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI T8 PTA2 JTAG_TDO/ TSI0_CH3 TRACE_SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ EZP_DO TRACE_SWO P8 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ FTM0_CH0 b R8 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 T12 PTA5 DISABLED PTA5 G10 VDD VDD VDD J9 VSS VSS VSS P9 PTF21 ADC3_SE6b ADC3_SE6b PTF21 GLCD_D17 JTAG_TMS/ SWD_DIO FTM0_CH1 USB_CLKIN NMI_b FTM0_CH2 RMII0_RXER/ CMP2_OUT MII0_RXER FTM2_CH1 UART5_RTS_ b I2S0_TX_ BCLK EZP_CS_b JTAG_TRST_ b GLCD_D17 K70 Sub-Family, Rev.6, 09/2015. 86 Freescale Semiconductor, Inc. Pinout 256 MAP BGA N9 Pin Name PTF22 Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ADC3_SE7b ADC3_SE7b PTF22 I2C0_SCL FTM1_CH0 UART5_CTS_ b R12 PTA6 ADC3_SE6a ADC3_SE6a PTA6 ULPI_CLK FTM0_CH3 I2S1_RXD0 P12 PTA7 ADC0_SE10 ADC0_SE10 PTA7 ULPI_DIR FTM0_CH4 I2S1_RX_ BCLK N12 PTA8 ADC0_SE11 ADC0_SE11 PTA8 ULPI_NXT FTM1_CH0 I2S1_RX_FS FTM1_QD_ PHA TRACE_D2 T13 PTA9 ADC3_SE5a ADC3_SE5a PTA9 ULPI_STP FTM1_CH1 MII0_RXD3 FTM1_QD_ PHB TRACE_D1 P13 PTA10 ADC3_SE4a ADC3_SE4a PTA10 ULPI_DATA0 FTM2_CH0 MII0_RXD2 FTM2_QD_ PHA TRACE_D0 R13 PTA11 ADC3_SE15 ADC3_SE15 PTA11 ULPI_DATA1 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB M10 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ MII0_RXD1 I2S0_TXD0 FTM1_QD_ PHA N10 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 RMII0_RXD0/ MII0_RXD0 I2S0_TX_FS FTM1_QD_ PHB R11 PTA14 CMP3_IN0 CMP3_IN0 PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ DV/ MII0_RXDV I2S0_RX_ BCLK I2S0_TXD1 P11 PTA15 CMP3_IN1 CMP3_IN1 PTA15 SPI0_SCK UART0_RX RMII0_TXEN/ MII0_TXEN I2S0_RXD0 T14 VSS GLCD_D18 CLKOUT TRACE_ CLKOUT TRACE_D3 VSS VSS N11 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_SOUT UART0_CTS_ RMII0_TXD0/ b/ MII0_TXD0 UART0_COL_ b I2S0_RX_FS T11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_ RMII0_TXD1/ b MII0_TXD1 I2S0_MCLK P10 PTF23 ADC3_SE10 ADC3_SE10 PTF23 I2C0_SDA FTM1_CH1 TRACE_ CLKOUT GLCD_D19 R10 PTF24 ADC3_SE11 ADC3_SE11 PTF24 CAN1_RX FTM1_QD_ PHA TRACE_D3 GLCD_D20 R9 PTF25 ADC3_SE12 ADC3_SE12 PTF25 CAN1_TX FTM1_QD_ PHB TRACE_D2 GLCD_D21 T9 PTF26 ADC3_SE13 ADC3_SE13 PTF26 FTM2_QD_ PHA TRACE_D1 GLCD_D22 T10 PTF27 ADC3_SE14 ADC3_SE14 PTF27 FTM2_QD_ PHB TRACE_D0 GLCD_D23 J7 VDD VDD VDD K8 VSS VSS VSS T15 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 T16 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_ ALT1 R16 RESET_b RESET_b RESET_b N13 PTA24 CMP3_IN4 CMP3_IN4 MII0_TXD2 FB_A29 PTA24 ULPI_DATA2 EzPort I2S0_RXD1 K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 87 Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 R14 PTA25 CMP3_IN5 CMP3_IN5 PTA25 ULPI_DATA3 MII0_TXCLK FB_A28 M13 PTA26 ADC2_SE15 ADC2_SE15 PTA26 ULPI_DATA4 MII0_TXD3 FB_A27 R15 PTA27 ADC2_SE14 ADC2_SE14 PTA27 ULPI_DATA5 MII0_CRS FB_A26 P14 ALT7 PTA28 ADC2_SE13 ADC2_SE13 PTA28 ULPI_DATA6 MII0_TXER FB_A25 N14 PTA29 ADC2_SE12 ADC2_SE12 PTA29 ULPI_DATA7 MII0_COL FB_A24 P16 PTF0 ADC2_SE11 ADC2_SE11 PTF0 CAN0_TX FTM3_CH0 I2S1_RXD1 GLCD_PCLK L13 PTF1 ADC2_SE10 ADC2_SE10 PTF1 CAN0_RX FTM3_CH1 I2S1_RX_ BCLK GLCD_DE M12 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 RMII0_MDIO/ MII0_MDIO FTM1_QD_ PHA M11 PTB1 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/ MII0_MDC FTM1_QD_ PHB P15 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ ENET0_1588_ b TMR0 FTM0_FLT3 M14 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ ENET0_1588_ b/ TMR1 UART0_COL_ b FTM0_FLT0 N15 PTB4 ADC1_SE10 ADC1_SE10 PTB4 GLCD_ CONTRAST ENET0_1588_ TMR2 FTM1_FLT0 M15 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_ TMR3 FTM2_FLT0 L14 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 L15 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 K14 PTB8 DISABLED PTB8 K15 PTB9 DISABLED PTB9 J13 PTB10 ADC1_SE14 ADC1_SE14 J14 PTB11 ADC1_SE15 ADC1_SE15 K9 VSS VSS VSS J10 VDD VDD VDD N16 PTF2 ADC2_SE6a M16 PTF3 L16 J15 UART3_RTS_ b FB_AD21 SPI1_PCS1 UART3_CTS_ b FB_AD20 PTB10 SPI1_PCS0 UART3_RX I2S1_TX_ BCLK FB_AD19 FTM0_FLT1 PTB11 SPI1_SCK UART3_TX I2S1_TX_FS FB_AD18 FTM0_FLT2 ADC2_SE6a PTF2 I2C1_SCL FTM3_CH2 I2S1_RX_FS GLCD_HFS ADC2_SE7a ADC2_SE7a PTF3 I2C1_SDA FTM3_CH3 I2S1_RXD0 GLCD_VFS PTF4 ADC2_SE4b ADC2_SE4b PTF4 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX I2S1_TXD0 FB_AD17 EWM_IN H13 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX I2S1_TXD1 FB_AD16 EWM_OUT_b H14 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA FTM3_CH4 I2S1_TXD0 EzPort GLCD_D0 K70 Sub-Family, Rev.6, 09/2015. 88 Freescale Semiconductor, Inc. Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 K16 PTF5 ADC2_SE5b ADC2_SE5b PTF5 FTM3_CH5 I2S1_TX_FS GLCD_D1 J16 PTF6 ADC2_SE6b ADC2_SE6b PTF6 FTM3_CH6 I2S1_TX_ BCLK GLCD_D2 H15 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX G13 PTB20 ADC2_SE4a ADC2_SE4a PTB20 SPI2_PCS0 FB_AD31/ CMP0_OUT NFC_DATA15 G14 PTB21 ADC2_SE5a ADC2_SE5a PTB21 SPI2_SCK FB_AD30/ CMP1_OUT NFC_DATA14 G15 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/ CMP2_OUT NFC_DATA13 H16 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/ CMP3_OUT NFC_DATA12 G16 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14/ I2S0_TXD1 NFC_DATA11 F13 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_ FTM0_CH0 b FB_AD13/ I2S0_TXD0 NFC_DATA10 F14 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_ FTM0_CH1 b FB_AD12/ NFC_DATA9 I2S0_TX_FS E13 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK F15 PTF7 ADC2_SE7b ADC2_SE7b PTF7 FTM3_CH7 UART3_RX I2S1_TXD1 GLCD_D3 L9 VSS VSS VSS K10 VDD VDD VDD F16 PTF8 DISABLED PTF8 FTM3_FLT0 UART3_TX I2S1_MCLK GLCD_D4 E14 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11/ NFC_DATA8 CMP1_OUT I2S1_TX_ BCLK E15 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 FB_AD10/ NFC_DATA7 CMP0_OUT I2S1_TX_FS F12 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_RX_ BCLK FB_AD9/ NFC_DATA6 I2S0_MCLK G12 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS FB_AD8/ NFC_DATA5 H12 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4 I2S0_MCLK FB_AD7/ NFC_DATA4 F11 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5 I2S0_RX_ BCLK FB_AD6/ NFC_DATA3 FTM2_FLT0 G11 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL FTM3_CH6 I2S0_RX_FS FB_AD5/ NFC_DATA2 I2S1_MCLK H11 PTC11/ LLWU_P11 ADC1_SE7b ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA FTM3_CH7 I2S0_RXD1 FB_RW_b/ NFC_WE J12 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 K13 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 PTC9 FTM2_CH1 I2S0_TX_FS FB_OE_b EzPort FTM2_QD_ PHB FTM3_FLT0 K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 89 Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 PTC14 ALT3 ALT4 UART4_RX ALT5 ALT6 ALT7 J11 PTC14 DISABLED K12 PTF9 CMP2_IN4 CMP2_IN4 PTF9 UART3_RTS_ b GLCD_D5 L12 PTF10 CMP2_IN5 CMP2_IN5 PTF10 UART3_CTS_ b GLCD_D6 F10 PTC15 DISABLED N7 VSS VSS VSS L10 VDD VDD VDD K11 PTF11 DISABLED PTF11 UART2_RTS_ b GLCD_D7 L11 PTF12 DISABLED PTF12 UART2_CTS_ b GLCD_D8 F9 PTC16 DISABLED PTC16 CAN1_RX UART3_RX ENET0_1588_ FB_CS5_b/ NFC_RB TMR0 FB_TSIZ1/ FB_BE23_16_ b E9 PTC17 DISABLED PTC17 CAN1_TX UART3_TX ENET0_1588_ FB_CS4_b/ NFC_CE0_b TMR1 FB_TSIZ0/ FB_BE31_24_ b M9 PTC18 DISABLED PTC18 UART3_RTS_ ENET0_1588_ FB_TBST_b/ NFC_CE1_b b TMR2 FB_CS2_b/ FB_BE15_8_b M8 PTC19 DISABLED PTC19 UART3_CTS_ ENET0_1588_ FB_CS3_b/ b TMR3 FB_BE7_0_b FB_TA_b L8 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ FTM3_CH0 b FB_ALE/ FB_CS1_b/ FB_TS_b I2S1_RXD1 F8 PTD1 ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_ FTM3_CH1 b FB_CS0_b I2S1_RXD0 K6 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FTM3_CH2 FB_AD4 I2S1_RX_FS J6 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 I2S1_RX_ BCLK K5 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ FTM0_CH4 b FB_AD2/ NFC_DATA1 EWM_IN J5 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b/ UART0_COL_ b FB_AD1/ NFC_DATA0 EWM_OUT_b K4 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FB_AD0 FTM0_FLT0 H6 PTF13 DISABLED PTF13 UART2_RX GLCD_D9 G6 PTF14 DISABLED PTF14 UART2_TX GLCD_D10 T4 VSS VSS E7 PTD7 DISABLED PTC15 ADC0_SE5b EzPort FB_AD25 UART4_TX FB_AD24 FTM0_CH6 VSS PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 K70 Sub-Family, Rev.6, 09/2015. 90 Freescale Semiconductor, Inc. Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 J4 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/ NFC_CLE F7 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17/ NFC_ALE E6 PTD10 DISABLED PTD10 UART5_RTS_ b FB_A18/ NFC_RE G5 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_ SDHC0_ b CLKIN FB_A19 GLCD_ CONTRAST F5 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 SDHC0_D4 FB_A20 GLCD_PCLK F4 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 GLCD_DE E5 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 GLCD_HFS E4 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 GLCD_VFS F6 PTF15 DISABLED PTF15 E1 PTF16 DISABLED PTF16 B1 DDR_VDD DDR_VDD DDR_VDD UART0_RTS_ b SPI2_PCS0 A1 DDR_VSS DDR_VSS DDR_VSS D3 DDR_DQS1 DISABLED DDR_DQS1 D1 DDR_DQ8 DISABLED DDR_DQ8 C1 DDR_DQ9 DISABLED DDR_DQ9 B5 DDR_VDD DDR_VDD DDR_VDD A5 DDR_VSS DDR_VSS DDR_VSS D5 DDR_VSS DDR_VSS DDR_VSS C2 DDR_DQ10 DISABLED DDR_DQ10 B2 DDR_DQ11 DISABLED DDR_DQ11 C3 DDR_DQ12 DISABLED DDR_DQ12 B8 DDR_VDD DDR_VDD DDR_VDD A12 DDR_VSS DDR_VSS DDR_VSS C4 DDR_DQ13 DISABLED DDR_DQ13 B3 DDR_DQ14 DISABLED DDR_DQ14 A2 DDR_DQ15 DISABLED DDR_DQ15 A3 DDR_DM1 DISABLED DDR_DM1 E8 DDR_VSS DDR_VSS DDR_VSS B12 DDR_VDD DDR_VDD DDR_VDD A16 DDR_VSS DDR_VSS DDR_VSS C6 DDR_VREF DDR_VREF DDR_VREF C5 DDR_DQ0 DISABLED DDR_DQ0 B4 DDR_DQ1 DISABLED DDR_DQ1 A4 DDR_DQ2 DISABLED DDR_DQ2 C16 DDR_VDD DDR_VDD DDR_VDD FTM0_CH3 EzPort GLCD_D11 UART0_CTS_ GLCD_D12 b/ UART0_COL_ b K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 91 Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 C7 DDR_VSS DDR_VSS DDR_VSS B6 DDR_DQ3 DISABLED DDR_DQ3 D6 DDR_DQ4 DISABLED DDR_DQ4 A6 DDR_DQ5 DISABLED DDR_DQ5 A7 DDR_ODT DISABLED DDR_ODT E11 DDR_VSS DDR_VSS DDR_VSS D2 DDR_VDD DDR_VDD DDR_VDD C9 DDR_VSS DDR_VSS DDR_VSS B7 DDR_DQ6 DISABLED DDR_DQ6 A8 DDR_DQ7 DISABLED DDR_DQ7 C8 DDR_DQS0 DISABLED DDR_DQS0 D9 DDR_DM0 DISABLED DDR_DM0 D4 DDR_VDD DDR_VDD DDR_VDD C14 DDR_VSS DDR_VSS DDR_VSS A9 DDR_BA0 DISABLED DDR_BA0 B10 DDR_BA1 DISABLED DDR_BA1 B9 DDR_BA2 DISABLED DDR_BA2 A10 DDR_CKB DISABLED DDR_CKB A11 DDR_CK DISABLED DDR_CK D7 DDR_VDD DDR_VDD DDR_VDD D8 DDR_VSS DDR_VSS DDR_VSS D10 DDR_A0 DISABLED DDR_A0 C11 DDR_A1 DISABLED DDR_A1 B11 DDR_A2 DISABLED DDR_A2 C12 DDR_A3 DISABLED DDR_A3 E10 DDR_VDD DDR_VDD DDR_VDD D12 DDR_VSS DDR_VSS DDR_VSS C10 DDR_A4 DISABLED DDR_A4 A13 DDR_A5 DISABLED DDR_A5 A14 DDR_A6 DISABLED DDR_A6 D11 DDR_A7 DISABLED DDR_A7 A15 DDR_A8 DISABLED DDR_A8 E12 DDR_VDD DDR_VDD DDR_VDD E3 DDR_VSS DDR_VSS DDR_VSS B16 DDR_CKE DISABLED DDR_CKE B15 DDR_A9 DISABLED DDR_A9 B13 DDR_A10 DISABLED DDR_A10 B14 DDR_A11 DISABLED DDR_A11 C15 DDR_A12 DISABLED DDR_A12 D16 DDR_A13 DISABLED DDR_A13 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K70 Sub-Family, Rev.6, 09/2015. 92 Freescale Semiconductor, Inc. Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 D15 DDR_A14 DISABLED DDR_A14 E16 DDR_RAS_B DISABLED DDR_RAS_B C13 DDR_CAS_B DISABLED DDR_CAS_B D14 DDR_CS_B DISABLED DDR_CS_B D13 DDR_WE_B DISABLED DDR_WE_B ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 8.3 K70 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 93 Revision History 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DDR_VSS DDR_DQ15 DDR_DM1 DDR_DQ2 DDR_VSS DDR_DQ5 DDR_ODT DDR_DQ7 DDR_BA0 DDR_CKB DDR_CK DDR_VSS DDR_A5 DDR_A6 DDR_A8 DDR_VSS A B DDR_VDD DDR_DQ11 DDR_DQ14 DDR_DQ1 DDR_VDD DDR_DQ3 DDR_DQ6 DDR_VDD DDR_BA2 DDR_BA1 DDR_A2 DDR_VDD DDR_A10 DDR_A11 DDR_A9 DDR_CKE B C DDR_DQ9 DDR_DQ10 DDR_DQ12 DDR_DQ13 DDR_DQ0 DDR_VREF DDR_VSS DDR_DQS0 DDR_VSS DDR_A4 DDR_A1 DDR_A3 DDR_CAS_B DDR_VSS DDR_A12 DDR_VDD C D DDR_DQ8 DDR_VDD DDR_DQS1 DDR_VDD DDR_VSS DDR_DQ4 DDR_VDD DDR_VSS DDR_DM0 DDR_A0 DDR_A7 DDR_VSS DDR_WE_B DDR_CS_B DDR_A14 DDR_A13 D E PTF16 PTE0 DDR_VSS PTD15 PTD14 PTD10 PTD7 DDR_VSS PTC17 F PTF17 PTE1/ LLWU_P0 PTE2/ LLWU_P1 PTD13 PTD12 PTF15 PTD9 PTD1 PTC16 PTC15 PTC9 G PTF18 PTE3 PTE4/ LLWU_P2 PTE5 PTD11 PTF14 VDD VDD VDD VDD PTC10 PTC7 H PTF19 PTE6 PTE7 PTE8 PTF20 PTF13 VDDINT VSS VSS VDDINT PTC11/ LLWU_P11 J PTE9 PTE10 PTE16 PTD8 PTD5 PTD3 VDD VSS VSS VDD K PTE11 PTE17 PTE12 PTE27 VSS VSS L VOUT33 VSS VREGIN PTE18 TAMPER2 PTE28 PTD0/ LLWU_P12 M USB0_DP USB0_DM PTE19 VREFL TAMPER0/ TAMPER7 RTC_ WAKEUP_B PTE26 PTD6/ PTD4/ PTD2/ LLWU_P15 LLWU_P14 LLWU_P13 TAMPER1 DDR_VDD DDR_VSS DDR_VDD PTC3/ LLWU_P7 PTC6/ PTC1/ LLWU_P10 LLWU_P6 PTC4/ LLWU_P8 PTC5/ LLWU_P9 DDR_RAS_B E PTC2 PTF7 PTF8 F PTB20 PTB21 PTB22 PTC0 G PTC8 PTB17 PTB18 PTB19 PTB23 H PTC14 PTC12 PTB10 PTB11 PTB16 PTF6 J VDD PTF11 PTF9 PTC13 PTB8 PTB9 PTF5 K VSS VDD PTF12 PTF10 PTF1 PTB6 PTB7 PTF4 L PTC19 PTC18 PTA12 PTB1 PTB0/ LLWU_P5 PTA26 PTB3 PTB5 PTF3 M N PGA2_DP/ PGA2_DM/ ADC0_SE16/ ADC2_DP0/ ADC2_DM0/ CMP1_IN2/ ADC3_DP3/ ADC3_DM3/ ADC0_SE21 ADC0_DP1 ADC0_DM1 VSSA VDDA TAMPER6 VSS PTA1 PTF22 PTA13/ LLWU_P4 PTA16 PTA8 PTA24 PTA29 PTB4 PTF2 N P PGA3_DP/ PGA3_DM/ ADC1_SE16/ ADC3_DP0/ ADC3_DM0/ CMP2_IN2/ ADC2_DP3/ ADC2_DM3/ ADC0_SE22 ADC1_DP1 ADC1_DM1 VREFH VBAT TAMPER4 PTE24 PTA3 PTF21 PTF23 PTA15 PTA7 PTA10 PTA28 PTB2 PTF0 P R DAC1_OUT/ PGA0_DP/ PGA0_DM/ DAC0_OUT/ CMP0_IN4/ ADC0_DP0/ ADC0_DM0/ CMP1_IN3/ TAMPER3 CMP2_IN3/ ADC1_DP3 ADC1_DM3 ADC0_SE23 ADC1_SE23 TAMPER5 PTE25 PTA4/ LLWU_P3 PTF25 PTF24 PTA14 PTA6 PTA11 PTA25 PTA27 RESET_b R T VREF_OUT/ PGA1_DP/ PGA1_DM/ CMP1_IN5/ ADC1_DP0/ ADC1_DM0/ CMP0_IN5/ ADC0_DP3 ADC0_DM3 ADC1_SE18 T 1 2 3 VSS EXTAL32 XTAL32 PTA0 PTA2 PTF26 PTF27 PTA17 PTA5 PTA9 VSS PTA18 PTA19 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 48. K70 256 MAPBGA Pinout Diagram 9 Revision History The following table provides a revision history for this document. K70 Sub-Family, Rev.6, 09/2015. 94 Freescale Semiconductor, Inc. Revision History Table 63. Revision History Rev. No. Date Substantial Changes 3 3/2012 Initial public release 4 10/2012 Replaced TBDs throughout. 5 10/2013 Changes for 4N96B mask set: * Min VDD operating requirement specification updated to support operation down to 1.71V. New specifications: * Updated Vdd_ddr min specification. * Added Vodpu specification. * Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specfications. They have been replaced by new Iina, Iind, and Zind specifications. * Fpll_ref_acc specification has been added. * I2C module was previously covered by the general switching specifications. To provide more detail on I2C operation a dedicated Inter-Integrated Circuit Interface (I2C) timing section has been added. Modified specifications: * * * * Vref_ddr max spec has been updated. Tpor spec has been split into two specifications based on VDD slew rate. Trd1allx and Trd1alln max have been updated. 16-bit ADC Temp sensor slope and Temp sensor voltage (Vtemp25) have been modified. The typical values that were listed previously have been updated, and min and max specifications have been added. Corrections: * Some versions of the datasheets listed incorrect clock mode information in the "Diagram: Typical IDD_RUN operating behavior section." These errors have been corrected. * Fintf_ft specification was previously shown as a max value. It has been corrected to be shown as a typical value as originally intended. * Corrected DDR write and read timing diagrams to show the correct location of the Tcmv specification. * SDHC peripheral 50MHz high speed mode options were left out of the last datasheet. These have been added to the SDHC specifications section. 6 09/2015 * Updated Power Sequencing section * Added footnote to ambient temperature specification of Thermal Operating requirements * Updated the data and DQS waveforms in DDR read timing diagram * Removed "USB HS/LS/FS on-the-go controller with on-chip high speed transceiver" from features section * Updated Terminology and guidelines section * Updated the footnotes and the values of Power consumption operating behaviors table * Added Notes in USB electrical specification section * Updated I2C timing table K70 Sub-Family, Rev.6, 09/2015. Freescale Semiconductor, Inc. 95 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. 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