1
LT1241 Series
The LT
®
1241 series devices are 8-pin, fixed frequency,
current mode, pulse width modulators. They are improved
plug compatible versions of the industry standard UC1842
series. These devices have both improved speed and
lower quiescent current. The LT1241 series is optimized
for off-line and DC/DC converter applications. They con-
tain a temperature-compensated reference, high gain er-
ror amplifier, current sensing comparator and a high
current totem pole output stage ideally suited to driving
power MOSFETs. Start-up current has been reduced to
less than 250µA. Cross-conduction current spikes in
the output stage have been eliminated, making 500kHz
operation practical. Several new features have been incor-
porated. Leading edge blanking has been added to the
current sense comparator. Trims have been added to the
oscillator circuit for both frequency and sink current, and
both of these parameters are tightly specified. The output
stage is clamped to a maximum V
OUT
of 18V in the
on state. The output and the reference output are actively
pulled low during undervoltage lockout.
High Speed Current Mode
Pulse Width Modulators
■
Low Start-Up Current: < 250µA
■
50ns Current Sense Delay
■
Current Mode Operation: To 500kHz
■
Pin Compatible with UC1842 Series
■
Undervoltage Lockout with Hysteresis
■
No Cross-Conduction Current
■
Trimmed Bandgap Reference
■
1A Totem Pole Output
■
Trimmed Oscillator Frequency and Sink Current
■
Active Pull-Down on Reference and Output During
Undervoltage Lockout
■
High Level Output Clamp: 18V
■
Current Sense Leading Edge Blanking
D
U
ESCRIPTIO
S
FEATURE
U
S
A
O
PPLICATI
■
Off-Line Converters
■
DC/DC Converters
, LTC and LT are registered trademarks of Linear Technology Corporation.
+
–
+
–
1
2
FB
COMP
2.5V
2R
R
1V
1.5V
–
+
3
I
SENSE
BLANKING
1mA
5.6V
4
R
T
/C
T
OSCILLATOR
R
S
18V
7V
CC
5 GND
6 OUTPUT
8V
REF
5V REF
MAIN BIAS
REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
1241 BD01
T
UV
LOCKOUT
W
IDAGRA
B
L
O
C
K
LT1241 Series
2
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Section
Output Voltage I
O
= 1mA, T
J
= 25°C 4.925 5.000 5.075 V
Line Regulation 12V < V
CC
< 25V ●320mV
Load Regulation 1mA < I
VREF
< 20mA ●–6 –25 mV
Temperature Stability 0.1 mV/°C
Total Output Variation Line, Load, Temp ●4.87 5.13 V
Output Noise Voltage 10Hz < F < 10kHz, T
J
= 25°C50µV
Long Term Stability T
A
= 125°C, 1000 Hrs. 5 25 mV
Output Short-Circuit Current ●–30 –90 –180 mA
Oscillator Section
Initial Accuracy R
T
= 10k, C
T
= 3.3nF, T
J
= 25°C 47.5 50 52.5 kHz
R
T
= 13.0k, C
T
= 500pF, T
J
= 25°C 228 248 268 kHz
Voltage Stability 12V < V
CC
< 25V, T
J
= 25°C1%
Temperature Stability T
MIN
< T
J
< T
MAX
–0.05 %/°C
Amplitude T
J
= 25°C (Pin 4) 1.7 V
Clock Ramp Reset Current V
OSC
(Pin 4) = 2V, T
J
= 25°C 7.9 8.2 8.5 mA
Error Amplifier Section
Feedback Pin Input Voltage V
PIN1
= 2.5V ●2.42 2.50 2.58 V
Input Bias Current V
FB
= 2.5V ●–2 µA
Open-Loop Voltage Gain 2 < V
O
< 4V ●65 90 dB
Unity-Gain Bandwidth T
J
= 25°C 0.7 1.3 2 MHz
Power Supply Rejection Ratio 12V < V
CC
< 25V ●60 dB
Output Sink Current V
PIN2
= 2.7V, V
PIN1
= 1.1V ●26 mA
Output Source Current V
PIN2
= 2.3V, V
PIN1
= 5V ●–0.5 –0.75 mA
ELECTRICAL C CHARA TERISTICS
(Notes 1, 2)
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
I
S
Supply Voltage ........................................................ 25V
Output Current....................................................... ±1A*
Output Energy (Capacitive Load per Cycle)...............5µJ
Analog Inputs (Pins 2, 3)...............................–0.3 to 6V
Error Amplifier Output Sink Current...................... 10mA
Power Dissipation at T
A
≤ 25°C ................................ 1W
Operating Junction Temperature Range
LT124XC ............................................. 0°C to 100°C
LT124XI......................................... – 40°C to 100°C
LT124XM........................................ –55°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
*The 1A rating for output current is based on transient switching
requirements.
ORDER PART
NUMBER
LT124XCJ8
LT124XCN8
LT124XCS8
LT124XIN8
LT124XIS8
LT124XMJ8
S8 PART MARKING
124X
124XI
WU
U
PACKAGE/ORDER I FOR ATIO
COMP
FB
I
SENSE
R
T
/C
T
V
REF
V
CC
OUTPUT
GND
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
J8 PACKAGE
8-LEAD CERDIP
1
2
3
4
8
7
6
5
TOP VIEW
T
JMAX
= 125°C, θ
JA
= 100°C/W (J8)
T
JMAX
= 100°C, θ
JA
= 130°C/W (N8)
T
JMAX
= 100°C, θ
JA
= 150°C/W (S8)
3
LT1241 Series
PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amplifier Section
Output Voltage High Level V
PIN2
= 2.3V, R
L
= 15k to GND ●5 5.6 V
Output Voltage Low Level V
PIN2
= 2.7V, R
L
= 15k to Pin 8 ●0.2 1.1 V
Current Sense Section
Gain ●2.85 3.00 3.15 V/V
Maximum Current Sense Input Threshold V
PIN3
< 1.1V ●0.90 1.00 1.10 V
Power Supply Rejection Ratio ●70 dB
Input Bias Current ●–1 10 µA
Delay to Output ●50 100 ns
Blanking Time 100 ns
Blanking Override Voltage 1.5 V
Output Section
Output Low Level I
OUT
= 20mA ●0.25 0.4 V
I
OUT
= 200mA ●0.75 2.2 V
Output High Level I
OUT
= 20mA ●12.0 V
I
OUT
= 200mA ● 11.75 V
Rise Time C
L
= 1nF, T
J
= 25°C5080ns
Fall Time C
L
= 1.0nF, T
J
= 25°C3060ns
Output Clamp Voltage I
O
= 1mA ●18 19.5 V
Undervoltage Lockout
Start-Up Threshold
LT1241 ●9.0 9.6 10.2 V
LT1242/LT1244 ●15 16 17 V
LT1243/LT1245 ●7.8 8.4 9.0 V
Minimum Operating Voltage
LT1241/LT1243/LT1245 ●7.0 7.6 8.2 V
LT1242/LT1244 ●9.0 10 11 V
Hysteresis
LT1241 1.6 2.0 V
LT1242/LT1244 5.5 6.0 V
LT1243/LT1245 0.4 0.8 V
PWM
Maximum Duty Cycle
LT1241/LT1244/LT1245 T
J
= 25°C4648%
LT1242/LT1243 T
J
= 25°C9496%
Minimum Duty Cycle ●0%
Total Device
Start-Up Current ●170 250 µA
Operating Current ●710 mA
The ● denotes those specifications which apply over the full operating
temperature range.
Note 1: Unless otherwise specified, V
CC
= 15V, R
T
= 10k, C
T
= 3.3nF.
(Notes 1, 2)
ELECTRICAL C CHARA TERISTICS
Note 2: Low duty cycle pulse techniques are used during test to maintain
junction temperature close to ambient.
LT1241 Series
4
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Undervoltage Lockout – Undervoltage Lockout –
Undervoltage Lockout – LT1241 LT1242, LT1244 LT1243, LT1245
Supply Current vs
Oscillator Frequency Oscillator Frequency Oscillator Sink Current
TEMPERATURE (°C)
–50
6
V
CC
(V)
7
8
9
10
11
–25 25 75 125
LT1241 • TPC01
0 50 100
MINIMUM OPERATING VOLTAGE
START-UP THRESHOLD
TEMPERATURE (°C)
–50
9
VCC (V)
10
11
16
17
–25 25 75 125
LT1241 • TPC02
0 50 100
MINIMUM OPERATING VOLTAGE
START-UP THRESHOLD
15
TEMPERATURE (°C)
–50
6
V
CC
(V)
7
8
9
10
11
–25 25 75 125
LT1241 • TPC03
0 50 100
MINIMUM OPERATING VOLTAGE
START-UP THRESHOLD
TEMPERATURE (°C)
–50
5
I
CC
(mA)
6
7
8
9
10
–25 25 75 125
LT1241 • TPC06
0 50 100
V
CC
= 15V
R
T
= 10k
C
T
= 3300pF
TEMPERATURE (°C)
–50
0
START-UP CURRENT (µA)
40
80
120
160
200
–25 25 75 125
LT1241 • TPC05
0 50 100
180
140
100
60
20
Start-Up Current Start-Up Current Supply Current
V
CC
(V)
0
0
START-UP CURRENT (µA)
50
100
150
200
2 8 12 18
LT1241 • TPC04
410146 16
LT1241 LT1242/4
LT1243/5
T
J
= 25°C
START-UP
THRESHOLD
OSCILLATOR FREQUENCY (Hz)
10k
0
SUPPLY CURRENT (mA)
2
3
5
7
8
10
100k 1M
LT1241 • TPC18
9
6
4
1
LT1242, LT1243
LT1241, LT1244, LT1245
V
CC
= 15V
R
T
= 10k
C
L
= 15pF
TEMPERATURE (°C)
–50
40
FREQUENCY (kHz)
44
48
52
56
60
–25 25 75 125
LT1241 • TPC07
0 50 100
42
46
50
54
58 VCC = 5V
RT = 10k
CT = 3300pF
TEMPERATURE (°C)
–50
7.7
OSCILLATOR SINK CURRENT (mA)
8.7
–25 25 75 125
LT1241 • TPC08
0 50 100
7.8
8.0
8.2
8.4
8.6
8.5
7.9
8.1
8.3
V
PIN4
= 2V
5
LT1241 Series
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Error Amplifier Open-Loop Gain
and Phase Current Sense Clamp Voltage Current Sense Input Threshold
Low Level Output Saturation
High Level Output Low Level Output Voltage During Undervoltage
Saturation Voltage Saturation Voltage Lockout
TEMPERATURE (°C)
–50
20
REFERENCE SHORT-CIRCUIT CURRENT (mA)
140
–25 25 75 125
LT1241 • TPC09
0 50 100
40
80
100
120
60
TEMPERATURE (°C)
–50
4.95
REFERENCE VOLTAGE (V)
5.05
–25 25 75 125
LT1241 • TPC10
0 50 100
4.96
5.00
5.01
4.97
4.98
4.99
5.02
5.03
5.04 IO = 1mA
Reference Voltage Reference Short-Circuit Current Feedback Pin Input Voltage
TEMPERATURE (°C)
–50
2.45
FEEDBACK PIN INPUT VOLTAGE (V)
2.55
–25 25 75 125
LT1241 • TPC11
0 50 100
2.46
2.50
2.51
2.47
2.48
2.49
2.52
2.53
2.54
ERROR AMP OUTPUT VOLTAGE (V)
0
0
CURRENT SENSE INPUT THRESHOLD (V)
1.2
36
LT1241 • TPC17
0.6
0.2
0.4
0.8
1.0
12 45
T
J
= –55°C
T
J
=125°C
T
J
= 25°C
TEMPERATURE (°C)
–50
0.95
CURRENT SENSE CLAMP VOLTAGE (V)
1.05
–25 25 75 125
LT1241 • TPC12
0 50 100
0.96
1.00
1.01
0.97
0.98
0.99
1.02
1.03
1.04
FREQUENCY (Hz)
10
–20
A
VOL
OPEN-LOOP VOLTAGE GAIN (dB)
100
10k 10M
LT1241 • TPC16
40
0
20
60
80
100 1k 100k 1M
PHASE
GAIN
V
CC
= 15V
V
O
= 2.0V - 4.0V
R
L
= 100k
T
A
= 25°C
PHASE (DEG)
180
–45
225
90
0
45
135
OUTPUT SOURCE CURRENT (mA)
0
0
OUTPUT SATURATION VOLTAGE (V)
4.0
200
LT1241 • TPC13
0.5
2.0
2.5
1.0
1.5
3.0
3.5
T
J
= –55°C
T
J
= 25°C
T
J
= 125°C
100
OUTPUT SINK CURRENT (mA)
0
0
OUTPUT SATURATION VOLTAGE (V)
1.0
100 200
LT1241 • TPC14
T
J
= –55°C
T
J
= 25°C
T
J
= 125°C
0.5
OUTPUT SINK CURRENT (mA)
0
0
OUTPUT SATURATION VOLTAGE (V)
4.0
510
LT1241 • TPC15
2.0
0.5
1.0
1.5
2.5
3.0
3.5
T
J
= 125°C
T
J
= –55°C
T
J
= 25°C
LT1241 Series
6
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
OSCILLATOR FREQUENCY (kHz)
0
0
% OF DEADTIME
10
20
30
40
50
60
100 1000
LT1241 • TPC19
5nF 2nF 1nF
100pF
500pF
TIME 50ns/DIV
LT1241 • TPC22
OUTPUT VOLTAGE
Output Rise and Fall Time Output Cross-Conduction Current Current Sense Delay
OUTPUT
VOLTAGE
5V/DIV
CURRENT
SENSE INPUT
1V/DIV
TIME 50ns/DIV
LT1241 • TPC24
TIME 50ns/DIV
LT1241 • TPC23
OUTPUT
VOLTAGE
5V/DIV
OUTPUT CROSS-
CONDUCTION CURRENT
20mA/DIV
Output Deadtime vs Oscillator Output Deadtime vs Oscillator Timing Resistor vs Oscillator
Frequency – LT1242, LT1244 Frequency – LT1241, LT1243,LT1245 Frequency
OSCILLATOR FREQUENCY (kHz)
0
50
% OF DEADTIME
55
60
65
70
75
100 1000
LT1241 • TPC20
5nF 2nF
500pF
100pF
10nF 1nF
OSCILLATOR FREQUENCY (Hz)
10k
1
R
T
(kΩ)
10
100
100k 1M
LT1241 • TPC21
5nF
2nF
500pF
100pF
C
T
=10nF
1nF
200pF
V
CC
= 15V
T
J
= 25°C
VCC = 15V
CL = 1nF VCC = 15V
CL = 15pF VCC = 15V
CL = 1nF
7
LT1241 Series
PI
U
FU
U
C
U
S
O
TI
COMP (Pin 1): Compensation Pin. This pin is the output of
the Error Amplifier and is made available for loop compen-
sation. It can also be used to adjust the maximum value of
the current sense clamp voltage to less than 1V. This pin
can source a minimum of 0.5mA (0.8mA typ) and sink a
minimum of 2mA (4mA typ)
FB (Pin 2) Voltage Feedback Pin. This pin is the inverting
input of the error amplifier. The output voltage is normally
fed back to this pin through a resistive divider. The non-
inverting input of the error amplifier is internally commit-
ted to a 2.5V reference point.
I
SENSE
(Pin 3): Current Sense Pin. This is the input to the
current sense comparator. The trip point of the compara-
tor is set by, and is proportional to, the output voltage of
the Error Amplifier.
R
T
/C
T
(Pin 4): The oscillator frequency and the deadtime
are set by connecting a resistor (R
T
) from V
REF
to R
T
/C
T
and a capacitor (C
T
) from R
T
/C
T
to GND.
The rise time of the oscillator waveform is set by the RC
time constant of R
T
and C
T
. The fall time, which is equal to
the output deadtime, is set by a combination of the RC time
constant and the oscillator sink current (8.2mA typ).
GND (Pin 5): Ground.
OUTPUT (Pin 6): This pin is the output of a high current
totem pole output stage. It is capable of driving up to ±1A
of current into a capacitive load such as the gate of a
MOSFET.
V
CC
(Pin 7): This pin is the positive supply of the control
IC.
V
REF
(Pin 8): Reference. This is the reference output of the
IC. The reference output is used to supply charging current
to the external timing resistor R
T
. The reference provides
biasing to a large portion of the internal circuitry, and is
used to generate several internal reference levels includ-
ing the V
FB
level and the current sense clamp voltage.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
MINIMUM
START-UP OPERATING MAXIMUM
DEVICE THRESHOLD VOLTAGE DUTY CYCLE REPLACES
LT1241 9.6V 7.6V 50% NONE
LT1242 16V 10V 100% UC1842
LT1243 8.4V 7.6V 100% UC1843
LT1244 16V 10V 50% UC1844
LT1245 8.4V 7.6V 50% UC1845
Oscillator
The LT1241 series devices are fixed frequency current
mode pulse width modulators. The oscillator frequency
and the oscillator discharge current are both trimmed and
tightly specified to minimize the variations in frequency
and deadtime. The oscillator frequency is set by choosing
a resistor and capacitor combination, R
T
and C
T
. This RC
combination will determine both the frequency and the
maximum duty cycle. The resistor R
T
is connected from
V
REF
(Pin 8) to the R
T
/C
T
pin (Pin 4). The capacitor C
T
is
connected from the R
T
/C
T
pin to ground. The charging
current for C
T
is determined by the value of R
T
. The
discharge current for C
T
is set by the difference between
the current supplied by R
T
and the discharge current of the
LT124X. The discharge current of the device is trimmed to
8.2mA. For large values of R
T
discharge time will be
determined by the discharge current of the device and the
value of C
T
. As the value of R
T
is reduced it will have more
effect on the discharge time of C
T
. During an oscillator
cycle capacitor C
T
is charged to approximately 2.8V and
discharged to approximately 1.1V. The output is enabled
during the charge time of C
T
and disabled, in an off state,
during the discharge time of C
T
. The deadtime of the circuit
is equal to the discharge time of C
T
. The maximum duty
cycle is limited by controlling the deadtime of the oscilla-
tor. There are many combinations of R
T
and C
T
that will
yield a given oscillator frequency, however there is only
one combination that will yield a specific deadtime at that
frequency. Curves of oscillator frequency and deadtime
LT1241 Series
8
for various values of R
T
and C
T
appear in the Typical
Performance Characteristics section. Frequency and
deadtime can also be calculated using the following
formulas:
Oscillator Rise Time: t
r
= 0.583 • RC
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Oscillator Discharge Time:
Oscillator Frequency:
Oscillator Period: T
OSC
= t
r
+ t
d
frequency for LT1241, LT1244 and LT1245. The oscillator
of LT1241 series devices will run at frequencies up to
1MHz, allowing 500kHz output switching frequencies for
all devices.
Error Amplifier
The LT1241 series of devices contain a fully compensated
error amplifier with a DC gain of 90dB and a unity-gain
frequency of 1MHz. Phase margin at unity-gain is 80°. The
noninverting input is internally committed to a 2.5V refer-
ence point derived from the 5V reference of Pin 8. The
inverting input (Pin 2) and the output (Pin 1) are made
available to the user. The output voltage in a regulator
circuit is normally fed back to the inverting input of the
error amplifier through a resistive divider.
The output of the error amplifier is made available for
external loop compensation. The output current of the
error amplifier is limited to approximately 0.8mA sourcing
and approximately 6mA sinking. In a current mode PWM
the peak switch current is a function of the output voltage
of the error amplifier. In the LT1241 series devices the
output of the error amplifier is offset by two diodes (1.4V
at 25°C), divided by a factor of three, and fed to the
inverting input of the current sense comparator. For error
amplifier output voltages less than 1.4V the duty cycle of
the output stage will be zero. The maximum offset that can
appear at the current sense input is limited by a 1V clamp.
This occurs when the error amplifier output reaches 4.4V
at 25°C.
The output of the error amplifier can be clamped below
4.4V in order to reduce the maximum voltage allowed
across the current sensing resistor to less than 1V. The
supply current will increase by the value of the output
source current when the output voltage of the error
amplifier is clamped.
tRC
R
d=•
()
−
346
0 0164 11 73
.
..
f
T
OSC OSC
=1
Maximum Duty Cycle:
LT1241, LT1244, LT1245
Dt
T
Tt
T
MAX r
OSC
OSC d
OSC
==
−
22
LT1242, LT1243
The above formulas will give values that will be accurate
to approximately ±5%, at the oscillator, over the full
operating frequency range. This is due to the fact that the
oscillator trip levels are constant versus frequency and the
discharge current and initial oscillator frequency are
trimmed. Some fine adjustment may be required to achieve
more accurate results. Once the final R
T
/C
T
combination is
selected the oscillator characteristics will be repeatable
from device to device. Note that there will be some slight
differences between maximum duty cycle at the oscillator
and maximum duty cycle at the output due to the finite rise
and fall times of the output.
The output switching frequency will be equal to the
oscillator frequency for LT1242 and LT1243. The output
switching frequency will be equal to one-half the oscillator
Dt
T
Tt
T
MAX r
OSC
OSC d
OSC
==−
9
LT1241 Series
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
change in the error amplifier output voltage. The threshold
voltage will be 0.333V for an error amplifier voltage of
2.4V. To reduce the maximum current sense threshold to
less than 1V the error amplifier output should be clamped
to less than 4.4V.
Blanking
A unique feature of the LT1241 series devices is the built-
in blanking circuit at the output of the current sense
comparator. A common problem with current mode
PWM circuits is erratic operation due to noise at the
current sense input. The primary cause of noise problems
is the leading edge current spike due to transformer
interwinding capacitance and diode reverse recovery
time. This current spike can prematurely trip the current
sense comparator causing an instability in the regulator
circuit. A filter at the current sense input is normally
required to eliminate this instability.
This filter will in turn slow down the current sense loop.
A slow current sense loop will increase the minimum pulse
width which will increase the short-circuit current in an
overload condition. The LT1241 series devices blank (lock
out) the signal at the output of the current sense compara-
tor for a fixed amount of time after the switch is turned on.
This effectively prevents the PWM latch from tripping due
to the leading edge current spike.
The blanking time will be a function of the voltage at the
feedback pin (Pin 2). The blanking time will be 100ns for
normal operating conditions (V
FB
= 2.5V). The blanking
time goes to zero as the feedback pin is pulled to 0V. This
means that the blanking time will be minimized during
start-up and also during an output short-circuit fault. This
blanking circuit eliminates the need for an input filter at the
current sense input except in extreme cases. Eliminating
the filter allows the current sense loop to operate with
minimum delays, reducing peak currents during fault
conditions.
Current Sense Comparator and PWM Latch
LT1241 series devices are current mode controllers.
Under normal operating conditions the output (Pin 6) is
turned on at the start of every oscillator cycle, coincident
with the rising edge of the oscillator waveform. The output
is then turned off when the current reaches a threshold
level proportional to the error voltage at the output of the
error amplifier. Once the output is turned off it is latched
off until the start of the next cycle. The peak current is thus
proportional to the error voltage and is controlled on a
cycle by cycle basis. The peak switch current is normally
sensed by placing a sense resistor in the source lead of the
output MOSFET. This resistor converts the switch current
to a voltage that can be fed into the current sense input. For
normal operating conditions the peak inductor current,
which is equal to the peak switch current, will be equal to:
IVV
R
PK PIN
S
=−
()
()
1
14
3
.
During fault conditions the maximum threshold voltage at
the input of the current sense comparator is limited by the
internal 1V clamp at the inverting input. The peak switch
current will be equal to:
IV
R
PK MAX S
()
.
=
10
In certain applications, such as high power regulators, it
may be desirable to limit the maximum threshold voltage
to less than 1V in order to limit the power dissipated in the
sense resistor or to limit the short-circuit current of the
regulator circuit. This can be accomplished by clamping
the output of the error amplifier. A voltage level of
approximately 1.4V at the output of the error amplifier will
give a threshold voltage of 0V. A voltage level of approxi-
mately 4.4V at the output of the error amplifier will give
a threshold level of 1V. Between 1.4V and 4.4V the
threshold voltage will change by a factor of one-third of the
LT1241 Series
10
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Undervoltage Lockout
The LT1241 series devices incorporate an undervoltage
lockout comparator which prevents the internal reference
circuitry and the output from starting up until the supply
voltage reaches the start-up threshold voltage. The quies-
cent current, below the start-up threshold, has been
reduced to less than 250µA (170µA typ.) to minimize the
power loss due to the bleed resistor used for start-up in
off-line converters. In undervoltage lockout both V
REF
(Pin 8) and the output (Pin 6) are actively pulled low by
Darlington connected PNP transistors. They are designed
to sink a few milliamps of current and will pull down to
about 1V. The pull-down transistor at the reference pin can
be used to reset the external soft start capacitor. The pull-
down transistor at the output eliminates the external pull-
down resistor required, with earlier devices, to hold the
external MOSFET gate low during undervoltage lockout.
Output
The LT1241 series devices incorporate a single high
current totem pole output stage. This output stage is
capable of driving up to ±1A of output current. Cross-
conduction current spikes in the output totem pole have
been eliminated. This device is primarily intended for
driving MOSFET switches. Rise time is typically 40ns and
fall time is typically 30ns when driving a 1.0nF load. A
clamp is built into the device to prevent the output from
rising above 18V in order to protect the gate of the
MOSFET switch.
The output is actively pulled low during undervoltage
lockout by a Darlington PNP. This PNP is designed to sink
several milliamps and will pull the output down to approxi-
mately 1V. This active pull-down eliminates the need for an
external resistor which was required in older designs. The
output pin of the device connects directly to the emitter of
the upper NPN drive transistor and the collector of the
lower NPN drive transistor in the totem pole. The collector
of the lower transistor, which is n-type silicon, forms a
p-n junction with the substrate of the device. This junction
is reverse biased during normal operation.
In some applications the parasitic LC of the external
MOSFET gate can ring and pull the OUTPUT pin below
ground. If the OUTPUT pin is pulled negative by more than
a diode drop the parasitic diode formed by the collector of
the output NPN and the substrate will turn on. This can
cause erratic operation of the device. In these cases a
Schottky clamp diode is recommended from the output to
ground.
Reference
The internal reference of the LT1241 series devices is a 5V
bandgap reference, trimmed to within ±1% initial toler-
ance. The reference is used to power the majority of
internal logic and the oscillator circuitry. The oscillator
charging current is supplied from the reference. The
feedback pin voltage and the clamp level for the current
sense comparator are derived from the reference voltage.
The reference can supply up to 20mA of current to power
external circuitry. Note that using the reference in this
manner, as a voltage regulator, will significantly increase
power dissipation in the device which will reduce the
useful operating ambient temperature range.
Design/Layout Considerations
LT1241 series devices are high speed circuits capable of
generating pulsed output drive currents of up to 1A peak.
The rise and fall time for the output drive current is in the
range of 10ns to 20ns. High speed circuit techniques must
be used to insure proper operation of the device. Do not
attempt to use Proto-boards or wire-wrap techniques to
breadboard high speed switching regulator circuits.
They
will not
work properly.
Printed circuit layouts should include separate ground
paths for the voltage feedback network, oscillator capaci-
tor, and switch drive current. These ground paths should
be connected together directly at the ground pin (Pin 5) of
the LT124X. This will minimize noise problems due to
pulsed ground pin currents. V
CC
should be bypassed, with
a minimum of 0.1µF, as close to the device as possible.
High current paths should be kept short and they should
be separated from the feedback voltage network with
shield traces if possible.
11
LT1241 Series
U
SA
O
PPLICATITYPICAL
LT1241 • TA01
5V REF
OSCILLATOR
EXTERNAL
SYNC
INPUT 0.01µF
47Ω
C
T
D1
R
T
R
T
/C
T
V
REF
D1 IS REQUIRED IF THE SYNC AMPLITUDE IS LARGE
ENOUGH TO PULL THE BOTTOM OF C
T
MORE THAN
300mV BELOW GROUND.
8
4
+
+
–
+
–
1
2
–
+
3
LT1241 • TA02
R
V
REF
FB
COMP
I
SENSE
C
2.5V
2R
R
1V
1.5V
1mA
5.6V
85V REF
+
–
+
–
2
–
+
4
1
8
7
5
6
LT1241 • TA03
FB
COMP
R
T
/C
T
V
REF
V
IN
R
S
R2
CR1
V
CLAMP
≈ 1.67
R2 + 1
R1
(
(
I
PK (MAX)
≈ V
CLAMP
R
S
WHERE: 0V ≤ V
CLAMP
≤ 1.0V t
SOFT START
= –ln
1 – V
C
C R1 R2
3 • V
CLAMP
R1 + R2
I
SENSE
2.5V
2R
R
1V
1.5V
BLANKING
1mA
5.6V
OSCILLATOR
R
S
18V
V
CC
UV
LOCKOUT
GND
OUTPUT
5V REF
MAIN BIAS REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
T
3
100k
External Clock Synchronization Soft Start
Adjustable Clamp Level with Soft Start
LT1241 Series
12
300kHz Off-Line Power Supply
U
SA
O
PPLICATITYPICAL
LT1241 • TA06
HOT
NEU
90VAC
TO
240VAC
R5
1M
1/2W
C2
0.1µF
250V
MP3-X2
24
13
T1
BALEN
C3
0.1µF
250V
MP3-X2
C4
4700pF
250V
Y-CAP
D5
–+
2KBPO8M
C5
4700pF
250V
Y-CAP
AC GND
C6
4700pF
250V
Y-CAP
R1
200k
1/2W
+
C14
100µF
400V
R
T1
MCID404
2KBPOO5M
R3
200k
1/2W
D6
1N5245B
15V
R2
660k
1/10W
R4
660k
1/10W
C1
470pF
R5
27k
2W
D1
MUR160
30T8
2
13T3
6
30T7
1
R7
510 
1/10W
C7
0.22µF
MKS-2
R8
152k
C8
100pF
D7
BAV21
V
CC
GND
R
T
/C
T
V
REF
COMP
C10
0.1µF
MKS-2
R9
200k
C9
0.01µF, 100V
MKS-2
2
7
1
8
4
R13
12k
C11
220pF
R10
20k
LT1241
5
OUTPUT
I
SENSE
R12
1k
1/10W
6
3D4
BAT 85
R18
2Ω
1/4W
R16
2Ω
1/4W
R17
2Ω
1/4W
R11
12 Q1
MPT2N60
C12
22µF
25V
R14
39
D2
BAV21
LP = 100µH
12T
4
5
T2
D3
MUR420
C15
3.3µF
50V
R15
750Ω
1W
L1
5 1/2 TURN
AIRCORE
C16
3.3µF
50V
C13
4700pF
1kV
Y-CAP
20V
1.5A
RTN
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTANCES ARE IN OHMS, 1/4W, 5%.
2. ALL CAPACITANCES ARE IN MICROFARADS, 50V, 10%.
1212-R6103
COILTRONICS
CTX210433-1
FB
13
LT1241 Series
U
SA
O
PPLICATITYPICAL
+
–
+
–
–
+
LT1241 • TA04
R
T
C
T
FB
COMP
R
T
/C
T
V
REF
V
IN
R
S
I
SENSE
2
2.5V
2R
R
1V
1.5V
BLANKING
1mA
5.6V
OSCILLATOR
R
S
18V
7
V
CC
UV
LOCKOUT
5
GND
6
OUTPUT
5V REF
MAIN BIAS REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
T
1
8
3
4
Slope Compensation at ISENSE Pin
U
PACKAGE DESCRIPTIO
J8 0694
0.014 – 0.026
(0.360 – 0.660)
0.200
(5.080)
MAX
0.015 – 0.060
(0.381 – 1.524)
0.125
3.175
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.300 BSC
(0.762 BSC)
0.008 – 0.018
(0.203 – 0.457) 0° – 15°
0.385 ± 0.025
(9.779 ± 0.635)
0.005
(0.127)
MIN
0.405
(10.287)
MAX
0.220 – 0.310
(5.588 – 7.874)
1234
8765
0.025
(0.635)
RAD TYP
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION 
(4 PLCS)
0.045 – 0.068
(1.143 – 1.727)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.
J8 Package
8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
Dimensions in inches (millimeters) unless otherwise noted.
LT1241 Series
14
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N8 0695
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.380)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
12 34
8765
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.025
–0.015
+0.635
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
15
LT1241 Series
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 0695
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH 
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD 
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1241 Series
16 LINEAR TECHNOLOGY CORPORATION 1992
1241fa LT/TP 0297 5K REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
(408) 432-1900
FAX: (408) 434-0507
●
TELEX: 499-3977
●
www.linear-tech.com
LT1241 • TA05
FB
COMP
R
T
/
C
T
V
REF
I
SENSE
+
–
+
–
2.5V
2R
R
1V
1.5V
–
+
BLANKING
1mA
5.6V
4OSCILLATOR
R
S
18V
7
V
CC
UV
LOCKOUT
5
GND
6
OUTPUT
5V REF
MAIN BIAS REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
T
8
3
R
SLOPE
TO
V
OUT
2
R
f
R
T
C
T
1
Slope Compensation at Error Amp
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1246 1MHz Current Mode PWM 16V Start-Up Threshold, 10V Minimum Operating Voltage
LT1248/LT1249 Power Factor Controllers Minimal Parts Count
LT1372 High Efficiency Switching Regulator 500kHz 1.5A Boost Regulator
LT1376 1.5A 500kHz Step-Down Switching Regulator Steps Down from Up to 25V Using 4.7µH Inductors
LT1509 Power Factor and PWM Controller Complete Solution for Universal Off-Line Switching Power Supplies
TYPICAL APPLICATION
U