LTC4418
1
Rev A
For more information www.analog.com
TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual Channel Prioritized
PowerPath Controller
The LT C
®
4418 connects one of two valid power supplies
to a common output based on priority and validity. Priority
is defined by pin assignment, with V1 assigned the higher
priority and V2 the lower priority. A power supply is defined
as valid when its voltage has been within its overvoltage
(OV) and undervoltage (UV) window continuously for at
least the configured validation time. If the highest priority
valid input falls out of the OV/UV window, the channel is
immediately disconnected and the other valid input is con-
nected to the common output. Multiple LTC4418s, as well
as triple channel LTC4417s, can be cascaded to provide
switchover between more than two inputs.
The LTC4418 incorporates fast non-overlap switching
circuitry to prevent both reverse and cross conduction
while minimizing output droop. The gate driver includes
a 6V clamp to protect external MOSFETs. A controlled
soft-start feature minimizes start-up inrush current. Open
drain VALID outputs indicate the input supplies have been
within their OV/UV window for the duration of the valida-
tion time. The validation time can be disabled or adjusted
using an external capacitor.
APPLICATIONS
n Selects Highest Priority Supply from Two Inputs
n Blocks Reverse and Cross Conduction Currents
n Wide Operating Voltage Range: 2.5V to 40V
n –42V Protection Against Reverse Connection
n 60V Tolerant V1, V2 Inputs
n Adjustable Input Validation Time
n Fast Switchover Minimizes Output Voltage Droop
n Low 26µA Operating Current
n ±1.5% Input Overvoltage/Undervoltage Protection
n Adjustable Overvoltage/Undervoltage Hysteresis
n Cascadable for Additional Input Supplies
n 20-Lead 4mm × 4mm QFN Package
n Industrial Handheld Instruments
n High Availability Systems
n Battery Backup Systems
n Servers and Computer Peripherals
All registered trademarks and trademarks are the property of their respective owners.
V2
UV2
OV2
LTC4418
4418 TA01a
VS1 G1 VS2 G2
1M
100nF
60.4k
226k
1M
33.2k
78.7k
470nF BAT46WJ
M3 M4
47nF
698Ω
100k
82µF
1.25A MAX OUTPUT
V1
UV1
OV1
CAS
INTVCC
EN
SHDN
+
FDS4465
M1 M2
FDS4465
5V SYS
12V WALL
ADAPTER
GND HYS
255k
TMR
1nF 100nF
100k
VALID1
VALID2
VOUT
Priority Switching from V1 to V2
V
OUT
5V
13.8V
2ms/DIV
ILOAD = 1.25A
COUT = 82µF
V1
2V/DIV
V2
2V/DIV
Document Feedback
LTC4418
2
Rev A
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltages
V1, V2 ..................................................... –42V to 60V
VOUT....................................................... –0.3V to 42V
VS1, VS2 ................................................ –0.3V to 60V
Voltage from V1, V2 to VOUT ....................... –84V to 60V
Voltage from VS1, VS2 to G1, G2 ...............–0.3V to 7.5V
Input Voltages
EN, SHDN .............................................. –0.3V to 60V
OV1, OV2, UV1, UV2, TMR....................... –0.3V to 6V
HYS ......................................................... –0.3V to 1V
INTVCC .................................................. –0.3V to 6.2V
Output Voltages
VALID1, VALID2 ...................................... –0.3V to 60V
CAS .......................................................... –0.3V to 6V
Input Currents
OV1, OV2, UV1, UV2, HYS, TMR,
INTVCC, EN, SHDN ............................................ –3mA
Output Currents
VALID1, VALID2, CAS .............................. –2mA/+5mA
Operating Ambient Temperature Range
LTC4418C ................................................ 0°C to 70°C
LTC4418I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
20 19 18 17 16
6 7 8
TOP VIEW
GND
21
UF PACKAGE
20-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 47°C/W, θJC = 4.5°C/W
EXPOSED PAD (PIN 21), PCB GND CONNECTION OPTIONAL
9 10
5
4
3
2
1
11
12
13
14
15TMR
UV1
OV1
UV2
OV2
VOUT
VS1
G1
VS2
G2
HYS
SHDN
EN
V1
V2
VALID1
VALID2
GND
CAS
INTVCC
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4418CUF#PBF LTC4418CUF#TRPBF 4418 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C
LTC4418IUF#PBF LTC4418IUF#TRPBF 4418 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC4418#orderinfo
LTC4418
3
Rev A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V1 = VS1 = 12V and/or V2 = VS2 = 12V,
VOUT = 12V, HYS = GND, CAS = Open, G1 = G2 = Open. (Notes 1, 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Start-Up
V1, V2, VOUT V1, V2, VOUT Operating Supply Range l2.5 40 V
VINTVCC INTVCC Voltage l2.5 3.3 4 V
ITOT Total Supply Current
(Sum of IVOUT, IV1, IV2, IVS1, IVS2)
SHDN = 0V
l
l
26
22
52
44
µA
µA
IVOUT VOUT Supply Current l17 34 µA
IV1, IV2 V1, V2 Supply Current (Note 3)
VOUT = 0V, EN = 0V
VOUT = 0V, SHDN = 0V
l
l
l
1.4
21
13
2.8
42
26
µA
µA
µA
IVS1, IVS2 VS Supply Current Channel ON
Channel OFF
l
l
5.7
1.8
11.4
3.6
µA
µA
Gate Control
∆VGOpen Clamp Voltage (VS – VG) VOUT = 11V, G1 = G2 = Open l5.4 6.2 6.7 V
∆VG(SOURCE) Sourcing Clamp Voltage (VS – VG) VOUT = 11V, I = –10µA l5.8 6.6 7 V
∆VG(SINK) Sinking Clamp Voltage (VS – VG) VOUT = 11V, I = 10µA l4.5 5.2 6 V
IG(DN) Gate Pull-Down Current VG = 3V, VS Floating l28 60 120 mA
∆VG(OFF) Gate Off Threshold (VS – VG) VS1 = VS2 = 2.8V, VOUT = 11V, Gate Rising l0.2 0.3 0.4 V
RG(OFF) Gate Off Resistance V1 or V2 = 12V, IG = –10mA l8 16 28 Ω
VREV Reverse Voltage Threshold Measure (V1 or V2) – VOUT Falling l75 125 185 mV
tG(SWITCHOVER) Break-Before-Make Time VOUT = 11V, CGATE = 10nF (Note 4) l1 2.7 4 µs
tP(SHDN)Gate Turn-Off Delay from SHDN VOUT = 11V, Falling Edge SHDN to
G1 = VS1–3V or G2 = VS2 – 3V, CGATE = 10nF
l 0.3 0.7 1.4 µs
tP(EN) Gate Turn-On/Off Delay from EN VOUT = 11V, Rising/Falling EN Edge to
G1 = VS1–3V or G2 = VS2 – 3V, CGATE = 10nF
l0.3 0.7 1.4 µs
tSS Soft-Start Timeout VOUT = 2V l20 35 70 ms
Input/Output Pins
VVALID(OL) VALID Output Low Voltage I = 1mA, V1 or V2 = 2.5V, VOUT = 0V l0.23 0.5 V
VCAS(OH) CAS Output High Voltage I = –1µA, V1, V2, VOUT > 2.5V,
UV = OV = EN = 0V
l1.6 2.7 3.5 V
VCAS(OL) CAS Output Low Voltage I = 1mA, V1 or V2 = 2.5V, VOUT = 0V l60 150 mV
ICAS CAS Pull-Up Current SHDN = 0V, CAS = 1V l–10 –20 –40 µA
tCAS(EN) CAS Delay from VG(OFF) VOUT = 11V l0.3 0.7 1.4 µs
VEN(TH) EN Threshold Voltage EN Rising, VOUT = 11V l0.6 1 1.4 V
VSHDN(TH) SHDN Threshold Voltage SHDN Rising l0.6 1 1.4 V
VSHDN_EN(HYS) SHDN, EN Threshold Hysteresis 130 mV
ICTRL SHDN, EN Pull-Up Current SHDN = EN = 0V l–1.5 –3.2 –5.5 µA
ILEAK SHDN, EN, VALID1, VALID2, CAS
Leakage Current
SHDN = EN = VALID1 = VALID2 = 40V,
CAS = 5.5V
l±1 µA
LTC4418
4
Rev A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V1 = VS1 = 12V and/or V2 = VS2 = 12V,
VOUT = 12V, HYS = GND, CAS = Open, G1 = G2 = Open. (Notes 1, 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
OV, UV Protection Circuitry
VTH OV/UV Comparator Threshold VOUT = 11V, OV Rising, UV Falling l0.985 1 1.015 V
VHYS(INT) OV/UV Comparator Hysteresis VOUT = 11V l15 30 45 mV
ILEAK OV/UV Leakage Current OV = 1.015V, UV = 0.985V l±10 nA
IEXT External Hysteresis Current
Into/Out of UV/OV Pins
IHYS = –400nA
IHYS = –4µA
l
l
40
470
50
500
60
530
nA
nA
VHYS HYS Voltage IHYS = –4µA l480 500 520 mV
Validation Timer
ITMR TMR Pull-Up Current
TMR Pull-Down Current
Timer On, VTMR ≤600mV
Timer On, VTMR ≥1.6V
l
l
–1
1
–2
2
–3.5
3.5
µA
µA
tVALID OV, UV Validation Time TMR = VINTVCC
CTMR = 1nF
l
l
2
9
3.5
16
7
32
µs
ms
tVALID(OFF) VALID Off Delay from OV/UV Fault UV or OV 10% Overdrive,
Measure VALID1 or VALID2 Rising Edge
l2 3.5 7 µs
VTH(TMROFF) TMR Disable Voltage Threshold Measure VINTVCC-VTMR, Rising Edge l50 100 180 mV
VTH(TMRHYS) TMR Disable Voltage Hysteresis 120 mV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 3: Specification represents the diode-OR’d current of V1 or V2 input
supplies. Current is split evenly if both supplies are equal.
Note 4: UV1 or UV2 driven below VTH. Time is measured from respective
rising edge G1 crossing VS1 – 3V or G2 crossing VS2 – 3V to next valid
priority falling edge G1 crossing VS1 – 3V or G2 crossing VS2 – 3V.
LTC4418
5
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Total Enabled Supply Current
vs Supply Voltage
Total Shutdown Supply Current
vs Supply Voltage
IV1, IV2, IVOUT
vs V2 Supply Voltage
Gate Drive Voltage
vs Temperature
Gate Falling Slew Rate
vs Temperature
Gate Rising Slew Rate
vs Temperature
Gate Pull-Down Current
vs Gate Voltage
Break Before Make Time
vs Temperature
Valid Delay Off Time
vs Temperature
ALL SUPPLY VS AND VOUT
PINS CONNECTED TOGETHER
–45°C
90°C
25°C
SUPPLY VOLTAGE (V)
0
10
20
30
40
0
5
10
15
20
25
30
35
40
TOTAL ENABLE SUPPLY CURRENT (µA)
4418 G01
–45°C
90°C
25°C
SUPPLY VOLTAGE (V)
0
10
20
30
40
0
5
10
15
20
25
30
TOTAL SUPPLY CURRENT (µA)
4418 G02
ALL SUPPLY VS AND VOUT
PINS CONNECTED TOGETHER
V2 VOLTAGE (V)
–40
–30
–20
–10
0
10
20
30
40
0
5
10
15
20
I
V1-V2-VOUT(EN)
(µA)
4418 G03
I
VOUT
I
VS1
+I
VS2
I
V2
I
V1
V1 = VS1 = VS2 = VOUT = 12V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
4.5
5.0
5.5
6.0
6.5
7.0
∆VG (V)
4418 G04
OPEN
IG = –10µA
IG = 10µA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
0
2
4
6
8
10
12
14
16
18
GATE FALLING SLEW RATE (V/µs)
4418 G05
V1 = 2.7V
V1 = 5V
V1 = 12V
V1 = 40V
V1 = 24V
V1 = V2
CGATE = 10nF
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
0
4
8
12
16
GATE RISING SLEW RATE (V/µs)
4418 G06
V1 = 2.7V
V1 = 5V
V1 = 12V, 24V, 40V
V1 = V2
CGATE = 10nF
GATE VOLTAGE (V)
0
0.5
1
1.5
2
2.5
3
3.5
0.01
0.1
1
10
100
GATE PULL–DOWN CURRENT (mA)
4418 G07
90°C
25°C
–45°C
V1/V2 = 12V
VS1/VS2 = FLOATING
VOUT = 11.7V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
1.5
2.0
2.5
3.0
3.5
t
G(SWITCHOVER)
(µs)
4418 G08
V1 = 40V
V1 = 12V
V1 = 3V
V1 = V2
CGATE = 10nF
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
2
3
4
5
6
7
VALID DELAY TIME (µs)
4418 G09
TA = 25°C, unless otherwise noted.
LTC4418
6
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
OV, UV Threshold vs Temperature
Validation Time
vs TMR Capacitance
OV, UV Hysteresis Current
Configuration
INTVCC
vs Input Voltage (V1, V2, VOUT)
VTH
UV RISING THRESHOLD
OV FALLING THRESHOLD
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
VTH (V)
4418 G10
V1/2 = 12V
C
TMR
(nF)
0.1
1
10
100
1k
1
10
100
1k
10k
VALIDATION DELAY (ms)
4418 G11
I
HYS
(nA)
0
1000
2000
3000
4000
0
100
200
300
400
500
IEXT (nA)
4418 G12
INPUT VOLTAGE (V)
0
8
16
24
32
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INTVCC (V)
4418 G13
VALID1, VALID2
Pull-Down Strength
90°C
25°C
–45°C
V1/V2 = 12V
VOUT = 12V
PULL-UP CURRENT (mA)
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1.0
VVALID(OL) (V)
4418 G14
Deglitched Connection
V
OUT
5ms/DIV
CTMR = 1nF
COUT = 120µF
ILOAD = 1A
–40A PCH FDS4685
V1
2V/DIV
V2
2V/DIV
4418 G15
VOUT Switching from Higher to
Lower Voltage
VOUT Switching from Lower
to Higher Voltage with Inrush
Current Limiting Circuitry Reverse Voltage Blocking
500µs/DIV
VOUT
2V/DIV
V1
2V/DIV
V2
2V/DIV
4418 G16
COUT = 120µF
ILOAD = 2A
–20V PCH FDS4465
V
OUT
50µs/DIV
RS = 475Ω
CS = 47nF
COUT = 120µF
ILOAD = 2A
–20V PCH FDS4465
V1
4V/DIV
V2
4V/DIV
IV2
10A/DIV
4418 G17
V1 = +15V
V1 = –15V
–40V PCH FDD4685
COUT = 10µF
ILOAD = 1A
2ms/DIV
V1
5V/DIV
V2, VOUT
5V/DIV
4418 G18
LTC4418
7
Rev A
For more information www.analog.com
PIN FUNCTIONS
TMR (Pin 1): Validation Timer. Attach an external capacitor
between TMR and GND of at least 100pF to set a Valida-
tion Time of 16ms/nF for both channels. Connect TMR to
INTVCC to set a minimum validation time of 3.5µs (Fast
Mode). Do not leave open.
UV1, UV2 (Pins 2, 4): Undervoltage Comparator Inputs.
Falling voltages below 1V (VTH) trigger an undervoltage
event, invalidating the respective input supply channel.
Connect UV1 and UV2 to a resistive divider between the
respective V1 and V2 and ground to achieve the desired
undervoltage threshold. The comparator hysteresis can
be set internally to VHYS(INT) or set externally via the HYS
pin. Connect unused pins to ground.
OV1, OV2 (Pins 3, 5): Overvoltage Comparator Inputs.
Rising voltages above 1V (VTH) signal an overvoltage
event, invalidating the respective input supply channel.
Connect OV1 and OV2 to an external resistive divider from
its respective V1 and V2 to achieve the desired overvoltage
threshold. The comparator hysteresis can be set internally
to VHYS(INT) or set externally via the HYS pin. Connect
unused pins to ground.
VALID1, VALID2 (Pins 6, 7): Valid Channel Indicator Out-
puts. VALID1 and VALID2 are 40V rated, open drain outputs
that pull low when the respective V1 and V2 are within the
OV/UV window for at least the configured validation time
and release when the respective V1 and V2 are outside
the OV/UV window. Connect a resistor between VALID1
and VALID2 and a desired supply, which may be V1, V2 or
VOUT, to provide the pull-up. Leave open when not used.
GND (Pin 8, Exposed Pad Pin 21): Device Ground. Exposed
pad may be left open or connected to device ground.
CAS (Pin 9): Cascade Output. Digital output used for cas-
cading multiple LTC4418s and/or LTC4417s. Connect CAS
to EN of another LTC4417/LTC4418 to increase the number
of multiplexed input supplies. CAS is pulled up to INTVCC
by an internal 20µA current source (ICAS) to indicate when
all inputs are invalid, the external P-channel MOSFETs are
determined to be off, and EN is above VEN(TH). CAS also
pulls high when SHDN is driven below VSHDN(TH). CAS
is pulled low when any input supply is within the OV/UV
window for at least the configured validation time and
SHDN is above its threshold. CAS also pulls low when EN
is driven below VEN(TH). CAS can be pulled up to voltages
as high as 5.5V, independent of the input supply voltages.
Leave open if not used.
INTVCC (Pin 10): Internal Low Voltage Supply Decoupling
Output. Do not connect an external load current to INTVCC.
Connect a 0.1µF capacitor from this pin to GND.
G1, G2 (Pins 13, 11): P-Channel MOSFET Gate Drive
Outputs. G1 and G2 are used to control external P-channel
MOSFETs. When driven low, G1 and G2 are clamped 6.2V
(∆VG) below their corresponding VS1 and VS2. Connect
G1 and G2 to external P-channel MOSFET gate pins.
VS1, VS2 (Pins 14, 12): External P-Channel MOSFET
Common Source Connection. The gate drivers use VS1
and VS2 to monitor the common source connection of the
external P-channel MOSFETs. Connect VS1 and VS2 to the
respective common source connection of the P-channel
MOSFETs. Connect to ground when channel is not used.
See Applications Information section for bypass capacitor
recommendations.
VOUT (Pin 15): Output Voltage Supply and Sense. VOUT
is an output voltage sense pin used to prevent any input
supply from connecting to the output if the output voltage
is not below the input supply voltage by at least 125mV
(VREV). During normal operation, VOUT powers most of
the internal circuitry when its voltage exceeds 2.475V.
See Applications Information section for bypass capacitor
recommendations.
V2 (Pin 16): Lower Priority Input Supply. When V2 is
within its user defined OV/UV window for the configured
validation time, it is connected to VOUT via its external
P-channel MOSFETs only if V1 does not meet its OV/UV
requirements. Connect V2 to ground when channel is not
used. See Applications Information for bypass capacitor
recommendations.
V1 (Pin 17): Higher Priority Input Supply. When V1 is
within its user defined OV/UV window for the configured
validation time, it is connected to VOUT via its external
P-channel MOSFETs. See Applications Information for
bypass capacitor recommendations.
LTC4418
8
Rev A
For more information www.analog.com
PIN FUNCTIONS
EN (Pin 18): Channel Enable Input. EN is a 40V input
that allows the user to quickly connect and disconnect
channels without resetting the OV/UV Validation timer.
This feature is essential in cascading applications. When
below 1V (VEN(TH)), both external P-channel MOSFETs are
driven off by pulling G1 and G2 to their respective VS1
and VS2. When above VEN(TH), the highest valid priority
channel is connected to the output. EN is pulled to INTVCC
with a 3.2µA current source (ICTRL) and can be pulled
up externally to a maximum voltage of 40V. Connect to
INTVCC when not used.
SHDN (Pin 19): Shutdown Input. Driving SHDN below
VSHDN(TH) turns off all external P-channel MOSFETs, dis-
ables the OV/UV comparators and resets the validation
timers used to validate V1 and V2. CAS is pulled high to
allow lower priority LTC4417/LTC4418s in a cascaded
system to provide power to VOUT. Driving SHDN above
1V (VSHDN(TH)) allows channels to validate and connect.
SHDN is pulled high to INTVCC with a 3.2µA current source
(ICTRL) and can be pulled up externally to a maximum
voltage of 40V. Connect to INTVCC when not used.
HYS (Pin 20): OV/UV Comparator Hysteresis Input. Con-
necting HYS to ground sets a fixed hysteresis (VHYS(INT)) for
the OV and UV comparators. Connecting a resistor, RHYS,
between HYS and ground disables the internal hysteresis
and sets a 63mV/RHYS hysteresis current which is sourced
from each OV1 and OV2 and sunk into each UV1 and UV2
pin. Connect to GND if not used.
LTC4418
9
Rev A
For more information www.analog.com
BLOCK DIAGRAM
3.2µA
INTVCC
1V
INTVCC
SHDN
EN
20µA
INTVCC
INTVCC
VOUT
CAS
GND
VALIDATION
TIMER
CH1
VALID
HOLD
CH OFF
EXTERNAL
SWITCH ON
REV
VGS
GATE
DRIVER
UV2
UV1
OV2
OV1
VALID2
VALID1
CHANNEL 1
CHANNEL 2
V2
V1
VS2
VS1
G2
4418 BD
G1
PRIORITIZED
NONOVERLAP
CONTROL
LOGIC
TMR
UV
OV
INTVCC
IEXT
VOUT
INT HYS
EXT HYS
UV
OV
IEXT
125mV
300mV
IEXT
1V
1.03V
6.2V
970mV
3.2µA
INTVCC
+
–
1V
INTVCC
+
–
OSCILLATOR
DISABLE GATEDRIVERS AND
RESET VALIDATION TIMER
DISABLE GATEDRIVERS
HYS
+
–
+
–
HYSTERESIS
+
–
+
–
+–
+–
REGULATOR
V1
V2
LTC4418
10
Rev A
For more information www.analog.com
TIMING DIAGRAM
G1
G2
VALID2
VALID1
UV2
UV1
EN
tVALID
tVALID(OFF)
tG(SWITCHOVER)
tP(EN)
tP(EN)
tP(SHDN)
SHDN
4418 TD
LTC4418
11
Rev A
For more information www.analog.com
OPERATION
The LTC4418 is an intelligent 40V dual channel PowerPath™
switch that automatically connects one of two input sup-
plies to a common output based on a channel’s priority
and validity. Channel 1 is defined to be higher priority
than Channel 2 regardless of voltage levels. A channel’s
validity is user defined by a set of undervoltage (UV) and
overvoltage (OV) comparators biased with a resistive
divider off of the channel’s input. Connection is made by
enhancing external back-to-back P-channel MOSFETs. Un-
like a diode-OR, which always passes the highest supply
voltage to the output, the LTC4418 lets one use a higher
supply as a secondary for backup power.
During normal operation the LTC4418 continuously moni-
tors V1 and V2 through its respective UV and OV pins
using precision overvoltage and undervoltage compara-
tors. An input supply is defined valid when the voltage
remains in the OV/UV window for at least the validation
time, (tVALID). If the input supply connected to V1 falls
out of the OV/UV window and remains outside for at least
3.5µs (tVALID(OFF)) the channel is disconnected. V2 is then
connected to the common output if it is within its OV/UV
window. The LTC4418 always connects the higher priority
V1 supply if it becomes valid regardless of the status of
V2. VALID1 and VALID2 pull low to indicate when the V1
and V2 input supplies are valid.
Hysteresis on the UV and OV inputs can be configured to
be a fixed 3% or made adjustable. Connecting the HYS
pin to ground sets the hysteresis on both channels to be
3% of the monitored voltage. Connecting a resistor, RHYS,
between HYS and ground forces 63mV/RHYS current out
of OV1 and OV2 and into UV1 and UV2 in order to create
hysteresis when outside their respective OV/UV windows.
The configuration of HYS affects both channels.
During channel transitions, monitoring circuitry prevents
cross conduction between input supplies and reverse
conduction from VOUT using a break-before-make archi-
tecture. The VGS comparator monitors the disconnecting
channel’s gate pin voltage (G1 or G2). When the gate
voltage is 300mV (∆VG(OFF)) from its common source
connection (VS1 or VS2), the VGS comparator latches the
output to indicate the channel is off and allows the other
valid priority input supply to connect to VOUT, preventing
cross conduction between channels.
To prevent reverse conduction from VOUT to V1 and V2
during channel switchover, the REV comparator monitors
the connecting input supply (V1 or V2) and VOUT. The REV
comparator delays the connection until the output voltage
droops lower than the input voltage by 120mV (VREV).
Once activated, the LTC4418 gate driver pulls G1 or G2
down to 6.2V (∆VG) below its respective VS1 or VS2 with
a strong pull-down current. After turning on, the gate
driver holds the gates of the external P-channel MOSFETs
at ∆VG with a small pull-down current. To minimize inrush
current at start-up, the gate driver soft-starts the first input
supply to connect to VOUT at a rate of approximately 4V/
ms terminating when any channel disconnects or 35ms
elapses. Once slew rate control has terminated, the gate
driver returns to normal gate driving operation.
When EN is driven above 1V (VEN(TH)) the highest valid
priority input supply is connected to VOUT. When EN is
driven below VEN(TH) all channels are disconnected from
VOUT and the LTC4418 continues to monitor the OV and
UV pins indicating status with VALID1 and VALID2. When
SHDN is pulled below 1V (VSHDN(TH)) all channels are
disconnected, OV and UV comparators are disabled and
both channel validation timers are reset. A SHDN low to
high transition reactivates soft-start, provided VOUT drops
below 2.3V before SHDN is high. VOUT dropping below
1.7V also reactivates soft-start.
When additional supplies need to be prioritized the part can
work in conjunction with other LTC4417s and/or LTC4418s
where the CAS pin of the highest priority controller is con-
nected to the EN of the lower priority controller. If VOUT
is allowed to fall below 1.7V, the next connecting input
supply is soft-started.
The LTC4418 has its own internally generated 3.3V rail
(INTVCC) that provides power to internal circuits of the
part. The INTVCC rail is prioritized such that supply cur-
rent comes from one of three prioritized sources (V1, V2
or VOUT).
An external capacitor must be connected between the
INTVCC pin and GND to hold up the internal rail in the event
of transients such as input supply shorts.
LTC4418
12
Rev A
For more information www.analog.com
PowerPath controllers are designed to connect one of
several input supplies to a common output based on their
priority and validity. The highest priority supply may not
necessarily be the highest in voltage. While the applica-
tion appears simple at first glance there are a few issues
that must be accounted for when building an application.
One issue is input supply inrush current during a channel
switchover that occurs when charging a low ESR output
capacitor. Inrush current dissipates significant power in the
external P-channel MOSFETs. It also causes input voltage
droop due to the input power supply’s source impedance
and the parasitic impedance of connectors, cables and PCB
traces. Input supply voltage droop can cause UV faults
that trigger a phenomenon called motor-boating, where
the input supply repeatedly connects and disconnects
from the output. Motor-boating can lead to component
damage or undesirable/erratic circuit behavior.
Another issue is output voltage droop which occurs dur-
ing the break-before-make time of a switchover between
channels. Ideally, there would be no disruption of the
output voltage during a switchover. However, load current
discharges the output capacitor during the break-before-
make time resulting in output voltage droop. To ensure
minimum output voltage droop, a large value, low ESR
capacitor is used to ride through this dead time. There
is a trade-off between inrush current and output voltage
droop. The following sections describe these challenges in
more detail and explain component selection to properly
manage them. Note that input supply voltages denoted
by “SYS” are not hot-swappable, all other input supplies
are hot-swappable.
DEFINING OPERATION RANGE
The operation range for each LTC4418 channel is defined
by an OV/UV window. An input supply must remain inside
the OV/UV window for the OV/UV validation time, tVALID, to
become valid and connect to the output. Both OV and UV
thresholds include hysteresis which reduces the operat-
ing window as shown in Figure1. For example, V1 supply
voltage must be greater than UVHYS to exit the UV fault. If
an OV fault occurs, the V1 supply voltage must return to a
voltage lower than the OVHYS voltage to exit the OV fault.
REDUCED
OPERATING
WINDOW
OV/UV
WINDOW
OV
UV
V1
4418 F01
UV1 FAULT
OV1 FAULT
V1 VALID1
OVHYS
UVHYS
Figure1. OV and UV Thresholds and Hysteresis Voltage
APPLICATIONS INFORMATION
The OV/UV window for each input supply is set by a resis-
tive divider connected from the input supply to GND. The
most important consideration when setting the resistive
divider values for the OV/UV window is to provide enough
hysteresis to allow for input supply voltage droop due to
inrush and load current during switchover.
In addition to input supply droop take into consideration:
1. Tolerance of the Input Supply
2. 1.5% OV/UV Comparator Threshold Error
3. Tolerance of External Resistive Divider
4. Max ILEAK OV/UV Pin Leakage Currents
Hysteresis for the OV and UV comparators is set via the
HYS pin. Two options are available. Connecting a resistor,
RHYS, between HYS and GND, as shown in Figure2, sets
the hysteresis current IHYS that is sunk into UV1 and UV2
and sourced out of OV1 and OV2. The value of RHYS is
calculated with:
RHYS =
63mV
IEXT
Choose RHYS to limit the hysteresis current in the range
50nA to 500nA. Connecting HYS to GND, as shown in
Figure3, selects an internal 30mV fixed hysteresis, result-
ing in 3% of the input supply range.
LTC4418
13
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
R3
R2
R1
R7
R6
R5
R4
R10
R9
R8
R12
R11
IHYS/8
IHYS/8
M1
RP
RHYS
T-RESISTIVE
CONNECTION
DUAL-
RESISTIVE
CONNECTION
ALTERNATE INDEPENDENT
HYSTERESIS
UV1
OV1
OV1
UV1
V1
UV1
GND
1V
1V
INTVCC
UV
OV
VALIDATION
TIMER
LTC4418
VOUT
VALID1
HYS
124k
TO
1.24M
IHYS
V1 INPUT
SUPPLY
OV1
4418 F02
Figure2. Adjustable External OV/UV Hysteresis
R3
R2
R1
M1
RP
CUVF
M2
V1
UV1
GND
1V
1V
UV
OV
LTC4418
VOUT
VALID1
HYS
V1 INPUT
SUPPLY
OPTIONAL
FILTER
CAPACITOR
OPTIONAL
DISCONNECT
OV1
1.03V
0.97V
VALIDATION
TIMER
4418 F03
Figure3. 3% Internal Hysteresis with Optional Filter Capacitor
and Manual Disconnect MOSFET
LTC4418
14
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
Refer to the Design Example for an explanation of the
Three-Resistor configuration for setting OV/UV thresholds
and hysteresis. Independent OV and UV hysteresis values
are available by separating the single string resistive divid-
ers R1, R2 and R3, shown in Figure2, into two resistive
strings, R4-R5 and R6-R7. In such a configuration, the top
resistor defines the amount of hysteresis and the bottom
resistor defines the threshold.
RTOP and RBOT are calculated using:
RTOP =Desired Hysteresis
IEXT
RBOT =RTOP
(OV/UV Threshold)−1
When large independent hysteresis voltages are required,
a resistive T structure can be used to define hysteresis
values, also shown in Figure2. After the desired OV and
UV thresholds are set with resistors R8 through R10, R11
and R12 are calculated using:
R11=R8 • [OVHYS −IEXT • (R9 +R10)]
IEXT • (R8 +R9 +R10)
R12 =(R8 +R9) • [UVHYS −IEXT • R10]
I
EXT
• (R8 +R9 +R10)
where OVHYS, UVHYS are the desired OV and UV hyster-
esis voltage magnitudes at V1 through V2, and IEXT is the
programmed hysteresis current.
The LTC4418 has an OV/UV fault filter time of tVALID(OFF).
Add a filter capacitor, CUVF, between the OV or UV pin and
GND to extend the fault filter time and ride through tran-
sients as shown in Figure3. By extending the filter time,
the detection of a valid UV condition will also be delayed. To
tailor the filter time delays individually, separate the single
resistive divider into two resistive dividers. When selecting
resistor values, take into consideration board leakage and
OV/UV pin leakage and their affect on threshold accuracy.
PRIORITY REASSIGNMENT
A connected input supply can be manually disconnected
by artificially creating a UV fault. An example is shown in
Figure3. When N-channel MOSFET, M2, is turned on, the
UV1 pin is pulled below 1V. The LTC4418 then disconnects
V1 and connects the next highest valid priority to VOUT.
Alternatively, the VALID2 can be connected directly to
UV1 to swap priority to Channel 2, as shown in Figure12.
Connect TMR to INTVCC to ensure quick switchover to
channel 1 when channel 2 becomes invalid.
SELECTING EXTERNAL P-CHANNEL MOSFETS
The LTC4418 drives external P-channel MOSFETs to
conduct or block load current between an input supply
and load. When selecting external P-channel MOSFETs,
the key parameters to consider are:
1. On-Resistance (RDS(ON))
2. Absolute Max Drain-Source Breakdown Voltage
(BVDSS(MAX))
3. Threshold Voltage (VGS(TH))
4. SOA
The on-resistance of each P-channel MOSFET should
be sufficiently low when conducting the maximum load
current to minimize voltage drop and power dissipation.
External P-channel MOSFET devices may be paralleled to
decrease resistance and decrease power dissipation of
each paralleled MOSFET.
The clamped gate drive output is 4.5V (minimum) from
the common source connection. Select logic level or lower
threshold external MOSFETs to ensure adequate overdrive.
For applications with input supplies lower than the clamp
voltage, choose external MOSFETs with thresholds suf-
ficiently lower than the input supply voltage to guarantee
full enhancement.
LTC4418
15
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
It is imperative that external P-channel MOSFET devices
never exceed their BVDSS(MAX) rating in the application.
Switching inductive supply inputs with low value input
and/or output capacitances may require additional precau-
tions; see Transient Supply Protection section for more
information.
In normal operation, the external P-channel MOSFET de-
vices are either fully on, dissipating relatively low power,
or off, dissipating no power. However, during slew-rate
controlled startup or switchover from a lower to a higher
voltage with inrush current, significant power may be dis-
sipated in the external P-channel MOSFETs. The external
MOSFETs must satisfy the Safe Operating Area (SOA)
curve for these conditions.
A list of suggested P-channel MOSFETs is shown in
Table1. Use procedures outlined in this section and the
SOA curves in the chosen MOSFET manufacturer’s data
sheet to verify suitability for the application.
Table1. Listed of Suggested P-Channel MOSFETs
MOSFET APP MAX OP VOLTAGE VTH(MAX) VGS(MAX) VDS(MAX) RDS(ON) (Ω)
Si4465ADY 5V –1V ±8V –8V 0.009 at –4.5V
0.011 at –2.5V
Si4931DY 10V –1V ±8V –12V 0.018 at –4.5V
0.022 at –2.5V
IRF7220 10V –0.6V ±12V –12V 0.012 at –4.5V
0.02 at –2.5V
IRF7325* 10V –0.9V ±8V –12V 0.024 at –4.5V
0.033 at –2.5V
FDS4465 18V –1.5V ±8V –20V 0.0085 at –4.5V
0.010 at –2.5V
FDMS6673BZ 28V –3V ±25V –30V 0.0125
FDS6675 28V –3V ±20V –30V 0.02
AO4803A* 28V –2.5V ±20V –30V 0.074
Si4909DY* 36V –2.5V ±20V –40V 0.034
SUD50P04-23 36V –3V ±20V –40V 0.0117
Si7463ADP 36V –3V ±20V –40V 0.0135
FDD4685/FDS4685 36V –3V ±20V –40V 0.035
Si7461DP 40V –3V ±20V –60V 0.019
FDMC5614P 40V –3V ±20V –60V 0.135
SUD50P06-15 40V –3V ±20V –60V 0.02
FDD5614P 40V –3V ±20V –60V 0.13
FDS9958 40V –3V ±20V –60V 0.135
SUD50P08-25L 40V –3V ±20V –80V 0.029
Si7469DP 40V –3V ±20V –80V 0.029
FDS8935 40V –3V ±20V –80V 0.247
Si7489DP 40V –3V ±20V –100V 0.047
*Dual P-channel MOSFETs in a single package.
LTC4418
16
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
SELECTING VOUT CAPACITANCE
To ensure there is minimal droop at the output, select a
low ESR capacitor large enough to ride through the dead
time between channel switchover. A low ESR bulk capacitor
will reduce IR drops to the output voltage while the load
current is sourced from the capacitor.
To calculate the value of the load capacitor that will ride
through the break-before-make time, tG(SWITCHOVER) during
a normal switchover use:
COUT ≥
I
LOAD(MAX)
• t
G(SWITCHOVER)
ΔVOUT(DROOP) −ESR • ILOAD(MAX)
where ILOAD(MAX) is the maximum load current drawn
and VOUT(DROOP) is the maximum acceptable amount of
voltage droop at the output. This equation assumes no
inrush current limiting circuitry is required. If inrush cur-
rent limiting is necessary then a modified equation for the
minimum COUT calculation is used:
COUT ≥ILOAD • tG(SWITCHOVER) +0.79 • RS• CS
( )
ΔVOUT(DROOP) −ESR • ILOAD
The selection of RS and COUT is iterative. Initially, the
minimum COUT is calculated by approximating:
0.79 • RS • CS = 15µs
Once RS is determined, the selection of COUT should be
checked by substituting the values of RS and CS into the
equation above to ensure the condition is satisfied. See
the Inrush Current and Input Voltage Droop section.
For conditions where V1/2 supplies are rapidly discon-
nected or may be shorted then it is appropriate to add
the VALID1/2 Off Delay from OV/UV Fault (tVALID(OFF)) to
tG(SWITCHOVER) in the previous equations. Note that there
is a trade-off between larger COUT and tolerating higher
inrush current.
COUT ≥
ILOAD • tG(SWITCHOVER) +tVALID(OFF) +0.79 • RS• CS
( )
ΔVOUT(DROOP) −ESR • ILOAD
INRUSH CURRENT AND INPUT VOLTAGE DROOP
When connecting a higher voltage supply to a lower voltage
output, significant inrush current can occur while charging
an output capacitor with low ESR. Inrush current during a
switchover can cause two issues, (1) P-channel MOSFETs
are subjected to damaging power dissipation and (2) an
undesirable UV fault from significant input voltage droop
also known as motor-boating. Motor-boating is specifi-
cally a concern when the UVHYS threshold for the input
supply connected to V1 is higher in voltage than the OV/
UV window of the input supply connected to V2. Motor-
boating is prevented through inrush current limiting and
ensuring that there is a proper amount of hysteresis to
accommodate the expected input supply voltage droop.
At a minimum hysteresis should provide enough margin
for the input supply voltage to droop due to inrush and
load current during switchover. Select the OV/UV operation
range appropriately.
Inrush current limiting is necessary in situations where
one or more of these conditions apply:
1. Max IINRUSH through the supply source resistance,
RSRC can cause a UV condition.
2. Peak inrush current violates the maximum pulsed drain
current (IDM) of the external P-channel MOSFETs.
3. Large voltage differential between input supplies or the
configured OV/UV thresholds between input supplies.
4. Small or unknown source impedance.
5. Large output capacitance.
In order to check maximum expected inrush current use:
Max IINRUSH =(Max V1 or V2) −VOUT(MIN)
RSRC +ESRCOUT +2 • RDS(ON)
Where ESRCOUT is the ESR of the output capacitor and
RDS(ON) is the channel resistance of the selected P-channel
MOSFETs. The maximum voltage differential is determined
from the higher supply’s OV threshold and the lower sup-
ply’s UV threshold minus VOUT droop.
LTC4418
17
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
With the LTC4418, inrush current can be reduced by
slew rate limiting the output voltage. The gate driver can
be configured to slew rate limit the output voltage with a
resistor, capacitor and Schottky diode, as shown in Figure4.
The series resistor, RS, and capacitor, CS, are inrush cur-
rent limiting components, while the Schottky diode, DS,
provides a fast turn off path when G1 is pulled to VS1.
Choose CS to be at least ten times the external P-channel
MOSFET’s reverse transfer capacitance, CRSS(MAX), and
CVS to be ten times CS. Alternatively, CRSS(MAX) itself can
be used in place of CS, where its value is taken at the
minimum VDS voltage.
GATE DRIVER
When turning a channel on, the LTC4418 pulls the com-
mon gate connection (G1 and G2) down with a strong
low impedance pull-down. See IG(DN) in the Electrical
Characteristics table. VS1 and VS2 voltages lower than
5V will result in lower gate slew rates, see the Typical
Performance Characteristics curves for more detail. After
turning a channel on the gate driver holds down G1 or
G2 with a small pull-down current sufficient to maintain
the ∆VG clamp voltage. Clamping the G1 and G2 voltage
prevents any overvoltage stress on the gate to source
oxide of the external P-channel MOSFETs. When turning
a channel off, the gate driver pulls the common gate to the
common source with a switch having an on-resistance of
RG(OFF), to facilitate a quick turn-off.
To minimize inrush current at start-up, the gate driver
soft-starts the gate drive of the first input to connect to
VOUT. The gate pin is regulated to create an approximately
4V/ms slew rate on VOUT. Logic level P-channel MOSFETs
with thresholds below 1V will result in faster soft-start slew
rates on VOUT. Slew rate control is terminated when any
channel disconnects or a time period 35ms has elapsed.
Once soft-start has terminated, the gate driver operates nor-
mally. A SHDN low to high transition reactivates soft-start,
provided VOUT drops below 2.3V before SHDN is high.
VOUT drooping below 1.7V also reactivates soft-start.
SELECTING VALIDATION TIME
The validation time is adjustable allowing greater flexibility
when validating input supplies over a variety of applica-
tions. The validation time, tVALID, is adjusted by connecting
a capacitor, CTMR, between the TMR pin and ground. The
value of this capacitor is determined by:
CTMR =
t
VALID
16ms/nF
It is not recommended to leave the TMR pin open, instead
connect the pin to INTVCC to engage “Fast Mode” operation
where tVALID is reduced to approximately 3.5µs typical.
The accuracy of the validation time is affected by capacitor
leakage (the nominal charging current is specified by ITMR)
and capacitor tolerance. A low leakage ceramic capacitor
is recommended.
Figure4. Inrush Current Limiting Components
M1
M2
DS
BAT54
RS
CS
CVS
CIN
COUT
LTC4418
VS1/2
G1/2
VOUT
V1/2
VOUT
4418 F04
With a desired COUT and inrush current target the value
of RS is:
RS≥ΔVG(SINK) −VGS
( )
• COUT
CS• IINRUSH
where ∆VG(SINK) is the LTC4418’s sink clamp voltage
and VGS is the external P-channel’s gate to source volt-
age when driving the load and inrush current. The output
load current ILOAD is neglected for simplicity. When in-
rush current limiting, ensure power dissipation does not
exceed the manufacturer’s SOA for the chosen external
P-channel MOSFET.
LTC4418
18
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
TRANSIENT SUPPLY PROTECTION
The LTC4418’s abrupt switching due to OV or UV faults
can create large transient overvoltage events with induc-
tive input supplies, such as supplies connected by a long
cable. At times the transient overvoltage condition can
exceed twice the nominal voltage resulting in damage to
the system. It is imperative that external P-channel MOSFET
devices do not exceed their single pulse avalanche energy
specification (EAS) in unclamped inductive applications and
input voltages to the LTC4418 never exceed the Absolute
Maximum Ratings.
To minimize inductive voltage spikes, use wider and/or
heavier trace plating. Transient voltage suppressors (TVS)
should be placed on supply pins, V1 and V2 where inductive
transients beyond the 60V absolute maximum rating are
expected. When selecting transient voltage suppressors,
ensure the reverse standoff voltage (VR) is equal to or
greater than the application operating voltage, the peak
pulse current (IPP) is higher than the peak transient voltage
divided by the source impedance, the maximum clamping
voltage (VCLAMP) at the rated IPP is less than the absolute
maximum ratings and BVDSS of all the external P-channel
MOSFETs. See Figure5. The LTC4418’s absolute maximum
voltage rating for V1 and V2 allow it to withstand supply-
side inductive voltage spikes up to 60V. A range of TVS
diode specifications can be used accommodating VRWM
ratings up to 36V and VCLAMP ratings up to 60V.
REVERSE VOLTAGE PROTECTION
The LTC4418 is designed to withstand reverse voltages
applied to V1 and V2 with respect to VOUT up to –84V. This
allows VOUT to operate at or near its maximum operating
voltage, 42V with V1/V2 at a –42V reverse voltage. The
large reverse voltage rating protects input supplies and
downstream devices connected to VOUT against high re-
verse voltage connections of –42V (absolute maximum)
with margin. Select P-channel MOSFETs with BVDSS(MAX)
ratings capable of handling any anticipated reverse volt-
ages between VOUT and V1 or V2. Ensure transient volt-
age suppressors (TVS) connected to reverse connection
protected inputs (V1 and V2) are bidirectional and input
capacitors are rated for the negative voltage. See Typical
Performance Characteristics for voltage waveforms il-
lustrating this feature.
REVERSE CURRENT BLOCKING
When switching channels from higher voltages to lower
voltages, the REV comparator verifies the VOUT voltage is
below the connecting channel’s voltage by 120mV before
the new channel is allowed to connect to VOUT. VOUT is
allowed to decay at a slew rate determined by the load
current divided by the load capacitance. This ensures
little to no reverse conduction occurs during switching.
Figure5. Transient Voltage Suppression
CLOAD
TVS
COUT
RSN
CSN
CVIN
V1/2
VOUT
OUTPUT
PARASITIC
INDUCTANCE
INPUT
PARASITIC
INDUCTANCE
SNUBBER
OR
OR
TVS
LTC4418
VS1/2
G1/2
VOUT
4418 F05
M1
M2
LTC4418
19
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
DISABLING ALL CHANNELS WITH EN AND SHDN
Driving EN below 1V turns off all external P-channel
MOSFETs but does not interrupt input supply monitoring
or reset the validation timers. Driving EN above 1V enables
the highest valid priority channel to connect to VOUT. This
feature is essential in cascading applications. For applica-
tions where EN could be driven below ground, limit the
current from EN with a 10k resistor. Forcing SHDN below
0.8V turns off all external P-channel MOSFETs, disables
all OV and UV comparators and resets all validation tim-
ers. VALID1 and VALID2 release high to indicate all inputs
are invalid, regardless of the input supply condition. The
LTC4418 is required to revalidate the input supplies before
connecting the inputs to VOUT. For applications where
SHDN could be driven below ground, limit the current
from SHDN with a 10k resistor. If EN or SHDN are not
used then each can be connected to INTVCC.
INPUT SUPPLY AND VOUT SHORTS
Input shorts can cause high current slew rates. Coupled
with series parasitic inductances in the input and output
paths, potentially destructive transients may appear at the
input and output pins. If the short occurs on an input that
is not powering VOUT, the impact to the system is benign
due to the P-channel MOSFETs having reverse block
capability. If a short occurs on an input that is power-
ing VOUT, the issue is compounded by high conduction
current and low impedance connection to the output via
the P-channel MOSFETs. Once the LTC4418 blocks the
high input short current, V1 and V2 may experience large
negative voltage spikes while the output may experience
large positive voltage spikes.
If VOUT is shorted there will be an input supply UV fault
due to its low impedance connection. If the UV threshold is
high enough and the short resistive enough, the LTC4418
will disconnect the input. If the other input supply is valid
it will attempt to connect. Rapid switching between sup-
plies may occur if tVALID is configured to be too short in
duration or in Fast Mode. The fast change in current may
force the output below GND, while the input will increase
in voltage. If UV thresholds are set close to the minimum
operating voltage of the LTC4418, it may not disconnect
the input from the output before the output is dragged
below the operating voltage of the LTC4418.
Placing a bypass capacitor from INTVCC to GND keeps the
internal rail of the LTC4418 from collapsing due to these
types of transients. To prevent damage to the LTC4418
and associated devices in the event of an input or output
short, it may be necessary to protect the input and output
pins as shown in Figure5.
Protect the input pins with either unidirectional or bidirec-
tional TVS and VOUT with a unidirectional TVS. In situations
where VOUT has the potential to get pulled below ground
place a reverse Schottky diode from VOUT to GND or a
small series resistance with the VOUT pin to limit current.
An input and output capacitor between 0.1µF and 10µF
with intentional or parasitic series resistance will aid in
dampening voltage spikes.
CASCADING
The LTC4418 is cascadable and can work in conjunction
with the LTC4417 to prioritize three or more input sup-
plies. When cascading multiple LTC4418s, connect VOUT
pins together and connect each LTC4418 CAS pin to the
next lower priority LTC4418’s EN pin. See Figure6. The
first LTC4418 to validate an input will soft-start the com-
mon output. Once the output is above 2.5V, power will be
drawn from VOUT by the other LTC4418 regardless of its
supply connections. When the master LTC4418 wants to
connect one of its input supplies to the VOUT, it simultane-
ously initiates a channel turn on and pulls its CAS pin low
to force the slave LTC4418 to disconnect its channels.
A small amount of reverse conduction may occur in this
case. The amount of cross conduction will depend on
the total turn-on delay of the master channel compared
with the turn-off delay of the slave channel. Care should
be taken to ensure the connection between CAS and EN
is as short as possible, to minimize the capacitance and
hence the turn-off delay of the slave channel.
When all of the inputs to the master LTC4418 are invalid,
the master confirms that all its inputs are disconnected
from VOUT before releasing CAS. CAS is pulled to the
INTVCC rail with a 20µA current source, allowing the slave
LTC4418
20
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
LTC4418 to connect its highest valid priority channel to
VOUT. Confirmation that all channels are off before the
slave is allowed to connect its channel to VOUT prevents
cross conduction from occurring.
Driving the master LTC4418’s EN low forces both master
and slave to disconnect all channels from the common
output and continue monitoring the input supplies. Driv-
ing the master LTC4418’s SHDN low places it in a reset
state where all of its channels are disconnected and CAS is
pulled high with a 20µA current source, allowing the slave
LTC4418 to become the master and connect its highest
valid priority channel to the common output.
DESIGN EXAMPLE
In this example, the LTC4418 prioritizes between 5V and
12V supplies for a 1.25A system as shown in Figure7.
Power is only sourced from the 12V supply when the 5V
supply is invalid. The 12V supply has a 20mΩ source
resistance (RSRC) and the ambient conditions of the
system are between 25°C and 85°C. The design must
accommodate ±2.5% tolerance on the 5V supply and a
±10% tolerance on the 12V supply and limit the VOUT
droop to 500mV during switchover. The load capacitor
is assumed to be an electrolytic with a minimum ESR
(ESRCOUT) of 25mΩ at 25°C.
Determining OV/UV Windows
For the 5V V1 supply, ±2.5% tolerance sets an operational
window of 4.875V to 5.125V. In order to accommodate this
voltage range the OV/UV thresholds must allow for desired
hysteresis, external resistive divider error and comparator
threshold error. For the 5V V1 supply, an additional ±2.5%
error is included for margin which means that the OV/UV
window must accommodate 4.75V to 5.25V range. For 5%
external hysteresis or 250mV, set the UV1 = 4.5V and OV1
= 5.5V. For the 12V V2 supply, taking into account supply
tolerance and a margin for error sources the operational
window is 10.2V to 13.78V. Since external hysteresis is
used, channel 2 also has 250mV of hysteresis (±2.1%).
The OV/UV thresholds are UV2 = 9.95V and OV2 = 14.03V.
These thresholds determine the maximum possible dif-
ferential voltage between supplies at switchover.
M3
M4
LTC4418
MASTER
CAS TO EN CONNECTION
VS2
G2
VOUT
CAS
EN
SHDN
DISABLE ALL CHANNELS
SHDN MASTER
2 SUPPLIES
MASTER
2 SUPPLIES
SLAVE
1ST PRIORITY
SUPPLY
2ND PRIORITY
SUPPLY
4TH PRIORITY
SUPPLY
3RD PRIORITY
SUPPLY
M1
M2
VS1
G2
M5
M6
LTC4418
SLAVE
VS5
G6
VOUT
EN
SHDN
M7
M8
VS7
G8
4418 F06
+
VOUT
COUT
Figure6. Cascaded Application
LTC4418
21
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure7. Design Example Schematic 5V/12V System
CHANNEL 1 2
UV THRESHOLD 4.5V 9.95V
OV THRESHOLD 5.5V 14.13V
HYSTERESIS 250mV 250mV
INRUSH LIMIT – 12A
VALIDATION DELAY 16ms 16ms
VOUT DROOP MAX 500mV
V2
UV2
OV2
LTC4418
4418 F07
VS1 G1 VS2 G2
R3
1M
CVS1
100nF
R2
53.6k
R1
232k
R6
1M
R5
33.2k
R4
78.7k
CVS2
470nF
DS
BAT46WJ
M3 M4
CS
47nF
RS
698Ω
R7
100k
V1 INVALID
V2 INVALID
COUT
82µF
25mΩ ESR
VOUT
1.25A
V1
UV1
OV1
VOUT
VALID1
VALID2
CAS
INTVCC
EN
SHDN
TMR
+
CIN1
10µF
+
CIN2
10µF
+
FDS4465
M1 M2
FDS4465
5V SYS
12V WALL
ADAPTER
INPUT IMPEDANCE: 20mΩ
GND
CV1
100nF
CV2
100nF
HYS
RHYS
255k
CTMR
1nF
CINTVCC
100nF
R8
100k
LT3060-3.3
LTC4418
22
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
P-Channel MOSFET Selection
Using the list of suggested P-channel MOSFETs in Table1
as a guideline, the FDS4465 (Max VDS = –20V, RDS(ON) =
8.5mΩ) is appropriate for this application. When selecting
external MOSFETs the following items are relevant:
1. MAX VDS
2. RDS(ON)
3. IDM
4. CRSS (Maximum)
5. VGS (At IINRUSH + ILOAD Current)
6. SOA
Inrush Current Component Selection
The UV2 threshold for V2 is larger than the OV/UV window
of V1. This means that there could be significant inrush
current during switchover from V1 to V2. There are two
inrush current issues to address:
1. Avoid damaging the P-channel MOSFETs by violating
their IDM specification
2. Prevent UV faults on channel 2 from V2 input droop
The maximum inrush current occurs when switching to
the V2 supply which has a maximum voltage of 14.03V.
The minimum voltage of VOUT is 4.5V if V1 is at its UV
threshold. For these conditions, the maximum inrush
current through the P-channel MOSFETs is:
MAX IINRUSH =V2(MAX) −VOUT(MIN)
RSRC +ESRCOUT +2 • RDS(ON)
=14.03V −4.5V
0.02Ω + 0.025Ω + 0.17Ω
=154A
The 154A worst case inrush current far exceeds the 50A
IDM spec of the FDS4465. The worst case condition for
generating a UV fault on Channel 2 is if V2 is just above
UVHYS threshold of 10.2V. Given the input impedance of
20mΩ, the maximum tolerable inrush current is:
Tolerable IINRUSH =UVHYS2
R
SRC
=250mV
0.02Ω=12.5A
Based on these calculations, the target inrush current for
the V2 PowerPath switches is 12A. Now the appropriate
values for output capacitance and inrush current limiting
components are determined.
The first step is to calculate the minimum required output
capacitance, COUT, to satisfy the desired output voltage
droop, 500mV. Assume the inrush current limiting com-
ponents, RS and CS, add 15µs to the switchover time.
COUT ≥ILOAD • tG(SWITCHOVER) +15µs
( )
ΔVOUT(DROOP) −ESRCOUT • ILOAD
≥1.25A • (2.7µs +15µs)
500mV −1.25A • 25mΩ
≥47µF
For aluminum electrolytic capacitors add at least 20%.
For margin, choose 82µF for COUT for this application.
The inrush current limiting components must now be
determined. Information from the FDS4465 data sheet
required is VGS at IINRUSH + ILOAD which is 1.25V at ap-
proximately 12A and the maximum value of CRSS which
is 4000pF. The minimum value of CS is 10 • CRSS or 40nF
so a 47nF CS value is selected. Next calculate RS using
the maximum specification for ∆VG(SINK):
RS≥(ΔVG(SINK) −VGS )•COUT
CS• IINRUSH(TARGET)
≥(6V −1.25V) • 82µF
47nF • 12A
≥690.6Ω
where the closest 1% value is 698Ω.
With the inrush current limiting components known, the
desired output capacitance is checked with the equation:
COUT ≥ILOAD • tG(SWITCHOVER) +0.79 • RS• CS
( )
ΔVOUT(DROOP) −ESR • ILOAD
≥1.25A • (2.7µs +0.79 • 698Ω• 47nF)
500mV −25mΩ
≥71.54µF
The selected 82µF output capacitance is therefore suit-
able. A typical value for CVS1 and CVS2 is 0.1µF. For the
situation where inrush current limiting components are
used, so CVS2 is chosen to be 0.47µF.
LTC4418
23
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
External P-Channel MOSFET Power Dissipation
The SOA of the P-channel MOSFET should be checked
to ensure it is not violated. Worst case channel turn on
time for the V2 power path occurs for the same condition
used to determine inrush current limiting components for
a maximum inrush current of 12A.
dt =V2(MAX) −VOUT(MIN)
( )
• COUT
IINRUSH(TARGET)
=(14.05V −4.5V) • 82µF
12A
=62µs
Checking the Maximum Safe Operating Area plot in the
FDS4465 data sheet shows that it must withstand 12A at
10V worst case (120W) for 62µs. The SOA plot for the
FDS4465 shows that it can conduct 50A at 10V (1kW)
for 100µs satisfying the requirement. The Maximum Safe
Operating Area plot can also be checked with regard to
the soft-start power dissipation.
Setting Operational Range
The 5V supply has a ±2.5% operational window in this
example. The thresholds chosen give an additional 2.5%
margin in each direction. Instead of using the internal
fixed 150mV (or 3%) hysteresis, the higher priority 5V
supply is set for 250mV hysteresis using an external hys-
teresis current (IEXT) of 250nA. The resistive divider will
be configured as a Three-Resistive network. First select
an appropriate RHYS value:
RHYS =63mV
250nA
=252kΩ
where the closest 1% value is 255kΩ.
IEXT =63mV
255kΩ
=247nA
R3 is calculated from:
R3 =
Desired Hysteresis
IEXT
=
250mV
247nA =1012kΩ
where the closest 1% value is 1000kΩ.
Next, calculate R1 from:
R1=VTH
OV1 •1
UV1/ VTH
( )
−1+1
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟• R3
=1V
5.5V •1
4.5V / 1V
( )
−1+1
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟• 1MΩ = 233.7kΩ
where the closest 1% value is 232kΩ.
R2 can be calculated from:
R2 =R3
(UV1/ VTH)−1−R1
=1MΩ
(4.5V / 1V)
−
1−232kΩ = 53.7kΩ
where the closest 1% value is 53.6kΩ.
The actual UV threshold is:
UV1=VTH •
R1
+
R2
+
R3
R1+R2 =4.5V
UV1
HYS =R3 • IEXT =1MΩ• 247nA =247mV
Likewise, the actual OV threshold is:
OV1=VTH •R1+R2 +R3
R1 =5.54V
OV1
HYS =(R2 +R3) • IEXT
=(113kΩ + 1MΩ) • 247nA =260mV
The values of R4 through R6 are calculated similarly using
the configured hysteresis current. If internal hysteresis is
desired, the resistor values for a Three-Resistive network
can be determined by initially selecting resistive divider
current and using it to determine R1-R3 or RSUM. The choice
of resistive divider values should take into consideration
board and OV/UV pin leakages. The hysteresis thresholds
are calculated by:
UV(Rising) =VTH +VHYS(INT)
( )
• RSUM
R1+R2
UV(Falling) =VTH +VHYS(INT)
( )
• RSUM
R1
LTC4418
24
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure8. LTC4418 Layout Example
FROM V1
INPUT SOURCE
FROM V2
INPUT SOURCE
GND
GND
4418 F08
TO OUTPUT
NOTE: NOT TO SCALE
CINTVCC
CVS2
CVS1
CV1
M1
M2
M3
M4
CS1
0.03" PER
AMPERE
TRANSIENT
VOLTAGE
SUPPRESSOR
CTMR
R1
R3
R6
R4
CV2
RHYS
S
RS1
DS1
G
G
S
D
D
G
S
D
S
G
D
R2
R5
TMR
UV1
OV1
UV2
OV2
VOUT
VS1
G1
VS2
G2
HYS
SHDN
EN
V1
V2
VALLID1
VALID2
GND
CAS
INTVCC
20 19 18 17 16
678
GND
21
9 10
5
4
3
2
1
11
12
13
14
15
Using internal hysteresis in this application would result
in 130mV UV hysteresis and 170mV OV hysteresis for V1.
Likewise, the V2 OV/UV window would result in 300mV
UV hysteresis and 420mV OV hysteresis.
Layout Consideration
High current applications demand careful attention to trace
resistances. Sheet resistance of 1oz copper is ~530µΩ
per square. Keep high current traces short with minimum
trace widths of 0.02" per Amp to ensure traces stay at a
reasonable temperature. Using 0.03" per Amp or wider is
recommended. To improve noise immunity, place OV/UV
resistive dividers as close to the LTC4418 as possible.
Transient voltage suppressors should be located as close
to the input connector as possible with short wide traces
to GND. Figure8 shows a partial layout that addresses
these issues.
Dual 28V System with Kelvin Sense Connection
Through Connector
The dual 28V supply system in Figure13 includes a back-
plane connector with a kelvin sense. The supply pin and
resistive divider network for each channel are connected
to the kelvin sense. A rapid disconnection of one of the
input supplies from the backplane causes an immediate
UV fault since the time constant at V1/2 and the respective
OV/UV pins is much shorter than at the output. Without a
kelvin sense connection the input supply must discharge
down to its UV threshold over a period of time before
switchover. Both input supplies include transient voltage
suppression diodes (SMBJ36CA) rated for 36V operation
and a clamping voltage of 58V.
LTC4418
25
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
Figure9. Dual 5V System
V2
UV2
OV2
LTC4418
4418 F09
VS1 G1 VS2 G2
R3
1.15M
R2
82.5k
R1
255k
R6
1.15M
R5
82.5k
R4
255k
CVS2
470nF
CVS1
470nF
M3 M4
R7
100k
SYSA INVALID
SYSB INVALID
CIN3
82µF
25mΩ ESR
VOUT
1.5A MAX
CS2
47nF
DS2
BAT46WJ
V1
UV1
OV1
VOUT
VALID1
VALID2
CAS
INTVCC
EN
SHDN
TMR
+
Si4465DY
M1 M2
Si4465DY
5V ±2.5%
SYS A
IMPUT IMPEDANCE: 25mΩ
5V ±2.5%
SYS B
IMPUT IMPEDANCE: 25mΩ
GND
CV1
100nF
HYS
RHYS
210k
CTMR
1nF
CINTVCC
100nF
RS2
422Ω
R8
100k
CV2
100nF
CIN1
10µF
+
CIN2
10µF
+
CS1
47nF
DS1
BAT46WJ
RS1
422Ω
CHANNEL 1 2
UV THRESHOLD 4.4V 4.4V
OV THRESHOLD 5.85V 5.85V
HYSTERESIS 350mV 350mV
INRUSH LIMIT 25A 25A
VALIDATION DELAY 16ms 16ms
VOUT DROOP MAX 400mV
LTC4418
26
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
Figure10. 5V USB and AA Alkaline Battery Backup
V2
UV2
OV2
LTC4418
4418 F10
VS1 G1 VS2 G2
R3
402k
R2
30.9k
R1
90.9k
R6
402k
R7
562k
R5
76.8k
R4
78.7k
CVS2
0.1µF
CVS1
0.1µF
M3 M4
R9
1M
V1 INVALID
V2 INVALID
COUT
33µF
30mΩ ESR
VOUT
500mA MAX
V1
UV1
OV1
VOUT
VALID1
VALID2
CAS
INTVCC
EN
SHDN
TMR
+
IRF7325
M1 M2
IRF7325
5V USB
4× AA
BATTERIES
GND
CV1
0.1µF
HYS
RHYS
255k
CINTVCC
100nF
CTMR
1nF
R10
1M
CV2
0.1µF
CIN1
10µF
+
VBAT
INPUT IMPEDANCE: 900mΩ
R8
105k
CHANNEL 1 2
UV THRESHOLD 4.3V 3.6V
OV THRESHOLD 5.76V 7.1V
HYSTERESIS 100mV 600mV (UV)
300mV (OV)
INRUSH LIMIT – –
VALIDATION DELAY 16ms 16ms
VOUT DROOP MAX 500mV
LTC4418
27
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
Figure11. 12V System with 24V Backup Supply
V2
UV2
OV2
LTC4418
4418 F11
VS1 G1 VS2 G2
R3
634k
CVS1
100nF
R2
23.2k
RHYS
158k
R1
49.9k
R6
634k
R5
11.8k
R4
23.2k
CVS2
220nF
RS
1.96k
DS
BAT46WJ
M3 M4
CS
6.8nF
R7
1M
12V INVALID
24V INVALID
COUT
39µF
30mΩ ESR
VOUT
2A MAX
V1
UV1
OV1
VOUT
VALID1
VALID2
CAS
INTVCC
EN
SHDN
TMR
+
CIN1
39µF
+
CIN2
39µF
+
FDS4685
M1 M2
FDS4685
12V SYS
24V SYS
INPUT IMPEDANCE: 30mΩ
GND
CVS1
100nF
CV2
100nF
HYS
CTMR
1nF
CINTVCC
100nF
R8
1M
LT3060-3.3
CHANNEL 1 2
UV THRESHOLD 9.67V 19.17V
OV THRESHOLD 14.17V 28.84V
HYSTERESIS 250mV 250mV
INRUSH LIMIT – 8A
VALIDATION DELAY 16ms 16ms
VOUT DROOP MAX 1.2V
LTC4418
28
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
Figure12. Dual 24V System with Priority Swapped
V2
UV2
OV2
LTC4418
4418 F12
VS1 G1 VS2 G2
R3
1.87M
CVS1
68nF
R2
34.8k
R1
68.1k
R6
1.87M
R5
34.8k
R4
68.1k
CVS2
68nF
RS2
133Ω
DS2
BAT46WJ
M3 M4
CS2
6.8nF
R7
100k
V1 INVALID
CH PRIORITY SWAP
COUT
10µF
120mΩ ESR
VOUT
1A MAX
V1
UV1
OV1
VOUT
VALID1
VALID2
INTVCC
EN
SHDN
TMR
+
CIN1
47µF
+
CIN2
47µF
+
FDD4685
M1 M2
FDD4685
24V SYS A
INPUT IMPEDANCE: 30mΩ
24V SYS B
INPUT IMPEDANCE: 30mΩ
GND
CV1
100nF
CV2
100nF
HYS
CINTVCC
100nF
RHYS
158k
LT3060-3.3
RS1
133Ω
DS1
BAT46WJ
CS1
6.8nF
CHANNEL 1 2
UV THRESHOLD 19.17V 19.17V
OV THRESHOLD 29V 29V
HYSTERESIS 750mV 750mV
INRUSH LIMIT 50A 50A
VALIDATION DELAY 3.5µs 3.5µs
VOUT DROOP MAX 2.4V
CH PRIORITY IS SWAPPED - FAST MODE REQUIRED
LTC4418
29
Rev A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/18 Updated specification conditions: RG(OFF), tSS, ITMR 3, 4
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4418#packaging for the most recent package drawings.
4.00 ±0.10
4.00 ±0.10
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.00 REF
2.45 ±0.10
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF20) QFN 01-07 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.00 REF 2.45 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
2.45 ±0.10
2.45 ±0.05
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
LTC4418
30
Rev A
For more information www.analog.com
D16838-0-4/18(A)
www.analog.com
ANALOG DEVICES, INC. 2017-2018
RELATED PARTS
TYPICAL APPLICATION
Figure13. Dual 28V System with Kelvin Sense Connection Through Connector
PART NUMBER DESCRIPTION COMMENTS
LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal 2.6A P-Channel, 2.6V to 5.5V, 40µA IQ, SOT-23 Package
LTC4412 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-Channel, 11µA IQ SOT-23 Package
LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-Channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages
LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35µA IQ MSOP-10 Package
LTC4417 3-Channel Prioritized PowerPath Controller Triple P-Channel Controller, 2.5V to 36V, SSOP-24 and QFN-24 Packages
LTC4419/
LTC4420
18V Dual Input Micropower PowerPath Prioritizer Internal P-Channel, 1.8V to 18V, 3.6µA IQ, DFN-12 and MSOP-12 Packages
LTC4355 Positive High Voltage Ideal Diode-OR Dual N-Channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages
LTC4359 Ideal Diode Controller with Reverse Input Protection N-Channel, 4V to 80V, MSOP-8 and DFN-6 Packages
CHANNEL 1 2
UV THRESHOLD 22.4V 22.4V
OV THRESHOLD 33V 33V
HYSTERESIS 3% OV/UV 3% OV/UV
INRUSH LIMIT 10A 10A
VALIDATION DELAY 16ms 16ms
VOUT DROOP MAX 2.8V
V2
UV2
OV2
LTC4418
4418 F13
VS1 G1 VS2 G2
R3
1.33M
CVS1
470nF
100V
R2
20k
R1
42.2k
R6
1.33M
R5
20k
R4
42.2k
CVS2
470nF
100V
RS2
243Ω
DS2
BAT46WJ
M3 M4
CS2
47nF
R7
100k
V1 INVALID
V2 INVALID
COUTA
22µF
50V
170mΩ ESR
VOUT
3.5A
V1
UV1
OV1
VOUT
VALID1
VALID2
INTVCC
EN
SHDN
TMR
+
TVS1
SMBJ36CA
KELVIN
KELVIN
SUD50P06
M1 M2
SUD50P06
28V SYS
INPUT IMPEDANCE: 30mΩ
28V BACKUP
INPUT IMPEDANCE: 30mΩ
GND
CV2
100nF
100V
CV1
100nF
100V
HYS
CINTVCC
100nF
CTMR
1nF
R8
100k
LT3060-3.3
TVS2
SMBJ36CA
RS1
243Ω
DS1
BAT46WJ
CS1
47nF
CONNECTOR 4 CONNECTOR 2
CONNECTOR 3 CONNECTOR 1
COUTB
22µF
50V
170mΩ ESR
+