November 2006 Rev 1 1/36
36
VIPer53 - E
OFF-line primary switch
Features
■Switching frequency up to 300kHz
■Current limitation
■Current mode control with adjustable limitation
■Soft start and shut-down control
■Automatic burst mode in standby condition
(“Blue Angel“ compliant )
■Undervoltage lockout with Hysteresis
■HIgh voltage star-tup current source
■Overtemperature protection
■Overload and short-circuit control
Description
The VIPer53-E combines an enhanced current
mode PWM controller with a high voltage
MDMesh Power Mosfet in the same package.
Typical applications cover offline power supplies
with a secondary power capability ranging up to
30W in wide range input voltage, or 50W in single
European voltage range and DIP-8 package, with
the following benefits:
■Overload and short circuit controlled by
feedback monitoring and delayed device reset.
■Efficient standby mode by enhanced pulse
skipping.
■Primary regulation or secondary loop failure
protection through high gain error amplifier.
General features
Type European
(195 - 265Vac)
US / Wide range
(85 - 265 Vac)
DIP-8 50W 30W
PowerSO-10TM 65W 40W
DIP-8PowerSO-10
www.st.com
Block diagram
FF
OSCILLATOR
150/400ns
BLANKING
1V
4V
OVERTEMP.
DETECTOR
8.4/
11.5V
15V
0.5V
VDD
OSC DRAIN
TOVL COMP SOURCE
PWM
LATCH
ON/OFF
BLANKING TIME
SELECTION
PWM
COMPARATOR
CURRENT
AMPLIFIER
S
R1
R2
R3 R4 R5
Q
8V
4.35V
OVERLOAD
COMPARATOR
18V 4.5V
125k
0.5V
STANDBY
COMPARATOR
OVERVOLTAGE
COMPARATOR
ERROR
AMPLIFIER
UVLO
COMPARATOR H
COMP
Contents VIPer53 - E
2/36
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Primary regulation configuration example . . . . . . . . . . . . . . . . . . . . . . 15
6 Secondary feedback configuration example . . . . . . . . . . . . . . . . . . . . 17
7 Current mode topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 High voltage Start-up current source . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10 Short-circuit and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12 Special recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13 Software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VIPer53 - E Electrical data
3/36
1 Electrical data
1.1 Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
1.2 Thermal data
Table 1. Absolute maximum rating
Symbol Parameter Value Unit
VDS Continuous drain source voltage (TJ= 25 ... 125°C) (1) -0.3 ... 620 V
IDContinuous drain current Internally limited A
VDD Supply voltage 0 ... 19 V
VOSC OSC input voltage range 0 ... VDD V
ICOMP
ITOVL
COMP and TOVL input current range (1)
1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ
should be inserted in series with the TOVL pin.\
-2 ... 2 mA
VESD
Electrostatic discharge:
Machine model (R = 0Ω; C = 200pF)
Charged device model
200
1.5
V
kV
TJJunction operating temperature Internally limited °C
TC Case operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150 °C
Table 2. Thermal data
Symbol Parameter PowerSO-10 (1)
1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the DRAIN pin.
DIP-8 (2)
2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the device tab.
Unit
RthJC Thermal Resistance Junction-case Max 2 20 °C/W
RthJA Thermal Resistance Ambient-case Max 60 80 °C/W
Electrical characteristics VIPer53 - E
4/36
2 Electrical characteristics
TJ = 25°C, VDD = 13V, unless otherwise specified
Table 3. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
BVDSS Drain-source voltage ID = 1mA; VCOMP = 0V 620 V
IDSS Off state drain
current
VDS = 500V; VCOMP = 0V;
TJ = 125°C 150 µA
RDS(on)
Static drain-source
On state resistance
ID = 1A; VCOMP = 4.5V; VTOVL = 0V
TJ = 25°C
TJ = 100°C
0.9 1
1.7
Ω
Ω
tfv Fall time ID = 0.2A; VIN = 300V (1)
1. On clamped inductive load
100 ns
trv Rise time ID = 1A; VIN = 300V (1) 50 ns
Coss Drain capacitance VDS = 25V 170 pF
CEon Effective output
capacitance 200V < VDSon < 400V (2)
2. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain
to source voltage VDSon and the following formula:
60 pF
Table 4. Oscillator section
Symbol Parameter Test conditions Min. Typ. Max. Unit
FOSC1 Oscillator frequency
initial accuracy
RT = 8kΩ; CT = 2.2nF
Figure 12 on page 12 95 100 105 kHz
FOSC2 Oscillator frequency
total variation
RT = 8kΩ; CT = 2.2nF
Figure 16 on page 14
VDD = VDDon ... VDDovp;
TJ = 0 ... 100°C
93 100 107 kHz
VOSChi Oscillator peak
voltage 9V
VOSClo Oscillator valley
voltage 4V
Eton
1
2
---CEon 3002VDSon
300
----------------
⎝⎠
⎛⎞
1.5
⋅⋅⋅=
VIPer53 - E Electrical characteristics
5/36
Table 5. Supply section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VDSstart Drain voltage starting
threshold VDD = 5V; IDD = 0mA 34 50 V
IDDch1 Startup charging current VDD = 0 ... 5V; VDS = 100V
Figure 5 on page 10 -12 mA
IDDch2 Startup charging current VDD = 10V; VDS = 100VFigure 5. -2 mA
IDDchoff
Startup charging current
in thermal shutdown
VDD = 5V; VDS = 100VFigure 7.
TJ > TSD - THYST
0mA
IDD0
Operating supply current
not switching Fsw = 0kHz; VCOMP = 0V 811mA
IDD1
Operating supply current
switching Fsw = 100kHz 9mA
VDDoff
VDD undervoltage
shutdown threshold Figure 5 on page 10 7.5 8.4 9.3 V
VDDon VDD startup threshold Figure 5. 10.2 11.5 12.8 V
VDDhyst VDD threshold hysteresis Figure 5. 2.6 3.1 V
VDDovp
VDD Overvoltage
shutdown threshold Figure 5. 17 18 19 V
Table 6. Error amplifier section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VDDreg VDD regulation point ICOMP = 0mA
Figure 11. on page 11 14.5 15 15.5 V
∆VDDreg
VDD regulation point
total variation ICOMP = 0mA; TJ = 0 ... 100°C 2 %
GBW Unity gain bandwidth
From Input = VDD to Output =
VCOMP
ICOMP = 0mA Figure 14 and 15
700 kHz
AVOL Voltage gain ICOMP = 0mA Figure 14 and 15 40 45 dB
GmDC transconductance VCOMP = 2.5V Figure 11. 11.41.8mS
VCOMPlo Output low level ICOMP = -0.4mA; VDD = 16V 0.2 V
VCOMPhi Output high level ICOMP = 0.4mA; VDD=14V(1)
1. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should
always be present on the COMP pin.
4.5 V
ICOMPlo Output sinking current VCOMP = 2.5V; VDD = 16V
Figure 11. on page 11 -0.6 mA
ICOMPhi Output sourcing current VCOMP = 2.5V; VDD= 14V
Figure 11. 0.6 mA
Electrical characteristics VIPer53 - E
6/36
Table 9. Over temperature Protection Section
Table 7. PWM comparator section
Symbol Parameter Test conditions Min. Typ. Max. Unit
HCOMP ∆VCOMP / ∆IDPEAK
VCOMP = 1 ... 4 V Figure 10.
dID/dt = 0 1.7 2 2.3 V/A
VCOMPos VCOMP Offset dID/dt = 0 Figure 10. on page 11 0.5 V
IDlim Peak drain current
limitation
ICOMP = 0mA; VTOVL = 0V
Figure 10.
dID/dt = 0 1.7 2 2.3 A
IDmax Drain current
capability
VCOMP = VCOMPovl; VTOVL = 0V
dID/dt = 0 1.6 1.9 2.3 A
tdCurrent sense delay to
Turn-Off ID = 1A 250 ns
VCOMPbl
VCOMP blanking time
change threshold Figure 6 on page 10 1V
tb1 Blanking time VCOMP < VCOMPBLFigure 6. 300 400 500 ns
tb2 Blanking time VCOMP > VCOMPBLFigure 6. 100 150 200 ns
tONmin1 Minimum On time VCOMP < VCOMPBL 450 600 750 ns
tONmin2 Minimum On time VCOMP > VCOMPBL 250 350 450 ns
VCOMPoff
VCOMP Shutdown
Threshold Figure 9 on page 11 0.5 V
Table 8. Overload protection section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCOMPovl
VCOMP overload
threshold
ITOVL = 0mA (1)
Figure 4 on page 9
1. VCOMPovl is always lower than VCOMPhi
4.35 V
VDIFFovl
VCOMPhi to VCOMPovl
voltage difference
VDD = VDDoff ... VDDreg;
ITOVL= 0mA
Figure 4. (1)
50 150 250 mV
VOVLth
VTOVL overload
threshold Figure 4. 4V
tOVL Overload delay COVL = 100nF Figure 4. 8ms
Symbol Parameter Test Conditions Min. Typ. Max. Unit
TSD Thermal shutdown
temperature Figure 7 on page 10 140 160 °C
THYST Thermal shutdown
hysteresis Figure 7 on page 10 40 °C
VIPer53 - E Pin connections and function
7/36
3 Pin connections and function
Figure 1. Pin connection (top view)
Figure 2. Current and voltage conventions
SOURCE
TOVLCOMP
VDD
NC
DRAIN
SOURCE
1
54
8
7
6
2
3
OSC
DIP-8 PowerSO-10
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
I
DD
V
DD
I
OSC
V
OSC
I
TOVL
V
TOVL
I
COMP
V
COMP
I
D
V
D
S
Pin connections and function VIPer53 - E
8/36
Table 10. Pin function
Pin Name Pin function
VDD
Power supply of the control circuits. Also provides the charging current of the external
capacitor during start-up. The functions of this pin are managed by four threshold
voltages:
- VDDon: Voltage value at which the device starts switching (Typically 11.5 V).
- VDDoff: Voltage value at which the device stops switching (Typically 8.4 V).
- VDDreg: Regulation voltage point when working in primary feedback
(Trimmed to 15 V).
- VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).
SOURCE Power MOSFET source and circuit ground reference.
DRAIN Power MOSFET drain. Also used by the internal high voltage current source during the
start-up phase to charge the external VDD capacitor.
COMP
Input of the current mode structure, and output of the internal error amplifier. Allows
the setting of thedynamic characteristic of the converter through an external passive
network. The useful voltage range extends from 0.5V to 4.5V. The Power MOSFET is
always off below 0.5V, and the overload protection is triggered if the voltage exceeds
4.35V. This action is delayed by the timing capacitor connected tothe TOVL pin.
TOVL Allows the connection of an external capacitor for delaying the overload protection,
which is triggered by a voltage on the COMP pin higher than 4.35V.
OSC Allows the setting of the switching frequency through an external Rt-Ct network.
VIPer53 - E Operation pictures
9/36
4 Operation pictures
Figure 3. Rise and fall time
Figure 4. Overloaded event
I
D
V
DS
90%
10%
t
fv
t
rv
t
t
300
V
CLD
C<<C
OSS
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
Normal
operation
VTOVL
VCOMP
VDD
VDDon
VDDoff
VDS
Switching
Not
switching
Abnormal
operation
VOVLth tOVL
VDIFFovl
Operation pictures VIPer53 - E
10/36
Figure 5. Start-up VDD current Figure 6. Blanking time
Figure 7. Thermal shutdown Figure 8. Overvoltage event
IDD
VDD
VDDhyst
VDDoff VDDon
IDD0
IDDch1
IDDch2
VDS = 100 V
FSW = 0 kHz
tb
tb1
tb2
VCOMPbl VCOMPhi
VDD
VCOMP
Tj
VDDon
TSD
TSD-THYST
Automatic
startup
Abnormal
operation
VDS
VCOMP
VDD
VDDovp
Switching
Not
switching
VIPer53 - E Operation pictures
11/36
Figure 9. Shutdown action Figure 10. Comp pin gain and offset
Figure 11. Output characteristics
t
t
I
D
V
COMP
t
V
OSC
V
COMPoff
V
OSChi
V
OSClo
V
COMP
I
Dpeak
V
COMPos
V
COMPhi
Slope = 1 / H
COMP
I
Dlim
V
COMPovl
I
Dmax
ICOMP
VDD
VDDreg
ICOMPhi
ICOMPlo
0
Slope = Gm
Operation pictures VIPer53 - E
12/36
Figure 12. Oscillator schematic
The switching frequency settings shown on the graphic here below is valid within the
following boundaries:
Rt > 2kΩ
FSW = 300kHz
Figure 13. Oscillator settings
320 Ω
SOURCE
OSC
VDD
PWM
section
Ct
Rt
Vcc
110100
10
300
100
Frequency (kHz)
R
T
(KΩ)
1nF
2.2nF
4.7nF
10nF
22nF
VIPer53 - E Operation pictures
13/36
Figure 14. Error amplifier test cpfiguration
This configuration is for test purpose only. In order to insure a correct stability of the error
amplifier, a capacitor of 10nF (minimum value: 8nF) should be always connected between
COMP pin and ground. See figures Figure 18, 19 and 22.
Figure 15. Error amplifier transfer function
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
R
2.5 V
Vin
Vout
-60
-40
-20
0
20
40
60
Gain (dB)
Frequency (Hz)
Open
R = 10 kΩ
R = 2.2 kΩ
R = 47 0 Ω
1 10 100 1k 10k 100k 1M 10M
Operation pictures VIPer53 - E
14/36
Figure 16. Typical frequency variation vs. junction temperature
Figure 17. Typical current limitation vs. junction temperature
-20 0 20 40 60 80 100 120
0.96
0.98
1
1.02
1.04
Norm alised Frequency
Tem perature (°C)
-20 0 20 40 60 80 100 120
0.96
0.98
1
1.02
1.04
Normalised IDlim
Temperature (°C)
VIPer53 - E Primary regulation configuration example
15/36
5 Primary regulation configuration example
Figure 18. Off line power supply with auxiliary supply feedback
The schematic on Figure 18 delivers a fixed output voltage by using the internal error
amplifier of the device in a primary feedback configuration. The primary auxiliary winding
provides a voltage to the VDD pin, and is automatically regulated at 15V, due to the internal
error amplifier connected to this pin. The secondary voltage has to be adjusted through the
turn ratio of the transformer between auxiliary and secondary.
The error amplifier of the VIPer53 is a transconductance type: its output is a current
proportional to the difference of voltage between the VDD pin and the internally trimmed 15V
reference (i.e., the error voltage). As the transconductance value is set at a relatively low
value to control the overall loop gain and ensure stability, this current has to be integrated by
a capacitor (C7 in Figure 18). When the steady state operation is reached, this capacitor
blocks any DC current from the COMP pin and imposes a “nil” error voltage. Therefore, the
VDD voltage is accurately regulated to 15V.
This results in a good load regulation, which depends only on transformer coupling and
output diodes impedance. The current mode structure takes care of all incoming voltage
changes, thus providing at the same time an excellent line regulation.
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
U1
VIPer73
R3
R4 D3
D1
C1
T1
C2
F1
R1
D2
C7
C5
C4
C6
T2
D4 C8
C10
L1
C9
R2
C3
AC IN
DC OUT
C11
10nF
R5
R6
1k
Primary regulation configuration example VIPer53 - E
16/36
The switching frequency can be set to any value through the choice of R3 and C5. This
allows to optimize the efficiency of the converter by adopting the best compromise between
switching losses, EMI (Lower with low switching frequencies) and transformer size (Smaller
with high switching frequencies). For an output power of a few watts, typical switching
frequencies between 20kHz and 40kHz because of the small size of the transformer. For
higher power, 70kHz to 130kHz are generally chosen.
The R5 compensation resistor value sets the dynamic behavior of the converter. It can be
adjusted to provide the best compromise between stability and recovery time with fast load
changes.
VIPer53 - E Secondary feedback configuration example
17/36
6 Secondary feedback configuration example
When a more accurate output voltage is needed, the way is to monitor it directly secondary
side, and drive the PWM controller through an optocoupler as shown on Figure 17.
The optocoupler is connected in parallel with the compensation network on the COMP pin.
The design of the auxiliary winding that the VDD voltage is always lower than the internal
15V reference. The internal error amplifier will therefore be saturated in the high state, and
because of its transconductance nature, will deliver a constant biasing current of 0.6mA to
the optotransistor. This current does not depend on the compensation voltage, and so it
does not depend on the output load either. Consequently, the gain of the optocoupler
ensures consequently a constant biasing of the TL431 device (U3) which is in charge of
secondary regulation. If the optocoupler gain is sufficiently low, no additional components
are required to ensure a minimum current biasing of U3. Also, the low biasing current value
avoid any ageing of the optocoupler.
The constant current biasing can be used to simplify the secondary circuit: Instead of a
TL431, a simple zener and resistance network in series with the optocoupler diode can
insure a good secondary regulation. As the current flowing in this branch remains constant
for the same reason as above, typical load regulation of 1% can be achieved from zero to full
output current with this simple configuration.
Figure 19. Off line power supply with optocoupler feedback
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
U1
VIPer73
R5
R3
R4 D3
D1
C1
T1
C2
F1
R1
D2
C7
C5
C4
C6
T2
D4 C8
C10
L1
C9
R2
C3
AC IN
DC OUT
U2
U3
C12
R6
R7
R8
C11
10nF
R9
1k
Secondary feedback configuration example VIPer53 - E
18/36
Since the dynamic characteristics of the converter are set on the secondary side through
components associated to U3, the compensation network has only a role of gain
stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed
value of 1kΩ, offering the possibility of using C7 as a soft start capacitor: When starting up
the converter, the VIPer53 device delivers a constant current of 0.6 mA on the COMP pin,
creating a constant voltage of 0.6V in R5 and a rising slope across C7. This voltage shape,
together with the operating range of 0.5V to 4.5V provides a soft start-up of the converter.
The rising speed of the output voltage can be set through the value of C7. The C4 and C6
values must be adjusted accordingly in order to ensure a correct start-up.
VIPer53 - E Current mode topology
19/36
7 Current mode topology
The VIPer53-E implements the conventional current mode control method for regulating the
output voltage. This kind of feedback includes two nested regulation loops:
The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored
with a SenseFET technique and converted into a voltage. When VS reaches VCOMP
, the
power switch is turned off. This structure is completely integrated as shown on the Block
Diagram on page 1, with the current amplifier, the PWM comparator, the blanking time
function and the PWM latch. The following formula gives the peak current in the Power
MOSFET according to the compensation voltage:
Equation 1
The outer loop defines the level at which the inner loop regulates peak current in the power
switch. For this purpose, VCOMP is driven by the feedback network (TL431 through an
optocoupler in secondary feedback configuration, see Figure 19 on page 17) and is sets
accordingly the peak drain current for each switching cycle.
As the inner loop regulates the peak primary current in the primary side of the transformer,
all input voltage changes are compensated for before impacting the output voltage. This
results in an improved line regulation, instantaneous correction to line changes, and better
stability for the voltage regulation loop.
Current mode topology also provides a good converter start-up control. The compensation
voltage can be controlled to increase slowly during the start-up phase, so the peak primary
current will follow this soft voltage slope to provide a smooth output voltage rise, without any
overshoot. The simpler voltage mode structure which only controls the duty cycle, leads
generally to high current at start-up with the risk of transformer saturation.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in the case of current spikes caused by primary side
transformer capacitance or secondary side rectifier reverse recovery time when working in
continuous mode.
IDpeak
VCOMP VCOMPos
–
HCOMP
--------------------------------------------------=
Standby mode VIPer53 - E
20/36
8 Standby mode
The device offers a special feature to address the low load condition. The corresponding
function described hereafter consists of reducing the switching frequency by going into burst
mode, with the following benefits:
– It reduces the switching losses, thus providing low consumption on the mains lines.
The device is compliant with “Blue Angel” and other similar standards, requiring less
than 0.5 W of input power when in standby.
– It allows the regulation of the output voltage, even if the load corresponds to a duty
cycle that the device is not able to generate because of the internal blanking time, and
associated minimum turn on.
For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM
latch and the Power MOSFET in the Off state as long as VCOMP remains below 0.5V (See
Block Diagram on page 1). If the output load requires a duty cycle below the one defined by
the minimum turn on of the device, the VCOMP net decreases its voltage until it reaches this
0.5V threshold (VCOMPoff). The Power MOSFET can be completely Off for some cycles, and
resumes normal operation as soon as VCOMP is higher than 0.5V. The output voltage is
regulated in burst mode. The corresponding ripple is not higher than the nominal one at full
load.
In addition, the minimum turn on time which defines the frontier between normal operation
and burst mode changes according to VCOMP value. Below 1.0V (VCOMPbl), the blanking
time increases to 400ns, whereas for higher voltages, it is 150ns Figure 6 on page 10 The
minimum turn on times resulting from these values are respectively 600 ns and 350 ns,
when taking into account internal propagation time. This brutal change induces an
hysteresis between normal operation and burst mode as shown on Figure 20 on page 21.
When the output power decreases, the system reaches point 2 where VCOMP equals
VCOMPbl. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding
the effective turn-on time that should be needed at this output power level. Therefore the
regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst
mode and to control the output voltage. The corresponding hysteresis can be seen on the
switching frequency which passes from FSWnom which is the normal switching frequency set
by the components connected to the OSC pin and to FSWstby. Note: This frequency is
actually an equivalent number of switching pulses per second, rather than a fixed switching
frequency since the device is working in burst mode.
As long as the power remains below PRST the output of the regulation loop remains stuck at
VCOMPsd and the converter works in burst mode. Its “density” increases (i.e. the number of
missing cycles decreases) as the power approaches PRST and finally resumes normal
operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be
seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power level.
The power points value PRST and PSTBY are defined by the following formulas:
Equation 2
PRST
1
2
---FSWnom
•tb1td+()•2V2
•IN 1
Lp
-------
•=
VIPer53 - E Standby mode
21/36
Equation 3
Where Ip(VCOMPbl2) is the peak Power MOSFET current corresponding to a compensation
voltage of VCOMPbl (1V).
Note: The power point PSTBY where the converter is going into burst mode does not depend on
the input voltage.
The standby frequency FSWstby is given by:
Equation 4
The ratio between the nominal and standby switching frequencies can be as high as 4,
depending on the Lp value and input voltage.
Figure 20. Standby mode implementation
PSTBY
1
2
---FSWnom
•Ip2VCOMPbl
()•Lp•=
PSWstby
PSTBY
PRST
----------------- FSWnom
•=
V
COMP
V
COMPsd
V
COMPbl
V
COMPoff
600ns
350ns
F
SW
P
IN
F
SWnom
F
SWstby
P
STBY
P
RST
Minimum 1
3
2
1
2
3
ton
turn on
High voltage Start-up current source VIPer53 - E
22/36
9 High voltage Start-up current source
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits in standby
mode with reduced consumption, and also supplies the external capacitor connected to the
VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the
UVLO logic, the device turns into active mode and starts switching. The start-up current
generator is switched off, and the converter should normally provide the needed current on
the VDD pin through the auxiliary winding of the transformer, as shown on Figure 19 on
page 17.
The external capacitor CVDD on the VDD pin must be sized according to the time needed by
the converter to start-up, when the device starts switching. This time tss depends on many
parameters, including transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin and possible secondary feedback
circuit.
The following formula can be used for defining the minimum capacitor needed:
Equation 5
Figure 21 on page 23 shows a typical start-up event. VDD starts from 0V with a charging
current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduced
down to IDDch2 which is about 0.6mA. This lower current leads to a slope change on the VDD
rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some
energy to VDD capacitor after the start-up time tss.
The charging current change at VDDoff allows a fast complete start-up time tSDU, and
maintains a low restart duty cycle. This is especially useful for short circuits and overloads
conditions, as described in the following section.
CVDD
IDD1 tss⋅
VDDhyst
---------------------------
>
VIPer53 - E High voltage Start-up current source
23/36
Figure 21. Start-up waveforms
IDD
IDD1
tSS
IDDch2
IDDch1
t
t
VDDsd
VDDst
VDDreg
VDD
tSU
Short-circuit and overload protection VIPer53 - E
24/36
10 Short-circuit and overload protection
A VCOMPovl threshold of about 4.35V has been implemented on the COMP pin. When
VCOMP goes above this level, the capacitor connected on the TOVL pin begins to charge.
When reaching typically VOVLth (4V), the internal MOSFET driver is disabled and the device
stops switching. This state is latched because of to the regulation loop which maintains the
COMP pin voltage above the VCOMPovl threshold. Since the VDD pin does not receive any
more energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and
the device is reset, recharging the VDD capacitor for a new restart cycle. Note: If VCOMP
drops below the VCOMPovl threshold for any reason during the VDD drop, the device
resumes switching immediately.
The device enters an endless restart sequence if the overload or short circuit condition is
maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries
to restart, thus delivering its full power capability to the output. In order to keep the whole
converter in a safe state during this event, DRST must be kept as low as possible, without
compromising the real start-up of the converter. A typical value of about 10% is generally
sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the
following conditions:
Equation 6
Equation 7
Refer to the previous start-up section for the definition of tss, and CVDD must also be
checked against the limit given in this section. The maximum value of the two calculus will
be adopted.
All this behavior can be observed on Figure 8 on page 10. In Figure 10 on page 11 the value
of the drain current Id for VCOMP = VCOMPovl is shown. The corresponding parameter IDmax
is the drain current to take into account for design purposes. Since IDmax represents the
maximum value for which the overload protection is not triggered, it defines the power
capability of the power supply.
COVL 12.5 10 6–tss⋅⋅>
CVDD 810
41
DRST
-------------- 1–
⎝⎠
⎛⎞
COVL IDDch2
⋅
VDDhyst
---------------------------------------
⋅⋅ ⋅>
VIPer53 - E Transconductance error amplifier
25/36
11 Transconductance error amplifier
The VIPer53-E includes a transconductance error amplifier. Transconductance Gm is the
change in output current ICOMP versus change in input voltage VDD. Thus:
Equation 8
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:
Equation 9
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP:
Equation 10
where Gm value for VIPer53 is typically 1.4mA/V.
Gm is well defined by specification, but ZCOMP, and therefore AVOL, are subject to large
tolerances. An impedance Z must be connected between the COMP pin and ground in order
to accurately define the transfer function F of the error amplifier, the following equation, very
similar to the one above:
Equation 11
The error amplifier frequency response is shown in .0 for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier
shows an internal ZCOMP of about 140KΩ. More complex impedances can be connected on
the COMP pin to achieve different compensation methods. A capacitor provides an
integrator function, thus eliminating the DC static error, and a resistance in series leads to a
flat gain at higher frequency, introducing a zero level and ensuring a correct phase margin.
This configuration illustrated in Figure 22, for the schematic and Figure 23 on page 28 for
the error amplifier transfer function for a typical set of values of CCOMP and RCOMP
.
Note that a 10nF capacitor (8nF, minimum value) should always be connected to the COMP
pin to ensure a correct stability of the internal error amplifier.
The complete converter open loop transfer function can be built from both power cell and
error amplifier transfer functions. A theoretical example can be seen in Figure 24 for a
discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no
Gm ∂ICOMP
∂VDD
--------------------=
ZCOMP
∂VCOMP
∂ICOMP
----------------------1
Gm
----------∂VCOMP
∂VDD
----------------------
⋅==
AVOL Gm ZCOMP
⋅=
Fs() Gm Z s()⋅=
Transconductance error amplifier VIPer53 - E
26/36
optocoupler, the internal error amplifier is fully used for regulation). A typical schematic
corresponding to this situation can be seen on Figure 18.
The transfer function of the power cell is represented as G(s) in Figure 24 Iexhibits a pole
which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, RL1 and RL2. A zero at higher frequency values then appears, due to the output
capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control.
The error amplifier has a fixed behavior, similar to the one shown in Figure 23. Its bandwidth
is to avoid injection of high frequency noise in the current mode section. A zero due to the
RCOMP-CCOMP network is set at the same value as the maximum load RL2 pole.
The total transfer function is shown as F(s). G(s) at the bottom of Figure 24. For maximum
load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and
the result is a perfect first order decreasing until it reaches the zero of the output capacitor
ESR. The error amplifier cut-off then definitely any further spurious noise or resonance from
disturbing the regulation loop.
The point where the complete transfer function has a unity gain is known as the regulation
bandwidth and has:
– The higher it is, the faster the reaction will be to an eventual load change, and the
smaller the output voltage change will be.
– The phase shift in the complete system at this point has to be less than 135° to
ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.
In Figure 24, the unity gain is reached in a first order slope, so the stability is ensured.
The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected: As the transfer function above the zero due the capacitor
ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take
place), the bandwidth should always be lower than the minimum of FC and ESR zero.
As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load
in Figure 24), the above criteria will be checked for this condition and allows to define the
value of RCOMP
, as the error amplifier gain depends only on this value for this frequency
range. The following formula can be derived:
Equation 12
RCOMP
POUT2
PMAX
-----------------
FBW2 RL2 COUT
⋅⋅
Gm
------------------------------------------------------
⋅=
POUT2
VOUT
2
RL2
--------------=PMAX
1
2
---LPILIM
2FSW
⋅⋅ ⋅=
With: and:
VIPer53 - E Transconductance error amplifier
27/36
The lowest load gives another condition for stability: The frequency FBW1 must not encounter
the second order slope generated by the load pole and the integrator part of the error
amplifier. This condition can be met by adjusting the CCOMP value:
Equation 13
The above formula gives a minimum value for CCOMP
. It can be then increased to provide a
natural soft start function as this capacitor is charged by the error amplifier current capacity
ICOMPhi at start-up.
Figure 22. Typical compensation network
CCOMP
RL1 COUT
⋅
6.3 Gm RCOMP
2
⋅⋅
------------------------------------------------------
POUT1
PMAX
-------------------⋅>
POUT1
VOUT
2
RL1
---------------=
With:
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
Rcomp
Ccomp
10nF
Transconductance error amplifier VIPer53 - E
28/36
Figure 23. Typical transfer functions
Frequency (Hz)
1 10 100 1k 10k 100k 1M
Gain (dB)
-10
0
10
20
30
40
50
60
Rcomp=4.7k
Ccomp=470nF
Frequency (Hz)
Phase (°)
1 10 100 1k 10k 100k 1M
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Rcomp=4.7k
Ccomp=470nF
VIPer53 - E Transconductance error amplifier
29/36
Figure 24. Complete converter transfer function
G(S)
F
FC
F
F
F(S)
F(S).G(S)
1
πRL1 COUT
⋅⋅
-------------------------------------------- ---
1
πRL2 COUT
⋅⋅
-----------------------------------------------
1
2πESR COUT
⋅⋅ ⋅
--------------------------------------------------- --------
1
2πRCOMP CCOMP
⋅⋅ ⋅
-------------------------------------------------- --------------------------
FBW2
FBW1
1
1
1
Special recommendations VIPer53 - E
30/36
12 Special recommendations
As steted in the error amplifier section, a capacitor of 10nF capacitor (minimum value: 8nF)
should always be connected to the COMP pin to ensure correct stability of the internal error
amplifier Figure 18, 19 and 22.
In order to improve the ruggedness of the device versus eventual drain overvoltages, a
resistance of 1kΩ should be inserted in series with the TOVL pin, as shown on Figure 18,
Figure 19 on page 17.
Note that, this resistance does not impact the overload delay, as its value is negligible prior
to the internal pull-up resistance (about 125kΩ).
13 Software implementation
All the above considerations and some others are included included in ST design software
which provides all of the needed components around the VIPer device for specified output
configurations, and is available on www.st.com.
VIPer53 - E Package mechanical data
31/36
14 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Package mechanical data VIPer53 - E
32/36
Figure 25. Package dimensions
Table 11. DIP8 mechanical data
Dimensions
Ref.
Databook (mm)
Nom. Min Max
A5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.26
E1 6.10 6.35 7.11
e2.54
eA 7.62
eB 10.92
L 2.92 3.30 3.81
Package Weight Gr. 470
VIPer53 - E Package mechanical data
33/36
Figure 26. Package dimensions
Table 12. PowerSO-10 mechanical data
Dimensions
Ref.
Databook (mm)
Nom. Min Max
A 3.35 3.65
A1 0.00 0.10
B 0.40 0.60
c 0.35 0.55
D 9.40 9.60
D1 7.40 7.60
E 9.30 9.50
E1 7.20 7.40
E2 7.20 7.60
E3 6.10 6.35
E4 5.90 6.10
e 1.27
F 1.25 1.35
H 13.80 14.40
h 0.50
L 1.20 1.80
q 1.70
α 0° 8°
Order codes VIPer53 - E
34/36
15 Order codes
Table 13. Order codes
Part Number Package Shipment
VIPer53DIP-E DIP-8 Tube
VIPer53SP-E PowerSO-10 Tube
VIPer53SPTR - E PowerSO-10 Tape and reel
VIPer53 - E Revision history
35/36
16 Revision history
Table 14. Revision history
Date Revision Changes
13-Nov-2006 1Initial release.
VIPer53 - E
36/36
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