S-8223A/B/C/D Series
www.ablicinc.com
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK
(SECONDARY PROTECTION)
© ABLIC Inc., 2017-2018 Rev.1.3_00
1
The S-8223A/B/C/D Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates
high-accuracy voltage detection circuits and delay circuits.
Short-circuits between cells accommodate series connection of two cells or three cells.
The S-8223B/D Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be
used.
Features
• High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n = 1 to 3)
3.600 V to 4.700 V (50 mV step) Accuracy ±20 mV (Ta = +25°C)
Accuracy ±25 mV (Ta = −10°C to +60°C)
Overcharge hysteresis voltage n (n = 1 to 3)*1
0.0 mV to −550 mV (50 mV step)
−300 mV to −550 mV Accuracy ±20%
−100 mV to −250 mV Accuracy ±50 mV
−50 mV Accuracy ±25 mV
0.0 mV Accuracy −25 mV to +20 mV
• Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary)
Overcharge detection delay time is selectable: 1 s, 2 s, 4 s, 6 s, 8 s
Overcharge release delay time is selectable: 2 ms, 64 ms
• Built-in timer reset delay circuit
• Output form is selectable (S-8223A/C Series): CMOS output, Nch open-drain output
• Output logic is selectable (S-8223A/C Series): Active "H", active "L"
• CO pin output voltage is limited to 11.5 V max. (S-8223B/D Series)*2
• High-withstand voltage: Absolute maximum rating 28 V
• Wide operation voltage range: 3.6 V to 28 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption
During operation (VCU − 1.0 V for each cell): 0.25 μA typ., 0.5 μA max. (Ta = +25°C)
During overdischarge (VCU × 0.5 V for each cell): 0.3 μA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free
*1. Select the overcharge hysteresis voltage calculated as the following formula.
(Overcharge detection voltage n) + (Overcharge hysteresis voltage n) ≥ 3.4 V
*2. Only output logic active "H" is available.
Application
• Lithium-ion rechargeable battery packs (for secondary protection)
Package
• SNT-6A
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BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
2
Block Diagrams
1. S-8223A/C Series
1. 1 CMOS output product
VC1
VC3
VC2
VSS
VDD
Control logic
Delay circuit
Oscillator
−
+
−
+
−
+
CO
Overcharge detection
comparator 1
Overcharge detection
comparator 2
Overcharge detection
comparator 3
Figure 1
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
3
1. 2 Nch open-drain output product
VC3
VC2
VC1
VSS
VDD
Control logic
Delay circuit
Oscillator
−
+
−
+
−
+
CO
Overcharge detection
comparator 1
Overcharge detection
comparator 2
Overcharge detection
comparator 3
Figure 2
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
4
2. S-8223B/D Series
VC3
VC2
VC1
VSS
VDD
Control logic
Delay circuit
Oscillator
−
+
−
+
−
+
CO
CO pin output voltage
limit circuit
Overcharge detection
comparator 1
Overcharge detection
comparator 2
Overcharge detection
comparator 3
Figure 3
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
5
Product Name Structure
1. Product name
S-8223 x xx - I6T1 U
Package abbreviation and IC packing specifications*1
I6T1: SNT-6A, Tape
Serial code*2
Sequentially set from AA to AZ
Environmental code
U: Lead-free (Sn 100%), halogen-free
Product type
A: Pin configuration 1, CMOS output, Nch open-drain output
B: Pin configuration 1, CO pin output voltage 11.5 V max.
C: Pin configuration 2, CMOS output, Nch open-drain output
D: Pin configuration 2, CO pin output voltage 11.5 V max.
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name Dimension Tape Reel Land
SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD
3. Product name list
3. 1 S-8223A Series
Table 2
Product Name
Overcharge
Detection
Voltage
[VCU]
Overcharge
Hysteresis
Voltage
[VHC]
Overcharge
Detection
Delay Time
*1
[tCU]
Overcharge
Release
Delay Time
*2
[tCL]
Output Form
*3
Output Logic
*4
S-8223AAA-I6T1U 4.450 V −400 mV 6 s 64 ms CMOS output Active "H"
S-8223AAB-I6T1U 4.500 V −400 mV 6 s 64 ms CMOS output Active "H"
S-8223AAC-I6T1U 4.350 V −400 mV 6 s 64 ms CMOS output Active "H"
S-8223AAD-I6T1U 4.400 V −400 mV 6 s 64 ms CMOS output Active "H"
S-8223AAE-I6T1U 4.550 V −400 mV 6 s 64 ms CMOS output Active "H"
S-8223AAF-I6T1U 4.500 V −400 mV 6 s 2 ms CMOS output Active "H"
S-8223AAG-I6T1U 4.550 V −400 mV 6 s 2 ms CMOS output Active "H"
S-8223AAH-I6T1U 4.350 V −400 mV 4 s 64 ms CMOS output Active "H"
S-8223AAI-I6T1U 4.500 V −400 mV 4 s 64 ms CMOS output Active "H"
S-8223AAJ-I6T1U 4.550 V −400 mV 4 s 64 ms CMOS output Active "H"
*1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable.
*2. Overcharge release delay time 2 ms / 64 ms is selectable.
*3. Output form CMOS output / Nch open-drain output is selectable.
*4. Output logic active "H" / active "L" is selectable.
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
6
3. 2 S-8223B Series
Table 3
Product Name
Overcharge
Detection
Voltage
[VCU]
Overcharge
Hysteresis
Voltage
[VHC]
Overcharge
Detection
Delay Time
*1
[tCU]
Overcharge Release
Delay Time
*2
[tCL]
Output Logic
*3
S-8223BAA-I6T1U 4.500 V −300 mV 4 s 2 ms Active "H"
*1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable.
*2. Overcharge release delay time 2 ms / 64 ms is selectable.
*3. Only output logic active "H" is available.
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
3. 3 S-8223C Series
Table 4
Product Name
Overcharge
Detection
Voltage
[VCU]
Overcharge
Hysteresis
Voltage
[VHC]
Overcharge
Detection
Delay Time
*1
[tCU]
Overcharge
Release
Delay Time
*2
[tCL]
Output Form
*3
Output Logic
*4
S-8223CAA-I6T1U 4.400 V −400 mV 4 s 2 ms CMOS output Active "H"
S-8223CAB-I6T1U 4.450 V −400 mV 4 s 2 ms CMOS output Active "H"
S-8223CAC-I6T1U 4.500 V −400 mV 4 s 2 ms CMOS output Active "H"
S-8223CAD-I6T1U 4.350 V −400 mV 4 s 2 ms CMOS output Active "H"
S-8223CAE-I6T1U 4.250 V −50 mV 2 s 2 ms Nch open-drain output Active "H"
S-8223CAF-I6T1U 4.150 V −50 mV 2 s 2 ms Nch open-drain output Active "H"
S-8223CAG-I6T1U 4.350 V −400 mV 2 s 2 ms CMOS output Active "H"
S-8223CAH-I6T1U 4.450 V −400 mV 2 s 2 ms CMOS output Active "H"
S-8223CAI-I6T1U 4.500 V −400 mV 2 s 2 ms CMOS output Active "H"
S-8223CAJ-I6T1U 4.300 V −400 mV 4 s 2 ms CMOS output Active "H"
S-8223CAK-I6T1U 4.200 V −400 mV 2 s 2 ms Nch open-drain output Active "H"
*1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable.
*2. Overcharge release delay time 2 ms / 64 ms is selectable.
*3. Output form CMOS output / Nch open-drain output is selectable.
*4. Output logic active "H" / active "L" is selectable.
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
7
Pin Configuration
1. SNT-6A
5
4
6
2
3
1
Top view
Figure 4
Table 5 S-8223A/B Series (Pin Configuration 1)
Pin No. Symbol Description
1 VC1 Positive voltage connection pin of battery 1
2 VC2 Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
3 VSS Negative power supply input pin
Negative voltage connection pin of battery 3
4 VC3 Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
5 VDD Positive power supply input pin
6 CO FET gate connection pin for charge control
Table 6 S-8223C/D Series (Pin Configuration 2)
Pin No. Symbol Description
1 CO FET gate connection pin for charge control
2 VDD Positive power supply input pin
3 VC1 Positive voltage connection pin of battery 1
4 VC2 Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
5 VC3 Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
6 VSS Negative power supply input pin
Negative voltage connection pin of battery 3
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
8
Absolute Maximum Ratings
Table 7
(Ta = +25°C unless otherwise specified)
Item Symbol Applied Pin Absolute Maximum Rating Unit
Input voltage between VDD pin and VSS pin VDS VDD VSS − 0.3 to VSS + 28 V
Input pin voltage VIN VC1 VSS − 0.3 to VSS + 28 V
VC2, VC3 VDD − 28 to VDD + 0.3 V
CO pin output
voltage
S-8223A/C Series CMOS output
VCO CO
VSS − 0.3 to VDD + 0.3 V
Nch open-drain output VSS − 0.3 to VSS + 28 V
S-8223B/D Series VSS − 0.3 to VDD + 0.3 V
Operation ambient temperature Topr − −40 to +85 °C
Storage temperature Tstg − −40 to +125 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage.
These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 8
Item Symbol Condition Min. Typ. Max. Unit
Junction-to-ambient thermal resistance*1 θJA SNT-6A
Board A − 224 − °C/W
Board B − 176 − °C/W
Board C − − − °C/W
Board D − − − °C/W
Board E − − − °C/W
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Power Dissipation" and "Test Board" for details.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
9
Electrical Characteristics
Table 9
(Ta = +25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test
Circuit
Detection Voltage
Overcharge detection voltage n
(n = 1, 2, 3) VCUn
Ta = +25°C VCU
− 0.020 VCU VCU
+ 0.020 V 1
Ta = −10°C
to
+60°C*1 VCU
− 0.025 VCU VCU
+ 0.025 V 1
Overcharge hysteresis voltage n
(n = 1, 2, 3) VHCn
−550 mV
≤
VHC
≤
−300 mV VHC
×
1.2 VHC V
HC
×
0.8 V 1
−250 mV
≤
VHC
≤
−100 mV VHC
− 0.050 VHC VHC
+ 0.050 V 1
VHC = −50 mV VHC
− 0.025 VHC VHC
+ 0.025 V 1
VHC = 0.0 mV VHC
− 0.025 VHC VHC
+ 0.020 V 1
Input Voltage
Operation voltage between
VDD pin and VSS pin VDSOP − 3.6 − 28 V −
Output Voltage
CO pin output voltage "H" VCOH S-8223B/D Series 5.0 8.0 11.5 V 1
Input Current
Current consumption
during operation IOPE V1 = V2 = V3 = VCU − 1.0 V − 0.25 0.5 μA2
Current consumption
during overdischarge IOPED V1 = V2 = V3 = VCU × 0.5 V − − 0.3 μA2
VC1 pin input current IVC1 V1 = V2 = V3 = VCU − 1.0 V − − 0.3 μA3
VCn pin input current (n = 2, 3) IVCn V1 = V2 = V3 = VCU − 1.0 V −0.3 0 0.3 μA3
Output Current
CO pin source current ICOH
S-8223A/C Series
(CMOS output product),
S-8223B/D Series
− − −20 μA4
CO pin sink current ICOL − 20 − − μA4
CO pin leakage current ICOLL S-8223A/C Series
(Nch open-drain output product) − − 0.1 μA4
Delay Time
Overcharge detection delay time tCU − t
CU × 0.8 tCU t
CU × 1.2 s 1
Overcharge release delay time tCL tCL = 2 ms 1.6 2.0 3.0 ms 1
tCL = 64 ms 51.2 64 76.8 ms 1
Overcharge timer reset delay time tTR − 6 12 20 ms 1
Transition time to test mode tTST − − − 10 ms 1
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
10
Test Circuits
1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in
Nch open-drain output product of the S-8223A/C Series.
1. 1 Overcharge detection voltage n (VCUn)
Set V0 = 0 V, V1 = V2 = V3 = VCU − 0.05 V in test circuit 1. The overcharge detection voltage 1 (VCU1) is the V1
voltage when the CO pin output inverts after the V1 voltage has been gradually increased.
Overcharge detection voltage (VCUn) (n = 2 to 3) can be determined in the same way as when n = 1.
1. 2 Overcharge hysteresis voltage n (VHCn)
Set V0 = 0 V, V1 = VCU + 0.05 V, V2 = V3 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference
between V1 voltage and VCU1 when the CO pin output inverts again after the V1 voltage has been gradually
decreased.
Overcharge hysteresis voltage (VHCn) (n = 2 to 3) can be determined in the same way as when n = 1.
2. Output voltage (S-8223B/D Series) (Test circuit 1)
Set SW1 to OFF in the S-8223B/D Series.
2. 1 CO pin output voltage "H"
The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when V0 = 0 V, V1 = V2
= V3 = 5.2 V.
3. Output current (Test circuit 4)
3. 1 CMOS output product in S-8223A/C Series
Set SW4 and SW5 to OFF.
3. 1. 1 Active "H"
(1) CO pin source current (ICOH)
Set SW4 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V4 = 0.5 V. I1 is the CO pin source
current (ICOH) at that time.
(2) CO pin sink current (ICOL)
Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that
time.
3. 1. 2 Active "L"
(1) CO pin source current (ICOH)
Set SW4 to ON after setting V1 = V2 = V3 = 3.5 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at
that time.
(2) CO pin sink current (ICOL)
Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V4 = 0.5 V. I2 is the CO pin sink current
(ICOL) at that time.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
11
3. 2 Nch open-drain output product in S-8223A/C Series
Set SW4 and SW5 to OFF.
3. 2. 1 Active "H"
(1) CO pin leakage current (ICOLL)
Set SW5 to ON after setting V1 = 9.4 V, V2 = V3 = 9.3 V, V5 = 28 V. I2 is the CO pin leakage current
(ICOLL) at that time.
(2) CO pin sink current (ICOL)
Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V5 = 0 V. I2 is the CO pin sink current
(ICOL) at that time.
3. 2. 2 Active "L"
(1) CO pin leakage current (ICOLL)
Set SW5 to ON after setting V1= V2 = V3 = 3.5 V, V5 = 28 V. I2 is the CO pin leakage current (ICOLL)
at that time.
(2) CO pin sink current (ICOL)
Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V5 = 0 V. I2 is the CO pin sink current
(ICOL) at that time.
3. 3 S-8223B/D Series
Set SW4 and SW5 to OFF.
3. 3. 1 CO pin source current (ICOH)
Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = VCOH − 0.5 V. I2 is the CO pin source current
(ICOH) at that time.
3. 3. 2 CO pin sink current (ICOL)
Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that
time.
4. Overcharge detection delay time (tCU), overcharge release delay time (tCL) (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in
Nch open-drain output product of the S-8223A/C Series.
Increase V1 up to 5.2 V after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. The overcharge detection delay time (tCU) is the time
period until the CO pin output inverts. After that, decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is
the time period until the CO pin output inverts.
5. Overcharge timer reset delay time (tTR) (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in
Nch open-drain output product of the S-8223A/C Series.
Increase V1 up to 5.2 V (first rise), and decrease V1 down to 3.5 V within the overcharge detection delay time (tCU) after
setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. After that, increase V1 up to 5.2 V again (second rise), and detect the time period
until the CO pin output inverts.
When the period from when V1 has fallen to the second rise is short, CO pin output inverts after tCU has elapsed since
the first rise. If the period is gradually made longer, CO pin output inverts after tCU has elapsed since the second rise.
The overcharge timer reset delay time (tTR) is the period from V1 fall until the second rise at that time.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
12
6. Transition time to test mode (tTST) (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in
Nch open-drain output product of the S-8223A/C Series.
Increase V0 up to 4.0 V, and decrease V0 again to 0 V after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V.
When the period from when V0 was raised to when it has fallen is short, if an overcharge detection operation is
performed subsequently, the overcharge detection delay time is tCU. However, when the period from when V0 is raised to
when it has fallen is gradually made longer, the delay time during the subsequent overcharge detection operation is
shorter than tCU. The transition time to test mode (tTST) is the period from when V0 was raised to when it has fallen at that
time.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
13
V1
V2
V3
S-8223A/B/C/D Series
VDD
VC1
VC2
CO
VSS
VC3
V
V0
100 kΩ
SW1
V1
V2
V3
VDD
VC1
VC2
CO
VSS
VC3
S-8223A/B/C/D Series
A
I
OPE
I
OPED
Figure 5 Test Circuit 1 Figure 6 Test Circuit 2
V1
V2
VDD
VC1
VC2
CO
VSS
VC3
S-8223A/B/C/D Series
A
A
I
VC2
I
VC1
A
I
VC3
V3
V4
V1
V2
SW5
SW4
VDD
VC1
VC2
CO
VSS
VC3
V5
V
AI1
AI2
S-8223A/B/C/D Series
V3
Figure 7 Test Circuit 3 Figure 8 Test Circuit 4
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
14
Operation
Remark Refer to " Battery Protection IC Connection Examples".
1. Normal status
If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCU) + the overcharge hysteresis
voltage (VHC)", the CO pin output changes to "L" (active "H") or "H" (active "L"). This is called normal status.
2. Overcharge status
When the voltage of one of the batteries exceeds VCU during charging under normal conditions and the status is
retained for the overcharge detection delay time (tCU) or longer, CO pin output inverts. This status is called overcharge
status. Connecting a FET to the CO pin provides charge control and a second protection.
If the voltage of each of the batteries is lower than VCU + VHC and the status is retained for the overcharge release delay
time (tCL) or longer, S-8223A/B/C/D Series changes to normal status.
3. Overcharge timer reset function
When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during
tCU from when VCU is exceeded to when charging is stopped, tCU is continuously counted if the time the overcharge
release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time
the overcharge release noise persists is tTR or longer, counting of tCU is reset once. After that, when VCU has been
exceeded, counting tCU resumes.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
15
4. Test mode
In the S-8223A/B/C/D Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 4.0 V or more higher than the VC1 pin voltage for at least
10 ms (V1 = V2 = V3 = 3.5 V, Ta = +25 °C). The status is retained by the internal latch and the test mode is retained
even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin.
If the CO pin becomes detection status when the delay time has elapsed after overcharge detection, the latch for
retaining the test mode is reset and the S-8223A/B/C/D Series exits from the test mode.
VCUn
Pin voltage
CO pin
(Active "H")
Test mode
VDD pin voltage
4.0 V or
higher
Battery voltage
VHCn
tTST = 10 ms max.
VC1 pin voltage
(n = 1 to 3)
32 ms typ.
CO pin
(Active "L")
tCL
Caution 1. Set the test mode when no batteries are overcharged.
2. The overcharge timer reset delay time (tTR) is not shortened in the test mode.
Figure 9
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
16
Timing Charts
1. Overcharge detection operation
VCUn
Battery voltage
VHCn
(n = 1 to 3)
CO pin
(Active "H")
tCU
CO pin
(Active "L")
tCL
tTR or longer tTR or shorter
tCU or shorter
Figure 10
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
17
2. Overcharge timer reset operation
VCUn
Battery voltage
CO pin
(Active "H")
tCU
VHCn
tCU or
shorter tTR
tTR or shorter
Timer reset
tTR or shorter
tTR or longer
(n = 1 to 3)
CO pin
(Active "L")
Figure 11
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
18
Battery Protection IC Connection Examples
1. 3-serial cell
SCP
EB−
C1
C2
C3
EB+
R1
R2
R3
BAT1
BAT2
BAT3
FET*1
VC1
VC2
VC3
VSS
CO
VDD
CVDD
RVDD
DP
S-8223A/B/C/D
Series
*1. The S-8223B/D Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage
of 12 V can be used.
Fi
g
ure 12
Table 10 Constants for External Components
No. Part Min. Typ. Max. Unit
1 R1 to R3 0.1 1 10 kΩ
2 C1 to C3, CVDD 0.01 0.1 1 μF
3 RVDD 100 330 1000 Ω
Caution 1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1 to R3, and to C1 to C3 and CVDD.
4. Since the CO pin may become detection status transiently when the battery is being connected,
be sure to connect the positive terminal of BAT1 last in order to prevent the protection fuse from
cutoff.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
19
2. 2-serial cell
SCP
EB−
C1
C2
EB+
R1
R2
BAT1
BAT2
VC1
VC2
VC3
VSS
CO
VDD
CVDD
RVDD
FET
DP
S-8223A/B/C/D
Series
Figure 13
Table 11 Constants for External Components
No. Part Min. Typ. Max. Unit
1 R1, R2 0.1 1 10
kΩ
2 C1, C2, CVDD 0.01 0.1 1 μF
3 RVDD 100 330 1000 Ω
Caution 1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1, R2, and to C1, C2 and CVDD.
4. Since the CO pin may become detection status transiently when the battery is being connected,
be sure to connect the positive terminal of BAT1 last in order to prevent the protection fuse from
cutoff.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
20
[For SCP, contact]
Global Sales & Marketing Division, Dexerials Corporation
Gate City Osaki East Tower 8F, 1-11-2
Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan
TEL +81-3-5435-3946
Contact Us: http://www.dexerials.jp/en/
Precaution
• Do not connect batteries charged with VCU + VHC or higher.
• If the connected batteries include a battery charged with VCU + VHC or higher, the S-8223A/B/C/D Series may become
overcharge status after all pins are connected.
• In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of the CO pin detection pulses when the batteries are connected. Perform
thorough evaluation with the actual application circuit.
• Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figures in " Battery
Protection IC Connection Examples".
• The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
• Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
21
Characteristics (Typical Data)
1. Detection voltage
1. 1 VCU vs. Ta
VCU = 4.500 V
1. 2 VCU + VHC vs. Ta
VHC = −400 mV
V
CU
[V]
4.520
4.510
4.500
4.490
4.480
−40 −25 25 50 75 85
Ta [°C]
0
V
CU
+V
HC
[V]
−40 −25 25 50 75 85
Ta [°C]
0
4.200
4.150
4.100
4.050
4.000
2. Current consumption
2. 1 IOPE vs. Ta
VDD = 10.5 V
2. 2 IOPED vs. Ta
VDD = 6.75 V
I
OPE
[μA]
0.4
0.3
0.2
0.1
0.0
−40 −25 25 50 75 85
Ta [°C]
0
0.5
IOPED [μA]
0.3
0.2
0.1
0.0
−40 −25 25 50 75 85
Ta [°C]
0
2. 3 IOPE vs. VDD
Ta = +25°C
0
20
40
60
80
V
DD
[V]
I
OPE
[μA]
0105152025 30
3. Delay time
3. 1 tCU vs. Ta
VDD = 12.2 V
t
CU
[s]
8.0
6.0
4.0
2.0
Ta [°C]
0.0
−40 −25 25 50 75 850
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
22
4. Output current
4. 1 ICOH vs. VDD (S-8223A/C Series)
Ta = +25°C
4. 2 ICOH vs. VDD (S-8223B/D Series)
Ta = +25°C
200
180
160
140
80
V
DD
[V]
I
COH
[A]
0105152025
120
100
30
50
40
10
VDD [V]
ICOH [A]
0105152025
30
20
30
4. 3 ICOL vs. VDD
Ta = +25°C
4. 4 ICOLL vs. VDD
Ta = +25°C
0
20
60
100
V
DD
[V]
I
COL
[A]
0105152025
40
80
30
0.00
0.02
0.06
0.10
V
DD
[V]
I
COLL
[A]
0105152025
0.04
0.08
30
5. Output voltage
5. 1 VCOH vs. VDD
0
2
6
12
V
DD
[V]
V
COH
[V]
0105152025
4
8
10
30
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00 S-8223A/B/C/D Series
23
Marking Specifications
1. SNT-6A
Top view
132
645
(1) (2) (3)
(4) (5) (6)
(1) to (3): Product code (refer to Product name vs. Product code)
(4) to (6): Lot number
Product name vs. Product code
1. 1 S-8223A Series
Product name Product code
(1) (2) (3)
S-8223AAA-I6T1U 5 Q A
S-8223AAB-I6T1U 5 Q D
S-8223AAC-I6T1U 5 Q E
S-8223AAD-I6T1U 5 Q F
S-8223AAE-I6T1U 5 Q G
S-8223AAF-I6T1U 5 Q H
S-8223AAG-I6T1U 5 Q I
S-8223AAH-I6T1U 5 Q J
S-8223AAI-I6T1U 5 Q K
S-8223AAJ-I6T1U 5 Q L
1. 2 S-8223B Series
Product name Product code
(1) (2) (3)
S-8223BAA-I6T1U 5 Q W
1. 3 S-8223C Series
Product name Product code
(1) (2) (3)
S-8223CAA-I6T1U 5 Q M
S-8223CAB-I6T1U 5 Q N
S-8223CAC-I6T1U 5 Q O
S-8223CAD-I6T1U 5 Q P
S-8223CAE-I6T1U 5 Q Q
S-8223CAF-I6T1U 5 Q R
S-8223CAG-I6T1U 5 Q S
S-8223CAH-I6T1U 5 Q T
S-8223CAI-I6T1U 5 Q U
S-8223CAJ-I6T1U 5 Q V
S-8223CAK-I6T1U 5 Q X
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8223A/B/C/D Series Rev.1.3_00
24
Power Dissipation
0 25 50 75 100 125 150 175
0.0
0.2
0.4
0.6
0.8
1.0
Ambient temperature (Ta) [°C]
Power dissipation (P
D
) [W]
T
j
= +125°C max.
SNT-6
A
B
A
Board Power Dissipation (PD)
A 0.45 W
B 0.57 W
C −
D −
E −
(1)
1
2
3
4
(2)
1
2
3
4
Board B
Item Specification
Thermal via -
Material FR-4
Number of copper foil layer 4
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Size [mm] 114.3 x 76.2 x t1.6
2
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
-
-
74.2 x 74.2 x t0.070
Thermal via -
Material FR-4
Board A
Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Number of copper foil layer
ICMountArea
SNT-6A Test Board
No. SNT6A-A-Board-SD-1.0
ABLIC Inc.
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A-PKG Dimensions
PG006-A-P-SD-2.1
No. PG006-A-P-SD-2.1
0.2±0.05
0.48±0.02
0.08 +0.05
-0.02
0.5
1.57±0.03
123
45
6
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5
1.85±0.05 0.65±0.05
0.25±0.05
mm
PG006-A-C-SD-2.0
SNT-6A-A-Carrier Tape
No. PG006-A-C-SD-2.0
+0.1
-0
1
2
4
3
56
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY.
No. PG006-A-R-SD-1.0
PG006-A-R-SD-1.0
Enlarged drawing in the central part
SNT-6A-A-Reel
5,000
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A
-Land Recommendation
PG006-A-L-SD-4.1
No. PG006-A-L-SD-4.1
0.3
0.2
0.52
1.36
0.52
1
2
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.30 mm ~ 1.40 mm)
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
1.
2. (1.30 mm ~ 1.40 mm)
(0.25 mm min. / 0.30 mm typ.)
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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