S-8223A/B/C/D Series www.ablic.com www.ablicinc.com BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 (c) ABLIC Inc., 2017-2018 The S-8223A/B/C/D Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates high-accuracy voltage detection circuits and delay circuits. Short-circuits between cells accommodate series connection of two cells or three cells. The S-8223B/D Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be used. Features * High-accuracy voltage detection circuit for each cell Overcharge detection voltage n (n = 1 to 3) 3.600 V to 4.700 V (50 mV step) * * * * * * * * * * Accuracy 20 mV (Ta = +25C) Accuracy 25 mV (Ta = -10C to +60C) Overcharge hysteresis voltage n (n = 1 to 3)*1 0.0 mV to -550 mV (50 mV step) -300 mV to -550 mV Accuracy 20% -100 mV to -250 mV Accuracy 50 mV -50 mV Accuracy 25 mV 0.0 mV Accuracy -25 mV to +20 mV Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary) Overcharge detection delay time is selectable: 1 s, 2 s, 4 s, 6 s, 8 s Overcharge release delay time is selectable: 2 ms, 64 ms Built-in timer reset delay circuit Output form is selectable (S-8223A/C Series): CMOS output, Nch open-drain output Output logic is selectable (S-8223A/C Series): Active "H", active "L" CO pin output voltage is limited to 11.5 V max. (S-8223B/D Series)*2 High-withstand voltage: Absolute maximum rating 28 V Wide operation voltage range: 3.6 V to 28 V Wide operation temperature range: Ta = -40C to +85C Low current consumption During operation (VCU - 1.0 V for each cell): 0.25 A typ., 0.5 A max. (Ta = +25C) During overdischarge (VCU x 0.5 V for each cell): 0.3 A max. (Ta = +25C) Lead-free (Sn 100%), halogen-free *1. Select the overcharge hysteresis voltage calculated as the following formula. (Overcharge detection voltage n) + (Overcharge hysteresis voltage n) 3.4 V *2. Only output logic active "H" is available. Application * Lithium-ion rechargeable battery packs (for secondary protection) Package * SNT-6A 1 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Block Diagrams 1. S-8223A/C Series 1. 1 CMOS output product VDD VC1 Overcharge detection comparator 1 + - VC2 VC3 Overcharge detection comparator 2 Delay circuit - Oscillator Overcharge detection comparator 3 + - VSS Figure 1 2 Control logic + CO BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 1. 2 Nch open-drain output product VDD VC1 Overcharge detection comparator 1 + - VC2 Overcharge detection comparator 2 Delay circuit + Oscillator - VC3 Control logic CO Overcharge detection comparator 3 + - VSS Figure 2 3 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 2. S-8223B/D Series VDD VC1 Overcharge detection comparator 1 + - VC2 Overcharge detection comparator 2 Oscillator - Overcharge detection comparator 3 + - VSS Figure 3 4 Control logic Delay circuit + VC3 CO pin output voltage limit circuit CO BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Product Name Structure 1. Product name S-8223 x xx - I6T1 U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 I6T1: SNT-6A, Tape Serial code*2 Sequentially set from AA to AZ Product type A: Pin configuration 1, CMOS output, Nch open-drain output B: Pin configuration 1, CO pin output voltage 11.5 V max. C: Pin configuration 2, CMOS output, Nch open-drain output D: Pin configuration 2, CO pin output voltage 11.5 V max. *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Codes Package Name SNT-6A Dimension PG006-A-P-SD Tape PG006-A-C-SD Reel PG006-A-R-SD Land PG006-A-L-SD 3. Product name list 3. 1 S-8223A Series Table 2 Overcharge Overcharge Overcharge Overcharge Hysteresis Detection Release Detection Product Name *1 *2 Voltage Delay Time Delay Time Voltage [VHC] [VCU] [tCU] [tCL] S-8223AAA-I6T1U 4.450 V -400 mV 6s 64 ms S-8223AAB-I6T1U 4.500 V -400 mV 6s 64 ms S-8223AAC-I6T1U 4.350 V -400 mV 6s 64 ms S-8223AAD-I6T1U 4.400 V -400 mV 6s 64 ms S-8223AAE-I6T1U 4.550 V -400 mV 6s 64 ms S-8223AAF-I6T1U 4.500 V -400 mV 6s 2 ms S-8223AAG-I6T1U 4.550 V -400 mV 6s 2 ms S-8223AAH-I6T1U 4.350 V -400 mV 4s 64 ms S-8223AAI-I6T1U 4.500 V -400 mV 4s 64 ms S-8223AAJ-I6T1U 4.550 V -400 mV 4s 64 ms *1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. *2. Overcharge release delay time 2 ms / 64 ms is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. *4. Output logic active "H" / active "L" is selectable. *3 Output Form CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output Output Logic *4 Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Remark Please contact our sales office for the products with detection voltage value other than those specified above. 5 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 3. 2 S-8223B Series Table 3 Overcharge Overcharge Overcharge Hysteresis Detection Detection Product Name *1 Voltage Delay Time Voltage [VHC] [VCU] [tCU] S-8223BAA-I6T1U 4.500 V -300 mV 4s *1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. *2. Overcharge release delay time 2 ms / 64 ms is selectable. *3. Only output logic active "H" is available. Overcharge Release *2 Delay Time [tCL] 2 ms Output Logic *3 Active "H" Remark Please contact our sales office for the products with detection voltage value other than those specified above. 3. 3 S-8223C Series Table 4 Product Name S-8223CAA-I6T1U S-8223CAB-I6T1U S-8223CAC-I6T1U S-8223CAD-I6T1U S-8223CAE-I6T1U S-8223CAF-I6T1U S-8223CAG-I6T1U S-8223CAH-I6T1U S-8223CAI-I6T1U S-8223CAJ-I6T1U S-8223CAK-I6T1U *1. *2. *3. *4. Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] -400 mV -400 mV -400 mV -400 mV -50 mV -50 mV -400 mV -400 mV -400 mV -400 mV -400 mV Overcharge Detection *1 Delay Time [tCU] 4s 4s 4s 4s 2s 2s 2s 2s 2s 4s 2s Overcharge Release *2 Delay Time [tCL] 4.400 V 4.450 V 4.500 V 4.350 V 4.250 V 4.150 V 4.350 V 4.450 V 4.500 V 4.300 V 4.200 V Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. Overcharge release delay time 2 ms / 64 ms is selectable. Output form CMOS output / Nch open-drain output is selectable. Output logic active "H" / active "L" is selectable. 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms *3 Output Form CMOS output CMOS output CMOS output CMOS output Nch open-drain output Nch open-drain output CMOS output CMOS output CMOS output CMOS output Nch open-drain output Output Logic Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Remark Please contact our sales office for the products with detection voltage value other than those specified above. 6 *4 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Pin Configuration 1. SNT-6A Top view 1 2 3 Table 5 S-8223A/B Series (Pin Configuration 1) 6 5 4 Figure 4 Pin No. 1 Symbol VC1 2 VC2 3 VSS 4 VC3 5 6 VDD CO Description Positive voltage connection pin of battery 1 Negative voltage connection pin of battery 1 Positive voltage connection pin of battery 2 Negative power supply input pin Negative voltage connection pin of battery 3 Negative voltage connection pin of battery 2 Positive voltage connection pin of battery 3 Positive power supply input pin FET gate connection pin for charge control Table 6 S-8223C/D Series (Pin Configuration 2) Pin No. 1 2 3 Symbol CO VDD VC1 4 VC2 5 VC3 6 VSS Description FET gate connection pin for charge control Positive power supply input pin Positive voltage connection pin of battery 1 Negative voltage connection pin of battery 1 Positive voltage connection pin of battery 2 Negative voltage connection pin of battery 2 Positive voltage connection pin of battery 3 Negative power supply input pin Negative voltage connection pin of battery 3 7 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Absolute Maximum Ratings Table 7 (Ta = +25C unless otherwise specified) Item Input voltage between VDD pin and VSS pin Symbol Applied Pin VDS VDD VC1 VIN VC2, VC3 Input pin voltage CO pin output voltage S-8223A/C Series CMOS output Nch open-drain output S-8223B/D Series Operation ambient temperature Storage temperature VCO CO Topr Tstg - - Absolute Maximum Rating VSS - 0.3 to VSS + 28 VSS - 0.3 to VSS + 28 VDD - 28 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VSS + 28 VSS - 0.3 to VDD + 0.3 -40 to +85 -40 to +125 Unit V V V V V V C C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Thermal Resistance Value Table 8 Item Condition Board A Board B Junction-to-ambient thermal resistance*1 JA SNT-6A Board C Board D Board E *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark 8 Symbol Refer to " Power Dissipation" and "Test Board" for details. Min. - - - - - Typ. 224 176 - - - Max. - - - - - Unit C/W C/W C/W C/W C/W BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Electrical Characteristics Table 9 Item Symbol Condition (Ta = +25C unless otherwise specified) Test Min. Typ. Max. Unit Circuit Detection Voltage Overcharge detection voltage n (n = 1, 2, 3) Ta = +25C VCUn Ta = -10C to +60C*1 -550 mV VHC -300 mV -250 mV VHC -100 mV Overcharge hysteresis voltage n (n = 1, 2, 3) VHCn VHC = -50 mV VHC = 0.0 mV Input Voltage Operation voltage between VDD pin and VSS pin Output Voltage CO pin output voltage "H" Input Current Current consumption during operation Current consumption during overdischarge VC1 pin input current VCn pin input current (n = 2, 3) Output Current VCU VCU VHC VHC VHC VHC VCU + 0.020 VCU + 0.025 VHC x 0.8 VHC + 0.050 VHC + 0.025 VHC + 0.020 V 1 V 1 V 1 V 1 V 1 V 1 3.6 - 28 V - 5.0 8.0 11.5 V 1 VCOH S-8223B/D Series IOPE V1 = V2 = V3 = VCU - 1.0 V - 0.25 0.5 A 2 IOPED V1 = V2 = V3 = VCU x 0.5 V - - 0.3 A 2 IVC1 IVCn V1 = V2 = V3 = VCU - 1.0 V V1 = V2 = V3 = VCU - 1.0 V - -0.3 - 0 0.3 0.3 A A 3 3 - - -20 A 4 20 - - A 4 - - 0.1 A 4 tCU x 0.8 1.6 51.2 6 - tCU 2.0 64 12 - tCU x 1.2 3.0 76.8 20 10 s ms ms ms ms 1 1 1 1 1 CO pin source current ICOH CO pin sink current ICOL CO pin leakage current ICOLL Delay Time Overcharge detection delay time tCU Overcharge release delay time - VDSOP VCU - 0.020 VCU - 0.025 VHC x 1.2 VHC - 0.050 VHC - 0.025 VHC - 0.025 tCL S-8223A/C Series (CMOS output product), S-8223B/D Series - S-8223A/C Series (Nch open-drain output product) - tCL = 2 ms tCL = 64 ms Overcharge timer reset delay time tTR - Transition time to test mode tTST - *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. 9 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Test Circuits 1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in Nch open-drain output product of the S-8223A/C Series. 1. 1 Overcharge detection voltage n (VCUn) Set V0 = 0 V, V1 = V2 = V3 = VCU - 0.05 V in test circuit 1. The overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO pin output inverts after the V1 voltage has been gradually increased. Overcharge detection voltage (VCUn) (n = 2 to 3) can be determined in the same way as when n = 1. 1. 2 Overcharge hysteresis voltage n (VHCn) Set V0 = 0 V, V1 = VCU + 0.05 V, V2 = V3 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference between V1 voltage and VCU1 when the CO pin output inverts again after the V1 voltage has been gradually decreased. Overcharge hysteresis voltage (VHCn) (n = 2 to 3) can be determined in the same way as when n = 1. 2. Output voltage (S-8223B/D Series) (Test circuit 1) Set SW1 to OFF in the S-8223B/D Series. 2. 1 CO pin output voltage "H" The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when V0 = 0 V, V1 = V2 = V3 = 5.2 V. 3. Output current (Test circuit 4) 3. 1 CMOS output product in S-8223A/C Series Set SW4 and SW5 to OFF. 3. 1. 1 Active "H" (1) CO pin source current (ICOH) Set SW4 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 3. 1. 2 Active "L" (1) CO pin source current (ICOH) Set SW4 to ON after setting V1 = V2 = V3 = 3.5 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V4 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 10 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 3. 2 Nch open-drain output product in S-8223A/C Series Set SW4 and SW5 to OFF. 3. 2. 1 Active "H" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1 = 9.4 V, V2 = V3 = 9.3 V, V5 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V5 = 0 V. I2 is the CO pin sink current (ICOL) at that time. 3. 2. 2 Active "L" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1= V2 = V3 = 3.5 V, V5 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V5 = 0 V. I2 is the CO pin sink current (ICOL) at that time. 3. 3 S-8223B/D Series Set SW4 and SW5 to OFF. 3. 3. 1 CO pin source current (ICOH) Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = VCOH - 0.5 V. I2 is the CO pin source current (ICOH) at that time. 3. 3. 2 CO pin sink current (ICOL) Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 4. Overcharge detection delay time (tCU), overcharge release delay time (tCL) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in Nch open-drain output product of the S-8223A/C Series. Increase V1 up to 5.2 V after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. The overcharge detection delay time (tCU) is the time period until the CO pin output inverts. After that, decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is the time period until the CO pin output inverts. 5. Overcharge timer reset delay time (tTR) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in Nch open-drain output product of the S-8223A/C Series. Increase V1 up to 5.2 V (first rise), and decrease V1 down to 3.5 V within the overcharge detection delay time (tCU) after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. After that, increase V1 up to 5.2 V again (second rise), and detect the time period until the CO pin output inverts. When the period from when V1 has fallen to the second rise is short, CO pin output inverts after tCU has elapsed since the first rise. If the period is gradually made longer, CO pin output inverts after tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR) is the period from V1 fall until the second rise at that time. 11 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 6. Transition time to test mode (tTST) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in Nch open-drain output product of the S-8223A/C Series. Increase V0 up to 4.0 V, and decrease V0 again to 0 V after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. When the period from when V0 was raised to when it has fallen is short, if an overcharge detection operation is performed subsequently, the overcharge detection delay time is tCU. However, when the period from when V0 is raised to when it has fallen is gradually made longer, the delay time during the subsequent overcharge detection operation is shorter than tCU. The transition time to test mode (tTST) is the period from when V0 was raised to when it has fallen at that time. 12 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 100 k SW1 S-8223A/B/C/D Series VDD V0 IOPE IOPED CO V VC1 VSS VC2 V2 VDD CO VC1 VSS VC2 VC3 A V3 V1 S-8223A/B/C/D Series V1 V3 VC3 V2 Figure 5 Test Circuit 1 Figure 6 Test Circuit 2 V4 A I1 S-8223A/B/C/D Series IVC1 A V1 VDD CO VDD CO VC1 VSS VC1 VSS VC2 VC3 VC2 VC3 IVC2 A SW4 S-8223A/B/C/D Series IVC3 A V2 V3 V1 SW5 V3 V2 A I2 V V5 Figure 7 Test Circuit 3 Figure 8 Test Circuit 4 13 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Operation Remark Refer to " Battery Protection IC Connection Examples". 1. Normal status If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCU) + the overcharge hysteresis voltage (VHC)", the CO pin output changes to "L" (active "H") or "H" (active "L"). This is called normal status. 2. Overcharge status When the voltage of one of the batteries exceeds VCU during charging under normal conditions and the status is retained for the overcharge detection delay time (tCU) or longer, CO pin output inverts. This status is called overcharge status. Connecting a FET to the CO pin provides charge control and a second protection. If the voltage of each of the batteries is lower than VCU + VHC and the status is retained for the overcharge release delay time (tCL) or longer, S-8223A/B/C/D Series changes to normal status. 3. Overcharge timer reset function When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during tCU from when VCU is exceeded to when charging is stopped, tCU is continuously counted if the time the overcharge release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists is tTR or longer, counting of tCU is reset once. After that, when VCU has been exceeded, counting tCU resumes. 14 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 4. Test mode In the S-8223A/B/C/D Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 4.0 V or more higher than the VC1 pin voltage for at least 10 ms (V1 = V2 = V3 = 3.5 V, Ta = +25 C). The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin. If the CO pin becomes detection status when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the S-8223A/B/C/D Series exits from the test mode. VDD pin voltage VC1 pin voltage 4.0 V or higher Pin voltage VCUn VHCn Battery voltage (n = 1 to 3) Test mode tTST = 10 ms max. CO pin (Active "H") CO pin (Active "L") 32 ms typ. Caution tCL 1. Set the test mode when no batteries are overcharged. 2. The overcharge timer reset delay time (tTR) is not shortened in the test mode. Figure 9 15 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Timing Charts 1. Overcharge detection operation VHCn VCUn Battery voltage (n = 1 to 3) tTR or longer tTR or shorter tCU or shorter CO pin (Active "H") CO pin (Active "L") tCU Figure 10 16 tCL BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 2. Overcharge timer reset operation VHCn tTR or shorter tTR or shorter tTR or longer VCUn Battery voltage (n = 1 to 3) tCU or shorter tTR CO pin (Active "H") Timer reset tCU CO pin (Active "L") Figure 11 17 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Battery Protection IC Connection Examples 1. 3-serial cell SCP EB+ VDD RVDD CVDD VC1 R1 BAT1 C1 VC2 R2 BAT2 BAT3 R3 C2 S-8223A/B/C/D Series VC3 CO C3 FET *1 DP VSS EB- *1. The S-8223B/D Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be used. Figure 12 Table 10 Constants for External Components No. Part Min. Typ. Max. Unit 0.1 1 R1 to R3 1 10 k 0.01 2 C1 to C3, CVDD 0.1 1 F 100 3 RVDD 330 1000 Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3, and to C1 to C3 and CVDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, be sure to connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff. 18 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 2. 2-serial cell SCP EB+ VDD RVDD CVDD VC1 BAT1 R1 C1 VC2 BAT2 R2 C2 S-8223A/B/C/D Series FET VC3 CO DP VSS EB- Figure 13 Table 11 Constants for External Components No. Part Min. Typ. Max. Unit 0.1 1 10 1 R1, R2 k 0.01 0.1 1 2 C1, C2, CVDD F 100 330 1000 3 RVDD Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1, R2, and to C1, C2 and CVDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, be sure to connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff. 19 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series [For SCP, contact] Global Sales & Marketing Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/ Precaution * Do not connect batteries charged with VCU + VHC or higher. * If the connected batteries include a battery charged with VCU + VHC or higher, the S-8223A/B/C/D Series may become overcharge status after all pins are connected. * In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be restricted to prevent transient output of the CO pin detection pulses when the batteries are connected. Perform thorough evaluation with the actual application circuit. * Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figures in " Battery Protection IC Connection Examples". * The application conditions for the input voltage, output voltage, and load current should not exceed the power dissipation. * Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit. * ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC. 20 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Characteristics (Typical Data) 1. Detection voltage 1. 2 VCU + VHC vs. Ta 1. 1 VCU vs. Ta VCU = 4.500 V 4.520 VCU + VHC [V] VCU [V] 4.510 4.500 4.490 4.480 -40 -25 0 25 Ta [C] 50 VHC = -400 mV 4.200 4.150 4.100 4.050 4.000 -40 -25 75 85 0 25 Ta [C] 50 75 85 2. Current consumption 2. 1 IOPE vs. Ta 2. 2 IOPED vs. Ta VDD = 10.5 V 0.5 VDD = 6.75 V 0.3 IOPED [A] IOPE [A] 0.4 0.3 0.2 0.2 0.1 0.1 0.0 -40 -25 0 25 Ta [C] 75 85 50 0.0 -40 -25 0 25 Ta [C] 50 75 85 2. 3 IOPE vs. VDD Ta = +25C 80 IOPE [A] 60 40 20 0 0 5 10 15 20 VDD [V] 25 30 3. Delay time 3. 1 tCU vs. Ta VDD = 12.2 V 8.0 tCU [s] 6.0 4.0 2.0 0.0 -40 -25 0 25 Ta [C] 50 75 85 21 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series 4. Output current 4. 1 ICOH vs. VDD (S-8223A/C Series) 4. 2 ICOH vs. VDD (S-8223B/D Series) Ta = +25C Ta = +25C 80 10 20 120 ICOH [A] ICOH [A] 100 140 160 180 200 0 5 10 15 20 VDD [V] 25 40 50 30 4. 3 ICOL vs. VDD 30 0 5 10 15 20 VDD [V] 80 0.08 ICOLL [A] ICOL [A] 0.10 60 40 0.06 0.04 0.02 0 5 10 15 20 VDD [V] 25 30 5. Output voltage 5. 1 VCOH vs. VDD 12 10 VCOH [V] Ta = +25C 100 20 8 6 4 2 0 0 22 30 4. 4 ICOLL vs. VDD Ta = +25C 0 25 5 10 15 20 VDD [V] 25 30 0.00 0 5 10 15 20 VDD [V] 25 30 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Marking Specifications 1. SNT-6A Top view 6 5 (1) to (3): (4) to (6): 4 Product code (refer to Product name vs. Product code) Lot number (1) (2) (3) (4) (5) (6) 1 2 3 Product name vs. Product code 1. 1 S-8223A Series Product name S-8223AAA-I6T1U S-8223AAB-I6T1U S-8223AAC-I6T1U S-8223AAD-I6T1U S-8223AAE-I6T1U S-8223AAF-I6T1U S-8223AAG-I6T1U S-8223AAH-I6T1U S-8223AAI-I6T1U S-8223AAJ-I6T1U 1. 3 S-8223C Series (1) 5 5 5 5 5 5 5 5 5 5 Product code (2) Q Q Q Q Q Q Q Q Q Q (3) A D E F G H I J K L Product name S-8223CAA-I6T1U S-8223CAB-I6T1U S-8223CAC-I6T1U S-8223CAD-I6T1U S-8223CAE-I6T1U S-8223CAF-I6T1U S-8223CAG-I6T1U S-8223CAH-I6T1U S-8223CAI-I6T1U S-8223CAJ-I6T1U S-8223CAK-I6T1U Product code (1) (2) (3) 5 5 5 5 5 5 5 5 5 5 5 Q Q Q Q Q Q Q Q Q Q Q M N O P Q R S T U V X 1. 2 S-8223B Series Product name S-8223BAA-I6T1U Product code (1) (2) (3) 5 Q W 23 BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8223A/B/C/D Series Power Dissipation SNT-6A Tj = +125C max. Power dissipation (PD) [W] 1.0 0.8 B 0.6 A 0.4 0.2 0.0 0 25 50 75 100 125 150 Ambient temperature (Ta) [C] Board A B C D E 24 Power Dissipation (PD) 0.45 W 0.57 W - - - 175 SNT-6A Test Board (1) Board A ICMountArea Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] 1 2 3 4 Thermal via Specification 114.3 x 76.2 x t1.6 FR-4 2 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 - (2) Board B Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] Thermal via 1 2 3 4 Specification 114.3 x 76.2 x t1.6 FR-4 4 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 - No. SNT6A-A-Board-SD-1.0 ABLIC Inc. 1.570.03 6 1 5 4 2 3 +0.05 0.08 -0.02 0.5 0.480.02 0.20.05 No. PG006-A-P-SD-2.1 TITLE SNT-6A-A-PKG Dimensions No. PG006-A-P-SD-2.1 ANGLE UNIT mm ABLIC Inc. +0.1 o1.5 -0 4.00.1 2.00.05 0.250.05 +0.1 1.850.05 o0.5 -0 4.00.1 0.650.05 3 2 1 4 5 6 Feed direction No. PG006-A-C-SD-2.0 TITLE SNT-6A-A-Carrier Tape No. PG006-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.00.3 Enlarged drawing in the central part o130.2 (60) (60) No. PG006-A-R-SD-1.0 SNT-6A-A-Reel TITLE No. PG006-A-R-SD-1.0 ANGLE QTY. UNIT mm ABLIC Inc. 5,000 0.52 1.36 2 0.52 0.2 0.3 1. 2. 1 (0.25 mm min. / 0.30 mm typ.) (1.30 mm ~ 1.40 mm) 0.03 mm SNT 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.30 mm ~ 1.40 mm) No. PG006-A-L-SD-4.1 TITLE SNT-6A-A -Land Recommendation No. PG006-A-L-SD-4.1 ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com