74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 2 -- 20 June 2014 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard JESD8-B/JESD36 ESD protection: HBM JESD22-A114-D exceeds 2000 V CDM JESD22-C101-C exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C. 3. Applications Serial-to-parallel data conversion Remote control holding register 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC595AD 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LVC595APW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74LVC595ABQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm SOT763-1 5. Functional diagram 6+&3 67&3 46 4 4 4 4 '6 4 4 4 4 05 Fig 1. Logic symbol 74LVC595A Product data sheet '6 6+&3 46 67&3 %,76725$*(5(*,67(5 2( 2( 67$*(6+,)75(*,67(5 05 67$7(2873876 4 4 4 4 4 4 4 4 PQD Fig 2. PQD Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 2 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 67$*( '6 ' 67$*(672 ' 4 67$*( ' 4 )) &3 46 4 )) &3 5 5 6+&3 05 ' 4 ' 4 /$7&+ /$7&+ &3 &3 67&3 2( PQD 4 Fig 3. 4 4 4 4 4 4 4 Logic diagram 6+&3 '6 67&3 05 2( =VWDWH 4 =VWDWH 4 =VWDWH 4 =VWDWH 4 46 PQD Fig 4. Timing diagram 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 3 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6. Pinning information 6.1 Pinning WHUPLQDO LQGH[DUHD 74LVC595A 4 16 VCC 4 '6 2( 67&3 15 Q0 Q3 3 14 DS 4 Q4 4 13 OE 4 Q5 5 12 STCP 4 Q6 6 11 SHCP Q7 7 10 MR GND 8 9 Q7S *1' 6+&3 05 2 46 Q2 4 1 4 *1' Q1 9&& 4 /9&$ DDI 7UDQVSDUHQWWRSYLHZ 001aaf569 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q[0:7] 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input VCC 16 supply voltage 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 4 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 7. Functional description Function table[1] Table 3. Input Output Function SHCP STCP OE MR DS Q7S Qn X X L NC X L L a LOW-state on MR only affects the shift register X L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high impedance OFF-state X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] H = HIGH voltage state; L = LOW voltage state; = LOW-to-HIGH transition; X = don't care; NC = no change; Z = high-impedance OFF-state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 3-state [1] 0.5 6.5 V output HIGH or LOW state [1] 0.5 VCC + 0.5 V - 50 mA VO > VCC or VO < 0 V IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW Tamb = 40 C to +125 C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 5 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions functional VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V 3-state 0 - 5.5 V output HIGH or LOW state 0 - VCC V 40 - +125 C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 1.2 V Product data sheet 40 C to +125 C Max Min Max Unit 1.08 - - 1.08 - V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V 0.12 V VCC = 1.65 V to 1.95 V VCC = 1.2 V - - 0.12 - VCC = 1.65 V to 1.95 V - - 0.35 VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A 0.35 VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL input leakage VCC = 3.6 V; current VI = 5.5 V or GND 74LVC595A Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 6 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions [2] 40 C to +125 C Unit Min Typ[1] Max Min Max - 0.1 10 - 20 A IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 1.65 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] For transceivers, the parameter IOZ includes the input leaking current. 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tpd 40 C to +85 C Conditions Min Max Min Max - 17.5 - - - ns VCC = 1.65 V to 1.95 V 2.0 6.6 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 4.2 8.1 1.5 9.3 ns propagation delay SHCP to Q7S; see Figure 7 VCC = 2.7 V 1.5 4.7 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.5 4.0 6.7 1.5 7.7 ns - 16.8 - - - ns STCP to Qn; see Figure 8 VCC = 1.2 V Product data sheet [2] VCC = 1.65 V to 1.95 V 2.0 5.8 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 3.7 8.1 1.5 9.3 ns VCC = 2.7 V 1.5 4.0 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.2 3.3 6.7 1.2 7.7 ns - 17.3 - - - ns VCC = 1.65 V to 1.95 V 2.0 6.9 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 4.3 8.1 1.5 9.3 ns HIGH to LOW MR to Q7S; see Figure 11 propagation delay VCC = 1.2 V 74LVC595A Unit [2] VCC = 1.2 V tPHL 40 C to +125 C Typ[1] VCC = 2.7 V 1.5 4.5 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.2 3.8 6.7 1.2 7.7 ns All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 7 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter ten enable time 40 C to +85 C Conditions OE to Qn; see Figure 12 Max - 17.9 - - - ns 6.4 14.1 2.0 16.2 ns VCC = 2.3 V to 2.7 V 1.5 4.2 8.0 1.5 9.2 ns VCC = 2.7 V 1.5 4.5 7.6 1.5 8.7 ns 1.2 3.8 6.7 1.2 7.7 ns - 9.6 - - - ns 2.0 4.9 9.8 2.0 11.2 ns OE to Qn; see Figure 12 VCC = 1.65 V to 1.95 V pulse width Min 2.0 VCC = 1.2 V tW Max Unit VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V disable time 40 C to +125 C [3] VCC = 1.2 V tdis Min Typ[1] [4] VCC = 2.3 V to 2.7 V 1.2 2.8 5.8 1.2 6.6 ns VCC = 2.7 V 1.5 3.7 6.2 1.5 7.1 ns VCC = 3.0 V to 3.6 V 1.2 3.5 5.7 1.2 6.5 ns VCC = 1.65 V to 1.95 V 6.0 2.5 - 7.0 - ns VCC = 2.3 V to 2.7 V 5.0 2.0 - 5.5 - ns VCC = 2.7 V 4.5 1.5 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.5 - 4.5 - ns VCC = 1.65 V to 1.95 V 5.0 2.0 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 1.5 - 4.5 - ns VCC = 2.7 V 2.5 1.0 - 3.0 - ns VCC = 3.0 V to 3.6 V 2.5 1.0 - 3.0 - ns 5.0 0.4 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 0.1 - 4.5 - ns VCC = 2.7 V 2.0 0 - 2.5 - ns VCC = 3.0 V to 3.6 V 2.0 0.1 - 2.5 - ns SHCP, STCP HIGH or LOW; see Figure 7 and Figure 8 MR LOW; see Figure 11 tsu set-up time DS to SHCP; see Figure 9 VCC = 1.65 V to 1.95 V MR to STCP; see Figure 10 VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns VCC = 2.7 V 4.0 1.8 - 4.5 - ns VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns VCC = 2.7 V 4.0 1.8 - 4.5 - ns VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns SHCP to STCP; see Figure 8 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 8 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter 40 C to +85 C Conditions Min th hold time recovery time trec maximum frequency fmax output skew time power dissipation capacitance CPD 40 C to +125 C Max Min Max VCC = 1.65 V to 1.95 V 1.5 0.2 - 2.0 - ns VCC = 2.3 V to 2.7 V 1.5 0.1 - 2.0 - ns VCC = 2.7 V 1.5 0.1 - 2.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.2 - 1.5 - ns VCC = 1.65 V to 1.95 V 5.0 2.7 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 1.5 - 4.5 - ns VCC = 2.7 V 2.0 1.0 - 2.5 - ns VCC = 3.0 V to 3.6 V 2.0 1.0 - 2.5 - ns VCC = 1.65 V to 1.95 V 80 130 - 70 - MHz VCC = 2.3 V to 2.7 V 100 140 - 90 - MHz VCC = 2.7 V 110 150 - 100 - MHz 130 180 - 115 - MHz - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 50 - - - pF VCC = 2.3 V to 2.7 V - 45 - - - pF VCC = 3.0 V to 3.6 V - 44 - - - pF MR to SHCP; see Figure 11 SHCP or STCP; see Figure 7 and Figure 8 VCC = 3.0 V to 3.6 V [5] VI = GND to VCC [6] [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [6] Unit DS to SHCP; see Figure 9 VCC = 3.0 V to 3.6 V tsk(o) Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 9 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 12. Waveforms IPD[ 9, 6+&3LQSXW 90 *1' W: W 3+/ W 3/+ 92+ 90 46RXWSXW 92/ PQD Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency 9, 6+&3LQSXW 90 *1' IPD[ W VX 9, 67&3LQSXW 90 *1' W: W 3+/ W 3/+ 92+ 90 4QRXWSXW 92/ PQD Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 10 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9, 90 6+&3LQSXW *1' W VX W VX WK WK 9, 90 '6LQSXW *1' 92+ 90 46RXWSXW 92/ PQD Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The data set-up and hold times for the serial data input (DS) VI MR input VM GND tsu VI STCP input VM GND VOH Qn outputs VM VOL 001aaf571 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The master reset (MR) to storage clock (STCP) set-up times 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 11 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9, 90 05LQSXW *1' W: W UHF 9, 6+&3LQSXW *1' 90 W 3+/ 92+ 90 46RXWSXW 92/ PQD Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time VI VM OE input GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae821 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. 3-state enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY VCC < 2.7 V 0.5 VCC 0.5 VCC VOL 0.15 V VOH 0.15 V VCC 2.7 V 1.5 V 1.5 V VOL 0.3 V VOH 0.3 V 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 12 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state W: 9, QHJDWLYH SXOVH 90 90 9 WI WU WU WI 9, SRVLWLYH SXOVH 90 90 9 W: 9(;7 9&& * 9, 5/ 92 '87 57 5/ &/ DDH Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 1.2 V 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 13 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 13. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H Z 0 ES GHWDLO; PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 14. Package outline SOT109-1 (SO16) 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 14 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( 02 Fig 15. Package outline SOT403-1 (TSSOP16) 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 15 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV 627 WHUPLQDOVERG\[[PP % ' $ $ $ ( F GHWDLO; WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD & H H E \ \ & Y 0 & $ % Z 0 & / (K H 'K ; PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 PP $ PD[ $ E F ' 'K ( (K H / Y Z \ \ H 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627 02 (8523($1 352-(&7,21 ,668('$7( Fig 16. Package outline SOT763-1 (DHVQFN16) 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 16 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC595A v.2 20140620 Product data sheet - 74LVC595A v.1 Modifications: 74LVC595A v.1 74LVC595A Product data sheet * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * Figure note for Figure 6 added. 20070529 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 - (c) Nexperia B.V. 2017. All rights reserved 17 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 16. 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The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes -- Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC595A Product data sheet Suitability for use -- Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the Nexperia product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). Nexperia does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 18 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LVC595A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 20 June 2014 (c) Nexperia B.V. 2017. All rights reserved 19 of 20 74LVC595A Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 (c) General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 20 June 2014