FN7525 Rev 2.00 Page 1 of 16
December 16, 2014
FN7525
Rev 2.00
December 16, 2014
ISL8014A
4A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator
DATASHEET
The ISL8014A is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 4A
continuous output current from a 2.8V to 5.5V input supply. It
uses a current control architecture to deliver very low duty
cycle operation at high frequency with fast transient response
and excellent loop stability.
The ISL8014A integrates a pair of low ON-resistance P-Channel
and N-Channel internal MOSFETs to maximize efficiency and
minimize external component count. The 100% duty-cycle
operation allows less than 400mV dropout voltage at 4A
output current. High 1MHz pulse-width modulation (PWM)
switching frequency allows the for use of small external
components and the SYNC input enables multiple ICs to
synchronize out-of-phase to reduce ripple and eliminate beat
frequencies.
The ISL8014A can be configured for discontinuous or forced
continuous operation at light load. Forced continuous
operation reduces noise and RF interference while
discontinuous mode provides high efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions, an
output overvoltage comparator and over-temperature monitor
circuit. A power-good output voltage monitor indicates when
the output is in regulation.
The ISL8014A is offered in a space saving 4mmx4mm QFN,
lead free package with exposed pad lead frames for low
thermal resistance.
The ISL8014A offers a 1ms power-good (PG) timer at
power-up. When shutdown, ISL8014A discharges the output
capacitor. Other features include internal soft-start, internal
compensation, overcurrent protection, and thermal shutdown.
The ISL8014A is offered in a 16 Ld 4mmx4mm QFN package
with 1mm maximum height. The complete converter occupies
less than 0.4in2 area.
Features
• High efficiency synchronous buck regulator with up to 97%
efficiency
• Power-good (PG) output with a 1ms delay
• 2.8V to 5.5V supply voltage
• 3% output accuracy over-temperature/load/line
•4A output current
• Pin compatible to ISL8013A
• Start-up with prebiased output
• Internal soft-start - 1ms
• Soft-stop output discharge during disabled
• 35µA quiescent supply current in PFM mode
• Selectable forced PWM mode and PFM mode
• External synchronization up to 4MHz
• Less than 1µA logic controlled shutdown current
• 100% maximum duty cycle
• Internal current mode compensation
• Peak current limiting and hiccup mode short-circuit
protection
• Over-temperature protection
• Small 16 Ld 4mmx4mm QFN
• Pb-Free (RoHS compliant)
Applications
• DC/DC POL modules
• µC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
•Portable instruments
• Test and measurement systems
• Li-ion battery powered devices
• Small form factor (SFP) modules
• Barcode readers
ISL8014A
FN7525 Rev 2.00 Page 2 of 16
December 16, 2014
Pin Configuration
ISL8014A
(16 LD QFN)
TOP VIEW
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8014AIRZ 80 14AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL8014AEVAL2Z Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8014A. For more information on MSL please see tech brief TB363.
1
3
4
15
VIN
VIN
VDD
SYNCH
NC
LX
LX
NC
16 14 13
2
12
10
9
11
6578
PGND
PGND
SGND
SGND
EN
NC
PG
VFB
REFER TO APPLICATION NOTE AN1366 FOR MORE LAYOUT SUGGESTIONS.
PAD
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1, 2 VIN Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
3 VDD Input supply voltage for the analog circuitry. Connect to VIN pin.
5 EN Regulator enable pin. Enable the output when driven to high. Shut down the chip and discharge output
capacitor when driven to low. Do not leave this pin floating.
7 PG 1ms timer output. At power-up or EN HI, this output is a 1ms delayed power-good signal for the output
voltage.
4 SYNCH Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the negative
edge trigger. Do not leave this pin floating.
14, 15 LX Switching node connection. Connect to one terminal of the inductor.
11, 12 PGND Power ground
9, 10 SGND Signal ground
8 VFB Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output
voltage. For 0.8V output voltage, connect this pin to the output.
6, 13, 16 NC No connect
- Exposed Pad The exposed pad must be connected to the SGND pin for proper electrical performance. Place as much
vias as possible under the pad connecting to SGND plane for optimal thermal performance.
ISL8014A
FN7525 Rev 2.00 Page 3 of 16
December 16, 2014
Typical Application
Block Diagram
L
1.5µH
LX
PGND
VFB
VIN
EN
PG
SYNCH
INPUT 2.8V TO 5.5V
OUTPUT
1.8V
C1
2 x 22µF
ISL8014A
C2
R2
124k
R3
100k
2 x 22µF
VDD
SGND
C3
47pF
R1
100k
LX
++
CSA
+
+
OCP 1.4V
0.5V
SKIP
+
+
+
Slope
COMP
SLOPE
Soft
START
SOFT
0.8V
EAMP COMP PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
VFB
+
0.736V
PG
SYNCH
SHUTDOWN
VIN
PGND
OSCILLATOR
ZERO-CROSS
SENSING
BANDGAP
SCP
+
0.2V
EN
SHUTDOWN
1ms
DELAY
27pF
390k
SGND
3pF
6k
-
-
-
-
-
-
-
-
ISL8014A
FN7525 Rev 2.00 Page 4 of 16
December 16, 2014
Absolute Maximum Ratings (Reference to GND) Thermal Information
VIN, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
EN, SYNCH, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
LX . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.8V
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Thermal Resistance (Typical, Notes 4, 5)JA (°C/W) JC (°C/W)
16 Ld 4x4 QFN Package . . . . . . . . . . . . . 39 3
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions and
the typical specification are measured at the following conditions unless otherwise noted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are
at TA= +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNITS
INPUT SUPPLY
VDD Undervoltage Lockout Threshold VUVLO Rising, no load -2.6 2.8 V
Falling, no load 2.15 2.35 -V
Quiescent Supply Current IVIN SYNCH = GND, no load at the output -35 -µA
SYNCH = GND, no load at the output and no switches
switching
-30 45 µA
SYNCH = VDD, fSW = 1MHz, no load at the output -6.5 10 mA
Shut Down Supply Current ISD VIN = 5.5V, EN = low -0.1 2µA
OUTPUT REGULATION
Reference Voltage VREF 0.790 0.8 0.810 V
VFB Bias Current IVFB VFB = 0.75V -0.1 -µA
Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.8V) -0.2 -%/V
Soft-Start Ramp Time Cycle -1-ms
OVERCURRENT PROTECTION
Current Limit Blanking Time tOCON -17 -Clock pulses
Overcurrent and Auto Restart Period tOCOFF -4-SS cycle
Switch Current Limit ILIMIT (Note 6)4.9 6.0 7.1 A
Peak Skip Limit ISKIP (Note 6)-1.3 -A
COMPENSATION
Error Amplifier Transconductance -20 -µA/V
Trans-Resistance RT 0.17 0.20 0.23 Ω
LX
P-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA -50 75 mΩ
VIN = 2.8V, IO = 200mA -70 100 mΩ
ISL8014A
FN7525 Rev 2.00 Page 5 of 16
December 16, 2014
N-Channel MOSFET ON-resistance VIN = 5V, IO = 200mA -50 75 mΩ
VIN = 2.8V, IO = 200mA -70 100 mΩ
LX Maximum Duty Cycle -100 -%
PWM Switching Frequency fSW 0.80 1.0 1.20 MHz
LX Minimum On-time SYNCH = High --140 ns
PG
Output Low Voltage Sinking 1mA --0.3 V
Delay Time (Rising Edge) 0.65 11.35 ms
PG Pin Leakage Current PG = VIN = 3.6V -0.01 0.1 µA
PGOOD Rising Threshold Percentage of regulation voltage 89 92 95 %
PGOOD Falling Threshold Percentage of regulation voltage 85 88 91 %
PGOOD Delay Time (Falling Edge) -15 -µs
EN, SYNCH
Logic Input Low --0.4 V
Logic Input High 1.4 --V
Synch Logic Input Leakage Current ISYNCH Pulled up to 5.5V -0.1 1µA
Enable Logic Input Leakage Current IEN -0.1 1µA
Thermal Shutdown -140 -°C
Thermal Shutdown Hysteresis -25 -°C
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions and
the typical specification are measured at the following conditions unless otherwise noted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are
at TA= +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7)TYP
MAX
(Note 7)UNITS
ISL8014A
FN7525 Rev 2.00 Page 6 of 16
December 16, 2014
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A.
FIGURE 1. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) FIGURE 2. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)
FIGURE 3. EFFICIENCY vs LOAD (
1MHz 5V
IN
PWM)
FIGURE 4. EFFICIENCY vs LOAD (
1MHz 5V
IN
PFM
)
FIGURE 5. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V) FIGURE 6. POWER DISSIPATION WITH NO LOAD vs VIN
(PWM VOUT = 1.8V)
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
EFFICIENCY (%)
2.5VOUT-PWM
1.8VOUT-PWM
1.5VOUT-PWM
1.2VOUT-PWM
40
50
60
70
80
90
100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT LOAD (A)
EFFICIENCY (%)
2.5VOUT-PFM
1.8VOUT-PFM 1.5VOUT-PFM 1.2VOUT-PFM
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
EFFICIENCY (%)
2.5VOUT-PWM 1.8VOUT-PWM 1.5VOUT-PWM
1.2VOUT-PWM
3.3VOUT-PWM
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.00.10.20.30.40.50.60.70.80.91.0
OUTPUT LOAD (A)
EFFICIENCY (%)
2.5VOUT-PFM
1.8VOUT-PFM
1.5VOUT-PFM
1.2VOUT-PFM
3.3VOUT-PFM
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.00.51.01.52.02.53.0
OUTPUT LOAD (A)
POWER DISSIPATION (W)
5VIN-PFM
5VIN-PWM
3.3VIN-PFM
3.3VIN-PWM
0
25
50
75
100
125
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V)
POWER DISSIPATION (mW)
ISL8014A
FN7525 Rev 2.00 Page 7 of 16
December 16, 2014
FIGURE 7. POWER DISSIPATION WITH NO LOAD vs VIN
(PFM VOUT = 1.8V)
FIGURE 8. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A. (Continued)
0
0.05
0.10
0.15
0.20
0.25
POWER DISSIPATION (mW)
2.02.53.03.54.04.55.05.5
VIN (V)
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
0.00.51.01.52.02.53.03.54.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
5VIN-PWM
5VIN-PFM
3.3VIN-PWM
3.3VIN-PFM
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
0.00.51.01.52.02.53.03.54.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
5VIN-PWM
5VIN-PFM
3.3VIN-PWM
3.3VIN-PFM
1.75
1.76
1.77
1.78
1.79
1.80
1.81
1.82
1.83
0.0 0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
5VIN-PWM
5VIN-PFM
3.3VIN-PFM
3.3VIN-PWM
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
5VIN-PWM
5VIN-PFM
3.3VIN-PWM
3.3VIN-PFM
2.44
2.45
2.46
2.47
2.48
2.49
2.50
2.51
2.52
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
5VIN-PWM
5VIN-PFM
4.5VIN-PWM
4.5VIN-PFM
ISL8014A
FN7525 Rev 2.00 Page 8 of 16
December 16, 2014
FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN
(PWM VOUT = 1.8 )
FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN
(PFM VOUT = 1.8V)
FIGURE 15. STEADY STATE OPERATION AT NO LOAD (PWM) FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PFM)
FIGURE 17. STEADY STATE OPERATION WITH FULL LOAD FIGURE 18. MODE TRANSITION CCM TO DCM
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A. (Continued)
1.75
1.76
1.77
1.78
1.79
1.80
1.81
1.82
1.83
OUTPUT VOLTAGE (V)
2.02.53.03.54.04.55.05.5
INPUT VOLTAGE (V)
4A LOAD PWM 0A LOAD PWM
1.75
1.76
1.77
1.78
1.79
1.80
1.81
1.82
1.83
OUTPUT VOLTAGE (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V)
4A LOAD
0A LOAD
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
ISL8014A
FN7525 Rev 2.00 Page 9 of 16
December 16, 2014
FIGURE 19. MODE TRANSITION DCM TO CCM FIGURE 20. LOAD TRANSIENT (PWM)
FIGURE 21. LOAD TRANSIENT (PFM) FIGURE 22. SOFT-START WITH NO LOAD (PWM)
FIGURE 23. SOFT-START AT NO LOAD (PFM) FIGURE 24. SOFT-START WITH PRE-BIASED 1V
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A. (Continued)
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
LX 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
PG 5V/DIV
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
PG 5V/DIV
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
PG 5V/DIV
ISL8014A
FN7525 Rev 2.00 Page 10 of 16
December 16, 2014
FIGURE 25. SOFT-START AT FULL LOAD FIGURE 26. SOFT-DISCHARGE SHUTDOWN
FIGURE 27. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
FIGURE 28. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
FIGURE 30. STEADY STATE OPERATION AT FULL LOAD (PWM)
WITH FREQUENCY = 4MHz
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A. (Continued)
EN 2V/DIV
VOUT 0.5V/DIV
IL 2A/DIV
PG 5V/DIV
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
PG 5V/DIV
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
SYNCH 2V/DIV
IL 1A/DIV
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
SYNCH 2V/DIV
IL 1A/DIV
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
SYNCH 2V/DIV
IL 0.5A/DIV
LX 2V/DIV
VOUT RIPPLE 20mV/DIV
SYNCH 2V/DIV
IL 1A/DIV
ISL8014A
FN7525 Rev 2.00 Page 11 of 16
December 16, 2014
FIGURE 31. OUTPUT SHORT CIRCUIT FIGURE 32. OUTPUT SHORT CIRCUIT RECOVERY
FIGURE 33. OUTPUT CURRENT LIMIT vs TEMPERATURE
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A. (Continued)
LX 2V/DIV
VOUT 0.5V/DIV
IL 2A/DIV
PG 5V/DIV
LX 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
PG 5V/DIV
4.500
4.625
4.750
4.875
5.000
5.125
5.250
5.375
5.500
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
OUTPUT CURRENT (A)
OCP_3.3VIN
OCP_5VIN
ISL8014A
FN7525 Rev 2.00 Page 12 of 16
December 16, 2014
Theory of Operation
The ISL8014A is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates at
1MHz fixed switching frequency under heavy load conditions to
allow smaller external inductors and capacitors to be used for
minimal printed-circuit board (PCB) area. At light load, the regulator
reduces the switching frequency, unless forced to the fixed
frequency, to minimize the switching loss and to maximize the
battery life. The quiescent current when the output is not loaded is
typically only 35µA. The supply current is typically only 0.1µA when
the regulator is shut down.
PWM Control Scheme
Pulling the SYNCH pin HI (>2.5V) forces the converter into PWM
mode, regardless of output current. The ISL8014A employs the
current-mode pulse-width modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. “Block
Diagram” is shown on page 3. The current loop consists of the
oscillator, the PWM comparator, current sensing circuit and the
slope compensation for the current loop stability. The gain for the
current sensing circuit is typically 200mV/A. The control reference
for the current loops comes from the error amplifier's (EAMP)
output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
(237mV/µs) reaches the control reference of the current loop, the
PWM comparator COMP sends a signal to the PWM logic to turn
off the P-MOSFET and turn on the N-Channel MOSFET. The
N-MOSFET stays on until the end of the PWM cycle. Figure 34 on
page 12 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.8V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 27pF and 390kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
SKIP Mode
Pulling the SYNCH pin LO (<0.4V) forces the converter into PFM
mode. The ISL8014A enters a pulse-skipping mode at light load
to minimize the switching loss by reducing the switching
frequency. Figure 35 illustrates the skip-mode operation. A
zero-cross sensing circuit shown in the “Block Diagram” monitors
the N-MOSFET current for zero crossing. When 8 consecutive
cycles of the inductor current crossing zero are detected, the
regulator enters the skip mode. During the eight detecting cycles,
the current in the inductor is allowed to become negative. The
counter is reset to zero when the current in any cycle does not
cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in the “Block Diagram”.
Each pulse cycle is still synchronized by the PWM clock. The P-
MOSFET is turned on at the clock's rising edge and turned off when
the output is higher than 1.5% of the nominal regulation or when its
current reaches the peak skip current limit value, then the inductor
current is discharging to 0A and stays at zero. The internal clock is
disabled. The output voltage reduces gradually due to the load
current discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-MOSFET will be turned on again
at the rising edge of the internal clock as it repeats the previous
operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
FIGURE 34. PWM OPERATION WAVEFORMS
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 35. SKIP MODE OPERATION WAVEFORMS
CLOCK
IL
VOUT
NOMINAL +1.5%
NOMINAL
PFM CURRENT LIMIT
LOAD CURRENTT
0
PWM PFM
8 CYCLES
ISL8014A
FN7525 Rev 2.00 Page 13 of 16
December 16, 2014
Synchronization Control
The frequency of operation can be synchronized up to 4MHz by an
external signal applied to the SYNCH pin. The falling edge on the
SYNCH triggers the rising edge of the LX pulse. Make sure that the
minimum on time of the LX node is greater than 140ns.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA output
with the OCP comparator, as shown in the “Block Diagram”. The
current sensing circuit has a gain of 200mV/A, from the P-MOSFET
current to the CSA output. When the CSA output reaches 1.4V,
which is equivalent to 5.7A for the switch current, the OCP
comparator is tripped to turn off the P-MOSFET immediately. The
overcurrent function protects the switching converter from a shorted
output by monitoring the current flowing through the upper MOSFET.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. Upon detection of the initial overcurrent
condition, the overcurrent fault counter is set to 1. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC fault counter will be incremented. If there are 17 sequential
OC fault detections, the regulator will be shut down under an
overcurrent fault condition. An overcurrent fault condition will
result in the regulator attempting to restart in a hiccup mode
within the delay of four soft-start periods. At the end of the fourth
soft-start wait period, the fault counters are reset and soft-start is
attempted again. If the overcurrent condition goes away during
the delay of four soft-start periods, the output will resume back
into regulation point after hiccup mode expires.
Short-Circuit Protection
The short-circuit protection SCP comparator monitors the VFB pin
voltage for output short-circuit protection. When the VFB is lower
than 0.2V, the SCP comparator forces the PWM oscillator
frequency to drop to 1/3 of the normal operation value. This
comparator is effective during start-up or an output short-circuit
event.
PG
During power-up, the open-drain power-good output holds low for
about 1ms after VOUT reaches the regulation voltage. The PG
output also serves as a 1ms delayed the power-good signal when
the pull-up resistor R1 is installed.
UVLO
When the input voltage is below the undervoltage lockout (UVLO)
threshold, the regulator is disabled. To adjust the voltage level of
power on and UVLO, use a resistive divider across EN. The input
voltage programming resistor R4 will depend on the bottom
resistor R5, as referred to in Figure 36. The value of R5 is typically
between 10kΩ and 100kΩ.
Soft Start-Up
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed so that the output voltage rises
in a controlled fashion. When VFB is less than 0.2V at the
beginning of the soft-start, the switching frequency is reduced to
1/3 of the nominal value so that the output can start up
smoothly at light load condition. During soft-start, the IC operates
in the SKIP mode to support pre-biased output condition.
Enable
The enable (EN) input allows the user to control the turning on or
off the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft-start-up
begins. It is recommended that the EN voltage should be kept
logic low (less than 400mV), until VIN reaches 2.5V. Refer to
Figure 37 for suggested circuit implementation with VIN slew
rate.
Let T equal the rise time of VIN. Select the ratio of R5 and R4
such that the voltage is 1.4V (minimum enable logic high
threshold) when VIN is equal to or greater than 2.5V. Set R5
between 10kΩ to 100kΩ, and use Equation 1 to determine R4:
Where VIN is greater than or equal to 2.5V.
Then select C such that the equivalent time constant is at least
2x the rise time, T. This will delay the EN voltage enough so that
the overall EN voltage is less than 400mV by the time VIN
reaches 2.5V. Use Equation 2 to get C:
Where T is the rise time of VIN
R4
R5
1V
EN
+
-
VIN
FIGURE 36. EXTERNAL RESISTOR DIVIDER
C
FIGURE 37. CIRCUIT IMPLEMENTATION WITH VIN SLEW RATE
VIN
EN
<400mV
2.5V
V (VOLTS)
Tt (TIME)
R4
R5VIN 1.4V–
1.4V
---------------------------------------------
=(EQ. 1)
C2T
R4R5
--------------------
(EQ. 2)
ISL8014A
FN7525 Rev 2.00 Page 14 of 16
December 16, 2014
As an example, let VIN = 5V with rise time, T = 10ms. Then
R4=56.2kΩ, R5 = 71.5kΩ, and C = 0.68µF are used to insure
that VIN was >2.5V and the EN voltage was <400mV.
Discharge Mode (Soft-stop)
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-MOSFET is typically 50mΩ and the
ON-resistance for the N-MOSFET is typically 50mΩ.
100% Duty Cycle
The ISL8014A features 100% duty cycle operation to maximize
the battery life. When the battery voltage drops to a level that the
ISL8014A can no longer maintain the regulation at the output,
the regulator completely turns on the P-MOSFET. The maximum
dropout voltage under the 100% duty-cycle operation is the
product of the load current and the ON-resistance of the
P-MOSFET.
Thermal Shut-Down
The ISL8014A has built-in thermal protection. When the internal
temperature reaches +140°C, the regulator is completely shut
down. As the temperature drops to +115°C, the ISL8014A
resumes operation by stepping through the soft-start.
Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operations, ISL8014A
typically uses a 1.5µH output inductor. The higher or lower
inductor value can be used to optimize the total converter system
performance. For example, for higher output voltage 3.3V
application, in order to decrease the inductor current ripple and
output voltage ripple, the output inductor value can be increased.
It is recommended to set the ripple inductor current
approximately 30% of the maximum output current for optimized
performance. The inductor ripple current can be expressed as
shown in Equation 3:
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8014A protects the typical
peak current 6A. The saturation current needs be over 7A for
maximum output current application.
ISL8014A uses internal compensation network and the output
capacitor value is dependent on the output voltage. The ceramic
capacitor is recommended to be X5R or X7R. The recommended
X5R or X7R minimum output capacitor values are shown in
Table 1.
Table 1 shows the minimum output capacitor value is given for
the different output voltage to make sure that the whole
converter system is stable. Additional output capacitance should
be added for better performances in applications where high
load transient or low output ripple is required. It is recommended
to check the system level performance along with the simulation
model.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to the “Typical
Application” on page 3.
The output voltage programming resistor, R3, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩas shown in Equation 4.
If the output voltage desired is 0.8V, then R3 is left unpopulated
and R2 is shorted. There is a leakage current from VIN to LX. It is
recommended to preload the output with 10µA minimum. For
better performance, add 47pF in parallel with R2 (100kΩ
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. Two 22µF X5R or X7R ceramic capacitors are a good
starting point for the input capacitor selection.
I
VO1
VO
VIN
---------
–
Lf
S
-------------------------------------
=
(EQ. 3)
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT
VOUT
(V)
COUT
(µF)
L
(µH)
0.8 2 x 22 1.0~2.2
1.2 2 x 22 1.0~2.2
1.5 2 x 22 1.5~3.3
1.8 2 x 22 1.5~3.3
2.5 2 x 22 1.5~3.3
3.3 2 x 22 2.2~4.7
3.6 2 x 22 2.2~4.7
R3
R20.8V
VOUT 0.8V–
----------------------------------=(EQ. 4)
FN7525 Rev 2.00 Page 15 of 16
December 16, 2014
ISL8014A
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
December 16, 2014 FN8091.2 Added ISL8014AEVAL2Z to the Ordering Information table on page 2.
Updated Tape & Reel note in “Ordering Information” on page 2 from "Add “-T” suffix for tape and reel." to new
standard "Add “-T*” suffix for tape and reel." The "*" covers all possible tape and reel options
Replaced Figure 4 on page 6, Figure 5 on page 6 and Figure 10 on page 7 with the new data curves.
Added more content to section “Enable” on page 13.
Added more content to section “UVLO” on page 13.
Replaced the “Products” section with the About Intersil section.
December 3, 2009 FN8091.1 In the “Features” section on page 1, changed “Pin Compatible to ISL8013” to “Pin Compatible to ISL8013A”
November 25, 2009 FN8091.0 Initial Release.
ISL8014A
FN7525 Rev 2.00 Page 16 of 16
December 16, 2014
Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
INDEX AREA
(4X) 0.15
PIN 1
6
4.00
4.00
A
B
+0.15
-0.10
16X 0 . 60
2 . 10 ± 0 . 15
0.28 +0.07 / -0.05
PIN #1 INDEX AREA
5
8
4
0.10 CM
12
9
4
0.65
12X
13
4X 1.95
16
1
6
A B
( 3 . 6 TYP )
( 2 . 10 ) ( 12X 0 . 65 )
( 16X 0 . 28 )
( 16 X 0 . 8 )
SEE DETAIL "X"
BASE PLANE
1.00 MAX
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
C5
0.08 C
C
SEATING PLANE
0.10 C
