MC74HC4060ADTR2G - ON Semiconductor

May, 2011 − Rev. 6

1Publication Order Number:

MC74HC4060A/D

MC74HC4060A

14-Stage Binary Ripple

Counter With Oscillator

High−Performance Silicon−Gate CMOS

The MC74HC4060A is identical in pinout to the standard CMOS

MC14060B. The device inputs are compatible with standard CMOS

outputs; with pullup resistors, they are compatible with LSTTL

outputs.

This device consists of 14 master−slave flip−flops and an oscillator

with a frequency that is controlled either by a crystal or by an RC

circuit connected externally. The output of each flip−flop feeds the

next and the frequency at each output is half of that of the preceding

one. The state of the counter advances on the negative−going edge of

the Osc In. The active−high Reset is asynchronous and disables the

oscillator to allow very low power consumption during stand−by

operation.

State changes of the Q outputs do not occur simultaneously because

of internal ripple delays. Therefore, decoded output signals are subject

to decoding spikes and may have to be gated with Osc Out 2 of the

HC4060A.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With JEDEC Standard No. 7A Requirements

•Chip Complexity: 390 FETs or 97.5 Equivalent Gates

•These Devices are Pb−Free, Halogen Free and are RoHS Compliant

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See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

16 PDIP−16

N SUFFIX

CASE 648

MC74HC4060AN

AWLYYWWG

HC4060AG

AWLYWW

HC40

60A

ALYWG

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

74HC4060A

ALYWG

SOEIAJ−16

F SUFFIX

CASE 966

(Note: Microdot may be in either location)

MC74HC4060A

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1516 14 13 12 11 10

21 34567

VCC

Q10 Q8 Q9 Reset Osc In

Osc

Out 1

Osc

Out 2

Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND

Pinout: 16−Lead Plastic Package (Top View)

FUNCTION TABLE

Clock Reset Output State

No Change

Advance to Next State

All Outputs Are Low

LOGIC DIAGRAM

Q10

Q12

Q13

Q14

Osc In 11

Reset 12 Pin 16 = VCC

Pin 8 = GND

Osc Out 1 Osc Out 2

910

ORDERING INFORMATION

Device Package Shipping†

MC74HC4060ANG PDIP−16

(Pb−Free)

500 Units / Box

MC74HC4060ADG SOIC−16

(Pb−Free)

48 Units / Rail

MC74HC4060ADR2G SOIC−16

(Pb−Free)

2500 Units / Reel

MC74HC4060ADTG TSSOP−16* 96 Units / Rail

MC74HC4060ADTR2G TSSOP−16* 2500 Units / Reel

MC74HC4060AFELG SOEIAJ−16

(Pb−Free)

2000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74HC4060A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

750

500

450

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature Range

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎÎÎ

260

ÎÎÎ

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.5*

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise/Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at

2.0 V by driving Pin 11 with an external clock source.

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Parameter Condition

VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

VOH Minimum High−Level Output Voltage

(Q4−Q10, Q12−Q14)

Vin = VIH or VIL

|Iout| ≤ 20mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC4060A

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DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Unit

Guaranteed Limit

VCC

ConditionParameter

Symbol Unit

≤125°C≤85°C−55 to 25°C

VCC

ConditionParameter

VOL Maximum Low−Level Output Voltage

(Q4−Q10, Q12−Q14)

Vin = VIH or VIL

|Iout| ≤ 20mA

2.0

4.5

6.0

0.1

Vin = VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

VOH Minimum High−Level Output Voltage

(Osc Out 1, Osc Out 2)

Vin = VCC or GND

|Iout| ≤ 20mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VCC or GND |Iout| ≤ 0.7mA

|Iout| ≤ 1.0mA

|Iout| ≤ 1.3mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low−Level Output Voltage

(Osc Out 1, Osc Out 2)

Vin = VCC or GND

|Iout| ≤ 20mA

2.0

4.5

6.0

0.1

Vin =VCC or GND |Iout| ≤ 0.7mA

|Iout| ≤ 1.0mA

|Iout| ≤ 1.3mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0mA

6.0 4 40 160 mA

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol Parameter

VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

fmax Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

3.0

4.5

6.0

9.0

8.0

MHz

tPLH,

tPHL

Maximum Propagation Delay, Osc In to Q4*

(Figures 1 and 4)

2.0

3.0

4.5

6.0

300

180

375

200

450

250

tPLH,

tPHL

Maximum Propagation Delay, Osc In to Q14*

(Figures 1 and 4)

2.0

3.0

4.5

6.0

500

350

250

200

750

450

275

220

1000

600

300

250

tPHL Maximum Propagation Delay, Reset to Any Q

(Figures 2 and 4)

2.0

3.0

4.5

6.0

195

245

100

300

125

tPLH,

tPHL

Maximum Propagation Delay, Qn to Qn+1

(Figures 3 and 4)

2.0

3.0

4.5

6.0

125

MC74HC4060A

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AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) − continued

Symbol Parameter

VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance 10 10 10 pF

* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [93.7 + 59.3 (n−1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n−1)] ns

VCC = 3.0 V: tP = [61.5+ 34.4 (n−1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n−1)] ns

CPD Power Dissipation Capacitance (Per Package)*

Typical @ 25°C, VCC = 5.0 V

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Symbol Parameter

VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

trec Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

2.0

3.0

4.5

6.0

100

125

100

150

120

twMinimum Pulse Width, Clock

(Figure 1)

2.0

3.0

4.5

6.0

110

twMinimum Pulse Width, Reset

(Figure 2)

2.0

3.0

4.5

6.0

110

tr, tfMaximum Input Rise and Fall Times

(Figure 1)

2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

MC74HC4060A

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PIN DESCRIPTIONS

INPUTS

Osc In (Pin 11)

Negative−edge triggering clock input. A high−to−low

transition on this input advances the state of the counter. Osc

In may be driven by an external clock source.

Reset (Pin 12)

Active−high reset. A high level applied to this input

asynchronously resets the counter to its zero state (forcing

all Q outputs low) and disables the oscillator.

OUTPUTS

Q4—Q10, Q12−Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)

Active−high outputs. Each Qn output divides the Clock

input frequency by 2N. The user should note the Q1, Q2, Q3

and Q11 are not available as outputs.

Osc Out 1, Osc Out 2 (Pins 9, 10)

Oscillator outputs. These pins are used in conjunction

with Osc In and the external components to form an

oscillator. When Osc In is being driven with an external

clock source, Osc Out 1 and Osc Out 2 must be left open

circuited. With the crystal oscillator configuration in Figure

6, Osc Out 2 must be left open circuited.

SWITCHING WAVEFORMS

Osc In

VCC

GND

90%

50%

10%

90%

50%

10%

tPHL

1/fMAX

tPLH

tTLH tTHL

Reset

VCC

GND

tPHL

50%

Figure 1. Figure 2.

VCC

GND

50%

Osc In 50%

trec

50%

VCC

GND

50%

Qn+1

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Figure 4. Test Circuit

tPLH tPHL

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Figure 5. Expanded Logic Diagram

Osc Out 2 9

Q12

Q13

Q14

Q6 = Pin 4

Q7 = Pin 6

Q8 = Pin 14

Q9 = Pin 13

Q10 = Pin 15

VCC = Pin 16

GND = Pin 8

Osc Out 1 10

Osc In 11

Reset 12

Figure 6. Oscillator Circuit Using RC Configuration

Reset 12

Osc In 11 Osc Out 1 10 Osc Out 2 9

Rtc

Ctc

For 2.0V ≤ VCC ≤ 6.0V

10Rtc > RS > 2Rtc

400Hz ≤ f ≤ 400Khz:

f[1

3RtcCtc

(finHz, Rtcinohms, Ctcinfarads)

The formula may vary for other frequencies.

Figure 7. Pierce Crystal Oscillator Circuit

Reset 12

Osc In 11 Osc Out 1 10 9 Osc Out 2

C1 C2

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TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25°C; Input = Pin 11, Output = Pin 10)

Type Positive Reactance (Pierce)

Input Resistance, Rin 60MW Minimum

Output Impedance, Zout (4.5V Supply) 200W (See Text)

Input Capacitance, Cin 5pF Typical

Output Capacitance, Cout 7pF Typical

Series Capacitance, Ca5pF Typical

Open Loop Voltage Gain with Output at Full Swing, α3Vdc Supply

4Vdc Supply

5Vdc Supply

6Vdc Supply

5.0 Expected Minimum

4.0 Expected Minimum

3.3 Expected Minimum

3.1 Expected Minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

Figure 8. Equivalent Crystal Networks

RSLSCS

Re Xe 212121

Value are supplied by crystal manufacturer (parallel resonant crystal).

Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier

Zload

-jXCo

-jXC2 R

-jXC

-jXCs

jXLs

Rload

Xload

NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of

the load. Ca and Rf typically have minimal effect below 2MHz.

Cin Cout

Values are listed in Table 1.

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DESIGN PROCEDURES

The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional

impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from

180°C.

Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.

Ze+

*jXCo(Rs)jXLs*jXCs)

*jXCo)Rs)jXLs*jXCs

+Re)jXe

Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.

The maximum Rs for the crystal should be used in the equation.

Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν is

the gain of the HC4060A amplifier.

Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load

capacitance of 32pF at the required frequency.

Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of

100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLS/Q) − Rs where Ls and Rs are

crystal parameters.

Step 5: Simultaneously solve, using a computer,

b+XC@XC2

R@Re)XC2 (Xe*XC)( Eq 1(with feedback phase shift = 180°)

Xe+XC2 )XC)ReXC2

R+XCload ( Eq 2(where the loading capacitor is an external load, not including Co)

Rload +

RXCoXC2 [(XC)XC2)(XC)XCo)*XC(XC)XCo)XC2)]

X2C2(XC)XCo)2)R2(XC)XCo)XC2)2( Eq 3

Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.

Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that

Q = 2πfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.

CHOOSING R1

Power is dissipated in the effective series resistance of the

crystal. The drive level specified by the crystal manufacturer

is the maximum stress that a crystal can withstand without

damage or excessive shift in frequency. R1 limits the drive

level.

To verify that the maximum dc supply voltage does not

overdrive the crystal, monitor the output frequency as a

function of voltage at Osc Out 2 (Pin 9). The frequency

should increase very slightly as the dc supply voltage is

increased. An overdriven crystal will decrease in frequency

or become unstable with an increase in supply voltage. The

operating supply voltage must be reduced or R1 must be

increased in value if the overdriven condition exists. The

user should note that the oscillator start-up time is

proportional to the value of R1.

SELECTING Rf

The feedback resistor, Rf, typically ranges up to 20MW. Rf

determines the gain and bandwidth of the amplifier. Proper

bandwidth insures oscillation at the correct frequency plus

roll-off to minimize gain at undesirable frequencies, such as

the first overtone. Rf must be large enough so as to not affect

the phase of the feedback network in an appreciable manner.

ACKNOWLEDGEMENTS AND RECOMMENDED

REFERENCES

The following publications were used in preparing this

data sheet and are hereby acknowledged and recommended

for reading:

Technical Note TN-24, Statek Corp.

Technical Note TN-7, Statek Corp.

D. Babin, “Designing Crystal Oscillators”, Machine

Design, March 7, 1985.

D. Babin, “Guidelines for Crystal Oscillator Design”,

Machine Design, April 25, 1985.

ALSO RECOMMENDED FOR READING:

E. Hafner, “The Piezoelectric Crystal Unit-Definitions

and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2,

Feb., 1969.

D. Kemper, L. Rosine, “Quartz Crystals for Frequency

Control”, Electro-Technology, June, 1969.

P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic

Design, May, 1966.

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Clock

Reset

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384

Q10

Q12

Q13

Q14

Figure 11. Timing Diagram

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PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

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PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

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PACKAGE DIMENSIONS

TSSOP−16

CASE 948F−01

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉÉ

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

MC74HC4060A

http://onsemi.com

PACKAGE DIMENSIONS

SOEIAJ−16

CASE 966−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

DETAIL P

VIEW P

0.13 (0.005) 0.10 (0.004)

16 9

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