CMLDM7003E
CMLDM7003JE
ENHANCED SPECIFICATION
SURFACE MOUNT
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CMLDM7003E
and CMLDM7003JE are Enhancement-mode
N-Channel Field Effect Transistors, manufactured
by the N-Channel DMOS Process, designed for high
speed pulsed amplifier and driver applications. The
CMLDM7003E utilizes the USA pinout configuration,
while the CMLDM7003JE utilizes the Japanese pinout
configuration. These special Dual Transistor devices
offer low drain-source on state resistance (rDS(ON))
and ESD protection up to 2kV.
MARKING CODES: CMLDM7003E: C73
CMLDM7003JE: C7J
♦Enhanced specification
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♦
♦
♦
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SOT-563 CASE
MAXIMUM RATINGS: (TA=25°C) SYMBOL UNITS
Drain-Source Voltage VDS 50 V
Drain-Gate Voltage VDG 50 V
Gate-Source Voltage VGS 12 V
Continuous Drain Current ID 280 mA
Maximum Pulsed Drain Current IDM 1.5 A
Power Dissipation (Note 1) PD 350 mW
Power Dissipation (Note 2) PD 300 mW
Power Dissipation (Note 3) PD 150 mW
Operating and Storage Junction Temperature TJ, Tstg -65 to +150 °C
Thermal Resistance ΘJA 357 °C/W
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted)
SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IGSSF, IGSSR V
GS=5.0V 50 nA
IGSSF, IGSSR VGS=10V 0.5 μA
IGSSF, IGSSR V
GS=12V 1.0 μA
IDSS V
DS=50V, VGS=0 50 nA
BVDSS V
GS=0, ID=10μA 50 V
VGS(th) VDS=VGS, ID=250μA 0.49 1.2 V
VSD V
GS=0, IS=115mA 1.4 V
rDS(ON) V
GS=1.8V, ID=50mA 1.6 2.3 Ω
rDS(ON) V
GS=2.5V, ID=50mA 1.3 1.9 Ω
rDS(ON) V
GS=5.0V, ID=50mA 1.1 1.5 Ω
gFS V
DS=10V, ID=200mA 200 mS
Crss VDS=25V, VGS=0, f=1.0MHz 5.0 pF
Ciss V
DS=25V, VGS=0, f=1.0MHz 50 pF
Coss V
DS=25V, VGS=0, f=1.0MHz 25 pF
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2
FEATURES
• ESD protected up to 2kV
R2 (18-January 2010)
www.centralsemi.com
CMLDM7003E
CMLDM7003JE
ENHANCED SPECIFICATION
SURFACE MOUNT
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
SOT-563 CASE - MECHANICAL OUTLINE
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
MARKING CODE: C73
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODE: C7J
PIN CONFIGURATIONS
CMLDM7003E (USA Pinout) CMLDM7003JE (Japanese Pinout)
www.centralsemi.com
R2 (18-January 2010)
