8700F–SEEPR–6/12
Features
Low-voltage operation
VCC = 1.7V to 5.5V
Internally organized as 128 x 8 (1K) or 256 x 8 (2K)
I2C compatible (2-wire) serial interface
Schmitt Trigger, filtered inputs for noise suppression
Bidirectional data transfer protocol
400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) compatibility
Write Protect pin for hardware data protection
8-byte Page Write mode
Partial page writes allowed
Self-timed write cycle (5ms max)
High-reliability
Endurance: 1,000,000 write cycles
Data retention: 100 years
Green package options (Pb/Halide-free/RoHS-compliant)
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 5-lead SOT23,
and 8-ball VFBGA
Die sale options: wafer form and tape and reel available
Description
The Atmel® AT24C01C/02C provides 1024/2048-bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 128/256 words of eight
bits each. Both devices include a cascading feature that allows up to eight devices to
share a common 2-wire bus. These devices are optimized for use in many industrial
and commercial applications where low power and low voltage operation are essential.
The AT24C01C/02C are available in space saving 8-lead PDIP, 8-lead JEDEC SOIC,
8-lead TSSOP, 8-lead UDFN, 5-lead SOT23, and 8-ball VFBGA packages. In addition,
the entire family operates from 1.7V to 5.5V VCC.
Atmel AT24C01C and AT24C02C
I2C-Compatible (2-wire) Serial EEPROM
1-Kbit (128 x 8), 2-Kbit (256 x 8)
DATASHEET
2
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
1. Pin Configurations and Pinouts
Note: 1. For use of 5-lead SOT23, the software A2, A1, and A0 bits in the device address word must be set to zero to
properly communicate.
2. Absolute Maximum Ratings
Pin Name Function
A0 - A2Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
GND Ground
VCC Power Supply
1
2
3
4
8
7
6
5
A
0
A
1
A
2
GND
V
CC
WP
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
A
0
A
1
A
2
GND
V
CC
WP
SCL
SDA
8-lead PDIP
1
2
3
5
4
SCL
GND
SDA
WP
V
CC
5-lead SOT23
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A
0
A
1
A
2
GND
8-lead UDFN
Bottom View
V
CC
WP
SCL
SDA
A
0
A
1
A
2
GND
1
2
3
4
8
7
6
5
8-ball VFBGA
Bottom View
1
2
3
4
8
7
6
5
A
0
A
1
A
2
GND
V
CC
WP
SCL
SDA
8-lead TSSOP
(1)
Operating Temperature ........................–55C to +125C
Storage Temperature ...........................–65C to +150C
Voltage on any pin
with respect to ground .............................–1.0V to +7.0V
Maximum Operating Voltage ................................. 6.25V
DC Output Current................................................ 5.0mA
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification is
not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
3. Block Diagram
4. Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open drain or open collector devices.
Device/Page Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard wired for the
AT24C01C/02C. As many as eight 1-Kbit or 2-Kbit devices may be addressed on a single bus system. See Section 7.
“Device Addressing” on page 9 for more details.
Write Protect (WP): The AT24C01C/02C have a Write Protect pin that provides hardware data protection. The Write
Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is
connected to VCC, the write protection feature is enabled and operates as shown below in Table 4-1.
Table 4-1. Write Protect
Start
Stop
Logic
VCC
GND
WP
SCL
SDA
A2
A1
A0
Serial
Control
Logic
EN H.V. Pump/Timing
EEPROM
Data Recovery
Serial MUX
X DEC
DOUT/ACK
Logic
COMP
LOAD INC
Data Word
Addr/counter
Y DEC
R/W
DOUT
DIN
LOAD
Device
Address
Comparator
WP Pin
Status
Part of the Array Protected
Atmel AT24C01C and AT24C02C
At VCC Full (2K) Array
At GND Normal Read/Write Operations
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
5. Memory Organization
Atmel AT24C01C, 1K Serial EEPROM: Internally organized with 16 pages of eight bytes each, the 1K requires a 7-bit
data word address for random word addressing.
Atmel AT24C02C, 2K Serial EEPROM: Internally organized with 32 pages of eight bytes each, the 2K requires an 8-bit
data word address for random word addressing.
Table 5-1. Pin Capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested.
Table 5-2. DC Characteristics
Note: 1. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 1.7V to 5.5V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.7 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V Read at 400kHz 0.4 1.0 mA
ICC2 Supply Current VCC = 5.0V Write at 400kHz 2.0 3.0 mA
ISB1 Standby Current VCC = 1.7V VIN = VCC or VSS 1.0 μA
ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 2.0 μA
ISB3 Standby Current VCC = 5.5V VIN = VCC or VSS 6.0 μA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 μA
ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 μA
VIL Input Low Level(1) –0.6 VCC x0.3 V
VIH Input High Level(1) VCC x0.7 VCC +0.5 V
VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
Table 5-3. AC Characteristics
Note: 1. This parameter is ensured by characterization only.
2. AC measurement conditions:
RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.7V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5 VCC
Applicable over recommended operating range from TAI = –40C to +85C, VCC = 1.7V to 5.5V, CL = 1TTL Gate and
100pF (unless otherwise noted). Test conditions are listed in Note 2.
Symbol Parameter
1.7V 2.5V,5.0V
UnitsMin Max Min Max
fSCL Clock Frequency, SCL 400 1000 kHz
tLOW Clock Pulse Width Low 1.2 0.4 μs
tHIGH Clock Pulse Width High 0.6 0.4 μs
tINoise Suppression Time 100 50 ns
tAA Clock Low to Data Out Valid 0.1 0.9 0.05 0.55 μs
tBUF
Time the bus must be free before a new
transmission can start. 1.2 0.5 μs
tHD.STA Start Hold Time 0.6 0.25 μs
tSU.STA Start Setup Time 0.6 0.25 μs
tHD.DAT Data In Hold Time 0 0 μs
tSU.DAT Data In Setup Time 100 100 ns
tRInputs Rise Time(1) 0.3 0.3 μs
tFInputs Fall Time(1) 300 100 ns
tSU.STO Stop Setup Time 0.6 .25 μs
tDH Data Out Hold Time 50 50 ns
tWR Write Cycle Time 5 5 ms
Endurance(1) 3.3V, +25C, Page Mode 1,000,000 Write Cycles
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
6. Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see Figure 6-4 on page 8). Data changes during SCL high periods will indicate
a Start or Stop condition as defined below.
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede any
other command (see Figure 6-5 on page 8).
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the Stop
command will place the EEPROM in a standby power mode (see Figure 6-5 on page 8).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Standby Mode: The AT24C01C/02C features a low power standby mode which is enabled:
Upon power-up.
After the receipt of the stop bit and the completion of any internal operations.
2-wire Software Reset: After an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by
following these steps:
1. Create a start bit condition.
2. Clock nine cycles.
3. Create another start bit followed by stop bit condition as shown in Figure 6-1.
The device is ready for the next communication after above steps have been completed.
Figure 6-1. Software reset
SCL 9
Start
Bit Start
Bit
Stop
Bit
8321
SDA
Dummy Clock Cycles
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
Figure 6-2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Figure 6-3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
Notes: 1. The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal
clear/write cycle.
SCL
SDA IN
SDA OUT
tF
tHIGH
tLOW tLOW
tR
tAA tDH tBUF
tSU.STO
tSU.DAT
tHD.DAT
tHD.STA
tSU.STA
tWR
(1)
Stop
Condition
Start
Condition
WORDN
ACK
8th Bit
SCL
SDA
8
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
Figure 6-4. Data Validity
Figure 6-5. Start and Stop Definition
Figure 6-6. Output Acknowledge
SDA
SCL
Data Stable Data Stable
Data
Change
SDA
SCL
Start Stop
SCL
Data In
Data Out
Start Acknowledge
9
8
1
9
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
7. Device Addressing
The 1-Kbit and 2-Kbit EEPROM device requires an 8-bit device address word following a start condition to enable the
chip for a Read or Write operation.
The device address word consists of a mandatory ‘1010’ (0xA) sequence for the first four most significant bits as
shown in Figure 7-1. This is common to all Serial EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits for the 1K and 2K EEPROM. These three bits must
compare to their corresponding hard-wired input pins A2, A1, and A0 in order for the part to acknowledge.
The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit is high
and a Write operation is initiated if this bit is low.
Upon a valid compare of the device address with hard-wired input pins A2, A1, and A0, the EEPROM will output a zero. If
a compare is not successfully made, the chip will return to a standby state.
Figure 7-1. Device Address
8. Write Operations
Byte Write: A Byte Write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such
as a microcontroller, must terminate the write sequence with a Stop condition. At this time, the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see Figure 9-1 on page 10).
Page Write: The 1-Kbit and 2-Kbit EEPROM are capable of an 8-byte Page Write.
A Page Write is initiated the same as a Byte Write, but the microcontroller does not send a Stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to seven data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the page write sequence with a Stop condition (see Figure 9-2 on page 10).
The data word address lower three bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight
data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.
Data Security: The AT24C01C/02C has a hardware data protection scheme that allows the user to write protect the
entire memory when the WP pin is at VCC.
1 0 1 0 A2 A1 A0 R/W
1K or 2K
MSB LSB
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
9. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three read operations:
Current Address Read
Random Address Read
Sequential Read.
Current Address Read: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll-over during read is from the last byte of the last memory page to the first byte of the first
page. The address roll-over during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an zero but does generate a
following Stop condition (see Figure 9-3 on page 11).
Random Read: A Random Read requires a dummy byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a Current Address Read by sending a device address
with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word.
The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 9-4 on page
11).
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will roll-over and the Sequential Read will continue. The
Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a
following stop condition (see Figure 9-5 on page 11).
Figure 9-1. Byte Write
Figure 9-2. Page Write
SDA LINE
S
T
A
R
T
W
R
I
T
E
S
T
O
P
Device
Address Word Address Data
M
S
B
A
C
K
A
C
K
A
C
K
R
/
W
SDA LINE
S
T
A
R
T
W
R
I
T
E
S
T
O
P
Device
Address
Word
Address (n) Data (n) Data (n + 1) Data (n + x)
M
S
B
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
R
/
W
11
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
Figure 9-3. Current Address Read
Figure 9-4. Random Read
Figure 9-5. Sequential Read
SDA LINE
S
T
A
R
T
R
E
A
D
S
T
O
P
Device
Address Data
M
S
B
A
C
K
N
O
A
C
K
R
/
W
SDA LINE
S
T
A
R
T
S
T
A
R
T
R
E
A
D
W
R
I
T
E
S
T
O
P
Device
Address
Device
Address
Word
Address (n) Data (n)
M
S
B
A
C
K
A
C
K
A
C
K
N
O
A
C
K
R
/
W
Dummy Write
SDA LINE
R
E
A
D
S
T
O
P
Device
Address Data (n) Data (n + 1) Data (n + 2) Data (n + x)
M
S
B
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
R
/
W
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
10. Ordering Code Detail
Atmel Designator
Product Family
Device Density
Device Revision
Shipping Carrier Option
Operating Voltage
01 = 1-Kbit
02 = 2-Kbit
B or blank = Bulk (tubes)
T = Tape and Reel
M = 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
U = Green, matte Sn lead finish,
Industrial temperature range
(-40˚C to +85˚C)
H = Green, NiPdAu lead finish,
Industrial temperature range
(-40˚C to +85˚C)
11 = 11mil wafer thickness
Package Option
P = PDIP
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
ST = SOT23
C = VFBGA
WWU = Wafer unsawn
AT24C01C-SSHM-B
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
11. Part Markings
DRAWING NO. REV.
TITLE
Catalog Number Truncation
AT24C01C Truncation Code ###: 01C
AT24C02C Truncation Code ###: 02C
AAAAAAAA
###M @
ATMLUYWW
8-lead PDIP
AAAAAAAA
###M @
ATMLHYWW
8-lead SOIC 8-lead TSSOP
AAAAAAA
###M @
ATHYWW
###U
@YMXX
2.35 x 3.73 mm Body
8-ball VFBGA8-lead UDFN
###
HM@
YXX
2.0 x 3.0 mm Body
5-lead SOT-23
###MU
YMXX Bottom Mark
Top Mark
Note 2: Package drawings are not to scale
Note 1: designates pin 1
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
24C01-02CSM A
5/4/12
24C01-02CSM, AT24C01C and AT24C02C Package
Marking Information
Date Codes Voltages
Y = Year M = Month WW = Work Week of Assembly M: 1.7V min
2: 2012 6: 2016 A: January 02: Week 2
3: 2013 7: 2017 B: February 04: Week 4
4: 2014 8: 2018 ... ...
5: 2015 9: 2019 L: December 52: Week 52
Country of Assembly Lot Number Grade/Lead Finish Material
@ = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/Matte Tin
H: Industrial/NiPdAu
Trace Code Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel
Example: AA, AB.... YZ, ZZ ATM: Atmel
ATML: Atmel
AT24C01C and AT24C02C: Package Marking Information
14
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
12. Ordering Codes
12.1 Atmel AT24C01C Ordering Information
Notes: 1. B = Bulk (tubes)
2. T = Tape and reel
SOIC = 4K per reel
TSSOP, UDFN, SOT23, and VFBGA = 5K per reel
3. For Wafer sales, please contact Atmel Sales.
Ordering Code Package Voltage Operation Range
AT24C01C-PUM (Bulk Form Only) 8P3
1.7V to 5.5V
Lead-free/Halogen-free/
Industrial Temperature
(–40C to 85C)
AT24C01C-SSHM-B(1) (NiPdAu Lead Finish) 8S1
AT24C01C-SSHM-T(2) (NiPdAu Lead Finish) 8S1
AT24C01C-XHM-B(1) (NiPdAu Lead Finish) 8X
AT24C01C-XHM-T(2) (NiPdAu Lead Finish) 8X
AT24C01C-MAHM-T(2) (NiPdAu Lead Finish) 8MA2
AT24C01C-STUM-T(2) 5TS1
AT24C01C-CUM-T(2) 8U3-1
AT24C01C-WWU11M(3) Wafer Sale Industrial Temperature
(–40C to 85C)
Package Type
8P3 8-lead, 0.300" wide, Plastic Dual Inline (PDIP)
8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm body, 0.50mm Pitch, Ultra Thin Dual Flat No Lead (UDFN)
5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23)
8U3-1 8-ball, die Ball Grid Array (VFBGA)
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Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
12.2 Atmel AT24C02C Ordering Information
Notes: 1. B = Bulk (tubes)
2. T = Tape and reel
SOIC = 4K per reel
TSSOP, UDFN, SOT23, and VFBGA = 5K per reel
3. For Wafer sales, please contact Atmel Sales.
Ordering Code Package Voltage Operation Range
AT24C02C-PUM (Bulk Form Only) 8P3
1.7V to 5.5V
Lead-free/Halogen-free/
Industrial Temperature
(–40C to 85C)
AT24C02C-SSHM-B(1) (NiPdAu Lead Finish) 8S1
AT24C02C-SSHM-T(2) (NiPdAu Lead Finish) 8S1
AT24C02C-XHM-B(1) (NiPdAu Lead Finish) 8X
AT24C02C-XHM-T(2) (NiPdAu Lead Finish) 8X
AT24C02C-MAHM-T(2) (NiPdAu Lead Finish) 8MA2
AT24C02C-STUM-T(2) 5TS1
AT24C02C-CUM-T(2) 8U3-1
AT24C02C-WWU11M(3) Wafer Sale Industrial Temperature
(–40C to 85C)
Package Type
8P3 8-lead, 0.300" wide, Plastic Dual Inline (PDIP)
8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm body, 0.50mm Pitch, Ultra Thin Dual Flat No Lead (UDFN)
5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23)
8U3-1 8-ball, die Ball Grid Array (VFBGA)
16
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
13. Packaging Information
13.1 8P3 — 8-lead PDIP
DRAWING NO. REV. TITLE GPC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Top View
Side View
End View
Package Drawing Contact:
packagedrawings@atmel.com
8P3 D
06/21/11
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP) PTC
17
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
13.2 8S1 — 8-lead JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
Ø
Ø
0° – 8°
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
Package Drawing Contact:
packagedrawings@atmel.com
8S1 G
6/22/11
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) SWB
18
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
13.3 8X — 8-lead TSSOP
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
Package Drawing Contact:
packagedrawings@atmel.com
8X D
6/22/11
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
19
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
13.4 8MA2 — 8-pad UDFN
TITLE DRAWING NO. GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com
8MA2YNZ B
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 1.20 1.30 1.40
A 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 – – 0.55
C 0.152 REF
L 0.30 0.35 0.40
e 0.50 BSC
b 0.18 0.25 0.30 3
K 0.20 – –
7/15/11
D2
E2
E
e (6x)
L (8x)
b (8x)
Pin#1 ID
A
A1
A2
Pin 1 ID
D
C
K
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
20
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
13.5 5TS1 — 5-lead SOT23
DRAWING NO. REV. TITLE GPC
Package Drawing Contact:
packagedrawings@atmel.com
5TS1 D
5/31/12
5TS1, 5-lead 1.60mm Body, Plastic Thin
Shrink Small Outline Package (Shrink SOT) TSZ
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.00
A1 0.00 - 0.10
A2 0.70 0.90 1.00
c 0.08 - 0.20 3
D 2.90 BSC 1,2
E 2.80 BSC 1,2
E1 1.60 BSC 1,2
L1 0.60 REF
e 0.95 BSC
e1 1.90 BSC
b 0.30 - 0.50 3,4
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,
protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does
not include interlead flash or protrusion. Interlead flash or protrusion shall not
exceed 0.15 mm per side.
2. The package top may be smaller than the package bottom. Dimensions D and E1
are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch
between the top and bottom of the plastic body.
3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15
mm from the lead tip.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion
shall be 0.08 mm total in excess of the "b" dimension at maximum material
condition. The dambar cannot be located on the lower radius of the foot. Minimum
space between protrusion and an adjacent lead shall not be less than 0.07 mm.
This drawing is for general information only. Refer to JEDEC
Drawing MO-193, Variation AB for additional information.
54
2
L1
L
C
END VIEW
C
A
A2
A1
b
e
PLANE
SEATING
D
SIDE VIEW
E
e1
E1
3
1
TOP VIEW
21
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
13.6 8U3-1 — 8-ball VFBGA
DRAWING NO. REV. TITLE GPC
Package Drawing Contact:
packagedrawings@atmel.com
8U3-1 E
3/27/12
8U3-1, 8-ball, 1.50mm x 2.00mm body,
0.50mm pitch, VFBGA Package GXU
COMMON DIMENSIONS
(Unit of Measure - mm)
SYMBOL MIN NOM MAX NOTE
A
0.73 0.79 0.85
A1 0.09 0.14 0.19
A2 0.40 0.45 0.50
b 0.20 0.25 0.30 2
D
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1 0.25 REF
d
1.00 BSC
d1 0.25 REF
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
Notes:
A2
SIDE VIEW
A
PIN 1 BALL PAD CORNER
TOP VIEW
E
D
A1
b
8 SOLDER BALLS
BOTTOM VIEW
(d1)
d
4
3
2
(e1)
6
e
5
7
PIN 1 BALL PAD CORNER
1
8
2.
22
Atmel AT24C01C/02C [DATASHEET]
8700F–SEEPR–6/12
14. Revision History
Doc. Rev. Date Comments
8700F 06/2012
Correct ordering codes:
- AT24C01C-WWU11, Die Sale to AT24C01C-WWU11M, Wafer Sale.
- AT24C02C-WWU11, Die Sale to AT24C02C-WWU11M, Wafer Sale.
Remove WDT from ordering code detail.
Update Atmel logos and disclaimer page.
8700E 05/2012
Update datasheet template.
Add AT24C01C to document.
Electrical performance improvements:
- Reduce all ISB from legacy values
- Increase 1MHz frequency range to include 2.5V operation.
Update package drawings to latest versions (where applicable) and selected waveforms.
8700D 08/2010 Change AT24C02C-XHM Part Marking from C02CM@ to 02CM @.
8700C 07/2010
Ordering Information:
- Change Atmel AT24C02C-TSUM-T to Atmel AT24C02C-STUM-T.
- Change Atmel AT24C02CY6-MAHM-T to Atmel AT24C02C-MAHM-T.
- Change Atmel AT24C02CU3-CUM-T to Atmel AT24C02C-CUM-T.
Catalog numbering scheme, change TS = SOT23 to ST = SOT23.
Part marking SOT23:
- Change 2CMWU to 2CMBU.
- Change W = Write Protection Feature to B = Write Protection.
Part marking PDIP and SOIC: Added @ = Country of Assembly.
Part marking TSSOP: Replaced and removed bottom mark.
Part marking UDFN: Added HM@.
Remove preliminary status.
Change tI Max 40 to 50 in Table AC Characteristics.
8700B 02/2010 Correct catalog numbering scheme and ordering information.
8700A 12/2009 Initial document release.
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© 2012 Atmel Corporation. All rights reserved. / Rev.: 8700F–SEEPR–6/12
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