SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Four (’391), Eight (’389) or Sixteen (’387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard
D
Designed for Signaling Rates† up to
630 Mbps With Very Low Radiation (EMI)
D
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
D
Propagation Delay Times Less Than 2.9 ns
D
Output Skew Is Less Than 150 ps
D
Part-to-Part Skew Is Less Than 1.5 ns
D
35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz
D
Driver Is High Impedance When Disabled or
With VCC < 1.5 V
D
SN65’ Version Bus-Pin ESD Protection
Exceeds 15 kV
D
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
D
Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
description
This family of four, eight, and sixteen differential
line drivers implements the electrical characteris-
tics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a
3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
when enabled.
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
VCC
VCC
GND
ENA
A1A
A2A
A3A
A4A
ENB
B1A
B2A
B3A
B4A
GND
VCC
VCC
GND
C1A
C2A
C3A
C4A
ENC
D1A
D2A
D3A
D4A
END
GND
VCC
VCC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
VCC
GND
ENA
A1A
A2A
A3A
A4A
GND
VCC
GND
B1A
B2A
B3A
B4A
ENB
GND
VCC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
NC
NC
NC
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
’LVDS389
DBT PACKAGE
(TOP VIEW)
’LVDS387
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN1,2
1A
2A
VCC
GND
3A
4A
EN3,4
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
’LVDS391
D OR PW PACKAGE
(TOP VIEW)
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal
pulldown that will drive the input to a low level when open circuited.
The SN65LVDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from –40°C to 85°C.
The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0°C to 70°C.
logic diagram (positive logic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A
(1/4 of ’LVDS387 or 1/2 of ’L VDS389 shown)
EN
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A
(’LVDS391 shown)
EN
EN
AVAILABLE OPTIONS
PART NUMBER†TEMPERATURE
RANGE NO. OF
DRIVERS BUS-PIN
ESD
SN65LVDS387DGG –40°C to 85°C 16 15 kV
SN75LVDS387DGG 0°C to 70°C 16 4 kV
SN65LVDS389DBT –40°C to 85°C 8 15 kV
SN75LVDS389DBT 0°C to 70°C 8 4 kV
SN65LVDS391D –40°C to 85°C 4 15 kV
SN75LVDS391D 0°C to 70°C 4 4 kV
SN65LVDS391PW –40°C to 85°C 4 15 kV
SN75LVDS391PW 0°C to 70°C 4 4 kV
†This package is available taped and reeled. To order this packaging option, add
an R suffix to the part number (e.g., SN65LVDS387DGGR).
DRIVER FUNCTION TABLE
INPUT ENABLE OUTPUTS
A EN Y Z
H H H L
L H L H
X L Z Z
OPEN H L H
H = high-level, L = low-level, X = irrelevant,
Z = high-impedance (off)
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
7 V
300 kΩ
50 Ω
VCC
A or EN
Input
VCC
5 Ω
7 V
Y or Z
Output
EQUIVALENT OF EACH A OR EN INPUT TYPICAL OF ALL OUTPUTS
10 kΩ
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: Inputs –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y or Z –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: SN65’ (Y, Z, and GND) Class 3, A:15 kV, B: 500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN75’ (Y, Z, and GND) Class 3, A:4 kV, B: 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°CDERATING FACTOR‡
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D950 mW 7.6 mW/°C608 mW 494 mW
DBT 1071 mW 8.5 mW/°C688 mW 556 mW
DGG 2094 mW 16.7 mW/°C1342 mW 1089 mW
PW 774 mW 6.2 mW/°C496 mW 402 mW
‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
O
p
erating free-air tem
p
erature TA
SN75’0 70 °C
O erating
free
-
air
tem erature
,
TA
SN65’ –40 85 °C
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
|VOD|Differential output voltage magnitude
RL= 100 Ω
247 340 454
∆|VOD|Change in differential output voltage
magnitude between logic states
R
L =
100
Ω
,,
See Figure 1 and Figure 2 –50 50 mV
VOC(SS) Steady-state common-mode output voltage 1.125 1.375 V
∆VOC(SS) Change in steady-state common-mode output
voltage between logic states See Figure 3 –50 50 mV
VOC(PP) Peak-to-peak common-mode output voltage 50 150 mV
’LVDS387
Enabled,
85 95
’LVDS389
Enabled
,
RL = 100 Ω,50 70
ICC
Su
pp
ly current
’LVDS391 VIN = 0.8 V or 2 V 20 26
mA
I
CC
Supply
current
’LVDS387
Di bl d
0.5 1.5
mA
’LVDS389 Disabled,
VIN =0VorV
CC
0.5 1.5
’LVDS391
VIN
=
0
V
or
VCC
0.5 1.3
IIH High-level input current VIH = 2 V 3 20 µA
IIL Low-level input current VIL = 0.8 V 2 10 µA
IOS
Short circuit out
p
ut current
VOY or VOZ = 0 V ±24 mA
I
OS
Short
-
circuit
output
current
VOD = 0 V ±12 mA
IOZ High-impedance output current VO = 0 V or VCC ±1µA
IO(OFF) Power-of f output current VCC = 1.5 V, VO = 2.4 V ±1µA
CIN Input capacitance VI = 0.4 sin (4E6πt) + 0.5 V 5 pF
COOutput capacitance VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled 9.4 pF
†All typical values are at 25°C and with a 3.3-V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
tPLH Propagation delay time, low-to-high-level output 0.9 1.7 2.9 ns
tPHL Propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns
trDifferential output signal rise time
RL= 100 Ω
0.4 0.8 1 ns
tfDifferential output signal fall time
RL
=
100
Ω
,
CL = 10 pF, 0.4 0.8 1 ns
tsk(p) Pulse skew (|tPHL – tPLH|)
L
See Figure 4 150 500 ps
tsk(o) Output skew‡80 150 ps
tsk(pp) Part-to-part skew§1.5 ns
tPZH Propagation delay time, high-impedance-to-high-level output 6.4 15 ns
tPZL Propagation delay time, high-impedance-to-low-level output
See Figure 5
5.9 15 ns
tPHZ Propagation delay time, high-level-to-high-impedance output
See
Figure
5
3.5 15 ns
tPLZ Propagation delay time, low-level-to-high-impedance output 4.5 15 ns
†All typical values are at 25°C and with a 3.3-V supply.
‡tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together .
§tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
GND
VI
A
(VOY + VOZ)/2
IOZ
IOY
Y
ZVOD
VOY VOC
II
VOZ
Figure 1. Voltage and Current Definitions
±
3.75 kΩ
0 V ≤ VTEST ≤ 2.4 V
Y
ZVOD
Input 100 Ω
3.75 kΩ
Figure 2. VOD Test Circuit
Y
Z
Input
50 pF
49.9 Ω ± 1% (2 Places)
VOC
VO
VOC(PP) VOC(SS)
0 V
3 V
VI
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
ZVOD
Input
CL = 10 pF
(2 Places)
100 Ω ± 1 %
2 V
1.4 V
0.8 V
tPLH tPHL
100%
80%
20%
0%
Input
Output
0 V
tftr
VOD(H)
VOD(L)
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CL = 10 pF
(2 Places)
Y
Z
Input
49.9 Ω ± 1% (2 Places)
tPZH tPHZ
tPZL tPLZ
2 V
1.4 V
0.8 V
≅ 1.4 V
1.3 V
1.2 V
≅ 1 V
1.2 V
1.1 V
Input
VOY
or
VOZ
VOZ
or
VOY
VOY VOZ
0.8 V or 2 V
1.2 V
+
–
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
f – Frequency – MHz
– Supply Current – mA
ICC
0
10
20
30
40
50
60
0 50 100 150 200 250 300
VCC = 3.6 V
All outputs loaded and enabled.
VCC = 3.3 V
VCC = 3 V
’LVDS391
SUPPLY CURRENT (RMS)
vs
SWITCHING FREQUENCY
Figure 6
Figure 7
f – Frequency – MHz
– Supply Current – mA
ICC
80
100
120
140
160
180
200
220
240
0 50 100 150 200 250 300 350
VCC = 3.6 V
All outputs loaded and enabled.
VCC = 3.3 V
VCC = 3 V
’LVDS387
SUPPLY CURRENT (RMS)
vs
SWITCHING FREQUENCY
Figure 8
f – Frequency – MHz
– Supply Current – mA
ICC
40
50
60
70
80
90
100
110
0 50 100 150 200 250 300
VCC = 3.6 V
All outputs loaded and enabled.
VCC = 3.3 V
VCC = 3 V
’LVDS389
SUPPLY CURRENT (RMS)
vs
SWITCHING FREQUENCY
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
TA – Free-Air Temperature – °C
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
–40 –20 0 20 40 60 80 100
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
tPLH – Low-To-High Propagation Delay Time – ns
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
Figure 10
Ta – Free-Air Temperature – °C
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
1.0
1.2
1.4
1.6
1.8
2.0
2.2
–40 –20 0 20 40 60 80 100
tPHL – High-To-Low Propagation Delay Time – ns
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
Figure 11
0
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL – Low-Level Output Current – mA
4
3
046
2
2
VCC = 3.3 V
TA = 25°C
1
VOL – Low-Level Output Voltage – V
Figure 12
–4
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH – High-Level Output Current – mA
3.5
2.5
0–20
1.5
–3
0.5
VOH– High-Level Output Voltage – V
–1
3
2
1
VCC = 3.3 V
TA = 25°C
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
t – Time – ns
OUTPUT VOLTAGE
vs
TIME
– Output Voltage – V
VO
VOY
VOZ
VOD
Figure 13
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Host
Controller
TX Clock
SN65LVDS387 or 389
Target
Controller
Target
LVDS Receiver(s)
Indicates twisting of the
conductors.
T
T
T
T
TIndicates the line termination
circuit.
Host Balanced Interconnect
Power Power
DB0
DB1
DB2
DBn–3
T
T
T
T
DBn–2
DBn–1
DBn
RX Clock
DB0
DB1
DB2
DBn–3
DBn–2
DBn–1
DBn
Figure 14. Typical Application Schematic
Signaling Rate vs Distance
The ultimate data transfer rate over a given cable or trace length involves many variables. Starting with the
capabilities of this LVDS driver to reproduce a data pulse as short as 1.6 ns (a 630 Mbps signaling rate) with
less than 500 ps of pulse distortion, any degradation of this pulse by the transmission media will necessarily
reduce the timing margin at the receiving end of the data link.
The timing uncertainty induced by the transmission media is commonly referred to as jitter and comes from
numerous sources. The characteristics of a particular transmission media can be quantified by using an
eyepattern measurement such as shown in Figure 12, which shows about 340 ps of jitter or 20% of the data
pulse width.
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
width
abs.
jitter
height
unit interval
Figure 15. Typical LVDS Eyepattern
A generally accepted range of jitter at the receiver inputs that allows data recovery is 5% to 20% of the unit
interval (data pulse width). Table 1 shows the signaling rate achieved on various cables and lengths at a 5%
eyepattern jitter with a typical LVDS driver.
Table 1. Signaling Rates for Various Cables for 5% Eyepattern Jitter
LENGTH
CABLE†
LENGTH
(m) A
(Mbps) B
(Mbps) C
(Mbps) D
(Mbps) E
(Mbps) F
(Mbps)
1 240 200 240 270 180 230
5 205 210 230 250 215 230
10 180 150 195 200 145 180
†Cable A: CAT 3, specified up to 16 MHz, no shield, outside conductor diameter (∅) 0.52 mm
Cable B: CAT 5, specified up to 100 MHz, no shield, ∅ 0.52 mm
Cable C: CAT 5, specified up to 100 MHz, taped over all shield, ∅ 0.52 mm
Cable D: CA T 5 (exceeding CAT 5), specified up to 300 MHz, braided over all shield plus taped individual shield for any
pair, ∅ 0.64 mm (A WG22)
Cable E: CAT 5 (exceeding CAT 5), specified up to 350 MHz, ∅ 0.64 mm (AWG22), no shield
Cable F: CAT 5 (exceeding CAT 5), specified up to 350 MHz, “self-shielded”, ∅0.64 mm (A WG22)
During synchronous parallel transfers, skew between the data and clock lines will also reduce the timing margin.
This must be accounted for in the system timing budget. Fortunately, the low output skew of this LVDS driver
will generally be a small portion of this budget.
other LVDS products
For other products and applications notes in the LVDS and LVDM product families visit our Web site at
http://www.ti.com/sc/datatran.
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,75
0,25
0,50
0,15 NOM
Gage Plane
50
12,60
38
9,80 11,10
44
12,409,60 10,90
4073252/D 09/97
4,30
4,50
0,27
0,17
16
15
30
A
1
7,90
30
DIM
A MAX
PINS **
7,70
A MIN
1,20 MAX
6,60
6,20
Seating Plane
0,10
0,50 M
0,08
0°–8°
7,90
28
7,70
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS387DGG ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS387DGGG4 ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS387DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS387DGGRG4 ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS389DBT ACTIVE TSSOP DBT 38 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS389DBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS389DBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS389DBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS391D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS391PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS387DGG ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS387DGGG4 ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS387DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS387DGGRG4 ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS389DBT ACTIVE TSSOP DBT 38 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS389DBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS389DBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS389DBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS391D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 12-Feb-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75LVDS391DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS391DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS391DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS391PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS391PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS391PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LVDS391PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Feb-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS387DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1
SN65LVDS389DBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
SN65LVDS391DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS391PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN75LVDS387DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1
SN75LVDS389DBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
SN75LVDS391DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN75LVDS391PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS387DGGR TSSOP DGG 64 2000 346.0 346.0 41.0
SN65LVDS389DBTR TSSOP DBT 38 2000 346.0 346.0 33.0
SN65LVDS391DR SOIC D 16 2500 346.0 346.0 33.0
SN65LVDS391PWR TSSOP PW 16 2000 346.0 346.0 29.0
SN75LVDS387DGGR TSSOP DGG 64 2000 346.0 346.0 41.0
SN75LVDS389DBTR TSSOP DBT 38 2000 346.0 346.0 33.0
SN75LVDS391DR SOIC D 16 2500 346.0 346.0 33.0
SN75LVDS391PWR TSSOP PW 16 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers amplifier.ti.com Audio www.ti.com/audioData Converters dataconverter.ti.com Automotive www.ti.com/automotiveDLP® Products www.dlp.com Broadband www.ti.com/broadbandDSP dsp.ti.com Digital Control www.ti.com/digitalcontrolClocks and Timers www.ti.com/clocks Medical www.ti.com/medicalInterface interface.ti.com Military www.ti.com/militaryLogic logic.ti.com Optical Networking www.ti.com/opticalnetworkPower Mgmt power.ti.com Security www.ti.com/securityMicrocontrollers microcontroller.ti.com Telephony www.ti.com/telephonyRFID www.ti-rfid.com Video & Imaging www.ti.com/videoRF/IF and ZigBee® Solutions www.ti.com/lprf Wireless www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated
