Product Folder Sample & Buy Technical Documents Support & Community Tools & Software LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 LP3850x-ADJ, LP3850xA-ADJ 1.5-A Flexcap Low-Dropout Linear Regulator for 2.7-V to 5.5-V Inputs 1 Features 3 Description * * * TI's FlexCap low-dropout (LDO) linear regulators feature unique compensation that allow use of any type of output capacitor with no limits on minimum or maximum equivalent series resistance (ESR). The LP38500 and LP38502 series of LDOs operates from a 2.7-V to 5.5-V input supply. These ultra-low-dropout linear regulators respond very quickly to step changes in load, making them suitable for low-voltage microprocessor applications. Developed on a CMOS process (utilizing a PMOS pass transistor) the LP38500-ADJ and LP38502-ADJ have low quiescent currents that changes little with load current. * GND Pin Current: Typically 2 mA at 1.5-A load current. * Disable Mode: Typically 25-nA quiescent current when the EN pin is pulled low. (LP38502-ADJ) * Simplified Compensation: Stable with any type of output capacitor, regardless of ESR. * Precision Output: A grade versions available with 1.5% VADJ tolerance (25C) and 3% over line, load, and temperature. 1 * * * * * * * * Input Voltage: 2.7 V to 5.5 V Adjustable Output Voltage: 0.6 V to 5 V FlexCap: Stable with Ceramic, Tantalum, or Aluminum Capacitors Stable with 10-F Input and Output Capacitors Low Ground-Pin Current 25-nA Quiescent Current in Shutdown Mode Ensured Output Current of 1.5 A Ensured VADJ Accuracy of 1.5% at 25C (A Grade) Ensured Accuracy of 3.5% at 25C (STD) Overtemperature and Overcurrent Protection ENABLE Pin (LP38502) 2 Applications * * * * ASIC Power Supplies In: - Printers, Graphics Cards, DVD Players - Set Top Boxes, Copiers, Routers DSP and FPGA Power Supplies SMPS Regulator Conversion from 3.3-V or 5-V Rail Device Information(1) PART NUMBER LP38500 LP38502 PACKAGE BODY SIZE (NOM) DDPAK/TO-263 (5) 10.16 mm x 8.42 mm TO-263 (5) 10.16 mm x 9.85 mm WSON (8) 3.00 mm x 2.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Circuit (LP38500) Typical Circuit (LP38502) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configurations and Functions ....................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagrams ....................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Applications ............................................... 13 9 Power Supply Recommendations...................... 16 9.1 Power Dissipation/Heatsinking................................ 16 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Examples................................................... 17 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (June 2015) to Revision H * Page Changed thermal values for KTT (DDPAK/TO-263); add notes 2 and 3 to Thermal Information table ................................ 4 Changes from Revision F (April 2013) to Revision G Page * Added Added Device Information and Pin Configuration and Functions sections, ESD Ratings and updated Thermal Information tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support , and Mechanical, Packaging, and Orderable Information sections................................................................................................................................................................ 1 * Deleted obsolete heatsinking information for DDPAK/TO-263 package ............................................................................. 16 Changes from Revision E (April 2013) to Revision F * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 19 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 5 Pin Configurations and Functions KTT Package (LP38500) 5-Pin DDPAK/TO-263 Top View KTT Package (LP38502) 5-Pin DDPAK/TO-263 Top View NDQ Package (LP38500) 5-Pin TO-263 Top View NDQ Package (LP38502) 5-Pin TO-263 Top View NGS Package (LP38500A) 8-Pin WSON Top View NGS Package (LP38502A) 8-Pin WSON Top View Pin Functions PIN NAME TYPE DESCRIPTION KTT NDQ NGS ADJ 5 5 8 O Sets output voltage EN 1 1 2 I Enable (LP38502-ADJ only). Pull high to enable the output, low to disable the output. This pin has no internal bias and must be either tied to the input voltage, or actively driven. GND 3 3 1 G Ground IN -- -- 2 I Input supply (LP38500-ADJ only). Input supply pins share current and must be connected together on the PC board. IN 2 2 3, 4 I Input supply. Input Supply pins share current and must be connected together on the PC board. N/C 1 1 -- -- In the LP38500-ADJ, this pin has no internal connections. It can be left floating or used for trace routing. OUT 4 4 5, 6, 7 O Regulated output voltage. Output pins share current and must be connected together on the PC board. -- The DAP is used to remove heat from the device by conducting it to a copper clad area on the PCB which acts as a heatsink. The DAP is electrically connected to the backside of the die. The DAP must be connected to ground potential, but can not be used as the only ground connection. DAP Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 3 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Input pin voltage (survival) -0.3 6 V Enable pin voltage (survival) -0.3 6 V Output pin voltage (survival) -0.3 6 V IOUT (survival) Internally limited Power dissipation (3) Internally limited -65 Storage temperature, Tstg (1) (2) (3) 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Office/ Distributors for availability and specifications. Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RJA). See Application and Implementation. 6.2 ESD Ratings VESD (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN NOM MAX UNIT Input supply voltage 2.7 5.5 V Enable input voltage 0 5.5 V Output current (DC) 0 1.5 A 0.6 5 V -40 125 C VOUT Junction temperature (1) (1) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RJA). See Application and Implementation. 6.4 Thermal Information LP38500 and LP38502 THERMAL METRIC (1) KTT(DDPAK/TO-263) NDQ (TO-263) NGS (WSON) 5 PINS 5 PINS 8 PINS UNIT RJA (2) Junction-to-ambient thermal resistance 41.8 33.3 52.5 (3) C/W RJC(top) Junction-to-case (top) thermal resistance 45.0 22.1 53.6 C/W RJB Junction-to-board thermal resistance 24.8 16.9 26.1 C/W JT Junction-to-top characterization parameter 13.1 5.8 0.6 C/W JB Junction-to-board characterization parameter 23.8 16.8 26.3 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 2.4 2.3 7.4 C/W (1) (2) (3) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Thermal resistance value RJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. The PCB for the NGN (WSON) package RJA includes thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5. Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 6.5 Electrical Characteristics Unless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 F, COUT = 10 F, VEN = VIN, VOUT = 1.8 V. Minimum and maximum limits apply over the junction temperature (TJ) range of -40C to +125C and are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. PARAMETER VADJ VADJ IADJ TEST CONDITIONS Adjust pin voltage (1) Adjust pin voltage (A grade) (1) MIN TYP MAX 2.7 V VIN 5.5 V 10 mA IOUT 1.5 A TJ = 25C 0.584 0.605 0.626 2.7 V VIN 5.5 V 10 mA IOUT 1.5 A 0.575 2.7 V VIN 5.5 V 10 mA IOUT 1.5 A TJ = 25C 0.596 2.7 V VIN 5.5 V 10 mA IOUT 1.5 A 0.587 V 0.635 0.605 0.623 50 2.7 V VIN 5.5 V IOUT = 1.5 A TJ = 25C Dropout voltage (2) VDO 220 IOUT = 1.5 A VOUT / VIN VOUT / IOUT IGND Output voltage line regulation (1) (3) Output voltage load regulation (1) (4) Ground pin current in normal operation mode IDISABLED Ground pin current IOUT(PK)GN Peak output current 0.614 V 2.7 V VIN 5.5 V TJ = 25C ADJUST pin bias current UNIT 2.7 V VIN 5.5 V TJ = 25C 0.04 2.7 V VIN 5.5 V 0.05 10 mA < IOUT < 1.5 A TJ = 25C 0.18 10 mA < IOUT < 1.5 A 0.33 10 mA < IOUT < 1.5 A TJ = 25C 2 nA 750 nA 275 mV 375 mV %/V %/V %/A %/A 3.5 mA 10 mA < IOUT < 1.5 A 4.5 VEN < VIL(EN), TJ = 25C 0.025 VEN < VIL(EN) 0.125 15 VOUT VOUT(NOM) - 5% A 3.6 A 3.7 A D ISC VOUT = 0 V, TJ = 25C Short-circuit current VOUT = 0 V 2 1.4 ENABLE INPUT (LP38502 Only) VIH(EN) Enable logic high VOUT = ON VIL(EN) Enable logic low VOUT = OFF td(off) Turnoff delay Time from VEN < VIL(EN) to VOUT = OFF ILOAD = 1.5 A 25 s td(on) Turnon delay Time from VEN >VIH(EN) to VOUT = ON ILOAD = 1.5A 25 s IIH(EN) Enable pin high current VEN = VIN 1 nA IIL(EN) Enable pin low current VEN = 0 V 0.1 (1) (2) (3) (4) V 0.65 V The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the adjust voltage tolerance specification. Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For any output voltage less than 2.5V, the minimum VIN operating voltage is the limiting factor. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current. Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 5 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 F, COUT = 10 F, VEN = VIN, VOUT = 1.8 V. Minimum and maximum limits apply over the junction temperature (TJ) range of -40C to +125C and are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PARAMETERS VIN = 3 V, IOUT = 1.5 A, = 120 Hz 58 VIN = 3 V, IOUT = 1.5 A, = 1 kHz 56 PSRR Ripple rejection n(l/f) Output noise density = 120 Hz, COUT = 10 F CER 1 V/Hz Output noise voltage BW = 100 Hz - 100 kHz COUT = 10 F CER 100 V(rms) TSD Thermal shutdown TJ rising 170 -- C TSD Thermal shutdown hysteresis TJ falling from TSD 10 -- C en dB THERMALS 6 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 6.6 Typical Characteristics Unless otherwise specified: TJ = 25C, VIN = 2.7 V, VEN = VIN, CIN = 10 F, COUT = 10 F, IOUT = 10 mA, VOUT = 1.8 V. Figure 1. Noise Density Figure 2. Noise Density Figure 3. IGND vs Load Current Figure 4. IGND(OFF) vs Temperature Figure 5. VADJ vs Temperature Figure 6. Dropout Voltage vs Load Current Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 7 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified: TJ = 25C, VIN = 2.7 V, VEN = VIN, CIN = 10 F, COUT = 10 F, IOUT = 10 mA, VOUT = 1.8 V. Figure 7. VEN vs Temperature Figure 8. Turnon Characteristics Figure 9. PSRR 8 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 7 Detailed Description 7.1 Overview The LP38500-ADJ and LP38502-ADJ are flex-cap and low-dropout adjustable regulators, the output voltage can be set from 0.6 V to 5 V. Standard regulator features, such as overcurrent and overtemperature protections, are also included. The LP38500-ADJ and LP38502-ADJ contains several features: Stable with any type of output capacitor Fast load transient response Disable Mode (LP38502-ADJ only) 7.2 Functional Block Diagrams Figure 10. LP38500-ADJ DDPAK/TO-263 Block Diagram Figure 11. LP38502-ADJ DDPAK/TO-263 Block Diagram Figure 12. LP38500-ADJ WSON Block Diagram Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 9 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com Functional Block Diagrams (continued) Figure 13. LP38502-ADJ WSON Block Diagram 7.3 Feature Description 7.3.1 Stability And Phase Margin Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate phase margin, which is defined as the difference between the phase shift and -180 degrees at the frequency where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to create a zero to add enough phase lead to ensure stable operation. The LP38500-ADJ and LP38502-ADJ each have a unique internal compensation circuit which maintains phase margin regardless of the ESR of the output capacitor, so any type of capacitor may be used. Figure 14 shows the gain/phase plot of the LP38500-ADJ and LP38502-ADJ with an output of 1.2 V, a 10-F ceramic output capacitor, delivering 1.5 A of load current. It can be seen that the unity-gain crossover occurs at 150 kHz, and the phase margin is about 40 (which is very stable). Figure 14. Gain-Bandwidth Plot for 1.5-A Load Figure 15 shows the gain and phase with no external load. In this case, the only load is provided by the gain setting resistors (about 12 k total in this test). It is immediately obvious that the unity-gain frequency is significantly lower (dropping to about 500 Hz), at which point the phase margin is 125. 10 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 Feature Description (continued) Figure 15. Gain-Bandwidth Plot for No Load The reduction in unity-gain bandwidth as load current is reduced is normal for any LDO regulator using a P-FET or PNP pass transistor, because they have a pole in the loop gain function given by: 1 FP 2 u S u RL u COUT (1) This illustrates how the pole goes to the highest frequency when RL is minimum value (maximum load current). In general, LDOs have maximum bandwidth (and lowest phase margin) at full load current. In the case of the LP38500-ADJ or LP38502-ADJ, it can be seen that it has good phase margin even when using ceramic capacitors with ESR values of only a few m. 7.3.2 Load Transient Response Load transient response is defined as the change in regulated output voltage which occurs as a result of a change in load current. Many applications have loads which vary, and the control loop of the voltage regulator must adjust the current in the pass FET transistor in response to load current changes. For this reason, regulators with wider bandwidths often have better transient response. The LP38500-ADJ and LP38502-ADJ employs an internal feed-forward design which makes the load transient response much faster than would be predicted simply by loop speed: this feedforward means any voltage changes appearing on the output are coupled through to the high-speed driver used to control the gate of the pass FET along a signal path using very fast FET devices. Because of this, the pass transistor's current can change very quickly. Figure 15 shows the output voltage load transient which occurs on a 1.8-V output when the load changes from 0.1 A to 1.5 A at an average slew rate of 0.5 A/s. As shown, the peak output voltage change from nominal is about 40 mV, which is about 2.2%. Figure 16. Load Transient Response Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 11 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) In cases where extremely fast load changes occur, the output capacitance may have to be increased. For fast changing loads, the internal parasitics of ESR (equivalent series resistance) and ESL (equivalent series inductance) degrade the capacitor's ability to source current quickly to the load. The best capacitor types for transient performance are (in order): 1. Multilayer Ceramic: with the lowest values of ESR and ESL, they can have ESR values in the range of a few m. Disadvantage: capacitance values above about 22 F significantly increase in cost. 2. Low-ESR Aluminum Electrolytics: these are aluminum types (like OSCON) with a special electrolyte which provides extremely low ESR values, and are the closest to ceramic performance while still providing large amounts of capacitance. These are cheaper (by capacitance) than ceramic. 3. Solid tantalum: can provide several hundred F of capacitance, transient performance is slightly worse than OSCON type capacitors, cheaper than ceramic in large values. 4. General purpose aluminum electrolytics: cheap and provide a lot of capacitance, but give the worst performance. In general, managing load transients is done by paralleling ceramic capacitance with a larger bulk capacitance. In this way, the ceramic can source current during the rapidly changing edge and the bulk capacitor can support the load current after the first initial spike in current. 7.3.3 Dropout Voltage The dropout voltage of a regulator is defined as the input-to-output differential required by the regulator to keep the output voltage within 2% of the nominal value. For CMOS LDOs, the dropout voltage is the product of the load current and the RDS(on) of the internal MOSFET pass element. Since the output voltage is beginning to "drop out" of regulation when it drops by 2%, electrical performance of the device will be reduced compared to the values listed in the Electrical Characteristics table for some parameters (line and load regulation and PSRR would be affected). 7.3.4 Reverse Current Path The internal MOSFET pass element in the LP38500-ADJ and LP38502-ADJ has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-mA continuous and 1-A peak. The regulator output pin should not be taken below ground potential. If the LP38500-ADJ and LP38502-ADJ is used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground. 7.4 Device Functional Modes 7.4.1 Short-Circuit Protection The LP38500-ADJ and LP38502-ADJ contain internal current limiting which will reduce output current to a safe value if the output is overloaded or shorted. Depending upon the value of VIN, thermal limiting may also become active as the average power dissipated causes the die temperature to increase to the limit value (about 170C). The hysteresis of the thermal shutdown circuitry can result in a "cyclic" behavior on the output as the die temperature heats and cools. 7.4.2 Enable Operation (LP38502-ADJ Only) The Enable pin (EN) must be actively terminated by either a 10-k pull-up resistor to VIN, or a driver which actively pulls high and low (such as a CMOS rail to rail comparator). If active drive is used, the pull-up resistor is not required. This pin must be tied to VIN if not used (it must not be left floating). 12 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP38500-ADJ and LP38502-ADJ devices can provide 1.5-A output current with 2.7-V to 5.5-V input voltage. These ultra-low-dropout linear regulators respond very quickly to step changes in load, making them suitable for low-voltage microprocessor applications. Input and output capacitors of at least 10 F are required. 8.2 Typical Applications Figure 17. Typical Circuit (LP38500) Figure 18. Typical Circuit (LP38502) 8.2.1 Design Requirements For LP3850x-ADJ typical applications, use the parameters listed in Table 1 as the input parameters. Table 1. Design Parameters DESIGN PARAMETERS VALUE Input voltage 2.7 V to 5.5 V Output voltage 0.6 V to 5 V (adjustable) Output current 1.5 A (maximum) Input capacitor 10 F (minimum) Output capacitor 10 uF (minimum) 8.2.2 Detailed Design Procedure 8.2.2.1 External Capacitors The LP38500-ADJ and LP38502-ADJ require that at least 10-F (20%) capacitors be used at the input and output pins located within one cm of the device. Larger capacitors may be used without limit on size for both CIN and COUT. Capacitor tolerances such as temperature variation and voltage loading effects must be considered when selecting capacitors to ensure that they will provide the minimum required amount of capacitance under all operating conditions for the application. In general, ceramic capacitors are best for noise bypassing and transient response because of their ultra low ESR. It must be noted that if ceramics are used, only the types with X5R or X7R dielectric ratings should be used (never Z5U or Y5F). Capacitors which have the Z5U or Y5F characteristics will see a drop in capacitance of as much as 50% if their temperature increases from 25C to 85C. In addition, the capacitance drops significantly with applied voltage: a typical Z5U or Y5F capacitor can lose as much as 60% of its rated capacitance if only half of the rated voltage is applied to it. For these reasons, only X5R and X7R ceramics should be used. Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 13 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com 8.2.2.2 Input Capacitor All linear regulators can be affected by the source impedance of the voltage which is connected to the input. If the source impedance is too high, the reactive component of the source may affect the control loop's phase margin. To ensure proper loop operation, the ESR of the capacitor used for CIN must not exceed 0.5 . Any good quality ceramic capacitor will meet this requirement, as well as many good quality tantalums. Aluminum electrolytic capacitors may also work, but can possibly have an ESR which increases significantly at cold temperatures. If the ESR of the input capacitor may exceed 0.5 , it is recommended that a 2.2-F ceramic capacitor be used in parallel, as this will assure stable loop operation. 8.2.2.3 Output Capacitor Any type of capacitor may be used for COUT, with no limitations on minimum or maximum ESR, as long as the minimum amount of capacitance is present. The amount of capacitance can be increased without limit. Increasing the size of COUT typically will give improved load transient response. 8.2.2.4 Setting The Output Voltage The output voltage of the LP38500/2-ADJ can be set to any value between 0.6V and 5V using two external resistors shown as R1 and R2 in Figure 19. Figure 19. Setting Output Voltage The value of R2 should always be less than or equal to 10 k for good loop compensation. R1 can be selected for a given VOUT using the following formula: VOUT = VADJ (1 + R1/R2) + IADJ (R1) where * * VADJ is the adjust pin voltage IADJ is the bias current flowing into the adjust pin (2) 8.2.2.5 RFI/EMI Susceptibility Radio Frequency Interference (RFI) and Electro-Magnetic Interference (EMI) can degrade any integrated circuit's performance because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the device regulator. If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the device to reduce the amount of EMI conducted into the device. If the LP38500, LP38502-ADJ output is connected to a load which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the device output. Since the bandwidth of the regulator loop is less than 300 kHz, the control circuitry cannot respond to load changes above that frequency. This means the effective output impedance of the device at frequencies above 300 kHz is determined only by the output capacitor(s). Ceramic capacitors provide the best performance in this type of application. 14 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 In applications where the load is switching at high speed, the output of the device may need RF isolation from the load. In such cases, it is recommended that some inductance be placed between the output capacitor and the load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from clean circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multi-layer PC Board applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. 8.2.2.6 Output Noise Noise is specified in two ways: * Spot noise or output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. * Total output noise or broadband noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Spot noise is measured in units V/Hz or nV/Hz and total output noise is measured in V(rms). The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a lowfrequency component and a high frequency component, which depend strongly on the silicon area and quiescent current. Noise can generally be reduced in two ways: increase the transistor area or increase the reference current. However, enlarging the transistors will increase die size, and increasing the reference current means higher total supply current (ground pin current). 8.2.3 Application Curves Figure 20. Turnon Time Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Figure 21. Turnon Time Submit Documentation Feedback 15 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com 9 Power Supply Recommendations The LP38500-ADJ and LP38502-ADJ devices are designed to operate from an input voltage supply range between 2.7 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. An input capacitor of at least 10 F is required. 9.1 Power Dissipation/Heatsinking The maximum power dissipation (PD(MAX)) of the LP38500-ADJ and LP38502-ADJ is limited by the maximum junction temperature of 125C, along with the maximum ambient temperature (TA(MAX)) of the application, and the thermal resistance (RJA) of the package. Under all possible conditions, the junction temperature (TJ) must be within the range specified in the Recommended Operating Conditions. The total power dissipation of the device is given by: PD = ((VIN - VOUT) x IOUT) + (VIN x IGND) where * IGND is the operating ground current of the device (specified under Electrical Characteristics) (3) The maximum allowable junction temperature rise (TJ) depends on the maximum expected ambient temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)): TJ = TJ(MAX)- TA(MAX) (4) The maximum allowable value for junction-to-ambient thermal resistance, RJA, can be calculated using the formula: RJA = TJ / PD(MAX) (5) The LP38500-ADJ and LP38502-ADJ are available in the DDPAK/TO-263, TO-263, and WSON packages. The thermal resistance depends on the amount of copper area allocated to heat transfer. 16 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 10 Layout 10.1 Layout Guidelines 10.1.1 Printed Circuit Board Layout Good layout practices will minimize voltage error and prevent instability which can result from ground loops. The input and output capacitors should be directly connected to the device pins with short traces that have no other current flowing in them (Kelvin connect). The best way to do this is to place the capacitors very near the device and make connections directly to the device pins via short traces on the top layer of the PCB. The regulator's ground pin should be connected through vias to the internal or backside ground plane so that the regulator has a single point ground. The external resistors which set the output voltage must also be located very near the device with all connections directly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to the load point or DC error will be induced. 10.2 Layout Examples R2 N/C ADJ R1 IN OUT Input Capacitor Output Capacitor Ground Figure 22. LP38500-ADJ TO-263 Layout (LP38500) Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 17 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com Layout Examples (continued) R2 EN ADJ Pull-up Resistor R1 IN OUT Input Capacitor Output Capacitor Ground Figure 23. LP38502-ADJ TO-263 Layout BYPASS SHUTDOWN Error Pullup Resistor N/C VOUT ERROR Ground GROUND SENSE IN OUT Input Capacitor VOUT VIN Output Capacitor Figure 24. LP3850x WSON Layout 10.2.1 Heatsinking WSON Package The junction-to-ambient thermal resistance for the WSON package is dependent on how much PCB copper is present to conduct heat away from the device. The LP38502SD-ADJ evaluation board (980600046-100) was tested and gave a result of about 52.5C/W with a power dissipation of 1 W and no external airflow. This evaluation board is a two layer board using two ounce copper, and the copper area on topside for heatsinking is approximately two square inches. Multiple vias under the DAP also thermally connect to the backside layer which has about three square inches of copper dedicated to heatsinking. With four thermal vias directly under the DAP to the first copper plane, the modeling predicts a RJA of 52.5C/W. Adding a dog-bone copper area with four additional thermal vias in the dog-bone area to the first copper plane can improve RJA to 45C/W. 18 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 Layout Examples (continued) See Application Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages (SNVA183) for additional thermal considerations for printed circuit board layouts. Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ Submit Documentation Feedback 19 LP38500-ADJ, LP38502-ADJ SNVS539H - NOVEMBER 2007 - REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation Application Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages (SNVA183). 11.1.2 Related Links Table 2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LP38500-ADJ Click here Click here Click here Click here Click here LP38502-ADJ Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 2007-2015, Texas Instruments Incorporated Product Folder Links: LP38500-ADJ LP38502-ADJ PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP38500ASD-ADJ/NOPB ACTIVE WSON NGS 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LKUA LP38500ASDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LKUA LP38500ATJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LP38500 ATJ-ADJ LP38500SD-ADJ/NOPB ACTIVE WSON NGS 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LP38500SDE-ADJ/NOPB ACTIVE WSON NGS 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LP38500SDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKUB LP38500TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38500 TJ-ADJ LP38500TS-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38500 TS-ADJ LP38500TSX-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38500 TS-ADJ LP38502ASD-ADJ/NOPB ACTIVE WSON NGS 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LKVA LP38502ASDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LKVA LP38502ATJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38502A TJ-ADJ LP38502SD-ADJ/NOPB ACTIVE WSON NGS 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LKVB LP38502SDE-ADJ/NOPB ACTIVE WSON NGS 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LP38502SDX-ADJ/NOPB ACTIVE WSON NGS 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKVB LP38502TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38502 TJ-ADJ LP38502TS-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38502 TS-ADJ Addendum-Page 1 -40 to 125 LKUB LKUB LKVB Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Sep-2015 Status (1) LP38502TSX-ADJ/NOPB ACTIVE Package Type Package Pins Package Drawing Qty DDPAK/ TO-263 KTT 5 500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR Op Temp (C) Device Marking (4/5) -40 to 125 LP38502 TS-ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP38500ASD-ADJ/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500ASDX-ADJ/NOP B WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2 LP38500SD-ADJ/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500SDE-ADJ/NOPB WSON NGS 8 250 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500SDX-ADJ/NOPB WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2 LP38500TSX-ADJ/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP38502ASD-ADJ/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38502ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2 LP38502SD-ADJ/NOPB WSON NGS 8 1000 180.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38502SDE-ADJ/NOPB WSON NGS 8 250 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38502SDX-ADJ/NOPB WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38502TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2 LP38502TSX-ADJ/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38500ASD-ADJ/NOPB WSON NGS 8 1000 210.0 185.0 35.0 LP38500ASDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0 LP38500ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0 LP38500SD-ADJ/NOPB WSON NGS 8 1000 210.0 185.0 35.0 LP38500SDE-ADJ/NOPB WSON NGS 8 250 210.0 185.0 35.0 LP38500SDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0 LP38500TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0 LP38500TSX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP38502ASD-ADJ/NOPB WSON NGS 8 1000 210.0 185.0 35.0 LP38502ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0 LP38502SD-ADJ/NOPB WSON NGS 8 1000 203.0 203.0 35.0 LP38502SDE-ADJ/NOPB WSON NGS 8 250 210.0 185.0 35.0 LP38502SDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0 LP38502TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0 LP38502TSX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDQ0005A TJ5A (Rev F) www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com PACKAGE OUTLINE NGS0008C WSON - 0.8 mm max height SCALE 5.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 B A PIN 1 INDEX AREA 2.6 2.4 C 0.8 0.7 SEATING PLANE 0.08 C 1.6 0.1 (0.1) TYP SYMM EXPOSED THERMAL PAD 0.05 0.00 5 4 SYMM 9 2X 1.5 1.5 0.1 1 8 6X 0.5 8X PIN 1 ID 8X 0.5 0.3 0.3 0.2 0.1 0.05 C A B C 4214924/A 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NGS0008C WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.6) SYMM 8X (0.6) 8 1 8X (0.25) (0.5) 9 SYMM (1.5) 6X (0.5) 4 (R0.05) TYP 5 ( 0.2) VIA TYP (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214924/A 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NGS0008C WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 8X (0.6) SYMM METAL TYP 8 1 8X (0.25) 9 SYMM (1.38) 6X (0.5) 4 5 (R0.05) TYP (1.47) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 9: 82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4214924/A 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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