CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 D D D D D D D TSSOP PW PACKAGE (TOP VIEW) General-Purpose and PCI-X 1:4 Clock Buffer Operating Frequency: 0 MHz to 140 MHz Low Output Skew: <100 ps Distributes One Clock Input to One Bank of Four Outputs Output Enable Control That Drives Outputs Low When OE Is Low Operates From Single 3.3-V Supply 8-Pin TSSOP Package 1 2 3 4 CLKIN OE 1Y0 GND 8 7 6 5 1Y3 1Y2 VDD3.3V 1Y1 description The CDCV304 is a high-performance, low-skew, general-purpose and PCI-X clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V. The CDCV304 is characterized for operation from -40C to 85C for automotive and industrial applications. FUNCTION TABLE INPUTS OUTPUT CLKIN OE 1Y (0:3) L H L H L L H H L L L H functional block diagram OE CLKIN 2 Logic Control 3 1 5 7 8 1Y0 1Y1 1Y2 1Y3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 Terminal Functions TERMINAL NAME I/O NO. 1Y[0-3] 3, 5, 7, 8 CLKIN GND DESCRIPTION O Buffered output clocks 1 I Input reference frequency 4 Power OE 2 I VDD3.3V 6 Power Ground Outputs enable control 3.3-V supply absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.3 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230.5C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions Supply voltage, VDD High-level input voltage, VIH MIN NOM MAX 3 3.3 3.6 0.7xVDD V V Low-level input voltage, VIL Input voltage, VI UNIT 0.3xVDD VDD 0 V V High-level output current, IOH -24 mA Low-level output current, IOL 24 mA 85 C Operating free-air temperature, TA -40 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN fclk 2 Clock frequency 0 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 NOM MAX UNIT 140 MHz CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input voltage VOH High-level output voltage VDD = 3 V, II = -18 mA VDD = min to max, IOH = -1 mA VDD = 3 V, IOH = -24 mA Low-level output voltage VDD = 3 V, IOH = -12 mA VDD = min to max, IOL = 1 mA VDD = 3 V, IOL = 24 mA VOL VDD = 3 V, VDD = 3 V, IOL = 12 mA VO = 1 V VDD = 3.3 V, VDD = 3 V, VO = 1.65 V VO = 2 V VO = 1.65 V IOH High level output current High-level IOL Low level output current Low-level II IDD Input current VDD = 3.3 V, VI = VO or VDD Dynamic current, See Figure 5 f = 67 MHz Ci Input capacitance VDD = 3.3 V, VDD = 3.3 V, Co Output capacitance All typical values are at respective nominal VDD and 25C. MIN TYP MAX UNIT -1.2 V VDD-0.2 2 V 2.4 0.2 0.8 V 0.55 -50 mA -55 60 mA 70 VI = 0 V or VDD VI = 0 V or VDD 5 A 37 mA 3 pF 3.2 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 10 pF, VDD = 3.3 V 0.3 V (see Note 6 and Figures 1 and 2) PARAMETER tPLH tPHL High-to-low propagation delay tsk(o) tsk(p) Output skew (see Note 4) tsk(pr) tsk(pp) Process skew Thi h high CLK high time, time See Figure 4 Tllow CLK low time time, See Figure 4 Low-to-high propagation delay Pulse skew TEST CONDITIONS See Figures 1 and 2 MIN TYP MAX 1.8 2.5 3 ns 1.8 2.4 3 ns 50 100 ps 150 ps 0.2 0.3 ns 0.25 0.4 ns VIH = VDD, VIL = 0 V Part-to-part skew 66 MHz 6 140 MHz 3 66 MHz 6 140 MHz 3 tr Output rise slew rate 0.2VDD to 0.6VDD tf Output fall slew rate 0.6VDD to 0.2VDD All typical values are at respective nominal VDD. This symbol is according to PCI-X terminology. NOTE 4: The tsk(o) specification is only valid for equal loading of all outputs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT ns ns 1.5 2.7 4 V/ns 1.5 2.7 4 V/ns 3 CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 PARAMETER MEASUREMENT INFORMATION VDD 140 Yn 140 10 pF Figure 1. Test Load Circuit VDD 50% VDD CLKIN 0V tPLH tPHL 0.6 VDD 50% VDD 0.2 VDD 1Y0 - 1Y3 VOH 0.6 VDD 50% VDD 0.2 VDD tr VOL tf Figure 2. Voltage Thresholds for Propagation Delay (tpd) Measurements 50% VDD Any Y 50% VDD Any Y tsk(0) Figure 3. Output Skew tcyc PARAMETER VIH(Min) VIL(Max) Vtest VALUE 0.5 VDD 0.35 VDD UNIT V 0.4 VDD V V thigh 0.6 VDD VIH(Min) tlow Vtest VIL(Max) 0.2 VDD 0.4 VDD Peak to Peak (Minimum) NOTE: All parameters in Figure 4 are according to PCI-X 1.0 specifications. Figure 4. Clock Waveform 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 PARAMETER MEASUREMENT INFORMATION SUPPLY CURRENT vs FREQUENCY 60 I CC - Supply Current - mA VDD = 3.6 V TA = 85C 50 40 30 20 0 20 40 60 80 100 120 140 160 f - Frequency - MHz Figure 5 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT VOH - High-Level Output Voltage - V 3.5 3.0 VDD = 3.3 V TA = 25C 2.5 2.0 1.5 1.0 0.5 0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 IOH - High-Level Output Current - mA Figure 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 PARAMETER MEASUREMENT INFORMATION LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VOL - Low-Level Output Voltage - V 3.5 3.0 VDD = 3.3 V TA = 25C 2.5 2.0 1.5 1.0 0.5 0 -20 0 20 40 60 80 IOL - Low-Level Output Current - mA Figure 7 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 100 120 CDCV304 140-MHz PCI-X CLOCK BUFFER SCAS643B - SEPTEMBER 2000 REVISED JULY 2002 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCV304PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCV304PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCV304PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCV304PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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