Single-Channel, 16-Bit Current and Voltage Output DAC with Dynamic Power Control and HART Connectivity AD5758 Data Sheet FEATURES 16-bit resolution and monotonicity DPC for thermal management Current/voltage output available on a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, 0 mA to 24 mA, 20 mA, 24 mA, -1 mA to +22 mA Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, 5 V, and 10 V User-programmable offset and gain Advanced on-chip diagnostics, including a 12-bit ADC On-chip reference Robust architecture, including output fault protection EMC test standards: IEC 61000-4-6 conducted immunity (10 V, Class A) IEC 61000-4-3 radiated immunity (20 V/m, Class A) IEC 61000-4-2 ESD (6 kV contact, Class B) IEC 61000-4-4 electrical fast transient (EFT) (4 kV, Class B) IEC 61000-4-5 surge (4 kV, Class B) 32-lead, 5 mm x 5 mm LFCSP -40C to +115C temperature range converter, optimized for minimum on-chip power dissipation. The CHART pin enables a HART(R) signal to be coupled onto the current output. The device uses a versatile 4-wire serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPITM, MICROWIRETM, DSP, and microcontroller interface standards. The interface also features an optional SPI cyclic redundancy check (CRC) and a watchdog timer (WDT). The AD5758 offers improved diagnostic features from its predecessors, such as an integrated 12-bit diagnostic analog-to-digital converter (ADC). Additional robustness is provided by the inclusion of a line protector on the VIOUT, +VSENSE, and -VSENSE pins. When used with its companion power management unit (PMU)/isolator (ADP1031), the AD5758 is capable of enabling customers to develop an eight channel to channel isolated analog output module with less than 2 W power dissipation, while meeting CISPR 11 Class B. PRODUCT HIGHLIGHTS 1. APPLICATIONS Process control Actuator control Channel isolated analog outputs Programmable logic controller (PLC) and distributed control systems (DCS) applications HART network connectivity GENERAL DESCRIPTION The AD5758 is a single-channel, voltage and current output digital-to-analog converter (DAC) that operates with a power supply range from -33 V (minimum) on AVSS to +33 V (maximum) on AVDD1 with a maximum operating voltage between the two rails of 60 V. On-chip dynamic power control (DPC) minimizes package power dissipation, which is achieved by regulating the supply voltage (VDPC+) to the VIOUT output driver circuitry from 5 V to 27 V using a buck dc-to-dc Rev. B 2. 3. 4. DPC, using an integrated buck dc-to-dc converter for thermal management. When used with the ADP1031, the AD5758 enables eight channel to channel isolated outputs at <2 W dissipated power. Range of advanced diagnostic features, including an integrated ADC for high reliability. Highly robust with output protection from miswire events (38 V). HART compliant. COMPANION PRODUCTS Product Family: AD5755-1, AD5422, AD5753, AD5423 Integrated PMU/Isolation: ADP1031 HART Modem: AD5700, AD5700-1 External References: ADR431, ADR3425, ADR4525 Digital Isolators: ADuM142D, ADuM141D Power: LT8300, ADP2360, ADM6339, ADP1031 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5758 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Output ........................................................................... 36 Applications ...................................................................................... 1 Fault Protection .......................................................................... 36 General Description ......................................................................... 1 Current Output .......................................................................... 36 Product Highlights ........................................................................... 1 HART Connectivity ................................................................... 37 Companion Products ....................................................................... 1 Digital Slew Rate Control .......................................................... 37 Revision History ............................................................................... 2 AD5758 Address Pins ................................................................ 37 Functional Block Diagram .............................................................. 4 Watchdog Timer (WDT) .......................................................... 39 Specifications .................................................................................... 5 User Digital Offset and Gain Control ..................................... 39 AC Performance Characteristics .............................................. 10 DAC Output Update and Data Integrity Diagnostics .......... 40 Timing Characteristics .............................................................. 11 Use of Key Codes ....................................................................... 41 Absolute Maximum Ratings ......................................................... 14 Software Reset ............................................................................. 41 Thermal Resistance .................................................................... 14 Calibration Memory CRC......................................................... 41 ESD Caution................................................................................ 14 Internal Oscillator Diagnostics ................................................ 42 Pin Configuration and Function Descriptions .......................... 15 Sticky Diagnostic Results Bits .................................................. 42 Typical Performance Characteristics ........................................... 17 Background Supply and Temperature Monitoring .............. 42 Voltage Output ........................................................................... 17 Output Fault................................................................................ 42 Current Outputs ......................................................................... 21 ADC Monitoring ........................................................................ 43 DC-to-DC Block ......................................................................... 26 Register Map ................................................................................... 46 Reference ..................................................................................... 27 Writing to Registers ................................................................... 46 General ......................................................................................... 28 Reading from Registers ............................................................. 47 Terminology .................................................................................... 29 Programming Sequence to Enable the Output ...................... 50 Theory of Operation ...................................................................... 31 Register Details ........................................................................... 52 DAC Architecture ...................................................................... 31 Applications Information ............................................................. 67 Serial Interface ............................................................................ 31 Example Module Power Calculation ....................................... 67 Power-On State of the AD5758 ................................................ 32 Driving Inductive Loads ........................................................... 68 Power Supply Considerations .................................................. 32 Electromagnetic Compatibility (EMC) Considerations ....... 68 Device Features and Diagnostics.................................................. 34 Outline Dimensions ....................................................................... 69 Power Dissipation Control ....................................................... 34 Ordering Guide .......................................................................... 69 Interdie 3-Wire Interface .......................................................... 35 REVISION HISTORY 3/2020--Rev. A to Rev. B Changes to Companion Products Section .................................... 1 Changes to AVSS to AGND, DGND Parameter, Table 4 .......... 14 Changes to Table 6 ......................................................................... 16 Changes to Figure 29 ..................................................................... 20 Changes to Figure 35 ..................................................................... 21 Moved Figure 36; Renumered Sequentially ................................ 21 Changes to Figure 37 to Figure 42 ............................................... 22 Changes to Figure 56 ..................................................................... 25 Changes to Terminology Section ................................................. 29 Changes to 3-Wire Interface Diagnostics Section, Voltage Output Amplifier and VSENSE Functionality Section, and Figure 78...... 36 Changes to Figure 90 ..................................................................... 51 Changes to Table 25 ....................................................................... 52 Changes to the Software LDAC Register Section ...................... 55 Changes to Table 35 ....................................................................... 56 Changes to Figure 91 ..................................................................... 68 Added Electromagnetic Compatibility (EMC) Considerations Section .............................................................................................. 68 Rev. B | Page 2 of 69 Data Sheet AD5758 3/2019--Rev. 0 to Rev. A Changes to Features Section, General Description Section, Product Highlights Section, and Companion Products Section................................................................................................. 1 Changes to Figure 1 .......................................................................... 4 Changes to Specifications Section and Table 1 ............................. 5 Added Endnote 4, Table 1; Renumbered Sequentially ................ 7 Changes to AC Performance Characteristics Section and Digital-to-Analog Glitch Energy Parameter, Table 2 ................10 Changes to Timing Characteristics Section ................................11 Changes to Absolute Maximum Ratings Section and Table 4...............................................................................................14 Added Endnote 2 and Endnote 3, Table 4 ...................................14 Change to Figure 6 ..........................................................................15 Changes to Table 6 ..........................................................................16 Change to Figure 28 ........................................................................20 Changes to Figure 34 and Figure 35 .............................................21 Changes to Figure 37, Figure 38, Figure 39, Figure 40, Figure 41, and Figure 42 ...................................................................................22 Changes to Figure 52 and Figure 54 .............................................24 Added Figure 53; Renumbered Sequentially ...............................24 Deleted Figure 71; Renumbered Sequentially .............................28 Changes to Theory of Operation Section and Table 7 ...............31 Changes to Power-On State of the AD5758 Section ..................32 Change to AVDD1 Considerations Section ...................................32 Change to AVSS Considerations Section ......................................33 Changes to Figure 77, Table 10, DPC Current Mode Section, and PPC Current Mode Section ................................................................... 34 Changes to Figure 78 and Fault Protection Section ...................36 Deleted Internal Current Output Monitor Section and Figure 79; Renumbered Sequentially............................................37 Changes to Figure 79, Digital Slew Rate Control Section, AD5758 Address Pins Section, SPI Interface Diagnostics Section, and Table 12 ......................................................................37 Changes to Watchdog Timer (WDT) Section ............................39 Change to DAC Output Update and Data Integrity Diagnostics Section...............................................................................................40 Changes to Use of Key Codes Section ..........................................41 Changes to Background Supply and Temperature Monitoring Section...............................................................................................42 Changes to Table 17, ADC Monitoring Section, and Table 18 ............................................................................................ 43 Changes to Figure 84 ...................................................................... 44 Changes to ADC Configuration Section, Table 19, and ADC Conversion Timing Section ........................................................... 45 Deleted Key Sequencing (Command 010) Section, Automatic Sequencing (Command 011) Section, Single Immediate Conversion (Command 100) Section, Single Key Conversion (Command 101) Section, Sequencing Mode Setup Section ..... 45 Deleted Table 20; Renumbered Sequentially .............................. 45 Deleted Figure 86 ............................................................................ 46 Changes to Table 20 and Table 21 ................................................ 46 Changes to Table 23........................................................................ 47 Changes to Autostatus Readback Mode Section ........................ 48 Changes to Figure 88 ...................................................................... 49 Changes to Programming Sequence to Enable the Output Section .............................................................................................. 50 Changes to Software LDAC Register Section ............................. 55 Changes to Table 34 and Table 35 ................................................ 56 Changes to Table 36........................................................................ 57 Changes to DC-to-DC Configuration 1 Register Section, Table 37, and Table 38.................................................................... 58 Changes to Table 41........................................................................ 61 Changes to Table 42........................................................................ 62 Changes to Analog Diagnostic Results Register Section and Table 45 ............................................................................................ 64 Changes to Table 47........................................................................ 65 Changes to Power Calculation Methodology (RLOAD = 1 k) Section and Power Calculation Methodology (RLOAD = 0 k) Section .............................................................................................. 67 Added Figure 91 .............................................................................. 68 Changes to Driving Inductive Loads Section.............................. 68 Updated Outline Dimensions ....................................................... 69 Changes to Ordering Guide .......................................................... 69 Deleted Figure 93 ............................................................................ 70 Deleted Figure 94 ............................................................................ 71 5/2018--Revision 0: Initial Version Rev. B | Page 3 of 69 AD5758 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD2 VLDO AVDD1 AGND MCLK 10MHz POWER MANAGEMENT BLOCK POWER-ON RESET VDPC+ SW+ CALIBRATION MEMORY DC-TO-DC CONVERTER VLOGIC DGND CLKOUT AD0 AD1 RESET LDAC SCLK SDI SYNC SDO DIGITAL BLOCK DYNAMIC POWER CONTROL 3-WIRE INTERFACE DATA AND CONTROL REGISTERS WATCHDOG TIMER PGND1 16 DAC REG VDPC+ 16 16-BIT DAC - IOUT RANGE SCALING RB RA RSET IOUT VX USER GAIN USER OFFSET HART_EN CHART FAULT V DPC+ STATUS REGISTER REFIN VOUT RANGE SCALING REFERENCE BUFFERS +VSENSE VOUT VI OUT -VSENSE VREF 12-BIT ADC CCOMP ANALOG DIAGNOSTICS AVSS Figure 1. Rev. B | Page 4 of 69 11840-002 REFOUT REFGND TEMPERATURE SENSOR Data Sheet AD5758 SPECIFICATIONS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = -15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 k, CL = 220 pF; current output: RL = 300 ; all specifications at TA = -40C to +115C, TJ < 125C, unless otherwise noted. Table 1. Parameter VOLTAGE OUTPUT Output Voltage Ranges (VOUT) Output Voltage Overranges Output Voltage Offset Ranges Resolution VOLTAGE OUTPUT ACCURACY Total Unadjusted Error (TUE) TUE Long-Term Stability 1 Output Drift Relative Accuracy (INL) Differential Nonlinearity (DNL) Zero-Scale Error Zero-Scale Error Temperature Coefficient (TC) 2 Bipolar Zero Error Bipolar Zero Error TC2 Offset Error Offset Error TC2 Gain Error Gain Error TC2 Full-Scale Error Full-Scale Error TC2 VOLTAGE OUTPUT CHARACTERISTICS Headroom Min Typ 0 0 -5 -10 0 0 -6 -12 -0.3 -0.4 16 Max Unit Test Conditions/Comments 5 10 +5 +10 6 12 +6 +12 +5.7 +11.6 V V V V V V V V V V Bits Trimmed VOUT ranges Untrimmed overranges Untrimmed negatively offset ranges Loaded and unloaded, accuracy specifications refer to trimmed VOUT ranges only, unless otherwise noted -0.05 -0.01 +0.05 +0.01 15 0.35 -0.006 -1 -0.02 5 V, 10 V 5 V, 10 V 2 V Footroom 2 V Minimum voltage required between VIOUT and VDPC+ supply Minimum voltage required between VIOUT and AVSS supply Short-Circuit Current Load2 Capacitive Load Stability2 1 -0.02 -0.02 -0.02 +0.001 0.3 0.002 0.3 0.001 0.3 0.001 0.3 +0.015 TA = 25C Drift after 1000 hours, TJ = 150C Output drift All ranges Guaranteed monotonic, all ranges % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C DC Output Impedance DC Power Supply Rejection Ratio (PSRR) VOUT/-VSENSE Common-Mode Rejection Ration (CMRR) -0.015 0.002 0.3 2 +0.006 +1 +0.02 % FSR % FSR ppm FSR ppm FSR/C % FSR LSB % FSR ppm FSR/C +0.02 +0.02 +0.02 16 10 2 mA k nF F 7 10 m V/V 10 V/V Rev. B | Page 5 of 69 For specified performance External compensation capacitor of 220 pF connected Error in VOUT voltage due to changes in -VSENSE voltage AD5758 Parameter CURRENT OUTPUT Output Current Ranges (IOUT) Resolution CURRENT OUTPUT ACCURACY (EXTERNAL RSET) 3 Unipolar Ranges TUE TUE Long-Term Stability Output Drift INL DNL Zero-Scale Error Zero-Scale TC2 Offset Error Offset Error TC2 Gain Error Gain Error TC2 Full-Scale Error Full-Scale Error TC2 Bipolar Ranges Total Unadjusted Error (TUE) TUE Long-Term Stability1 Output Drift INL DNL Zero-Scale Error Zero-Scale TC2 Bipolar Zero Error Bipolar Zero Error TC2 Offset Error Offset Error TC2 Gain Error Gain Error TC2 Full-Scale Error Full-Scale Error TC2 CURRENT OUTPUT ACCURACY (INTERNAL RSET) Unipolar Ranges TUE TUE Long-Term Stability1 Output Drift INL DNL Zero-Scale Error Data Sheet Min Typ 0 0 4 -20 -24 -1 16 Max Unit 24 20 20 +20 +24 +22 mA mA mA mA mA mA Bits Test Conditions/Comments Assumes ideal 13.7 k resistor 4 mA to 20 mA, 0 mA to 20 mA, and 0 mA to 24 mA ranges -0.06 -0.012 +0.06 +0.012 125 3 -0.006 -1 -0.03 -0.03 -0.05 -0.05 0.002 0.5 0.001 0.7 0.001 3 0.001 3 7 +0.006 +1 +0.03 +0.03 +0.05 +0.05 % FSR % FSR ppm FSR ppm FSR/C % FSR LSB % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C TA = 25C Drift after 1000 hours, TJ = 150C Guaranteed monotonic 20 mA, 24 mA, and -1 mA to +22 mA ranges -0.08 -0.014 +0.08 +0.014 125 12 -0.01 -1 -0.04 -0.02 -0.06 -0.08 -0.08 0.002 0.9 0.002 0.4 0.002 0.9 0.002 4 0.002 3 15.5 +0.01 +1 +0.04 +0.02 +0.06 +0.08 +0.08 % FSR % FSR ppm FSR ppm FSR/C % FSR LSB % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C TA = 25C Drift after 1000 hours, TJ = 150C Guaranteed monotonic 4 mA to 20 mA, 0 mA to 20 mA, and 0 mA to 24 mA ranges -0.18 +0.18 380 9 -0.01 -1 -0.06 0.002 21 +0.01 +1 +0.06 % FSR ppm FSR ppm FSR/C % FSR LSB % FSR Rev. B | Page 6 of 69 Drift after 1000 hours, TJ = 150C Output drift Guaranteed monotonic Data Sheet Parameter Zero-Scale TC2 Offset Error Offset Error TC2 Gain Error Gain Error TC2 Full-Scale Error Full-Scale Error TC2 Bipolar Ranges TUE TUE Long-Term Stability1 Output Drift INL DNL Zero-Scale Error Zero-Scale TC2 Bipolar Zero Error Bipolar Zero Error TC2 Offset Error Offset Error TC2 Gain Error Gain Error TC2 Full-Scale Error Full-Scale Error TC2 CURRENT OUTPUT CHARACTERISTICS Headroom Footroom AD5758 Min -0.05 -0.14 -0.18 Typ 3 0.001 3 0.003 12 0.005 14 Reference TC2 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Capacitive Load2 Load Current Short-Circuit Current Line Regulation Load Regulation Thermal Hysteresis2 +0.05 +0.14 +0.18 Unit ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C Test Conditions/Comments 20 mA, 24 mA, and -1 mA to +22 mA ranges -0.16 +0.16 380 6 -0.01 -1 -0.06 -0.02 -0.07 -0.16 -0.16 0.002 4 0.002 0.3 0.001 4 0.003 12 0.005 11 21 +0.01 +1 +0.06 +0.02 +0.07 +0.16 0.16 % FSR ppm FSR ppm FSR/C % FSR LSB % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C 2.3 V 2.35/0 V Resistive Load2 Output Impedance DC PSRR REFERENCE INPUT/OUTPUT Reference Input Reference Input Voltage 4 DC Input Impedance Reference Output Output Voltage Max 1000 Drift after 1000 hours, TJ = 150C Output drift Guaranteed monotonic Minimum voltage required between VIOUT and VDPC+ supply Minimum voltage required between VIOUT and AVSS supply and unipolar ranges do not require any footroom The dc-to-dc converter is characterized with a maximum load of 1 k, chosen such that headroom/footroom compliance is not exceeded Midscale output 100 0.1 M A/V 2.5 120 V M For specified performance 55 2.495 2.5 2.505 V TA = 25C (including drift after 1000 hours at TJ = 150C) +10 ppm/C V p-p -10 7 80 1000 3 5 1 80 150 nV/Hz nF mA mA ppm/V ppm/mA ppm Rev. B | Page 7 of 69 At 10 kHz AD5758 Parameter VLDO OUTPUT Output Voltage Output Voltage TC2 Output Voltage Accuracy Externally Available Current Short-Circuit Current Load Regulation Capacitive Load DC-TO-DC Start-Up Time Switch Peak Current Limit2 Oscillator Oscillator Frequency (fSW) Minimum Duty Cycle Current Output DPC Mode VDPC+ Voltage Range Data Sheet Min VDPC+ Voltage Accuracy Voltage Output DPC Mode VDPC+ Voltage Range VDPC+ Voltage Accuracy Unit Test Conditions/Comments 55 0.8 0.1 V ppm/C % mA mA mV/mA F Recommended operation 1.25 ms -2 +2 30 150 400 500 5 4.95 mA V 2.5 V 5 25.677 V -500 +500 mV 25 V +500 mV 2.3 5 15 -500 User-programmable in 50 mA steps via the DCDC_CONFIG2 register kHz % 27 VIOUT LINE PROTECTOR On Resistance (RON) Overvoltage Response Time (tRESPONSE) Overvoltage Leakage Current ADC Resolution Total Error Conversion Time2 DIGITAL INPUTS Input Voltage 3 V VLOGIC 5.5 V High, VIH Low, VIL 1.71 V VLOGIC < 3 V Max 3.3 25 VDPC+ Headroom Current Output PPC Mode VDPC+ Voltage Range Typ Current output dynamic power control mode Assuming sufficient supply margin between AVDD1 and VDPC+; see the Power Dissipation Control section for further details; maximum operating range of |VDPC+ to AVSS| = 50 V Typical voltage headroom between VIOUT and VDPC+; only applicable when dc-to-dc converter is in regulation (that is, load is sufficiently high) PPC mode Assuming sufficient supply margin between AVDD1 and VDPC+; see the Power Dissipation Control section for further details; maximum operating range of |VDPC+ to AVSS| = 50 V Only applicable when dc-to-dc is operating in regulation (that is, load is sufficiently high) Voltage output dynamic power control mode 5 V = -VSENSE (MIN) + 15 V; 25 V = -VSENSE (MAX) + 15 V; assuming sufficient supply margin between AVDD1 and VDPC+; see the Power Dissipation Control section for further details; maximum operating range of |VDPC+ to AVSS| = 50 V Only applicable when dc-to-dc is operating in regulation (that is, load sufficiently high) 12 250 ns TA = 25C 100 A Line protector fault detect block sinks current for a positive fault and sources current for a negative fault 12 0.3 100 Bits % FSR s 0.7 x VLOGIC 0.3 x VLOGIC V V Rev. B | Page 8 of 69 Table 18 lists all ADC input nodes Data Sheet Parameter High, VIH Low, VIL Input Current Pin Capacitance2 DIGITAL OUTPUTS SDO Output Voltage Low, VOL High, VOH High Impedance Leakage Current High Impedance Output Capacitance2 FAULT Output Voltage Low, VOL AD5758 Min 0.8 x VLOGIC Typ Max 0.2 x VLOGIC +1.5 -1.5 2.4 pF 0.4 VLOGIC - 0.2 -1 Unit V V A +1 2.2 V V A Test Conditions/Comments Per pin, internal pull-down on SCLK, SDI, RESET, and LDAC; internal pull-up on SYNC Per pin Sinking 200 A Sourcing 200 A pF 0.4 V V V 10 k pull-up resistor to VLOGIC At 2.5 mA 10 k pull-up resistor to VLOGIC 7 33 V AVDD2 5 33 V AVSS5 -33 0 V Maximum operating range of |AVDD1 to AVSS| = 60 V Maximum operating range of |AVDD2 to AVSS| = 50 V Maximum operating range of |AVDD1 to AVSS| = 60 V; for bipolar output ranges, VOUT/IOUT headroom must be obeyed when calculating AVSS maximum; for unipolar current output ranges, AVSS maximum = 0 V; for unipolar voltage output ranges, AVSS maximum = -2 V 1.71 5.5 V 0.05 0.11 mA 0.05 0.11 mA 3.3 3.6 mA 2.9 3.1 mA 0.01 1.3 1 3.15 mA mA mA mA mA mA mA 0.6 High, VOH POWER REQUIREMENTS Supply Voltages AVDD1 5 VLOGIC Supply Quiescent Currents5 AIDD1 VLOGIC - 0.05 AIDD2 AISS ILOGIC IDPC+ -1.4 -3.15 -0.26 -1.1 -2.4 -0.23 1.0 0.8 2.4 Rev. B | Page 9 of 69 Quiescent current, assuming no load current Voltage output mode, dc-to-dc converter enabled but not active Current output mode, dc-to-dc converter enabled but not active Voltage output mode, dc-to-dc converter enabled but not active Current output mode, dc-to-dc converter enabled but not active Voltage output mode Bipolar current output mode Unipolar current output mode VIH = VLOGIC, VIL = DGND Voltage output mode Unipolar current output mode Bipolar current output mode AD5758 Parameter Power Dissipation Data Sheet Min Typ Max Unit 103 mW 145 mW 155 mW 200 mW Test Conditions/Comments Power dissipation assuming an ideal power supply and excluding external load power dissipation, current output DPC mode, 0 mA to 20 mA range; see the Example Module Power Calculation section for calculation methodology AVDD1 = 24 V, AVDD2 = 5 V, AVSS = -15 V, RLOAD = 1 k, IOUT = 20 mA AVDD1 = 24 V, AVDD2 = 5 V, AVSS = -15 V, RLOAD = 0 , IOUT = 20 mA AVDD1 = AVDD2 = 24 V, AVSS = -15 V, RLOAD = 1 k, IOUT = 20 mA AVDD1 = AVDD2 = 24 V, AVSS = -15 V, RLOAD = 0 , IOUT = 20 mA The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. Guaranteed by design and characterization; not production tested. 3 See the Current Output section for more information about the internal and external RSET resistors. 4 The AD5758 is factory calibrated with an external 2.5 V reference connected to REFIN. 5 Production tested to AVDD1 maximum = 30 V and AVSS minimum = -30 V. 1 2 AC PERFORMANCE CHARACTERISTICS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = -15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 k, CL = 220 pF; current output: RL = 300 ; all specifications at TA = -40C to +115C, TJ < 125C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE 1 Voltage Output Output Voltage Settling Time Min Typ 6 12 Slew Rate Power-On Glitch Energy Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Feedthrough Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density AC PSRR Max 20 20 15 Unit Test Conditions/Comments Output voltage settling time specifications also apply for dcto-dc converter enabled 5 V step to 0.03% FSR, 0 V to 5 V range 10 V step to 0.03% FSR, 0 V to 10 V range 100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V range 0 V to 10 V range, digital slew rate control disabled 3 25 5 25 2 0.2 s s s V/s nV-sec nV-sec mV nV-sec LSB p-p 185 70 nV/Hz dB Measured at 10 kHz, midscale output, 0 V to 10 V range 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage 15 15 s s 200 s 0.2 LSB p-p To 0.1% FSR (0 mA to 24 mA), dc-to-dc converter disabled PPC mode, dc-to-dc converter enabled, dc-to-dc current limit = 150 mA DPC mode, dc-to-dc converter enabled; external inductor and capacitor components as described in Table 10, dc-to-dc current limit = 150 mA. 16-bit LSB, 0 mA to 24 mA range 0.8 80 nA/Hz dB 16-bit LSB, 0 V to 10 V range Current Output Output Current Settling Time Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density AC PSRR 1 Measured at 10 kHz, midscale output, 0 mA to 24 mA range 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage Guaranteed by design and characterization; not production tested. Rev. B | Page 10 of 69 Data Sheet AD5758 TIMING CHARACTERISTICS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = -15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 k, CL = 220 pF; current output: RL = 300 ; all specifications at TA = -40C to +115C, TJ < 125C, unless otherwise noted. Table 3. Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 1 2 3 1.71 V VLOGIC < 3 V 33 120 16 60 16 60 10 3 V VLOGIC 5.5 V 20 66 10 33 10 33 10 Unit ns min ns min ns min ns min ns min ns min ns min 33 33 ns min 10 500 10 500 ns min ns min 1.5 500 1.5 500 s min s min 5 6 750 1.5 250 600 5 6 750 1.5 250 600 ns min ns min ns min s min ns min ns max 2 2 s max See the AC Performance Characteristics section 1.5 1.5 5 5 40 28 100 100 s max s max s min ns max s min Description SCLK cycle time, write operation SCLK cycle time, read operation SCLK high time, write operation SCLK high time, read operation SCLK low time, write operation SCLK low time, read operation SYNC falling edge to SCLK falling edge setup time, write operation SYNC falling edge to SCLK falling edge setup time, read operation 24th/32nd SCLK falling edge to SYNC rising edge SYNC high time (all register writes outside of those listed in this table) SYNC high time (DAC_INPUT register write) SYNC high time (DAC_CONFIG register write, where the Range[3:0] bits change; see the Calibration Memory CRC section) Data setup time Data hold time LDAC falling edge to SYNC rising edge SYNC rising edge to LDAC falling edge LDAC pulse width low LDAC falling edge to DAC output response time, digital slew rate control disabled. LDAC falling edge to DAC output response time, digital slew rate control enabled. DAC output settling time SYNC rising edge to DAC output response time (LDAC = 0) RESET pulse width SCLK rising edge to SDO valid RESET rising edge to 1st SCLK falling edge after SYNC falling edge (t17 does not appear in the timing diagrams) Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V. tR is rise time. tF is fall time. See Figure 2, Figure 3, Figure 4, and Figure 5. Rev. B | Page 11 of 69 AD5758 Data Sheet Timing Diagrams t1 24 2 1 SCLK t2 t3 t6 t4 t5 SYNC t8 t7 SDI LSB MSB t11 t10 LDAC t11 t9 t13 t12 VIOUT LDAC = 0 t13 t14 VIOUT 11840-003 t15 RESET Figure 2. Serial Interface Timing Diagram SCLK 1 24 1 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t16 Figure 3. Readback Timing Diagram Rev. B | Page 12 of 69 SELECTED REGISTER DATA CLOCKED OUT 11840-004 SDI Data Sheet AD5758 1 24 1 2 SCLK SYNC t8 t7 SDI SDO SDO DISABLED D23 D22 1 0 D21 D20 D19 D18 D17 FAULT PIN DIG DIAG ANA DIAG WDT STATUS ADC BUSY D16 ADC CHN[4] D11 D1 D0 ADC ADC ADC ADC CHN[0] DATA[11] DATA[1] DATA[0] SDO DISABLED 1IF ANY EXTRA SCLK FALLING EDGES ARE RECEIVED AFTER THE 24TH (OR 32ND, IF CRC IS ENABLED) SCLK, BEFORE SYNC RETURNS HIGH, SDO CLOCKS OUT 0. Figure 4. Autostatus Readback Timing Diagram 200A VOH (MIN) OR VOL (MAX) CL 30pF 200A IOH Figure 5. Load Circuit for SDO Timing Diagram Rev. B | Page 13 of 69 11840-006 TO OUTPUT PIN IOL 11840-005 t16 AD5758 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Transient currents of up to 200 mA do not cause silicon controlled rectifier (SCR) latch-up. Table 4. Parameter AVDD1 to AGND, DGND AVSS to AGND, DGND AVDD1 to AVSS AVDD2, VDPC+ to AGND, DGND AVDD2, VDPC+ to AVSS VLOGIC to DGND Digital Inputs to DGND (SCLK, SDI, SYNC, AD0, AD1, RESET, LDAC) Digital Outputs to DGND (FAULT, SDO, CLKOUT) REFIN, REFOUT, VLDO, CHART to AGND RA to AGND RB to AGND VIOUT to AGND +VSENSE to AGND -VSENSE to AGND CCOMP to AGND SW+ to AGND AGND, DGND to REFGND AGND, DGND to PGND1 Industrial Operating Temperature Range (TA)1 Storage Temperature Range Junction Temperature (TJ max) Power Dissipation Lead Temperature Soldering Electrostatic Discharge (ESD) Human Body Model2 Field Induced Charged Device Model3 Rating -0.3 V to +44 V +0.3 V to -35 V -0.3 V to +66 V -0.3 V to +35 V -0.3 V to +55 V -0.3 V to +6 V -0.3 V to VLOGIC + 0.3 V or +6 V (whichever is less) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 5. Thermal Resistance -0.3 V to VLOGIC + 0.3 V or +6 V (whichever is less) -0.3 V to AVDD2 + 0.3 V or +6 V (whichever is less) -0.3 V to +4.5 V -0.3 V to +4.5 V 38 V 38 V 38 V AVSS - 0.3 V to VDPC+ + 0.3 V -0.3 V to AVDD1 + 0.3 V or +33 V (whichever is less) -0.3 V to +0.3 V -0.3 V to +0.3 V -40C to +115C Package Type CP-32-301 1 JA 46 JC 18 Unit C/W Test Condition 1: thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with thermal vias. See JEDEC JESD51. ESD CAUTION -65C to +150C 125C (TJ maximum - TA)/JA JEDEC industry standard J-STD-020 3 kV 1 kV Power dissipated on the chip must be derated to keep the junction temperature below 125C. 2 As per ANSI/ESDA/JEDEC JS-001, all pins. 3 As per ANSI/ESDA/JEDEC JS-002, all pins. 1 Rev. B | Page 14 of 69 Data Sheet AD5758 32 31 30 29 28 27 26 25 PGND1 VDPC+ NIC VIOUT +VSENSE CCOMP -VSENSE AVSS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5758 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 FAULT AD0 AD1 SYNC SDI SCLK CLKOUT LDAC NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. CONNECT THE EXPOSED PAD TO THE POTENTIAL OF THE AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 11840-007 REFIN REFOUT CHART VLDO VLOGIC 9 10 11 12 13 SDO 14 DGND 15 RESET 16 SW+ 1 AVDD1 2 AVDD2 3 NIC 4 AGND 5 REFGND 6 RA 7 RB 8 Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic SW+ AVDD1 AVDD2 NIC AGND REFGND RA 8 RB 9 10 REFIN REFOUT 11 CHART 12 13 14 VLDO VLOGIC SDO 15 16 DGND RESET 17 LDAC 18 CLKOUT Description Switching Output for the DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 77. Positive Analog Supply. The voltage range is from 7 V to 33 V. Positive Low Voltage Analog Supply. The voltage range is from 5 V to 33 V. Not Internally Connected. This pin is not internally connected. Ground Reference Point for the Analog Circuitry. This pin must be connected to 0 V. Ground Reference Point for Internal Reference. This pin must be connected to 0 V. External Current Setting Resistor. An external, precision, low drift 13.7 k current setting resistor can be connected between RA and RB to improve the current output temperature drift performance. It is recommended that the external resistor be placed as close as possible to the AD5758. External Current Setting Resistor. An external, precision, low drift 13.7 k current setting resistor can be connected between RA and RB to improve the current output temperature drift performance. It is recommended that the external resistor be placed as close as possible to the AD5758. External 2.5 V Reference Voltage Input. Internal 2.5 V Reference Voltage Output. REFOUT must be connected to REFIN to use the internal reference. A capacitor between REFOUT and REFGND is not recommended. HART Input Connection. The HART signal must be ac-coupled to this pin. If HART is not being used, leave this pin unconnected. This pin is disconnected from the HART summing node by default and can be connected via the HART_EN bit in the GP_CONFIG1 register. 3.3 V LDO Output Voltage. VLDO must be decoupled to AGND with a 0.1 F capacitor. Digital Supply. The voltage range is from 1.71 V to 5.5 V. VLOGIC must be decoupled to DGND with a 0.1 F capacitor. Serial Data Output. This pin clocks data from the serial register in readback mode. The maximum SCLK speed for readback mode is 15 MHz (depending on the VLOGIC voltage). See Table 3. Digital Ground. Hardware Reset. Active low input. Do not write an SPI command within 100 s of issuing a reset (using the hardware RESET pin or via software). Load DAC. Active low input. This pin updates the DAC_OUTPUT register and, consequently, the DAC output. Do not assert LDAC within the window of 500 ns before the rising edge of SYNC or 1.5 s after the rising edge of SYNC (see Table 3 for the timing specifications). Optional Clock Output Signal (Disabled by Default). This pin is a divided down version of the internal 10 MHz oscillator (MCLK) and is configured in the GP_CONFIG1 register. Rev. B | Page 15 of 69 AD5758 Pin No. 19 Mnemonic SCLK 20 21 SDI SYNC 22 23 24 AD1 AD0 FAULT 25 AVSS 26 -VSENSE 27 CCOMP 28 +VSENSE 29 30 31 VIOUT NIC VDPC+ 32 PGND1 EPAD Data Sheet Description Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. In write mode, this pin operates at clock speeds of up to 50 MHz (depending on the VLOGIC voltage). In read mode, the maximum SCLK speed is 15 MHz (depending on the VLOGIC voltage). See Table 3 for the timing specifications. Serial Data Input. Data must be valid on the falling edge of SCLK. Frame Synchronization Signal for the Serial Interface. Active low input. While SYNC is low, data is transferred in on the falling edge of SCLK. Address Decode 1 for the AD5758. Address Decode 0 for the AD5758. Fault Pin. Active low, open-drain output. This pin is high impedance when no faults are detected and is asserted low when certain faults are detected, for example, an open circuit in current mode, a short circuit in voltage mode, a CRC error, or an overtemperature error (see the Output Fault section). This pin must be connected to VLOGIC with a 10 k pull-up resistor. Negative Analog Supply. The voltage range is from 0 V to -33 V. If using the device solely for unipolar current output purposes, AVSS can be 0 V. For a unipolar voltage output, AVSS (maximum) is -2.5 V. When using bipolar output ranges, VOUT/IOUT headroom must be obeyed when calculating the AVSS maximum, for example, for a 10 V output, the AVSS maximum is -12.5 V. See the AVSS Considerations section for an important note on power supply sequencing. Sense Connection for the Negative Voltage Output Load Connection for VOUT Mode. This pin must stay within 10 V of AGND for specified operation. It is recommended to connect a series 1 k resistor to this pin. If remote sensing is not being used, short this pin to AGND. Optional Compensation Capacitor Connection for the Voltage Output Buffer. Connecting a 220 pF capacitor between this pin and the VIOUT pin allows the voltage output to drive up to 2 F. The addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Positive Voltage Output Load Connection for Voltage Output Mode. It is recommended to connect a series 1 k resistor to this pin. If remote sensing is not being used, short this pin to VIOUT via the series 1 k resistor. Voltage/Current Output Pin. VIOUT is a shared pin, providing either a buffered output voltage or current. Not Internally Connected. This pin is not internally connected. Positive Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect as shown in Figure 77. Power Ground. Exposed Pad. Connect the exposed pad to the potential of the AVSS pin, or, alternatively, it can be left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Rev. B | Page 16 of 69 Data Sheet AD5758 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT 0.0020 +5V RANGE +10V RANGE 5V RANGE 10V RANGE +10V RANGE WITH DCDC ENABLED 0.0015 0.0015 AVDD1 = VDPC+ = 15V AVSS = -15V 1k LOAD TA = 25C 0.0010 INL ERROR (%FSR) 0.0010 INL ERROR (%FSR) AVDD1 = VDPC+ = 15V AVSS = -15V 1k LOAD 0.0005 0 0.0005 +5V RANGE, INL MIN +10V RANGE, INL MIN 5V RANGE, INL MIN 10V RANGE, INL MIN 0 +5V RANGE, INL MAX +10V RANGE, INL MAX 5V RANGE, INL MAX 10V RANGE, INL MAX -0.0005 -0.0005 16384 24576 32768 40960 49152 57344 65536 CODE -0.0015 -40 0.8 AVDD1 = VDPC+ = 15V AVSS = -15V 1k LOAD TA = 25C 0.8 DNL ERROR (LSB) 0.4 0.2 0 -0.2 0.4 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE -1.0 -40 TOTAL UNADJUSTED ERROR (%FSR) 0 -0.002 -0.004 +5V RANGE +10V RANGE 5V RANGE 10V RANGE +10V RANGE WITH DC-TO-DC ENABLED -0.008 -0.010 0 8192 16384 24576 32768 40960 49152 57344 CODE 65536 11840-209 TOTAL UNADJUSTED ERROR (%FSR) 0.008 0.002 -0.006 125 115 Figure 11. DNL Error vs Temperature AVDD1 = VDPC+ = 15V AVSS = -15V 1k LOAD TA = 25C 0.004 25 TEMPERATURE (C) Figure 8. DNL Error vs. DAC Code 0.006 DNL ERROR MAX DNL ERROR MIN AVDD1 = VDPC+ = +15V AVSS = -15V ALL RANGES 0.6 11840-208 DNL ERROR (LSB) 0.6 125 105 Figure 10. INL Error vs. Temperature 1.0 +5V RANGE +10V RANGE 5V RANGE 10V RANGE +10V RANGE WITH DCDC ENABLED 70 TEMPERATURE (C) Figure 7. INL Error vs. DAC Code 1.0 25 11840-211 8192 Figure 9. Total Unadjusted Error vs. DAC Code 0.006 +5V RANGE, TUE MIN +10V RANGE, TUE MIN 5V RANGE, TUE MIN 10V RANGE, TUE MIN +5V RANGE, TUE MAX +10V RANGE, TUE MAX 5V RANGE, TUE MAX 10V RANGE, TUE MAX 0.004 0.002 0 -0.002 AVDD1 = VDPC+ = +15V AVSS = -15V 1k LOAD -0.004 -0.006 -40 25 70 105 TEMPERATURE (C) Figure 12. Total Unadjusted Error vs. Temperature Rev. B | Page 17 of 69 125 11840-212 0 11840-207 -0.0015 11840-210 -0.0010 -0.0010 AD5758 Data Sheet 0.008 0.002 0 -0.002 -0.004 -0.006 AVDD1 = VDPC+ = +15V AVSS = -15V 1k LOAD 70 0 -0.005 -0.010 125 105 TEMPERATURE (C) AVDD1 = VDPC+ = +15V AVSS = -15V 1k LOAD -0.020 -40 0.008 AV DD1 = VDPC+ = +15V AV SS = -15V 1k LOAD 5V RANGE 10V RANGE 5V RANGE 10V RANGE 5V RANGE 10V RANGE ZERO-SCALE ERROR (%FSR) 0.006 0 -0.001 -0.002 -0.003 -0.004 -0.005 0.004 0.002 0 -0.002 -0.004 -0.006 AVDD1 = VDPC+ = +15V AVSS = -15V 1k LOAD -0.008 25 70 105 -0.010 -40 11840-215 -0.006 -40 125 105 Figure 16. Bipolar Zero Error vs. Temperature 0.002 OFFSET ERROR (%FSR) 70 TEMPERATURE (C) Figure 13. Full-Scale Error vs. Temperature 0.001 25 125 TEMPERATURE (C) 105 125 Figure 17. Zero-Scale Error vs. Temperature 0.005 5V RANGE 10V RANGE 5V RANGE 10V RANGE 0.008 70 TEMPERATURE (C) Figure 14. Offset Error vs. Temperature 0.010 25 11840-218 25 0.005 -0.015 11840-214 -0.010 -40 0.010 11840-217 0.004 -0.008 5V RANGE 10V RANGE 0.015 BIPOLAR ZERO ERROR (%FSR) 0.006 FULL-SCALE ERROR (%FSR) 0.020 5V RANGE 10V RANGE 5V RANGE 10V RANGE 0.004 0V TO 10V RANGE, MAX INL 0V TO 10V RANGE, MIN INL 1k LOAD TA = 25C 0.003 INL ERROR (%FSR) 0.004 0.002 0 0.002 0.001 0 -0.001 -0.002 -0.002 -0.003 AV DD1 = VDPC+ = +15V AV SS = -15V 1k LOAD -0.006 -40 25 -0.004 70 105 TEMPERATURE (C) 125 Figure 15. Gain Error vs. Temperature -0.005 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SUPPLY (V) Figure 18. INL Error vs. AVDD1/|AVSS| Supply Rev. B | Page 18 of 69 11840-219 -0.004 11840-216 GAIN ERROR (%FSR) 0.006 Data Sheet AD5758 1.0 15 0.8 10 OUTPUT VOLTAGE (V) 0.4 0.2 0 -0.2 -0.4 -0.6 5 0 -5 -10 SUPPLY (V) -15 11840-220 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 -5 0 Figure 19. DNL Erorr vs. AVDD1/|AVSS| Supply 15 OUTPUT VOLTAGE (V) 0.02 0.01 0 -0.01 -0.02 -0.03 5 0 -5 -10 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SUPPLY (V) -15 -5 Figure 23. Full-Scale Negative Step 0.0010 0.0006 15 10 TIME (s) Figure 20. Total Unadjusted Error vs. AVDD1/|AVSS| Supply 0.0008 5 0 11840-224 1k LOAD TA = 25C 11840-221 TOTAL UNADJUSTED ERROR (%FSR) 10 0.03 -0.04 0.10 HIGH TO LOW LOW TO HIGH AVDD1 = VDPC+ = +15V AVSS = -15V 10V RANGE TA = 25C 0.05 0 0.0004 VOUT (V) 0.0002 0 -0.0002 -0.0004 -0.05 -0.010 -0.015 AV DD1 = VDPC+ = +15V AV SS = -15V 0 TO 10V RANGE 1k LOAD TA = 25C -0.0006 -0.020 -0.0008 -0.0010 -20 -16 -12 -8 -4 0 4 8 12 16 OUTPUT CURRENT (mA) 20 11840-222 OUTPUT VOLTAGE DELTA (V) 15 AVDD1 = VDPC+ = +15V AVSS = -15V 10V RANGE OUTPUT UNLOADED TA = 25C 0V TO 10V RANGE, MAX TUE 0V TO 10V RANGE, MIN TUE 0.04 10 Figure 22. Full-Scale Positive Step 0.05 -0.05 5 TIME (s) 11840-223 1k LOAD TA = 25C -0.8 -0.025 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TIME (s) Figure 24. Digital-to-Analog Glitch Major Code Transition Figure 21. Sink and Source Capability of the Output Amplifier Rev. B | Page 19 of 69 4.0 11840-226 DNL ERROR (%FSR) 0.6 -1.0 AVDD1 = VDPC+ = +15V AVSS = -15V 10V RANGE OUTPUT UNLOADED TA = 25C 0V TO 10V RANGE, MAX DNL 0V TO 10V RANGE, MIN DNL AD5758 20 AVDD1 = VDPC+ = +15V AVSS = -15V 0V TO 10V RANGE OUTPUT UNLOADED 15 OUTPUT VOLTAGE (V) Data Sheet AVDD1 = VDPC+ = 15V AVSS = -15V 1k LOAD CLOAD = 220pF CH4 = AVDD1 CH2 = VIOUT TA = 25C 10 5 4 0 -5 2 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) CH2 10.0mV CH4 5.00V 300 0 0V TO 10V RANGE - MIDSCALE CODE OUTPUT UNLOADED AVDD1 = VDPC + = 15V AVSS = -15V TA = 25C AVDD2 = 5V VDPC+ = 15V AVSS = -15V 1k LOAD CLOAD = 220pF -10 -20 200 -30 VIOUT PSRR (dB) OUTPUT VOLTAGE (V) 1.30V Figure 28. VOUT vs. Time on Power Up Figure 25. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) 400 M10.0ms A CH4 T 28.71200ms 11840-328 -15 11840-228 -10 100 0 -100 -40 -50 -60 -70 -200 -80 -300 1 2 3 4 5 6 7 8 9 10 TIME (ms) -100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 29. VOUT PSRR vs. Frequency Figure 26. Peak-to-Peak Noise (100 kHz Bandwidth) AVDD1 = VDPC+ = +15V AVSS = -15V 10V RANGE MIDSCALE CODE TA = 25C 10k LOAD CLOAD = 220pF VDPC+ 2 AVDD1 = VDPC+ = +15V AVSS = -15V 10V RANGE MIDSCALE CODE TA = 25C 10k LOAD CLOAD = 220pF SYNC 3 VOUT VOUT 4 B W CH4 50.0mV B W 1.00s CH2 10.0mV CH4 10.0mV Figure 27. VOUT vs. Time on Output Enable B B W 2.00s W Figure 30. Voltage Output Ripple Rev. B | Page 20 of 69 11840-233 CH3 2.00V 11840-234 4 11840-232 0 11840-229 -400 -90 Data Sheet AD5758 CURRENT OUTPUTS 0.004 4mA TO 4mA TO 4mA TO 4mA TO 20mA, 20mA, 20mA, 20mA, AVDD1 = +15V AVSS = -15V 0.001 INL ERROR (%FSR) INL ERROR (%FSR) 0.003 0.002 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET, WITH DC-TO-DC CONVERTER INTERNAL RSET, WITH DC-TO-DC CONVERTER 0.002 0.001 0 0 0mA TO 20mA, MIN INL 0mA TO 24mA, MIN INL 4mA TO 20mA, MIN INL 24mA, MIN INL 0mA TO 20mA, MAX INL 0mA TO 24mA, MAX INL 4mA TO 20mA, MAX INL 24mA, MAX INL -0.001 -0.002 -0.003 AVDD = +15V AVSS = -15V TA =25C 300 LOAD 8192 16384 24576 32768 40960 49152 57344 65536 CODE -05 -40 0.002 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET, WITH DC-TO-DC CONVERTER INTERNAL RSET, WITH DC-TO-DC CONVERTER 0.001 0.4 0.2 0 -0.2 -0.4 0 -0.001 -0.002 -0.6 0mA TO 20mA, MIN INL 0mA TO 24mA, MIN INL 4mA TO 20mA, MIN INL 24mA, MIN INL -0.003 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE 11840-237 -0.8 -1.0 -0.004 -40 115 125 Figure 35. INL Error vs. Temperature, External RSET 1.0 4mA TO 20mA, EXTERNAL RSET 4mA TO 20mA, INTERNAL RSET 0.8 0.010 DNL ERROR MAX DNL ERROR MIN AVDD1 = VDPC+ = +15V AVSS = -15V ALL RANGES 0.6 DNL ERROR (LSB) 0.005 0 -0.005 0.4 0.2 0 -0.2 -0.4 -0.010 -0.6 -0.015 -0.020 0 8192 16384 24576 32768 40960 49152 57344 CODE 65536 Figure 33. Total Unadjusted Error vs. DAC Code -1.0 -40 25 115 TEMPERATURE (C) Figure 36. DNL vs. Temperature Rev. B | Page 21 of 69 125 11840-211 -0.8 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 11840-238 TOTAL UNADJUSTED ERROR (%FSR) 25 TEMPERATURE (C) Figure 32. DNL Error vs. DAC Code 0.015 0mA TO 20mA, MAX INL 0mA TO 24mA, MAX INL 4mA TO 20mA, MAX INL 24mA, MAX INL AVDD1 = +15V AVSS = -15V INL ERROR (%FSR) DNL ERROR (LSB) 0.6 20mA, 20mA, 20mA, 20mA, 125 Figure 34. INL Error vs. Temperature, Internal RSET 1.0 4mA TO 4mA TO 4mA TO 4mA TO 115 TEMPERATURE (C) Figure 31. INL Error vs. DAC Code 0.8 25 11840-434 0 11840-435 -0.002 -0.004 11840-236 -0.001 AD5758 Data Sheet 0.15 0.15 0mA TO 20mA, INTERNAL RSET 0mA TO 24mA, INTERNAL RSET 4mA TO 20mA, INTERNAL RSET 24mA, INTERNAL RSET 0mA TO 20mA, EXTERNAL RSET 0mA TO 24mA, EXTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 24mA, EXTERNAL RSET AVDD1 = +15V AVSS = -15V 0.10 FULL-SCALE ERROR (%FSR) 0.05 0 -0.15 -40 -0.05 -0.10 115 25 0 125 TEMPERATURE (C) AVDD1 = +15V AVSS = -15V -0.15 -40 0.04 AVDD1 = +15V AVSS = -15V ZERO-SCALE ERROR (%FSR) 0 -0.01 0mA TO 20mA MIN TUE 0mA TO 24mA MIN TUE 4mA TO 20mA MIN TUE 24mA, MIN TUE 0mA TO 20mA MAX TUE 0mA TO 24mA MAX TUE 4mA TO 20mA MAX TUE 20mA, MAX TUE 0.02 0.01 0 -0.01 125 115 TEMPERATURE (C) -0.04 -40 115 125 Figure 41. Zero-Scale Error vs. Temperature 0.10 0.04 AVDD1 = +15V AVSS = -15V 0mA TO 20mA, INTERNAL RSET 0mA TO 24mA, INTERNAL RSET 4mA TO 20mA, INTERNAL RSET 24mA, INTERNAL RSET 0mA TO 20mA, INTERNAL RSET 0mA TO 24mA, INTERNAL RSET 4mA TO 20mA, INTERNAL RSET 24mA, INTERNAL RSET 0.05 GAIN ERROR (%FSR) 0.02 0.01 0 -0.01 0 -0.05 -0.02 25 115 TEMPERATURE (C 125 -0.15 -40 0mA TO 20mA, EXTERNAL RSET 0mA TO 24mA, EXTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 24mA, EXTERNAL RSET 25 115 TEMPERATURE (C) Figure 42. Gain Error vs. Temperature Figure 39. Offset Error vs. Temperature Rev. B | Page 22 of 69 125 11840-442 -0.04 -40 -0.10 0mA TO 20mA, EXTERNAL RSET 0mA TO 24mA, EXTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 24mA, EXTERNAL RSET -0.03 11840-439 OFFSET ERROR (%FSR) 25 TEMPERATURE (C) Figure 38. Total Unadjusted Error vs. Temperature, External RSET 0.03 0mA TO 20mA, INTERNAL RSET 0mA TO 24mA, INTERNAL RSET 4mA TO 20mA, INTERNAL RSET 24mA, INTERNAL RSET 0mA TO 20mA, EXTERNAL RSET 0mA TO 24mA, EXTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 24mA, EXTERNAL RSET -0.02 -0.03 11840-438 TUE ERROR (%FSR) 0.01 25 AVDD1 = +15V AVSS = -15V 0.03 0.02 -0.04 -40 125 Figure 40. Full-Scale Error vs. Temperature 0.03 -0.03 115 TEMPERATURE (C) Figure 37. Total Unadjusted Error vs. Temperature, Internal RSET -0.02 25 11840-440 -0.10 0mA TO 20mA TUE MIN 0mA TO 24mA TUE MIN 4mA TO 20mA TUE MIN 24mA TUE MIN 0mA TO 20mA TUE MAX 0mA TO 24mA TUE MAX 4mA TO 20mA TUE MAX 24mA TUE MAX 0.05 11840-441 -0.05 11840-437 TUE ERROR (%FSR) 0.10 Data Sheet 0.6 0.02 0.4 DNL ERROR (LSB) 0.03 0.01 0 -0.01 -0.02 0 -0.2 -0.4 -0.6 -0.04 -0.8 -0.05 -1.0 8 10 12 14 16 18 20 22 24 26 28 30 SUPPLY (V) 0.05 0.04 12 14 16 18 20 22 24 26 28 30 0.005 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0.003 INL ERROR (%FSR) 0.02 0.01 0 -0.01 -0.02 -0.03 0.001 0 -0.001 -0.003 -0.04 8 10 12 14 16 18 20 22 24 26 28 30 SUPPLY (V) -0.005 8 10 12 14 16 18 20 22 24 26 28 30 SUPPLY (V) Figure 44. Total Unadjusted Error vs. AVDD1/|AVSS| Supply, External RSET Figure 47. INL Error vs. AVDD1/|AVSS| Supply, Internal RSET 1.0 0.005 4mA TO 20mA RANGE MAX DNL 4mA TO 20mA RANGE MIN DNL 0.8 6 11840-265 6 11840-269 RLOAD = 300 TA = 25C -0.05 0.6 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0.003 INL ERROR (%FSR) 0.4 0.2 0 -0.2 -0.4 -0.6 0.001 -0.001 -0.003 RLOAD = 300 TA = 25C LOAD A 6 8 10 12 14 16 18 20 22 24 26 28 SUPPLY (V) 30 -0.005 6 8 10 12 14 16 18 20 22 24 26 28 SUPPLY (V) Figure 45. DNL Error vs. AVDD1/|AVSS| Supply, Internal RSET Figure 48. INL Error vs. AVDD1/|AVSS| Supply, External RSET Rev. B | Page 23 of 69 30 11840-268 -0.8 11840-264 DNL ERROR (LSB) 10 Figure 46. DNL Error vs. AVDD1/|AVSS| Supply, External RSET 0.03 -1.0 8 SUPPLY (V) RLOAD = 300 TA = 25C 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE RLOAD = 300 TA = 25C 6 Figure 43. Total Unadjusted Error vs. AVDD1/|AVSS| Supply, Internal RSET TUE ERROR (%FSR) 0.2 -0.03 6 4mA TO 20mA RANGE MAX DNL 4mA TO 20mA RANGE MIN DNL 0.8 11840-266 TUE ERROR (%FSR) 0.04 1.0 RLOAD = 300 TA = 25C 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE 11840-267 0.05 AD5758 AD5758 Data Sheet VOLTAGE (V) AVDD1 = +15V AVSS = -15V 4mA TO 20mA RANGE FULL-SCALE STEP 300 LOAD TA = 25C AVDD1 3 IOUT 4 W 4.00ms 0 -100 -50 100 150 200 250 300 350 400 450 500 50 TIME (s) Figure 49. Output Current vs. Time on Power-Up 11840-231 B 11840-261 CH3 5.00V BW CH4 10.0mV IOUT WITH 150mA LIMIT (V) VDPC+ WITH 150mA LIMIT (V) VDPC+ WITH 400mA LIMIT (V) IOUT WITH 400mA LIMIT (V) Figure 52. Output Current and VDPC+ Settling Time 300 Load 30 AVDD1 = +24V AVSS = -24V 4mA TO 20mA RANGE 25 FULL-SCALE STEP 1K LOAD TA = 25C TA = 25C VOLTAGE (V) 20 SYNC 3 IOUT 4 15 10 5 W CH4 20.0mV B 400ns W 0 -600 -400 -200 Figure 50. Output Current vs. Time on Output Enable 16 12 800 1000 1200 1400 10 9 8 IOUT AT IOUT AT IOUT AT IOUT AT 7 VOLTAGE (V) 10 8 6 -40C +25C +85C +125C VDPC+ AT VDPC+ AT VDPC+ AT VDPC+ AT -40C +25C +85C +125C 6 5 4 3 2 2 0 1 0 5 10 15 20 25 30 OUTPUT CURRENT (mA) Figure 51. DC-to-DC Converter Headroom vs. Output Current 0 -100 -50 0 50 100 150 200 250 300 350 400 450 500 550 TIME (s) 11840-453 AVDD1 = +15V AVSS = -15V 4mA TO 20mA RANGE FULL-SCALE STEP 300 LOAD DCDC ILIMIT = 150mA 4 11840-257 HEADROOM (V) 200 400 600 TIME (s) Figure 53. Output Current and VDPC+ Settling Time 1 k Load AVDD1 = +30V AVSS = -15V 0mA TO 24mA RANGE 1k LOAD TA = 25C 14 0 11840-553 CH3 2.00V B 11840-260 VDPC+ IOUT Figure 54. Output Current and VDPC+ Settling Time vs. Temperature Rev. B | Page 24 of 69 Data Sheet AD5758 20 VDPC+ 0 2 TA = 25C AVDD2 = 5V VDPC+ = 15V AVSS = -15V 300 LOAD 0 to 24mA Range IOUT PSRR (dB) -20 IOUT 4 -40 -60 -80 B B W W 2.00s -120 10 100 1k 10k 100k FREQUENCY (Hz) Figure 55. Output Current Ripple vs. Time with DC-to-DC Converter Figure 56. IOUT PSRR vs. Frequency Rev. B | Page 25 of 69 1M 10M 11840-256 CH2 10.0mV CH4 10.0mV 11840-365 -100 AD5758 Data Sheet DC-TO-DC BLOCK 100 90 90 80 OUTPUT EFFICIENCY (%) 70 70 60 50 40 30 10 0 2 4 6 8 10 12 14 16 18 1k LOAD 300 LOAD 0 LOAD 300 LOAD 0 LOAD 20 22 50 40 30 20 10 24 CURRENT (mA) 0 -40 90 0.16 POWER DISSIPATION (W) 80 70 60 50 40 30 10 0 -40 1k LOAD 300 LOAD 0 LOAD 300 LOAD 0 LOAD 25 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 0.14 1k 300 0 300 0 0.12 0.10 0.08 0.06 85 105 125 0 0 2 4 6 8 10 12 14 16 18 20 22 24 CURRENT (mA) Figure 58. Combined DC-to-DC Efficiency vs. Temperature Figure 61. Power Dissipation vs. Current 0.16 AVDD1 = 28V, 1k LOAD AVDD1 = 28V, 300 LOAD AVDD1 = 15V, 300 LOAD 80 = 28V, = 28V, = 28V, = 15V, = 15V, 0.02 TEMPERATURE (C) 90 125 105 0.04 11840-357 COMBINED DC-TO-DC EFFICIENCY (%) 0.18 = 28V, = 28V, = 28V, = 15V, = 15V, 85 Figure 60. Output Efficiency vs. Temperature 100 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 25 TEMPERATURE (C) Figure 57. DC-to-DC Efficiency vs. Current 20 AVDD1 = 28V, 20mA, 1k LOAD AVDD1 = 28V, 20mA, 300 LOAD AVDD1 = 15V, 20mA, 300 LOAD 11840-286 0 = 28V, = 28V, = 28V, = 15V, = 15V, 60 11840-288 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 20 11840-283 DC-TO-DC EFFICIENCY (%) 80 0.14 50 40 30 20 10 0 0.12 0.10 0.08 0.06 0.04 0.02 0 2 4 6 8 10 12 14 16 18 20 CURRENT (mA) 22 24 Figure 59. Output Efficiency vs. Current 0 -40 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 = 28V, = 28V, = 28V, = 15V, = 15V, 25 20mA, 20mA, 20mA, 20mA, 20mA, 1k 300 0 300 0 85 105 TEMPERATURE (C) Figure 62. Power Dissipation vs. Temperature Rev. B | Page 26 of 69 125 11840-285 POWER DISSIPATION (W) 60 11840-284 OUTPUT EFFICIENCY (%) 70 Data Sheet AD5758 REFERENCE 2.5005 TA = 25C AVDD2 = 5V TA = 25C AVDD2 REFOUT (V) 2.5000 3 2.4995 REFOUT B W 2.4985 11840-270 CH3 2.00V BW CH4 1.00 V 10.0s 0 2.50044 REFERENCE OUTPUT VOLTAGE (V) 4.0 TA = 25C 1 0 -1 -2 2.50042 2.50041 2.50040 2.50039 2.50038 2.50037 2.50036 -4 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) 2.50035 11840-271 0 8 10 12 14 16 18 20 22 24 26 28 30 Figure 67. Reference Output Voltage vs. AVDD2 Supply 2.5030 AV DD1 = VDPC+ = 15V AV SS = -15V TA = 25C 1.0 6 AVDD2 (V) Figure 64. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) 1.5 4 11840-274 OUTPUT VOLTAGE (V) 2 -3 2.5025 30 DEVICES SHOWN AVDD2 = 15V 2.5020 2.5015 REFOUT (V) 0.5 0 2.5010 2.5005 2.5000 2.4995 -0.5 2.4990 -1.0 2.4985 -1.5 2.4975 -40 0 2 4 6 8 10 12 14 16 18 TIME (ms) 20 -20 0 20 40 60 80 TEMPERATURE (C) Figure 68. REFOUT vs. Temperature Figure 65. Peak-to-Peak Noise (100 kHz Bandwidth) Rev. B | Page 27 of 69 100 120 11840-367 2.4980 11840-272 OUTPUT VOLTAGE (V) 3.5 2.50043 3 -5 3.0 2.5 Figure 66. REFOUT vs. Load Current AV DD1 = VDPC+ = +15V AV SS = -15V TA = 25C 4 2.0 LOAD CURRENT (mA) Figure 63. REFOUT Turn On Transient 5 1.5 1.0 0.5 11840-273 2.4990 4 AD5758 Data Sheet GENERAL 80 10.15 VLOGIC = 3.3V TA = 25C 70 AVDD2 = 5.5V TA = 25C 10.10 FREQUENCY (MHz) VLOGIC CURRENT (A) 60 50 40 30 10.05 10.00 20 9.95 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE AT PIN (V) 9.90 -40 11840-281 0 105 125 Figure 72. Internal Oscillator Frequency vs. Temperature 3.31 VOUT = 0V TA = 25C 1.5 70 TEMPERATURE (C) Figure 69. VLOGIC Current vs. Logic Input Voltage 2.0 25 11840-282 10 AVDD2 = 15V TA = 25C 3.30 AIDD1 3.29 1.0 VLDO (V) CURRENT (mA) 3.28 0.5 0 3.27 3.26 3.25 -0.5 3.24 -1.0 AISS 3.23 -1.5 0 5 10 15 20 30 25 35 VOLTAGE (V) 3.21 AIDD1 0.8 0.6 0.5 0.4 0.3 0.2 IOUT = 0mA TA = 25C 0 5 10 15 20 25 VOLTAGE (V) 30 35 11840-279 CURRENT (mA) 0.7 0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 Figure 73. VLDO vs. Load Current 1.0 0.1 5 LOAD CURRENT (mA) Figure 70. AIDD1/AISS Current vs. AVDD1/|AVSS| Supply 0.9 0 Figure 71. AIDD1 Current vs AVDD1 Supply Rev. B | Page 28 of 69 11840-276 3.22 11840-278 -2.0 Data Sheet AD5758 TERMINOLOGY Total Unadjusted Error (TUE) TUE is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or INL, is a measure of the maximum deviation, in LSBs or % FSR, from the best fit line passing through the DAC transfer function. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5758 is monotonic over its full operating temperature range. Zero-Scale/Negative Full-Scale Error Zero-scale/negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC output register. Zero-Scale Temperature Coefficient (TC) Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/C. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC output register is loaded with 0x8000 (straight binary coding). Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC output register. Ideally, the output is full-scale - 1 LSB. Full-scale error is expressed in % FSR. Headroom This is the difference between the voltage required at the output (programmed voltage in voltage output mode and programmed current x RLOAD in current output mode) and the voltage supplied by the positive supply rail, VDPC+. Headroom is relevant when the output is positive with respect to ground. Footroom Footroom is the difference between the voltage required at the output (programmed voltage in voltage output mode and programmed current x RLOAD in current output mode) and the voltage supplied by the negative supply rail, AVSS. Footroom is relevant when the output is negative with respect to ground. VOUT/-VSENSE Common-Mode Rejection Ratio (CMRR) VOUT/-VSENSE CMRR is the error in VOUT voltage due to changes in -VSENSE voltage. Current Loop Compliance Voltage The maximum voltage at the VIOUT pin for which the output current is equal to the programmed value. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25C compared to the output voltage measured at +25C after cycling the temperature from +25C to -40C to +115C and then back to +25C. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/C, as follows: Offset Error V - VREF _ MIN 6 = TC REF _ MAX x 10 Offset error is the deviation of the analog output from the ideal and V TempRange x REF _ NOM is measured using 1/4 scale and 3/4 scale digital code measurements. It is expressed in % FSR. where: VREF_MAX is the maximum reference output measured over the Offset Error (TC) total temperature range. Offset error TC is a measure of the change in the offset error VREF_MIN is the minimum reference output measured over the with a change in temperature. It is expressed in ppm FSR/C. total temperature range. Gain Error VREF_NOM is the nominal reference output voltage, 2.5 V. Gain error is a measure of the span error of the DAC. It is the TempRange is the specified temperature range, -40C to deviation in slope of the DAC transfer characteristic from the +115C. ideal expressed in % FSR. Line Regulation Gain Error Temperature Coefficient (TC) Line regulation is the change in reference output voltage due to Gain error TC is a measure of the change in gain error with a specified change in power supply voltage. It is expressed in changes in temperature. Gain error TC is expressed in ppm/V. ppm FSR/C. Rev. B | Page 29 of 69 AD5758 Data Sheet Load Regulation Load regulation is the change in reference output voltage due to a specified change in reference load current. It is expressed in ppm/mA. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5758 is powered on. It is specified as the area of the glitch in nV-sec. Dynamic Power Control (DPC) In this mode, the AD5758 circuitry senses the output voltage and dynamically regulates the supply voltage, VDPC+, to meet compliance requirements plus an optimized headroom voltage for the output buffer. Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the energy of the impulse injected into the analog output when the input code in the DAC output register changes state. It is normally specified as the area of the glitch in nV-sec. Worst case is usually when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Programmable Power Control (PPC) In this mode, the VDPC+ voltage is user-programmable to a fixed level that needs to accommodate the maximum output load required. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. This specification depends on the manner in which the DPC feature is configured (enabled, disabled, PPC mode enabled) and on the characteristics of the external dc-to-dc inductor and capacitor components used. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is expressed in V/s. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC output register changes state. It is specified as the amplitude of the glitch in millivolts and the worst case is usually when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated (LDAC pin is held high). It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Rev. B | Page 30 of 69 Data Sheet AD5758 The AD5758 is a single-channel, precision voltage and current output DAC, designed to meet the requirements of industrial factory automation and process control applications. It provides a high precision, fully integrated, single-chip solution for generating a unipolar/bipolar current or voltage output. Package power dissipation is minimized by incorporating on-chip DPC, which is achieved by regulating the supply voltage (VDPC+) to the VIOUT output driver from 4.95 V to 27 V using a buck dc-to-dc converter, optimized for minimum on-chip power dissipation. The AD5758 consists of a two die solution with the dc-to-dc converter circuitry and the VIOUT line protector located on the dc-to-dc die, and the remaining circuitry on the main die. Interdie communication is performed over an internal 3-wire interface. Voltage Output Mode If voltage output mode is enabled, the voltage output from the DAC is buffered and scaled to output a software-selectable unipolar or bipolar voltage range (see Figure 75). The voltage ranges available are 0 V to 5 V, 5 V, 0 V to 10 V, and 10 V. A 20% overrange feature is also available via the DAC_ CONFIG register, as well as the facility to negatively offset the unipolar voltage ranges via the GP_CONFIG1 register (see the General-Purpose Configuration 1 Register section). +VSENSE DAC RANGE SCALING VOUT SHORT FAULT DAC ARCHITECTURE The DAC core architecture of the AD5758 consists of a voltage mode R-2R ladder network. The voltage output of the DAC core is either converted to a current or voltage output at the VIOUT pin. Only one mode can be enabled at any one time. Both the voltage and current output stages are supplied by the VDPC+ power rail (internally generated from AVDD1) and the AVSS rail. Current Output Mode If current output mode is enabled, the voltage output from the DAC is converted to a current (see Figure 74), which is then mirrored to the supply rail so that the application only sees a current source output. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, 4 mA to 20 mA, 20 mA, 24 mA, and -1 mA to +22 mA. An internal or external 13.7 k RSET resistor can be used for the voltage to current conversion. VDPC+ R2 R3 VIOUT -VSENSE 11840-024 THEORY OF OPERATION Figure 75. Voltage Output Reference The AD5758 can operate with either an external or internal reference. The reference input requires a 2.5 V reference for specified performance. This input voltage is then internally buffered before it is applied to the DAC. The AD5758 contains an integrated buffered 2.5 V voltage reference that is externally available for use elsewhere within the system. The internal reference drives the integrated 12-bit ADC. REFOUT must be connected to REFIN to use the internal reference to drive the DAC. SERIAL INTERFACE The AD5758 is controlled over a versatile 4-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary. Input Shift Register 16-BIT DAC With SPI CRC enabled (default state), the input shift register is 32 bits wide. Data is loaded into the device MSB first as a 32-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. See the Register Map section for full details on the registers that can be addressed via the SPI interface. RA RB VIOUT RSET Vx R1 R4 IOUT OPEN FAULT Figure 74. Voltage to Current Conversion Circuitry 11840-023 VSS Table 7. Writing to a Register (CRC enabled) MSB D31 Slip Bit Rev. B | Page 31 of 69 [D30:D29] AD5758 address [D28:D24] Register address [D23:D8] Data LSB [D7:D0] CRC AD5758 Data Sheet Transfer Function Table 8 shows the input code to ideal output voltage relationship for the AD5758 for straight binary data coding of the 5 V output range. Table 8. Ideal Output Voltage to Input Code Relationship Digital Input, Straight Binary Data Coding MSB LSB 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 Analog Output VOUT +2 VREF x (32,767/32,768) +2 VREF x (32,766/32,768) 0V -2 VREF x (32,767/32,768) -2 VREF POWER-ON STATE OF THE AD5758 On initial power-on or a device reset of the AD5758, the voltage and current output channels are disabled. The switch connecting VIOUT via a 30 k pull-down resistor to AGND is open. This switch can be configured in the DCDC_CONFIG2 register. VDPC+ is internally driven to 4.8 V on power-on, until the dc-todc converter is enabled. The AD5758 incorporates a power-on reset circuit that ensures the AD5758 is held in reset while the power supplies are at a level insufficient to allow reliable operation. The power-on reset circuit (see Figure 76) monitors the AVDD2 generated VLDO and INT_AVCC voltages, the RESET pin, and the SPI reset signal. The power-on reset circuit keeps the AD5758 in reset until the voltages on the VLDO and INT_AVCC nodes are sufficient for reliable operation. If the power-on circuit receives a signal from the RESET pin, or if a software reset is written to the AD5758 via the SPI interface, the AD5758 is reset. Do not write SPI commands to the device within 100 s of a reset event. POWER SUPPLY CONSIDERATIONS The AD5758 has four supply rails: AVDD1, AVDD2, AVSS, and VLOGIC. See Table 1 for the voltage range of the four supply rails and the associated conditions. AVDD1 Considerations AVDD1 is the supply rail for the dc-to-dc converter and can range from 7 V to 33 V. Although the maximum value of AVDD1 is 33 V and the minimum value of AVSS is -33 V, the maximum operating range of |AVDD1 to AVSS| is 60 V. VDPC+ is derived from AVDD1, and its value depends on the mode of operation of the dc-to-dc converter. After device power-on, or a device reset, a calibration memory refresh command is required (see the Programming Sequence to Enable the Output section). It is recommended to wait 500 s minimum after writing this command, before writing further instructions to the device to allow time for internal calibrations to take place (see Figure 90). The dc-to-dc converter requires a sufficient level of margin to be maintained between AVDD1 and VDPC+ to ensure the dc-to-dc circuitry operates correctly. This margin is 5% of the maximum VDPC+ voltage for a given mode of operation. Power-On Reset Table 9. AVDD1 to VDPC+ Margin Mode of Operation DPC Voltage Mode DPC Current Mode PPC Current Mode AVDD2 VLDO 3.3V LDO INT_AVCC VDPC+ Maximum 15 V (IOUT maximum x RLOAD) + IOUT headroom DCDC_CONFIG1[4:0] programmed value See the Power Dissipation Control section for further details on the dc-to-dc converter modes of operation. SOFTWARE RESET RESET HARDWARE RESET Assuming DPC current mode, * IOUT maximum = 20 mA; RLOAD = 1 k * IOUT headroom = 2.5 V * VDPC+ maximum = 20 V + 2.5 V = 22.5 V POWER-ON RESET Figure 76. Power-On Reset Block Diagram 11840-125 SYNC SCLK SDI |VDPC+ to AVDD1| headroom can be calculated as 5% of 22.5 V = 1.125 V. Therefore, AVDD1 (minimum) = 22.5 V + 1.125 V = 23.625 V. Assuming a worst case AVDD1 supply rail tolerance of 10%, this example requires an AVDD1 supply rail of approximately 26 V. Rev. B | Page 32 of 69 Data Sheet AD5758 AVSS Considerations AVDD2 Considerations AVSS is the negative supply rail and has a range of -33 V to 0 V. As in the case of AVDD1, AVSS must obey the maximum operating range of |AVDD1 to AVSS| of 60 V. For bipolar current output ranges, the maximum AVSS can be calculated as (IOUT_MAX x RLOAD) + IOUT foot-room. For unipolar current output ranges, AVSS can be tied to AGND (that is, 0 V). For unipolar voltage output ranges, the maximum AVSS is -2 V to enable sufficient footroom for the internal voltage output circuitry. To avoid power supply sequencing issues, a Schottky diode must be placed between AVSS and GND (the GND supply must always be available). AVDD2 is the positive low voltage supply rail and has a range of 5 V to 33 V. If only one positive power rail is available, AVDD2 can be tied to AVDD1. However, to optimize for reduced power dissipation, supply AVDD2 with a separate lower voltage supply. VLOGIC Considerations VLOGIC is the digital supply for the device and can range from 1.71 V to 5.5 V. The 3.3 V VLDO output voltage can be used to drive VLOGIC. Rev. B | Page 33 of 69 AD5758 Data Sheet DEVICE FEATURES AND DIAGNOSTICS POWER DISSIPATION CONTROL The AD5758 contains integrated buck dc-to-dc converter circuitry that controls the power supply to the output buffers, allowing a reduction in power consumption from standard designs when using the device in both current and voltage output modes. AVDD1 is the supply rail for the dc-to-dc converter and ranges from 7 V to 33 V. VDPC+ is derived from this rail and its value depends on the mode of operation of the dc-to-dc converter, as well as the output load, including DPC voltage mode, DPC current mode, and PPC current mode Figure 77 shows the discrete components needed for the dc-todc circuitry and the following sections describe component selection and operation of this circuitry. 0.1F AVDD1 CIN 4.7F LDCDC 47H CDCDC 2.2F PGND1 SW+ VDPC+ PGND1 11840-021 DC-TO-DC CONVERTER CIRCUITRY VDPC+ Figure 77. DC-to-DC Circuit Table 10. Recommended DC-to-DC Components Symbol LDCDC CDCDC CIN Component PA6594-AE GCM31CR71H225KA55L GRM31CR71H475KA12L Value 47 H 2.2 F 4.7 F Manufacturer Coilcraft Murata Murata DC-to-DC Converter Operation The dc-to-dc converter uses a fixed 500 kHz frequency, peak current mode control scheme to step down the AVDD1 input to produce VDPC+ to supply the driver circuitry of the voltage/current output channel. The dc-to-dc converter incorporates a low-side synchronous switch and, therefore, does not require an external Schottky diode. The dc-to-dc converter is designed to operate predominantly in discontinuous conduction mode (DCM), where the inductor current goes to zero for an appreciable percentage of the switching cycle. To avoid generating lower frequency harmonics on the VDPC+ regulated output voltage rail, the dc-to-dc converter does not skip any cycles. Therefore, the dc-to-dc converter must transfer a minimum amount of energy to its load (that is, the current or voltage output stage and its respective load) to operate at a fixed frequency. Thus, for light loads (for example, low RLOAD or low IOUT), the VDPC+ voltage can rise beyond the target value and go out of regulation. This rise in voltage is not a fault condition and does not represent the worst case power dissipation condition in an application. Note that the dc-to-dc converter requires a sufficient level of margin to be maintained between AVDD1 and VDPC+ to ensure that the dc-to-dc circuitry operates correctly. This margin value is 5% of VDPC+ maximum. DPC Voltage Mode In DPC voltage mode, with the voltage output enabled or disabled, the converter regulates the VDPC+ supply to 15 V above the -VSENSE voltage. This mode allows the full output voltage range to be efficiently applied across remote loads, with corresponding remote grounds at up to 10 V potential relative to the local ground supply (AGND) for the AD5758. DPC Current Mode In standard current input module designs, the combined line and load resistance values can range from typically 50 to 750 . Output module systems must provide enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop, when driving 20 mA into a 750 load, a compliance voltage of >15 V is required. When driving 20 mA into a 50 load, the required compliance is reduced to >1 V. In DPC current mode, the AD5758 dc-to-dc circuitry senses the output voltage and regulates the VDPC+ supply voltage to meet compliance requirements plus an optimized headroom voltage for the output buffer. VDPC+ is dynamically regulated to 4.95 V or (IOUT x RLOAD + headroom), whichever is greater, which excludes the light load condition whereby the VDPC+ voltage can rise beyond the target value. As previously noted, this exclusion does not represent the worst case power dissipation condition in an application. The AD5758 is capable of driving up to 24 mA through a 1 k load, for a given input supply (24 V + headroom). At low output power levels, the regulated headroom increases above 2.3 V due to the fact that the dc-to-dc circuitry uses a minimum on time duty cycle. This behaviour is expected and does not impact any worse case power dissipation. PPC Current Mode The dc-to-dc converter may also operate in programmable power control mode, where the VDPC+ voltage is user-programmable to a given level to accommodate the maximum output load required. This mode represents a trade-off between the optimized power efficiency of the DPC current mode and the settling time of a system with a fixed supply (dc-to-dc disabled). In PPC current mode, VDPC+ is regulated to a user-programmable level between 5 V and 25.677 V with respect to -VSENSE (in steps of 0.667 V). This mode is useful if settling time is an important requirement of the design. See the DC-to-DC Converter Settling Time section. Care is needed in selecting the programmed level of VDPC+ if the load is nonlinear in nature. VDPC+ must be set high enough to obey the output compliance voltage specification. If the load is unknown, the +VSENSE input to the ADC can be used to monitor the VIOUT pin in current mode to determine the user-programmable value at which to set VDPC+. Rev. B | Page 34 of 69 Data Sheet AD5758 DC-to-DC Converter Settling Time When in DPC current mode, the settling time is dominated by the settling time of the dc-to-dc converter and is typically 200 s without the digital slew rate control feature enabled. To reduce initial VIOUT waveform overshoot without adding a capacitor on VIOUT and thereby affecting HART operation, enable the digital slew rate control feature using the DAC_CONFIG register (see Table 32). Table 11 shows the typical settling time for each of the dc-todc converter modes. All values shown assume the use of the components recommended by Analog Devices, Inc., listed in Table 10. The achievable settling time in any given application is dependent on the choice of external inductor and capacitor components used, as well as the current-limit setting of the dcto-dc converter. Table 11. Settling Time vs. DC-to-DC Converter Mode DC-to-DC Converter Mode DPC Current Mode PPC Current Mode DPC Voltage Mode Settling Time (s) 200 15 15 DC-to-DC Converter Inductor Selection For typical 4 mA to 20 mA applications, a 47 H inductor (per Table 10), combined with the switching frequency of 500 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 k with an AVDD1 supply of greater than 24 V + headroom. It is important to ensure that the peak current does not cause the inductor to saturate, especially at the maximum ambient temperature. If the inductor enters saturation mode, it results in a decrease in efficiency. Larger size inductors translate to lower core losses. The slew rate control feature of the AD5758 can be used to limit peak currents during slewing. Program an appropriate current limit (via the DCDC_CONFIG2 register) to shut off the internal switch if the inductor current reaches that limit. DC-to-DC Converter Input and Output Capacitor Selection The output capacitor, CDCDC, affects the ripple voltage of the dcto-dc converter and limits the maximum slew rate at which the output current can rise. The ripple voltage is directly related to the output capacitance. The CDCDC capacitor recommended by Analog Devices (see Table 10), combined with the recommended 47 H inductor, results in a 500 kHz ripple with amplitude less than 50 mV and guarantees stability and operation with HART capability across all operating modes. For high voltage capacitors, the size of the capacitor is often an indication of the charge storage ability. It is important to characterize the dc bias voltage vs. capacitance curve for this capacitor. Any capacitance values specified are with reference to a dc bias corresponding to the maximum VDPC+ voltage in the application. As well as the voltage rating, the temperature range of the capacitor must also be considered for a given application. These considerations are key in selection of the components described in Table 10. The input capacitor, CIN, provides much of the dynamic current required for the dc-to-dc converter, and a low effective series resistance (ESR) component is recommended. For the AD5758, a low ESR tantalum or ceramic capacitor of 4.7 F (1206 size) in parallel with a 0.1 F (0402 size) capacitor is recommended. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value. CLKOUT The AD5758 can provide a CLKOUT signal to the system for synchronization purposes. This signal is programmable to eight frequency options between 416 kHz and 588 kHz, with the default option being 500 kHz--the same switching frequency of the dc-to-dc converter. This feature is configured in the GP_CONFIG1 register and is disabled by default INTERDIE 3-WIRE INTERFACE A 3-wire interface is used to communicate between the two die in the AD5758. The 3-wire interface master is located on the main die, and the 3-wire interface slave is on the dc-to-dc die. The three interface signals are data, DCLK (running at MCLK/8), and interrupt. The main purpose of the 3-wire interface is to read from or write to the DCDC_CONFIG1 and DCDC_CONFIG2 registers. Addressing these registers via the SPI interface initiates an internal 3-wire interface transfer from the main die to the dc-todc die. The 3-wire interface master on the main die initiates writes and reads to the registers on the dc-to-dc die using DCLK as the serial clock. The slave uses an interrupt signal to the dc-to-dc die to indicate that a read of the dc-to-dc die internal status register is required. For every 3-wire interface write, an automatic read and compare process can be enabled (default case) to ensure that the contents of the copy of the DCDC_CONFIGx registers on the main die match the contents of the registers on the dc-to-dc die. This comparison is performed to ensure the integrity of the digital circuitry on the dc-to-dc die. With this feature enabled, a 3-wire interface transfer takes approximately 300 s. When disabled, this transfer time reduces to 30 s. The BUSY_3WI flag in the DCDC_CONFIG2 register is asserted during the 3-wire interface transaction. The BUSY_3WI flag is also set when the user updates the DAC range (via the DAC_ CONFIG register, Bits[4:0]) due to the internal calibration memory refresh caused by this action, which requires a 3-wire interface transfer between the two die. A write to either of the DCDC_CONFIGx registers must not be initiated while BUSY_3WI is asserted. If a write occurs while BUSY_3WI is asserted, the new write is delayed until the current 3-wire interface (3WI) transfer completes. Rev. B | Page 35 of 69 AD5758 Data Sheet 3-Wire Interface Diagnostics Driving Large Capacitive Loads Any faults on the dc-to-dc die triggers an interrupt to the main die. An automatic status read of the dc-to-dc die is performed. After the read transaction, the main die retains a copy of the dc-todc die status bits (VIOUT_OV_ERR, DCDC_P_SC_ERR, and DCDC_P_PWR_ERR). These values are available in the ANALOG_DIAG_RESULTS register and via the OR'd analog diagnostic results bits in the status register. These bits also trigger the FAULT pin. The voltage output amplifier is capable of driving capacitive loads of up to 2 F with the addition of a 220 pF nonpolarized compensation capacitor. This capacitor, while allowing the AD5758 to drive higher capacitive loads and reduce overshoot, increases the settling time of the device and, therefore, affects the bandwidth of the system. Without the compensation capacitor, capacitive loads of up to 10 nF can be driven. In response to the interrupt request, the main die (master) performs a 3-wire interface read operation to read the status of the dc-to-dc die. The interrupt is only asserted again by a subsequent dc-to-dc die fault flag, upon which the 3-wire interface initiates another status read transaction. If an interrupt signal is detected six times in a row, the interrupt detection mechanism is disabled until a 3-wire interface write transaction completes. This disabling prevents the 3-wire interface from being blocked because of the constant dc-to-dc die status read when the interrupt is toggling. The INTR_SAT_3WI flag in the DCDC_CONFIG2 register indicates when this event occurs, and a write to either DCDC_CONFIGx register resets this bit to 0. Under normal operation, the voltage output sinks/sources up to 12 mA and maintains specified operation. The short-circuit current is typically 16 mA. If a short circuit is detected, the FAULT pin goes low and the VOUT_SC_ERR bit in the ANALOG_DIAG_RESULTS register is set. FAULT PROTECTION During a 3-wire read or write operation, the address and data bits in the transaction produce parity bits. These parity bits are checked on the receive side and, if they do not match on both die, the ERR_ 3WI bit in the DIGITAL_DIAG_RESULTS register is set. If the read and compare process is enabled and a parity error occurs, the 3WI_RC_ERR bit in the DIGITAL_DIAG_ RESULTS register is also set. VOLTAGE OUTPUT Voltage Output Amplifier and VSENSE Functionality The voltage output amplifier is capable of generating both unipolar and bipolar output voltages, and is also capable of driving a load of 1 k in parallel with 2 F (with an external compensation capacitor) to AGND. Figure 78 shows the voltage output driving a load, RLOAD, on top of a common-mode voltage (VCM) of 10 V. An integrated 2 M resistor ensures that the amplifier loop is kept closed, thus preventing potential large destructive voltages on VIOUT due to the broken amplifier loop in applications where a cable may become disconnected from +VSENSE. If remote sensing of the load is not required, connect +VSENSE directly to VIOUT via a 1 k resistor and connect -VSENSE directly to AGND via a 1 k resistor. AD5758 +VSENSE VOUT RANGE SCALING 2M VIOUT -VSENSE 2M Figure 78. Voltage Output RLOAD 10V VCM 11840-121 16-BIT DAC Voltage Output Short-Circuit Protection The AD5758 incorporates a line protector on the VIOUT pin, +VSENSE pin, and -VSENSE pin. The line protector operates by clamping the voltage internal to the line protector to the VDPC+ and AVSS rails, thereby protecting internal circuitry from external voltage faults. If a voltage outside of these limits is detected on the VIOUT pin, an error flag (VIOUT_OV_ERR) is also set and is located in the ANALOG_DIAG_RESULTS register. CURRENT OUTPUT External Current Setting Resistor As shown in Figure 74, RSET is an internal sense resistor that forms part of the voltage to current conversion circuitry. The stability of the output current value over temperature is dependent on the stability of the value of RSET. As a method of improving the stability of the output current over temperature, an external, 13.7 k, low drift resistor can be connected between the RA and RB pins of the AD5758, to be used instead of the internal resistor. Table 1 shows the performance specifications of the AD5758 with both the internal RSET resistor and an external, 13.7 k RSET resistor. The external RSET resistor specification assumes an ideal resistor. The actual performance depends on the absolute value and temperature coefficient of the resistor used. Therefore, the resistor specifications directly affect the gain error of the output and the TUE. To arrive at the absolute worst case overall TUE of the output with a particular external RSET resistor, add the percentage absolute error of the RSET resistor directly to the TUE of the AD5758 with the external RSET resistor, shown in Table 1 (expressed in % FSR). The temperature coefficient must also be considered, as well as the specifications of the external reference, if this is the option being used in the system. The magnitude of the error derived from directly summing the absolute error and TC error of both the external RSET resistor and the external reference with the TUE specification of the AD5758 is unlikely to occur because the TC values of the individual components are not likely to exhibit the same drift polarity, and, therefore, an element of cancelation occurs. For Rev. B | Page 36 of 69 Data Sheet AD5758 SR_STEP. SR_CLOCK defines the rate at which the digital slew is updated. For example, if the selected update rate is 8 kHz, the output updates every 125 s. In conjunction with SR_CLOCK, SR_STEP defines by how much the output value changes at each update. Together, both parameters define the rate of change of the output value. this reason, add the TC values in a root of squares fashion. A further improvement can be gained by performing a two point calibration at zero scale and full scale, thus reducing the absolute errors of the voltage reference and the RSET resistor. Current Output Open-Circuit Detection When in current output mode, if the headroom available falls below the compliance range due to an open-loop circuit or an insufficient power supply voltage, the IOUT_OC_ERR flag in the ANALOG_DIAG_RESULTS register is asserted, and the FAULT pin goes low. The following equation describes the slew rate as a function of the step size, the slew rate frequency, and the LSB size: Slew Time = HART CONNECTIVITY When the slew rate control feature is enabled, all output changes occur at the programmed slew rate. For example, if the WDT times out and an automatic clear occurs, the output slews to the clear value at the programmed slew rate (setting the CLEAR_NOW_ EN bit in the GP_CONFIG1 register overrides this default behavior to cause the output to update to the clear code immediately, rather than at the programmed slew rate). Figure 79 shows the recommended circuit for attenuating and coupling the HART signal into the AD5758. To achieve 1 mA p-p at the VIOUT pin, a signal of approximately 125 mV p-p is required at the CHART pin. The HART signal appearing at the VIOUT pin is inverted relative to the signal input at the CHART pin. The slew rate frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. IOUT CHART HART_EN C1 C2 HART MODEM OUTPUT Figure 79. Coupling the HART Signal As well as their use in attenuating the incoming HART modem signal, a minimum capacitance of the combination of C1 and C2 is required to ensure that the bandwidth presented to the modem output signal passes the 1.2 kHz and 2.2 kHz frequencies. Assuming a HART signal of 500 mV p-p, the recommended values are C1 = 47 nF and C2 = 150 nF. Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART. If the HART feature is not required, disable the HART_EN bit and leave the CHART pin open circuit. However, if it is required to slow the DAC output signal with a capacitor, the HART_EN bit must be enabled and the required CSLEW capacitor connected to the CHART pin. DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5758 allows the user to control the rate at which the output value changes. This feature is available in both current and voltage mode. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, enable the slew rate control feature. With this feature enabled, the output steps digitally from one value to the next at a rate defined by two parameters accessible via the DAC_CONFIG register. The parameters are SR_CLOCK and 11840-027 IOUT RANGE SCALING Step Size x Slew Rate Frequency x LSB Size where: Slew Time is expressed in seconds. Output Change is expressed in amps for current output mode or volts for voltage output mode. The AD5758 has a CHART pin, onto which a HART signal can be coupled. The HART signal appears on the current output if the HART_EN bit in the GP_CONFIG1 register is enabled and the VIOUT output is also enabled. 16-BIT DAC Output Change AD5758 ADDRESS PINS The AD5758 address pins (AD0 and AD1) are used in conjunction with the address bits within the SPI frame (see Table 12) to determine which AD5758 device is being addressed by the system controller. With the two address pins, up to four devices can be independently addressed on one board. SPI Interface and Diagnostics The AD5758 is controlled over a 4-wire serial interface with an 8-bit cyclic redundancy check (CRC-8) enabled by default. The input shift register is 32 bits wide, and data is loaded into the device MSB first under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. Table 12. Writing to a Register (CRC Enabled) MSB D31 Slip bit [D30:D29] AD5758 address [D28:D24] Register address [D23:D8] Data LSB [D7:D0] CRC As shown in Table 12, every SPI frame contains two address bits. These bits must match the hardware address pins (AD0 and AD1) for a particular device to accept the SPI frame on the bus. Rev. B | Page 37 of 69 AD5758 Data Sheet SPI Cyclic Redundancy Check To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8. The device controlling the AD5758 generates an 8-bit frame check sequence using the following polynomial: C(x) = x8 + x2 + x1 + 1 This sequence is added to the end of the data-word, and 32 bits are sent to the AD5758 before taking SYNC high. If the SPI_CRC_EN bit is set high (default state), the user must supply a frame of exactly 32 bits wide that contains the 24 data bits and 8-bit CRC. If the CRC check is valid, the data is written to the selected register. If the CRC check fails, the data is ignored, the FAULT pin goes low and the FAULT pin status bit and the digital diagnostic status bit (DIG_DIAG_STATUS) in the status register are asserted. A subsequent readback of the DIGITAL_DIAG_RESULTS register reveals that the SPI_CRC_ERR bit is also set. This register is a per bit, write to clear register (see the Sticky Diagnostic Results Bits section); therefore, the SPI_CRC_ERR bit can be cleared by writing a 1 to Bit D0 of the DIGITAL_DIAG_RESULTS register. Doing so clears the SPI_CRC_ERROR bit and causes the FAULT pin to return high (assuming that there are no other active faults). When configuring the FAULT_PIN_CONFIG register, the user can decide whether the SPI CRC error affects the FAULT pin. See the FAULT Pin Configuration Register section for further details. The SPI CRC feature can be used for both the transmission and receipt of data packets. UPDATE ON SYNC HIGH SYNC LSB D0 24-BIT DATA 24-BIT DATA TRANSFER--NO CRC ERROR CHECKING UPDATE ON SYNC HIGH ONLY IF CRC CHECK PASSED SYNC LSB D8 24-BIT DATA D7 D0 8-BIT CRC FAULT PIN GOES LOW IF CRC CHECK FAILS FAULT 32-BIT DATA TRANSFER WITH CRC ERROR CHECKING 11840-025 SDI Readback Modes The AD5758 offers four readback modes, as follows: * * * * Two stage readback mode Autostatus readback mode Shared SYNC autostatus readback mode Echo mode The two stage readback consists of a write to a dedicated register, TWO_STAGE_READBACK_SELECT, to select the register location to be read back. This write is followed by a no operation (NOP) command, during which the contents of the selected register are available on SDO. Table 13. SDO Contents for Read Operation MSB [D31:D30] D29 [D28:24] 0b10 FAULT pin status Register address LSB [D23:D8] [D7:D0] Data CRC Bits[D31:D30] = 0b10 are used for synchronization purposes during readback. The shared SYNC autostatus readback is a special version of the autostatus readback mode used to avoid SDO bus contention when multiple devices are sharing the same SYNC line. SCLK MSB D31 An SCLK count feature is also built into the SPI diagnostics, meaning that only SPI frames with exactly 32 SCLK falling edges (32 or 24 if SPI CRC is disabled) are accepted by the interface as a valid write. SPI frames of lengths other than these values are ignored and the SCLK_COUNT_ERR flag asserts in the DIGITAL_DIAG_RESULTS register. Figure 80. CRC Timing (Assume LDAC = 0) Echo mode behaves similarly to autostatus readback mode, except that every second readback consists of an echo of the previous command written to the AD5758 (see Figure 81). See the Reading from Registers section for further details on the readback modes. SPI Interface Slip Bit A further enhancement to the robustness of the interface is the addition of the slip bit. The MSB of the SPI frame must equal the inverse of the MSB - 1 for the frame to be considered valid. Rev. B | Page 38 of 69 PREVIOUS COMMAND STATUS REGISTER CONTENTS PREVIOUS COMMAND Figure 81. SDO Contents, Echo Mode 11840-019 SDI SPI Interface SCLK Count Feature If autostatus readback mode is selected, the contents of the status register are available on the SDO line during every SPI transaction. This feature allows the user to continuously monitor the status register and act quickly in the case of a fault. The AD5758 powers up with this feature disabled. When this feature is enabled, the normal two stage readback feature is not available. Only the status register is available on SDO. To read back any other register, disable the automatic readback feature first before following the two stage readback sequence. The automatic status readback can be reenabled after the register is read back. SCLK MSB D23 If an incorrect slip bit is detected, the data is ignored and the SLIPBIT_ERROR bit in the DIGITAL_DIAG_RESULTS register is asserted. Data Sheet AD5758 WATCHDOG TIMER (WDT) Table 14. Gain Register Adjustment The WDT feature is useful to ensure that communication is not lost between the system controller and the AD5758 and that the SPI datapath lines function as expected. Gain Adjustment Factor 1 65,535/65,536 ... 2/65,536 1/65,536 When enabled, the WDT alerts the system if the AD5758 has not received a specific SPI frame in the user-programmable timeout period. When the specific SPI frame is received, the watchdog resets the timer controlling the timeout alert. The SPI frame used to reset the WDT is configurable as one of the two following choices: * * A specific key code write to the key register (default). A valid SPI write to any register. When a watchdog timeout event occurs, there are two user configurable actions the AD5758 can take. The first user configurable action is to load the DAC output with a user defined clear code stored in the CLEAR_CODE register. The second user configurable action is to perform a software reset. These actions can be enabled via Bit 10 and Bit 9, respectively, in the WDT_CONFIG register. On a watchdog timeout event (regardless of Bit 10 or Bit 9 being enabled), a dedicated WDT_STATUS bit in the status register, as well as a WDT_ERR bit in the DIGITAL_DIAG_RESULTS register, alerts the user that the WDT timed out. Note that, after a WDT timeout occurs, all writes to the DAC_INPUT register, as well as the hardware or software LDAC events, are ignored until the active WDT fault flag within the DIGITAL_DIAG_RESULTS register clears. After this flag clears, the WDT can be restarted by performing a subsequent WDT reset command. On power-up, the WDT is disabled by default. The default timeout setting is 1 sec. The default method to reset the WDT is to write one specific key and, on timeout, the default action is to set the relevant flag bits and the FAULT pin. See Table 39 for the specific register bit details to support the configurability of the WDT operation. USER DIGITAL OFFSET AND GAIN CONTROL The AD5758 has a USER_GAIN register and a USER_OFFSET register that allow trimming of the gain and offset errors from the entire signal chain. The 16-bit USER_GAIN register allows the user to adjust the gain of the DAC channel in steps of 1 LSB. The USER_GAIN register coding is straight binary, as shown in Table 14. The default code in the USER_GAIN register is 0xFFFF, which results in no gain factor applied to the programmed output. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy. D15 1 1 ... 0 0 D14 to D1 1 1 ... 0 0 D0 1 0 ... 1 0 The 16-bit USER_OFFSET register allows the user to adjust the offset of the DAC channel by -32,768 LSBs to +32,768 LSBs in steps of 1 LSB. The USER_OFFSET register coding is straight binary, as shown in Table 15. The default code in the USER_ OFFSET register is 0x8000, which results in zero offset programmed to the output. Table 15. Offset Register Adjustment Gain Adjustment +32,768 LSBs +32,767 LSBs ... No Adjustment (Default) ... -32,767 LSBs -32,768 LSBs D15 1 1 ... 1 ... 0 0 D13 to D2 1 1 ... 0 ... 0 0 D0 1 0 ... 0 ... 1 0 The value (in decimal) that is written to the internal DAC register can be calculated by DAC _ Code = D x ( M + 1) 216 + C - 215 (1) where: D is the code loaded to the DAC_INPUT register. M is the code in the USER_GAIN register (default code = 216 - 1). C is the code in the USER_OFFSET register (default code = 215). Data from the DAC_INPUT register is processed by a digital multiplier and adder, controlled by the contents of the user gain and USER_OFFSET registers, respectively. The calibrated DAC data is then loaded to the DAC, dependent on the state of the LDAC pin. Each time data is written to the USER_GAIN or USER_ OFFSET register, the DAC output is not automatically updated. Instead, the next write to the DAC_INPUT register uses these user gain and user offset values to perform a new calibration and automatically updates the channel. The read only DAC_ OUTPUT register represents the value currently available at the DAC output, except in the case of user gain and user offset calibration. In this case, the DAC_OUTPUT register represents the DAC data input by the user, on which the calibration is performed and not the result of the calibration. Both the USER_GAIN register and the USER_OFFSET register have 16 bits of resolution. The correct method to calibrate the gain and offset is to first calibrate the gain and then calibrate the offset. Rev. B | Page 39 of 69 AD5758 Data Sheet DAC OUTPUT UPDATE AND DATA INTEGRITY DIAGNOSTICS Figure 82 shows a simplified version of the DAC input loading circuitry. If used, the USER_GAIN and USER_OFFSET registers must be updated before writing to the DAC_INPUT register. REFIN OUTPUT AMPLIFIER DAC OUTPUT REGISTER (READ ONLY) 16-BIT DAC VIOUT LDAC (HARDWARE OR SOFTWARE) CLEAR EVENT (WDT TIMEOUT) USER GAIN AND OFFSET CALIBRATION SCLK SYNC SDI DAC INPUT REGISTER INTERFACE LOGIC Figure 82. Simplified Serial Interface of Input Loading Circuitry Rev. B | Page 40 of 69 SDO 11840-026 CLEAR CODE REGISTER Data Sheet AD5758 * * * * If a write is performed to the DAC_INPUT register with the hardware LDAC pin tied low, the DAC_OUTPUT register is updated on the rising edge of SYNC and is subject to the timing specifications in Table 2. If the hardware LDAC pin is high and a write to the DAC_INPUT register occurs, the DAC_OUTPUT register does not update until a software LDAC instruction is issued or the hardware LDAC pin is pulsed low. If a WDT timeout occurs with the CLEAR_ON_WDT_ FAIL bit set, the CLEAR_CODE register contents are loaded into the DAC_OUTPUT register. If the slew rate control feature is enabled, the DAC_ OUTPUT register contains the dynamic value of the DAC as it slews between values. Note that, while a WDT fault is active, all writes to the DAC_ INPUT register, as well as hardware or software LDAC events, are ignored. If the CLEAR_ON_WDT_FAIL bit is set such that the output is set to the clear code, when the WDT fault flag clears, the DAC_INPUT register must be written to before an update to the DAC_OUTPUT register occurs; that is, performing a software or hardware LDAC only reloads the DAC with the clear code. As described in the Programming Sequence to Enable the Output section, after configuring the DAC range via the DAC_ CONFIG register, a write to the DAC_INPUT register must occur, even if the contents of the DAC_INPUT register are not changing from their current value. The GP_CONFIG2 register contains a bit to enable a global software LDAC mode, whereby the AD5758 address bits of the SW_LDAC command are ignored, thus enabling multiple AD5758 devices to be simultaneously updated using a single SW_LDAC command. This feature is useful if the hardware LDAC pin is not being used in a system containing multiple AD5758 devices. DAC Data Integrity Diagnostics To protect against transient changes to the internal digital circuitry, the digital block stores both the digital DAC value and an inverted copy of the digital DAC value. A check is completed to ensure that the two values correspond to each other before the DAC is strobed to update to the DAC code. This feature is enabled by default via the INVERSE_DAC_ CHECK_EN bit in the DIGITAL_DIAG_CONFIG register. Outside of the digital block, the DAC code is stored in latches, as shown in Figure 83. These latches are potentially vulnerable to the same transient events as those protected against within the digital block. To protect the DAC latches against such transients, the DAC latch monitor feature can be enabled via the DAC_LATCH_MON_EN bit within the DIGITAL_DIAG_ CONFIG register. This feature monitors the actual digital code driving the DAC and compares it with the digital code generated within the digital block. Any difference between the two codes causes the DAC_LATCH_MON_ERR flag to be set in the DIGITAL_DIAG_RESULTS register. DAC LATCHES DIGITAL BLOCK Q D Q D 16-BIT DAC Q Q 11840-028 The DAC_OUTPUT register (and ultimately the DAC output) updates in any of the following cases: Figure 83. DAC Data Integrity USE OF KEY CODES Key codes (via the key register) are used for the following functions (see the Key Register section for full details): * Initiate calibration memory refresh. * Initiate a software reset. * WDT reset key. Using specific keys for initiating such actions as a calibration memory refresh or a device reset provides extra system robustness because it reduces the probability of either of these tasks being initiated in error. SOFTWARE RESET A software reset requires two consecutive writes to the key register, 0x15FA and 0xAF51, respectively. A reset of the device can be initiated via the hardware RESET pin, the software reset keys, or automatically after a WDT timeout (if configured to do so). The RESET_OCCURRED bit in the DIGITAL_DIAG_ RESULTS register flags when the device is reset. This bit defaults to 1 on power-up. Both of the diagnostic results registers implement a write 1 to clear feature; that is, a 1 must be written to this bit to clear it (see the Sticky Diagnostic Results Bits section). CALIBRATION MEMORY CRC For every calibration memory refresh cycle (which is initiated via a key code write to the key register or automatically initiated when the range bits, Bits[3:0] of the DAC_CONFIG register, are changed), an automatic CRC is calculated on the contents of the calibration memory shadow registers. The result of this CRC is compared with the factory stored reference CRC value. If the CRC values match, the read of the entire calibration memory is considered valid. If they do not match, the CAL_ MEM_CRC_ERR bit in the DIGITAL_DIAG_RESULTS register is set to 1. This feature is enabled by default and can be disabled via the CAL_MEM_CRC_EN bit in the DIGITAL_DIAG_CONFIG register. While this calibration memory refresh cycle is active, two stage readback commands are permitted, but a write to any register (other than the TWO_STAGE_READBACK_SELECT register or the NOP register) causes the INVALID_SPI_ACCESS_ERR bit in the DIGITAL_DIAG_RESULTS register to set. As described in the Programming Sequence to Enable the Output section, a wait period of 500 s is recommended after a calibration memory refresh cycle is initiated. Rev. B | Page 41 of 69 AD5758 Data Sheet INTERNAL OSCILLATOR DIAGNOSTICS An internal frequency monitor uses the internal oscillator (MCLK) to increment a 16-bit counter at a rate of 1 kHz (MCLK/10,000). The value of the counter is available to be read in the FREQ_ MONITOR register. The user can poll this register periodically and use it both as a diagnostic tool for the internal oscillator (to monitor that the oscillator is running), and to measure the frequency. This feature is enabled by default via the FREQ_ MON_EN bit in the DIGITAL_DIAG_CONFIG register. In the event that the internal MCLK oscillator stops, the AD5758 sends a specific code of 0x07DEAD to the SDO line for every SPI frame. This feature is enabled by default and can be disabled by clearing the OSC_STOP_DETECT_EN bit in the GP_CONFIG1 register. Note that this feature is limited to the maximum readback timing specifications as outlined in Table 3. STICKY DIAGNOSTIC RESULTS BITS The AD5758 contains two diagnostic results registers: digital and analog (see Table 44 and Table 45, respectively). The diagnostic result bits contained within these registers are sticky (R/W-1-C), that is, each bit needs a 1 to be written to it to clear it. A more appropriate word here is update rather than clear because if the fault is still present, even after writing a 1 to the bit in question, it does not clear to 0. Upon writing Logic 1 to the bit, it updates to its latest value, which is Logic 1 if the fault is still present and Logic 0 if the fault is no longer present. There are two exceptions to this R/W-1-C access within the DIGITAL_DIAG_RESULTS register: CAL_MEMORY_ UNREFRESHED and SLEW_BUSY. These flags automatically clear when the calibration memory refresh or output slew, respectively, is complete. The status register contains a DIG_DIAG_STATUS and ANA_DIAG_STATUS bit, which is the result of a logical OR of the diagnostic results bits contained in each of the diagnostic results registers. All analog diagnostic flag bits are included in the logical OR of the ANA_DIAG_STATUS bit and all digital diagnostic flag bits, with the exception of the SLEW_BUSY bit, are included in the logical OR of the DIG_DIAG_STATUS bit. The OR'd bits within the status register are read only and not sticky (R/W-1-C). BACKGROUND SUPPLY AND TEMPERATURE MONITORING Excessive die temperature and overvoltage are known to be related to common cause failures. These conditions can be monitored in a continuous fashion using comparators, eliminating the requirement to poll the ADC. exceeds the programmed limit, the relevant status bit in the ANALOG_DIAG_RESULTS register is set and the FAULT pin is asserted low. The low voltage supplies on the AD5758 are monitored via low power static comparators. This function is disabled by default and can be enabled via the COMPARATOR_CONFIG bits in the GP_CONFIG2 register. Note that the INT_EN bit in the DAC_CONFIG register must be set for the REFIN buffer to be powered up and for this node to be available to the REFIN comparator. The monitored nodes are REFIN, REFOUT, VLDO, and an internal AVCC voltage node (INT_AVCC). There is a status bit in the ANALOG_DIAG_RESULTS register corresponding to each monitored node. If any of the supplies exceed the upper or lower threshold values (see Table 16), the corresponding status bit is set. Note that, in the case of a REFOUT fault, the REFOUT_ERR status bit is set. In this case, the INT_AVCC, VLDO, and temperature comparator status bits may also become set because REFOUT is used as the comparison voltage for these nodes. Like all the other status bits in the ANALOG_ DIAG_RESULTS register, these bits are sticky and need a 1 to be written to them to clear them, assuming that the error condition subsided. If the error condition is still present, the flag remains high, even after a 1 is written to clear it. Table 16. Comparator Supply Activation Thresholds Supply INT_AVCC VLDO REFIN REFOUT Lower Threshold (V) 3.8 2.8 2.24 2.24 Nominal Value/Range (V) 4 to 5 3 to 3.6 2.5 2.5 Upper Threshold (V) 5.2 3.8 2.83 2.83 OUTPUT FAULT The AD5758 is equipped with a FAULT pin. This pin is an active low, open-drain output allowing several AD5758 devices to be connected together to one pull-up resistor for global fault detection. This pin is high impedance when no faults are detected and is asserted low when certain faults are detected, for example, an open circuit in current mode, a short circuit in voltage mode, a CRC error, or an overtemperature error. Table 17 shows the fault conditions that automatically force the FAULT pin active and highlights the user maskable fault bits available via the FAULT_PIN_CONFIG register (see Table 42). Note that all registers contain a corresponding FAULT pin status bit, FAULT_PIN_STATUS, that mirrors the inverted current state of the FAULT pin. For example, if the FAULT pin is active, the FAULT_PIN_STATUS bit is 1. Both die have a built-in temperature sensor with an accuracy of typically 5oC. The die temperature is monitored by a comparator. The background temperature comparator is permanently enabled. Programmable trip points corresponding to 142C, 127C, 112C, and 97C can be configured in the GP_CONFIG1 register. If the temperature of the either die Rev. B | Page 42 of 69 Data Sheet AD5758 Table 17. FAULT Pin Trigger Sources1 Fault Type Digital Diagnostic Faults Oscillator Stop Detect Calibration Memory Not Refreshed Reset Detected 3-Wire Interface Error WDT Error 3-Wire Read and Compare Parity Error DAC Latch Monitor Error Inverse DAC Check Error Calibration Memory CRC Error Invalid SPI Access SCLK Count Error Slip Bit Error SPI CRC Error Analog Diagnostic Faults VIOUT Overvoltage Error DC-to-DC Short Circuit Error DC-to-DC Power Error Current Output Open Circuit Error Voltage Output Short-Circuit Error DC-to-DC Die Temperature Error Main Die Temperature Error REFFOUT Comparator Error REFIN Comparator Error INT_AVCC Comparator Error VLDO Comparator Error 1 2 Mapped to FAULT Pin Mask Ability Yes No No Yes Yes Yes Yes N/A N/A No Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No No No No The DIG_DIAG_STATUS, ANA_DIAG_STATUS, and WDT_ STATUS bits of the status register are used in conjunction with the FAULT pin and the FAULT_PIN_STATUS bit to inform the user which one of the fault conditions caused the FAULT pin or the FAULT_PIN_STATUS bit to be activated. ADC MONITORING The AD5758 incorporates a 12-bit ADC to provide diagnostic information on user-selectable inputs, such as supplies, grounds, internal die temperatures, references, and external signals. See Table 18 for a full list of the selectable inputs. The reference used for the ADC is derived from REFOUT, providing a means of independence from the DAC reference (REFIN), if necessary. The ADC_CONFIG register configures the selection of the multiplexed ADC input channel via the ADC_IP_SELECT bits (see Table 41). ADC Transfer Function Equations The ADC has an input range of 0 V to 2.5 V and can be used to digitize a variety of different nodes. The set of inputs to the ADC encompasses both unipolar and bipolar ranges, varying from high to low voltage values. Therefore, to be able to digitize them, the voltage ranges outside of the 0 V to 2.5 V ADC input range must be divided down. The ADC transfer function equation is dependent on the selected ADC input node (see Table 18 for a summary of all transfer function equations). N/A means not applicable. Although the SCLK count error cannot be masked in the FAULT_PIN_CONFIG register, it can be excluded from the FAULT pin by enabling the SPI_DIAG_ QUIET_EN bit (Bit D3 in the GP_CONFIG1 register). Table 18. ADC Input Node Summary ADC_IP_SELECT 00000 00001 00010 00011 00100 00101 00110 01100 01101 01110 10000 10001 10010 10011 10100 10101 10110 VIN Node Description Main die temperature DC-to-dc die temperature Reserved REFIN Internal 1.23 V reference voltage (REF2) Reserved Reserved Reserved Voltage on the +VSENSE buffer output Voltage on the -VSENSE buffer output Reserved Reserved Reserved Reserved INT_AVCC VLDO VLOGIC ADC Transfer Function T (C) = (-0.09369 x D) + 307 T (C) = (-0.11944 x D) + 436 Reserved REFIN (V) = (D/212) x 2.75 REF2 (V) = (D/212) x 2.5 Reserved Reserved Reserved +VSENSE (V) = ((50 x D)/212) - 25 -VSENSE (V) = ((50 x D)/212) - 25 Reserved Reserved Reserved Reserved INT_AVCC (V) = D/212 x 10 VLDO (V) = D/212 x 10 VLOGIC (V) = D/212 x 10 Rev. B | Page 43 of 69 AD5758 ADC_IP_SELECT 11000 11001 11010 11011 11100 11101 11110 11111 Data Sheet VIN Node Description REFGND AGND DGND VDPC+ AVDD2 AVSS DC-to-dc die node; configured in the DCDC_CONFIG2 register 00: AGND on dc-to-dc die 01: internal 2.5 V supply on dc-to-dc die 10: AVDD1 11: reserved REFOUT AVDD2 AGND (dc-dc) (V) = (D/212) x 2.5 Internal 2.5 V (dc-dc) (V) = (D/212) x 5 AVDD1 (V) = D/212 x 37.5 Reserved REFOUT (V) = (D/212) x 2.5 AVDD1 AGND POWER MANAGEMENT BLOCK VLDO ADC Transfer Function REFGND (V) = D/212 x 2.5 AGND (V) = D/212 x 2.5 DGND (V) = D/212 x 2.5 VDPC+ (V) = D/212 x 37.5 AVDD2 (V) = D/212 x 37.5 AVSS (V) = (15 x D/212 - 14) x 2.5 MCLK 10MHz POWER-ON RESET SW+ CALIBRATION MEMORY TEMPERATURE, INTERNAL 2.5V SUPPLY, DC-TO-DC DIE TO GND INT_AVCC, REF2 VLOGIC DGND CLKOUT AD0 AD1 RESET LDAC SCLK SDI SYNC SDO FAULT DIGITAL BLOCK DC-TO-DC DIE 3-WIRE INTERFACE DATA AND CONTROL REGISTERS WATCHDOG TIMER PGND1 VDPC+ 16 DAC REG 16 VDPC+ 16-BIT DAC IOUT RANGE SCALING - RB IOUT RSET RA VX USER GAIN USER OFFSET HART_EN CHART STATUS REGISTER REFERENCE BUFFERS +VSENSE BUFFER REFIN BUFFER REFOUT REFOUT REFGND TEMPERATURE SENSOR VREF VOUT RANGE SCALING VDPC+ VOUT VIOUT -VSENSE 12-BIT ADC -VSENSE BUFFER ANALOG DIAGNOSTICS CCOMP AD5758 AVSS NOTES 1. GRAY ITEMS REPRESENT DIAGNOSTIC ADC INPUT NODES. Figure 84. Diagnostic ADC Input Nodes Rev. B | Page 44 of 69 +VSENSE 11840-041 REFIN Data Sheet AD5758 ADC Configuration ADC Conversion Timing The ADC muxed input is configured using the ADC_CONFIG register via ADC_IP_SELECT (Bits[4:0]). Figure 85 shows an example where autostatus readback mode is enabled. The status register always contains the last completed ADC conversion result, together with the associated mux address, ADC_IP_SELECT. Table 19. ADC Configuration Register D7 to D5 000 D4 to D0 ADC input select During the first ADC conversion command shown, the contents of the status register are available on the SDO line. The ADC portion of this data contains the conversion result of the previously converted ADC node (ADC Conversion Result 0), as well as the associated channel address. Assuming another SPI frame is not received while the ADC is busy converting due to Command 1, the next data to appear on the SDO line contains the associated conversion result, ADC Conversion Result 1. However, if an SPI frame is received while the ADC is busy, the status register contents available on SDO still contain the previous conversion result and indicates that the ADC_BUSY flag is high. Any new ADC conversion instructions received while the ADC_BUSY bit is active are ignored. This write to the ADC Configuration register initiates a single conversion on the node currently selected in the ADC input select bits of the ADC_CONFIG register. When a conversion is complete, the ADC result is available in the status register. If a node from the dc-to-dc die is required, perform this configuration using the DCDC_ADC_CONTROL_DIAG bits in the DCDC_CONFIG2 register before configuring the ADC. ADC CONVERSION TIME SCLK 1 1 24/ 32 24/ 32 SYNC INITIATE CONVERSION 1 ADC CONVERSION COMMAND NUMBER 2 ADC CONVERSION COMMAND NUMBER 1 SDI ASSUME AUTOSTATUS READBACK IS ALREADY ENABLED ADC CONVERSION RESULT NUMBER 1 ADC CONVERSION RESULT NUMBER 0 SDO CONTENTS OF STATUS REGISTER CLOCKED OUT 1 0 FAULT PIN DIG DIAG ANA DIAG CONTENTS OF STATUS REGISTER CLOCKED OUT WDT STATUS ADC BUSY ADC ADC ADC ADC ADC CHN[4] CHN[0] DATA[11] DATA[1] DATA[0] NOTES 1. STATUS REGISTER CONTENTS CONTAINING ADC CONVERSION RESULT, CORRESPONDING ADDRESS, AND ADC BUSY INDICATOR. Figure 85. ADC Conversion Timing Example Rev. B | Page 45 of 69 11840-034 D10 to D8 100 AD5758 Data Sheet REGISTER MAP WRITING TO REGISTERS The AD5758 is controlled and configured via 29 on-chip registers described in the Register Details section. The four possible access permissions are as follows: * * * * R/W: read/write R: read only R/W-1-C: read/write 1 to clear R0/W: read zero/write Reading from and writing to reserved registers is flagged as an invalid SPI access (see Table 44). When accessing registers with reserved bit fields, the default value of those bit fields must be written. These values are listed in the Reset column of Table 26 to Table 49. When writing to any register, the format in Table 20 is used. By default, the SPI CRC is enabled and the input register is 32 bits wide, with the last eight bits corresponding to the CRC code. Only frames of exactly 32 bits wide are accepted as valid. If CRC is disabled, the input register is 24 bits wide;, and 32-bit frames are also accepted, with the final 8 bits ignored. Table 21 describes the function of Bit D23 to Bit D16. Bit D15 to Bit D0 depend on the register that is being addressed. Table 20. Writing to a Register MSB D23 AD1 D22 AD1 D21 AD0 D20 REG_ADR4 D19 REG_ADR3 D18 REG_ADR2 D17 REG_ADR1 D16 REG_ADR0 LSB D15 to D0 Data Table 21. Input Register Decode Bit AD1 AD1, AD0 REG_ADR4, REG_ADR3, REG_ADR2, REG_ADR1, REG_ADR0 Description Slip bit. This bit must equal the inverse of Bit D22 (that is, AD1). Used in association with the external pins, AD1 and AD0, to determine which AD5758 device is being addressed by the system controller. Up to four unique devices can be addressed, corresponding to the AD1 and AD0 addresses of 0b00, 0b01, 0b10, and 0b11. Selects which register is written to. See Table 25 for a summary of the available registers. Rev. B | Page 46 of 69 Data Sheet AD5758 Two Stage Readback Mode READING FROM REGISTERS Two stage readback mode consists of a write to the TWO_ STAGE_READBACK_SELECT register to select the register location to be read back, followed by a NOP command. To perform a NOP command, write all zeros to Bits[D15:D0] of the NOP register. During the NOP command, the contents of the selected register are available on SDO in the format shown in Table 22. It is also possible to write a new two stage readback command during the second frame, such that the corresponding new data is available on SDO in the subsequent frame (see Figure 86). Bits[D31:D30] (or Bits[D23:D22], if SPI CRC is not enabled) = 0b10 are used as part of the synchronization during readback. The contents of the first write instruction to the TWO_ STAGE_READBACK_SELECT register is shown in Table 23. The AD5758 has four options for readback mode that can be configured in the TWO_STAGE_READBACK_SELECT register (see Table 43). These options are as follows: * * * * Two stage readback Autostatus readback Shared SYNC autostatus readback Echo mode Table 22. SDO Contents for Read Operation MSB D23 to D22 0b10 LSB D21 FAULT pin status D20 to 16 Register address D15 to D0 Data Table 23. Reading from a Register Using Two Stage Readback Mode D22 AD1 SCLK D21 AD0 D20 D19 24/ 32 1 D18 0x13 D17 D16 [D15:D5] Reserved 24/ 32 1 LSB D4 D3 D2 D1 D0 READBACK_SELECT[4:0] 24/ 32 1 SYNC SDI 2-STAGE READBACK *NOP INPUT WORD SPECIFIES REGISTER TO BE READ *ALTERNATIVELY COULD WRITE ANOTHER TWO-STAGE READBACK NOP SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 86. Two Stage Readback Example Rev. B | Page 47 of 69 SELECTED REGISTER DATA CLOCKED OUT 11840-037 MSB D23 AD1 AD5758 Data Sheet Autostatus Readback Mode contents differ from the format shown in Table 22. The contents of the status register are shown in Table 24. If autostatus readback mode is selected, the contents of the status register are available on the SDO line during every SPI transaction. When reading back the status register, the SDO The autostatus readback mode can be configured via the READBACK_MODE bits in the two stage readback select register (see the Two Stage Readback Select Register section). Table 24. SDO Contents for a Read Operation on the Status Register MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 to D12 D11 to D0 1 0 FAULT_PIN_STATUS DIG_DIAG_STATUS ANA_DIAG_STATUS WDT_STATUS ADC_BUSY ADC_CH[4:0] ADC_DATA[11:0] SCLK 1 24/ 32 1 24/ 32 1 24/ 32 SYNC SDI ANY WRITE COMMAND ANY WRITE COMMAND ANY WRITE COMMAND ASSUME AUTOSTATUS READBACK IS ALREADY ENABLED CONTENTS OF STATUS REGISTER CLOCKED OUT CONTENTS OF STATUS REGISTER CLOCKED OUT Figure 87. Autostatus Readback Example Rev. B | Page 48 of 69 CONTENTS OF STATUS REGISTER CLOCKED OUT 11840-038 SDO Data Sheet AD5758 Shared SYNC Autostatus Readback Mode Figure 88. The shared SYNC autostatus readback mode can be configured via the READBACK_MODE bits in the two stage readback select register (see the Two Stage Readback Select Register section). The shared SYNC autostatus readback is a special version of the autostatus readback mode used to avoid SDO bus contention when multiple AD5758 devices are sharing the same SYNC line (whereby AD5758 devices are distinguished from each other using the hardware address pins). After each valid write to a device, a flag is set. On the subsequent falling edge of SYNC, the flag is cleared. This mode behaves in a similar manner to the normal autostatus readback mode, except that the device does not output the status register contents on SDO when SYNC goes low, unless the internal flag is set (that is, the previous SPI write was valid). Refer to the example shown in SCLK 1 24/ 32 1 24/ 32 Echo Mode Echo mode behaves in a similar manner to the autostatus readback mode, except that every second readback consists of an echo of the previous command written to the AD5758. Echo mode is useful for checking which SPI instruction was received in the previous SPI frame. Echo mode can be configured via the READBACK_MODE bits in the two stage readback select register (see the Two Stage Readback Select Register section). 1 24/ 32 24/ 32 1 24/ 32 1 SYNC DEVICE 0 FLAG SET SDI VALID WR TO DEVICE 0 DEVICE 1 FLAG SET NO FLAG SET VALID WR TO DEVICE 1 INVALID WR TO DEVICE 0 DEVICE 0 STATUS REG DEVICE 1 STATUS REG DEVICE 0 FLAG SET VALID WR TO DEVICE 0 DEVICE 1 FLAG SET VALID WR TO DEVICE 1 DEVICE 0 STATUS REG Figure 88. Shared SYNC Autostatus Readback Example PREVIOUS COMMAND STATUS REGISTER CONTENTS Figure 89. SDO Contents--Echo Mode Rev. B | Page 49 of 69 PREVIOUS COMMAND 11840-040 SDO 11840-039 ASSUME SHARED SYNC AUTOSTATUS READBACK IS ALREAD Y ENABLED FOR BOTH DUTS AD5758 Data Sheet PROGRAMMING SEQUENCE TO ENABLE THE OUTPUT To write to and set up the device from a power-on or reset condition, use the following procedure: 1. 2. 3. 4. 5. 6. 7. Perform a hardware or software reset and wait 100 s. Perform a calibration memory refresh by writing 0xFCBA to the key register. Wait a minimum of 500 s before proceeding to Step 3 to allow time for the internal calibrations to complete. As an alternative to waiting 500 s for the refresh cycle to complete, poll the CAL_MEM_UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register until it is 0. Write 1 to Bit D13 in the DIGITAL_DIAG_RESULTS register to clear the RESET_OCCURRED flag. If CLKOUT is required, configure and enable this feature via the GP_CONFIG1 register. It is important to configure this feature before enabling the dc-to-dc converter. Write to the DCDC_CONFIG2 register to set the dc-to-dc current limit. Wait 300 s to allow the 3-wire interface communication to complete. As an alternative to waiting 300 s for the 3-wire interface communication to complete, poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. Write to the DCDC_CONFIG1 register to set up the dcto-dc converter mode (thereby enabling the dc-to-dc converter). Wait 300 s to allow the 3-wire interface communication to complete. As an alternative to waiting 300 s to the 3-wire interface communication to complete, poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0. Write to the DAC_CONFIG register to set the INT_EN bit (powers up the DAC and internal amplifiers without enabling the output) and configure the output range, internal/external RSET, and slew rate. Keep the OUT_EN bit disabled at this point. Wait 500 s minimum before proceeding to Step 8 to allow time for the internal calibrations to complete. As an alternative to waiting 500 s for the refresh cycle to complete, poll the CAL_MEM_ UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register until it is 0. 8. Write zero-scale DAC code to the DAC_INPUT register. (If a bipolar range was selected in Step 7, then a DAC code that represents a 0 mA/0 V output must be written to the DAC_INPUT register). It is important that this step be completed even if the contents of the DAC_INPUT register are not changing. 9. If LDAC functionality is being used, perform either a software or hardware LDAC command. 10. Rewrite the same word to the DAC_CONFIG register as in Step 7 except, this time, with the OUT_EN bit enabled. Allow 1.25 ms minimum between Step 6 and Step 9; this is the time from when the dc-to-dc is enabled to when the VIOUT output is enabled. 11. Write the required DAC code to the DAC_INPUT register. An example configuration is shown in Figure 90. Changing and Reprogramming the Range After the output is enabled, use the following recommended steps when changing the output range: 1. 2. 3. 4. 5. Rev. B | Page 50 of 69 Write to the DAC_INPUT register. Set the output to 0 mA or 0 V. Write to the DAC_CONFIG register. Disable the output (OUT_EN = 0), and set the new output range. Keep the INT_EN bit set. Wait 500 s minimum before proceeding to Step 3 to allow time for internal calibrations to complete. Write Code 0x0000 (in the case of bipolar ranges, write Code 0x8000) to the DAC_INPUT register. It is important that this step be completed even if the contents of the DAC_INPUT register are not changing. Reload the DAC_CONFIG register word from Step 2 except, this time, set the OUT_EN bit to 1 to enable the output. Write the required DAC code to the DAC_INPUT register. Data Sheet AD5758 EXAMPLE CONFIGURATION TO ENABLE THE OUTPUT CORRECTLY 1. PERFORM HARDWARE OR SOFTWARE RESET ADDRESS[D23:D21] WRITE 2. PERFORM CALIBRATION MEMORY REFRESH SLIPBIT + AD[1:0] REGISTER ADDRESS[D20:D16] DATA[D15:D0] 0x08 0xFCBA WAIT = 0 IS CAL_MEM_ UNREFRESHED == 0? NO IS WAIT = 500s? NO WAIT = WAIT + 1 3. CLEAR RESET_ OCCURRED BIT WRITE 4. CONFIGURE CLKOUT IF REQUIRED WRITE 5. SET UP THE DCTODC CONVERTER SETTINGS WRITE ADDRESS[D23:D21] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x14 D13 = 1 ADDRESS[D23:D21] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x09 GP CONFIG1 SETTINGS ADDRESS[D23:D21] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x0C DC-TO-DC SETTINGS WAIT = 0 IS BUSY_3WI == 0? NO IS WAIT = 300s? NO 6. SET UP THE DCTODC CONVERTER MODE WAIT = WAIT + 1 WRITE ADDRESS[D23:D20] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x0B DC-TO-DC MODE ADDRESS[D23:D21] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x06 D6 = 0 ADDRESS[D23:D21] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x01 DAC CODE ADDRESS[D23:D21] REGISTER ADDRESS[D19:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x07 0x1DAC ADDRESS[D23:D21] REGISTER ADDRESS[D19:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x06 D6 = 1 ADDRESS[D23:D21] REGISTER ADDRESS[D20:D16] DATA[D15:D0] SLIPBIT + AD[1:0] 0x01 DAC CODE WAIT = 0 IS BUSY_3WI = 0? NO IS WAIT = 300s? NO WAIT = WAIT + 1 WRITE 7. CONFIGURE THE DAC (OUTPUT DISABLED) WAIT = 0 NO IS WAIT = 500s? NO 8. WRITE 0mV/0mA DAC CODE 9. PERFORM AN LDAC COMMAND WAIT = WAIT + 1 WRITE WRITE 10. CONFIGURE THE DAC (OUTPUT ENABLED) WRITE 11. WRITE THE REQUIRED DAC CODE WRITE Figure 90. Example Configuration to Enable the Output Correctly (CRC Disabled for Simplicity) Rev. B | Page 51 of 69 11840-118 IS CAL_MEM_ UNREFRESHED = 0? AD5758 Data Sheet REGISTER DETAILS Table 25. Register Summary Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C Name NOP DAC_INPUT DAC_OUTPUT CLEAR_CODE USER_GAIN USER_OFFSET DAC_CONFIG SW_LDAC Key GP_CONFIG1 GP_CONFIG2 DCDC_CONFIG1 DCDC_CONFIG2 Reserved Reserved WDT_CONFIG DIGITAL_DIAG_CONFIG ADC_CONFIG FAULT_PIN_CONFIG TWO_STAGE_READBACK_SELECT DIGITAL_DIAG_RESULTS ANALOG_DIAG_RESULTS Status CHIP_ID FREQ_MONITOR Reserved Reserved Reserved DEVICE_ID_3 Description NOP register. DAC input register. DAC output register. Clear code register. User gain register. User offset register. DAC configuration register. Software LDAC register. Key register. General-Purpose Configuration 1 register. General-Purpose Configuration 2 register. DC-to-DC Configuration 1 register. DC-to-DC Configuration 2 register. Reserved (do not write to this register). Reserved (do not write to this register). WDT configuration register. Digital diagnostic configuration register. ADC configuration register. FAULT pin configuration register. Two stage readback select register. Digital diagnostic results register. Analog diagnostic results register. Status register. Chip ID register. Frequency monitor register. Reserved. Reserved. Reserved. Generic ID register. Rev. B | Page 52 of 69 Reset 0x000000 0x010000 0x020000 0x030000 0x04FFFF 0x058000 0x060C00 0x070000 0x080000 0x090204 0x0A0200 0x0B0000 0x0C100 0x0D0000 0x0E0000 0x0F0009 0x10005D 0x110000 0x120000 0x130000 0x14A000 0x150000 0x100000 0x170101 0x180000 0x190000 0x1A0000 0x1B0000 0x1C0000 Access R0/W R/W R R/W R/W R/W R/W R0/W R0/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W-1-C R/W-1-C R R R R R R R Data Sheet AD5758 NOP Register Address: 0x00, Reset: 0x000000, Name: NOP Write 0x0000 to Bits[D15:D0] at this address to perform a no operation (NOP) command. Bits[15:0] of this register always read back as 0x0000. Table 26. Bit Descriptions for NOP Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS NOP command Register address. Write 0x0000 to perform a NOP command. 0x0 0x0 R R0/W DAC Input Register Address: 0x01, Reset: 0x010000, Name: DAC_INPUT Bits[D15:D0] consists of the 16-bit data to be written to the DAC. If the LDAC pin is tied low (that is, active), the DAC_INPUT register contents are written directly to the DAC_OUTPUT register without any LDAC functionality dependence. If the LDAC pin is tied high, the contents of the DAC_INPUT register are written to the DAC_OUTPUT register when the LDAC pin is brought low or when the software LDAC command is written. Table 27. Bit Descriptions for DAC_INPUT Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS DAC_INPUT_DATA Register address. DAC input data. 0x0 0x0 R R/W DAC Output Register Address: 0x02, Reset: 0x020000, Name: DAC_OUTPUT DAC_OUTPUT is a read only register and contains the latest calibrated 16-bit DAC output value. If a clear event occurs due to a WDT fault, this register contains the clear code until the DAC is updated to another code. Table 28. Bit Descriptions for DAC_OUTPUT Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS DAC_OUTPUT_DATA Register address. DAC output data. For example, the last calibrated 16-bit DAC output value. 0x0 0x0 R R Clear Code Register Address: 0x03, Reset: 0x030000, Name: CLEAR_CODE When writing to the CLEAR_CODE register, Bits[D15:D0] consist of the clear code to which the DAC clears on the occurrence of a clear event (for example, a WDT fault). After a clear event, the DAC_INPUT register must be rewritten to with the 16-bit data to be written to the DAC, even if it is the same data as previously written before the clear event. Performing an LDAC write (either hardware or software) does not update the DAC_OUTPUT register to a new code until the DAC_INPUT register is first written to. Table 29. Bit Descriptions for CLEAR_CODE Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS CLEAR_CODE Register address. Clear code. The DAC clears to this code upon a clear event, for example, a WDT fault. 0x0 0x0 R R/W Rev. B | Page 53 of 69 AD5758 Data Sheet User Gain Register Address: 0x04, Reset: 0x04FFFF, Name: USER_GAIN The 16-bit USER_GAIN register allows the user to adjust the gain of the DAC channel in steps of 1 LSB. The USER_GAIN register coding is straight binary. The default code is 0xFFFF. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy. Table 30. Bit Descriptions for USER_GAIN Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS USER_GAIN Register address. User gain correction code. 0x0 0xFFFF R R/W User Offset Register Address: 0x05, Reset: 0x058000, Name: USER_OFFSET The 16-bit USER_OFFSET register allows the user to adjust the offset of the DAC channel by -32,768 LSBs to +32,768 LSBs in steps of 1 LSB. The USER_OFFSET register coding is straight binary. The default code is 0x8000, which results in zero offset programmed to the output. Table 31. Bit Descriptions for USER_OFFSET Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS USER_OFFSET Register address. User offset correction code. 0x0 0x8000 R R/W DAC Configuration Register Address: 0x06, Reset: 0x060C00, Name: DAC_CONFIG This register configures the DAC (range, internal/external RSET, and output enable), enables the output stage circuitry, and configures the slew rate control function. Table 32. Bit Descriptions for DAC_CONFIG Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:13] REGISTER_ADDRESS SR_STEP 0x0 0x0 R R/W [12:9] SR_CLOCK Register address. Slew rate step. In conjunction with the slew rate clock, the slew rate step defines by how much the output value changes at each update. Together, both parameters define the rate of change of the output value. 000: 4 LSB (default). 001: 12 LSB. 010: 64 LSB. 011: 120 LSB. 100: 256 LSB. 101: 500 LSB. 110: 1820 LSB. 111: 2048 LSB. Slew rate clock. Slew rate clock defines the rate at which the digital slew is updated. 0000: 240 kHz. 0001: 200 kHz. 0010: 150 kHz. 0011: 128 kHz. 0100: 64 kHz. 0101: 32 kHz. 0110: 16 kHz (default). 0111: 8 kHz. 0x6 R/W Rev. B | Page 54 of 69 Data Sheet Bits Bit Name 8 SR_EN 7 RSET_EXT_EN 6 OUT_EN 5 INT_EN 4 OVRNG_EN [3:0] Range AD5758 Description 1000: 4 kHz. 1001: 2 kHz. 1010: 1 kHz. 1011: 512 Hz. 1100: 256 Hz. 1101: 128Hz. 1110: 64 Hz. 1111: 16 Hz. Enable slew rate control. 0: disable (default). 1: enable. Enable external current setting resistor. 0: select internal RSET resistor (default). 1: select external RSET resistor. Enable VIOUT. 0: disable VIOUT output (default). 1: enable VIOUT output. Enable internal buffers. 0: disable (default). 1: enable. Setting this bit powers up the DAC and internal amplifiers. Setting this bit does not enable the output. It is recommended to set this bit and allow a >200 s delay before enabling the output. This delay results in a reduced output enable glitch. Enable 20% voltage overrange. 0: disable (default). 1: enable. Select output range. Note that changing the contents of the range bits initiates an internal calibration memory refresh and, therefore, a subsequent SPI write must not be performed until the CAL_MEM_UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register returns to 0. Writes to invalid range codes are ignored. 0000: 0 V to 5 V voltage range (default). 0001: 0 V to 10 V voltage range. 0010: 5 V voltage range. 0011: 10 V voltage range. 1000: 0 mA to 20 mA current range. 1001: 0 mA to 24 mA current range. 1010: 4 mA to 20 mA current range. 1011: 20 mA current range. 1100: 24 mA current range. 1101: -1 mA to +22 mA current range. Reset Access 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Software LDAC Register Address: 0x07, Reset: 0x070000, Name: SW_LDAC Writing 0x1DAC to this register performs a software LDAC update on the device matching the ADDRESS bits within the SPI frame. If the GLOBAL_SW_LDAC bit in the GP_CONFIG2 register is set, the AD0 and AD1 bits are ignored and all devices sharing the same SPI bus are updated via the SW_LDAC command. Bits[15:0] of this register always read back as 0x0000. Table 33. Bit Descriptions for SW_LDAC Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS LDAC_COMMAND Register address. Software LDAC. Write 0x1DAC to this register to perform a software LDAC instruction. 0x0 0x0 R R0/W Rev. B | Page 55 of 69 AD5758 Data Sheet Key Register Address: 0x08, Reset: 0x080000, Name: Key This register accepts specific key codes to perform tasks such as calibration memory refresh and software reset. Bits[15:0] of this register always read back as 0x0000. All unlisted key codes are reserved. Table 34. Bit Descriptions for Key Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS KEY_CODE Register address. Key code. 0x15FA: first of two keys to initiate a software reset. 0xAF51: second of two keys to initiate a software reset. 0x0D06: key to reset the WDT. 0xFCBA: key to initiate a calibration memory refresh to the shadow registers. This key is only valid the first time it is run and has no effect if subsequent writes occur within a given system reset cycle. 0x0 0x0 R R0/W General-Purpose Configuration 1 Register Address: 0x09, Reset: 0x090204, Name: GP_CONFIG1 This register is used to configure functions such as the temperature comparator threshold and CLKOUT, as well as enabling other miscellaneous features. Table 35. Bit Descriptions for GP_CONFIG1 Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:14] [13:12] REGISTER_ADDRESS Reserved SET_TEMP_THRESHOLD 0x0 0x0 0x0 R R R/W [11:10] CLKOUT_CONFIG 0x0 R/W [9:7] CLKOUT_FREQ 0x4 R/W 6 HART_EN Register address. Reserved. Do not alter the default value of this bit. Set the temperature comparator threshold value. 00: 142C (default). 01: 127C. 10: 112C. 11: 97C. Configure the CLKOUT pin. 00: disable; no clock is output on the CLKOUT pin (default). 01: enable; clock is output on CLKOUT pin according to the CLKOUT_FREQ bits (Bits[9:7]). 10: reserved (do not select this option). 11: reserved (do not select this option). Configure the frequency of CLKOUT. 000: 416 kHz. 001: 435 kHz. 010: 454 kHz. 011: 476 kHz. 100: 500 kHz (default). 101: 526 kHz. 110: 555 kHz. 111: 588 kHz. Enable the path to the CHART pin. 0: output of the DAC drives the output stage directly (default). 1: CHART path is coupled to the DAC output to allow a HART modem connection or connection of a slew capacitor. 0x0 R/W Rev. B | Page 56 of 69 Data Sheet Bits 5 Bit Name NEG_OFFSET_EN 4 CLEAR_NOW_EN 3 SPI_DIAG_QUIET_EN 2 OSC_STOP_DETECT_EN 1 0 Reserved Reserved AD5758 Description Enable negative offset in unipolar VOUT mode. When set, this bit offsets the currently enabled unipolar output range by the value listed here. This bit is only applicable to the 0 V to 6 V range and the 0 V to 12 V range. The 0 V to 6 V range becomes -300 mV to 5.7 V; the 0 V to 12 V range becomes -400 mV to 11.6 V. 0: disable (default). 1: enable. Enables clear to occur immediately, even if the output slew feature is currently enabled. 0: disable (default). 1: enable. Enable SPI diagnostic quiet mode. When this bit is enabled, SPI_CRC_ERR, SLIPBIT_ERR, and SCLK_COUNT_ERR are not included in the logical OR calculation, which creates the DIG_DIAG_STATUS bit in the status register. They are also masked from affecting the FAULT pin if this bit is set. 0: disable (default). 1: enable. Enable automatic 0x07DEAD code on SDO if the internal oscillator (MCLK) stops. 0: disable. 1: enable (default). Reserved. Do not alter the default value of this bit. Reserved. Do not alter the default value of this bit. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 0x0 R/W R/W General-Purpose Configuration 2 Register Address: 0x0A, Reset: 0x0A0200, Name: GP_CONFIG2 This register is used to configure and enable functions such as the voltage comparators and the global software LDAC. Table 36. Bit Descriptions for GP_CONFIG2 Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] 15 [14:13] REGISTER_ADDRESS Reserved COMPARATOR_CONFIG 0x0 0x0 0x0 R R0 R/W 12 11 10 Reserved Reserved GLOBAL_SW_LDAC 0x0 0x0 0x0 R/W R/W R/W 9 FAULT_TIMEOUT 0x1 R/W [8:5] Reserved Register address. Reserved. Do not alter the default value of this bit. Enable/disable the voltage comparator inputs for test purposes. The temperature comparator is permanently enabled. See the Background Supply and Temperature Monitoring section. 00: disable voltage comparators (default). 01: reserved. 10: reserved. 11: enable voltage comparators. The INT_EN bit in the DAC_CONFIG register must be set for the REFIN buffer to be powered up and this node available to the REFIN comparator. Reserved. Do not alter the default value of this bit. Reserved. Do not alter the default value of this bit. When enabled, the address bits are ignored when performing a software LDAC command, enabling multiple devices to be simultaneously updated using one SW_LDAC command. 0: disable (default). 1: enable. Enable reduced fault detect timeout. This bit configures the delay from when the analog block indicates a VIOUT fault has been detected to the associated change of the relevant bit in the ANALOG_DIAG_RESULTS register. This feature provides flexibility to accommodate a variety of output load values. 0: fault detect timeout = 25 ms. 1: fault detect timeout = 6.5 ms (default). Reserved. Do not alter the default value of these bits. 0x0 R/W Rev. B | Page 57 of 69 AD5758 Bits 4 3 2 1 0 Data Sheet Bit Name Reserved Reserved Reserved Reserved Reserved Description Reserved. Do not alter the default value of this bit. Reserved. Do not alter the default value of this bit. Reserved. Do not alter the default value of this bit. Reserved. Do not alter the default value of this bit. Reserved. Do not alter the default value of this bit. Reset 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W DC-to-DC Configuration 1 Register Address: 0x0B, Reset: 0x0B0000, Name: DCDC_CONFIG1 This register is used to configure the dc-to-dc controller mode. Table 37. Bit Descriptions for DCDC_CONFIG1 Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:8] 7 [6:5] REGISTER_ADDRESS Reserved Reserved DCDC_MODE 0x0 0x0 0x0 0x0 R R0 R/W R/W [4:0] DCDC_VPROG Register address. Reserved. Do not alter the default value of these bits. Reserved. Do not alter the default value of this bit. These two bits configure the dc-to-dc converters. 00: DC-to-DC converter powered off (default). 01: DPC current mode. The positive DPC rail tracks the headroom of the current output buffer. 10: DPC voltage mode. The positive DPC rail is regulated to 15 V with respect to -VSENSE. 11: PPC current mode. VDPC+ is regulated to a user programmable level between 5 V and 25.677 V (depending on the DCDC_VPROG bits, Bits[4:0]) with respect to -VSENSE. The ENABLE_PPC_BUFFERS bit (Bit 11 in the ADC_CONFIG register) must be set prior to enabling PPC current mode. DC-to-dc programmed voltage in PPC mode. VDPC+ is regulated to a user programmable level between 5 V (0b00000) and 25.677 V (0b11111), in steps of 0.667 V. VDPC+ is regulated with respect to -VSENSE. 0x0 R/W DC-to-DC Configuration 2 Register Address: 0x0C, Reset: 0x0C0100, Name: DCDC_CONFIG2 This register configures various dc-to-dc die features, such as the dc-to-dc converter current limit and the dc-to-dc die node, to be multiplexed to the ADC. Table 38. Bit Descriptions for DCDC_CONFIG2 Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:13] 12 REGISTER_ADDRESS Reserved BUSY_3WI 0x0 0x0 0x0 R R0 R 11 INTR_SAT_3WI 0x0 R 10 DCDC_READ_COMP_DIS Register address. Reserved. Do not alter the default value of these bits. Three-wire interface busy indicator. 0: 3-wire interface not currently active. 1: 3-wire interface busy. Three-wire interface saturation flag. This flag is set to 1 when the interrupt detection circuitry is automatically disabled due to six consecutive interrupt signals. A write to either of the dc-to-dc configuration registers clears this bit to 0. Disable 3-wire interface read and compare cycle. This read and compare cycle ensures that the contents of the copy of the dc-to-dc configuration registers on the main die match the contents on the dc-to-dc die. 0: enable automatic read and compare cycle (default). 0x0 R/W Rev. B | Page 58 of 69 Data Sheet AD5758 Bits Bit Name [9:8] 7 Reserved VIOUT_OV_ERR_DEGLITCH 6 VIOUT_PULLDOWN_EN [5:4] DCDC_ADC_CONTROL_DIAG [3:1] DCDC_ILIMIT 0 Reserved Description 1: when set, this bit disables the automatic read and compare cycle after each 3-wire interface write. Reserved. Do not alter the default value of these bits. Adjust the deglitch time on VIOUT overvoltage error flag. 0: deglitch time set to 1.02 ms (default). 1: deglitch time set to 128 s. Enable the 30 k resistor to ground on VIOUT. 0: disable (default). 1: enable. Select which dc-to-dc die node is multiplexed to the ADC on the main die. 00: AGND on dc-to-dc die. 01: internal 2.5 V supply on dc-to-dc die. 10: AVDD1. 11: reserved (do not select this option). These three bits set the dc-to-dc converter current limit. 000: 150 mA (default). 001: 200 mA. 010: 250 mA. 011: 300 mA. 100: 350 mA. 101: 400 mA. 110: 400 mA. 111: 400 mA. Reserved. Do not alter the default value of this bit. Reset Access 0x1 0x0 R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Watchdog Timer (WDT) Configuration Register Address: 0x0F, Reset: 0x0D0009, Name: WDT_CONFIG This register configures the WDT timeout values. This register also configures the WDT setup in terms of acceptable resets and the resulting response to a WDT fault (for example, clear the output or reset the device). Table 39. Bit Descriptions for WDT_CONFIG Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:11] 10 REGISTER_ADDRESS Reserved CLEAR_ON_WDT_FAIL 0x0 0x0 0x0 R R R/W 9 RESET_ON_WDT_FAIL 0x0 R/W 8 KICK_ON_VALID_WRITE 0x0 R/W 7 6 Reserved WDT_EN 0x0 0x0 R/W R/W [5:4] Reserved Register address. Reserved. Do not alter the default value of these bits. Enable clear on WDT fault. If the WDT times out, a clear event occurs, whereby the output is loaded with the clear code stored in the CLEAR_CODE register. 0: disable (default). 1: enable. Enable a software reset to automatically occur if the WDT times out. 0: disable (default). 1: enable. Enable any valid SPI command to reset the WDT. Any active WDT error flags must be cleared before the WDT can be restarted. 0: disable (default). 1: enable. Reserved. Do not alter the default value of this bit. Enables the WDT, then starts the WDT, assuming there are no active WDT fault flags. 0: disable (default). 1: enable. Reserved. Do not alter the default value of these bits. 0x0 R/W Rev. B | Page 59 of 69 AD5758 Bits [3:0] Bit Name WDT_TIMEOUT Data Sheet Description Set the WDT timeout value. Setting WDT_TIMEOUT to a binary value beyond 0b1010 results in the default setting of 1 sec. 0000: 1 ms. 0001: 5 ms. 0010: 10 ms. 0011: 25 ms. 0100: 50 ms. 0101: 100 ms. 0110: 250 ms. 0111: 500 ms. 1000: 750 ms. 1001: 1 sec (default). 1010: 2 sec. Reset 0x9 Access R/W Digital Diagnostic Configuration Register Address: 0x10, Reset: 0x10005D, Name: DIGITAL_DIAG_CONFIG This register configures various digital diagnostic features of interest for a particular application. Table 40. Bit Descriptions for DIGITAL_DIAG_CONFIG Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:9] [8:7] 6 REGISTER_ADDRESS Reserved Reserved DAC_LATCH_MON_EN 0x0 0x0 0x0 0x1 R R0 R/W R/W 5 4 Reserved INVERSE_DAC_CHECK_EN 0x0 0x1 R/W R/W 3 CAL_MEM_CRC_EN 0x1 R/W 2 FREQ_MON_EN 0x1 R/W 1 0 Reserved SPI_CRC_EN Register address. Reserved. Do not alter the default value of these bits. Reserved. Do not alter the default value of these bits. Enable a diagnostic monitor on the DAC latches. This feature monitors the actual digital code driving the DAC and compares it with the digital code generated within the digital block. Any difference between the two codes causes the DAC_LATCH_MON_ERR flag to be set in the DIGITAL_DIAG_RESULTS register. 0: disable. 1: enable (default). Reserved. Do not alter the default value of this bit. Enable check for DAC code vs. inverse DAC code error. 0: disable. 1: enable (default). Enable CRC of calibration memory on a calibration memory refresh. 0: disable. 1: enable (default). Enable the internal frequency monitor on the internal oscillator (MCLK). 0: disable. 1: enable (default). Reserved. Do not alter the default value of this bit. Enable SPI CRC function. 0: disable. 1: enable (default). 0x0 0x1 R/W R/W Rev. B | Page 60 of 69 Data Sheet AD5758 ADC Configuration Register Address: 0x11, Reset: 0x110000, Name: ADC_CONFIG This register configures the ADC into one of four modes of operation: key sequencing, automatic sequencing, single immediate conversion of the currently selected ADC_IP_SELECT node, or single-key conversion. Table 41. Bit Descriptions for ADC_CONFIG Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:12] 11 [10:8] REGISTER_ADDRESS Reserved ENABLE_PPC_BUFFERS SEQUENCE_COMMAND 0x0 0x0 0x0 0x0 R R/W R/W R/W [7:5] [4:0] Reserved ADC_IP_SELECT Register address. Do not alter the default value. Reserved. Do not alter the default value of these bits. Enable the sense buffers for PPC mode. ADC sequence command bits. 000: reserved (do not select this option). 001: reserved (do not select this option). 010: reserved (do not select this option). 011: reserved (do not select this option). 100: initiate a single conversion on the ADC_IP_SELECT (Bits[4:0]) input. 101: reserved (do not select this option). 110: reserved (do not select this option). 111: reserved (do not select this option). Reserved. Do not alter the default value of these bits. Select which node to multiplex to the ADC. All unlisted 5-bit codes are reserved and return an ADC result of zero. 00000: Main die temperature. 00001: DC-to-dc die temperature. 00010: Reserved (do not select this option). 00011: REFIN. The INT_EN bit in the DAC_CONFIG register must be set for the REFIN buffer to be powered up and this node to be available to the ADC. 00100: REF2; internal 1.23 V reference voltage. 00101: Reserved (do not select this option). 00110: Reserved (do not select this option). 01100: Reserved (do not select this option). 01101: Voltage on the +VSENSE buffer output. 01110: Voltage on the -VSENSE buffer output 10000: Reserved (do not select this option). 10001: Reserved (do not select this option). 10010: Reserved (do not select this option). 10011: Reserved (do not select this option). 10100: INT_AVCC. 10101: VLDO. 10110: VLOGIC. 11000: REFGND. 11001: AGND. 11010: DGND. 11011: VDPC+. 11100: AVDD2. 11101: AVSS. 11110: DC-to-dc die node; configured in the DCDC_CONFIG2 register. 11111: REFOUT. 0x0 0x0 R/W R/W Rev. B | Page 61 of 69 AD5758 Data Sheet FAULT Pin Configuration Register Address: 0x12, Reset: 0x120000, Name: FAULT_PIN_CONFIG This register is used to mask particular fault bits from the FAULT pin, if so desired. Table 42. Bit Descriptions for FAULT_PIN_CONFIG Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] 15 REGISTER_ADDRESS INVALID_SPI_ACCESS_ERR Register address. If this bit is set, do not map the INVALID_SPI_ACCESS_ERR fault flag to the FAULT pin. 0x0 0x0 R R/W 14 VIOUT_OV_ERR If this bit is set, do not map the VIOUT_OV_ERR fault flag to the FAULT pin. 0x0 R/W 13 12 Reserved INVERSE_DAC_CHECK_ERR Reserved. Do not alter the default value of this bit. If this bit is set, do not map the INVERSE_DAC_CHECK_ERR flag to the FAULT pin. 0x0 0x0 R/W R/W 11 10 Reserved OSCILLATOR_STOP_DETECT Reserved. Do not alter the default value of this bit. If this bit is set, do not map the clock stop error to the FAULT pin. 0x0 0x0 R/W R/W 9 DAC_LATCH_MON_ERR If this bit is set, do not map the DAC_LATCH_MON_ERR fault flag to the FAULT pin. 0x0 R/W 8 WDT_ERR If this bit is set, do not map the WDT_ERR flag to the FAULT pin. 0x0 R/W 7 SLIPBIT_ERR If this bit is set, do not map the SLIPBIT_ERR error flag to the FAULT pin. 0x0 R/W 6 5 4 SPI_CRC_ERR Reserved DCDC_P_SC_ERR If this bit is set, do not map the SPI_CRC_ERR error flag to the pin. Reserved. Do not alter the default value of this bit. If this bit is set, do not map the positive rail dc-to-dc short circuit error flag to the FAULT pin. 0x0 0x0 0x0 R/W R/W R/W 3 IOUT_OC_ERR If this bit is set, do not map the current output open-circuit error flag to the FAULT pin. 0x0 R/W 2 VOUT_SC_ERR If this bit is set, do not map the voltage output short-circuit error flag to the FAULT pin. 0x0 R/W 1 DCDC_DIE_TEMP_ERR If this bit is set, do not map the dc-to-dc die temperature error flag to the FAULT pin. 0x0 R/W 0 MAIN_DIE_TEMP_ERR If this bit is set, do not map the main die temperature error flag to the FAULT pin. 0x0 R/W Two Stage Readback Select Register Address: 0x13, Reset: 0x130000, Name: TWO_STAGE_READBACK_SELECT This register selects the address of the register required for a two stage readback operation. The address of the register selected for readback is stored in Bits[D4:D0]. Table 43. Bit Descriptions for TWO_STAGE_READBACK_SELECT Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:7] [6:5] REGISTER_ADDRESS Reserved READBACK_MODE 0x0 0x0 0x0 R R R/W [4:0] READBACK_SELECT Register address. Reserved. These bits control the SPI readback mode. 0: two stage SPI readback mode (default). 01: autostatus readback mode: the status register contents are shifted out on SDO for every SPI frame. 10: shared SYNC autostatus readback mode. This mode allows the use of a shared SYNC line on multiple devices (distinguished using the hardware address pins). After each valid write to a device, a flag is set. This mode behaves similar to the normal autostatus readback mode, except that the device does not output the status register contents on SDO as SYNC goes low, unless the internal flag is set (that is, the previous SPI write is valid). 11: the status register contents and the previous SPI frame instruction are alternately available on SDO. Select readback address for a two stage readback. 0x00: NOP register (default). 0x01: DAC_INPUT register. 0x02: DAC_OUTPUT register. 0x0 R/W Rev. B | Page 62 of 69 Data Sheet Bits Bit Name AD5758 Description 0x03: CLEAR_CODE register. 0x04: USER_GAIN register. 0x05: USER_OFFSET register. 0x06: DAC_CONFIG register. 0x07: SW_LDAC register. 0x08: Key register. 0x09: GP_CONFIG1 register. 0x0A: GP_CONFIG2 register. 0x0B: DCDC_CONFIG1 register. 0x0C: DCDC_CONFIG2 register. 0x0D: Reserved (do not select this option). 0x0E: Reserved (do not select this option). 0x0F: WDT_CONFIG register. 0x10: DIGITAL_DIAG_CONFIG register. 0x11: ADC_CONFIG register. 0x12: FAULT_PIN_CONFIG register. 0x13: TWO_STAGE_READBACK_SELECT register. 0x14: DIGITAL_DIAG_RESULTS register. 0x15: ANALOG_DIAG_RESULTS register. 0x16: Status register. 0x17: CHIP_ID register. 0x18: FREQ_MONITOR register. 0x19: Reserved (do not select this option). 0x1A: Reserved (do not select this option). 0x1B: Reserved (do not select this option). 0x1C: DEVICE_ID_3 register. Reset Access Digital Diagnostic Results Register Address: 0x14, Reset: 0x14A000, Name: DIGITAL_DIAG_RESULTS This register contains an error flag for the on-chip digital diagnostic features, most of which are configurable using the digital diagnostic configuration register. This register also contains a flag to indicate that a reset occurred, as well as a flag to indicate that the calibration memory has not refreshed or an invalid SPI access attempted. With the exception of the CAL_MEM_UNREFRESHED and SLEW_BUSY flags, all of these flags require a 1 to be written to them to update them to their current value. The CAL_MEM_UNREFRESHED and SLEW_BUSY flags automatically clear when the calibration memory refresh or output slew, respectively, is complete. When the corresponding enable bits in the DIGITAL_DIAG_CONFIG register are not enabled, the respective flag bits read as zero. Table 44. Bit Descriptions for DIGITAL_DIAG_RESULTS Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] 15 REGISTER_ADDRESS CAL_MEM_UNREFRESHED 0x0 0x1 R R 14 SLEW_BUSY 0x0 R 13 12 11 10 RESET_OCCURRED ERR_3WI WDT_ERR Reserved Register address. Calibration memory unrefreshed flag. Note that modifying the range bits in the DAC_CONFIG register also initiates a calibration memory refresh, which asserts this bit. Unlike the R/W-1-C bits in this register, this bit is automatically cleared after the calibration memory refresh completes. 0: calibration memory is refreshed. 1: calibration memory is unrefreshed (default on power-up). Note that this bit asserts if the range bits are modified in the DAC_CONFIG register. This flag is set to 1 when the DAC is actively slewing. Unlike the R/W-1-C bits in this register, this bit is automatically cleared when slewing is complete. This bit flags that a reset occurred (default on power-up is therefore Logic 1). This bit flags an error in the interdie 3-wire interface communications. This bit flags a WDT fault. Reserved. 0x1 0x0 0x0 0x0 R/W-1-C R/W-1-C R/W-1-C R/W-1-C Rev. B | Page 63 of 69 AD5758 Data Sheet Bits 9 Bit Name 3WI_RC_ERR 8 7 6 DAC_LATCH_MON_ERR Reserved INVERSE_DAC_CHECK_ERR 5 CAL_MEM_CRC_ERR 4 INVALID_SPI_ACCESS_ERR 3 2 Reserved SCLK_COUNT_ERR 1 SLIPBIT_ERR 0 SPI_CRC_ERR Description This bit flags an error if the 3-wire read and compare process is enabled and a parity error occurs. This bit flags if the output of the DAC latches does not match the input. Reserved. This bit flags if a fault it detected between the DAC code driven by the digital core and an inverted copy. This bit flags a CRC error for the CRC calculation of the calibration memory upon refresh. This bit flags if an invalid SPI access is attempted, such as writing to or reading from an invalid or reserved address. This bit also flags if an SPI write is attempted directly after powering up but before a calibration memory refresh is performed or if an SPI write is attempted while a calibration memory refresh is in progress. Performing a two stage readback is permitted during a calibration memory refresh and does not cause this flag to set. Attempting to write to a read only register also causes this bit to assert. Reserved. This bit flags an SCLK falling edge count error. 32 clocks are required if SPI CRC is enabled and 24 clocks or 32 clocks are required if SPI CRC is not enabled. This bit flags an SPI frame slip bit error, that is, the MSB of the SPI word is not equal to the inverse of MSB - 1. This bit flags an SPI CRC error. Reset 0x0 Access R/W-1-C 0x0 0x0 0x0 R/W-1-C R/W-1-C R/W-1-C 0x0 R/W-1-C 0x0 R/W-1-C 0x0 0x0 R/W-1-C R/W-1-C 0x0 R/W-1-C 0x0 R/W-1-C Analog Diagnostic Results Register Address: 0x15, Reset: 0x150000, Name: ANALOG_DIAG_RESULTS This register contains an error flag corresponding to the four voltage nodes (VLDO, INT_AVCC, REFIN, and REFOUT) monitored in the background by comparators, as well as a flag for each die temperature, which is also monitored by comparators. Voltage output short circuit, current output open circuit and dc-to-dc error flags are also contained in this register. Like the DIGITAL_DIAG_RESULTS register, all of the flags contained in this register require a 1 to be written to them to update or clear them. When the corresponding diagnostic features are not enabled, the respective error flags are read as zero. Table 45. Bit Descriptions for ANALOG_DIAG_RESULTS Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:14] 13 12 11 10 9 REGISTER_ADDRESS Reserved VIOUT_OV_ERR Reserved DCDC_P_SC_ERR Reserved DCDC_P_PWR_ERR 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R R0 R/W-1-C R/W-1-C R/W-1-C R/W-1-C R/W-1-C 8 7 Reserved IOUT_OC_ERR 0x0 0x0 R/W-1-C R/W-1-C 6 5 4 3 VOUT_SC_ERR DCDC_DIE_TEMP_ERR MAIN_DIE_TEMP_ERR REFOUT_ERR 0x0 0x0 0x0 0x0 R/W-1-C R/W-1-C R/W-1-C R/W-1-C 2 1 REFIN_ERR INT_AVCC_ERR Register address. Reserved. This bit flags if the voltage at the VIOUT pin goes outside of the VDPC+ rail or AVSS rail. Reserved. This bit flags a dc-to-dc short-circuit error for the positive rail dc-to-dc circuit. Reserved. This bit flags a dc-to-dc regulation fault, that is, the dc-to-dc circuitry cannot reach the target VDPC+ voltage due to an insufficient AVDD1 voltage. Reserved. This bit flags a current output open circuit error. This error bit is set in the case of a current output open circuit and in the case where there is insufficient headroom available to the internal current output driver circuitry to provide the programmed output current. This bit flags a voltage output short-circuit error. This bit flags an overtemperature error for the dc-to-dc die. This bit flags an overtemperature error for the main die. This bit flags that the REFOUT node is outside of the comparator threshold levels or if its short-circuit current limit occurs. This bit flags that the REFIN node is outside of the comparator threshold levels. This bit flags that the INT_AVCC node is outside of the comparator threshold levels. 0x0 0x0 R/W-1-C R/W-1-C Rev. B | Page 64 of 69 Data Sheet Bits 0 Bit Name VLDO_ERR AD5758 Description This bit flags that the VLDO node is outside of the comparator threshold levels or if its short-circuit current limit occurs. Reset 0x0 Access R/W-1-C Status Register Address: 0x16, Reset: 0x100000, Name: Status This register contains ADC data and status bits, as well as the WDT, OR'd analog and digital diagnostics, and the FAULT pin status bits. Table 46. Bit Descriptions for Status Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R 20 DIG_DIAG_STATUS 0x1 R 19 ANA_DIAG_STATUS 0x0 R 18 17 [16:12] [11:0] WDT_STATUS ADC_BUSY ADC_CH ADC_DATA This bit represents the result of a logical OR of the contents of Bits[15:0] in the DIGITAL_DIAG_RESULTS register, with the exception of the SLEW_BUSY bit. Therefore, if any of these bits are high, the DIG_DIAG_STATUS bit is high. Note that this bit is high on power-up due to the active RESET_OCCURRED flag. A quiet mode is also available (SPI_DIAG_QUIET_EN in the GP_CONFIG1 register), such that the logical OR function only incorporates Bits[D15:D3] of the DIGITAL_DIAG_RESULTS register (with the exception of the SLEW_BUSY bit). If an SPI CRC, SPI slip bit, or SCLK count error occurs, the DIG_DIAG_STATUS bit is not set high. This bit represents the result of a logical OR of the contents of Bits[13:0] in the ANALOG_DIAG_RESULTS register. Therefore, if any bit in this register is high, the ANA_DIAG_STATUS bit is high. WDT status bit. ADC busy status bit. Address of the ADC channel represented by the ADC_DATA bits in the status register. 12 bits of ADC data representing the converted signal addressed by the ADC_CH bits, Bits[4:0]. 0x0 0x0 0x0 0x0 R R R R Chip ID Register Address: 0x17, Reset: 0x170101, Name: CHIP_ID This register contains the silicon revision ID of both the main die and the dc-to-dc die. Table 47. Bit Descriptions for CHIP_ID Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:11] [10:8] [7:0] REGISTER_ADDRESS Reserved DCDC_DIE_CHIP_ID MAIN_DIE_CHIP_ID Register address. Reserved. These bits reflect the silicon revision number of the dc-to-dc die. These bits reflect the silicon revision number of the main die. 0x0 0x0 0x2 0x2 R R0 R R Frequency Monitor Register Address: 0x18, Reset: 0x180000, Name: FREQ_MONITOR An internal frequency monitor uses the internal oscillator (MCLK) to create a pulse at a frequency of 1 kHz (MCLK/10,000). This pulse is used to increment a 16-bit counter. The value of the counter is available to read in the FREQ_MONITOR register. The user can poll this register periodically and use it both as a diagnostic tool for the internal oscillator (to monitor that the oscillator is running) and to measure the frequency. This feature is enabled by default via the FREQ_MON_EN bit in the DIGITAL_DIAG_CONFIG register. Table 48. Bit Descriptions for FREQ_MONITOR Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:0] REGISTER_ADDRESS FREQ_MONITOR Register address. Internal clock counter value. 0x0 0x0 R R Rev. B | Page 65 of 69 AD5758 Data Sheet Generic ID Register Address: 0x1C, Reset: 0x1C0000, Name: DEVICE_ID_3 Table 49. Bit Descriptions for DEVICE_ID_3 Bits 21 Bit Name FAULT_PIN_STATUS Description The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin. Reset 0x0 Access R [20:16] [15:8] [7:3] [2:0] REGISTER_ADDRESS Reserved Reserved Generic ID Register address. Reserved. Reserved. Generic ID. 000: reserved 001: reserved 010: AD5758 011: reserved 100: reserved 101: reserved 110: reserved 111: reserved 0x0 0x0 0x0 0x0 R R R R Rev. B | Page 66 of 69 Data Sheet AD5758 APPLICATIONS INFORMATION EXAMPLE MODULE POWER CALCULATION Using the example module shown in Figure 91, the module power dissipation (excluding the power dissipated in the load) can be calculated using the methodology shown in the Power Calculation Methodology (RLOAD = 1 k) section. Assuming a maximum IOUT value of 20 mA and RLOAD value of 1 k, the total module power is calculated as approximately 226 mW. Note that power associated with the external digital isolation is not included in the calculations because this power is dependent on the choice of component used. Replacing the 1 k load with a short circuit, the power dissipation calculation is shown in the Power Calculation Methodology (RLOAD = 0 ) section, which shows that the total module power becomes approximately 206 mW in a short-circuit load condition. Power Calculation Methodology (RLOAD = 1 k) Current (mA) AIDD1 = 0.05 AIDD2 = 2.9 AISS = 0.23 ILOGIC = 0.01 Assuming an 85% efficiency ADP1031, the total input power becomes 625.5 mW (see Figure 91). Total Module Power = Input Power - Load Power Therefore, 625.5 mW - 400 mW = 225.5 mW Power Calculation Methodology (RLOAD = 0 ) Using the voltage and current values in Table 50, the total quiescent current power is 19.18 mW. Next, Table 50. Quiescent Current Power Calculation Voltage (V) AVDD1 = 24 AVDD2 = 5 AVSS = -15 VLOGIC = 3.3 Assume the dc-to-dc converter is at 90% efficiency. Therefore, VDPC+ power = 512.5 mW. The total input power at the AD5758 side of the ADP1031 PMU is therefore 512.5 mW + 19.18 mW = 531.68 mW. Subtracting the 400 mW load power from this value gives the power associated only with the AD5758, which is 131.68 mW. (VDPC+) x (20 mA + IDPC+) = 4.95 V x 20.5 mA = 101.5 mW Power (mW) 1.2 14.5 3.45 0.033 Assume the dc-to-dc converter at 65% efficiency. Therefore, VDPC+ power = 156.2 mW. The total input power at the AD5758 side of the ADP1031 is therefore 156.2 mW + 19.18 mW = 175.38 mW. Subtracting the 0 mW load power from this value gives the power associated only with the AD5758, which is 175.38 mW. Using the voltage and current values in Table 50, the total quiescent current power is 19.18 mW. Next, perform the following calculation: (VDPC+) x (20 mA + IDPC+) = 22.5 V x 20.5 mA = 461.25 mW Assuming an 85% efficiency ADP1031, the total input power becomes 206.33 mW (see Figure 91). Total Module Power = Input Power - Load Power Therefore, 206.33 mW - 0 mW = 206.33 mW Rev. B | Page 67 of 69 AD5758 Data Sheet 1:1 D1 +24V VINP RFT1 CFLYBK 4.7F Tx1 RFB1 SWP FB1 SGND2 VOUT1 VINP SW2 EN R6 PGNDP VOUT3 GNDP FB3 SLEW SW3 MVDD R3 PGOOD FAULT LDAC RESET ADuCM3029 L1 100H CBUCK 4.7F MGPO3 100k ADP1031 MGPI1 SGPI3 MGND SGPO2 MOSI MISO GND PGND 47H 100nF SGPO1 SVDD2 MVDD SGND2 SVDD1 SGND1 CLK L2 100H MGPI2 MVDD CS RFT3 CINV 4.7F SYNC PWRGD C2 100nF VBAT -12V RFB3 MSS SSS SCK MCK SI MO C3 100nF 100k 100k CLKOUT 100nF C4 100nF MGND AVSS 100nF AVDD2 AVDD1 SW+ VDPC+ VLDO 1k VLOGIC +VSENSE SYNC SCLK VIOUT AD5758 10 OUTPUT SCREW TERMINAL SDI CCOMP SDO SO MI 100nF 2.2F 100k FAULT -VSENSE LDAC RESET DGND AD1 AD0 REFOUT REFIN MGND RA RB 13.7k DGND CHART AGND RLOAD 1k RETURN SCREW AGND TERMINAL AGND HART SIGNAL 11840-092 PGNDP +5.15V VOUT2 R5 CIN 4.7F Figure 91. Example Module Containing the ADP1031 and the AD5758 DRIVING INDUCTIVE LOADS When driving large inductive loads or poorly defined loads, a snubbing network may be required between VIOUT and AGND to minimize ringing. An example of a snubbing network is a series 300 resistor and capacitor (with a value between 2.5 nF and 10 nF) between VIOUT and AGND. In cases where a large inductive load is present, the digital slew rate control of the AD5758 can be used to minimize ringing when stepping the output current by minimizing the dI/dt of the current step. ELECTROMAGNETIC COMPATIBILITY (EMC) CONSIDERATIONS There are three minimum mandatory components for EMC and electromagnetic interference (EMI). * * * A 10 resistor on the trace between the VIOUT pin and the output screw terminal limits the transient current to and from the device. A transient voltage suppression (TVS) diode directly routed between the VIOUT and RETURN screw terminal with short and heavy traces. The TVS diode is crucial to clamp any electrical transient during EMC events. A 10 nF, 50 V, X7R capacitor located in parallel to the TVS diode diverts the small amount of high frequency transient to the RETURN screw terminal. Optional clamp diodes to AVDD1 and AVSS can be added to the VIOUT line to further improve the robustness. Refer to the AN-1599 Application Note for more information. Rev. B | Page 68 of 69 Data Sheet AD5758 OUTLINE DIMENSIONS 0.30 0.25 0.18 25 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 32 24 1 0.50 BSC 3.70 3.60 SQ 3.50 EXPOSED PAD 17 TOP VIEW 1.00 0.95 0.85 END VIEW PKG-004754/005209 SEATING PLANE 0.50 0.40 0.30 8 9 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-5 09-12-2018-A PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 5.10 5.00 SQ 4.90 Figure 92. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.95 mm Package Height (CP-32-30) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD5758BCPZ-RL7 EVAL-AD5758SDZ 1 2 Temperature Range -40C to +115C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. USB interface board, EVAL-SDP-CS1Z, must be ordered separately when ordering the EVAL-AD5758SDZ. (c)2018-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11840-3/20(B) Rev. B | Page 69 of 69 Package Option CP-32-30