TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLY Check for Samples: TPS51218 FEATURES APPLICATIONS * * * * * * * * 1 2 * * * * * * * * * * Wide Input Voltage Range: 3 V to 28 V Output Voltage Range: 0.7 V to 2.6 V Wide Output Load Range: 0 to 20A+ Built-in 0.5% 0.7 V Reference D-CAPTM Mode with 100-ns Load Step Response Adaptive On Time Control Architecture With 4 Selectable Frequency Setting 4700 ppm/C RDS(on) Current Sensing Internal 1-ms Voltage Servo Softstart Pre-Charged Start-up Capability Built in Output Discharge Power Good Output Integrated Boost Switch Built-in OVP/UVP/OCP Thermal Shutdown (Non-latch) SON-10 (DSC) Package Notebook Computers I/O Supplies System Power Supplies DESCRIPTION The TPS51218 is a small-sized single buck controller with adaptive on-time D-CAPTM mode. The device is suitable for low output voltage, high current, PC system power rail and similar point-of-load (POL) power supply in digital consumer products. A small package with minimal pin-count saves space on the PCB, while a dedicated EN pin and pre-set frequency selections minimize design effort required for new designs. The skip-mode at light load condition, strong gate drivers and low-side FET RDS(on) current sensing supports low-loss and high efficiency, over a broad load range. The conversion input voltage which is the high-side FET drain voltage ranges from 3 V to 28 V and the output voltage ranges from 0.7 V to 2.6 V. The device requires an external 5-V supply. The TPS51218 is available in a 10-pin SON package specified from -40C to 85C. TYPICAL APPLICATION CIRCUIT VIN V5IN TPS51218 EN 1 PGOOD VBST 10 2 TRIP DRVH 9 VOUT 3 EN SW 8 4 VFB V5IN 7 5 RF DRVL 6 GND VOUT_GND UDG-09064 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2012, Texas Instruments Incorporated TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PACKAGE -40C to 85C Plastic SON PowerPAD ORDERING DEVICE NUMBER PINS OUTPUT SUPPLY MINIMUM QUANTITY TPS51218DSCR 10 Tape and reel 3000 TPS51218DSCT 10 Mini reel 250 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE Input voltage range (2) Output voltage range (2) VBST -0.3 to 37 VBST (3) -0.3 to 7 SW -5 to 30 V5IN, EN, TRIP, VFB, RF -0.3 to 7 DRVH -5 to 37 DRVH (3) -0.3 to 7 DRVH (3), pulse width < 20 ns -2.5 to 7 DRVL -0.5 to 7 DRVL, pulse width < 20 ns -2.5 to 7 PGOOD -0.3 to 7 UNIT V V TJ Junction temperature range 150 C TSTG Storage temperature range -55 to 150 C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. DISSIPATION RATINGS 2-oz. trace and copper pad with solder. (1) 2 PACKAGE TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 85C POWER RATING 10-pin DSC (1) 1.54 W 15 mW/C 0.62 W Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Supply voltage Input voltage range 4.5 6.5 VBST -0.1 34.5 SW -1 28 SW (1) -4 28 -0.1 6.5 (2) -0.1 6.5 -1 34.5 DRVH (1) -4 34.5 DRVH (2) -0.1 6.5 DRVL -0.3 6.5 PGOOD -0.1 6.5 Operating free-air temperature -40 85 EN, TRIP, VFB, RF DRVH TA (1) (2) MAX V5IN VBST Output voltage range TYP UNIT V V V C This voltage should be applied for less than 30% of the repetitive period. Voltage values are with respect to the SW terminal. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 3 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, V5IN=5V. (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 320 500 A 1 A SUPPLY CURRENT IV5IN V5IN supply current V5IN current, TA = 25C, No Load, VEN = 5 V, VVFB = 0.735 V IV5INSDN V5IN shutdown current V5IN current, TA = 25C, No Load, VEN = 0 V INTERNAL REFERENCE VOLTAGE VFB voltage, CCM condition (1) VVFB VFB regulation voltage IVFB VFB input current 0.7000 V TA = 25C, skip mode 0.7005 0.7040 0.7075 TA = 0C to 85C, skip mode 0.6984 0.7040 0.7096 TA = -40C to 85C, skip mode 0.6970 0.7040 0.7110 0.01 0.2 VVFB = 0.735 V, TA = 25C, skip mode V A OUTPUT DISCHARGE Output discharge current from SW pin IDischg VEN = 0 V, VSW = 0.5 V 5 13 mA OUTPUT DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance tD Dead time Source, IDRVH = -50 mA 1.5 3 Sink, IDRVH = 50 mA 0.7 1.8 Source, IDRVL = -50 mA 1.0 2.2 Sink, IDRVL = 50 mA 0.5 1.2 DRVH-off to DRVL-on 7 17 30 DRVL-off to DRVH-on 10 22 35 ns BOOT STRAP SWITCH VFBST Forward voltage VV5IN-VBST, IF = 10 mA, TA = 25C IVBSTLK VBST leakage current VVBST = 34.5 V, VSW = 28 V, TA = 25C 0.1 0.2 V 0.01 1.5 A 260 400 DUTY AND FREQUENCY CONTROL tOFF(min) tON(min) Minimum off-time TA = 25C Minimum on-time VIN = 28 V, VOUT = 0.7 V, RRF = 39k, TA = 25C (1) 150 Internal SS time From VEN = high to VOUT = 95% ns 79 SOFTSTART tss 1 ms POWERGOOD VTHPG PG threshold PG in from lower 92.5% 95% 97.5% PG in from higher 107.5% 110% 112.5% 2.5% 5% 7.5% PG hysteresis IPGMAX PG sink current VPGOOD = 0.5 V 3 6 tPGDEL PG delay Delay for PG in 0.8 1 mA 1.2 ms LOGIC THRESHOLD AND SETTING CONDITIONS VEN EN voltage threshold IEN EN input current fSW VRF (1) (2) 4 Switching frequency CCM setting voltage Enable 1.8 Disable 0.5 VEN = 5V 1.0 RRF = 470 k, TA = 25C (2) 266 290 314 RRF = 200 k, TA = 25C (2) 312 340 368 (2) 349 380 411 RRF = 39 k, TA = 25C (2) 395 430 465 CCM 1.8 RRF = 100 k, TA = 25C Auto-skip 0.5 V A kHz V Ensured by design. Not production tested. Not production tested. Test condition is VIN= 8 V, VOUT= 1.1 V, IOUT = 10 A using application circuit shown in Figure 21. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, V5IN=5V. (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 9 10 11 UNIT PROTECTION: CURRENT SENSE ITRIP TRIP source current VTRIP = 1V, TA = 25C TCITRIP TRIP current temperature coeffficient On the basis of 25C VTRIP Current limit threshold setting range VTRIP-GND Voltage 0.2 VTRIP = 3.0 V 355 375 395 VTRIP = 1.6 V 185 200 215 VTRIP = 0.2 V 17 25 33 VTRIP = 3.0 V -395 -375 -355 VTRIP = 1.6 V -215 -200 -185 VTRIP = 0.2 V -33 -25 -17 3 15 VOCL VOCLN VAZCADJ Current limit threshold Negative current limit threshold Adaptive zero cross adjustable range 4700 Positive Negative A ppm/C 3 -15 -3 120% 125% V mV mV mV PROTECTION: UVP AND OVP VOVP OVP trip threshold OVP detect tOVPDEL OVP propagation delay time 50-mV overdrive VUVP Output UVP trip threshold UVP detect tUVPDEL Output UVP propagation delay time tUVPEN Output UVP enable delay time 115% s 1 65% 70% 75% 0.8 1 1.2 ms 1.0 1.2 1.4 ms Wake up 4.20 4.38 4.50 Shutdown 3.7 3.93 4.1 From Enable to UVP workable UVLO VUVV5IN V5IN UVLO threshold V THERMAL SHUTDOWN TSDN (3) Thermal shutdown threshold Shutdown temperature Hysteresis (3) (3) 145 10 C Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 5 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com DEVICE INFORMATION DSC PACKAGE (TOP VIEW) PGOOD 1 10 VBST TRIP 2 9 DRVH EN 3 8 SW VFB 4 7 V5IN RF 5 6 DRVL TPS51218DSC GND Thermal pad is used as an active terminal of GND. PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. DRVH 9 O High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is defined by the voltage across VBST to SW node bootstrap flying capacitor DRVL 6 O Synchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined by V5IN voltage. EN GND PGOOD 3 I SMPS enable pin. Short to GND to disable the device. Thermal Pad I Ground 1 O Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signal voltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes within specified limits. Power bad, or the terminal goes low, after a 2- s delay. Switching frequency selection. Connect a resistance to select switching frequency as shown in Table 1. RF 5 I The switching frequency is detected and stored into internal registers during startup. This pin also controls Auto-skip or forced CCM selection. Pull down to GND with resistor : Auto-Skip Connect to PGOOD with resistor: forced CCM after PGOOD becomes high. SW 8 I Switch node. A high-side MOSFET gate drive return. Also used for on time generation and output discharge. OCL detection threshold setting pin. 10 A at room temperature, 4700 ppm/C current is sourced and set the OCL trip voltage as follows. TRIP 2 I VOCL = VTRIP 8 (0.2 V VTRIP 3 V) V5IN 7 I 5 V +30%/-10% power supply input. VBST 10 I Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin to the SW pin. Internally connected to V5IN via bootstrap MOSFET switch. VFB 4 I SMPS feedback input. Connect the feedback resistor divider. 6 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM 0.7 V -30% + UV + OV 0.7 V +10/15% PGOOD + Delay + 0.7 V +20% 0.7 V -5/10% Enable/SS Control VBST Control Logic EN PWM + VFB + + SW + Ramp Comp XCON 0.7 V 10 mA + tON OneShot OCP x(-1/8) TRIP DRVH FCCM x(1/8) + V5IN ZC Auto-skip DRVL Auto-skip/FCCM RF GND Frequency Setting Detector TPS51218 UDG-09065 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 7 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS V5IN SUPPLY CURRENT vs JUNCTION TEMPERATURE V5IN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 800 20 VV5IN = 5 V VEN = 5 V VVFB = 0.735 V No Load IV5INSDN - V5IN Shutdown Current - mA IV5IN - V5IN Supply Current - mA 1000 600 400 200 0 -50 0 50 100 18 16 VV5IN = 5 V VEN = 0 V No Load 14 12 10 8 6 4 2 0 -50 150 0 Figure 1. Figure 2. OVP/UVP THRESHOLD vs JUNCTION TEMPERATURE CURRENT SENSE CURRENT (ITRIP) vs JUNCTION TEMPERATURE 150 150 20 VV5IN = 5 V 18 OVP ITRIP - Current Sense Current - mA VOVP /VUVP - OVP/UVP Trip Threshold - % 100 TJ - Junction Temperature - C TJ - Junction Temperature - C 100 UVP 50 VV5IN = 5 V VTRIP = 1 V 16 14 12 10 8 6 4 2 0 -50 0 50 100 150 0 -50 TJ - Junction Temperature - C Figure 3. 8 50 0 50 100 150 TJ - Junction Temperature - C Figure 4. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 1000 IO = 10 A Auto-Skip 450 fSW - Switching Frequency - kHz fSW - Switching Frequency - kHz 500 RRF = 39 kW 400 RRF = 100 kW 350 RRF = 200 kW RRF = 470 kW 300 250 FCCM 100 10 Auto-Skip 1 VIN = 12 V RRF = 470 kW 200 6 8 10 12 16 14 20 18 0.1 0.001 22 0.01 VIN - Input Voltage - V 1 Figure 5. Figure 6. SWITCHING FREQUENCY vs OUTPUT CURRENT SWITCHING FREQUENCY vs OUTPUT CURRENT 100 1000 fSW - Switching Frequency - kHz FCCM 100 10 Auto-Skip 1 FCCM 100 10 Auto-Skip 1 VIN = 12 V RRF = 200 kW 0.1 0.001 10 IOUT - Output Current - A 1000 fSW - Switching Frequency - kHz 0.1 0.01 0.1 1 10 VIN = 12 V RRF = 100 kW 100 0.1 0.001 IOUT - Output Current - A 0.01 0.1 1 10 100 IOUT - Output Current - A Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 9 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.12 MODE Auto-Skip FCCM FCCM 100 1.11 VOUT - Output Voltage - V fSW - Switching Frequency - kHz 1000 10 1.10 Auto-Skip 1 1.09 VIN = 12 V RRF = 39 kW 0.1 0.001 0.01 0.1 1 10 VIN = 12 V RRF = 470 kW 1.08 0.001 100 0.01 0.1 1 10 100 IOUT - Output Current - A IOUT - Output Current - A Figure 9. Figure 10. OUTPUT VOLTAGE vs INPUT VOLTAGE 1.1-V EFFICIENCY vs OUTPUT CURRENT 100 1.12 Auto-Skip RRF = 470 kW 90 IOUT = 20 A RRF = 470 kW VOUT = 1.1 V 80 VOUT - Output Voltage - V 1.11 h - Efficiency - % 70 1.10 IOUT = 0 A Auto-Skip 60 50 40 30 1.09 VIN (V) 20 10 1.08 6 8 10 12 14 16 18 20 22 0 0.001 0.01 0.1 1 10 100 IOUT - Output Current - A VIN - Input Voltage - V Figure 11. 10 8 12 20 FCCM Figure 12. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 13. 1.1-V Start-Up Waveform X X X Figure 14. Pre-Biased Start-Up Waveform X X X Figure 15. 1.1-V Soft-Stop Waveform X X X Figure 16. 1.1-V Load Transient Response X X X Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 11 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION GENERAL DESCRIPTION The TPS51218 is a high-efficiency, single channel, synchronous buck regulator controller suitable for low output voltage point-of-load applications in notebook computers and similar digital consumer applications. The device features proprietary D-CAPTM mode control combined with adaptive on-time architecture. This combination is ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.7 V to 2.6 V. The conversion input voltage range is from 3 V to 28 V. The D-CAPTM mode uses the ESR of the output capacitor(s) to sense current information. An advantage of this control scheme is that it does not require an external phase compensation network, helping the designer with ease-of-use and realizing low external component count configuration. The switching frequency is selectable from four preset values using a resistor connected from the RF pin to ground. Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltages, while it increases the switching frequency at step-up of load. The RF pin also serves in selecting between auto-skip mode and forced continuous conduction mode for light load conditions. The strong gate drivers of the TPS51218 allow low RDS(on) FETs for high current applications. ENABLE AND SOFT START When the EN pin voltage rises above the enable threshold, (typically 1.2 V) the controller enters its start-up sequence. The first 250 s calibrates the switching frequency setting resistance attached at RF to GND and stores the switching frequency code in internal registers. A voltage of 0.1 V is applied to RF for measurement. Switching is inhibited during this phase. In the second phase, internal DAC starts ramping up the reference voltage from 0 V to 0.7 V. This ramping time is 750 s. Smooth and constant ramp up of the output voltage is maintained during start up regardless of load current. Connect a 1-k resistor in series with the EN pin to provide protection. ADAPTIVE ON-TIME D-CAPTM CONTROL TPS51218 does not have a dedicated oscillator that determines switching frequency. However, the device runs with pseudo-constant frequency by feed-forwarding the input and output voltages into its on-time one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and proportional to the output voltage (tON VOUT / VIN ). This makes the switching frequency fairly constant in steady state conditions over wide input voltage range. The switching frequency is selectable from four preset values by a resistor connected to RF as shown in Table 1. (Leaving the resistance open sets the switching frequency to the lowest value, 290 kHz. However, it is recommended to apply one of the resistances on the table in any application designs.) Table 1. Resistor and Switching Frequency RESISTANCE (RRF) (k) SWITCHING FREQUENCY (fSW) (kHz) 470 290 200 340 100 380 39 430 The off-time is modulated by a PWM comparator. The VFB node voltage (the mid point of resistor divider) is compared to the internal 0.7-V reference voltage added with a ramp signal. When both signals match, the PWM comparator asserts the set signal to terminate the off-time (turn off the low-side MOSFET and turn on high-side MOSFET). The set signal becomes valid if the inductor current level is below OCP threshold, otherwise the off-time is extended until the current level to become below the threshold. 12 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com SMALL SIGNAL MODEL From small-signal loop analysis, a buck converter using D-CAPTM mode can be simplified as shown in Figure 17. Switching Modulator VIN DRVH R1 VFB Control Logic and Driver PWM + R2 + L IIND DRVL VOUT IOUT IC 0.7 V ESR RL Voltage Divider VC CO Output Capacitor UDG-09063 Figure 17. Simplified Modulator Model The output voltage is compared with internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially constant. H(s) = 1 s ESR CO (1) For loop stability, the 0-dB frequency, 0, defined in Equation 2 need to be lower than 1/4 of the switching frequency. f0 = f 1 SW 2p ESR CO 4 (2) According to Equation 2, the loop stability of D-CAPTM mode modulator is mainly determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have CO on the order of several 100 F and ESR in range of 10 m. These makes f0 on the order of 100 kHz or less and the loop is stable. However, ceramic capacitors have an 0 of more than 700 kHz, which is not suitable for this modulator. RAMP SIGNAL The TPS51218 adds a ramp signal to the 0.7-V reference in order to improve its jitter performance. As described in the previous section, the feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start with -7 mV at the beginning of ON-cycle and becomes 0 mV at the end of OFF-cycle in continuous conduction steady state. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 13 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com LIGHT LOAD CONDITION IN AUTO-SKIP OPERATION With RF pin pulled down to low via RRF, the TPS51218 automatically reduces switching frequency at light load conditions to maintain high efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in to discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the light load operation IO(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated in Equation 3. IO(LL ) = (V - VOUT ) VOUT 1 IN 2 L fSW VIN where * fSW is the PWM switching frequency (3) Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it decreases almost proportional to the output current from the IO(LL) given in Equation 3. For example, it is 58 kHz at IO(LL)/5 if the frequency setting is 290 kHz. ADAPTIVE ZERO CROSSING The TPS51218 has an adaptive zero crossing circuit which performs optimization of the zero inductor current detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early detection. As a result, better light load efficiency is delivered. FORCED CONTINUOUS CONDUCTION MODE When the RF pin is tied high, the controller keeps continuous conduction mode (CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load range which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency. To set the switching frequency to be the same as Auto-skip mode, it is recommended to connect RRF to PGOOD. In this way, RF is tied low prior to soft-start operation to set frequency and tied high after powergood indicates high. OUTPUT DISCHARGE CONTROL When EN is low, the TPS51218 discharges the output capacitor using internal MOSFET connected between SW and GND while high-side and low-side MOSFETs are kept off. The current capability of this MOSFET is limited to discharge slowly. LOW-SIDE DRIVER The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistance, which are 1.0 for V5IN to DRVL and 0.5 for DRVL to GND. A dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal to the gate charge at Vgs=5V times switching frequency. This gate drive current as well as the high-side gate drive current times 5V makes the driving power which need to be dissipated from TPS51218 package. HIGH-SIDE DRIVER The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5 V of bias voltage is delivered from V5IN supply. The average drive current is also equal to the gate charge at VGS=5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBST and SW pins. The drive capability is represented by its internal resistance, which are 1.5 for VBST to DRVH and 0.7 for DRVH to SW. 14 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com POWER-GOOD The TPS51218 has powergood output that indicates high when switcher output is within the target. The powergood function is activated after soft-start has finished. If the output voltage becomes within +10%/-5% of the target value, internal comparators detect power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of +15%/-10% of the target value, the powergood signal becomes low after a 2-s internal delay. The powergood output is an open-drain output and must be pulled up externally. CURRENT SENSE AND OVER CURRENT PROTECTION TPS51218 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. To provide both good accuracy and cost effective solution, the TPS51218 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10A typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 4. Note that VTRIP is limited up to approximately 3 V internally. VTRIP (mV) = RTRIP (kW) ITRIP (mA) (4) The inductor current is monitored by the voltage between GND pad and SW pin so that the SW pin should be connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700ppm/C temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive current sensing node so that GND should be connected to the proper current sensing device, i.e. the source terminal of the low-side MOSFET. As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load current at overcurrent threshold, IOCP, can be calculated in Equation 5 ae V TRIP IOCP = c c 8 RDS(on) e o IIND(ripple ) (V - VOUT ) VOUT VTRIP 1 /+ = + IN / 2 8 RDS(on) 2 L fSW VIN o (5) In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down the controller. When the device is operating in the forced continuous conduction mode, the negative current limit (NCL) protects the external FET from carrying too much current. The NCL detect threshold is set as the same absolute value as positive OCL but negative polarity. Please be noted the threshold still represents the valley value of the inductor current. OVER/UNDER VOLTAGE PROTECTION TPS51218 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After a 1-ms delay, TPS51218 latches OFF both high-side and low-side MOSFETs drivers. This function is enabled after 1.2 ms following EN has become high. UVLO PROTECTION TPS51218 has V5IN undervoltage lockout protection (UVLO). When the V5IN voltage is lower than UVLO threshold voltage, the switch mode power supply shuts off. This is non-latch protection. THERMAL SHUTDOWN TPS51218 monitors the die temperature. If the temperature exceeds the threshold value (typically 145C), the TPS51218 is shut off. This is non-latch protection. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 15 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com EXTERNAL COMPONENTS SELECTION Selecting external components is simple in D-CAPTM mode. 1. Choose the inductor. The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable operation. L= 1 IIND(ripple) fSW (V IN(max ) - VOUT ) V OUT VIN(max ) 3 = IOUT(max ) fSW (V IN(max ) - VOUT ) V OUT VIN(max ) (6) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 7. IIND(peak ) = VIN(max ) - VOUT VOUT VTRIP 1 + 8 RDS(on) L fSW VIN(max ) ) ( (7) 2. Choose the output capacitor(s). Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For loop stability, capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to determine ESR. ESR = VOUT 10 eemV uu (1 - D ) 0.7 ee V uu IIND(ripple) = 10 eemV uu L fSW 0.7 ee V uu = L fSW eW u 70 e u where D is the duty ratio the output ripple down slope rate is 10 mV/tSW in terms of VFB terminal voltage as shown in Figure 18 tSW is the switching period VVFB - Feedback Voltage - mV * * * (8) tSW x (1-D) 10 VRIPPLE(FB) 0 tSW t - Time Figure 18. Ripple Voltage Down Slope 16 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com 3. Determine the value of R1 and R2. The output voltage is programmed by the voltage-divider resistor, R1 and R2, shown in Figure 17. R1 is connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. Typical designs begin with the selection of an R2 value between 10 k and 20 k. Determine R1 using Equation 9. IIND(ripple) ESR o ae cc VOUT // - 0.7 2 e o R2 R1 = 0.7 (9) LAYOUT CONSIDERATIONS VIN TRIP TPS51218 2 V5IN RF VOUT 6 5 #1 1 mF #2 VFB DRVL 4 5 Thermal Pad GND #3 UDG-09066 Figure 19. Ground System of DC/DC Converter Using the TPS51218 Certain points must be considered before starting a layout work using the TPS51218. * Inductor, VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components should be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines. * All sensitive analog traces and components such as VFB, PGOOD, TRIP and RF should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components. * The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to suppress generating switching noise. - The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the VIN capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 of Figure 19) - The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of Figure 19) - The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 17 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 * * * * * www.ti.com from gate of the low-side MOSFET through the gate driver and GND pad of the device, and back to source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and GND pad of the device at ground as close as possible. (Refer to loop #3 of Figure 19) Since the TPS51218 controls output voltage referring to voltage across VOUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner both bottom side resistor and GND pad of the device should be connected to the negative node of VOUT capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component side and avoid via(s) between these resistors and the device. Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling to a high-voltage switching node. Connect the frequency setting resistor from RF pin to ground, or to the PGOOD pin, and make the connections as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to ground should avoid coupling to a high-voltage switching node. Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace. The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible. LAYOUT CONSIDERATIONS TO REMOTE SENSING VIN TRIP TPS51218 2 V5IN RF 6 5 VOUT 1 mF DRVL VFB 4 0.1 mF 5 100 W VTT_SENSE VSS_SENSE Thermal Pad GND UDG-09067 Figure 20. Remote Sensing of Output Voltage Using the TPS51218 * * * 18 Make a Kelvin connection to the load device. Run the feedback signals as a differential pair to the device. The distance of these parallel pair should be as short as possible. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane. Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com TPS51218 APPLICATION CIRCUITS V5IN 4.5 V to 6.5 V R1 5.6 kW U1 TPS51218 R6 100 kW C3 10 mF x 4 C1 0.1 mF 1 PGOOD VBST 10 2 TRIP DRVH 9 3 EN SW 8 4 VFB V5IN 7 5 RF DRVL 6 Q1 FDMS8680 R7 R3 1 kW 3.3 W EN R2 10 kW L1 0.45 mH R5 30 kW GND Q2 FDMS8670AS Q3 FDMS8670AS VOUT 1.1 V 18 A C4 330 mF x 4 C2 1 mF R4(A) 470 kW VIN 8V to 20 V VOUT_GND UDG-09068 Figure 21. 1.1-V/18-A Auto-Skip Mode V5IN 4.5 V to 6.5 V VIN 8V to 20 V R1 5.6 kW R3 1 kW EN R2 10 kW R6 100 kW R4(A) 470 kW U1 TPS51218 C3 10 mF x 4 C1 0.1 mF 1 PGOOD VBST 10 2 TRIP DRVH R7 9 Q1 FDMS8680 L1 0.45 mH 3.3 W 3 EN SW 8 4 VFB V5IN 7 5 RF DRVL 6 GND R5 30 kW Q2 FDMS8670AS Q3 FDMS8670AS C2 1 mF VOUT 1.1 V 18 A C4 330 mF x 4 VOUT_GND UDG-09069 A. See Table 1 for resistor/frequency values. Figure 22. 1.1-V/18-A Forced Continuous Conduction Mode Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 19 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com Table 2. 1.1-V, 18-A, 290-kHz Application List of Materials REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER Taiyo Yuden TMK325BJ106MM C3 1 4 x 10 F, 25 V C4 1 4 x 330 F, 2 V, 12 m Panasonic EEFCX0D331XR L1 1 0.45 H, 25 A, 1.1 m Panasonic ETQP4LR45XFC Q1 1 30 V, 35 A, 8.5 m Fairchild FDMS8680 Q2, Q3 2 30 V, 42 A, 3.5 m Fairchild FDMS8670AS 20 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 TPS51218 SLUS935B - MAY 2009 - REVISED FEBRUARY 2012 www.ti.com Changes from Revision A (June 2009) to Revision B Page * Added DRVH, pulse width < 20 ns rating in ABSOLUTE MAXIMUM RATINGS table ........................................................ 2 * Added DRVL, pulse width < 20 ns rating in ABSOLUTE MAXIMUM RATINGS table ......................................................... 2 Submit Documentation Feedback Copyright (c) 2009-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 21 PACKAGE MATERIALS INFORMATION www.ti.com 16-Nov-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51218DSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51218DSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Nov-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51218DSCR WSON DSC 10 3000 367.0 367.0 35.0 TPS51218DSCT WSON DSC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DSC0010J WSON - 0.8 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 C 0.8 0.7 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) EXPOSED THERMAL PAD (0.2) TYP 4X (0.25) 5 2X 2 6 11 SYMM 2.4 0.1 10 1 8X 0.5 PIN 1 ID (OPTIONAL) 10X SYMM 0.5 10X 0.3 0.30 0.18 0.1 0.05 C A B C 4221826/D 08/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DSC0010J WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 (2.4) SYMM (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4221826/D 08/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DSC0010J WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL TYP 11 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4221826/D 08/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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