INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 Zero-Drift, Bi-Directional CURRENT/POWER MONITOR with I2CTM Interface FEATURES DESCRIPTION 1 * * * * 23 * * * SENSES BUS VOLTAGES FROM 0V TO +26V REPORTS CURRENT, VOLTAGE, AND POWER 16 PROGRAMMABLE ADDRESSES HIGH ACCURACY: 1% (Max) OVER TEMPERATURE FILTERING OPTIONS CALIBRATION REGISTERS SOT23-8 AND SO-8 PACKAGES The INA219 is a high-side current shunt and power monitor with an I2C interface. The INA219 monitors both shunt drop and supply voltage, with programmable conversion times and filtering. A programmable calibration value, combined with an internal multiplier, enables direct readouts in amperes. An additional multiplying register calculates power in watts. The I2C interface features 16 programmable addresses. The INA219 senses across shunts on buses that can vary from 0V to 26V. The device uses a single +3V to +5.5V supply, drawing a maximum of 1mA of supply current. The INA219 operates from -40C to +125C. APPLICATIONS * * * * * * * * SERVERS TELECOM EQUIPMENT NOTEBOOK COMPUTERS POWER MANAGEMENT BATTERY CHARGERS WELDING EQUIPMENT POWER SUPPLIES TEST EQUIPMENT RELATED PRODUCTS DESCRIPTION DEVICE Current/Power Monitor with Watchdog, Peak-Hold, and Fast Comparator Functions INA209 Zero-Drift, Low-Cost, Analog Current Shunt Monitor Series in Small Package INA210-INA214 VS (Supply Voltage) VIN+ VIN- INA219 Power Register Data 2 Current Register PGA IC Interface CLK A0 ADC Voltage Register A1 GND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2009, Texas Instruments Incorporated INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING SO-8 D I219A SOT23-8 DCN A219 INA219 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). Supply Voltage, VS Analog Inputs, VIN+, VIN- Differential (VIN+) - (VIN-) (2) UNIT 6 V -26 to +26 V -0.3 to +26 V SDA GND - 0.3 to +6 V SCL GND - 0.3 to VS + 0.3 V Input Current Into Any Pin 5 mA Open-Drain Digital Output Current 10 mA Operating Temperature -40 to +125 C Storage Temperature -65 to +150 C Junction Temperature ESD Ratings (1) (2) 2 Common-Mode INA219 +150 C Human Body Model 4000 V Charged-Device Model 750 V Machine Model (MM) 200 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. VIN+ and VIN- may have a differential voltage of -26V to +26V; however, the voltage at these pins must not exceed the range -0.3V to +26V. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS: VS = +3.3V Boldface limits apply over the specified temperature range, TA = -25C to +85C. At TA = +25C, VIN+ = 12V, VSENSE = (VIN+ - VIN-) = 32mV, PGA = / 1, and BRNG (1) = 1, unless otherwise noted. INA219 PARAMETER TEST CONDITIONS MIN PGA = / 1 0 PGA = / 2 PGA = / 4 TYP MAX UNIT 40 mV 0 80 mV 0 160 mV PGA = / 8 0 320 mV BRNG = 1 0 32 V BRNG = 0 0 16 VIN+ = 0V to 26V 100 INPUT Full-Scale Current Sense (Input) Voltage Range Bus Voltage (Input Voltage) Range (2) Common-Mode Rejection CMRR Offset Voltage, RTI (3) VOS PSRR 10 100 V PGA = / 2 20 125 V PGA = / 4 30 150 V PGA = / 8 40 200 VS = 3V to 5.5V Current Sense Gain Error vs Temperature Input Impedance V dB PGA = / 1 vs Temperature vs Power Supply 120 V 0.1 V/C 10 V/V 40 m% 10 ppm/C Active Mode VIN+ Pin 20 A VIN- Pin 20 || 320 A || k Input Leakage (4) Power-Down Mode VIN+ Pin 0.1 0.5 A VIN- Pin 0.1 0.5 A DC ACCURACY ADC Basic Resolution 12 Bits 1 LSB Step Size Shunt Voltage 10 V Bus Voltage 4 mV Current Measurement Error 0.2 over Temperature Bus Voltage Measurement Error 0.2 over Temperature 0.5 % 1 % 0.5 % 1 Differential Nonlinearity 0.1 % LSB ADC TIMING ADC Conversion Time 12-Bit 532 586 s 11-Bit 276 304 s 10-Bit 148 163 s 9-Bit 84 93 s Minimum Convert Input Low Time (1) (2) (3) (4) s 4 BRNG is bit 13 of the Configuration Register. This parameter only expresses the full-scale range of the ADC scaling. In no event should more than 26V be applied to this device. Referred-to-input (RTI). Input leakage is positive (current flowing into the pin) for the conditions shown at the top of the table. Negative leakage currents can occur under different input conditions. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 3 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = +3.3V (continued) Boldface limits apply over the specified temperature range, TA = -25C to +85C. At TA = +25C, VIN+ = 12V, VSENSE = (VIN+ - VIN-) = 32mV, PGA = / 1, and BRNG = 1, unless otherwise noted. INA219 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 28 35 ms 1 A V SMBus SMBus Timeout (5) DIGITAL INPUTS (SDA as Input, SCL, A0, A1) Input Capacitance 3 0 VIN VS Leakage Input Current 0.1 pF Input Logic Levels: VIH 0.7 (VS) 6 VIL -0.3 0.3 (VS) Hysteresis 500 V mV OPEN-DRAIN DIGITAL OUTPUTS (SDA) Logic '0' Output Level High-Level Output Leakage Current ISINK = 3mA 0.15 0.4 V VOUT = VS 0.1 1 A POWER SUPPLY Operating Supply Range +3 +5.5 V 0.7 1 mA Quiescent Current, Power-Down Mode 6 15 A Power-On Reset Threshold 2 Quiescent Current V TEMPERATURE RANGE Specified Temperature Range -25 +85 C Operating Temperature Range -40 +125 C Thermal Resistance (6) (5) (6) 4 JA SOT23-8 142 C/W SO-8 120 C/W SMBus timeout in the INA219 resets the interface any time SCL or SDA is low for over 28ms. JA value is based on JEDEC low-K board. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 PIN CONFIGURATIONS DCN PACKAGE SOT23-8 (Top View) D PACKAGE SO-8 (Top View) VIN+ 1 8 A1 VIN- 2 7 A0 GND 3 6 SDA VS 4 5 SCL A1 1 8 VIN+ A0 2 7 VIN- SDA 3 6 GND SCL 4 5 VS PIN DESCRIPTIONS: SOT23-8 SOT23-8 (DCN) PIN NO NAME 1 VIN+ Positive differential shunt voltage. Connect to positive side of shunt resistor. DESCRIPTION 2 VIN- Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is measured from this pin to ground. 3 GND Ground. 4 VS Power supply, 3V to 5.5V. 5 SCL Serial bus clock line. 6 SDA Serial bus data line. 7 A0 Address pin. Table 1 shows pin settings and corresponding addresses. 8 A1 Address pin. Table 1 shows pin settings and corresponding addresses. PIN DESCRIPTIONS: SO-8 SO-8 (D) PIN NO NAME DESCRIPTION 1 A1 Address pin. Table 1 shows pin settings and corresponding addresses. 2 A0 Address pin. Table 1 shows pin settings and corresponding addresses. 3 SDA Serial bus data line. 4 SCL Serial bus clock line. 5 VS 6 GND Power supply, 3V to 5.5V. Ground. 7 VIN- Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is measured from this pin to ground. 8 VIN+ Positive differential shunt voltage. Connect to positive side of shunt resistor. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 5 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, VIN+ = 12V, VSENSE = (VIN+ - VIN-) = 32mV, PGA = / 1, and BRNG = 1, unless otherwise noted. ADC SHUNT OFFSET vs TEMPERATURE 100 -10 80 -20 60 -30 40 Offset (mV) Gain (dB) FREQUENCY RESPONSE 0 -40 -50 -60 20 0 -20 -70 -40 -80 -60 -90 -80 -100 -100 100 10 1k 10k 100k 320mV Range 160mV Range 1M 80mV Range 0 -40 -25 Input Frequency (Hz) 40mV Range 25 Figure 1. 80 45 60 40 40 35 160mV Range 0 -20 -40 125 30 25 20 16V Range 32V Range 15 80mV Range 40mV Range -60 10 -80 5 0 -100 -40 -25 0 25 50 75 100 0 -40 -25 125 25 50 75 100 125 Temperature (C) Temperature (C) Figure 3. Figure 4. ADC BUS GAIN ERROR vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT VOLTAGE 100 20 80 15 60 10 40 16V 20 INL (mV) Gain Error (m%) 100 ADC BUS VOLTAGE OFFSET vs TEMPERATURE 50 Offset (mV) Gain Error (m%) ADC SHUNT GAIN ERROR vs TEMPERATURE 320mV Range 75 Figure 2. 100 20 50 Temperature (C) 0 -20 0 -5 32V -40 5 -10 -60 -15 -80 -100 -40 -25 0 25 50 75 100 125 -20 -0.4 Figure 5. 6 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 Input Voltage (V) Temperature (C) Figure 6. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25C, VIN+ = 12V, VSENSE = (VIN+ - VIN-) = 32mV, PGA = / 1, and BRNG = 1, unless otherwise noted. INPUT CURRENTS WITH LARGE DIFFERENTIAL VOLTAGES (VIN+ at 12V, Sweep of VIN-) 2.0 ACTIVE IQ vs TEMPERATURE 1.2 VS+ = 5V 1.0 1.0 VS = 5V 0.8 0.5 IQ (mA) Input Currents (mA) 1.5 VS+ = 3V 0 VS+ = 3V 0.6 VS = 3V 0.4 -0.5 0.2 -1.0 VS+ = 5V 0 -1.5 0 10 5 15 20 25 30 25 50 Temperature (C) Figure 7. Figure 8. 75 100 125 ACTIVE IQ vs I2C CLOCK FREQUENCY SHUTDOWN IQ vs TEMPERATURE 16 1.0 14 0.9 VS = 5V 0.8 12 0.7 IQ (mA) 10 IQ (mA) 0 -40 -25 VIN- Voltage (V) VS = 5V 8 6 VS = 3V 4 0.6 VS = 3V 0.5 0.4 0.3 0.2 2 0.1 0 0 -40 -25 0 25 50 75 100 125 100k 10k 1k Temperature (C) SCL Frequency (Hz) Figure 9. Figure 10. 1M 10M SHUTDOWN IQ vs I2C CLOCK FREQUENCY 300 250 VS = 5V IQ (mA) 200 150 100 50 VS = 3V 0 1k 10k 100k 1M 10M SCL Frequency (Hz) Figure 11. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 7 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com REGISTER BLOCK DIAGRAM Power (1) Bus Voltage (1) Current Shunt Voltage Channel (1) ADC Bus Voltage Channel Full-Scale Calibration (2) Shunt Voltage (1) PGA (In Configuration Register) NOTES: (1) Read-only (2) Read/write Data Registers Figure 12. INA219 Register Block Diagram 8 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 APPLICATION INFORMATION The INA219 is a digital current-shunt monitor with an I2C and SMBus-compatible interface. It provides digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution, and continuousversus-triggered operation. Detailed register information appears at the end of this data sheet, beginning with Table 2. See the Register Block Diagram for a block diagram of the INA219. INA219 TYPICAL APPLICATION Figure 13 shows a typical application circuit for the INA219. Use a 0.1F ceramic capacitor for power-supply bypassing, placed as closely as possible to the supply and ground pins. The input filter circuit consisting of RF1, RF2, and CF is not necessary in most applications. If the need for filtering is unknown, reserve board space for the components and install 0 resistors unless a filter is needed. See the Filtering and Input Considerations section. The pull-up resistors shown on the SDA and SCL lines are not needed if there are pull-up resistors on these same lines elsewhere in the system. Resistor values shown are typical: consult either the I2C or SMBus specification to determine the acceptable minimum or maximum values. BUS OVERVIEW The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only when a difference between the two systems is being addressed. Two bidirectional lines, SCL and SDA, connect the INA219 to the bus. Both SCL and SDA are open-drain connections. The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates START and STOP conditions. To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH is interpreted as a START or STOP condition. Once all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The INA219 includes a 28ms timeout on its interface to prevent locking up an SMBus. The INA219 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another. Current Shunt Power Bus (0V to 26V) Supply Voltage (INA219 Power Supply Range is 3V to 5.5V) Load RF1 RF2 CBYPASS 0.1mF (typical) CF VIN+ RPULLUP 3.3kW (typical) VIN- INA219 SDA Power Register SCL 2 Current Register PGA IC Interface ADC RPULLUP 3.3kW (typical) Data (SDA) Clock (SCL) A0 A1 Voltage Register GND Figure 13. Typical Application Circuit Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 9 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com Serial Bus Address WRITING TO/READING FROM THE INA219 To communicate with the INA219, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. Accessing a particular register on the INA219 is accomplished by writing the appropriate value to the register pointer. Refer to Table 2 for a complete list of registers and corresponding addresses. The value for the register pointer as shown in Figure 17 is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the INA219 requires a value for the register pointer. The INA219 has two address pins, A0 and A1. Table 1 describes the pin logic levels for each of the 16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any activity on the interface occurs. The address pins are read at the start of each communication event. Table 1. INA219 Address Pins and Slave Addresses A1 A0 SLAVE ADDRESS GND GND 1000000 GND VS+ 1000001 GND SDA 1000010 GND SCL 1000011 VS+ GND 1000100 VS+ VS+ 1000101 VS+ SDA 1000110 VS+ SCL 1000111 SDA GND 1001000 SDA VS+ 1001001 SDA SDA 1001010 SDA SCL 1001011 SCL GND 1001100 SCL VS+ 1001101 SCL SDA 1001110 SCL SCL 1001111 Serial Interface The INA219 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The INA219 supports the transmission protocol for fast (1kHz to 400kHz) and high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted most significant byte first. 10 Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit LOW. The INA219 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register to which data will be written. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA219 acknowledges receipt of each data byte. The master may terminate data transfer by generating a START or STOP condition. When reading from the INA219, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a START condition and sends the slave address byte with the R/W bit HIGH to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA219 retains the register pointer value until it is changed by the next write operation. Figure 14 and Figure 15 show read and write operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte. Figure 16 shows the timing diagram for the SMBus Alert response operation. Figure 17 illustrates a typical register pointer configuration. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 Start By Master 1 1 1 1 0 0 A3 A2 A1 A0 (1) R/W Frame 1 Two-Wire Slave Address Byte 0 A3 A2 A1 A0 (1) 9 ACK By INA219 R/W 1 P7 P6 9 ACK By INA219 1 D15 D14 P4 P3 P2 D13 P1 Frame 2 Register Pointer Byte P5 D12 D11 D10 D9 (2) From INA219 Frame 2 Data MSByte 9 ACK By INA219 P0 1 D15 D14 D13 D8 9 1 D6 9 ACK By INA219 D8 D7 ACK By Master D9 Frame 3 Data MSByte D12 D11 D10 NOTES: (1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. (2) Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 19. (3) ACK by Master can also be sent. 0 Frame 1 Two-Wire Slave Address Byte D5 1 D7 D4 D3 From INA219 D5 D4 D2 D3 D1 (2) D2 Frame 3 Data LSByte D6 9 9 ACK By INA219 D0 NoACK By Master D0 D1 Frame 4 Data LSByte (3) Stop Stop By Master Product Folder Link(s): INA219 11 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated SCL SDA SCL SDA Start By Master NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure 15. Timing Diagram for Read Word Format Figure 14. Timing Diagram for Write Word Format INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 0 0 1 R/W Start By Master 0 0 A3 A2 ACK By INA219 A1 A0 0 From INA219 Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte NACK By Master Stop By Master (1) NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure 16. Timing Diagram for SMBus ALERT 1 9 1 9 SCL 1/4 SDA 1 0 0 A3 A2 A1 A0 R/W Start By Master P7 P6 P5 P4 P3 P2 P1 ACK By INA219 Frame 1 Two-Wire Slave Address Byte (1) P0 Stop ACK By INA219 Frame 2 Register Pointer Byte NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure 17. Typical Register Pointer Set 12 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 High-Speed I2C Mode The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the INA219 to support the F/S mode. When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This transmission is made in fast (400kbps) or standard (100kbps) (F/S) mode at no more than 400kbps. The INA219 does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 3.4Mbps operation. t(LOW) tF tR t(HDSTA) SCL t(HDSTA) t(HIGH) t(SUSTO) t(SUSTA) t(HDDAT) t(SUDAT) SDA t(BUF) P S S P Figure 18. Bus Timing Diagram Bus Timing Diagram Definitions FAST MODE PARAMETER HIGH-SPEED MODE MIN MAX MIN MAX UNITS SCL Operating Frequency f(SCL) 0.001 0.4 0.001 3.4 MHz Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns Hold time after repeated START condition. After this period, the first clock is generated. t(HDSTA) 100 100 ns Repeated START Condition Setup Time t(SUSTA) 100 100 ns STOP Condition Setup Time t(SUSTO) 100 100 ns Data Hold Time t(HDDAT) 0 0 ns Data Setup Time t(SUDAT) 100 10 ns SCL Clock LOW Period t(LOW) 1300 160 ns SCL Clock HIGH Period t(HIGH) 600 Clock/Data Fall Time tF 300 160 ns Clock/Data Rise Time tR 300 160 ns Clock/Data Rise Time for SCLK 100kHz tR 1000 60 ns ns Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 13 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com Power-Up Conditions (Configuration Register, BADC bits). The Mode control in the Configuration Register also permits selecting modes to convert only voltage or current, either continuously or in response to an event (triggered). Power-up conditions apply to a software reset via the RST bit (bit 15) in the Configuration Register, or the I2C bus General Call Reset. BASIC ADC FUNCTIONS All current and power calculations are performed in the background and do not contribute to conversion time; conversion times shown in the Electrical Characteristics table can be used to determine the actual conversion time. The two analog inputs to the INA219, VIN+ and VIN-, connect to a shunt resistor in the bus of interest. The INA219 is typically powered by a separate supply from +3V to +5.5V. The bus being sensed can vary from 0V to 26V. There are no special considerations for power-supply sequencing (for example, a bus voltage can be present with the supply voltage off, and vice-versa). The INA219 senses the small drop across the shunt for shunt voltage, and senses the voltage with respect to ground from VIN- for the bus voltage. Figure 19 illustrates this operation. Power-Down mode reduces the quiescent current and turns off current into the INA219 inputs, avoiding any supply drain. Full recovery from Power-Down requires 40s. ADC Off mode (set by the Configuration Register, MODE bits) stops all conversions. Writing any of the triggered convert modes into the Configuration Register (even if the desired mode is already programmed into the register) triggers a single-shot conversion. Table 5 lists the triggered convert mode settings. When the INA219 is in the normal operating mode (that is, MODE bits of the Configuration Register are set to '111'), it continuously converts the shunt voltage up to the number set in the shunt voltage averaging function (Configuration Register, SADC bits). The device then converts the bus voltage up to the number set in the bus voltage averaging VSHUNT = VIN+ - VINTypically < 50mV + - Current Shunt Supply Load INA219 Power-Supply Voltage 3V to 5.5V 3.3V Supply VIN+ VS VIN- INA219 Power Register Data (SDA) Clock (SCL) 2 VBUS = VIN- - GND Current Register Range of 0V to 26V Typical Application 12V PGA IC Interface A0 ADC Voltage Register A1 GND Figure 19. INA219 Configured for Shunt and Bus Voltage Measurement 14 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 Although the INA219 can be read at any time, and the data from the last conversion remain available, the Conversion Ready bit (Status Register, CNVR bit) is provided to help co-ordinate one-shot or triggered conversions. The Conversion Ready bit is set after all conversions, averaging, and multiplication operations are complete. The Conversion Ready bit clears under these conditions: 1. Writing to the Configuration Register, except when configuring the MODE bits for Power Down or ADC off (Disable) modes; 2. Reading the Status Register; or 3. Triggering a single-shot conversion with the Convert pin. Power Measurement Current and bus voltage are converted at different points in time, depending on the resolution and averaging mode settings. For instance, when configured for 12-bit and 128 sample averaging, up to 68ms in time between sampling these two values is possible. Again, these calculations are performed in the background and do not add to the overall conversion time. PGA Function If larger full-scale shunt voltages are desired, the INA219 provides a PGA function that increases the full-scale range up to 2, 4, or 8 times (320mV). Additionally, the bus voltage measurement has two full-scale ranges: 16V or 32V. Compatibility with TI Hot Swap Controllers The INA219 is designed for compatibility with hot swap controllers such the TI TPS2490. The TPS2490 uses a high-side shunt with a limit at 50mV; the INA219 full-scale range of 40mV enables the use of the same shunt for current sensing below this limit. When sensing is required at (or through) the 50mV sense point of the TPS2490, the PGA of the INA219 can be set to /2 to provide an 80mV full-scale range. Filtering and Input Considerations Measuring current is often noisy, and such noise can be difficult to define. The INA219 offers several options for filtering by choosing resolution and averaging in the Configuration Register. These filtering options can be set independently for either voltage or current measurement. The internal ADC is based on a delta-sigma () front-end with a 500kHz (30%) typical sampling rate. This architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling rate harmonics can cause problems. Because these signals are at 1MHz and higher, they can be dealt with by incorporating filtering at the input of the INA219. The high frequency enables the use of low-value series resistors on the filter for negligible effects on measurement accuracy. In general, filtering the INA219 input is only necessary if there are transients at exact harmonics of the 500kHz (30%) sampling rate (>1MHz). Filter using the lowest possible series resistance and ceramic capacitor. Recommended values are 0.1F to 1.0F. Figure 20 shows the INA219 with an additonal filter added at the input. Current Shunt Load Supply RFILTER 10W RFILTER 10W Supply Voltage 3.3V Supply 0.1mF to 1mF Ceramic Capacitor VIN+ VIN- VS INA219 Power Register Data (SDA) Clock (SCL) 2 Current Register PGA IC Interface A0 ADC Voltage Register A1 GND Figure 20. INA219 with Input Filtering Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 15 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com Overload conditions are another consideration for the INA219 inputs. The INA219 inputs are specified to tolerate 26V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long the power supply or energy storage capacitors support it). It must be remembered that removing a short to ground can result in inductive kickbacks that could exceed the 26V differential and common-mode rating of the INA219. Inductive kickback voltages are best dealt with by zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficient energy storage capacitance. In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem occurs because an excessive dV/dt can activate the ESD protection in the INA219 in systems where large currents are available. Testing has demonstrated that the addition of 10 resistors in series with each input of the INA219 sufficiently protects the inputs against dV/dt failure up to the 26V rating of the INA219. These resistors have no significant effect on accuracy. 16 Simple Current Shunt Monitor Usage (No Programming Necessary) The INA219 can be used without any programming if it is only necessary to read a shunt voltage drop and bus voltage with the default 12-bit resolution, 320mV shunt full-scale range (PGA=/8), 32V bus full-scale range, and continuous conversion of shunt and bus voltage. Without programming, current is measured by reading the shunt voltage. The Current Register and Power Register are only available if the Calibration Register contains a programmed value. Programming the INA219 The default power-up states of the registers are shown in the INA219 register descriptions section of this data sheet. These registers are volatile, and if programmed to other than default values, must be re-programmed at every device power-up. Detailed information on programming the Calibration Register specifically is given in the section, Programming the INA219 Power Measurement Engine. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 PROGRAMMING THE INA219 POWER MEASUREMENT ENGINE Calibration Register and Scaling The Calibration Register makes it possible to set the scaling of the Current and Power Registers to whatever values are most useful for a given application. One strategy may be to set the Calibration Register such that the largest possible number is generated in the Current Register or Power Register at the expected full-scale point; this approach yields the highest resolution. The Calibration Register can also be selected to provide values in the Current and Power Registers that either provide direct decimal equivalents of the values being measured, or yield a round LSB number. After these choices have been made, the Calibration Register also offers possibilities for end user system-level calibration, where the value is adjusted slightly to cancel total system error. Below are two examples for configuring the INA219 calibration. Both examples are written so the information directly relates to the calibration setup found in the INA219EVM software. Calibration Example 1: Calibrating the INA219 with no possibility for overflow. (Note that the numbers used in this example are the same used with the INA219EVM software as shown in Figure 21.) 1. Establish the following parameters: VBUS_MAX = 32 VSHUNT_MAX = 0.32 RSHUNT = 0.5 2. Using Equation 1, determine the maximum possible current . VSHUNT_MAX MaxPossible_I = RSHUNT MaxPossible_I = 0.64 (1) 3. Choose the desired maximum current value. This value is selected based on system expectations. Max_Expected_I = 0.6 4. Calculate the possible range of current LSBs. To calculate this range, first compute a range of LSBs that is appropriate for the design. Next, select an LSB within this range. Note that the results will have the most resolution when the minimum LSB is selected. Typically, an LSB is selected to be the nearest round number to the minimum LSB value. Max_Expected_I Minimum_LSB = 32767 Minimum_LSB = 18.311 10-6 (2) Max_Expected_I 4096 Maximum_LSB = 146.520 10-6 Maximum_LSB = (3) Choose an LSB in the range: Minimum_LSB 320.00 2. Translate this number to a whole decimal number ==> 32000 3. Convert it to binary==> 111 1101 0000 0000 4. Complement the binary result : 000 0010 1111 1111 5. Add 1 to the Complement to create the Two's Complement formatted result ==> 000 0011 0000 0000 6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h (Remember to extend the sign to all sign-bits, as necessary based on the PGA setting.) At PGA = /8, full-scale range = 320mV (decimal = 32000, positive value hex = 7D00, negative value hex = 8300), and LSB = 10V. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SD14_8 SD13_8 SD12_8 SD11_8 SD10_8 SD9_8 SD8_8 SD7_8 SD6_8 SD5_8 SD4_8 SD3_8 SD2_8 SD1_8 SD0_8 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At PGA = /4, full-scale range = 160mV (decimal = 16000, positive value hex = 3E80, negative value hex = C180), and LSB = 10V. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SIGN SD13_4 SD12_4 SD11_4 SD10_4 SD9_4 SD8_4 SD7_4 SD6_4 SD5_4 SD4_4 SD3_4 SD2_4 SD1_4 SD0_4 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At PGA = /2, full-scale range = 80mV (decimal = 8000, positive value hex = 1F40, negative value hex = E0C0), and LSB = 10V. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SIGN SIGN SD12_2 SD11_2 SD10_2 SD9_2 SD8_2 SD7_2 SD6_2 SD5_2 SD4_2 SD3_2 SD2_2 SD1_2 SD0_2 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At PGA = /1, full-scale range = 40mV (decimal = 4000, positive value hex = 0FA0, negative value hex = F060), and LSB = 10V. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SIGN SIGN SIGN SD11_1 SD10_1 SD9_1 SD8_1 SD7_1 SD6_1 SD5_1 SD4_1 SD3_1 SD2_1 SD1_1 SD0_1 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 Table 6. Shunt Voltage Register Format (1) VSHUNT Reading (mV) Decimal Value PGA = / 8 (D15.....................D0) PGA = / 4 (D15.....................D0) PGA = / 2 (D15.....................D0) PGA = / 1 (D15.....................D0) 320.02 32002 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 320.01 32001 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 320.00 32000 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 319.99 31999 0111 1100 1111 1111 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 319.98 31998 0111 1100 1111 1110 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 160.02 16002 0011 1110 1000 0010 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 160.01 16001 0011 1110 1000 0001 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 160.00 16000 0011 1110 1000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 159.99 15999 0011 1110 0111 1111 0011 1110 0111 1111 0001 1111 0100 0000 0000 1111 1010 0000 159.98 15998 0011 1110 0111 1110 0011 1110 0111 1110 0001 1111 0100 0000 0000 1111 1010 0000 80.02 8002 0001 1111 0100 0010 0001 1111 0100 0010 0001 1111 0100 0000 0000 1111 1010 0000 80.01 8001 0001 1111 0100 0001 0001 1111 0100 0001 0001 1111 0100 0000 0000 1111 1010 0000 80.00 8000 0001 1111 0100 0000 0001 1111 0100 0000 0001 1111 0100 0000 0000 1111 1010 0000 79.99 7999 0001 1111 0011 1111 0001 1111 0011 1111 0001 1111 0011 1111 0000 1111 1010 0000 79.98 7998 0001 1111 0011 1110 0001 1111 0011 1110 0001 1111 0011 1110 0000 1111 1010 0000 40.02 4002 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0000 40.01 4001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0000 40.00 4000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000 39.99 3999 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111 39.98 3998 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110 0.02 2 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010 0.01 1 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -0.01 -1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -0.02 -2 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110 -39.98 -3998 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010 -39.99 -3999 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001 -40.00 -4000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000 -40.01 -4001 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0110 0000 -40.02 -4002 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0110 0000 -79.98 -7998 1110 0000 1100 0010 1110 0000 1100 0010 1110 0000 1100 0010 1111 0000 0110 0000 -79.99 -7999 1110 0000 1100 0001 1110 0000 1100 0001 1110 0000 1100 0001 1111 0000 0110 0000 -80.00 -8000 1110 0000 1100 0000 1110 0000 1100 0000 1110 0000 1100 0000 1111 0000 0110 0000 -80.01 -8001 1110 0000 1011 1111 1110 0000 1011 1111 1110 0000 1100 0000 1111 0000 0110 0000 -80.02 -8002 1110 0000 1011 1110 1110 0000 1011 1110 1110 0000 1100 0000 1111 0000 0110 0000 -159.98 -15998 1100 0001 1000 0010 1100 0001 1000 0010 1110 0000 1100 0000 1111 0000 0110 0000 -159.99 -15999 1100 0001 1000 0001 1100 0001 1000 0001 1110 0000 1100 0000 1111 0000 0110 0000 -160.00 -16000 1100 0001 1000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -160.01 -16001 1100 0001 0111 1111 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -160.02 -16002 1100 0001 0111 1110 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -319.98 -31998 1000 0011 0000 0010 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -319.99 -31999 1000 0011 0000 0001 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -320.00 -32000 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -320.01 -32001 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 -320.02 -32002 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 (1) Out-of-range values are shown in grey shading. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 27 INA219 SBOS448C - AUGUST 2008 - REVISED MARCH 2009 ................................................................................................................................................... www.ti.com Bus Voltage Register 02h (Read-Only) The Bus Voltage Register stores the most recent bus voltage reading, VBUS. At full-scale range = 32V (decimal = 8000, hex = 1F40), and LSB = 4mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 -- CNVR OVF POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At full-scale range = 16V (decimal = 4000, hex = 0FA0), and LSB = 4mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME 0 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 -- CNVR OVF POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVR: Conversion Ready Bit 1 Although the data from the last conversion can be read at any time, the INA219 Conversion Ready bit (CNVR) indicates when data from a conversion is available in the data output registers. The CNVR bit is set after all conversions, averaging, and multiplications are complete. CNVR will clear under the following conditions: 1.) Writing a new mode into the Operating Mode bits in the Configuration Register (except for Power-Down or Disable) 2.) Reading the Power Register OVF: Math Overflow Flag Bit 0 The Math Overflow Flag (OVF) is set when the Power or Current calculations are out of range. It indicates that current and power data may be meaningless. Power Register 03h (Read-Only) Full-scale range and LSB are set by the Calibration Register. See the Programming the INA219 Power Measurement Engine section. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Power Register records power in watts by multiplying the values of the current with the value of the bus voltage according to the equation: Current BusVoltage Power = 5000 Current Register 04h (Read-Only) Full-scale range and LSB depend on the value entered in the Calibration Register. See the Programming the INA219 Power Measurement Engine section. Negative values are stored in two's complement format. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The value of the Current Register is calculated by multiplying the value in the Shunt Voltage Register with the value in the Calibration Register according to the equation: Current = 28 ShuntVoltage Calibration Register 4096 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 INA219 www.ti.com ................................................................................................................................................... SBOS448C - AUGUST 2008 - REVISED MARCH 2009 CALIBRATION REGISTER Calibration Register 05h (Read/Write) Current and power calibration are set by bits D15 to D1 of the Calibration Register. Note that bit D0 is not used in the calculation. This register sets the current that corresponds to a full-scale drop across the shunt. Full-scale range and the LSB of the current and power measurement depend on the value entered in this register. See the Programming the INA219 Power Measurement Engine section. This register is suitable for use in overall system calibration. Note that the '0' POR values are all default. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (1) BIT NAME FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1) D0 is a void bit and will always be '0'. It is not possible to write a '1' to D0. CALIBRATION is the value stored in D15:D1. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): INA219 29 PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty INA219AID ACTIVE SOIC D 8 INA219AIDCNR ACTIVE SOT-23 DCN INA219AIDCNRG4 ACTIVE SOT-23 INA219AIDCNT ACTIVE INA219AIDCNTG4 INA219AIDR 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DCN 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SOT-23 DCN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE SOT-23 DCN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) INA219AIDCNR SOT-23 DCN 8 3000 179.0 INA219AIDCNT SOT-23 DCN 8 250 179.0 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Mar-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA219AIDCNR SOT-23 DCN 8 3000 195.0 200.0 45.0 INA219AIDCNT SOT-23 DCN 8 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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