©2003 Fairchild Semiconductor Corporation Rev. A, June 2003
FQP9N50C/FQPF9N50C
QFETTM
FQP9N50C/FQPF9N50C
500V N-Ch annel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction, electronic lamp ballasts
based on half bridge topology.
Features
• 9 A, 500V, RDS(on) = 0.8 Ω @VGS = 10 V
• Low gate charge ( typical 28 nC)
• Low Crss ( typical 24 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
Absolute Maximu m Ratings TC = 25°C unless otherwise noted
* Drain current limited by maximum junction temperature
Thermal Characteri stics
Symbol Parameter FQP9N50C FQPF9N50C Units
VDSS Drain-Source Voltage 500 V
IDDrain Current - Continuous (TC = 25°C) 99 *A
- Continuous (TC = 100°C) 5.4 5.4 * A
IDM Drain Current - Pulsed (Note 1) 36 36 * A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 360 mJ
IAR Avalanche Current (Note 1) 9A
EAR Repetitive Avalanche Energy (Note 1) 13.5 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns
PDPower Dissipation (TC = 25°C) 135 44 W
- Derate above 25°C 1.07 0.35 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,
1/8" from case for 5 seconds 300 °C
Symbol Parameter FQP9N50C FQPF9N50C Units
RθJC Thermal Resistance, Junction-to-Case 0.93 2.86 °C/W
RθCS Thermal Resistance, Case-to-Sink Typ. 0.5 -- °C/W
RθJA Thermal Resistance, Junction-to-Ambient 62.5 62.5 °C/W
TO-220
FQP Series
GSD TO-220F
FQPF Series
GS
D
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Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
Electrical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 8 mH, IAS = 9A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 9A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
Symbol Parame ter Test Condit i ons Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA500 -- -- V
∆BVDSS
/ ∆TJ
Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C -- 0.57 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 500 V, VGS = 0 V -- -- 1 µA
VDS = 400 V, TC = 125°C -- -- 10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA2.0 -- 4.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V, ID = 4.5 A -- 0.65 0.8 Ω
gFS Forward Transconductance VDS = 40 V, ID = 4.5 A (Note 4) -- 6.5 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 790 1030 pF
Coss Output Capacitance -- 130 170 pF
Crss Reverse Transfer Capacitance -- 24 30 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = 250 V, ID = 9 A,
RG = 25 Ω
(Note 4, 5)
-- 18 45 ns
trTurn-On Rise Time -- 65 140 ns
td(off) Turn-Off D e l a y Time -- 93 195 ns
tfTurn -Off Fa ll Time -- 64 125 ns
QgTotal Gate Ch arge VDS = 400 V, ID = 9 A,
VGS = 10 V
(Note 4, 5)
-- 28 35 nC
Qgs Gate-Source Charge -- 4 -- nC
Qgd Gate-Drain Charge -- 15 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- 9 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 36 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, I S = 9 A -- -- 1.4 V
trr Reverse Recovery Time VGS = 0 V, I S = 9 A,
dIF / dt = 100 A/µs (Note 4)
-- 335 -- ns
Qrr Reverse Recovery Charge -- 2.95 - - µC
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
0 5 10 15 20 25 30
0
2
4
6
8
10
12
VDS = 250V
VDS = 100V
VDS = 400V
$ Note : ID = 9A
VGS, Gate-Source Voltage [V]
QG, T ota l Gate Char g e [nC]
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10-1
100
101
150%
$ Notes :
1. VGS = 0V
2. 250&s Pulse Test
25%
IDR, Reverse Drain C urrent [A]
VSD, Source-Drain voltage [V]
0 5 10 15 20 25
0.5
1.0
1.5
2.0
VGS = 20V
VGS = 10V
$ No te : TJ = 25%
RDS(ON) ['],
D rain-Sou rce On-R esistance
ID, Drain Current [A]
Typical Characteristics
Figure 5. Capacitanc e Ch a racteristics Figure 6. Gate Charge C haracteris tics
Figure 3. On-Resistanc e Variatio n vs
Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage
Variation with Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i st ics
10-1 100101
10-1
100
101
VGS
Top : 15 .0 V
10 .0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Botto m : 4.5 V
$ Note s :
1. 250&s Pulse Test
2. TC = 25%
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
246810
10-1
100
101
150oC
25oC-55oC
$ Notes :
1. VDS = 40V
2. 250&s Pulse Test
ID, D rain Current [A]
VGS, Gate-Source Voltage [V]
10-1 100101
0
400
800
1200
1600
2000 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
$ Note s ;
1. VGS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [pF]
VDS, Drain-So urce Voltage [V]
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
100101102103
10-2
10-1
100
101
102
100 ms
10 µ s
DC
10 m s 1 ms
100 µ s
Opera t io n in T his A r e a
is Limited by R DS(on)
$ N ote s :
1. TC = 25 oC
2. TJ = 150 oC
3. Sing le P u lse
ID, Drain Current [A]
VDS, Drain-So urce Voltage [V]
100101102103
10-2
10-1
100
101
102
100 ms
10 µs
DC
10 m s
1 m s 100 µs
Operation in This Area
is Limited by R DS(on)
$ Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Sing le P uls e
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
Typical Characteristics (Continued)
Figure 9 -1. M aximum Safe O per at in g A re a
for FQP9N50C
Figure 10. Maximu m Drain Current
vs Case Temperat ure
Figu re 7. Breakdown Voltage Variati on
vs Temperature Figure 8. On-Resistance Variation
vs Temperature
Figure 9-2. Ma xi m um Saf e O perating Area
for FQPF9N50C
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
$ Notes :
1. VGS = 0 V
2. ID = 250 &A
BV DSS , (N ormalized)
D rain-Source Breakdown Voltage
TJ, Junction Temperature [oC]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
$ Notes :
1. VGS = 10 V
2. ID = 4.5 A
RDS(ON) , (Normalized)
Drain-Source On-Resistance
TJ, Junction Te mperature [oC]
25 50 75 100 125 150
0
2
4
6
8
10
ID, Drain Current [A]
TC, Case Tem perature [%
]
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
$ Notes :
1 . Z (JC
(t) = 2 .86 %/W M a x .
2 . Du ty Fa c to r, D = t1/t2
3 . T JM - T C = PDM * Z (JC
(t)
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
Z(JC
(t), Therm al R esponse
t1, S quare W ave Pulse Duration [sec]
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
$ Notes :
1 . Z (JC
(t) = 0.93 %/W Ma x .
2 . Du ty Fa c to r, D = t1/t2
3 . T JM - T C = PDM * Z (JC
(t)
s in g le p uls e
D=0.5
0.02
0.2
0.05
0.1
0.01
Z(JC
(t), Th erm al R esponse
t1, S quare W ave Pulse Duration [sec]
Typical Characteristics (Continued)
Figure 11-1. Transient Th er m al Response Cur ve for FQP9N50C
Figure 11-2. Transient Thermal Res ponse Curve for FQPF9N50C
t1
PDM
t2
t1
PDM
t2
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50K)
200nF
12V
Same Type
as DUT
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50K)
200nF
12V
Same Type
as DUT
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
LL
ID
ID
t p
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
Peak Diode Recovery dv/dt Test Circuit & Waveform s
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS • dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS • dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
Package Dimensions
4.50 ±0.20
9.90 ±0.20
1.52 ±0.10
0.80 ±0.10 2.40 ±0.20
10.00 ±0.20
1.27 ±0.10
ø3.60 ±0.10
(8.70)
2.80 ±0.1015.90 ±0.20
10.08 ±0.30 18.95MAX.
(1.70)
(3.70)(3.00)
(1.46)
(1.00)
(45°)
9.20 ±0.2013.08 ±0.20
1.30 ±0.10
1.30 +0.10
–0.05
0.50 +0.10
–0.05
2.54TYP
[2.54 ±0.20]2.54TYP
[2.54 ±0.20]
TO-220
Dimensions in Millimeters
Rev. A, June 2003
FQP9N50C/FQPF9N50C
©2003 Fairchild Semiconductor Corporation
Package Dimensions (Continued)
(7.00) (0.70)
MAX1.47
(30°)
#1
3.30 ±0.10
15.80 ±0.20
15.87 ±0.20
6.68 ±0.20
9.75 ±0.30
4.70 ±0.20
10.16 ±0.20
(1.00x45°)
2.54 ±0.20
0.80 ±0.10
9.40 ±0.20
2.76 ±0.20
0.35 ±0.10
ø3.18 ±0.10
2.54TYP
[2.54 ±0.20]2.54TYP
[2.54 ±0.20]
0.50 +0.10
–0.05
TO-220F
Dimensions in Millimeters
©2003 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devic es or syst em s
which, (a) ar e intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production T his datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconduct or reserv es the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I2
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