TPS79028DBVT - TEXAS INSTRUMENTS

FN6660 Rev 9.00 Page 1 of 17

Mar 19, 2018

FN6660

Rev 9.00

Mar 19, 2018

ISL80102, ISL80103

High Performance 2A and 3A Linear Regulators

DATASHEET

The ISL80102 and ISL80103 are low voltage, high-current,

single output LDOs specified for 2A and 3A output current,

respectively. These LDOs operate from the input voltages of

2.2V to 6V and are capable of providing the output voltages of

0.8V to 5.5V on the adjustable VOUT versions. Other custom

voltage options are available upon request.

An external capacitor on the soft-start pin provides adjustment

for applications that demand inrush current less than the

current limit. The ENABLE feature allows the part to be placed

into a low quiescent current shutdown mode. A submicron

BiCMOS process is used for this product family to deliver

best-in-class analog performance and overall value.

These CMOS (LDOs) consume significantly lower quiescent

current as a function of load over bipolar LDOs, so they are

more efficient and allow packages with smaller footprints. The

quiescent current has been modestly compromised to enable

a leading class fast load transient response, and hence a lower

total AC regulation band for an LDO in this category.

Related Literature

For a full list of related documents, visit our website

•ISL80102, ISL80103 product pages

Features

• Stable with ceramic capacitors (Note 11)

• 2A and 3A output current ratings

• 2.2V to 6V input voltage range

•±1.8% V

OUT accuracy guaranteed over line, load, and

TJ= -40°C to +125°C

• Very low 120mV dropout voltage at 3A (ISL80103)

• Very fast transient response

• Excellent 62dB PSRR

• 49µVRMS output noise

• Power-good output

• Adjustable inrush current limiting

• Short-circuit and over-temperature protection

• Available in a 10 Ld DFN

Applications

•Servers

• Telecommunications and networking

• Medical equipment

• Instrumentation systems

•Routers and switchers

FIGURE 1. TYPICAL APPLICATION FOR FIXED OUTPUT VOLTAGE VERSION

ISL80102, ISL80103

VIN

ENABLE

GND

2.5V ±10%

CIN

10µF

VIN

OFF

*CSS

VOUT

1.8V ±1.8%

COUT

10µF

RPG

100kΩ

SENSE 3

PGOOD

*CSS is optional (see Note 12 on page 5).

ISL80102, ISL80103

FN6660 Rev 9.00 Page 2 of 17

Mar 19, 2018

Pin Configuration

ISL80102, ISL80103

(10 LD 3x3 DFN)

TOP VIEW

FIGURE 2. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION

ISL80102, ISL80103

VIN

ENABLE

GND

2.5V ±10%

CIN

10µF

VIN

*CSS

PG 4

VOUT

VOUT 2

VOUT

1.8V

COUT

10µF RPG

100kΩ

ADJ 3

PGOOD

10kΩ

1.0kΩ

**CPB

47pF

OPEN DRAIN COMPATIBLE

*CSS is optional (see Note 12 on page 5).

**CPB is optional (see “Functional Description” on page 12 for more information).

2.61kΩ

TABLE 1. COMPONENTS VALUE SELECTION

VOUT

(V)

RTOP

(kΩ)

RBOTTOM

(Ω)

CPB

(pF)

COUT

(µF)

5.0 2.61 287 47 10

3.3 2.61 464 47 10

2.5 2.61 649 47 10

1.8 (Note 1) 2.61 1.0k 47 10

1.8 (Note 1) 2.61 1.0k 82 22

1.5 2.61 1.3k 82 22

1.2 2.61 1.87k 150 47

1.0 2.61 2.61k 150 47

0.8 2.61 4.32k 150 47

NOTE:

1. Either option can be used depending on cost/performance

requirements

VOUT

SENSE/ADJ

GND

VIN

DNC

ENABLE

EPAD

Pin Descriptions

NUMBER

NAME DESCRIPTION

1, 2 VOUT Output voltage pin

3SENSE/

ADJ

Remote voltage sense for internally fixed VOUT

options. ADJ pin for externally set VOUT.

4PGV

OUT in regulation signal. Logic low defines when

VOUT is not in regulation. Must be grounded if not

used.

5GNDGND pin

6 SS External cap adjusts inrush current. Leave this pin

open if not used.

7ENABLE V

IN independent chip enable. TTL and CMOS

compatible.

8 DNC Do not connect this pin to ground or supply. Leave

floating.

9, 10 VIN Input supply pin

EPAD EPAD must be connected to a copper plane with as

many vias as possible for proper electrical and

optimal thermal performance.

ISL80102, ISL80103

FN6660 Rev 9.00 Page 3 of 17

Mar 19, 2018

Block Diagram

10µA 10µA

M5 M4

EN EN

ENEN

ENABLE M7

500mV

485mV

500mV

POWER PMOS

VIN

VOUT

SENSE

R4R2

*R3

GND

ADJ

V TO I

IL/10000

M8 EN

*R3 is open for ADJ versions.

FIGURE 3. BLOCK DIAGRAM

Ordering Information

PART NUMBER

(Notes 4, 5)

PART

MARKING

VOUT

VOLTAGE

TEMP. RANGE

(°C)

PACKAGE

(RoHS COMPLIANT)

PKG

DWG. #

ISL80102IRAJZ (Note 2) DZJA ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL80102IR18Z (Note 3)

(No longer available, recommended replacement: ISL80102IRAJZ)

DZNA 1.8V -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL80102IR25Z (Note 3)

(No longer available, recommended replacement: ISL80102IRAJZ)

DZPA 2.5V -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL80103IRAJZ (Note 2) DZAA ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL80103IR18Z (Note 3)

(No longer available, recommended replacement: ISL80103IRAJZ)

DZEA 1.8V -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL80103IR25Z (Note 3)

(No longer available, recommended replacement: ISL80103IRAJZ)

DZFA 2.5V -40 to +125 10 Ld 3x3 DFN L10.3x3

ISL80102EVAL2Z Evaluation Board

ISL80103EVAL2Z Evaluation Board

NOTES:

2. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit, or “-T7A” suffix for 250 unit tape and reel options. Refer to TB347 for details about reel specifications.

3. Add “-T” suffix for 6k unit or “-TK” suffix for 1k unit tape and reel options. Refer to TB347 for details about reel specifications.

4. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

5. For Moisture Sensitivity Level (MSL), refer to the ISL80102 and ISL80103 product information pages. For more information about MSL, refer to TB363.

ISL80102, ISL80103

FN6660 Rev 9.00 Page 4 of 17

Mar 19, 2018

Absolute Maximum Ratings (Note 8)Thermal Information

VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

PG, ENABLE, SENSE/ADJ, SS, Relative to GND. . . . . . . . . . . -0.3V to +6.5V

ESD Rating

Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.2kV

Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV

Latch-up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C

Recommended Operating Conditions

Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C

VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V

VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5.5V

PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . . . 0V to 6V

PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Thermal Resistance (Typical) JA (°C/W) JC (°C/W)

10 Ld 3x3 DFN Package (Notes 6, 7). . . . . 45 4

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. Refer to

TB379.

7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

8. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.

Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:

2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction

temperature. Refer to “Functional Description” on page 12 and TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C.

Pulse load techniques used by ATE to ensure TJ = TA defines established limits.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 9)TYP

MAX

(Note 9)UNIT

DC CHARACTERISTICS

DC Output Voltage Accuracy VOUT VOUT options: 1.8V

2.2V < VIN < 6V; ILOAD = 0A

0.5 %

VOUT options: 1.8V

2.2V < VIN < 6V; 0A < ILOAD < 3A

-1.8 1.8 %

VOUT options: 2.5V

6V < VIN < 6V; ILOAD = 0A

0.5 %

VOUT options: 2.5V

6V < VIN < 6V; 0A < ILOAD < full load

-1.8 -1.8 %

Feedback Pin (ADJ Version) VADJ 0A < ILOAD < full load 491 500 509 mV

DC Input Line Regulation (VOUT Low Line - VOUT

High Line)/

VOUT Low Line

2.2V < VIN < 3.6V, VOUT = 1.8V -0.4 0.1 0.4 %

2.9V < VIN < 6V, VOUT = 2.5V -0.8 0.1 0.8 %

DC Output Load Regulation (VOUT No Load - VOUT

High Load)/

VOUT No Load

ISL80103, 0A < ILOAD < 3A,

2.9V < VIN < 6V; VOUT = 2.5V for adjustable version.

VOUT = 1.8V and 2.5V for fixed version.

-0.8 -0.2 0.8 %

ISL80102, 0A < ILOAD < 2A

2.9V < VIN < 6V; VOUT = 2.5V for adjustable version.

VOUT = 1.8V and 2.5V for fixed version.

-0.6 -0.2 0.6 %

Feedback Input Current VADJ = 0.5V 0.01 1µA

Ground Pin Current IQILOAD = 0A, VOUT + 0.4V < VIN < 6V for all options.

VOUT = 2.5V for adjustable option.

7.5 9mA

ILOAD = 3A, VOUT + 0.4V < VIN < 6V for all options.

VOUT = 2.5V for adjustable option.

8.5 12 mA

ISL80102, ISL80103

FN6660 Rev 9.00 Page 5 of 17

Mar 19, 2018

Ground Pin Current in Shutdown ISHDN EN = 0V, VIN = 5V 0.4 µA

EN = 0V, VIN = 6V 3.3 16.0 µA

Dropout Voltage (Note 10)V

DO ISL80103, ILOAD = 3A, VOUT = 2.5V 120 185 mV

ISL80102, ILOAD = 2A, VOUT = 2.5V 81 125 mV

ISL80103, ILOAD = 3A, VOUT = 5.5V 120 244 mV

ISL80102, ILOAD = 2A, VOUT = 5.5V 60 121 mV

Output Short-Circuit Current

(3A Version)

ISC ISL80103, VOUT = 0V 5.0 A

Output Short-Circuit Current

(2A Version)

ISL80102, VOUT = 0V 2.8 A

Thermal Shutdown Temperature TSD 160 °C

Thermal Shutdown Hysteresis TSDn 15 °C

AC CHARACTERISTICS

Input Supply Ripple Rejection PSRR f = 1kHz, ILOAD = 1A; VIN = 2.2V 55 dB

f = 120Hz, ILOAD = 1A; VIN = 2.2V 62 dB

Output Noise Voltage VIN = 2.2V, VOUT = 1.8V, ILOAD = 3A,

BW = 100Hz < f < 100kHz

49 µVRMS

ENABLE PIN CHARACTERISTICS

Turn-On Threshold VEN(HIGH) 2.9V < VIN < 6V for 2.5V for fixed output option.

2.2V < VIN < 6V for adjustable and 1.8V

0.616 0.800 0.950 V

Turn-Off Threshold VEN(LOW) 2.9V < VIN < 6V for 2.5V fixed output option.

2.2V < VIN < 6V for adjustable and 1.8V

0.463 0.600 V

Hysteresis VEN(HYS) 2.9V < VIN < 6V for 2.5V fixed output option.

2.2V < VIN < 6V for adjustable and 1.8V

135 mV

Enable Pin Turn-On Delay tEN COUT = 10µF, ILOAD = 1A 150 µs

Enable Pin Leakage Current VIN = 6V, EN = 3V 1µA

SOFT-START CHARACTERISTICS

Reset Pull-Down Resistance RPD 323 Ω

Soft-Start Charge Current ICHG -7.0 -4.5 -2.0 µA

PG PIN CHARACTERISTICS

VOUT PG Flag Threshold 75 84 92 %VOUT

VOUT PG Flag Hysteresis 4%

PG Flag Low Voltage ISINK = 500µA 47 100 mV

PG Flag Leakage Current VIN = 6V, PG = 6V 0.05 1µA

NOTES:

9. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.

10. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal value.

11. Minimum cap of 10µF X5R/X7R on VIN and VOUT required for stability.

12. If the current limit for inrush current is acceptable in the application, do not use this feature (leave the SS pin open). Use only when large bulk capacitance

is required on VOUT for the application.

Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:

2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction

temperature. Refer to “Functional Description” on page 12 and TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C.

Pulse load techniques used by ATE to ensure TJ = TA defines established limits. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 9)TYP

MAX

(Note 9)UNIT

ISL80102, ISL80103

FN6660 Rev 9.00 Page 6 of 17

Mar 19, 2018

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A.

FIGURE 4. VOUT vs TEMPERATURE FIGURE 5. OUTPUT VOLTAGE vs SUPPLY VOLTAGE

FIGURE 6. VOUT vs OUTPUT CURRENT FIGURE 7. GROUND CURRENT vs SUPPLY VOLTAGE

FIGURE 8. GROUND CURRENT vs OUTPUT CURRENT FIGURE 9. GROUND CURRENT vs OUTPUT VOLTAGE (VIN = VOUT + VDO)

1.8

1.2

0.6

-0.6

-1.2

-1.8-50 -25 0 25 50 75 100 125 150

JUNCTION TEMPERATURE (°C)

VOUT (%)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0246

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

135

+125°C

+25°C -40°C

-1.8

-1.2

-0.6

0.0

0.6

1.2

1.8

0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT CURRENT (A)

VOUT (%)

+125°C

+25°C

-40°C

INPUT VOLTAGE (V)

GROUND CURRENT (mA)

3456

7.5

7.7

7.9

8.1

8.3

8.5

8.7

8.9

9.1

0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT CURRENT (A)

GROUND CURRENT (mA)

+125°C

+25°C

-40°C

7.5

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0

OUTPUT VOLTAGE (V)

CURRENT (mA)

+125°C

+25°C

-40°C

ISL80102, ISL80103

FN6660 Rev 9.00 Page 7 of 17

Mar 19, 2018

FIGURE 10. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE FIGURE 11. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE

FIGURE 12. DROPOUT VOLTAGE vs TEMPERATURE FIGURE 13. DROPOUT VOLTAGE vs OUTPUT CURRENT

FIGURE 14. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A. (Continued)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

GROUND CURRENT (µA)

VIN = 5V

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

GROUND CURRENT (µA)

VIN = 6V

100

110

120

130

140

150

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

DROPOUT VOLTAGE (mV)

100

110

120

130

140

150

0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (mV)

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

-40 -25 -10 5 20 35 50 65 80 95 110 125

JUNCTION TEMPERATURE (°C)

VOLTAGE (V)

ISL80102, ISL80103

FN6660 Rev 9.00 Page 8 of 17

Mar 19, 2018

FIGURE 15. ENABLE START-UP SS CAP 1nF FIGURE 16. ENABLE SHUTDOWN SS CAP 1nF

FIGURE 17. ENABLE START-UP SS CAP 100nF FIGURE 18. ENABLE START-UP (NO SS CAP)

FIGURE 19. ENABLE SHUTDOWN (NO SS CAP) FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A. (Continued)

SS (500mV/DIV)

VOUT (500mV/DIV)

PG (1V/DIV)

TIME (100µs/DIV)

EN (1V/DIV)

SS (500mV/DIV)

VOUT (500mV/DIV)

PG (1V/DIV)

TIME (6.4ms/DIV)

EN (1V/DIV)

SS (500mV/DIV)

VOUT (500mV/DIV)

PG (1V/DIV)

TIME (100µs/DIV)

EN (1V/DIV)

SS (1V/DIV)

VOUT (1V/DIV)

PG (1V/DIV)

TIME (50µs/DIV)

EN (1V/DIV)

SS (1V/DIV)

VOUT

(1V/DIV

)

PG (1V/DIV)

TIME (5ms/DIV)

EN (1V/DIV)

100

150

200

250

300

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

INPUT VOLTAGE (V)

START-UP TIME (µs)

ISL80102, ISL80103

FN6660 Rev 9.00 Page 9 of 17

Mar 19, 2018

FIGURE 21. START-UP TIME vs TEMPERATURE FIGURE 22. CURRENT LIMIT vs TEMPERATURE

FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE FIGURE 24. CURRENT LIMIT RESPONSE (ISL80102)

FIGURE 25. CURRENT LIMIT RESPONSE (ISL80103) FIGURE 26. INRUSH CURRENT WITH NO SOFT-START CAPACITOR,

COUT = 1000µF

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A. (Continued)

100

150

200

250

300

-40 -25 -10 5 20 35 50 65 80 95 110 125

JUNCTION TEMPERATURE (°C)

START-UP TIME (µs)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

ISL80103

ISL80102

OUTPUT CURRENT (A)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

INPUT VOLTAGE(V)

OUTPUT CURRENT (A)

ISL80103

ISL80102

IOUT (1A/DIV)

VOUT (1V/DIV)

TIME (10ms/DIV)

IOUT (2A/DIV)

VOUT (1V/DIV)

TIME (5ms/DIV)

VOUT (1V/DIV)

PG (1V/DIV)

TIME (200µs/DIV)

EN (1V/DIV)

IINRUSH (2A/DIV)

ISL80102, ISL80103

FN6660 Rev 9.00 Page 10 of 17

Mar 19, 2018

FIGURE 27. INRUSH WITH 22nF SOFT-START CAPACITOR,

COUT = 1000µF

FIGURE 28. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC

FIGURE 29. LOAD TRANSIENT 0A TO 3A, COUT =10µF

CERAMIC + 100µF OSCON

FIGURE 30. LOAD TRANSIENT 1A TO 3A, COUT = 10µF CERAMIC

FIGURE 31. LOAD TRANSIENT 1A TO 3A, COUT = 10µF

CERAMIC + 100µF OSCON

FIGURE 32. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC,

NO CPB (ADJ VERSION)

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A. (Continued)

TIME (1ms/DIV)

VOUT (1V/DIV)

PG (1V/DIV)

EN (1V/DIV)

IINRUSH (1A/DIV)

di/dt = 30A/µs

TIME (200µs/DIV)

VOUT (50mV/DIV)

IOUT (2A/DIV)

di/dt = 30A/µs

TIME (200µs/DIV)

VOUT (50mV/DIV)

IOUT (2A/DIV)

di/dt = 30A/µs

TIME (200µs/DIV)

VOUT (50mV/DIV)

IOUT (2A/DIV)

di/dt = 30A/µs

TIME (200µs/DIV)

VOUT (50mV/DIV)

IOUT (2A/DIV)

di/dt = 3A/µs

TIME (50µs/DIV)

VOUT (20mV/DIV)

IOUT (2A/DIV)

ISL80102, ISL80103

FN6660 Rev 9.00 Page 11 of 17

Mar 19, 2018

FIGURE 33. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC,

CPB = 1500pF (ADJ VERSION)

FIGURE 34. LINE TRANSIENT

FIGURE 35. PSRR vs FREQUENCY FOR VOUT = 1.0V, VIN = 2.5V;

COUT = 47µF, CPB = 150pF

FIGURE 36. PSRR vs FREQUENCY FOR VOUT = 1.2V; VIN = 2.5V;

COUT = 47µF, CPB = 150pF

FIGURE 37. PSRR vs FREQUENCY FOR VOUT = 1.5V, VIN = 2.5V;

COUT = 22µF, CPB = 82pF

FIGURE 38. PSRR vs FREQUENCY FOR VOUT = 1.8V, VIN = 2.5V;

COUT = 22µF, CPB = 82pF

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A. (Continued)

di/dt = 3A/sec

di/dt = 3A/µs

TIME (50µs/DIV)

VOUT (20mV/DIV)

IOUT (2A/DIV)

VOUT (10mV/DIV)

VIN (1V/DIV)

TIME (200µs/DIV)

3.2V

2.2V

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

PSRR (dB)

NO LOAD

1000mA

300mA

100mA

NO LOAD

1000mA 300mA

100mA

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

PSRR (dB)

10 100 1k 10k 100k 1M

NO LOAD

1000mA

300mA 100mA

2000mA

FREQUENCY (Hz)

PSRR (dB)

10 100 1k 10k 100k 1M

NO LOAD

1000mA

300mA

100mA

2000mA 3000mA

FREQUENCY (Hz)

PSRR (dB)

ISL80102, ISL80103

FN6660 Rev 9.00 Page 12 of 17

Mar 19, 2018

Functional Description

Input Voltage Requirements

Despite other output voltages offered, this family of LDOs is

optimized for a true 2.5V to 1.8V conversion in which the input

supply can have a tolerance of as much as ±10% for conditions

noted in the “Electrical Specifications” table on page 4. The

minimum guaranteed input voltage is 2.2V; however, due to the

nature of an LDO, VIN must be some margin higher than the

output voltage plus dropout at the maximum rated current of the

application if active filtering (PSRR) is expected from VIN to VOUT.

The dropout of this family of LDOs has been generously specified

to allow applications to design for a level of efficiency that can

accommodate the smaller outline package.

Enable Operation

The Enable turn-on threshold is typically 800mV with a hysteresis of

135mV. An internal pull-up or pull-down resistor is available upon

request. As a result, this pin must not be left floating. This pin must

be tied to VIN if it is not used. A 1kΩ to 10kΩ pull-up resistor is

required for applications that use open collector or open drain

outputs to control the Enable pin. The Enable pin can be connected

directly to VIN for applications that are always on.

Power-Good Operation

Applications not using the power-good (PGOOD) feature must

connect this pin to ground. The PGOOD flag is an open-drain

NMOS that can sink up to 10mA during a fault condition. The

PGOOD pin requires an external pull-up resistor, which is typically

connected to the VOUT pin. The PGOOD pin should not be pulled

up to a voltage source greater than VIN. PGOOD faults can be

caused by the output voltage going below 84% of the nominal

output voltage, or the current limit fault, or low input voltage.

PGOOD does not function during thermal shutdown.

Soft-Start Operation (Optional)

If the current limit for inrush current is acceptable in the

application, do not use the soft-start (SS) feature (leave the SS

pin open). The soft-start circuit controls the rate at which the

output voltage comes up to regulation at power-up or LDO

enable. The external soft-start capacitor always gets discharged

to ground pin potential at the beginning of start-up or enabling.

After the capacitor discharges, it will immediately begin charging

by a constant current source. The discharge rate is the RC time

constant of RPD and CSS. Refer to Figures 15 through 19 in the

“Typical Operating Performance Curves” beginning on page 8.

RPD is the ON-resistance of the pull-down MOSFET, M8. RPD is

typically 323Ω.

The soft-start feature effectively reduces the inrush current at

power-up or LDO enable until VOUT reaches regulation. The

in-rush current can be an issue for applications that require large,

external bulk capacitances on VOUT where high levels of charging

current can be seen for a significant period of time. The inrush

currents can cause VIN to drop below minimum which could

cause VOUT to shutdown. Figure 27 on page 10 shows the

relationship between inrush current and CSS with a COUT of

1000µF.

FIGURE 39. PSRR vs FREQUENCY FOR VOUT = 2.5V, VIN = 3.3V;

COUT = 10µF, CPB = 47pF

FIGURE 40. SPECTRAL NOISE DENSITY vs FREQUENCY

Typical Operating Performance Unless otherwise noted, VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

IL = 0A. (Continued)

10 100 1k 10k 100k 1M

NO LOAD

1000mA

300mA

100mA

2000mA

3000mA

FREQUENCY (Hz)

PSRR (dB)

0.01

0.1

10 100 1k 10k 100k 1M

NOISE µV/√Hz

FREQUENCY (Hz)

IL = 3A

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 20406080100

CSS (nF)

INRUSH CURRENT LIMIT (A)

FIGURE 41. INRUSH CURRENT vs SOFT-START CAPACITANCE

ISL80102, ISL80103

FN6660 Rev 9.00 Page 13 of 17

Mar 19, 2018

Output Voltage Selection

An external resistor divider scales the output voltage relative to

the internal reference voltage. This voltage is then fed back to

the error amplifier. The output voltage can be programmed to

any level between 0.8V and 5.5V. An external resistor divider, R3

and R4, sets the output voltage as shown in Equation 1. The

recommended value for R4 is 200Ω to 5kΩR3is then chosen

according to Equation 2:

External Capacitor Requirements

External capacitors are required for proper operation. To ensure

optimal performance, pay careful attention to the layout

guidelines and selection of capacitor type and value.

OUTPUT CAPACITOR

The ISL80102 and ISL80103 apply state-of-the-art internal

compensation to keep selection of the output capacitor simple

for the customer. Stable operation over full temperature, VIN

range, VOUT range, and load extremes are guaranteed for all

ceramic capacitors and values assuming a 10µF X5R/X7R is

used for local bypass on VOUT. This minimum capacitor (see

Table 1 on page 2 for component value selections) must be

connected to the VOUT and ground pins of the LDO with PCB

traces no longer than 0.5cm.

Lower cost Y5V and Z5U type ceramic capacitors are acceptable

if the size of the capacitor is large enough to compensate for the

significantly lower tolerance over X5R/X7R types. Additional

capacitors of any value in Ceramic, POSCAP, or Alum/Tantalum

Electrolytic types can be placed in parallel to improve PSRR at

higher frequencies and/or load transient AC output voltage

tolerances.

INPUT CAPACITOR

The minimum input capacitor required for proper operation is a

10µF with a ceramic dielectric. This minimum capacitor must be

connected to VIN and ground pins of the LDO with PCB traces no

longer than 0.5cm.

Phase Boost Capacitor (Optional)

The ISL80102 and ISL80103 are designed to be stable with

10µF or larger ceramic capacitors.

Applications using the ADJ versions may see improved

performance with the addition of a small ceramic capacitor CPB

as shown in Figure 2 on page 2. The conditions in which CPB may

be beneficial are:

•V

OUT > 1.5V

•C

OUT = 10µF

• Tight AC voltage regulation band

CPB introduces phase lead with the product of R3 and CPB that

results in increasing the bandwidth of the LDO. Typical R3 x CPB

should be less than 0.4μs (400ns).

Current Limit Protection

The ISL80102 and ISL80103 family of LDOs incorporates

protection against overcurrent due to a short overload condition

applied to the output and the inrush current that occurs at

start-up. The LDO performs as a constant current source when

the output current exceeds the current limit threshold noted in

the “Electrical Specifications” table on page 4. If the short or

overload condition is removed from VOUT, then the output returns

to normal voltage mode regulation. In the event of an overload

condition, the LDO may begin to cycle on and off due to the die

temperature exceeding the thermal fault condition.

Power Dissipation and Thermals

The junction temperature must not exceed the range specified in

the “Recommended Operating Conditions” on page 4. The power

dissipation can be calculated by using Equation 3:

The maximum allowable junction temperature, TJ(MAX) and the

maximum expected ambient temperature, TA(MAX) will

determine the maximum allowable power dissipation as shown

in Equation 4:

where JA is the junction-to-ambient thermal resistance.

For safe operation, ensure that the power dissipation calculated

in Equation 3, PD, is less than the maximum allowable power

dissipation PD(MAX).

The DFN package uses the copper area on the PCB as a heatsink.

The EPAD of this package must be soldered to the copper plane

(GND plane) for heat sinking. Figure 42 shows a curve for the JA

of the DFN package for different copper area sizes.

Thermal Fault Protection

If the die temperature exceeds typically +160°C, then the output

of the LDO will shut down until the die temperature can cool

down to typically +145°C. The level of power combined with the

thermal impedance of the package (+48°C/W for DFN) will

determine if the junction temperature exceeds the thermal

shutdown temperature.

VOUT 0.5V

-------1+







=(EQ. 1)

R3R4

VOUT

0.5V

----------------1–





=(EQ. 2)

PDVIN VOUT

–IOUT VIN IGND

+=(EQ. 3)

PDMAX

TJMAX

–

=(EQ. 4)

FIGURE 42. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH

THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND

AREA ON PCB

JA (°C/W)

2 4 6 8 10 12 14 16 18 20 22 24

EPAD-MOUNT COPPER LAND AREA ON PCB, mm2

ISL80102, ISL80103

FN6660 Rev 9.00 Page 14 of 17

Mar 19, 2018

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please go to web to make sure you have the latest Rev.

DATE REVISION CHANGE

Mar 19, 2018 FN6680.9 Added Related Literature section to page 1.

Changed values in Output Voltage Selection section on page 13 from “500Ω to 1kΩ” to “200Ω to 5kΩ”.

Removed About Intersil section and added Renesas disclaimer.

Sep 2, 2016 FN6660.8 Removed Note 8 “Electromigration specification defined as lifetime average junction temperature of +110°C

where max rated DC current = lifetime average current” from Recommended Operating Conditions.

Apr 8, 2016 FN6660.7 Updated Ordering Information table (on page 3), Note 1 to include quantities for tape and reel options.

Changed VOUT range upper limit from “5V to 5.5V” on page 1, in the “Recommended Operating Conditions

(Note 7)” on page 4 and in the “Output Voltage Selection” on page 12

Electrical Spec table test conditions changed from: VIN =V

OUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C,

ILOAD = 0A, to: 2.2V < VIN < 6V, VOUT = 0,5V, TJ = +25°C, ILOAD = 0A

Changed Test conditions in “Output Noise Voltage” on page 5 from: ILOAD = 10mA, BW = 300Hz <f< 300kHz; to:

VIN = 2.2V, VOUT = 1.8V, ILOAD = 3A, BW = 100Hz<f<100kHz and changed TYP from: 100; to: 49

Added two rows to “Dropout Voltage (Note 9)” on page 5 to show parameters for 5.5V VOUT conditions.

Updated verbiage for “About Intersil” on page 16.

Updated POD L10.3x3 to most updated revision with changes as follows:

Added missing dimension 0.415 in Typical Recommended land pattern.

Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line up

with the centers of the corner pins.

Changed Tiebar note 4, from: Tiebar shown (if present) is a non-functional feature.

to: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).

May 23, 2013 FN6660.6 Pin Descriptions on page page 2, updated EPAD section From: EPAD at ground potential. Soldering it directly to

GND plane is optional. To: EPAD must be connected to copper plane with as many vias as possible for proper

electrical and optimal thermal performance.

Removed obsolete part numbers: ISL80102IR33Z, ISL80102IR50Z, ISL80103IR33Z, ISL80103IR50Z from

ordering information table on page 3.

Added evaluation boards to ordering information table on page 3: ISL80103IR50Z and ISL80103EVAL2Z.

Features on page 1: Removed 5 Ld TO220 and 5 Ld TO263.

Input Voltage Requirements on page 12: Removed the sentence “those applications that cannot accommodate

the profile of the TO220/TO263”.

Jun 14, 2012 FN6660.5 In “Thermal Information” on page 4, corrected JA from 48 to 45.

Feb 14, 2012 FN6660.4 Increased “VEN(HIGH)” minimum limit from 0.4V to 0.616 and added the “VEN(LOW)” spec for clarity on page 5.

Dec 14, 2011 FN6660.3 Increased “Turn-on Threshold” minimum limit on page 5 from 0.3V to 0.4V.

Updated “Package Outline Drawing” on page 16 as follows:

Removed package outline and included center to center distance between lands on recommended land pattern.

Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm

from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.

Mar 4, 2011 FN6660.2 Converted to new template

On page 1 - first paragraph, changed "Fixed output voltage options are available in 1.5V, 1.8V, 2.5V, 3.3V and 5V"

to "Fixed output voltage options are available in 1.8V, 2.5V, 3.3V and 5V"

In “Ordering Information” table on page 2, removed ISL80102IR15Z and ISL80103IR15Z.

In Note 3 on page 2, below the “Ordering Information” table, removed '1.5V', so it reads “The 3.3V and 5V fixed

output voltages will be released in the future. Please contact Intersil Marketing for more details.”

ISL80102, ISL80103

FN6660 Rev 9.00 Page 15 of 17

Mar 19, 2018

Mar 4, 2010 FN6660.1 Corrected Features on page 1 as follows:

-Changed bullet "• 185mV Dropout @ 3A, 125mV Dropout @ 2A" to "• Very Low 120mV Dropout at 3A"

-Changed bullet "• 65dB Typical PSRR" to "• 62dB Typical PSRR"

-Deleted 0.5% Initial VOUT Accuracy

Modified Figure 1 and placed as “TYPICAL APPLICATION” on page 1.

Moved Pinout to page 3

In “Block Diagram” on page 2, corrected resistor associated with M5 from R4 to R5

Updated “Block Diagram” on page 2 as follows”

- Added M8 from SS to ground.

Updated Figure 1 on page 1 as follows:

-Corrected Pin 6 from SS to IRSET

-Removed Note 11 callout "Minimum cap on VIN and VOUT required for stability." Added Note "*CSS is optional.

See Note 12 on Page 5." and “** CPB is optional. See “Functional Description” on page 12 for more information.”

Added "The 1.5V, 3.3V and 5V fixed output voltages will be released in the future." to Note 3 on page 2.

In “Thermal Information” on page 4, updated Theta JA from 45 to 48.

In “Soft-Start Operation (Optional)” on page 12:

-Changed "The external capacitor always gets discharged to 0V at start-up of after coming out of a chip disable.

"The external capacitor always gets discharged to ground pin potential at start-up or enabling."

-Changed "The soft-start function effectively limits the amount of inrush current below the programmed current

limit during start-up or an enable sequence to avoid an overcurrent fault condition." to "The soft-start feature

effectively reduces the inrush current at power-up or LDO enable until VOUT reaches regulation."

-Added "See Figures 25 through 27 in the “Typical Operating Performance Curves” beginning on page 6."

-Added “RPD is the on resistance of the pull-down MOSFET, M8. RPD is 300Ω typically.”

Mar 4, 2010 Added “Phase Boost Capacitor (Optional)” on page 13.

In “Typical Operating Performance” on page 11, revised figure "PSRR vs VIN" which had 3 curves with “SPECTRAL

NOISE DENSITY vs FREQUENCY” which has one curve.

Added "Figure 33. “LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC, NO CPB (ADJ VERSION)” and "Figure 34.

“LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC, CPB = 1500pF (ADJ VERSION)”

Sep 30, 2009 FN6660.0 Initial Release.

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please go to web to make sure you have the latest Rev. (Continued)

DATE REVISION CHANGE

ISL80102, ISL80103

FN6660 Rev 9.00 Page 16 of 17

Mar 19, 2018

Package Outline Drawing

L10.3x3

10 LEAD DUAL FLAT PACKAGE (DFN)

Rev 11, 3/15

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

The configuration of the pin #1 identifier is optional, but must be

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

(4X) 0.10

INDEX AREA

PIN 1

PIN #1 INDEX AREA

SEATING PLANE

BASE PLANE

0.08

SEE DETAIL "X"

0.10 C

1.00

0.20

8x 0.50

2.00

3.00

(10x 0.23)

(8x 0.50)

2.00

1.60

(10 x 0.55)

3.00

0.05

0.20 REF

10 x 0.23

10x 0.35

1.60

MAX

(4X) 0.10 AB

0.415

0.23

0.35

0.200

2.85 TYP

0.415

Tiebar shown (if present) is a non-functional feature and may be

located on any of the 4 sides (or ends).

For the most recent package outline drawing, see L10.3x3.

http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.

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Notice

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