DESCRIPTION
The A5988 is a quad DMOS full-bridge driver capable of driving
up to two stepper motors or four DC motors. Each full-bridge
output is rated up to 1.6 A and 40 V. The A5988 includes fixed
off-time pulse-width modulation (PWM) current regulators,
along with 2- bit nonlinear DACs (digital-to-analog converters)
that allow stepper motors to be controlled in full, half, and
quarter steps, and DC motors in forward, reverse, and coast
modes. The PWM current regulator uses the Allegro™ patented
mixed decay mode for reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover-current protection.
Special power-up sequencing is not required.
The A5988 is supplied in two packages, EV and JP, with exposed
power tabs for enhanced thermal performance. The EV is a
6 mm × 6 mm, 36-pin QFN package with a nominal overall
package height of 0.90 mm. The JP is a 7 mm × 7 mm 48-pin
LQFP. Both packages are lead (Pb) free, with 100% matte-tin
leadframe plating.
A5988-DS, Rev. 1
FEATURES AND BENEFITS
• 40 V output rating
• 4 full bridges
• Dual stepper motor driver
• High-current outputs
• 3.3 and 5 V compatible logic
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Thermal shutdown circuitry
• Crossover-current protection
• Overcurrent protection
• Low-power sleep mode
• Low-profile QFN package
Quad DMOS Full-Bridge PWM Motor Driver
PACKAGES
A5988
Figure 1: Typical Application Circuit
PHASE1
I01
I11
SENSE1
OUT2A
OUT1A
SENSE2
OUT2B
OUT1B
VCP
VBB1
VBB2
SLEEPn SENSE4
OUT4B
OUT4A
SENSE3
OUT3B
OUT3A
VREF2
CP1
CP2
PHASE2
VREF1
VREF4
VREF3
V
REF
V32 V
MOTOR
I02
I12
PHASE3
I03
I13
PHASE4
I04
I14 R
S2
R
S1
R
S3
R
S4
0.1 µF
50 V
100 µF
50 V
0.22 µF
50 V
0.1 µF
50 V
A5988
Bipolar Stepper Motors
Microprocessor
FAULTn*
* JP package only
Package EV, 36-pin QFN
0.90 mm nominal height
with exposed thermal pad
Package JP, 48-pin LQFP
with exposed thermal pad Not to scale
Quad DMOS Full-Bridge PWM Motor Driver
A5988
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
SELECTION GUIDE
Part Number Package Packing Fixed Off-Time (µs)
A5988GEVTR-T 36-pin QFN with exposed thermal pad 1500 pieces per reel 30
A5988GJPTR-T 48-pin LQFP with exposed thermal pad 1500 pieces per reel 30
A5988GEVTR-1-T 36-pin QFN with exposed thermal pad 1500 pieces per reel 8.1
A5988GJPTR-1-T 48-pin LQFP with exposed thermal pad 1500 pieces per reel 8.1
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB –0.5 to 40 V
Output Current IOUT May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
1.6 A
Logic Input Voltage Range VIN –0.3 to 7 V
SENSEx Pin Voltage VSENSEx0.5 V
Pulsed tw < 1 µs 2.5 V
VREFx Pin Voltage VREFx2.5 V
Operating Temperature Range TARange G –40 to 105 ºC
Junction Temperature TJ(max) 150 ºC
Storage Temperature Range Tstg –40 to 125 ºC
THERMAL CHARACTERISTICS (may require derating at maximum conditions)
Characteristic Symbol Test Conditions Min. Units
Package Thermal Resistance RθJA
EV package, 4-layer PCB based on JEDEC standard 27 ºC/W
JP package, 4-layer PCB based on JEDEC standard 23 ºC/W
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
25 50 75 100 125 150 175
Temperature (°C)
Power Dissipation, P
D
(mW)
Power Dissipation versus Ambient Temperature
(RθJA = 23 ºC/W)
JP Package
4-layer PCB
(RθJA = 27 ºC/W)
EV Package
4-layer PCB
Quad DMOS Full-Bridge PWM Motor Driver
A5988
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL BLOCK DIAGRAM
CHARGE PUMP
DMOS
FULL-BRIDGE 1
DMOS
FULL-BRIDGE 2
DMOS
FULL-BRIDGE 4
DMOS
FULL-BRIDGE 3
V
CP
To
V
BB2
PHASE1
I01
I11
SENSE1
OUT1B
OUT1A
SENSE2
OUT2B
OUT2A
VCP
SLEEPn OSC
SENSE4
OUT4B
OUT4A
SENSE3
OUT3B
OUT3A
VBB2
Sense2
Sense3
Sense4
+ -
+ -
PWM LATCH
BLANKING
PWM LATCH
BLANKING
VREF2
GATE
DRIVE
V
CP
+ -
+ -
Sense1
Sense2
PWM LATCH
BLANKING
PWM LATCH
BLANKING
BRIDGES 1 AND 2
CONTROL LOGIC
3
GATE
DRIVE
GND
PGND
CP1
VBB1
PHASE2
CP2
3
VREF1
VREF4
Sense3
Sense4
3
3
VREF3
I02
I12
PHASE3
I03
I13
PHASE4
I04
I14
VBB2
0.1 µF
50 V
100 µF
50 V
0.22 µF
50 V
0.1 µF
50 V
BRIDGES 3 AND 4
CONTROL LOGIC
FAULTn*
OCP
*JP
package
only
V
REG
V
REG
Quad DMOS Full-Bridge PWM Motor Driver
A5988
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1: Valid at TA = 25°C, VBB = 40 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.2Max. Units
Load Supply Voltage Range VBB Operating 8 – 40 V
Output On Resistance RDS(on)
Source driver, IOUT = –1.2 A, TJ = 25°C – 500 600 mΩ
Sink driver, IOUT = 1.2 A, TJ = 25°C – 500 600 mΩ
Vf , Outputs IOUT = 1.2 A – – 1.2 V
Output Leakage IDSS Outputs, VOUT = 0 to VBB –20 – 20 µA
VBB Supply Current IBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50% – – 23 mA
Outputs off – 13.7 16 mA
Sleep mode –10 <1 10 µA
Output Driver Slew Rate SROUT 10% to 90% 50 100 150 ns
CONTROL LOGIC
Logic Input Voltage VIN(1) 2 – – V
VIN(0) – – 0.8 V
Logic Input Current IIN VIN = 0 to 5 V –20 <1 20 µA
Logic Input Hysteresis Vhys 150 300 500 mV
Sleep Rising Threshold 2.5 2.7 2.95 V
Sleep Falling Threshold – 2.4 – V
Sleep Hysteresis 250 325 450 mV
Sleep Input Current – 100 150 µA
Crossover Delay tCOD 250 425 1000 ns
Blank Time tBLANK 0.7 1 1.3 µs
VREFx Pin Input Voltage Range VREFxOperating 0.0 – 1.5 V
VREFx Pin Reference Input Current IREF VREF = 1.5 – – ±1 μA
Current Trip-Level Error3VERR
VREF = 1.5, phase current = 100% –5 – 5 %
VREF = 1.5, phase current = 67% –5 – 5 %
VREF = 1.5, phase current = 33% –15 – 15 %
PROTECTION CIRCUITS
VBB UVLO Threshold VUV(VBB) VBB rising 7.3 7.6 7.9 V
VBB Hysteresis VUV(VBB)hys 400 500 600 mV
Overcurrent Protection Threshold 1.6 – – A
Fault Output Voltage IOUT = 1 mA – – 0.5 V
Fault Output Leakage Current No fault, VOUT = 5 V – – 1 µA
Thermal Shutdown Temperature TJTSD 155 165 175 °C
Thermal Shutdown Hysteresis TJTSDhys – 15 – °C
1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3 VERR = [(VREF/3) – VSENSE] / (VREF/3).
Quad DMOS Full-Bridge PWM Motor Driver
A5988
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Operation. The A5988 is designed to operate two
stepper motors, four DC motors, or one stepper and two DC
motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse-width-
modulated (PWM) control circuitry. Each full-bridge peak cur-
rent is set by the value of an external current sense resistor, RSx ,
and a reference voltage, VREFx .
Internal PWM Current Control. Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP . Initially, a diagonal pair
of source and sink DMOS outputs are enabled, and current flows
through the motor winding and RSx. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
RS and voltage at the VREF input with a transconductance func-
tion, approximated by:
ITripMax = VREF / (3 × RS
)
Each current step is a percentage of the maximum current,
ITripMax. The actual current at each step ITrip is approximated by:
ITrip = (% ITripMax / 100) × ITripMax
where % ITripMax is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of
±500 mV on each SENSEx pin is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the time the drivers remain
off. For the A5988 variant, the off-time (toff) is 30 µs. For the
A5988-1 variant, toff is 8.1 µs.
Blanking. This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, tBLANK , is
approximately 1 μs.
Control Logic. Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent VREF input, so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than VBB to drive the source-side
DMOS gates. A 0.1 μF ceramic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic
capacitor is required between VCP and VBBx to act as a reservoir
to operate the high-side DMOS devices.
Shutdown. In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
FUNCTIONAL DESCRIPTION
Quad DMOS Full-Bridge PWM Motor Driver
A5988
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Synchronous Rectification
When a PWM-off cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The A5988 synchronous recti-
fication feature will turn on the appropriate MOSFETs during the
current decay, and effectively short out the body diodes with the
low RDS(on) driver. This significantly lowers power dissipation.
When a zero current level is detected, synchronous rectification is
turned off to prevent reversal of the load current.
Mixed Decay Operation
The bridges operate in mixed decay mode. Referring to Figure
2, as the trip point is reached, the device goes into fast decay
mode for 30.1% of the fixed off-time period. After this fast decay
portion, tFD
, the device switches to slow decay mode for the
remainder of the off-time. During transitions from fast decay to
slow decay, the drivers are forced off for approximately 600 ns.
This feature is added to prevent shoot-through in the bridge. As
shown in Figure 2, during this “dead time” portion, synchronous
rectification is not active, and the device operates in fast decay
and slow decay only.
Figure 2: Mixed Decay Mode Operation
Sleep Mode
To minimize power consumption when not in use, the A5988 can
be put into Sleep Mode by bringing the SLEEPn pin low. Sleep
Mode disables much of the internal circuitry, including the charge
pump.
Overcurrent Protection
An overcurrent monitor protects the A5988 from damage due to
output shorts. If a short is detected, the A5988 latches the fault
and disables the outputs. The latched fault can only be cleared
by cycling the power to VBB or by putting the device in Sleep
Mode. During OCP events, Absolute Maximum Ratings may be
exceeded for a short period of time before outputs are latched off.
Fault Output (FAULTn pin, available on JP pack-
age only)
The open-drain fault output is pulled low when an overcurrent
protection event occurs and the outputs are latched off.
I
OUT
FDDT SDDT
2.4 µs 5.7 µs
Fixed Off-Time 8.1 µs
ITrip
FD
SR
SD
SR
SDDT
V
PHASE
I
OUT
I
OUT
+
–
0
See Enlargement A
Enlargement A
A5988 A5988-1
FDDT SDDT
9µs 21 µs
Fixed Off-Time 30 µs
ITrip
FD
SR
SD
SR
SDDT
Quad DMOS Full-Bridge PWM Motor Driver
A5988
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
0
100.0
66.7
–100.0
–66.7
(%)
Phase 1
0
100.0
66.7
–100.0
–66.7
(%)
Phase 2
Half step 2 phase
Modified half step 2 phase
Figure 3: Step Sequencing for Full-Step Increments
0
100.0
66.7
–100.0
–66.7
(%)
Phase 1
0
100.0
66.7
–100.0
–66.7
(%)
Phase 2
Full step 2 phase
Modified full step 2 phase
STEP SEQUENCING DIAGRAMS
Figure 4: Step Sequencing for Half-Step Increments
Quad DMOS Full-Bridge PWM Motor Driver
A5988
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
0
100.0
66.7
33.3
–33.3
–100.0
–66.7
0
100.0
66.7
33.3
–33.3
–100.0
–66.7
(%)
Phase 1
(%)
Phase 2
Figure 5: Step Sequence for Quarter-Step Increments
Table 1: Step Sequencing Settings
Full 1/2 1/4 Phase 1
(%ITripMax)I0x I1x PHASE Phase 2
(%ITripMax)I0x I1x PHASE
1 1 0 H H X 100 L L 0
2 33 L H 1 100 L L 0
1 2 3 100/66*L/H*L 1 100/66*L/H*L 0
4 100 L L 1 33 L H 0
3 5 100 L L 1 0 H H X
6 100 L L 1 33 L H 1
2 4 7 100/66*L/H*L 1 100/66*L/H*L 1
8 33 L H 1 100 L L 1
5 9 0 H H X 100 L L 1
10 33 L H 0 100 L L 1
3 6 11 100/66*L/H*L 0 100/66*L/H*L 1
12 100 L L 0 33 L H 1
7 13 100 L L 0 0 H H X
14 100 L L 0 33 L H 0
4 8 15 100/66*L/H*L 0 100/66*L/H*L 0
16 33 L H 0 100 L L 0
*Denotes modified step mode
Quad DMOS Full-Bridge PWM Motor Driver
A5988
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
U1
CIN1
OUT1A
GND
GND
GND
CIN3
CCP
OUT1B
VBB
OUT2B
OUT2A
OUT3A
OUT3B
OUT4B
OUT4A
RS3
RS1
RS4
RS2
CVCP
CIN2
Motor Configurations. For applications that require either a
stepper/DC motor driver or dual DC motor driver, Allegro offers
the A5989 and A5995. These devices are offered in the same
36-terminal QFN package as the A5988. The DC motor drivers
are capable of supplying 3.2 A at 40 V. Commutation is done
with a standard phase/enable logic interface. Please refer to the
Allegro website for further information and datasheets about
those devices.
DC Motor Control. Each of the 4 full bridges has independent
PWM current control circuitry that makes the A5988 capable of
driving up to four DC motors at currents up to 1.2 A. Control
of the DC motors is accomplished by tying the I0x and I1x pins
together, creating an equivalent ENABLE function with maxi-
mum current defined by the voltage on the corresponding VREF
pin. The DC motors can be driven via a PWM signal on this
enable signal, or on the corresponding PHASE pin. Motor control
includes forward, reverse, and coast.
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A5988 must be soldered directly onto the board. On the under-
side of the A5988 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
Grounding. In order to minimize the effects of ground bounce
and offset issues, it is important to have a low-impedance single-
point ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A5988, that area
becomes an ideal location for a star ground point.
A low-impedance ground will prevent ground bounce during
high-current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below illustrates how to create a star ground under
the device to serve both as low-impedance ground point and
thermal path.
Figure 6: Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A5988 (U1) is
soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the
ground plane on the other side of the PCB, so the two copper areas together form the star ground.
I13
OUT3A
SENSE3
OUT3B
VBB2
OUT4B
SENSE4
OUT4A
I14
I04
OUT1A
SENSE1
OUT1B
VBB1
OUT2B
SENSE2
OUT2A
PHASE4
PHASE3
SLEEPn
VREF1
VREF2
VREF3
VREF4
GND
PHASE2
PHASE1
I03
I02
I01
CP2
CP1
VCP
PGND
I11
I12
V
BB
CCP
CVCP CIN3
RS1
RS2
PAD
1
A5988
CIN2
CIN1
RS3
RS4
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Solder
A5988
PCB
EV package layout shown
APPLICATIONS INFORMATION
Quad DMOS Full-Bridge PWM Motor Driver
A5988
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The two input capacitors should be placed in parallel and as
close to the device supply pins as possible. The ceramic capaci-
tor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high-frequency current components.
Sense Pins. The sense resistors, RSx, should have a very low
impedance path to ground, because they must carry a large cur-
rent while supporting very accurate voltage measurements by
the current sense comparators. Long ground traces will cause
additional voltage drops, adversely affecting the ability of the
comparators to accurately measure the current in the windings.
As shown in the layout in Figure 6, the SENSEx pins have very
short traces to the RSx resistors and very thick, low-impedance
traces directly to the star ground beneath the device. If possible,
there should be no other components on the sense circuits.
Note: When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
Quad DMOS Full-Bridge PWM Motor Driver
A5988
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Package EV
I12
I11
PGN
D
VCP
CP1
CP2
I01
I02
I03
PHASE1
PHASE2
GND
VREF4
VREF3
VREF2
VREF1
SLEEPn
PHASE3
I04
OUT1A
SENSE1
OUT1B
VBB1
OUT2B
SENSE2
OUT2A
PHASE4
I13
OUT3A
SENSE3
OUT3B
VBB2
OUT4B
SENSE4
OUT4A
I14
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
PAD
I13 37
I12 38
I11 39
PGND 40
NC 41
VCP 42
CP1 43
CP2 44
I01 45
I02 46
I03 47
I04 48
I14
24
FAULTn
23
PHASE1
22
PHASE2
21
GND
20
VREF4
19
VREF3
18
VREF2
17
VREF1
16
SLEEPn
15
PHASE3
14
PHASE4
13
NC
36
NC
35
OUT3A
34
SENSE3
33
OUT3B
32
VBB2
31
NC
30
OUT4B
29
SENSE4
28
OUT4A
27
NC
26
NC
25
NC 1
NC 2
OUT1A 3
SENSE1 4
OUT1B 5
VBB1 6
NC 7
OUT2B 8
SENSE2 9
OUT2A 10
NC 11
NC 12
PAD
Package JP
Number Pin Name Pin Description
EV JP
2 3 OUT1A DMOS Full-Bridge 1 Output A
3 4 SENSE1 Sense Resistor Terminal for Bridge 1
4 5 OUT1B DMOS Full-Bridge 1 Output B
5 6 VBB1 Load Supply Voltage
6 8 OUT2B DMOS Full-Bridge 2 Output B
7 9 SENSE2 Sense Resistor Terminal for Bridge 2
8 10 OUT2A DMOS Full-Bridge 2 Output A
9 13 PHASE4 Control Input
10 14 PHASE3 Control Input
11 15 SLEEPn Active Low Sleep Mode Input
12 16 VREF1 Analog Input
13 17 VREF2 Analog Input
14 18 VREF3 Analog Input
15 19 VREF4 Analog Input
16 20 GND* Analog and Digital Ground
17 21 PHASE2 Control Input
18 22 PHASE1 Control Input
– 23 FAULTn Open Drain Fault Output (JP package only)
19 24 I14 Control Input
20 27 OUT4A DMOS Full-Bridge 4 Output A
21 28 SENSE4 Sense Resistor Terminal for Bridge 4
22 29 OUT4B DMOS Full-Bridge 4 Output B
23 31 VBB2 Load Supply Voltage
24 32 OUT3B DMOS Full-Bridge 3 Output B
25 33 SENSE3 Sense Resistor Terminal for Bridge 3
26 34 OUT3A DMOS Full-Bridge 3 Output A
27 37 I13 Control Input
28 38 I12 Control Input
29 39 I11 Control Input
30 40 PGND* Power Ground
31 42 VCP Reservoir Capacitor Terminal
32 43 CP1 Charge Pump Capacitor Terminal
33 44 CP2 Charge Pump Capacitor Terminal
34 45 I01 Control Input
35 46 I02 Control Input
36 47 I03 Control Input
1 48 I04 Control Input
–
1, 2, 7, 11,
12, 25, 26,
30, 35, 36,
41
NC No Connect
– – PAD Exposed pad for enhanced thermal perfor-
mance. Should be soldered to the PCB.
* GND, PGND, and thermal pad must be connected together externally under the device.
Packages are not to scale
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
Quad DMOS Full-Bridge PWM Motor Driver
A5988
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
EV PACKAGE, 36-PIN QFN WITH EXPOSED THERMAL PAD
0.25 +0.05
–0.07 0.50
0.90 ±0.10
0.55 ±0.20
C
SEATING
PLANE
6.00 ±0.15
6.00 ±0.15
0.30
1.15 0.50
5.80
5.80
4.15
4.15
4.15
4.15
C0.08
37X
DCoplanarity includes exposed thermal pad and terminals
D
36
36
2
1
2
1
36
2
1
A
ATerminal #1 mark area
B
B
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
CReference land pattern layout (reference IPC7351
QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can
improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VJJD-3, except pin count)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
Quad DMOS Full-Bridge PWM Motor Driver
A5988
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
JP PACKAGE, 48-PIN LQFP WITH EXPOSED THERMAL PAD
21
48
A
Exposed thermal pad (bottom surface)
Terminal #1 mark area
B
B
A
7º
0º
C
SEATING
PLANE
C0.08
48X
GAGE PLANE
SEATING PLANE
5.00±0.04
5.00±0.04
1.60 MAX
0.50
5.00 8.60
0.30
1.70
8.60
5.00
For Reference Only
(reference JEDEC MS-026 BBCHD)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.40 ±0.05
0.10 ±0.05
0.22 ±0.05
9.00 ±0.20
9.00 ±0.20 7.00 ±0.20
7.00 ±0.20
0.50
PCB Layout Reference View
C
0.25
(1.00)
0.60 ±0.15
4° ±4
0.15 +0.05
–0.06
C
Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
48
2
1
C
Quad DMOS Full-Bridge PWM Motor Driver
A5988
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– March 21, 2016 Initial release
1 July 29, 2016 Updated Selection Guide table
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
