USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface PRODUCT FEATURES Data Brief USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0 Interface compliant with the ULPI Specification revision 1.1 in 8-bit mode Industry standard UTMI+ Low Pin Interface (ULPI) Converts 54 UTMI+ signals into a standard 12 pin Link controller interface 54.7mA Unconfigured Current (typical) - ideal for bus powered applications 83uA suspend current (typical) - ideal for battery powered applications Latch-Up performance exceeds 150 mA per EIA/JESD 78, Class II ESD protection levels of 8kV HBM without external protection devices Integrated protection to withstand IEC61000-4-2 ESD tests (8kV contact and 15kV air) per 3rd party test facility Supports FS pre-amble for FS hubs with a LS device attached (UTMI+ Level 3) Supports HS SOF and LS keep-alive pulse Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 1.0a specification Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Allows host to turn VBUS off to conserve battery power in OTG applications Supports OTG monitoring of VBUS levels with internal comparators. Includes support for an external VBUS or fault monitor. SMSC USB3300 Low Latency Hi-Speed Receiver (43 Hi-Speed clocks Max) allows use of legacy UTMI Links with a ULPI wrapper Integrated Pull-up resistor on STP for interface protection allows a reliable Link/PHY start-up with slow Links (software configured for low power) Internal 1.8 volt regulators allow operation from a single 3.3 volt supply Internal short circuit protection of ID, DP and DM lines to VBUS or ground Integrated 24MHz Crystal Oscillator supports either crystal operation or 24MHz external clock input Internal PLL for 480MHz Hi-Speed USB operation Industrial Operating Temperature -40C to +85C 32 pin, QFN Lead-Free RoHS Compliant package (5 x 5 x 0.90 mm height) Applications The USB3300 is the ideal companion to any ASIC, SoC or FPGA solution designed with a ULPI Hi-Speed USB host, peripheral or OTG core. The USB3300 is well suited for: Cell Phones PDAs MP3 Players Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players Printers PRODUCT PREVIEW Revision 1.1 (01-24-13) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface ORDER NUMBERS: USB3300-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package USB3300-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel) Reel Size is 4000 pieces. Copyright (c) 2013 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.1 (01-24-13) 2 PRODUCT PREVIEW SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface General Description The USB3300 is an industrial temperature Hi-Speed USB Physical Layer Transceiver (PHY). The USB3300 uses a low pin count interface (ULPI) to connect to a ULPI compliant Link layer. The ULPI interface reduces the UTMI+ interface from 54 pins to 12 pins using a method of in-band signaling and status byte transfers between the Link and PHY. This PHY was designed from the start with the ULPI interface. No UTMI to ULPI wrappers are used in this design which provides a seamless ULPI to Link interface. The result is a PHY with a low latency transmit and receive time. SMSC's low latency high speed and full speed receiver provide the option of re-using existing UTMI Links with a simple wrapper to convert UTMI to ULPI. The ULPI interface allows the USB3300 PHY to operate as a device, host, or an On-The-Go (OTG) device. Designs using the USB3300 PHY as a device, can add host and OTG capability at a later date with no additional pins. The ULPI interface, combined with SMSC's proprietary technology, makes the USB3300 the ideal method of adding Hi-Speed USB to new designs. The USB3300 features an industry leading small footprint package (5mm by 5mm) with sub 1mm height. In addition the USB3300 integrates all DP and DM termination resistances and requires a minimal number of external components. USB3300 CLK STP ULPI LINK DIR NXT VBUS ULPI Digital Logic Hi-Speed Analog w/ OTG DATA[7:0] ID DM DP USB Connector (Standard or Mini) 32 Pin QFN Figure 1 Basic ULPI USB Device Block Diagram The ULPI interface consists of 12 interface pins; 8 bi-directional data pins, 3 control pins, and a 60 MHz clock. By using the 12 pin ULPI interface the USB3300 is able to provide support for the full range of UTMI+ Level 3 through Level 0, as shown in Figure 2, "ULPI Interface Features as Related to UTMI+". This allows USB3300 to work as a HS and FS peripheral and as a HS, FS, and LS Host. The USB3300 can also, as an option, fully support the On-the-Go (OTG) protocol defined in the OnThe-Go Supplement to the USB 2.0 Specification. On-the-Go allows the USB3300 to function like a host, or peripheral configured dynamically by software. For example, a cell phone may connect to a computer as a peripheral to exchange address information or connect to a printer as a host to print pictures. Finally the OTG enabled device can connect to another OTG enabled device to exchange information. All this is supported using a single low profile Mini-AB USB connector. Designs not needing OTG can ignore the OTG feature set. In addition to the advantages of the leading edge ULPI interface, the use of SMSC's advanced analog technology enables the USB3300 to consume a minimum amount of power which results in maximized battery life for portable applications. SMSC USB3300 3 PRODUCT PREVIEW Revision 1.1 (01-24-13) ADDED FEATURES Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface ULPI Hi-Speed Peripheral, host controllers, On-theGo devices with 12 pin interface (HS, FS, LS, preamble packet) USB3300 UTMI+ Level 3 Hi-Speed Peripheral, host controllers, Onthe-Go devices (HS, FS, LS, preamble packet) USB3500 USB3450 UTMI+ Level 2 Hi-Speed Peripheral, host controllers, Onthe-Go devices (HS, FS, and LS but no preamble packet) UTMI+ Level 1 Hi-Speed Peripheral, host controllers, and On-the-Go devices (HS and FS Only) UTMI+ Level 0 Hi-Speed Peripherals Only USB3280 USB3250 Figure 2 ULPI Interface Features as Related to UTMI+ Revision 1.1 (01-24-13) 4 PRODUCT PREVIEW SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Block Diagram VDD3.3 Internal Regulator & POR m 24 MHz XTAL EXTVBUS XO XI VDDA1.8 VDD1.8 The USB3300 is a highly integrated USB PHY. It contains a complete Hi-Speed USB 2.0 PHY with the ULPI industry standard interface to support fast time to market for a USB product. The USB3300 is composed of the functional blocks shown in Figure 3, "USB3300 Block Diagram" below. XTAL & PLL FAULT CPEN OTG Module EN VBUS ID Rpu_dp Rpu_dm Rpd_dp Rpd_dm VDD3.3 DATA[7:0] HS XCVR CLKOUT STP ULPI Digital 5V Power Supply DP DM Mini-AB USB Connector Resistors DIR NXT Bias Gen. FS/LS XCVR RBIAS USB3300 Figure 3 USB3300 Block Diagram SMSC USB3300 5 PRODUCT PREVIEW Revision 1.1 (01-24-13) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Pin Configuration and Pin Definitions The USB3300 is offered in a 32 pin QFN package (5 x 5 x 0.9mm). The pin definitions and locations are documented below. RBIAS REG_EN VDD3.3 VDDA1.8 XI XO VDD1.8 VDD3.3 32 31 30 29 28 27 26 25 USB3300 Pin Locations GND 1 24 DATA0 GND 2 23 DATA1 CPEN 3 22 DATA2 VBUS 4 21 DATA3 ID 5 20 DATA4 VDD3.3 6 19 DATA5 DP 7 18 DATA6 17 DATA7 USB3300 Hi-Speed Hi-SpeedUSB2 USB ULPI PHY 32 Pin QFN GND FLAG 15 16 VDD3.3 13 STP VDD1.8 12 DIR 14 11 NXT CLKOUT 10 RESET EXTVBUS 8 9 DM Figure 4 USB3300 Pinout - Top View The exposed flag of the QFN package must be connected to ground with a via array to the ground plane. This is the main ground connection for the USB3300. Pin Definitions, 32-Pin QFN Package Table 1 USB3300 Pin Definitions PIN NAME DIRECTION, TYPE ACTIVE LEVEL 1 GND Ground N/A Ground 2 GND Ground N/A Ground 3 CPEN Output, CMOS High External 5 volt supply enable. This pin is used to enable the external Vbus power supply. The CPEN pin is low on POR. 4 VBUS I/O, Analog N/A VBUS pin of the USB cable. The USB3300 uses this pin for the Vbus comparator inputs and for Vbus pulsing during session request protocol. Revision 1.1 (01-24-13) 6 DESCRIPTION PRODUCT PREVIEW SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Table 1 USB3300 Pin Definitions (continued) DIRECTION, TYPE ACTIVE LEVEL ID Input, Analog N/A ID pin of the USB cable. For non-OTG applications this pin can be floated. For an A-Device ID = 0. For a B-Device ID = 1. 6 VDD3.3 Power N/A 3.3V Supply. A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB. 7 DP I/O, Analog N/A D+ pin of the USB cable. 8 DM I/O, Analog N/A D- pin of the USB cable. 9 RESET Input, CMOS High Optional active high transceiver reset. This is the same as a write to the ULPI Reset, address 04h, bit 5. This does not reset the ULPI register set. This pin includes an integrated pull-down resistor to ground. If not used, this pin can be floated or connected to ground (recommended). 10 EXTVBUS Input, CMOS High External Vbus Detect. Connect to fault output of an external USB power switch or an external Vbus Valid comparator. This pin has a pull down resistor to prevent it from floating when the ULPI bit UseExternalVbusIndicator is set to 0. 11 NXT Output, CMOS High The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. 12 DIR Output, CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL startup. 13 STP Input, CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. 14 CLKOUT Output, CMOS N/A 60MHz reference clock output. All ULPI signals are driven synchronous to the rising edge of this clock. 15 VDD1.8 Power N/A 1.8V for digital circuitry on chip. Supplied by On-Chip Regulator when REG_EN is active. Place a 0.1uF capacitor near this pin and connect the capacitor from this pin to ground. Connect pin 15 to pin 26. 16 VDD3.3 Power N/A A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB. PIN NAME 5 SMSC USB3300 7 DESCRIPTION PRODUCT PREVIEW Revision 1.1 (01-24-13) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Table 1 USB3300 Pin Definitions (continued) DIRECTION, TYPE ACTIVE LEVEL DATA[7] I/O, CMOS, Pull-low N/A 18 DATA[6] I/O, CMOS, Pull-low N/A 19 DATA[5] I/O, CMOS, Pull-low N/A 20 DATA[4] I/O, CMOS, Pull-low N/A 21 DATA[3] I/O, CMOS, Pull-low N/A 22 DATA[2] I/O, CMOS, Pull-low N/A 23 DATA[1] I/O, CMOS, Pull-low N/A 24 DATA[0] I/O, CMOS, Pull-low N/A 25 VDD3.3 Power N/A A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB. 26 VDD1.8 Power N/A 1.8V for digital circuitry on chip. Supplied by On-Chip Regulator when REG_EN is active. When using the internal regulators, place a 4.7uF low-ESR capacitor near this pin and connect the capacitor from this pin to ground. Connect pin 26 to pin 15. Do not connect VDD1.8 to VDDA1.8 when using internal regulators. When the regulators are disabled, pin 29 may be connected to pins 26 and 15. 27 XO Output, Analog N/A Crystal pin. If using an external clock on XI this pin should be floated. 28 XI Input, Analog N/A Crystal pin. A 24MHz crystal is supported. The crystal is placed across XI and XO. An external 24MHz clock source may be driven into XI in place of a crystal. 29 VDDA1.8 Power N/A 1.8V for analog circuitry on chip. Supplied by OnChip Regulator when REG_EN is active. Place a 0.1uF capacitor near this pin and connect the capacitor from this pin to ground. When using the internal regulators, place a 4.7uF low-ESR capacitor near this pin in parallel with the 0.1uF capacitor. Do not connect VDD1.8A to VDD1.8 when using internal regulators. When the regulators are disabled, pin 29 may be connected to pins 26 and 15. 30 VDD3.3 Power N/A Analog 3.3 volt supply. A 0.1uF low ESR bypass capacitor connected to the ground plane of the PCB is recommended. PIN NAME 17 Revision 1.1 (01-24-13) DESCRIPTION 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of CLKOUT. DATA[7] is the MSB and DATA[0] is the LSB. 8 PRODUCT PREVIEW SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Table 1 USB3300 Pin Definitions (continued) DIRECTION, TYPE ACTIVE LEVEL REG_EN I/O, CMOS, Pull-low N/A On-Chip 1.8V regulator enable. Connect to ground to disable both of the on chip (VDDA1.8 and VDD1.8) regulators. When regulators are disabled: External 1.8V must be supplied to VDDA1.8 and VDD1.8 pins. When the regulators are disabled, VDDA1.8 may be connected to VDD1.8 and a bypass capacitor (0.1uF recommended) should be connected to each pin. The voltage at VDD3.3 must be at least 2.64V (0.8 * 3.3V) before voltage is applied to VDDA1.8 and VDD1.8. RBIAS Analog, CMOS N/A External 12K +/- 1% bias resistor to ground. GND FLAG Ground N/A Ground. The flag must be connected to the ground plane with a via array under the exposed flag. This is the main ground for the IC. PIN NAME 31 32 SMSC USB3300 9 DESCRIPTION PRODUCT PREVIEW Revision 1.1 (01-24-13) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Application Notes Application Diagrams Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS. RVBUS may be installed in this configuration to assist in protecting the VBUS pin. 820 Ohms will protect against VBUS transients up to 8.5V. 10K Ohms will protect against transients up to 10V. RVBUS The capacitor CVBUS must be installed on this side of RVBUS. 3.3V Supply CBYP USB Receptacle Link Controller USB3300 CVBUS 17 18 19 20 21 22 23 24 13 11 12 14 9 31 REG_EN 30 VDD3.3 6 VDD3.3 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESET 16 VDD3.3 XO 27 25 VDD3.3 XI 28 4 VBUS VBUS 1 DM 2 8 DM VDD1.8 15 DP 3 7 DP VDD1.8 26 NC 5 ID VDDA1.8 29 NC 3 CPEN RBIAS 32 NC 10 CLOAD SHIELD GND DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT CDC_BLOCK CLOAD 12.0k 1% EXTVBUS GND FLAG 1 1M 2 COUT COUT Figure 5 USB3300 Application Diagram (Peripheral) Revision 1.1 (01-24-13) 10 PRODUCT PREVIEW SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS. USB3300 Link Controller 3 CPEN VBUS Switch 5V 10 EN FLG IN OUT 4 RVBUS may be installed to assist in protecting the VBUS pin. 820 Ohms will protect against VBUS transients up to 8.5V. RVBUS 3.3V The capacitor CVBUS must be installed on this side of RVBUS. USB Receptacle EXTVBUS VBUS CBYP CVBUS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESET 17 18 19 20 21 22 23 24 13 11 12 14 9 31 REG_EN 30 VDD3.3 6 VDD3.3 16 VDD3.3 XO 27 25 VDD3.3 XI 28 VBUS 1 DM 2 8 DM VDD1.8 15 DP 3 7 DP VDD1.8 26 ID 4 5 ID VDDA1.8 29 RBIAS 32 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT CLOAD SHIELD 1M CLOAD 12.0k 1% GND GND FLAG 1 2 COUT COUT Figure 6 USB3300 Application Diagram (Host or OTG) SMSC USB3300 11 PRODUCT PREVIEW Revision 1.1 (01-24-13) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS. Optional Over-voltage Protection The capacitor CVBUS must be installed on this side of RVBUS. 3.3V Supply CBYP USB Receptacle Link Controller USB3300 Over-voltage device may be desired to protect against out-of-spec chargers. CVBUS 4 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESET VBUS 17 18 19 20 21 22 23 24 13 11 12 14 9 31 REG_EN 30 VDD3.3 6 VDD3.3 16 VDD3.3 XO 27 25 VDD3.3 XI 28 VBUS 1 DM 2 8 DM VDD1.8 15 DP 3 7 DP VDD1.8 26 NC 5 ID VDDA1.8 29 NC 3 CPEN RBIAS 32 NC 10 CLOAD SHIELD GND DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT CDC_BLOCK CLOAD 12.0k 1% EXTVBUS GND FLAG 1 1M 2 COUT COUT Figure 7 USB3300 Application Diagram (Peripheral with Over Voltage Protection) Revision 1.1 (01-24-13) 12 PRODUCT PREVIEW SMSC USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Multi-Port Applications To support multiple ports a single USB3300 host can be combined with one of SMSC's many hub products to expand the number of ports. SMSC has 2-port, 3-port, 4-port, and 7-port hub designs which can be used to expand the number of ports in a design. DIR NXT STP CLOCK DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] DIR NXT STP CLOCK DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] CPEN DP DM VBUS_DET USBDP0 USBDM0 USB Port 1 USBDP1 USBDN1 DP DM USB Port 2 USBDP2 USBDN2 DP DM USB2502 USB Port 3 USBDP3 USBDN3 DP DM USB2503 SOC w/ ULPI Link USB3300 USB Port 4 USBDP4 USBDN4 DP DM USB2504 USB Ports 5-7 USBDP5-7 USBDN5-7 DP DM USB2507 Figure 8 Expanding Downstream Ports for USB3300 Host Applications Using a SMSC hub to expand the number of ports allows a single Link to run several USB devices without a separate Link to support each USB port. Another advantage of using a SMSC hub is on products where the main board is not located near the USB ports. The USB3300 can be placed on the main board with the Link ASIC and the hub can be placed on a separate board next to the USB ports. The only data connection required between the boards is DP and DM. The CPEN output of the USB3300 is optional and can be used to turn the Hub on or off to lower current when the USB connection isn't needed. Evaluation Board An evaluation board, EVB-USB3300, is available for building a prototype system with the USB3300. The evaluation board provides an industry standard T&MT connector to interface a ULPI Link controller and a Mini-AB connector for the USB cable. A 500mA fault protected 5V Vbus switch that is controlled by the USB3300 is also included. Supporting Documentation Universal Serial Bus Specification, Revision 2.0, April 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003 USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 UTMI+ Specification, Revision 1.0, February 2, 2004 UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 SMSC USB3300 13 PRODUCT PREVIEW Revision 1.1 (01-24-13) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Package Outline The USB3300 is offered in a compact 32 lead-free QFN package. Figure 9 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) Table 2 32 Terminal QFN Package Parameters A A1 A2 A3 D D1 D2 E E1 E2 L e b ccc MIN 0.70 0 ~ 4.85 4.55 3.15 4.85 4.55 3.15 0.30 0.18 ~ NOMINAL ~ 0.02 ~ 0.20 REF 5.0 ~ 3.3 5.0 ~ 3.3 ~ 0.50 BSC 0.25 ~ MAX 1.00 0.05 0.90 5.15 4.95 3.45 5.15 4.95 3.45 0.50 0.30 0.08 REMARKS Overall Package Height Standoff Mold Thickness Copper Lead-frame Substrate X Overall Size X Mold Cap Size X exposed Pad Size Y Overall Size Y Mold Cap Size Y exposed Pad Size Terminal Length Terminal Pitch Terminal Width Coplanarity Notes: 1. Controlling Unit: millimeter. 2. Dimension b applies to plated terminals and is measured between 0.15mm and 0.30mm from the terminal tip. Tolerance on the true position of the leads is 0.05 mm at maximum material conditions (MMC). 3. Details of terminal #1 identifier are optional but must be located within the zone indicated. 4. Coplanarity zone applies to exposed pad and terminals. Revision 1.1 (01-24-13) 14 PRODUCT PREVIEW SMSC USB3300