CDCLVD1212
LVDSBuffer
IN_SEL
PHY2
PHY2
PHY2
PHY2
125 MHz
125 MHz
Oscillator 2
PHY2
PHY2
PHY2
PHY 12
CDCLVD1212
www.ti.com
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
2:12 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD1212
1FEATURES DESCRIPTION
• 2:12 Differential Buffer
• Low Additive Jitter: <300 fs RMS in The CDCLVD1212 clock buffer distributes one of two
selectable clock inputs (IN0, IN1) to 12 pairs of
10 kHz to 20 MHz differential LVDS clock outputs (OUT0, OUT11) with
• Low Output Skew of 50 ps (Max) minimum skew for clock distribution. The
• Universal Inputs Accept LVDS, LVPECL, CDCLVD1212 can accept two clock sources into an
LVCMOS input multiplexer. The inputs can either be LVDS,
LVPECL, or LVCMOS.
• Selectable Clock Inputs Through Control Pin
• 12 LVDS Outputs, ANSI EIA/TIA-644A Standard The CDCLVD1212 is specifically designed for driving
Compatible 50 Ωtransmission lines. If driving the inputs in single
ended mode, the appropriate bias voltage (VAC_REF)
• Clock Frequency up to 800 MHz should be applied to the unused negative input pin.
• 2.375–2.625 V Device Power Supply The IN_SEL pin selects the input which is routed to
• LVDS Reference Voltage, VAC_REF, Available for the outputs. If this pin is left open it disables the
Capacitive Coupled Inputs outputs (static). The part supports a fail safe function.
• Industrial Temperature Range –40°C to 85°C It incorporates an input hysteresis, which prevents
random oscillation of the outputs in absence of an
• Packaged in 6mm × 6mm 40-Pin QFN (RHA) input signal.
• ESD Protection Exceeds 3 kV HBM, 1 kV CDM The device operates in 2.5 V supply environment and
APPLICATIONS is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD1212 is packaged in
• Telecommunications/Networking small 40-pin, 6mm × 6mm QFN package.
• Medical Imaging
• Test and Measurement Equipment
• Wireless Communications
• General Purpose Clocking
Figure 1. Application Example
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Reference
Generator
LVDS
INN0
INP0
INN1
INP1
IN_SEL
GND
OUTN [0..11]
OUTP [0..11]
GND
VAC_REF0
VAC_REF1
200 kW
200 kW
VCC
VCC
VCC VCC VCC VCC VCC
IN_MUX
6mmx 6mm
40 pinQFN (RHA)
ThermalPad (GND)
2 3 4 5 6 71
24 23 22 2127 26 25
VCC
GND
OUTP4
OUTN4
OUTP5
OUTP8
OUTN9
OUTP9
OUTN8
INN1
INP1
IN_SEL
N.C.
VAC_REF0
OUTN0
OUTP0
OUTN5
OUTP6
OUTN6
VCC
OUTN10
OUTP10
8 9 10
VAC_REF1
VCC
VCC
INN0
INP0
OUTN1
OUTP1
OUTN2
OUTP2
OUTN3
OUTP3
VCC
30 29 28
GND
OUTP7
OUTN7
VCC
OUTN11
OUTP11
11
12
13
14
15
16
17
37
36
35
34
33
32
31
18
19
20
40
39
38
CDCLVD1212
(TOP VIEW)
CDCLVD1212
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Figure 2. CDCLVD1212 Block Diagram
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SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
PIN FUNCTIONS
PIN
NAME NO. TYPE DESCRIPTION
5, 6, 11,
VCC Power 2.5V supplies for the device
20, 31, 40
GND 21, 30 Ground Device ground
INP0, INN0 9, 8 Input Differential input pair or single ended input
INP1, INN1 2, 3 Input Differential redundant input pair or single ended input
OUTP0, OUTN0 12, 13 Output Differential LVDS output pair no. 0
OUTP1, OUTN1 14, 15 Output Differential LVDS output pair no. 1
OUTP2, OUTN2 16, 17 Output Differential LVDS output pair no. 2
OUTP3, OUTN3 18, 19 Output Differential LVDS output pair no. 3
OUTP4, OUTN4 22, 23 Output Differential LVDS output pair no. 4
OUTP5, OUTN5 24, 25 Output Differential LVDS output pair no. 5
OUTP6, OUTN6 26, 27 Output Differential LVDS output pair no. 6
OUTP7, OUTN7 28, 29 Output Differential LVDS output pair no. 7
OUTP8,OUTN8 32, 33 Output Differential LVDS output pair no. 8
OUTP9,OUTN9 34, 35 Output Differential LVDS output pair no. 9
OUTP10,OUTN10 36, 37 Output Differential LVDS output pair no. 10
OUTP11,OUTN11 38, 39 Output Differential LVDS output pair no. 11
Bias voltage output for capacitive coupled inputs. If used, it is recommended to use
VAC_REF0 7 Output a 0.1µF to GND on this pin
Bias voltage output for capacitive coupled inputs. If used, it is recommended to use
VAC_REF1 4 Output a 0.1µF to GND on this pin.
N.C. 10 No connect
Input with an
internal 200kΩ
IN_SEL 1 Input selection – selects input port; (See Table 1)
pull-up and
pull-down Device ground. Thermal pad must be soldered to ground. See thermal management
Thermal Pad Ground recommendations
Table 1. Input Selection Table
IN_SEL ACTIVE CLOCK INPUT
0 INP0, INN0
1 INP1, INN1
Open None(1)
(1) The input buffers are disabled and the outputs are static.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
Supply voltage range, VCC –0.3 to 2.8 V
Input voltage range, VI–0.2 to (VCC + 0.2) V
Output voltage range, VO–0.2 to (VCC + 0.2) V
Driver short circuit current, IOSD See Note (2)
Electrostatic discharge (Human Body Model, 1.5 kΩ, 100 pF) >3000 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The outputs can handle permanent short.
Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
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SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
Device supply voltage, VCC 2.375 2.5 2.625 V
Ambient temperature, TA–40 85 °C
THERMAL INFORMATION CDCLVD1212
THERMAL METRIC(1) UNITS
RHA (40 PINS)
qJA Junction-to-ambient thermal resistance 31.0
qJC(top) Junction-to-case(top) thermal resistance 28.7
qJB Junction-to-board thermal resistance 9.3 °C/W
yJT Junction-to-top characterization parameter 0.4
yJB Junction-to-board characterization parameter 9.3
qJC(bottom) Junction-to-case(bottom) thermal resistance 3.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At VCC = 2.375V to 2.625V, TA= –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IN_SEL CONTROL INPUT CHARACTERISTICS
VdI3 3 State Open 0.5×VCC V
VdIH Input high voltage 0.7×VCC V
VdIL Input low voltage 0.2×VCC V
IdIH Input high current VCC = 2.625 V, VIH = 2.625 V 30 mA
IdIL Input low current VCC = 2.625 V, VIL = 0 V –30 mA
Rpull(IN_SEL) Input pull-up/ pull-down resistor 200 kΩ
2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS
fIN Input frequency 200 MHz
External threshold voltage applied to
Vth Input threshold voltage 1.1 1.5 V
complementary input
VIH Input high voltage Vth + 0.1 VCC V
VIL Input low voltage 0 Vth – 0.1 V
IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 mA
IIL Input low current VCC = 2.625 V, VIL = 0 V –10 mA
ΔV/ΔT Input edge rate 20%–80% 1.5 V/ns
CIN Input capacitance 2.5 pF
DIFFERENTIAL INPUT CHARACTERISTICS
fIN Input frequency Clock input 800 MHz
VIN, DIFF Differential input voltage peak-to-peak VICM = 1.25 V 0.3 1.6 VPP
VICM Input common mode voltage range VIN, DIFF, PP > 0.4 V 1.0 VCC – 0.3 V
IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 mA
IIL Input low current VCC = 2.625, VIL = 0 V –10 mA
ΔV/ΔT Input edge rate 20%–80% 0.75 V/ns
CIN Input capacitance 2.5 pF
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SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 2.375V to 2.625V, TA= –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS OUTPUT CHARACTERISTICS
|VOD| Differential output voltage magnitude 250 450 mV
Change in differential output voltage
ΔVOD –15 15 mV
magnitude VIN, DIFF, PP = 0.3V, RL= 100 Ω
Steady-state common mode output
VOC(SS) 1.1 1.375 V
voltage
Steady-state common mode output
ΔVOC(SS) VIN, DIFF, PP = 0.6V, RL= 100 Ω–15 15 mV
voltage
Vring Output overshoot and undershoot Percentage of output amplitude VOD 10%
VOS Output ac common mode VIN, DIFF, PP = 0.6V, RL= 100 Ω40 70 mVPP
IOS Short-circuit output current VOD = 0 V ±24 mA
tPD Propagation delay VIN, DIFF, PP = 0.3 V 1.5 2.5 ns
tSK, PP Part-to-part skew 600 ps
tSK, O Output skew 50 ps
Crossing-point-to-crossing-point
tSK,P Pulse skew(with 50% duty cycle input) –50 50 ps
distortion
Random additive jitter (with 50% duty Edge speed 0.75 V/ns, ps,
tRJIT 0.3
cycle input) 10 kHz – 20 MHz RMS
tR/tFOutput rise/fall time 20% to 80%, 100 Ω, 5 pF 50 300 ps
ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 17 28 mA
ICC100 Supply current All outputs, RL= 100 Ω, f = 100 MHz 85 110 mA
ICC800 Supply current All outputs, RL= 100 Ω, f = 800 MHz 117 146 mA
VAC_REF CHARACTERISTICS
VAC_REF Reference output voltage VCC = 2.5 V, Iload = 100 µA 1.1 1.25 1.35 V
Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER MIN TYP MAX UNIT
phn100 Phase noise at 100 Hz offset -132.9 dBc/Hz
phn1k Phase noise at 1 kHz offset -138.8 dBc/Hz
phn10k Phase noise at 10 kHz offset -147.4 dBc/Hz
phn100k Phase noise at 100 kHz offset -153.6 dBc/Hz
phn1M Phase noise at 1 MHz offset -155.2 dBc/Hz
phn10M Phase noise at 10 MHz offset -156.2 dBc/Hz
phn20M Phase noise at 20 MHz offset -156.6 dBc/Hz
tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER MIN TYP MAX UNIT
phn100 Phase noise at 100 Hz offset -80.2 dBc/Hz
phn1k Phase noise at 1 kHz offset -114.3 dBc/Hz
phn10k Phase noise at 10 kHz offset -138 dBc/Hz
phn100k Phase noise at 100 kHz offset -143.9 dBc/Hz
phn1M Phase noise at 1 MHz offset -145.2 dBc/Hz
phn10M Phase noise at 10 MHz offset -146.5 dBc/Hz
phn20M Phase noise at 20 MHz offset -146.6 dBc/Hz
tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS
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PhaseNoise-dBc/Hz
CDCLVD1212
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
INPUT- AND OUTPUT-CLOCK PHASE NOISES
vs
FREQUENCY FROM the CARRIER
(TA= 25°C and VCC = 2.5V)
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
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Product Folder Link(s): CDCLVD1212
250
260
270
280
290
300
310
320
330
340
350
0 100 200 300 400 500 600 800
V Differential Output Voltage − mV
OD −
Frequency − MHz
700
T = 25 C
A
o
2.625V
2.5V
2.375V
Oscilloscope
100 W
LVDS
PhaseNoise
Analyzer
50 W
LVDS
CDCLVD1212
www.ti.com
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
Differential Output Voltage
vs
Frequency
Figure 4.
TEST CONFIGURATIONS
Figure 5. LVDS Output DC Configuration During Device Test
Figure 6. LVDS Output AC Configuration During Device Test
Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CDCLVD1212
VIH
VIL
Vth
Vth
IN
IN
OUTNx
OUTPx
80%
20%
0 V
trtf
VOD
VOH
VOL
V (= 2 x V )
OUT,DIFF,PP OD
CDCLVD1212
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 7. DC Coupled LVCMOS Input During Device Test
Figure 8. Output Voltage and Rise/Fall Time
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SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
A. Output skew is calculated as the greater of the following: As of the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..11)
B. Part to part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..11)
Figure 9. Output Skew and Part-to-Part Skew
Figure 10. Output Overshoot and Undershoot
Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): CDCLVD1212
VOS
GND
FerriteBead
1 µF 10µF 0.1 µF(x6)
Board
Supply
Chip
Supply
CDCLVD1212
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 11. Output AC Common Mode
APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Check the mechanical data at the end of
the data sheet for land and via pattern examples.
POWER SUPPLY FILTERING
High-performance clock buffers are sensitive to noises on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is critical to the application.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is
recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply pins
in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and
the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip
supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for
proper operation.
Figure 12. Power Supply Filtering
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Product Folder Link(s): CDCLVD1212
LVDS
Z = 50 W
CDCLVD1212 100 W
Z = 50 W
LVDS
Z = 50 W
CDCLVD1212 100 W
100 nF
Z = 50 W
100 nF
CDCLVD1212
www.ti.com
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ωlines is 100 Ωbetween the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage
different than the output common mode voltage of the CDCLVD1212, ac-coupling should be used. If the LVDS
receiver has internal 100 Ωtermination, external termination must be omitted.
Unused outputs can be left open without connecting any trace to the output pins.
Figure 13. LVDS Output DC Termination
Figure 14. LVDS Output AC Termination with Receiver Internally Biased
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Product Folder Link(s): CDCLVD1212
LVDS
Z = 50 W
CDCLVD1212
100 W
Z = 50 W
LVDS
Z = 50 W
CDCLVD1212
Z = 50 W
VAC_REF
50 W50 W
100 nF
100 nF
CDCLVD1212
SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
www.ti.com
INPUT TERMINATION
The CDCLVD1212 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS Driver can be connected to CDCLVD1212 inputs with dc or ac coupling as shown Figure 15 and Figure 16
respectively.
Figure 15. LVDS Clock Driver Connected to CDCLVD1212 Input (DC coupled)
Figure 16. LVDS Clock Driver Connected to CDCLVD1212 Input (AC coupled)
Figure 17 shows how to connect LVPECL inputs to the CDCLVD1212. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP.
Figure 17. LVPECL Clock Driver Connected to CDCLVD1212 Input
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SCAS901B –SEPTEMBER 2010–REVISED JANUARY 2011
Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD1212 directly. The series
resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs
to be limited to VIH ≤VCC.
Figure 18. 2.5V LVCMOS Clock Driver Connected to CDCLVD1212 Input
For unused inputs, it is recommended to ground both input pins (INP, INN) using 1 kΩresistors.
SPACER REVISION HISTORY
Changes from Original (September 2010) to Revision A Page
• Deleted the Recommended PCB Layout illustration .......................................................................................................... 10
Changes from Revision A (November 2010) to Revision B Page
• Changed the device status From: Product Preview To: Production ..................................................................................... 1
Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): CDCLVD1212
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CDCLVD1212RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CDCLVD1212RHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCLVD1212RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
CDCLVD1212RHAT VQFN RHA 40 250 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCLVD1212RHAR VQFN RHA 40 2500 336.6 336.6 28.6
CDCLVD1212RHAT VQFN RHA 40 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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