REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8132
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
Low-Cost, High-Speed
Differential Amplifier
FUNCTIONAL BLOCK DIAGRAM
AD8132
+
1
2
3
4
NC = NO CONNECT
–IN +IN
V
OCM
NC
V+ V–
+OUT –OUT
8
7
6
5
FEATURES
High Speed
350 MHz –3 dB Bandwidth
1200 V/s Slew rate
Resistor-Settable Gain
Internal Common-Mode Feedback to Improve Gain
and Phase Balance –68 dB @ 10 MHz
Separate Input to Set the Common-Mode Output
Voltage
Low Distortion –99 dBc SFDR @ 5 MHz 800 Load
Low Power 10.7 mA @ 5 V
Power Supply Range +2.7 V to 5.5 V
APPLICATIONS
Low Power Differential ADC Driver
Differential Gain and Differential Filtering
Video Line Driver
Differential In/Out Level-Shifting
Single-Ended Input to Differential Output Driver
Active Transformer
GENERAL DESCRIPTION
The AD8132 is a low-cost differential or single-ended input to
differential output amplifier with resistor-settable gain. The
AD8132 is a major advancement over op amps for driving differ-
ential input ADCs or for driving signals over long lines. The
AD8132 has a unique internal feedback feature that provides
output gain and phase matching balanced to –68 dB at 10 MHz,
suppressing harmonics, and reducing radiated EMI.
Manufactured on ADI’s next generation of XFCB bipolar pro-
cess, the AD8132 has a –3 dB bandwidth of 350 MHz and
delivers a differential signal with –99 dBc SFDR at 5 MHz,
despite its low cost. The AD8132 eliminates the need for a
transformer with high-performance ADCs, preserving the low
frequency and dc information. The common-mode level of the
differential output is adjustable by applying a voltage on the V
OCM
pin, easily level-shifting the input signals for driving single supply
ADCs. Fast overload recovery preserves sampling accuracy.
The AD8132 can also be used as a differential driver for the
transmission of high-speed signals over low-cost twisted pair or
coaxial cables. The feedback network can be adjusted to boost
the high-frequency components of the signal. The AD8132 can
be used for either analog or digital video signals or for other high-
speed data transmission. The AD8132 is capable of driving either
cat3 or cat5 twisted pair or coaxial with minimal line attenu-
ation. The AD8132 has considerable cost and performance
improvements over discrete line driver solutions.
Differential signal processing reduces the effects of ground noise
which plagues ground referenced systems. The AD8132 can be
used for differential signal processing (gain and filtering) through-
out a signal chain, easily simplifying the conversion between
differential and single-ended components.
The AD8132 is available in both SOIC and µSOIC packages for
operation over –40°C to +85°C temperatures.
FREQUENCY – MHz
6
1
GAIN – dB
3
0
–3
–6
–9
–12
10 100 1k
VS = 5V
G = 1
VO,dm = 2V p-p
RL,dm = 499
Figure 1. Large Signal Frequency Response
REV. 0
–2–
AD8132–SPECIFICATIONS
P
arameter Conditions Min Typ Max Unit
D
IN
to OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth V
OUT
= 2 V p-p 300 350 MHz
V
OUT
= 2 V p-p, G = 2 190 MHz
–3 dB Small Signal Bandwidth V
OUT
= 0.2 V p-p 360 MHz
V
OUT
= 0.2 V p-p, G = 2 160 MHz
Bandwidth for 0.1 dB Flatness V
OUT
= 0.2 V p-p 90 MHz
V
OUT
= 0.2 V p-p, G = 2 50 MHz
Slew Rate V
OUT
= 2 V p-p 1000 1200 V/µs
Settling Time 0.1%, V
OUT
= 2 V p-p 15 ns
Overdrive Recovery Time V
IN
= 5 V to 0 V Step, G = 2 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic V
OUT
= 2 V p-p, 1 MHz, R
L,dm
= 800 Ω–96 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–83 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–73 dBc
Third Harmonic V
OUT
= 2 V p-p, 1 MHz, R
L,dm
= 800 Ω–102 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–98 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–67 dBc
IMD 20 MHz, R
L,dm
= 800 Ω–76 dBc
IP3 20 MHz, R
L,dm
= 800 Ω40 dBm
Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz
Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz
Differential Gain Error NTSC, G = 2, R
L,dm
= 150 Ω0.01 %
Differential Phase Error NTSC, G = 2, R
L,dm
= 150 Ω0.10 Degrees
INPUT CHARACTERISTICS
Offset Voltage (RTI) V
OS,dm
= V
OUT,dm
/2; V
DIN+
= V
DIN–
= V
OCM
= 0 V ±1.0 ±3.5 mV
T
MIN
to T
MAX
Variation 10 µV/°C
Input Bias Current 37µA
Input Resistance Differential 12 MΩ
Common-Mode 3.5 MΩ
Input Capacitance 1pF
Input Common-Mode Voltage –7 to +6 V
CMRR ∆V
OUT,dm
/∆V
IN,cm
; ∆V
IN,cm
= ±1 V; –70 –60 dB
Resistors Matched to 0.01%
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆V
OUT
; Single-Ended Output –3.6 to +3.6 V
Output Current 70 mA
Output Balance Error ∆V
OUT,cm
/∆V
OUT,dm
; ∆V
OUT,dm
= 1 V –70 dB
V
OCM
to OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth ∆V
OCM
= 600 mV p-p 210 MHz
Slew Rate ∆V
OCM
= –1 V to +1 V 400 V/µs
DC PERFORMANCE
Input Voltage Range ±3.6 V
Input Resistance 150 kΩ
Input Offset Voltage V
OS,cm
= V
OUT,cm
; V
DIN+
= V
DIN–
= V
OCM
= 0 V ±1.5 ±7mV
Input Bias Current 0.5 µA
V
OCM
CMRR [∆V
OUT,dm
/∆V
OCM
]; ∆V
OCM
= ±1 V; –68 dB
Resistors Matched to 0.01%
Gain ∆V
OUT,cm
/∆V
OCM
;
∆V
OCM
= ±1 V 0.985 1 1.015 V/V
POWER SUPPLY
Operating Range ±1.35 ±5.5 V
Quiescent Current V
DIN+
= V
DIN–
= V
OCM
= 0 V 11 12 13 mA
T
MIN
to T
MAX
Variation 16 µA/°C
Power Supply Rejection Ratio ∆V
OUT,dm
/∆V
S
; ∆V
S
= ±1 V –70 –60 dB
OPERATING TEMPERATURE RANGE –40
+85 °C
Specifications subject to change without notice.
(@ 25C, VS = 5 V, VOCM = 0 V, G = 1, RL,dm = 499 , RF = RG = 348 unless
otherwise noted. For G = 2, RL,dm = 200 , RF = 1000 , RG = 499 . Refer to TPC 1 and TPC 10 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs unless otherwise noted.)
REV. 0 –3–
AD8132
P
arameter Conditions Min Typ Max Unit
D
IN
to OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth V
OUT
= 2 V p-p 250 300 MHz
V
OUT
= 2 V p-p, G = 2 180 MHz
–3 dB Small Signal Bandwidth V
OUT
= 0.2 V p-p 360 MHz
V
OUT
= 0.2 V p-p, G = 2 155 MHz
Bandwidth for 0.1 dB Flatness V
OUT
= 0.2 V p-p 65 MHz
V
OUT
= 0.2 V p-p, G = 2 50 MHz
Slew Rate V
OUT
= 2 V p-p 800 1000 V/µs
Settling Time 0.1%, V
OUT
= 2 V p-p 20 ns
Overdrive Recovery Time V
IN
= 2.5 V to 0 V Step, G = 2 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic V
OUT
= 2 V p-p, 1 MHz, R
L,dm
= 800 Ω–97 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–100 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–74 dBc
Third Harmonic V
OUT
= 2 V p-p, 1 MHz, R
L,dm
= 800 Ω–100 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–99 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–67 dBc
IMD 20 MHz, R
L,dm
= 800 Ω–76 dBc
IP3 20 MHz, R
L,dm
= 800 Ω40 dBm
Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz
Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz
Differential Gain Error NTSC, G = 2, R
L,dm
= 150 Ω0.025 %
Differential Phase Error NTSC, G = 2, R
L,dm
= 150 Ω0.15 Degree
INPUT CHARACTERISTICS
Offset Voltage (RTI) V
OS,dm
= V
OUT,dm
/2; V
DIN+
= V
DIN–
= V
OCM
= 2.5 V ±1.0 ±3.5 mV
T
MIN
to T
MAX
Variation 6 µV/°C
Input Bias Current 37µA
Input Resistance Differential 10 MΩ
Common-Mode 3 MΩ
Input Capacitance 1pF
Input Common-Mode Voltage –1 to +4 V
CMRR ∆V
OUT,dm
/∆V
IN,cm
; ∆V
IN,cm
= ±1 V; –70 –60 dB
Resistors Matched to 0.01%
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆V
OUT
; Single-Ended Output 1 to 3.7 V
Output Current 50 mA
Output Balance Error ∆V
OUT,cm
/∆V
OUT,dm
; ∆V
OUT,dm
= 1 V –68 dB
V
OCM
to OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth ∆V
OCM
= 600 mV p-p 210 MHz
Slew Rate ∆V
OCM
= 1.5 V to 3.5 V 340 V/µs
DC PERFORMANCE
Input Voltage Range 1 to 3.7 V
Input Resistance 130 kΩ
Input Offset Voltage V
OS,cm
= V
OUT,cm
; V
DIN+
= V
DIN–
= V
OCM
= 2.5 V ±5±11 mV
Input Bias Current 0.5 µA
V
OCM
CMRR [∆V
OUT,dm
/∆V
OCM
]; ∆V
OCM
= 2.5 ± 1 V; –66 dB
Resistors Matched to 0.01%
Gain ∆V
OUT,cm
/∆V
OCM
;
∆V
OCM
= 2.5 ± 1 V 0.985 1 1.015 V/V
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current V
DIN+
= V
DIN–
= V
OCM
= 2.5 V 9.4 10.7 12 mA
T
MIN
to T
MAX
Variation 10 µA/°C
Power Supply Rejection Ratio ∆V
OUT,dm
/∆V
S
; ∆V
S
= ±1 V –70 –60 dB
OPERATING TEMPERATURE RANGE –40
+85 °C
Specifications subject to change without notice.
(@ 25C, VS = 5 V, VOCM = 2.5 V, G = 1, RL,dm = 499 , RF = RG = 348 unless
otherwise noted. For G = 2, RL,dm = 200 , RF = 1000 , RG = 499 . Refer to TPC 1 and TPC 10 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs unless otherwise noted.)
AD8132–SPECIFICATIONS
REV. 0
–4–
AD8132–SPECIFICATIONS
P
arameter Conditions Min Typ Max Unit
D
IN
to OUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth V
OUT
= 1 V p-p 350 MHz
V
OUT
= 1 V p-p, G = 2 165 MHz
–3 dB Small Signal Bandwidth V
OUT
= 0.2 V p-p 350 MHz
V
OUT
= 0.2 V p-p, G = 2 150 MHz
Bandwidth for 0.1 dB Flatness V
OUT
= 0.2 V p-p 45 MHz
V
OUT
= 0.2 V p-p, G = 2 50 MHz
NOISE/HARMONIC PERFORMANCE
Second Harmonic V
OUT
= 1 V p-p, 1 MHz, R
L,dm
= 800 Ω–100 dBc
V
OUT
= 1 V p-p, 5 MHz, R
L,dm
= 800 Ω–94 dBc
V
OUT
= 1 V p-p, 20 MHz, R
L,dm
= 800 Ω–77 dBc
Third Harmonic V
OUT
= 1 V p-p, 1 MHz, R
L,dm
= 800 Ω–90 dBc
V
OUT
= 1 V p-p, 5 MHz, R
L,dm
= 800 Ω–85 dBc
V
OUT
= 1 V p-p, 20 MHz, R
L,dm
= 800 Ω–66 dBc
INPUT CHARACTERISTICS
Offset Voltage (RTI) V
OS,dm
= V
OUT,dm
/2; V
DIN+
= V
DIN–
= V
OCM
= 1.5 V ±10 mV
Input Bias Current 3µA
CMRR ∆V
OUT,dm
/∆V
IN,cm
; ∆V
IN,cm
= ±0.5 V; –60 dB
Resistors Matched to 0.01%
V
OCM
to OUT Specifications
DC PERFORMANCE
Input Offset Voltage V
OS,cm
= V
OUT,cm
; V
DIN+
= V
DIN–
= V
OCM
= 1.5 V ±7mV
Gain ∆V
OUT,cm
/∆V
OCM
;
∆V
OCM
= ±0.5 V 1 V/V
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current V
DIN+
= V
DIN–
= V
OCM
= 0 V 7.25 mA
Power Supply Rejection Ratio ∆V
OUT,dm
/∆V
S
; ∆V
S
= ±0.5 V –70 dB
OPERATING TEMPERATURE RANGE –40
+85 °C
Specifications subject to change without notice.
(@ 25C, VS = 3 V, VOCM = 1.5 V, G = 1, RL,dm = 499 , RF = RG = 348 unless
otherwise noted. For G = 2, RL,dm = 200 , RF = 1000 , RG = 499 . Refer to TPC 1 and TPC 10 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs unless otherwise noted.)
REV. 0 –5–
AD8132
ABSOLUTE MAXIMUM RATINGS
1, 2
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5 V
V
OCM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above listed in the operational section of this
specification is not implied. Exposure to Absolute Maximum Ratings for any
extended periods may affect device reliability.
2
Thermal resistance measured on SEMI standard 4-layer board.
8-Lead SOIC: θ
JA
= 121°C/W
8-Lead µSOIC: θ
JA
= 142°C/W
AMBIENT TEMPERATURE – C
–50
0
TJ = 150C
2.0
1.5
1.0
MAXIMUM POWER DISSIPATION – Watts
8-LEAD SOIC
PACKAGE
–40 –30 0 10203040506070 8090
8-LEAD
microSOIC
0.5
–20 –10
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8132AR –40°C to +85°C 8-Lead SOIC SO-8
AD8132AR-REEL
1
–40°C to +85°C 13" Tape and Reel
AD8132AR-REEL7
2
–40°C to +85°C 7" Tape and Reel
AD8132ARM –40°C to +85°C 8-Lead µSOIC SM-8
AD8132ARM-REEL
3
–40°C to +85°C 13" Tape and Reel
AD8132ARM-REEL7
2
–40°C to +85°C 7" Tape and Reel
AD8132-EVAL Evaluation Board
NOTES
1
13" Reels of 2500 each.
2
7" Reels of 1000 each.
3
13" Reels of 3000 each.
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1 –IN Negative Input.
2V
OCM
Voltage applied to this pin sets the common-
mode output voltage with a ratio of 1:1. For
example, 1 V dc on V
OCM
will set the dc bias
level on +OUT and –OUT to 1 V.
3 V+ Positive Supply Voltage.
4 +OUT Positive Output. Note: the voltage at –D
IN
is
inverted at +OUT.
5 –OUT Negative Output. Note: the voltage at +D
IN
is inverted at –OUT.
6 V– Negative Supply Voltage.
7 NC No Connect.
8 +IN Positive Input.
PIN CONFIGURATION
AD8132
+
1
2
3
4
NC = NO CONNECT
–IN +IN
V
OCM
NC
V+ V–
+OUT –OUT
8
7
6
5
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8132 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD8132
–6–
0.1F
348
348
49.9
24.9
348
348
499
CF
CF
TPC 1. Basic Test Circuit, G = 1
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
V
S
AS SHOWN
G = 1
V
O,dm
= 0.2V p-p
R
L,dm
= 499
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
V
S
= 3V V
S
= 5V
V
S
= 5V
TPC 4. 0.1 dB Flatness vs. Frequency;
C
F
= 0.5 pF
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
2
1
0
–1
–2
–3
–4
–5
3
V
S
= 5V
G = 1
V
O,dm
= 2V p-p
R
L,dm
= 499
TEMPERATURE AS SHOWN
–40C
+85C
+25C
TPC 7. Large Signal Response vs.
Temperature
FREQUENCY – MHz
GAIN – dB
2
1
1
0
–1
–2
–3
–4
–510 100 1k
V
S
AS SHOWN
G = 1
V
O,dm
= 0.2V p-p
R
L,dm
= 499
V
S
= 3V V
S
= 5V
V
S
= 5V
TPC 2. Small Signal Frequency
Response
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
2
1
0
–1
–2
–3
–4
–5
3
V
S
AS SHOWN
G = 1
V
O,dm
= 2V p-p FOR V
S
= 5V, 5V
V
O,dm
= 1V p-p FOR V
S
= 3V
R
L,dm
= 499
V
S
= 3V
V
S
= 5V
V
S
= 5V
V
S
= 3V
TPC 5. Large Signal Frequency
Response; C
F
= 0 pF
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
2
1
0
–1
–2
–3
–4
–5
3
VS = 5V
G = 1
VO,dm = 2V p-p
RL,dm = 499
RF AS SHOWN
RF = 499
RF = 348
RF = 249
TPC 8. Large Signal Frequency
Response vs. R
F
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
V
S
AS SHOWN
G = 1
V
O,dm
= 0.2V p-p
R
L,dm
= 499
V
S
= 3V
V
S
= 5V
V
S
= 5V
TPC 3. 0.1 dB Flatness vs. Frequency;
C
F
= 0 pF
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
2
1
0
–1
–2
–3
–4
–5
V
S
AS SHOWN
G = 1
V
O,dm
= 2V p-p FOR V
S
= 5V, 5V
V
O,dm
= 1V p-p FOR V
S
= 3V
R
L,dm
= 499
V
S
= 3V
V
S
= 5V
V
S
= 5V
V
S
= 3V
TPC 6. Large Signal Frequency
Response; C
F
= 0.5 pF
FREQUENCY – MHz
IMPEDANCE –
100
1
10
1
0.1
10 100
V
S
= 5V
V
S
= 5V
TPC 9. Closed-Loop Single-Ended
Z
OUT
vs. Frequency; G = 1
–Typical Performance Characteristics
REV. 0
AD8132
–7–
FREQUENCY – MHz
GAIN – dB
7
1
6
5
4
3
2
110 100 1k
V
S
AS SHOWN
G = 2
V
O,dm
= 0.2V p-p
R
L,dm
= 200
V
S
= 3V
V
S
= 5V,
+5V
TPC 11. Small Signal Frequency
Response
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
7
6
5
4
3
2
1
VS = 5V
G = 2
VO,dm = 0.2V p-p
RL,dm = 200
RF AS SHOWN
RF = 1.0k
RF = 499
RF = 1.5k
TPC 14. Small Signal Frequency
Response vs. R
F
0.1F
49.9
24.9
RF
RF
RG
RG
RL
RL
G = 1: RF = RG = 348, RL = 249 (RL,dm = 498)
G = 2: RF = 1000, RG = 499, RL = 100
(RL,dm = 200)
TPC 17. Test Circuit for Output
Balance
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
VS = 3V, 5V, 5V
G = 2
VO,dm = 0.2V p-p
RL,dm = 200
6.1
6.0
5.9
5.8
5.7
5.6
5.5
TPC 12. 0.1 dB Flatness vs.
Frequency
0.1F
499
499
49.9
24.9
R
F
200
R
F
TPC 15. Test Circuit for Various
Gains
FREQUENCY – MHz
RTI BALANCE ERROR – dB
1 10 100 1k
–25
–30
–35
–40
–45
–50
–55
V
S
= 5V
GAIN AS SHOWN
V
OUT,dm
= 2V p-p
V
OUT,cm
/V
OUT,dm
–60
–65
G = 1
G = 2
–70
–75
TPC 18. RTI Output Balance
Error vs. Frequency
0.1F
499
499
49.9
24.9
1000
1000
200
TPC 10. Basic Test Circuit, G = 2
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
7
6
5
4
3
2
1
V
S
= 5V, 5V
V
S
= 3V
V
S
AS SHOWN
G = 2
V
O,dm
= 2V p-p FOR
V
S
= 5V, 5V
V
O,dm
= 1V p-p FOR
V
S
= 3V
R
L,dm
= 200
TPC 13. Large Signal Frequency
Response
FREQUENCY – MHz
GAIN – dB
1 10 100 1k
25
20
15
10
5
0
–5V
S
= 5V
V
O, dm
= 2V p-p
R
L, dm
= 200
R
G
= 499
–10
–15
G = 10, R
F
= 4.99k
G = 5, R
F
= 2.49k
G = 2, R
F
= 1k
G = 1, R
F
= 499
TPC 16. Large Signal Response for
Various Gains
REV. 0
AD8132
–8–
0.1F
348
348
49.9
24.9
348
348
LPF
300
300
HPF
Z
IN
= 50
2:1 TRANSFORMER
TPC 19. Harmonic Distortion Test Circuit,
G = 1, R
L,dm
= 800
Ω
FREQUENCY – MHz
DISTORTION – dBc
0506070
–40
–50
–60
–70
–80
–90
–100
20 30 4010
–110
R
L,dm
= 800
V
OUT,dm
= 1V p-p
HD3 (V
S
= 3V)
HD2 (V
S
= 3V)
HD2 (V
S
= 5V)
HD3 (V
S
= 5V)
TPC 20. Harmonic Distortion vs.
Frequency, G = 1
DIFFERENTIAL OUTPUT VOLTAGE – V
p
-
p
DISTORTION – dBc
0
–40
–50
–60
–70
–80
–90
–100
2341
–110
V
S
= 5V
R
L,dm
= 800
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
TPC 23. Harmonic Distortion vs.
Differential Output Voltage, G = 1
FREQUENCY – MHz
DISTORTION – dBc
0506070
–40
–50
–60
–70
–80
–90
–100
20 30 4010
–110
RL,dm = 800
VOUT,dm = 2V p-p
HD3 (VS = 5V)
HD2 (VS = 5V)
HD2 (VS = 5V)
HD3 (VS = 5V)
–30
TPC 21. Harmonic Distortion vs.
Frequency, G = 1
DIFFERENTIAL OUTPUT VOLTAGE – V
p
-
p
DISTORTION – dBc
0
–40
–50
–60
–70
–80
–90
–100
2341
–110
V
S
= 5V
R
L,dm
= 800HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
56
TPC 24. Harmonic Distortion vs.
Differential Output Voltage, G = 1
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DISTORTION – dBc
0.25 1.50 1.75
–40
–50
–60
–70
–80
–90
–100
0.75 1.00 1.250.50
–110
V
S
= 3V
R
L,dm
= 800HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
TPC 22. Harmonic Distortion vs.
Differential Output Voltage, G = 1
R
LOAD
–
DISTORTION – dBc
200 700 800
–50
–60
–70
–80
–90
–100
400 500 600300
–110
V
S
= 3V
V
O,dm
= 1V p-p
900 1000
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
TPC 25. Harmonic Distortion vs.
R
LOAD
, G = 1
REV. 0
AD8132
–9–
R
LOAD
–
DISTORTION – dBc
200 700 800
–50
–60
–70
–80
–90
–100
400 500 600300
–110
V
S
= 5V
V
OUT,dm
= 2V p-p
900 1000
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
TPC 26. Harmonic Distortion vs.
R
LOAD
, G = 1
R
LOAD
–
DISTORTION – dBc
200 700 800
–50
–60
–70
–80
–90
–100
400 500 600300
–110
V
S
= 5V
V
OUT,dm
= 2V p-p
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
900 1000
TPC 27. Harmonic Distortion vs.
R
LOAD
, G = 1
0.1F
499
499
49.9
24.9
1000
1000
LPF
300
300
HPF
ZIN = 50
2:1 TRANSFORMER
TPC 28. Harmonic Distortion Test Circuit, G = 2, R
L,dm
= 800
Ω
FREQUENCY – MHz
DISTORTION – dBc
40 50
–50
–60
–70
–80
–90
–100
10 20 300
–110
HD3 (V
S
= 3V)
60 70
R
L,dm
= 800
V
OUT,dm
= 1V p-p
–40
HD3 (V
S
= 5V)
HD2 (V
S
= 5V)
HD2 (V
S
= 3V)
TPC 29. Harmonic Distortion vs.
Frequency, G = 2
FREQUENCY – MHz
DISTORTION – dBc
40 50
–50
–60
–70
–80
–90
–100
10 20 300
HD3 (V
S
= 5V)
60 70
R
L,dm
= 800
V
OUT,dm
= 4V p-p
–40
HD3 (V
S
= 5V)
HD2 (V
S
= 5V)
80
–30
–20
HD2 (V
S
= 5V)
TPC 30. Harmonic Distortion vs.
Frequency, G = 2
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DISTORTION – dBc
2
–50
–60
–70
–80
–90
–100
103
V
S
= 5V
R
L,dm
= 800
–40
HD3 (F = 20MHz)
4
–110
–120
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
TPC 31. Harmonic Distortion vs.
Differential Output Voltage, G = 2
REV. 0
AD8132
–10–
DIFFERENTIAL OUTPUT VOLTAGE – V
p
-
p
DISTORTION – dBc
2
–50
–60
–70
–80
–90
–100
103
V
S
= 5V
R
L,dm
= 800
–40
HD3 (F = 20MHz)
4
–110
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
56
TPC 32. Harmonic Distortion vs.
Differential Output Voltage, G = 2
FREQUENCY – MHz
POUT – dBm (Re:50)
10
19.5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
20 20.5
fC = 20MHz
VS = 5V
RL,dm = 800
TPC 35. Intermodulation
Distortion, G = 1
300mV 5ns
VS = 3V
VOUT,dm = 1.5V p-p
CF = 0pF
CF = 0.5pF
TPC 38. Large Signal Transient
Response, G = 1
R
LOAD
–
DISTORTION – dBc
400
–50
–60
–70
–80
–90
–100
300200 500
HD3 (F = 20MHz)
600
–110
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
700 800
V
S
= 5V
V
OUT,dm
= 2V p-p
900 1000
TPC 33. Harmonic Distortion vs.
R
LOAD
, G = 2
FREQUENCY – MHz
INTERCEPT – dBm (Re:50)
45
15 010 70
20 30 40 50 60
40
35
30
25
20
VS = 5V, 5V
RL,dm = 800
TPC 36. Third Order Intercept vs.
Frequency, G = 1
400mV 5ns
VS = 5V
VOUT,dm = 2V p-p
CF = 0pF
CF = 0.5pF
TPC 39. Large Signal Transient
Response, G = 1
R
LOAD
–
DISTORTION – dBc
400
–50
–60
–70
–80
–90
–100
300200 500
HD3 (F = 20MHz)
600
–110
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
700 800
V
S
= 5V
V
OUT,dm
= 2V p-p
900 1000
TPC 34. Harmonic Distortion vs.
R
LOAD
, G = 2
V
S
= 5V, 5V, 3V
40mV 5ns
TPC 37. Small Signal Transient
Response, G = 1
V
S
= 5V
V
OUT,dm
= 2V p-p
400mV 5ns
C
F
= 0pF
C
F
= 0.5pF
TPC 40. Large Signal Transient
Response, G = 1
REV. 0
AD8132
–11–
1V 5ns
V
OUT–
V
OUT+
V
+DIN
V
OUT,dm
TPC 41. Large Signal Transient
Response, G = 1
400mV 5ns
VS = 5, 5V
TPC 44. Large Signal Transient
Response, G = 2
0.1F
348
348
49.9
24.9
348
348
453
24.9
24.9
C
L
TPC 47. Test Circuit for Cap Load
Drive
40mV 5ns
VS = 5, 5, 3V
TPC 42. Small Signal Transient
Response, G = 2
1V 5ns
VS = 5V
VOUT,dm
VOUT–
VOUT+
V+DIN
TPC 45. Large Signal Transient
Response, G = 2
5ns
CL = 5pF
CL = 0pF
CL = 20pF
400mV
TPC 48. Large Signal Transient
Response for Various Capacitor
Loads
300mV 5ns
VS = 3V
TPC 43. Large Signal Transient
Response, G = 2
2mV 5ns
VS = 5V
G = 1
VO,dm = 2V p-p
RL,dm = 499
5ns/DIV
0.1%/DIV
0 5 10 15 20 25 30 35 40
TPC 46. 0.1% Settling Time
FREQUENCY – MHz
PSRR – dB
0.1 1 10 100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1000
V
OUT,dm
V
S
+PSRR
–PSRR
+PSRR (V
S
= 5V, 5V)
–PSRR (V
S
= 5V)
TPC 49. PSRR vs. Frequency
REV. 0
AD8132
–12–
348
348
49.9
348
348
249
249
V
OUT,dm
V
OUT, cm
NOTE: RESISTORS MATCHED TO 0.01%.
TPC 50. CMRR Test Circuit
VS = 5V
VOCM = –1V TO +1V
400mV 5ns
VOUT,cm
TPC 53. V
OCM
Transient Response
FREQUENCY – Hz
1000
10
100
10
1100 1k 10k 100k 1M 10M 100M
1.8pA/ Hz
INPUT CURRENT NOISE – pA/ Hz
TPC 56. Input Current Noise vs.
Frequency
FREQUENCY – MHz
CMRR – dB
1 10 100 1000
–70
–80
–50
–60
–30
–40
–20
V
OUT,dm
V
IN,cm
V
OUT,cm
V
IN,cm
V
S
= 5V
V
IN,cm
= 2V p-p
TPC 51. CMRR vs. Frequency
FREQUENCY – MHz
VOCM CMRR – dB
1 10 100 1000
–70
–80
–50
–60
–30
–40
–20
VOCM = 2V p-p
VOCM = 600mV p-p
VOUT,dm
VOCM
–10
TPC 54. V
OCM
CMRR vs. Frequency
5ns
VOUT,dm (0.5V/DIV)
VIN,sm (1V/DIV)
VS = 5V
VIN = 2.5V STEP
G = 2
RF = 1k
RL,dm = 200
V/DIV AS SHOWN
TPC 57. Overdrive Recovery
FREQUENCY – MHz
dB
1 10 100 1000
–9
–12
–3
–6
0
V
OUT,cm
V
OCM
V
OCM
= 600mV p-p
V
OCM
= 2V p-p
3
6
–15
V
S
= 5V
TPC 52. V
OCM
Gain Response
FREQUENCY – Hz
INPUT VOLTAGE NOISE – nV/ Hz
1000
10
100
10
1100 1k 10k 100k 1M 10M
8nV/ Hz
100M
TPC 55. Input Voltage Noise vs.
Frequency
TEMPERATURE – C
SUPPLY CURRENT – mA
15
13
5
–50 –30 90
–10 10 30 50 70
11
9
7
V
S
= 5V
V
S
= 5V
TPC 58. Quiescent Current vs.
Temperature
REV. 0
AD8132
–13–
OPERATIONAL DESCRIPTION
Definition of Terms
AD8132
C
F
+IN
–IN
R
F
C
F
R
F
R
G
R
G
+D
IN
V
OCM
–D
IN
R
L, dm
+OUT
V
OUT, dm
–OUT
Figure 3. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as:
V
OUT,dm
= (V
+OUT
– V
–OUT
)
V
+OUT
and V
–OUT
refer to the voltages at the +OUT and –OUT
terminals with respect to a common reference.
Common-mode voltage refers to the average of two node volt-
ages. The output common-mode voltage is defined as:
V
OUT,cm
= (V
+OUT
+ V
–OUT
)/2
Basic Circuit Operation
One of the more useful and easy to understand ways to use the
AD8132 is to provide two equal-ratio feedback networks. To
match the effect of parasitics, these networks should actually be
comprised of two equal-value feedback resistors, R
F
and two
equal-value gain resistors, R
G
. This circuit is diagrammed in
Figure 3.
Like a conventional op amp, the AD8132 has two differential
inputs that can be driven with both a differential-mode input
voltage, V
IN,dm
, and a common-mode input voltage, V
IN,cm
.
There is another input, V
OCM
, which is not present on conven-
tional op amps, but provides another input to consider on the
AD8132. It is totally separate from the above inputs.
There are two complementary outputs whose response can be
defined by a differential-mode output, V
OUT,dm
and a common-
mode output, V
OUT,cm
.
TEMPERATURE – C
DIFFERENTIAL OUTPUT OFFSET – mV
0
–0.5
–2.5
–40 –20 100
0 20406080
–1.0
–1.5
–2.0
V
S
= 5V
V
S
= 5V
TPC 59. Differential Offset Voltage vs. Temperature
Table I indicates the gain from any type of input to either type
of output.
Table I. Differential and Common-Mode Gains
Input V
OUT,dm
V
OUT,cm
V
IN,dm
R
F
/R
G
0 (By Design)
V
IN,cm
0 0 (By Design)
V
OCM
0 1 (By Design)
The differential output (V
OUT,dm
) is equal to the differential
input voltage (V
IN,dm
) times R
F
/R
G
. In this case, it does not
matter if both differential inputs are driven, or only one output
is driven and the other is tied to a reference voltage, like ground.
As can be seen from the two zero entries in the first column,
neither of the common-mode inputs has any effect on this gain.
The gain from V
IN,dm
to V
OUT,cm
is 0 and to first order does not
depend on the ratio matching of the feedback networks. The
common-mode feedback loop within the AD8132 provides a
corrective action to keep this gain term minimized. The term
“balance error” describes the degree to which this gain term
differs from zero.
The gain from V
IN,cm
to V
OUT,dm
does directly depend on the
matching of the feedback networks. The analogous term for this
transfer function, which is used in conventional op amps, is
“common-mode rejection ratio” or CMRR. Thus, if it is desirable
to have a high CMRR, the feedback ratios must be well matched.
The gain from V
IN,cm
to V
OUT,cm
is also ideally 0, and is first-
order independent of the feedback ratio matching. As in the
case of V
IN,dm
to V
OUT,cm
, the common-mode feedback loop
keeps this term minimized.
The gain from V
OCM
to V
OUT,dm
is ideally 0 only when the feed-
back ratios are matched. The amount of differential output
signal that will be created by varying V
OCM
is related to the
degree of mismatch in the feedback networks.
V
OCM
controls the output common-mode voltage V
OUT,cm
with a
unity-gain transfer function. With equal-ratio feedback networks
(as assumed above), its effect on each output will be the same,
which is another way to say that the gain from V
OCM
to V
OUT,dm
is zero. If not driven, the output common-mode will be at mid-
supplies. It is recommended that a 0.1 µF bypass capacitor be
connected to V
OCM
.
REV. 0
AD8132
–14–
When unequal feedback ratios are used, the two gains associated
with V
OUT,dm
become nonzero. This significantly complicates
the mathematical analysis along with any intuitive understand-
ing of how the part operates. Some of these configurations will
be in another section.
THEORY OF OPERATION
The AD8132 differs from conventional op amps by the external
presence of an additional input and output. The additional
input, V
OCM
, controls the output common-mode voltage. The
additional output is the analog complement of the single output
of a conventional op amp. For its operation, the AD8132 makes
use of two feedback loops as compared to the single loop of
conventional op amps. While this provides significant freedom
to create various novel circuits, basic op amp theory can still be
used to analyze the operation.
One of the feedback loops controls the output common-mode
voltage, V
OUT,cm
. Its input is V
OCM
(Pin 2) and the output is the
common-mode, or average voltage, of the two differential outputs
(+OUT and –OUT). The gain of this circuit is internally set to
unity. When the AD8132 is operating in its linear region, this
establishes one of the operational constraints: V
OUT,cm
= V
OCM
.
The second feedback loop controls the differential operation.
Similar to an op amp, the gain and gain-shaping of the transfer
function is controllable by adding passive feedback networks. How-
ever, only one feedback network is required to “close the loop” and
fully constrain the operation. But depending on the function
desired, two feedback networks can be used. This is possible as
a result of having two outputs that are each inverted with respect
to the differential inputs.
General Usage of the AD8132
Several assumptions are made here for a first-order analysis, which
are the typical assumptions used for the analysis of op amps:
• The input impedances are arbitrarily large and their loading
effect can be ignored.
• The input bias currents are sufficiently small so they can be
neglected.
• The output impedances are arbitrarily low.
• The open-loop gain is arbitrarily large, which drives the
amplifier to a state where the input differential voltage is
effectively zero.
• Offset voltages are assumed to be zero.
While it is possible to operate the AD8132 with a purely differ-
ential input, many of its applications call for a circuit that has a
single-ended input with a differential output.
For a single-ended-to-differential circuit, the R
G
of the undriven
input will be tied to a reference voltage. For now this is ground,
and other conditions will be discussed later. Also, the voltage at
V
OCM
, and hence V
OUT,cm
will be assumed to be ground for now.
Figure 4 shows a generalized schematic of such a circuit using
an AD8132 with two feedback paths.
For each feedback network, a feedback factor can be defined,
which is the fraction of the output signal that is fed back to the
opposite-sign input. These terms are:
β1 = R
G1
/(R
G1
+ R
F1
)
β2 = R
G2
/(R
G2
+ R
F2
)
The feedback factor β1 is for the side that is driven, while the
feedback factor β2 is for the side that is tied to a reference volt-
age, (ground for now). Note also that each feedback factor can
vary anywhere between 0 and 1.
A single-ended-to-differential gain equation can be derived
which is true for all values of β1 and β2:
G = 2 × (1–β1)/(β1 + β2)
This expression is not very intuitive, but some further examples
can provide better understanding of its implications. One obser-
vation that can be made right away is that a tolerance error in β1
does not have the same effect on gain as the same tolerance
error in β2.
Resistorless Differential Amplifier (High Input Impedance
Inverting Amplifier)
The simplest closed-loop circuit that can be made does not require
any resistors and is shown in Figure 7. In this circuit, β1 is equal
to zero, and β2 is equal to one. The gain is equal to two.
A more intuitive means to figure the gain is by simple inspec-
tion. +OUT is connected to –IN, whose voltage is equal to the
voltage at +IN under equilibrium conditions. Thus, +V
OUT
is
equal to V
IN
, and there is unity gain in this path. Since –OUT
has to swing in the opposite direction from +OUT due to the
common-mode constraint, its effect will double the output
signal and produce a gain of two.
One useful function that this circuit provides is a high input-
impedance inverter. If +OUT is ignored, there is a unity-gain,
high-input-impedance amplifier formed from +IN to –OUT.
Most traditional op amp inverters have relatively low input
impedances, unless they are buffered with another amplifier.
V
OCM
has been assumed to be at midsupply. Since there is
still the constraint from the above discussion that +V
OUT
must
equal V
IN
, changing the V
OCM
voltage will not change +V
OUT
(= V
IN
). Therefore, all of the effect of changing V
OCM
must
show up at –OUT.
For example, if V
OCM
is raised by 1 V, then –V
OUT
must go up
by 2 V. This makes V
OUT,cm
also go up by 1 V, since it is defined
as the average of the two differential output voltages. This means
that the gain from V
OCM
to the differential output is two.
Other 2 = 1 Circuits
The above simple configuration with β2 = 1 and its gain-of-two
is the highest gain circuit that can be made under this condition.
Since β1 was equal to zero, only higher β1 values are possible.
All of these circuits with higher values of β1 will have gains lower
than two. However, circuits with β1 equal to one are not practical,
because they have no effective input, and result in a gain of 0.
To increase β1 from zero, it is necessary to add two resistors in
a feedback network. A generalized circuit that has β1 with a
value higher than zero is shown in Figure 6. A couple of differ-
ent convenient gains that can be created are a gain of 1, when
β1 is equal to 1/3, and a gain of 0.5 when β1 equals 0.6.
In all of these circuits with β2 equal to 1, V
OCM
serves as the
reference voltage from which to measure the input voltage and
the individual output voltages. In general, when V
OCM
is varied
in these circuits, a differential output signal will be generated in
addition to V
OUT,cm
changing the same amount as the voltage
change of V
OCM
.
REV. 0
AD8132
–15–
Varying 2
While the circuit above sets β2 to 1, another class of simple
circuits can be made that set β2 equal to zero. This means that
there is no feedback from +OUT to –IN. This class of circuits is
very similar to a conventional inverting op amp. However, the
AD8132 circuits have an additional output and common-mode
input which can be analyzed separately (see Figure 8).
With –IN connected to ground, +IN becomes a “virtual ground”
in the same sense that the term is used in conventional op amps.
Both inputs must maintain the same voltage for equilibrium
operation, so if one is set to ground, the other will be driven to
ground. The input impedance can also be seen to be equal to
R
G
, just as in a conventional op amp.
In this case, however, the positive input and negative output are
used for the feedback network. Since a conventional op amp
does not have a negative output, only its inverting input can be
used for the feedback network. The AD8132 is symmetrical, so the
feedback network on either side can be used to produce the same
results.
Since +IN is a summing junction, by analogy to conventional op
amps, the gain from V
IN
to –OUT will be –R
F
/R
G
. This will hold
true regardless of the voltage on V
OCM
. And since +OUT will
move the same amount in the opposite direction from –OUT,
the overall gain will be –2 (R
F
/R
G
).
V
OCM
still governs V
OUT,cm
, so +OUT must be the only output
that moves when V
OCM
is varied. Since V
OUT,cm
is the average
of the two outputs, +OUT must move twice as fast and in the
same direction as V
OCM
to create the proper V
OUT,cm
. Therefore,
the gain from V
OCM
to +OUT must be two.
In these circuits with β2 equal to zero, the gain can theoretically
be set to any value from close to zero to infinity, just as it can
with a conventional op amp in the inverting mode. However,
practical real-world limitations and parasitics will limit the range
of acceptable gains to more modest values.
1 = 0
There is yet another class of circuits where there is no feedback
from –OUT to +IN. This is the case where β1 = 0. The resistorless
differential amplifier described above meets this condition, but
it was presented only with the condition that β2 = 1. Recall that
this circuit had a gain equal to two.
If β2 is decreased in this circuit from unity, a smaller part of
+V
OUT
will be fed back to –IN and the gain will increase. See
Figure 5. This circuit is very similar to a noninverting op amp
configuration, except for the presence of the additional comple-
mentary output. Therefore, the overall gain is twice that of a
noninverting op amp or 2 × (1 + R
F2
/R
G2
) or 2 × (1/ β2).
Once again, varying V
OCM
will not affect both outputs in the
same way, so in addition to varying V
OUT,cm
with unity gain,
there will also be an affect on V
OUT,dm
by changing V
OCM
.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
GR
R
N
F
G
=+
1
To compute the total output referred noise for the circuit of
Figure 3, consideration must also be given to the contribution of
the resistors R
F
and R
G
. Refer to Table II for estimated output
noise voltage densities at various closed-loop gains.
Table II. Recommended Resistor Values and
Noise Performance for Specific Gains
R
G
R
F
Bandwidth Output Noise Output Noise
Gain ()() –3 dB AD8132 Only AD8132 + R
G
, R
F
1 499 499 360 MHz 16 nV/√Hz 17 nV/√Hz
2 499 1.0 k 160 MHz 24.1 nV/√Hz 26.1 nV/√Hz
5 499 2.49 k 65 MHz 48.4 nV/√Hz 53.3 nV/√Hz
10 499 4.99 k 20 MHz 88.9 nV/√Hz 98.6 nV/√Hz
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as that in Fig-
ure 3, at +D
IN
and –D
IN
, will depend on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (R
IN
,dm)
between the inputs (+D
IN
and –D
IN
) is simply:
R
IN,dm
= 2 × R
G
In the case of a single-ended input signal (for example if –D
IN
is
grounded and the input signal is applied to +D
IN
), the input
impedance becomes:
RR
R
RR
IN dm
G
F
GF
,=
−×+
()
1
2
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor R
G
.
Input Common-Mode Voltage Range in Single Supply
Applications
The AD8132 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at –D
IN
in Figure 3 would be zero
volts when the amplifier’s negative power supply voltage (at V–)
was also set to zero volts.
Setting the Output Common-Mode Voltage
The AD8132’s V
OCM
pin is internally biased at a voltage approxi-
mately equal to the midsupply point (average value of the voltages
on V+ and V–). Relying on this internal bias will result in an
output common-mode voltage that is within about 100 mV of
the expected value.
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source,
or resistor divider (with R
SOURCE
< 10K), be used. The output
common-mode offset specified on pages 2 and 3 assume the
V
OCM
input is driven by a low impedance voltage source.
REV. 0
AD8132
–16–
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8132 resulting in high frequency ringing in
the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in TPC 47.
LAYOUT, GROUNDING AND BYPASSING
As a high-speed part, the AD8132 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high-
speed PCB design.
The first requirement is a good solid ground plane that covers as
much of the board area around the AD8132 as possible. The
only exception to this is that the two input pins (Pins 1 and 8)
should be kept a few mm from the ground plane, and ground
should be removed from inner layers and the opposite side of
the board under the input pins. This will minimize the stray
capacitance on these nodes and help preserve the gain flatness
vs. frequency.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high-frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 µF to 0.1 µF for each
supply. Further away, low frequency bypassing should be provided
with 10 µF tantalum capacitors from each supply to ground.
The signal routing should be short and direct in order to avoid
parasitic effects. Wherever there are complementary signals, a
symmetrical layout should be provided to the extent possible to
maximize the balance performance. When running differential
signals over a long distance, the traces on PCB should be close
together or any differential wiring should be twisted together to
minimize the area of the loop that is formed. This will reduce
the radiated energy and make the circuit less susceptible to
interference.
CIRCUITS
RF1
+
RF2
RG1
RG2
Figure 4. Typical Four-Resistor Feedback Circuit
+
RF2
RG2
VIN
Figure 5. Typical Circuit with
β
1 = 0
RF1
+
RG1
Figure 6. Typical Circuit with
β
2 = 1
+
VIN
Figure 7. Resistorless G = 2 Circuit with
β
1 = 0
R
F1
+
R
G1
V
IN
Figure 8. Typical Circuit with
β
2 = 0
REV. 0
AD8132
–17–
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
FUND
2ND
3RD 4TH
5TH
7TH
8TH
9TH
6TH
fS = 40MHz
fIN = 2.5MHz
INPUT FREQUENCY – MHz
OUTPUT – dBc
Figure 10. FFT Response for AD8132 Driving AD9203
Balanced Cable Driver
When driving a twisted pair cable, it is desirable to drive only a
pure differential signal onto the line. If the signal is purely dif-
ferential (i.e., fully balanced), and the transmission line is twisted
and balanced, there will be a minimum radiation of any signal.
3V
0.1F10F
+
3V
348
0.1F
348
49.9
348
24.9
10k
10k
1V p-p
348
60.4
60.4
20pF
20pF
AINN
AINP
AVDD DRVDD
AVSS DRVSS
AD9203 DIGITAL
OUTPUTS
3V
0.1F0.1F
AD8132
Figure 9. AD8132 Driving AD9203, a 10-Bit 40 MSPS A/D Converter
APPLICATIONS
A/D Driver
Many of the newer high-speed A/D converters are single-supply
and have differential inputs. Thus, the driver for these devices
should be able to convert from a single-ended to a differential
signal and provide output common-mode level-shifting in
addition to having low distortion and noise. The AD8132 con-
veniently performs these functions when driving the AD9203, a
10-bit, 40 MSPS A/D converter.
In Figure 9 a 1 V p-p signal drives the input of an AD8132
configured for unity gain. Both the AD8132 and the AD9203
are powered from a single 3 V supply. A voltage divider biases
V
OCM
at midsupply, which in turn drives V
OUT,cm
to be half the
supply voltage. This is within the common-mode range of the
AD9203.
Between the A/D and the driver is a one-pole, differential filter
that helps to filter some of the noise and assists the switched-
capacitor inputs of the A/D. Each of the A/D inputs will be driven
by a 0.5 V p-p signal that goes from 1.25 V dc to 1.75 V dc.
Figure 10 is an FFT plot of the performance of the circuit when
running at a clock rate of 40 MSPS and an input frequency of
2.5 MHz.
499
523
1k
1k
10F
+
+5V
AD8132
0.1F
49.9
50
SOURCE
0.1F
+0.1F
10F
–5V
49.9
49.9
TWISTED
PAIR
100
1
2
3
4
7
5
AD830
+0.1F
10F
–5V
10F
+
+5V
0.1F
V
OUT
Figure 11. Balanced Line Driver and Receiver Using AD8132 and AD830
REV. 0
AD8132
–18–
Low-Pass Differential Filter
Similar to an op amp, various types of active filters can be cre-
ated with the AD8132. These can have single-ended inputs and
differential outputs, which can provide an antialias function
when driving a differential A/D converter.
Figure 14 is a schematic of a low-pass, multiple-feedback filter.
The active section contains two poles, and an additional pole is
added at the output. The filter was designed to have a –3 dB
frequency of 1 MHz. The actual –3 dB frequency was measured
to be 1.12 MHz as shown in Figure 15.
33pF
2.15k
953
953
33pF
2.15k
100pF
100pF
2k
2k
24.9
49.9
549
549
200pF
200pF
VIN VOUT
Figure 14. 1 MHz, 3-Pole Differential Output Low-Pass
Multiple Feedback Filter
FREQUENCY – Hz
10
10k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100k 1M 10M 100M
VOUT/VIN – dB
Figure 15. Frequency Response of 1 MHz Low-Pass Filter
High Common-Mode-Output-Impedance Amplifier
Changing the connection to V
OCM
(Pin 2) can change the
common-mode from low impedance to high impedance. If
V
OCM
is actively set to a particular voltage, the AD8132 will try
to force V
OUT,cm
to the same voltage with a relatively low output
impedance. All the previous analysis assumed that this output
impedance is arbitrarily low enough to drive the load condition
in the circuit.
However, the are some applications that benefit from a high
common-mode output impedance. This can be accomplished
with the circuit shown in Figure 16.
R
G
348
R
F
348
R
F
348
R
G
348
10
10
1k
1k
49.9
49.9
Figure 16. High Common-Mode Output Impedance Differ-
ential Amplifier
The complementary electrical fields will mostly be confined to
the space between the two twisted conductors and will not sig-
nificantly radiate out from the cable. The current in the cable will
create magnetic fields that will radiate to some degree. However,
the amount of radiation is mitigated by the twists, because for
each twist, the two adjacent twists will have an opposite polarity
magnetic field. If the twist pitch is tight enough, these small
magnetic field loops will contain most of the magnetic flux,
and the magnetic far-field strength will be negligible.
Any imbalance in the differential drive signal will appear as a
common-mode signal on the cable. This is the equivalent of a
single wire that is driven with the common-mode signal. In this
case, the wire will act as an antenna and radiate. Thus, in order
to minimize radiation when driving differential twisted pair
cables, the differential drive signal should be very well balanced.
The common-mode feedback loop in the AD8132 helps to
minimize the amount of common-mode voltage at the output,
and can therefore be used to create a well-balanced differential
line driver. Figure 11 shows an application that uses an AD8132
as a balanced line driver and AD830 as a differential receiver
configured for unity gain. This circuit was operated with 10 m
of Category 5 cable.
Transmit Equalizer
Any length of transmission line will attenuate the signals it carries.
This effect is worse at higher frequencies than at low frequen-
cies. One way to compensate for this is to provide an equalizer
circuit that boosts the higher frequencies in the transmitter
circuit, so that at the receive end of the cable, the attenuation
effects are diminished.
By lowering the impedance of the R
G
component of the feed-
back network at higher frequency, the gain can be increased at
high frequency. Figure 12 shows a gain-of-two line driver that
has its R
G
s shunted by 10 pF resistors. The effect of this is shown
in the frequency response plot of Figure 13.
249
49.9
10pF 499
10pF
249
24.9
VIN
49.9
499
49.9
100VOUT
Figure 12. Frequency Boost Circuit
11000
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
V
OUT
/V
IN
– dB
10 100
FREQUENCY – MHz
Figure 13. Frequency Response for Transmit Boost Circuit
REV. 0
AD8132
–19–
V
OCM
is driven by a resistor divider that “measures” the output
common- mode voltage. Thus, the common-mode output volt-
age takes on the value that is set by the driven circuit. In this
case it comes from the center point of the termination at the
receive end of a 10 m length of Category 5 twisted pair cable.
If the receive end common-mode voltage is set to “ground,” it
will be well-defined at the receive end. Any common-mode
signal that is picked up over the cable length due to noise, will
appear at the transmit end, and must be “absorbed” by the
transmitter. Thus, it is important that the transmitter have
adequate common-mode output range to absorb the full ampli-
tude of the common-mode signal coupled onto the cable and
thus prevent clipping.
Another way to look at this is that the circuit performs what is
sometimes called “transformer action.” One main difference is
that the AD8132 passes dc while transformers do not.
A transformer can also be easily configured to have either a high
or low common-mode output impedance. If the transformer’s
center tap is connected to a solid voltage reference, it will set the
common-mode voltage on the secondary side of the transformer.
In this case, if one of the differential outputs is grounded, the
other output will have only half of the differential output signal.
This keeps the common-mode voltage at ground, where it is
required to be due to the center tap connection. This is analo-
gous to the AD8132 operating with a low output impedance
common-mode. See Figure 17.
V
DIFF
V
OCM
Figure 17. Transformer Whose Low Output Impedance
Secondary Is Set at V
OCM
If the center tap of the secondary of a transformer is allowed to
float (or there is no center tap), the transformer will have a high
common-mode output impedance. This means that the common-
mode of the secondary will be determined by what it is connected
to, and not by anything to do with the transformer itself.
If one of the differential ends of the transformer is grounded, the
other end will swing with the full output voltage. This means
that the common-mode of the output voltage is one-half of the
differential output voltage. But this shows that the common-mode
is not forced via a low impedance to a given voltage. The common-
mode output voltage can easily be changed to any voltage through
its other output terminals.
The AD8132 can exhibit the same performance when one of the
outputs in Figure 16 is grounded. The other output will swing
at the full differential output voltage. The common-mode signal
is “measured” by the voltage divider across the outputs and input
to V
OCM
. This then drives V
OUT,cm
to the same level. At higher
frequencies, it is important to minimize the capacitance on the
V
OCM
node or else phase shifts can compromise the performance.
The voltage divider resistances can also be lowered for better
frequency response.
V
DIFF
V
OCM
Figure 18. Transformer with High Output Impedance
Secondary
Full-Wave Rectifier
The balanced outputs of the AD8132, along with a couple of
Schottky diodes, can create a very high-speed full-wave rectifier.
Such circuits are useful for measuring ac voltages and other
computational tasks.
Figure 19 shows the configuration of such a circuit. Each of the
AD8132 outputs drives the anode of an HP 2835 Schottky diode.
These Schottky diodes were chosen for their high-speed opera-
tion. At lower frequencies (approximately lower than 10 MHz),
a silicon signal diode, like a 1N4148 can be used. The cathodes
of the two diodes are connected together and this output node is
connected to ground by a 50 Ω resistor.
R
G1
348
R
F1
348
R
F2
348
R
G2
348
+5V
–5V
R
L
100
R
T2
24.9
R
T1
49.9
V
IN
HP2835
V
OUT
5V
CR1
10k
Figure 19. Full-Wave Rectifier
The diodes should be operated such that they are slightly forward-
biased when the differential output voltage is zero. For the
Schottky diodes, this is about 400 mV. The forward biasing can
be conveniently adjusted by CR1, which, in this circuit, raises
and lowers V
OUT,CM
without creating a differential output voltage.
One advantage of this circuit is that the feedback loop is never
momentarily opened while the diodes reverse their polarity within
the loop. This is the scheme that is sometimes used for full-wave
rectifiers that use conventional op amps. These conventional
circuits do not work well at frequencies above about 1 MHz.
If there is not enough forward bias (V
OUT,cm
too low), the lower
sharp cusps of the full-wave rectified output waveform will be
rounded off. Also, as the frequency increases, there tends to be
some rounding of the lower cusps. The forward bias can be
increased to yield sharper cusps at higher frequencies.
There is not a reliable, entirely quantifiable, means to measure
the performance of a full-wave rectifier. Since the ideal wave-
form has periodic sharp discontinuities, it should have (mostly
even) harmonics that have no upper bound on the frequency.
However, for a practical circuit, as the frequency increases, the
higher harmonics become attenuated and the sharp cusps that
are present at low frequencies become significantly rounded.
REV. 0
–20–
C3846–8–4/00 (rev. 0) 01035
PRINTED IN U.S.A.
AD8132
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25) 45
85
41
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
8-Lead microSOIC
(SM-8)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
85
41
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
The circuit was run at a frequency up to 300 MHz and, while
it was still functional, the major harmonic that remained in
the output was the second. This made it look like a sine
wave at 600 MHz. Figure 20 is an oscilloscope plot of the
output when driven by a 100 MHz, 2.5 V p-p input.
Sometimes a second harmonic generator is actually useful, as
for creating a clock to oversample a DAC by a factor of two.
If the output of this circuit is run through a low-pass filter, it
can be used as a second harmonic generator.
100mV 2ns
1V
Figure 20. Full-Wave Rectifier Response with
100 MHz Input
