PRELIMINARY
3.3V Programmable Skew Clock Buffe
r
CY7C9915
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-07687 Rev. *A Revised April 29, 2005
Features
• All output pair skew <100 ps (typical)
• Input Frequency Range: 3.75 MHz to 150 MHz
• Output Frequency Range: 3.75 MHz to 150 MHz
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 1⁄2 and 1⁄4 input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input-to-output delay
• 3.3V power supply
• ± 3.0% Output Duty Cycle Distortion
•LVTTL outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC package
• Jitter < 100ps peak-to-peak (< 15 ps RMS)
Functional Description
The CY7C9915 RoboClock is a 150-MHz Low-voltage
Programmable Skew Clock Buffer that offers user-selectable
control over system clock functions. This multiple-output clock
driver provides the system integrator with functions necessary
to optimize the timing of high-performance computer systems.
Eight individual drivers, arranged as four pairs of user-control-
lable outputs, can each drive terminated transmission lines
with impedances as low as 50Ω while delivering minimal and
specified output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.42 to 1.6 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and trans-
mission line delay effects to be canceled. When this “zero
delay” capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility
minimizes clock distribution difficulty while allowing maximum
system clock speed and flexibility.
Block Diagram Pin Configuration
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL) SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
CY7C9915
3031
32
1
2
34
3F0
VCCQ
FS
REF
GND
TEST
2F1
2019
18
17
16
1514
3Q1
VCCN3
3Q0
FB
VCCN2
2Q1
2Q0
5
6
7
8
9
10
11
12
13
3F1
4F1
4F0
VCCQ
VCCN4
4Q1
4Q0
GND
GND
29
28
27
26
25
24
23
22
21
2F0
1F1
GND
1F0
VCCN1
1Q0
1Q1
GND
GND
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 2 of 14
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the Reference Frequency
(REF) input and the Feedback (FB) input and generate
correction information to control the frequency of the
Voltage-Controlled Oscillator (VCO). These blocks, along with
the VCO, form a Phase-Locked Loop (PLL) that tracks the
incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create discrete time units that are selected in the
skew select matrix. The operational range of the VCO is deter-
mined by the FS control pin. The time unit (tU) is determined
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.
Skew Select Matrix
The skew select matrix is comprised of four independent
sections. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
(xF0, xF1) inputs. Table 2 below shows the nine possible
output functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0tU selected.
Notes:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal
frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the
REF and FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part
is configured for a frequency multiplication by using a divided output as the FB input.
Pin Definitions (CY7C9915)
Pin No. Name I/O Type Description
1 REF Input LVTTL/LVCMOS Reference Clock Input
17 FB Input LVTTL Feedback Clock Input
3 FS Input Three-level Three Level Frequency Range Select
26,27 1F0, 1F1 Input Three-level Three level function select for 1Q0,1Q1
29,30 2F0, 2F1 Input Three-level Three level function select for 2Q0,2Q1
4,5 3F0, 3F1 Input Three-level Three level function select for 3Q0,3Q1
6,7 4F0, 4F1 Input Three-level Three level function select for 4Q0,4Q1
31 Test Input Three-level Three level select for test modes
23,24 1Q0, 1Q1 Output LVTTL Output Pair
19,20 2Q0, 2Q1 Output LVTTL Output Pair
14,15 3Q0, 3Q1 Output LVTTL Output Pair
10,11 4Q0, 4Q1 Output LVTTL Output Pair
25 VCCN1 Power POWER 3.3V Power Supply for output pair 1Q0 and 1Q1.
18 VCCN2 Power POWER 3.3V Power Supply for output pair 2Q0 and 2Q1.
16 VCCN3 Power POWER 3.3V Power Supply for output pair 3Q0 and 3Q1.
9 VCCN4 Power POWER 3.3V Power Supply for output pair 4Q0 and 4Q1.
2,8 VCCQ Power POWER 3.3V Core Power
12,13,21,22,
28, 32
GND Ground POWER Ground
Table 1. Frequency Range Select and tU Calculation[1]
FS[2]
fNOM (MHz)
where N =
Approximate
Frequency (MHz)
At Which tU = 1.0
nsMin. Max.
LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 150 16 62.5
tU
1
fNOM
N
×
----------------------
--
=
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 3 of 14
Test Mode
The TEST input is a three-level input. In normal system
operation, this pin is connected to ground, allowing the
CY7C9915 to operate as explained briefly above (for testing
purposes, any of the three-level inputs can have a removable
jumper to ground, or be tied LOW through a 100Ω resistor.
This will allow an external tester to change the state of these
pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.
Note:
3. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
Table 2. Programmable Skew Configurations[1]
Function Selects Output Functions
1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1
LOW LOW –4tUDivide by 2 Divide by 2
LOW MID –3tU–6tU–6tU
LOW HIGH –2tU–4tU–4tU
MID LOW –1tU–2tU–2tU
MID MID 0tU0tU0tU
MID HIGH +1tU+2tU+2tU
HIGH LOW +2tU+4tU+4tU
HIGH MID +3tU+6tU+6tU
HIGH HIGH +4tUDivide by 4 Inverted
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[3]
t
0– 6t U
t
0– 5t U
t
0– 4t U
t
0– 3t U
t
0– 2t U
t
0– 1t U
t
0
t
0+1t U
t
0
t
0
t
0
t
0
t
0
+2t U
+3t U
+4t U
+5t U
+6t U
FBInput
REFInput
– 6tU
– 4tU
– 3tU
– 2tU
– 1tU
0tU
+1tU
+2tU
+3tU
+4tU
+6tU
DIVIDED
INVERT
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
3Fx
4Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
1Fx
2Fx
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 4 of 14
Operational Mode Descriptions
Figure 2 shows the LVPSCB configured as a zero-skew clock
buffer. In this mode the CY7C9915 can be used as the basis
for a low-skew clock distribution tree. When all of the function
select inputs (xF0, xF1) are left open, the outputs are aligned
and may each drive a terminated transmission line to an
independent load. The FB input can be tied to any output in
this configuration and the operating frequency range is
selected with the FS pin. The low-skew specification, coupled
with the ability to drive terminated transmission lines (with
impedances as low as 50Ω), allows efficient printed circuit
board design.
Figure 3 shows a configuration to equalize skew between
metal traces of different lengths. In addition to low skew
between outputs, the LVPSCB can be programmed to stagger
the timing of its outputs. The four groups of output pairs can
each be programmed to different output timing. Skew timing
can be adjusted over a wide range in small increments with the
appropriate strapping of the function select pins. In this config-
uration the 4Q0 output is fed back to FB and configured for
zero skew. The other three pairs of outputs are programmed
to yield different skews relative to the feedback. By advancing
the clock signal on the longer traces or retarding the clock
signal on shorter traces, all loads can receive the clock pulse
at the same time.
In this illustration the FB input is connected to an output with
0-ns skew (xF1, xF0 = MID) selected. The internal PLL
synchronizes the FB and REF inputs and aligns their rising
edges to insure that all outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (tU) when using
an output selected for zero skew as the feedback. A wider
range of delays is possible if the output connected to FB is also
skewed. Since “Zero Skew”, +tU, and –tU are defined relative
to output groups, and since the PLL aligns the rising edges of
REF and FB, it is possible to create wider output skews by
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
SYSTEM
CLOCK
L1
L2
L3
L4
LENGTH L1 = L2 = L3 = L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
Z0
LOAD
LOAD
LOAD
LOAD
REF
Z0
Z0
Z0
Figure 3. Programmable-Skew Clock Driver
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 b
y
6 inches
SYS-
TEM
CLOCK
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
Z0
LOAD
LOAD
LOAD
LOAD
REF
Z0
Z0
Z0
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 5 of 14
proper selection of the xFn inputs. For example a +10 tU
between REF and 3Qx can be achieved by connecting 1Q0 to
FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High.
(Since FB aligns at –4 tU and 3Qx skews to +6 tU, a total of
+10 tU skew is realized.) Many other configurations can be
realized by skewing both the output used as the FB input and
skewing the other outputs.
Figure 4 shows an example of the invert function of the
LVPSCB. In this example the 4Q0 output used as the FB input
is programmed for invert (4F0 = 4F1 = HIGH) while the other
three pairs of outputs are programmed for zero skew. When
4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted
zero phase outputs. The PLL aligns the rising edge of the FB
input with the rising edge of the REF. This causes the 1Q, 2Q,
and 3Q outputs to become the “inverted” outputs with respect
to the REF input. By selecting which output is connect to FB,
it is possible to have 2 inverted and 6 non-inverted outputs or
6 inverted and 2 non-inverted outputs. The correct configu-
ration would be determined by the need for more (or fewer)
inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed
to compensate for varying trace delays independent of
inversion on 4Q.
Figure 5 illustrates the LVPSCB configured as a clock multi-
plier. The 3Q0 output is programmed to divide by four and is
fed back to FB. This causes the PLL to increase its frequency
until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the
1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1
outputs are programmed to divide by two, which results in a
40-MHz waveform at these outputs. Note that the 20- and
40-MHz clocks fall simultaneously and are out of phase on
their rising edge. This will allow the designer to use the rising
edges of the 1⁄2 frequency and 1⁄4 frequency outputs without
concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1
outputs run at 80 MHz and are skewed by programming their
select inputs accordingly. Note that the FS pin is wired for
80-MHz operation because that is the frequency of the fastest
output.
Figure 6 demonstrates the LVPSCB in a clock divider appli-
cation. 2Q0 is fed back to the FB input and programmed for
zero skew. 3Qx is programmed to divide by four. 4Qx is
programmed to divide by two. Note that the falling edges of the
4Qx and 3Qx outputs are aligned. This allows use of the rising
edges of the 1⁄2 frequency and 1⁄4 frequency without concern
for skew mismatch. The 1Qx outputs are programmed to zero
skew and are aligned with the 2Qx outputs. In this example,
the FS input is grounded to configure the device in the 15- to
30-MHz range since the highest frequency output is running at
20 MHz.
Figure 7 shows some of the functions that are selectable on
the 3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An
inverted output allows the system designer to clock different
subsystems on opposite edges, without suffering from the
pulse asymmetry typical of non-ideal loading. This function
allows the two subsystems to each be clocked 180 degrees
out of phase, but still to be aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of
the system that need the clock to be divided by either two or
four, and still remain within a narrow skew of the “1X” clock.
Without this feature, an external divider would need to be
added, and the propagation delay of the divider would add to
the skew between the different clock signals.
These divided outputs, coupled with the Phase Locked Loop,
allow the LVPSCB to multiply the clock rate at the REF input
by either two or four. This mode will enable the designer to
distribute a low-frequency clock between various portions of
the system, and then locally multiply the clock rate to a more
suitable frequency, while still maintaining the low-skew charac-
teristics of the clock driver. The LVPSCB can perform all of the
functions described above at the same time. It can multiply by
Figure 4. Inverted Output Connections
Figure 5. Frequency Multiplier with Skew Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
20 MHz
20 MHz
40 MHz
80 MHz
Figure 6. Frequency Divider Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
20 MHz
5 MHz
10 MHz
20 MHz
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 6 of 14
two and four or divide by two (and four) at the same time that
it is shifting its outputs over a wide range or maintaining zero
skew between selected outputs.
Figure 8 shows the CY7C9915 connected in series to
construct a zero-skew clock distribution tree between boards.
Delays of the downstream clock buffers can be programmed
to compensate for the wire length (i.e., select negative skew
equal to the wire delay) necessary to connect them to the
master clock source, approximating a zero-delay clock tree.
Cascaded clock buffers will accumulate low-frequency jitter
because of the non-ideal filtering characteristics of the PLL
filter. It is recommended that not more than two clock buffers
be connected in series.
Figure 7. Multi-Function Clock Driver
Figure 8. Board-to-Board Clock Distribution
27.5-MHz
DISTRIBUTION
CLOCK
110-MHz
INVERTED
Z0
27.5-MHz
110-MHz
ZERO SKEW
110-MHz
SKEWED –2.273 ns (–4tU)
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF LOAD
LOAD
LOAD
LOAD
Z0
Z0
Z0
SYSTEM
CLOCK
Z0
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
FS
FB
LOAD
LOAD
LOAD
LOAD
LOAD
TEST
Z0
Z0
Z0
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 7 of 14
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VDD Supply Voltage Nonfunctional –0.5 4.6 VDC
VIN Input Voltage REF Relative to VCC –0.5 4.6 VDC
VIN Input Voltage Except REF Relative to VCC –0.5 VDD + 0.5 VDC
LUILatch-up Immunity Functional 300 mA
TSTemperature, Storage Nonfunctional –65 +125 °C
TATemperature, Operating Ambient Commercial Temperature 0 +70 °C
TATemperature, Operating Ambient Industrial Temperature –40 +85 °C
TJJunction Temperature Industrial Temperature 125 °C
ESDhESD Protection (Human Body Model) 2000 V
MSL Moisture Sensitivity Level MSL – 3 Class
UL–94 Flammability Rating @ 1/8 in. V–0 class
FIT Failure in Time Manufacturing test 10 ppm
TPU Power-up time for all VDDs to reach
minimum specified voltage (power ramps
must be monotonic)
0.05 500 ms
CIN Input Capacitance[4] TA = 25°C, f = 1 MHz, VCC = 3.3V – 10 pF
ZOUT Output Impedance Low to High (Rising edge) 27 Ω
High to Low (Falling edge) 7 Ω
Electrical Characteristics Over the Operating Range [5]
Parameter Description
CY7C9915
UnitTest Conditions Min. Max.
VCCQ Core Power Supply @3.3V ± 10% 2.97 3.63 V
VCCN[1:4] Output Buffer Power Supply @3.3V ± 10% 2.97 3.63 V
VOH Output HIGH Voltage VCC = Min., IOH = –20 mA 2.4 – V
VOL Output LOW Voltage VCC = Min., IOL = 36 mA – 0.45 V
VIH Input HIGH Voltage
(REF and FB inputs only)[6] 2.0 VCC V
VIL Input LOW Voltage
(REF and FB inputs only)[6] –0.5 0.8 V
VIHH Three-Level Input HIGH
Voltage (Test, FS, xFn)[7] Min. ≤ VCC ≤ Max. 0.87 * VCC V
CC V
VIMM Three-Level Input MID
Voltage (Test, FS, xFn)[7] Min. ≤ VCC ≤ Max. 0.47 * VCC 0.53 * VCC V
VILL Three-Level Input LOW
Voltage (Test, FS, xFn)[7] Min. ≤ VCC ≤ Max. 0.0 0.13 * VCC V
IIH Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max., VIN = Max. – 10 µA
Notes:
4. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
5. See the last page of this specification for Group A subgroup testing information.
6. VIH and VIL for FB inputs guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect this parameters.
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 8 of 14
IIL Input LOW Leakage Current
(REF and FB inputs only)
VCC = Max., VIN = 0.4V –10 – µA
IIHH Input HIGH Current
(Test, FS, xFn)
VIN = VCC –200µA
IIMM Input MID Current
(Test, FS, xFn)
VIN = VCC/2 – 50 50 µA
IILL Input LOW Current
(Test, FS, xFn)
VIN = GND – – 200 µA
IOS Short Circuit Current[8] VCC = MAX, VOUT = GND (25° only) – –200 mA
ICCQ Operating Current Used by
Internal Circuitry
VCCN = VCCQ = Max., All
Input Selects Open
Com’l – 90 mA
Industrial – 100 mA
ICCN Output Buffer Current per
Output Pair[9] VCCN = VCCQ = Max., IOUT = 0 mA
Input Selects Open, fMAX
–14mA
PD Power Dissipation per
Output Pair[10] VCCN = VCCQ = Max., IOUT = 0 mA
Input Selects Open, fMAX
–78mW
Electrical Characteristics Over the Operating Range (continued)[5]
Parameter Description
CY7C9915
UnitTest Conditions Min. Max.
AC Test Loads and Waveforms
AC Input Specifications
Parameter Description Condition Min. Max. Unit
TR,TFInput Rise/Fall Edge Rate 0.8V – 2.0V – 10 ns/V
TPWC Input Clock Pulse[11] HIGH or LOW 2 – ns
10 90 %
TDCIN Input Duty Cycle Test Mode 30 70 %
FREF Reference Input Frequency FS=LOW 3.75 30 MHz
FS=MID 6.25 50
FS=HIGH 10 150[12]
Notes:
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
8. CY7C9915 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7C9915:ICCN = [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F ∗ C
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the
load circuit:
PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1
See note 9 for variable definition.
11. The minimum input clock pulse (HIGH or LOW) is the greater of the two parameters. Therefore, below 50MHz the limit is 10%; above 50MHz the limit is 2ns.
12. In test mode, Max REF input frequency is 133MHz.
TTL AC Test Load TTL Input Test Waveform
VCC
R1
R2
CL
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns ≤1ns
2.0V
0.8V
Vth =1.5V
R1=100
R2=100
CL=30pF
(Includes fixture and probe capacitance)
[+] Feedback
PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 9 of 14
Switching Characteristics Over the Operating Range [2, 13]
Parameter Description
CY7C9915-1
Min. Typ. Max. Unit
fNOM Operating Clock
Frequency in MHz
FS = LOW[1, 2] 15 – 30 MHz
FS = MID[1, 2] 25 – 50
FS = HIGH[1, 2 ] 40 – 150
FOUT Output Frequency FS = LOW 3.75 – 30 MHz
FS = MID 6.25 – 50
FS = HIGH 10 – 150
FVCO VCO Frequency 160 – 650 MHz
FBW Loop Bandwidth – 1 – MHz
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 16] –0.050.1ns
tSKEW0 Zero Output Skew (All Outputs)[14, 17,18] –0.10.2ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[14, 19] –0.10.3ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 19] –0.30.5ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[14, 19] –0.250.5ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[14, 19] –0.250.5ns
tDEV Device-to-Device Skew[15, 20] – – 0.75 ns
tPD Propagation Delay, REF Rise to FB Rise –0.15 – +0.15 ns
tODC Output Duty Cycle[21] 47 50 53 %
tORISE Output Rise Time[22] 0.15 0.5 1.2 ns
tOFALL Output Fall Time[22] 0.15 0.5 1.2 ns
tLOCK PLL Lock Time[23] ––0.5ms
tJR Cycle-to-Cycle Output Jitter RMS, fNOM > 22MHz[15] ––15
ps
RMS, fNOM < 22MHz[15] ––30
Peak, fNOM > 22MHz[15] ––100
ps
Peak, fNOM < 22MHz[15] ––200
tPJ Period Jitter RMS, fNOM > 22MHz[15] ––25
ps
RMS, fNOM < 22MHz[15] ––50
Peak-to-Peak, fNOM >
22 MHz[15] ––150
ps
Peak-to-Peak, fNOM <
22 MHz[15] ––300
Notes:
13. Test measurement levels for the CY7C9915 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown
in the AC Test Loads and Waveforms unless otherwise specified.
14. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 30 pF and terminated with TTL AC Test Load.
15. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
16. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
17. tSKEW0 is defined as the skew between all outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
18. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
19. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
or Divide-by-4 mode).
20. tDEV is the output-to-output skew between the same outputs of any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
21. tODC is measure at VCCN/2.
22. Specified with outputs loaded with 30 pF. tORISE and tOFALL measured between 0.8V and 2.0V.
23. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 10 of 14
Switching Characteristics Over the Operating Range [2, 13]
Parameter Description
CY7C9915-2
Min. Typ. Max. Unit
fNOM Operating Clock
Frequency in MHz
FS = LOW[1, 2] 15 – 30 MHz
FS = MID[1, 2] 25 – 50
FS = HIGH[1, 2 ] 40 – 150
FOUT Output Frequency FS=LOW 3.75 – 30 MHz
FS=MID 6.25 – 50
FS=HIGH 10 – 150
FVCO VCO Frequency 160 – 650 MHz
FBW Loop Bandwidth – 1 – MHz
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 16] –0.050.2ns
tSKEW0 Zero Output Skew (All Outputs)[14, 17,18] – 0.1 0.25 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[14, 19] –0.10.5ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 19] –0.31.0ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[14, 19] –0.250.5ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[14, 19] –0.250.9ns
tDEV Device-to-Device Skew[15, 20] ––1.0ns
tPD Propagation Delay, REF Rise to FB Rise –0.25 – +0.25 ns
tODC Output Duty Cycle[21] 47 50 53 %
tORISE Output Rise Time[22, 22] 0.15 0.5 1.2 ns
tOFALL Output Fall Time[22, 22] 0.15 0.5 1.2 ns
tLOCK PLL Lock Time[23] ––0.5ms
tJR Cycle-to-Cycle Output Jitter RMS, fNOM > 22MHz[15] ––15
ps
RMS, fNOM < 22MHz[15] ––30
Peak, fNOM > 22MHz[15] ––100
ps
Peak, fNOM < 22MHz[15] ––200
tPJ Period Jitter RMS, fNOM > 22MHz[15] ––25
ps
RMS, fNOM < 22MHz[15] ––50
Peak-to-Peak, fNOM >
22 MHz[15] ––150
ps
Peak-to-Peak, fNOM <
22 MHz[15] ––300
Switching Characteristics Over the Operating Range [2, 13]
Parameter Description
CY7C9915-5
Min. Typ. Max. Unit
fNOM Operating Clock
Frequency in MHz
FS = LOW[1, 2] 15 – 30 MHz
FS = MID[1, 2] 25 – 50
FS = HIGH[1, 2 ] 40 – 150
FOUT Output Frequency FS=LOW 3.75 – 30 MHz
FS=MID 6.25 – 50
FS=HIGH 10 – 150
FVCO VCO Frequency 160 – 650 MHz
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PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 11 of 14
FBW Loop Bandwidth – 1 – MHz
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 16] – 0.05 0.25 ns
tSKEW0 Zero Output Skew (All Outputs)[14, 17,18] –0.10.5ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[14, 19] –0.10.7ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 19] –0.31.0ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[14, 19] –0.250.7ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[14, 19] –0.251.0ns
tDEV Device-to-Device Skew[15, 20] – – 1.25 ns
tPD Propagation Delay, REF Rise to FB Rise –0.5 – +0.5 ns
tODC Output Duty Cycle[21] 45 50 55 %
tORISE Output Rise Time[22, 22] 0.15 0.5 1.2 ns
tOFALL Output Fall Time[22, 22] 0.15 0.5 1.2 ns
tLOCK PLL Lock Time[23] ––0.5ms
tJR Cycle-to-Cycle Output Jitter RMS, fNOM > 22MHz[15] ––15
ps
RMS, fNOM < 22MHz[15] ––30
Peak, fNOM > 22MHz[15] ––100
ps
Peak, fNOM < 22MHz[15] ––200
tPJ Period Jitter RMS, fNOM > 22MHz[15] ––25
ps
RMS, fNOM < 22MHz[15] ––50
Peak-to-Peak, fNOM >
22MHz[15] ––150
ps
Peak-to-Peak, fNOM <
22MHz[15] ––300
Switching Characteristics Over the Operating Range (continued)[2, 13]
Parameter Description
CY7C9915-5
Min. Typ. Max. Unit
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PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 12 of 14
AC Timing Diagrams
Ordering Information
Ordering Code Package Type Operating Range
CY7C9915-1JXC 32-Lead PLCC Commercial, 0°C to 70°C
CY7C9915-1JXI 32-Lead PLCC Industrial, –40°C to 85°C
CY7C9915-2JXC 32-Lead PLCC Commercial, 0°C to 70°C
CY7C9915-2JXI 32-Lead PLCC Industrial, –40°C to 85°C
CY7C9915-5JXC 32-Lead PLCC Commercial, 0°C to 70°C
CY7C9915-5JXI 32-Lead PLCC Industrial, –40°C to 85°C
tODC
tODC
tREF
REF
FB
Q
OTHER Q
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
tPWC
tPWC
tPD
tSKEWPR,
tSKEW0,1
tSKEWPR,
tSKEW0,1
tSKEW2
tSKEW2
tSKEW3,4
tSKEW3,4tSKEW3,4
tSKEW1,3, 4tSKEW2,4
tJR
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PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 13 of 14
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Drawing and Dimensions
All product and company names mentioned in this document are trademarks of their respective holders.
32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B
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PRELIMINARY CY7C9915
Document #: 38-07687 Rev. *A Page 14 of 14
Document History Page
Document Title: CY7C9915 3.3V Programmable Skew Clock Buffer
Document Number: 38-07687
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 236268 See ECN RGL New Data Sheet
*A 357435 See ECN RGL Clarified minimum input pulse width and tDEV
.
Added two slower speed grades (-2 and -5).
Switching Characteristics (-1 speed grade): tightened tSKEW4, tORISE and
tOFALL typ. values and max. limits; relaxed tODC; relaxed tJR and tPJ below
22 MHz; eliminated phase jitter spec.
Corrected AC Timing Diagrams.
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