2009-2018 Microchip Technology Inc. DS20001711K-page 1
24AA01/24LC01B/24FC01
Device Selection Table
Features
• Single Supply with Operation down to 1.7V for
24AAXX and 24FCXX Devices, 2.5V for 24LCXX
Devices
• Low-Power CMOS Technology:
- Read current 1 mA, maximum
- Standby current 1 µA, maximum (I-temp.)
• 2-Wire Serial Interface, I2C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, Maximum
• Self-Timed Erase/Write Cycle
• 8-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified
Packages:
• 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP, 8-Lead
SOIC, 8-Lead TDFN, 8-Lead TSSOP, 8-Lead
UDFN, 5-Lead SOT-23 and 5-Lead SC-70
Description
The Microchip Technology Inc. 24XX01(1) is a 1 Kbit
Electrically Erasable PROM. The device is organized
as one block of 128 x 8-bit memory with a 2-wire serial
interface. Its low-voltage design permits operation
down to 1.7V with standby and active currents of only
1 µA and 1 mA, respectively. The 24XX01 also has a
page write capability for up to 8 bytes of data.
Package Types
Part Number VCC Range Max. Clock Frequency Temp. Ranges Available Packages
24AA01 1.7V-5.5V 400 kHz(1)I P, SN, MS, ST, MC, LT, MNY, OT
24LC01B 2.5V-5.5V 400 kHz I, E P, SN, MS, ST, MC, LT, MNY, OT
24FC01 1.7V-5.5V 1 MHz I, E P, SN, MS, ST, MUY, OT
Note 1: 100 kHz for VCC <2.5V
Note 1: 24XX01 is used in this document as a
generic part number for the
24AA01/24LC01B/24FC01 devices.
SOIC, TSSOP
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
DFN/TDFN/UDFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
SOT-23/SC-70
SCL
Vss
SDA
WP
Vcc
Note 1: Pins A0, A1 and A2 are not used by the
24XX01 (no internal connections).
(Top View)
(Top View)
1
2
3
4
8
7
6
5
(Top View)
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP
(Top View)
15
4
3
2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1K I2C Serial EEPROM
24AA01/24LC01B/24FC01
DS20001711K-page 2 2009-2018 Microchip Technology Inc.
Block Diagram
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
V
CC
V
SS
R/W Control
2009-2018 Microchip Technology Inc. DS20001711K-page 3
24AA01/24LC01B/24FC01
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC01B)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC01)
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
D1 VIH High-Level Input Voltage 0.7 VCC —— V
D2 VIL Low-Level Input Voltage — — 0.3 VCC V
D3 VHYS Hysteresis of Schmitt
Trigger Inputs
0.05 VCC —— V(Note)
D4 VOL Low-Level Output
Voltage
— — 0.40 V IOL =3.0mA, VCC =2.5V
D5 ILI Input Leakage Current — — ±1 µA VIN =VSS or VCC
D6 ILO Output Leakage Current — — ±1 µA VOUT =VSS or VCC
D7 CIN,
COUT
Pin Capacitance
(all inputs/outputs)
— — 10 pF VCC = 5.0V (Note)
TA = 25°C, FCLK =1MHz
D8 ICCWRITE Operating Current — — 3 mA VCC = 5.5V, SCL = 400 kHz
D9 ICCREAD —— 1mAVCC = 5.5V, SCL = 400 kHz
D10 ICCS Standby Current — — 1 µA SDA = SCL = VCC
WP = VSS, I-Temp.
— — 3 µA SDA = SCL = VDD
WP = VSS, E-Temp. (24FC01)
— — 5 µA SDA = SCL = VCC
WP = VSS, E-Temp. (24LC01B)
Note: This parameter is periodically sampled and not 100% tested.
24AA01/24LC01B/24FC01
DS20001711K-page 4 2009-2018 Microchip Technology Inc.
TABLE 1-2 AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC01B)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC01)
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
1F
CLK Clock Frequency — — 400 kHz 2.5V ≤ VCC ≤ 5.5V
— — 100 kHz 1.7V ≤ VCC < 2.5V (24AA01)
— — 1000 kHz 1.7V ≤ VCC ≤ 5.5V (24FC01)
2THIGH Clock High Time 600 — — ns 2.5V ≤ VCC ≤ 5.5V
4000 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
260 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
3TLOW Clock Low Time 1300 — — ns 2.5V ≤ VCC ≤ 5.5V
4700 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
500 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
4TRSDA and SCL Rise Time — — 300 ns 2.5V ≤ VCC ≤ 5.5V (Note 1)
— — 1000 ns 1.7V ≤ VCC < 2.5V (24AA01)
(Note 1)
— — 1000 ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
(Note 1)
5T
FSDA and SCL Fall Time — — 300 ns (Note 1)
6THD:STA Start Condition Hold Time 600 — — ns 2.5V ≤ VCC ≤ 5.5V
4000 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
250 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
7TSU:STA Start Condition Setup
Time
600 — — ns 2.5V ≤ VCC ≤ 5.5V
4700 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
250 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
8THD:DAT Data Input Hold Time 0 — — ns (Note 2)
9T
SU:DAT Data Input Setup Time 100 — — ns 2.5V ≤ VCC ≤ 5.5V
250 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
50 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
10 TSU:STO Stop Condition Setup
Time
600 — — ns 2.5V ≤ VCC ≤ 5.5V
4000 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
250 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
11 TSU:WP WP Setup Time 0 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
12 THD:WP WP Hold Time 1000 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
13 TAA Output Valid from Clock — — 900 ns 2.5V ≤ VCC ≤ 5.5V (Note 2)
— — 3500 ns 1.7V ≤ VCC < 2.5V (24AA01)
(Note 2)
——450ns1.7V ≤ VCC ≤ 5.5V (24FC01)
(Note 2)
Note 1: Characterized but not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: CB = total capacitance of one bus line in pF.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at
www.microchip.com.
2009-2018 Microchip Technology Inc. DS20001711K-page 5
24AA01/24LC01B/24FC01
FIGURE 1-1: BUS TIMING DATA
14 TBUF Bus Free Time: The time
the bus must be free
before a new transmis-
sion can start
1300 — — ns 2.5V ≤ VCC ≤ 5.5V
4700 — — ns 1.7V ≤ VCC < 2.5V (24AA01)
500 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01)
15 TOF Output Fall Time from VIH
Minimum to VIL Maximum
20+0.1CB— 250 ns 2.5V ≤ VCC ≤ 5.5V (24LC01B)
(Notes 1 and 3)
— — 250 ns 1.7V ≤ VCC < 2.5V (24AA01)
(Note 1)
16 TSP Input Filter Spike
Suppression
(SDA and SCL pins)
— — 50 ns (Note 1)
17 TWC Write Cycle Time
(byte or page)
——5 ms
18 Endurance 1,000,000 — — cycles 25°C, 5.5V, Page Mode (Note 4)
Note 1: Characterized but not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: CB = total capacitance of one bus line in pF.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at
www.microchip.com.
TABLE 1-2 AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS (Continued)
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC01B)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC01)
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D3 4
10
11 12
14
24AA01/24LC01B/24FC01
DS20001711K-page 6 2009-2018 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX01.
They may be left floating or tied to either VSS or VCC.
2.2 Serial Address/Data Input/Output
(SDA)
The SDA input is a bidirectional pin used to transfer
addresses and data into and out of the device. Since
it is an open-drain terminal, the SDA bus requires a
pull-up resistor to VCC (typical 10 kΩ for 100 kHz,
2kΩ for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 00-7F).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
Name DFN MSOP PDIP SC-70 SOIC SOT-23 TDFN TSSOP UDFN Description
A0 1 1 1 — 1 — 1 1 1 Not Connected
A1 2 2 2 — 2 — 2 2 2 Not Connected
A2 3 3 3 — 3 — 3 3 3 Not Connected
VSS 4 4 4 2 4 2 4 4 4 Ground
SDA 5 5 5 3 5 3 5 5 5 Serial Address/Data I/O
SCL 6 6 6 1 6 1 6 6 6 Serial Clock
WP 7 7 7 5 7 5 7 7 7 Write-Protect Input
VCC 8 8 8 4 8 4 8 8 8 Power Supply
2009-2018 Microchip Technology Inc. DS20001711K-page 7
24AA01/24LC01B/24FC01
3.0 FUNCTIONAL DESCRIPTION
The 24XX01 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while defining a
device receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX01 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last eight will
be stored when doing a write operation). When an
overwrite does occur, it will replace data based on the
first-in first-out (FIFO) principle.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge-related clock pulse.
Moreover, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX01) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX01 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
24AA01/24LC01B/24FC01
DS20001711K-page 8 2009-2018 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a four-bit control code. For the 24XX01, this
is set as ‘1010’ binary for read and write operations.
The next three bits of the control byte are “don’t cares”
for the 24XX01. The combination of the 4-bit control
code and the next three bits are called the slave
address.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to ‘1’, a read operation is selected. When set to ‘0’,
a write operation is selected. Following the Start
condition, the 24XX01 monitors the SDA bus, checking
the device type identifier being transmitted. Upon
receiving a valid slave address and the R/W bit, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX01 will select a read or write operation.
The next byte received defines the address of the first
data byte within the selected block (Figure 5-2).
Because only A6…A0 are used, the upper address bit
is a “don’t care”.
FIGURE 5-1: CONTROL BYTE
ALLOCATION
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
Operation Control
Code Block Select R/W
Read 1010 Block Address 1
Write 1010 Block Address 0
10 10xxx
R/W ACK
Start Bit
Read/Write Bit
x = “don’t care”
S
Slave Address
Acknowledge Bit
Control Code
Block
Select
Bits
1 010xxR/W A
6
A
0
•••• •
Control Byte Word Address Byte
Control
Code
Block
Select
bits
x = “don’t care”
xx
2009-2018 Microchip Technology Inc. DS20001711K-page 9
24AA01/24LC01B/24FC01
6.0 WRITE OPERATION
6.1 Byte Write
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits, “don’t
cares”) and the R/W bit, which is a logic-low, is placed
onto the bus by the master transmitter. This indicates to
the addressed slave receiver that a byte with a word
address will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
Pointer of the 24XX01. After receiving another
Acknowledge signal from the 24XX01, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX01
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and,
during this time, the 24XX01 will not generate
Acknowledge signals (Figure 6-1).
6.2 Page Write
The write control byte, word address and first data byte
are transmitted to the 24XX01 in the same way as in a
byte write. However, instead of generating a Stop
condition, the master transmits up to 8 data bytes to the
24XX01, which are temporarily stored in the on-chip
page buffer and will be written into the memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the three lower-order Address
Pointer bits, which form the byte counter, are internally
incremented by one. The higher-order five bits of the
word address remain constant. If the master should
transmit more than eight words prior to generating the
Stop condition, the Address Pointer will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received, an internal write cycle will begin (Figure 6-2).
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (00-7F) when the pin is tied to VCC. If tied to VSS,
the write protection is disabled.
FIGURE 6-1: BYTE WRITE
Note: Page write operations are limited to writ-
ing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address Data
A
C
K
A
C
K
A
C
K
1010xxx0
x = “don’t care”
Block
Select
Bits
24AA01/24LC01B/24FC01
DS20001711K-page 10 2009-2018 Microchip Technology Inc.
FIGURE 6-2: PAGE WRITE
S P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Word
Address (n) Data (n) Data (n + 7)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
x = “don’t care”
10 10 xxx0
Block
Select
Bits
2009-2018 Microchip Technology Inc. DS20001711K-page 11
24AA01/24LC01B/24FC01
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle. ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a write command (R/W =0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next read or write
operation. See Figure 7-1 for a flow diagram of this
operation.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA01/24LC01B/24FC01
DS20001711K-page 12 2009-2018 Microchip Technology Inc.
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX01 contains an Address Pointer that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the previ-
ous access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24XX01
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XX01
discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX01 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX01 will then issue an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX01 discontinues transmission (Figure 8-2).
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX01 transmits
the first data byte, the master issues an acknowledge
(as opposed to a Stop condition in a random read). This
directs the 24XX01 to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24XX01 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4 Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
FIGURE 8-1: CURRENT ADDRESS READ
SP
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte Data (n)
A
C
K
N
o
A
C
K
S
T
A
R
T
Block
Select
Bits
x = “don’t care”
1010
xxx1
2009-2018 Microchip Technology Inc. DS20001711K-page 13
24AA01/24LC01B/24FC01
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
S P
S
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address (n)
Control
Byte
S
T
A
R
T
Data (n)
A
C
K
A
C
K
N
o
A
C
K
x = “don’t care”
10 10 xxx01010xxx 1
Block
Select
Bits
Block
Select
Bits
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte
A
C
K
N
o
A
C
K
Data (n) Data (n + 1) Data (n + 2) Data (n + x)
A
C
K
A
C
K
A
C
K
1
24AA01/24LC01B/24FC01
DS20001711K-page 14 2009-2018 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information*
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example
8-Lead SOIC (3.90 mm)
XXXXXXXX
XXXXYYWW
NNN
24LC01B
I/P 13F
1742
3
e
8-Lead 2x3 DFN Example
XXX
YWW
NN
214
742
13
8-Lead MSOP Example
4L1BI
74213F
XXXXXX
YWWNNN
5-Lead SC-70 Example
XXNN B13F
Example
13F
24LC01BI
SN 1742
3
e
2009-2018 Microchip Technology Inc. DS20001711K-page 15
24AA01/24LC01B/24FC01
Part Number
1st Line Marking Codes
TSSOP MSOP UDFN
SOT-23 DFN TDFN SC-70
I-Temp E-Temp I-Temp E-Temp I-Temp E-Temp I-Temp E-Temp
24AA01 4A01 4A01T(1)—B1NN
(2,3)— 211 — A11 — B2NN(2)—
24LC01B 4L1B 4L1BT(1)—M1NN
(2,3)N1NN(2,3)214 215 A14 A15 B1NN(2)B3NN(2)
24FC01 AADP 24FC01 CAP AAEUYY(4)AAEUYY(4)———— — —
Note 1: T = Temperature grade (I, E)
2: NN = Alphanumeric traceability code
3: These parts use the 1-line SOT-23 marking format
4: These parts use the 2-line SOT-23 marking format
8-Lead TSSOP Example
XXXX
TYWW
NNN
4L1B
I742
13F
8-Lead 2x3 TDFN Example
XXX
YWW
NN
A14
742
13
8-Lead 2x3 UDFN Example
XXX
YWW
NN
CAP
742
13
5-Lead SOT-23 (1-Line Marking)
XXNN
Example
2K3F
5-Lead SOT-23 (2-Line Marking)
XXXXY
Example
AAEU18
WWNNN 4213F
24AA01/24LC01B/24FC01
DS20001711K-page 16 2009-2018 Microchip Technology Inc.
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code,
and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2009-2018 Microchip Technology Inc. DS20001711K-page 17
24AA01/24LC01B/24FC01
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D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &&
24AA01/24LC01B/24FC01
DS20001711K-page 18 2009-2018 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2018 Microchip Technology Inc. DS20001711K-page 19
24AA01/24LC01B/24FC01
24AA01/24LC01B/24FC01
DS20001711K-page 20 2009-2018 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2018 Microchip Technology Inc. DS20001711K-page 21
24AA01/24LC01B/24FC01
24AA01/24LC01B/24FC01
DS20001711K-page 22 2009-2018 Microchip Technology Inc.
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
2009-2018 Microchip Technology Inc. DS20001711K-page 23
24AA01/24LC01B/24FC01
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
24AA01/24LC01B/24FC01
DS20001711K-page 24 2009-2018 Microchip Technology Inc.
0.15 C
0.15 C
0.10 C A B
C
SEATING
PLANE
13
4
2X
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-061D Sheet 1 of 2
2X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
5-Lead Plastic Small Outline Transistor (LT) [SC70]
D
EE1
e
e
5X b
0.30 C
5X TIPS
END VIEW
B
A
N
A
A1
A2
L
c
NOTE 1
2009-2018 Microchip Technology Inc. DS20001711K-page 25
24AA01/24LC01B/24FC01
Microchip Technology Drawing C04-061D Sheet 2 of 2
Number of Pins
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width
Molded Package Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E1
A2
e
L
E
N
0.65 BSC
0.10
0.15
0.80
0.00
-
0.20
1.25 BSC
-
-
2.10 BSC
MILLIMETERS
MIN NOM
5
0.46
0.40
1.10
0.10
MAX
c-0.08 0.26
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Lead Thickness
5-Lead Plastic Small Outline Transistor (LT) [SC70]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Overall Length
Exposed Pad Length
D
D2 2.50
2.00 BSC
2.60 2.70
0.80 - 1.00
1.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
24AA01/24LC01B/24FC01
DS20001711K-page 26 2009-2018 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2061B
5-Lead Plastic Small Outline Transistor (LT) [SC70]
12
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pad Width
Contact Pitch
X
MILLIMETERS
0.65 BSC
MIN
E
MAX
Distance Between Pads
Contact Pad Length
G
Y0.95
GxDistance Between Pads 0.20
NOM
0.45
2.20
1.25
X
Y
E
C
Gx
G
3
45
SILK SCREEN
2009-2018 Microchip Technology Inc. DS20001711K-page 27
24AA01/24LC01B/24FC01
0.25 CA–B D
C
SEATING
PLANE
TOP VIEW
SIDE VIEW
VIEW A–A
0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
12
N
h
h
A1
A2
A
A
B
e
D
E
E
2
E1
2
E1
NOTE 5
NOTE 5
NX b
0.10 CA–B
2X
H0.23
(L1)
L
R0.13
R0.13
VIEW C
SEE VIEW C
NOTE 1
D
24AA01/24LC01B/24FC01
DS20001711K-page 28 2009-2018 Microchip Technology Inc.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-5°
Mold Draft Angle Bottom
15°-5°
Mold Draft Angle Top
0.51-0.31
b
Lead Width
0.25-0.17
c
Lead Thickness
1.27-0.40LFoot Length
0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
8NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
protrusions shall not exceed 0.15mm per side.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
§
Footprint L1 1.04 REF
5. Datums A & B to be determined at Datum H.
2009-2018 Microchip Technology Inc. DS20001711K-page 29
24AA01/24LC01B/24FC01
RECOMMENDED LAND PATTERN
Microchip Technology Drawing C04-2057-SN Rev B
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
5.40
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
1.55
0.60
NOM
E
X1
C
Y1
SILK SCREEN
24AA01/24LC01B/24FC01
DS20001711K-page 30 2009-2018 Microchip Technology Inc.
0.15 C D
2X
NOTE 1 12
N
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 of
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.20 C
C
SEATING PLANE
AA2
A1
e
NX bB
0.20 C A-B D
e1
D
E1
E1/2
E/2
E
D
A
0.20 C2X
(DATUM D)
(DATUM A-B)
A
A
SEE SHEET 2
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
2009-2018 Microchip Technology Inc. DS20001711K-page 31
24AA01/24LC01B/24FC01
Microchip Technology Drawing C04-091D [OT] Sheet 2 of
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
c
L
L1
T
VIEW A-A
SHEET 1
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
protrusions shall not exceed 0.25mm per side.
1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
Foot Angle
Number of Pins
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Lead Width
Notes:
L1
I
b
c
Dimension Limits
E
E1
D
L
e1
A
A2
A1
Units
N
e
0°
0.08
0.20 -
-
-
10°
0.26
0.51
MILLIMETERS
0.95 BSC
1.90 BSC
0.30
0.90
0.89
-
0.60 REF
2.90 BSC
-
2.80 BSC
1.60 BSC
-
-
-
MIN
6
NOM
1.45
1.30
0.15
0.60
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M
24AA01/24LC01B/24FC01
DS20001711K-page 32 2009-2018 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2091A [OT]
Dimension Limits
Contact Pad Length (X5)
Overall Width
Distance Between Pads
Contact Pad Width (X5)
Contact Pitch
Contact Pad Spacing
3.90
1.10
G
Z
Y
1.70
0.60
MAXMIN
C
X
E
Units
NOM
0.95 BSC
2.80
MILLIMETERS
Distance Between Pads GX 0.35
1
5
X
Y
ZC
E
GX
G
2
SILK SCREEN
2009-2018 Microchip Technology Inc. DS20001711K-page 33
24AA01/24LC01B/24FC01
B
A
0.15 C
0.15 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
12
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
12
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2
2X
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
D
E
D2
E2
A
(A3)
A1
e
8X b
L
K
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
24AA01/24LC01B/24FC01
DS20001711K-page 34 2009-2018 Microchip Technology Inc.
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOM
MILLIMETERS
0.50 BSC
2.00 BSC
3.00 BSC
0.20 REF
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Contact-to-Exposed Pad
Contact Thickness
Exposed Pad Width
Exposed Pad Length
4. Dimensioning and tolerancing per ASME Y14.5M
3. Package is saw singulated
2. Package may have one or more exposed tie bars at ends.
Notes:
Contact Width
Overall Width
Overall Length
Contact Length
Standoff
Number of Pins
Overall Height
Pitch
K0.20
Units
N
e
A
Dimension Limits
D
A3
A1
b
D2
E2
E
L
0.20
1.35
1.25
0.25
0.00
0.70
MIN
--
0.25
0.30
1.30
1.40
1.35
0.30
0.45
1.45
8
0.75
0.02 0.05
0.80
MAX
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
2009-2018 Microchip Technology Inc. DS20001711K-page 35
24AA01/24LC01B/24FC01
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
1.50
1.60
MILLIMETERS
0.50 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
0.85
0.25
Microchip Technology Drawing No. C04-129-MNY Rev. B
NOM
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
12
8
CContact Pad Spacing 2.90
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C
E
X1
Y1
Y2
X2
EV
EV
ØV
SILK SCREEN
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
24AA01/24LC01B/24FC01
DS20001711K-page 36 2009-2018 Microchip Technology Inc.
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0ROGHG3DFNDJH:LGWK (   
0ROGHG3DFNDJH/HQJWK '   
)RRW/HQJWK /   
)RRWSULQW / 5()
)RRW$QJOH  ± 
/HDG7KLFNQHVV F  ± 
/HDG:LGWK E  ± 
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
2009-2018 Microchip Technology Inc. DS20001711K-page 37
24AA01/24LC01B/24FC01
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA01/24LC01B/24FC01
DS20001711K-page 38 2009-2018 Microchip Technology Inc.
B
A
0.10 C
0.10 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
12
N
2X
TOP VIEW
SIDE VIEW
NOTE 1
12
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2
2X
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
D
E
D2
E2 K
L8X b
e
e
2
0.10 C A B
0.05 C
A
(A3)
A1
BOTTOM VIEW
2009-2018 Microchip Technology Inc. DS20001711K-page 39
24AA01/24LC01B/24FC01
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E2
A3
e
L
E
N
0.50 BSC
0.152 REF
1.20
0.35
0.18
0.50
0.00
0.25
0.40
1.30
0.55
0.02
3.00 BSC
MILLIMETERS
MIN NOM
8
1.40
0.45
0.30
0.60
0.05
MAX
K-0.20 -Terminal-to-Exposed-Pad
Overall Length
Exposed Pad Length
D
D2 1.40
2.00 BSC
1.50 1.60
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
24AA01/24LC01B/24FC01
DS20001711K-page 40 2009-2018 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
1.40
1.60
MILLIMETERS
0.50 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
0.85
0.30
NOM
12
8
CContact Pad Spacing 2.90
Contact Pad to Center Pad (X8) G1 0.20
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-21355-Q4B Rev A
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
X2
Y2
Y1
SILK SCREEN X1
E
C
EV
G2
G1
ØV
Contact Pad to Contact Pad (X6) G2 0.33
2009-2018 Microchip Technology Inc. DS20001711K-page 41
24AA01/24LC01B/24FC01
APPENDIX A: REVISION HISTORY
Revision K (11/2018)
Added the 24FC01 device.
Revision J (01/2009)
Added TDFN Package; Updated Package Drawings.
Revision H (08/2008)
Added SC-70 Package; Updated Package Drawings.
Revision G (03/2007)
Replaced Package Drawings (Rev. AM).
Revision F (01/2007)
Revised Device Selection Table; Revised Features
Section; Changed 1.8V to 1.7V; Revised Table 1-1,
1-2, 8-1; Replaced Package Drawings; Revised
Product ID System.
Revision E
Revised Figure 3-2 Control Byte Allocation; Figure 4-1
Byte Write; Figure 4-2 Page Write; Section 6.0 Write
Protection; Figure 7-1 Current Address Read; Figure
7-2 Random Read; Figure 7-3 Sequential Read.
Revision D
Added DFN package.
Revision C
Corrections to Section 1.0, Electrical Characteristics
and Section 9.1, 24LC01B standard marking code.
2018 Microchip Technology Inc. DS20001711K-page 1
24AA01/24LC01B/24FC01
THE MICROCHIP WEBSITE
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
DEVICE FAMILY
DS20001711K-page 2 2018 Microchip Technology Inc.
NOTES:
2009-2018 Microchip Technology Inc. DS20001711K-page 43
24AA01/24LC01B/24FC01
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: 24AA01: = 1.7V, 1 Kbit I2C Serial EEPROM
24LC01B: = 2.5V, 1 Kbit I2C Serial EEPROM
24FC01: = 1.7V, High Speed, 1 Kbit I2C Serial EEPROM
Tape and
Reel Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range:
I = -40°C to +85°C (Industrial)
E = -40°C to +125°C (Extended)
Package: MC = Plastic Dual Flat, No Lead Package – 2x3x0.9mm,
Body, 8-lead (DFN)
MS = Plastic Micro Small Outline Package, 8-lead (MSOP)
P = Plastic Dual In-Line – 300 mil Body, 8-lead (PDIP)
LT = Plastic Small Outline Transistor, 5-lead (SC-70)
(Tape and Reel only)
SN = Plastic Small Outline - Narrow, 3.90 mm Body,
8-lead (SOIC)
OT = Plastic Small Outline Transistor, 5-lead (SOT-23)
(Tape and Reel only)
MNY = Plastic Dual Flat, No Lead Package - 2x3x0.8 mm
Body, 8-lead (TDFN)
ST = Plastic Thin Shrink Small Outline – 4.4 mm, 8-lead
(TSSOP)
MUY = Plastic Dual Flat, No Lead Package - 2x3x0.6 mm
Body, 8-lead (UDFN)
Examples:
a) 24LC01BT-E/MC: Tape and Reel, Extended
Temperature, 2.5V, DFN package.
b) 24LC01BT-I/MS: Tape and Reel, Industrial
Temperature, 2.5V, MSOP package.
c) 24AA01-I/P: Industrial Temperature, 1.7V,
PDIP package.
d) 24LC01BT-I/LT: Tape and Reel, Industrial
Temperature, 2.5V, SC-70 package.
e) 24AA01-I/SN: Industrial Temperature,
1.7V, SOIC package.
f) 24AA01T-I/OT: Tape and Reel, Industrial
Temperature, 1.7V, SOT-23 package.
g) 24AA01T-I/MNY: Tape and Reel, Industrial
Temperature, 1.7V, TDFN package.
h) 24AA01T-I/ST: Tape and Reel, Industrial
Temperature, 1.7V, TSSOP package.
i) 24FC01-I/P: Industrial Temperature, 1.7V,
PDIP package.
j) 24FC01T-I/MUY: Tape and Reel, Industrial
Temperature, 1.7V, UDFN package.
PART NO. –X /XX
PackageTemperature
Range
Device
[X](1)
Tape and Reel
Option
Note 1: Tape and Reel identifier only
appears in the catalog part number
description. This identifier is used
for ordering purposes and is not
printed on the device package.
Check with your Microchip Sales
Office for package availability with
the Tape and Reel option.
2: Contact Microchip for Automotive
grade ordering part numbers.
24AA01/24LC01B/24FC01
DS20001711K-page 44 2009-2018 Microchip Technology Inc.
NOTES:
2018 Microchip Technology Inc. DS20001711K-page 45
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3881-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20001711K-page 46
AMERICAS
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2018 Microchip Technology Inc.
08/15/18