PIC18F4455-I/PREL - Microchip Technology

PIC18F2455/2550/4455/4550

Data Sheet

28/40/44-Pin, High Performance,

Enhanced Flash, USB Microcontrollers

with nanoWatt Technology

Information contained in this publication regarding device

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and may be supers eded by updates. It is y our res po nsibilit y to

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Trademarks

The Microchip name and logo, the Microchip logo, Accur on,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MX DEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h a c t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

PIC18F2455/2550/4455/4550

Universal Seri al Bus Features:

• USB V2.0 Compliant

• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)

• Suppo rts Control , Interr upt, Is ochro nous and Bu lk

Transfers

• Supports up to 32 Endpoints (16 bidirectional)

• 1-Kbyte Dual Access RAM for USB

• On-Chip USB Transceiver with On-Chip Voltage

Regulator

• Interface for Off-Chip USB Transceiver

• Streaming Parallel Port (SPP) for USB streaming

transfers (40/44-pin devices only)

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 μA typical

• Sleep mode currents down to 0.1 μA typical

• Timer1 Oscillator: 1.1 μA typical, 32 kHz , 2V

• Watchdog Timer: 2.1 μA typical

• Two-Speed Os ci llator Start-up

Flexible Oscil lator Struc ture:

• Four Cry stal mo des, incl uding High Prec ision PLL

for USB

• Two External Clock modes, up to 48 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies, from 31 kHz

to 8 MHz

- User-tunable to com pe ns ate for frequ enc y drif t

• Secondary Oscillator using Timer1 @ 32 kHz

• Dual Oscillator options allow microcontroller and

USB module to run at different clock speeds

• Fail-Safe Clock Monitor:

- Allows for s afe shutdown if any clock stops

Peripheral Highl ight s:

• High-Cur rent Sink /So urc e: 25 mA/25 mA

• Three Externa l Interru pt s

• Four Timer modules (Timer0 to Timer3)

• Up to 2 Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)

- Compare is 16-bit, max. resolution 83.3 ns (TCY)

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- Multiple output modes

- Selectab le pol ari t y

- Programmable dead time

- Auto-shutdown and auto-restart

• Enhanced USART module:

- LIN bus support

• Master Synchronous Serial Port (MSSP) module

supporting 3-wire SPI (all 4 modes) and I2C™

Master and Slav e mod es

• 10-bit, up to 13-channel Analog-to-Digital Conv erter

module (A/D) with Programmable Acquisition Time

• Dual Analog Comparators with Input Multiplexing

Special Microcontroller Features:

• C Compiler Optimized Architecture with optional

Extended Instruction Set

• 100,000 Erase/Write Cycle Enhanced Flash

Program Memory typical

• 1,000,000 Erase/Write Cycle Data EEPROM

Memory typical

• Flash/Data EEPROM Retention: > 40 years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Ti mer (WDT):

- Programmable period from 41 ms to 131s

• Programmable Code Protection

• Single -Supply 5V In -Circuit Serial

Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Optional dedicated ICD/ICSP port (44-pin devices only)

• Wide Operating Voltage Range (2.0V to 5.5V)

Device

Progra m Memory Dat a Memory

I/O 10-Bit

A/D (ch) CCP/ECCP

(PWM) SPP

MSSP

EAUSART

Comparators

Timers

8/16-Bit

Flash

(bytes) # Single-Word

Instructions SRAM

(bytes) EEPROM

(bytes) SPI Master

I2C™

PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3

PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3

PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

28/40/44-Pin, High-Performance, Enhanced Flash,

USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550

Pin Diagrams

40-Pin PDIP

PIC18F2455

28-Pin PDIP, SOIC

PIC18F2550

14 15

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS/HLVDIN/C2OUT

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(1)/UOE

RC2/CCP1

VUSB

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0

RB3/AN9/CCP2(1)/VPO

RB2/AN8/INT2/VMO

RB1/AN10/INT1/SCK/SCL

RB0/AN12/INT0/FLT0/SDI/SDA

VDD

VSS

RC7/RX/DT/SDO

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0/CSSPP

RB3/AN9/CCP2(1)/VPO

RB2/AN8/INT2/VMO

RB1/AN10/INT1/SCK/SCL

RB0/AN12/INT0/FLT0/SDI/SDA

VDD

VSS

RD7/SPP7/P1D

RD6/SPP6/P1C

RD5/SPP5/P1B

RD4/SPP4

RC7/RX/DT/SDO

RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

RD2/SPP2

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS/HLVDIN/C2OUT

RE0/AN5/CK1SPP

RE1/AN6/CK2SPP

RE2/AN7/OESPP

VDD

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(1)/UOE

RC2/CCP1/P1A

VUSB

RD0/SPP0

RD1/SPP1

PIC18F4455

PIC18F4550

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

PIC18F2455/2550/4455/4550

Pin Diagrams (Continued)

PIC18F4455

44-Pin TQFP

44-Pin QFN

PIC18F4455

PIC18F4550

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

NC/ICCK(2)/ICPGC(2)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0/CSSPP

NC/ICDT(2)/ICPGD(2) RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

RD2/SPP2

RD1/SPP1

RD0/SPP0

VUSB

RC2/CCP1/P1A

RC1/T1OSI/CCP2(1)/UOE

NC/ICPORTS(2)

NC/ICRST(2)/ICVPP(2)

RC0/T1OSO/T13CKI

OSC2/CLKO/RA6

OSC1/CLKI

VSS

VDD

RE2/AN7/OESPP

RE1/AN6/CK2SPP

RE0/AN5/CK1SPP

RA5/AN4/SS/HLVDIN/C2OUT

RA4/T0CKI/C1OUT/RCV

RC7/RX/DT/SDO

RD4/SPP4

RD5/SPP5/P1B

RD6/SPP6/P1C

VSS

VDD

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2(1)/VPO

RD7/SPP7/P1D 5

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/AN11/KBI0/CSSPP

NC RC6/TX/CK

RC5/D+/VP

RC4/D-/VM

RD3/SPP3

RD2/SPP2

RD1/SPP1

RD0/SPP0

VUSB

RC2/CCP1/P1A

RC1/T1OSI/CCP2(1)/UOE

RC0/T1OSO/T13CKI

OSC2/CLKO/RA6

OSC1/CLKI

VSS

VDD

RE2/AN7/OESPP

RE1/AN6/CK2SPP

RE0/AN5/CK1SPP

RA5/AN4/SS/HLVDIN/C2OUT

RA4/T0CKI/C1OUT/RCV

RC7/RX/DT/SDO

RD4/SPP4

RD5/SPP5/P1B

RD6/SPP6/P1C

VSS

VDD

RB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2(1)/VPO

RD7/SPP7/P1D 5

4VSS

VDD

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: Special ICPORTS features available in select circumstances. See Section 25.9 “Special ICPORT Features (Designated

Packages Only)” for more infor ma ti on .

PIC18F2455/2550/4455/4550
DS39632D-page 4 Preliminary © 2007 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes .......... .. .... ....... .. .... .. .. .... ....... .. .. .... .. .... ..... .... .. .... .. .. ....... .... .. .... .. .. ....... .................................................... 35
4.0 Reset.......................................................................................................................................................................................... 43
5.0 Memory O rganization................................................................................................................................................................. 57
6.0 Flash Pro g ram Memory.......................... ........................... ........................... ..................... ......................................................... 79
7.0 Data EEPR OM Mem o ry.... ............... ........................... ........................... ........................... ......................................................... 89
8.0 8 x 8 Hardware Multip lier.................... ..................... .............. ..................... ............... ................................................................. 95
9.0 Interrupts.................................................................................................................................................................................... 97
10.0 I/O Ports ...................... ................................. ........................... ............................ ..................................................................... 111
11.0 Timer0 Module ......................................................................................................................................................................... 125
12.0 Timer1 Module ......................................................................................................................................................................... 129
13.0 Timer2 Module ......................................................................................................................................................................... 135
14.0 Timer3 Module ......................................................................................................................................................................... 137
15.0 Capture/Compare/PWM (CCP) Modules ..................................................................................... ............................................ 141
16.0 Enhanc ed Capture/Com pare/PW M (ECCP) Module................................................................................................................ 149
17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 163
18.0 Streaming Parallel Port ............................................................................................................................................................ 187
19.0 Mas ter Sy nchronous  Serial Port (M SSP ) Module ............................................................................... ..................................... 193
20.0 Enhanc ed Universal Sync hronous As ynchronous Receiver Transmitter (EUSART)............................................ ................... 237
21.0 10-Bit Analog-to-Digital Converter (A/D) Module ...................................................... .... .... ........... ............................................ 259
22.0 Comparator Module....................... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... ......................................................... 269
23.0 Comparator Voltage Reference Module......... .... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .............................................. 275
24.0 High/Low-Voltage Detect (HLVD)................................ .... .... .... ......... .... .... .... ........... .... .... ......................................................... 279
25.0 Specia l Features of the CPU........................ ..................... ..................... ........................... ....................................................... 285
26.0 Instruction Set Summary.......................................................................................................................................................... 307
27.0 Developm ent Suppor t............................................................................................................................................................... 357
28.0 Electrical Characteristics.......................................................................................................................................................... 361
29.0 DC and AC Characteristics Graphs and Tables................ .... ......... .. .... .... .... ....... .... .... .... .. ......... .... .......................................... 399
30.0 Packagin g  In fo rmation............................ ..................... ........................... ..................... ............................................................. 401
Appendix A: Revision History............................................................................................................................................................. 409
Appendix B: Device Differences......................................................................................................................................................... 409
Appendix C: Conversion Considerations ..................... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....................................................... 410
Appendix D: Migration From Baseline to Enhanced Devices ............................................................................................................. 410
Appendix E: Migration From Mid-Range to Enhanced Devices............................. ....... .... .... .. .... ....... .... .. .... .. .. .................................. 411
Appendix F: Migration From High-End to Enhanced Devices.................. .... .. .... .. .. ......... .. .... .. .. ......... .. .. .... .. .. .................................... 411
Index .................................................................................................................................................................................................. 413
The Micro chip Web Site......................................... ........................... ............................ ..................................................................... 425
Customer Change Notification Service ........................ ............... ...... ............. ...... ............... ...... ......................................................... 425
Customer Support.......... ............. ...... .... ............. ...... .... ............. ...... ............. ...... .... ............................................................................ 425
Reader Response.............................................................................................................................................................................. 426
PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 427

PIC18F2455/2550/4455/4550

TO OUR VALUED CUSTOMERS

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Customer Noti fic atio n Syst em

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

1.0 DEVICE OVERVIEW

This docu ment conta ins dev ice -specific info rm atio n for

the following devices:

This family of devices offers the advantages of all

PIC18 microcontrollers – namely, high computational

performance at an economical price – with the addition

of high endurance, Enhanced Flash program mem-

ory. In addition to these features, the

PIC18F2 455/2550/ 4455/4550 family introd uces desig n

enhancements that make these microcontrollers a log-

ical choice for many high-performance, power sensitive

applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2455/2550/4455/4550

family incorporate a range of features that can signifi-

cantly reduce power consumption during operation.

Key items include:

•Alternate Run Modes: By clo cking the control ler

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

•Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active . In these st ates, powe r consumptio n can be

reduced even further, to as little as 4% of normal

operation requirements.

•On-the-Fly Mode Switching: The

power-m anage d mod es are invo ked b y use r code

during operation, allowing the user to incorporate

power-saving ideas into their application’s

software design.

•Low Consumption in Key Modules: The power

requirements for both Timer1 and the Watchdog

Timer are minimized. See Section 28.0

“Electri cal Characteristics” for values.

1.1.2 UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F2455/2550/4455/4550 family

incorporate a fully featured Universal Serial Bus

commu nication s modul e that is compl iant with the USB

Specification Revision 2.0. The module supports both

low-speed and full-speed communication for all sup-

ported data transfer types. It also incorporates its own

on-chip transceiver and 3.3V regulator and supports

the use of extern al transc eivers and volt age reg ulators.

1.1.3 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2455/2550/4455/4550

family offer twelve different oscillator options, allowing

users a wide range o f choices i n developin g applica tion

hardware. These include:

• Four Crystal modes using crystals or ceramic

resonators.

• Four External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4

clock output) or one pin (oscillator input, with the

second pin reassigned as general I/O).

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC

source (app rox im ate ly 31 kHz, stable over

temperature and VDD), as well as a range of

6 user-select a ble clock frequen ci es, betw een

125 kHz to 4 MHz, for a total of 8 clock

frequenci es. This op tion frees an oscillat or pin for

use as an additi ona l gene ral purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and

External Oscillator modes, which allows a wide

range of clock speeds from 4 MHz to 48 MHz.

• Asynchronous dual clock operation, allowing the

USB module to run from a high-frequency

oscillator while the rest of the microcontroller is

clocked from an internal low-power oscillator.

Besides its availability as a clock source, the internal

oscill ato r blo ck pro vid es a s t ab le re ference sourc e th at

gives the family additional features for robust

operation:

•Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a

reference signal provided by the internal

oscill ator. If a clock failure o ccurs, the control ler is

switched to the internal oscillator block, allowing

for continued low-speed operation or a safe

application shutdown.

•Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset , or wake-up from Sleep

mode, until the primary clock source is available.

• PIC18F2455 • PIC18LF2455

• PIC18F2550 • PIC18LF2550

• PIC18F4455 • PIC18LF4455

• PIC18F4550 • PIC18LF4550

PIC18F2455/2550/4455/4550

1.2 Other Special Features

•Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are

rated to last for many thousands of erase/write

cycles – up to 100,000 for program memory and

1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greater

than 40 year s.

•Self-Programmability: These devices can w rite to

their own program memory sp aces under internal

software control. By using a bootloader routine,

located in the protected Boot Block at the top of

program memory, it be comes p ossible to create an

application that can update itself in the field.

•Extended Instruction Set: The

PIC18F2455/2550/4455/4550 family introduces

an option al extensi on to the PIC18 instr uction set,

which adds 8 new instructions and an Indexed

Literal Offset Addressing mode. This extension,

enabled as a device configuration option, has

been specifically designed to optimize re-entrant

applic ation code original ly develo ped in high-l evel

languages such as C.

•Enhanced CCP Module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for

controlling half-bridge and full-bridge drivers.

Other featu res inc lu de auto - sh ut d ow n for

disabl ing PWM output s on interrup t or other selec t

conditions and auto-restart to reactivate outputs

once the condition has cleared.

•Enhanced Addressable USART: This serial

communication module is capable of standard

RS-232 operation an d provides support for th e LIN

bus protocol. Other enhancements include

Automati c Baud Rate Detectio n an d a 16-bit Baud

Rate Genera tor for improved res olution. Whe n the

microcontroller is using the internal oscillator

block, the EUSART provides stable operation for

applications that talk to the outside world without

using an external crystal (or its accompanying

power requirement).

•10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiate d, without waitin g for a sampling pe riod and

thus, reducing code overhead.

• Dedicated ICD/ICSP Port: These dev ic es

introduce the use of debugger and programming

pins that are no t mult iplexed with other micro -

controller features. Offered as an option in select

pac kages, thi s feature allo ws users to d evelop I/O

intensive applications while retaining the ability to

program and debug in the circuit.

1.3 Details on Individual Family

Members

Devices in the PIC18F 2455/2550/44 55/4550 famil y are

available in 28-pin and 40/44-pin packages. Block

diagrams for the two groups are shown in Figure 1-1

and Figure 1-2.

The devices are differentiated from each other in six

ways:

1. Flash program memory (24 Kbytes for

PIC18FX455 devices, 32 Kbytes for

PIC18FX550).

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports and 1 input only

port on 28-pin devices, 5 bidirectional ports on

40/44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have two standard CCP

modules, 40/44-pin devices have one standard

CCP module and one ECCP module).

5. Streaming Parallel Port (present only on

40/44-pin devices).

All other feature s for devi ces in th is family are ide ntical.

These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and

Table 1-3.

Like all Microchip PIC18 devices, members of the

PIC18F2455/2550/4455/4550 family are available as

both standard and low-voltage devices. Standard

device s with En hanced Fl ash memory, designated w ith

an “F” in the part number (such as PIC18F2550),

accom modate an operati ng V DD ra nge of 4 .2V t o 5. 5V.

Low-voltage parts, designated by “LF” (such as

PIC18LF2550), function over an extended VDD range

of 2.0V to 5.5V.

PIC18F2455/2550/4455/4550

TABLE 1-1: DEVICE FEATURES

Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz

Program Memo ry (Bytes ) 24576 32768 24576 32768

Program Memo ry (Instructions) 12288 16384 12288 16384

Data Me mo ry (Byte s) 2048 2048 2048 2048

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 2 2 1 1

Enhanced Capture/

Compare/PWM Modules 0011

Serial Communications MSSP,

Enhanced USART MSSP,

Enhanced USART

Universal Serial Bus (USB)

Module 1111

Streaming Parallel Port (SPP) No No Yes Yes

10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Comparators 2 2 2 2

Resets (and Delays) POR, BOR,

RESET Ins truction,

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

POR, BOR,

RESET Instruction,

Stack Full,

St ac k Unde rflow

(PWRT, OST),

MCLR (optional),

WDT

POR, BOR,

RESET Instruction,

Stack Full,

St ac k Unde rflow

(PWRT, OST),

MCLR (optional),

WDT

Programmable Low -Voltage

Detect Yes Yes Yes Yes

Programmab le Brown-o ut Rese t Yes Yes Yes Yes

Instruct ion Set 75 Instructions;

83 with Extended

Instruction Set

enabled

75 Instructions;

83 with Extended

Instruction Set

enabled

75 Instructio ns ;

83 with Extended

Instruction Set

enabled

75 Instructio ns ;

83 with Extended

Instruction Set

enabled

Packages 28-pin PDIP

28-pin SOIC 28-pin PDIP

28-pin SOIC 40-pin P DIP

44-pin QFN

44-pin TQFP

40-pin P DIP

44-pin QFN

44-pin TQFP

PIC18F2455/2550/4455/4550

FIGURE 1-1: PIC18F 2455/ 2550 ( 28-PIN) BLOCK DI AGR AM

Data Latch

Dat a Memory

(2 Kbytes)

Addr ess L atc h

Data Address<12>

Access

BSR

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

ALU<8>

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

Tabl e Poin te r < 2 1 >

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

3: RB3 is the alternate pin for CCP2 multiplexing.

Instruction Bus <16>

STKPTR Bank

BITOP

FSR0

FSR1

FSR2

inc/dec

Address

Decode

logic

EUSART

Comparator MSSP 10-Bit

ADC

Timer2Timer1 Timer3Timer0

HLVD

CCP2

BOR Data

EEPROM

USB

Instruction

Decode &

Control

State Machine

Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Reference

Band Gap

VSS

MCLR(1)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

USB Voltage

Regulator

VUSB

PORTB

PORTC

RB0/AN12/INT0/FLT0/SDI/SDA

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(3)/UOE

RC2/CCP1

RC4/D-/VM

RC5/D+/VP

RC6/TX/CK

RC7/RX/DT/SDO

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2(3)/VPO

RB4/AN11/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

PORTA

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS/HLVDIN/C2OUT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

OSC2/CLKO/RA6

CCP1

PIC18F2455/2550/4455/4550

FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM

Instruction

Decode &

Control

Data Latch

Data Mem o ry

(2 Kbytes)

Address Latch

Dat a Addr ess<12 >

Access

BSR

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP 8

ALU<8>

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PORTD

RD0/SPP0:RD4/SPP4

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

RE2/AN7/OESPP

RE0/AN5/CK1SPP

RE1/AN6/CK2SPP

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CL K O are only a vailab le in sele ct oscilla tor m odes an d whe n the se pins are not being used as digital I/O. Refer

to Section 2.0 “Oscillator Configurations” for additional information.

3: These pi ns are only avai lable on 4 4-pin TQFP pac kages unde r certain co nditions. Refer to Section 25.9 “S pecial ICPORT F eatures

(Designated Packages Only)” for additional information.

4: RB3 is the alternate pin for CCP2 multiplexing.

EUSART

Comparator MSSP 10-Bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR Data

EEPROM

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(2)

OSC2(2)

VDD, VSS

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor Reference

Band Gap

MCLR(1)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

RD5/SPP5/P1B

RD6/SPP6/P1C

RD7/SPP7/P1D

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT/RCV

RA5/AN4/SS/HLVDIN/C2OUT

RB0/AN12/INT0/FLT0/SDI/SDA

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(4)/UOE

RC2/CCP1/P1A

RC4/D-/VM

RC5/D+/VP

RC6/TX/CK

RC7/RX/DT/SDO

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMO

RB3/AN9/CCP2(4)/VPO

OSC2/CLKO/RA6

RB4/AN11/KBI0/CSSPP

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

USB

FSR0

FSR1

FSR2

inc/dec

Address

Decode

logic

USB Voltage

Regulator

VUSB

ICRST(3)

ICPGC(3)

ICPGD(3)

ICPORTS(3)

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS

Pin Name

Number Pin

Type Buffer

Type Description

PDIP,

SOIC

MCLR/VPP/RE3

MCLR

VPP

RE3

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

Programmi ng vol t ag e inpu t.

Digital input.

OSC1/CLKI

OSC1

CLKI

IAnalog

Analog

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

External clock source input. Always associated with pin

function OSC1. (See OSC2/CLKO pin.)

OSC2/CLKO/RA6

OSC2

CLKO

RA6

10 O

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode.

In select modes, O SC 2 pi n ou tpu ts CLKO whi ch has 1/4 the

frequency of OSC1 and denotes the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

PIC18F2455/2550/4455/4550

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

2I/O

ITTL

Analog Digital I/O.

Analog input 0.

RA1/AN1

RA1

AN1

3I/O

ITTL

Analog Digital I/O.

Analog input 1.

RA2/AN2/VREF-/CVREF

RA2

AN2

VREF-

CVREF

4I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (low) input.

Analog comparator reference output.

RA3/AN3/VREF+

RA3

AN3

VREF+

5I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI/C1OUT/RCV

RA4

T0CKI

C1OUT

RCV

6I/O

—

TTL

Digital I/O.

Timer0 external clock input.

Comparator 1 output.

External USB transceiver RCV input.

RA5/AN4/SS/

HLVDIN/C2OUT

RA5

AN4

HLVDIN

C2OUT

I/O

TTL

Analog

TTL

Analog

—

Digital I/O.

Analog input 4.

SPI slave select input.

High/Low-Voltage Detect input.

Comparator 2 output.

RA6 — — — See t he OSC2/CLKO/RA6 pin.

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Number Pin

Type Buffer

Type Description

PDIP,

SOIC

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

PIC18F2455/2550/4455/4550

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/AN12/INT0/FLT0/

SDI/SDA

RB0

AN12

INT0

FLT0

SDI

SDA

I/O

TTL

Analog

Digital I/O.

Analog input 12.

External interrupt 0.

PWM Fault input (CCP1 module).

SPI data in.

I2C™ data I/O.

RB1/AN10/INT1/SCK/

SCL

RB1

AN10

INT1

SCK

SCL

I/O

TTL

Analog

Digital I/O.

Analog input 10.

External interrupt 1.

Synchronous serial clock input/output for SPI mode.

Synchronou s serial clock input/output for I2C mode.

RB2/AN8/INT2/VMO

RB2

AN8

INT2

VMO

23 I/O

TTL

Analog

—

Digital I/O.

Analog input 8.

External interrupt 2.

External USB transceiver VMO output.

RB3/AN9/CCP2/VPO

RB3

AN9

CCP2(1)

VPO

24 I/O

I/O

TTL

Analog

—

Digital I/O.

Analog input 9.

Capture 2 input/Compare 2 output/PWM 2 output.

External USB transceiver VPO output.

RB4/AN11/KBI0

RB4

AN11

KBI0

25 I/O

TTL

Analog

TTL

Digital I/O.

Analog input 11.

Interrupt-on-change pin.

RB5/KBI1/PGM

RB5

KBI1

PGM

26 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

27 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

28 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Number Pin

Type Buffer

Type Description

PDIP,

SOIC

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

PIC18F2455/2550/4455/4550

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

11 I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2/UOE

RC1

T1OSI

CCP2(2)

UOE

12 I/O

I/O

—

CMOS

—

Digital I/O.

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM 2 output.

External USB transceiver OE output.

RC2/CCP1

RC2

CCP1

13 I/O

I/O ST

ST Digital I/O.

Capture 1 input/Compare 1 output/PWM 1 output.

RC4/D-/VM

RC4

D-

15 I

I/O

TTL

—

TTL

Digital input.

USB differential minus line (input/output).

External USB transceiver VM input.

RC5/D+/VP

RC5

D+

16 I

I/O

TTL

—

TTL

Digital input.

USB differential plus line (input/output).

External USB transceiver VP input.

RC6/TX/CK

RC6

17 I/O

I/O

—

Digital I/O.

EUSART asy nc hronous transmit.

EUSART sy nc hron ous clock (se e RX/DT).

RC7/RX/DT/SDO

RC7

SDO

18 I/O

I/O

—

Digital I/O.

EUSART asy nc hro nou s rece iv e.

EUSART sy nc hron ous dat a (se e TX/CK) .

SPI data out.

RE3 — — — See MCLR/VPP/RE3 pin.

VUSB 14 O — Internal USB 3.3V voltage regulator.

VSS 8, 19 P — Ground reference for logic and I/O pins.

VDD 20 P — Positive supply for logic and I/O pins.

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Number Pin

Type Buffer

Type Description

PDIP,

SOIC

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

MCLR/VPP/RE3

MCLR

VPP

RE3

11818I

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

Programming voltage input.

Digital input.

OSC1/CLKI

OSC1

CLKI

13 32 30 I

IAnalog

Analog

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

External clock source input. Always associated with

pin function OSC1. (See OSC2/CLKO pin.)

OSC2/CLKO/RA6

OSC2

CLKO

RA6

14 33 31 O

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has 1/4

the frequency of OSC1 and denotes the instruction

cycle rate.

General purpos e I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2455/2550/4455/4550

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

21919

I/O

ITTL

Analog Digital I/O.

Analog input 0.

RA1/AN1

RA1

AN1

32020

I/O

ITTL

Analog Digital I/O.

Analog input 1.

RA2/AN2/VREF-/

CVREF

RA2

AN2

VREF-

CVREF

42121

I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (low) input.

Analog comparator reference output.

RA3/AN3/VREF+

RA3

AN3

VREF+

52222

I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI/C1OUT/

RCV

RA4

T0CKI

C1OUT

RCV

62323

I/O

—

TTL

Digital I/O.

Timer0 external clock input.

Comparator 1 output.

External USB transceiver RCV input.

RA5/AN4/SS/

HLVDIN/C2OUT

RA5

AN4

HLVDIN

C2OUT

72424

I/O

TTL

Analog

TTL

Analog

—

Digital I/O.

Analog input 4.

SPI slave select input.

High/Low-Voltage Detect input.

Comparator 2 output.

RA6 — — — — — See the OSC2/CLKO/RA6 pin.

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2455/2550/4455/4550

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/AN12/INT0/

FLT0/SDI/SDA

RB0

AN12

INT0

FLT0

SDI

SDA

33 9 8

I/O

TTL

Analog

Digital I/O.

Analog input 12.

External interrupt 0.

Enhanced PWM Fault input (ECCP1 module).

SPI data in.

I2C™ data I/O.

RB1/AN10/INT1/SCK/

SCL

RB1

AN10

INT1

SCK

SCL

34 10 9

I/O

TTL

Analog

Digital I/O.

Analog input 10.

External interrupt 1.

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C mode.

RB2/AN8/INT2/VMO

RB2

AN8

INT2

VMO

35 11 10 I/O

TTL

Analog

—

Digital I/O.

Analog input 8.

External interrupt 2.

External USB transceiver VMO output.

RB3/AN9/CCP2/VPO

RB3

AN9

CCP2(1)

VPO

36 12 11 I/O

I/O

TTL

Analog

—

Digital I/O.

Analog input 9.

Capture 2 input/Compare 2 output/PWM 2 output.

External USB transceiver VPO output.

RB4/AN11/KBI0/CSSPP

RB4

AN11

KBI0

CSSPP

37 14 14 I/O

TTL

Analog

TTL

—

Digital I/O.

Analog input 11.

Interrupt-on-change pin.

SPP chip select control output.

RB5/KBI1/PGM

RB5

KBI1

PGM

38 15 15 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

39 16 16 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming cloc k pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

40 17 17 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming dat a pin.

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2455/2550/4455/4550

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

15 34 32 I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1 /Timer3 external clock input.

RC1/T1OSI/CCP2/

UOE

RC1

T1OSI

CCP2(2)

UOE

16 35 35

I/O

CMOS

—

Digital I/O.

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM 2 output.

External USB transceiver OE output.

RC2/CCP1/P1A

RC2

CCP1

P1A

17 36 36 I/O

I/O

TTL

Digital I/O.

Capture 1 input/Compare 1 output/PWM 1 output.

Enhanced CCP1 PWM output, channel A.

RC4/D-/VM

RC4

D-

23 42 42 I

I/O

TTL

—

TTL

Digital input.

USB differential minus line (input/output).

External USB transceiver VM input.

RC5/D+/VP

RC5

D+

24 43 43 I

I/O

TTL

—

TTL

Digital input.

USB differential plus line (input/output).

External USB transceiver VP input.

RC6/TX/CK

RC6

25 44 44 I/O

I/O

—

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see RX/DT).

RC7/RX/DT/SDO

RC7

SDO

26 1 1 I/O

I/O

—

Digital I/O.

EU SART asynchrono us receive.

EUSART synchronous data (see TX/CK).

SPI data out.

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2455/2550/4455/4550

PORTD is a bidirectional I/O port or a Streaming

Parallel Port (SPP). These pins have TTL input buffers

when the SPP module is enabled.

RD0/SPP0

RD0

SPP0

19 38 38 I/O

I/O ST

TTL Digital I/O.

Streaming Parallel Port data.

RD1/SPP1

RD1

SPP1

20 39 39 I/O

I/O ST

TTL Digital I/O.

Streaming Parallel Port data.

RD2/SPP2

RD2

SPP2

21 40 40 I/O

I/O ST

TTL Digital I/O.

Streaming Parallel Port data.

RD3/SPP3

RD3

SPP3

22 41 41 I/O

I/O ST

TTL Digital I/O.

Streaming Parallel Port data.

RD4/SPP4

RD4

SPP4

27 2 2 I/O

I/O ST

TTL Digital I/O.

Streaming Parallel Port data.

RD5/SPP5/P1B

RD5

SPP5

P1B

28 3 3 I/O

I/O

TTL

—

Digital I/O.

Streaming Parallel Port data.

Enhanced CCP1 PWM output, channel B.

RD6/SPP6/P1C

RD6

SPP6

P1C

29 4 4 I/O

I/O

TTL

—

Digital I/O.

Streaming Parallel Port data.

Enhanced CCP1 PWM output, channel C.

RD7/SPP7/P1D

RD7

SPP7

P1D

30 5 5 I/O

I/O

TTL

—

Digital I/O.

Streaming Parallel Port data.

Enhanced CCP1 PWM output, channel D.

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2455/2550/4455/4550

PORTE is a bidirectional I/O port.

RE0/AN5/CK1SPP

RE0

AN5

CK1SPP

82525

I/O

Analog

—

Digital I/O.

Analog input 5.

SPP clock 1 output.

RE1/AN6/CK2SPP

RE1

AN6

CK2SPP

92626

I/O

Analog

—

Digital I/O.

Analog input 6.

SPP clock 2 output.

RE2/AN7/OESPP

RE2

AN7

OESPP

10 27 27 I/O

Analog

—

Digital I/O.

Analog input 7.

SPP output enable output.

RE3 — — — — — See MCLR/VPP/RE3 pin.

VSS 12, 31 6, 30,

31 6, 29 P — Ground reference for logic and I/O pins.

VDD 11, 32 7, 8,

28, 29 7, 28 P — Positive supply for logic and I/O pins.

VUSB 18 37 37 O — Internal USB 3.3V voltage regulator output.

NC/ICCK/ICPGC(3)

ICCK

ICPGC

——12

I/O

I/O ST

No Connect or dedicated ICD/ICSP™ port clock.

In-Circuit Debugger clock.

ICSP programming clock.

NC/ICDT/ICPGD(3)

ICDT

ICPGD

——13

I/O

I/O ST

No Connect or dedicated ICD/ICSP port clock.

In-Circuit Debugger data.

ICSP programming data.

NC/ICRST/ICVPP(3)

ICRST

ICVPP

——33 I

P—

—

No Connect or dedicated ICD/ICSP port Reset.

Master Clear (Reset) input.

Programming voltage input.

NC/ICPORTS(3)

ICPORTS — — 34 P — No Connect or 28-pin device emulation.

Enable 28-pin device emulation when connected

to VSS.

NC — 13 — — — No Con n e c t .

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

PIC18F2455/2550/4455/4550

NOTES:

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 23
PIC18F2455/2550/4455/4550
2.0 OSCILLATOR 
CONFIGURATIONS
2.1 Overview
Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock  sy st em  than  previous PIC18F device s. The addi-
tion of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full-speed specifications.
To accommo da te these requ irem ents, PIC18F2455/
2550/44 55/455 0 devices in clude  a new clock  branch to
provide a 48 MHz clock for full-speed USB operation.
Since it is driven from the primary clock source, an
additional system of prescalers and postscalers has
been adde d to accomm odate a wid e range of oscil lator
frequencies. An overview of the oscillator structure is
shown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
2.1.1 OSCILLATOR CONTROL
The operation of the oscillator in PIC18F2455/2550/
4455/4550 devices is controlled through two Configu-
ration re gister s and two  control re gisters.  Configur ation
registers, CONFIG1L and CONFIG1H, select the
oscillator mode and USB prescaler/postscaler options.
As Configuration bits, these are set when the device is
programmed and left in that configuration until the
dev ice is reprogra mmed. 
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2
“OSCTUNE Register”.
2.2 Oscillator Types
PIC18F2455/2550/4455/4550 dev ices can be operated
in twel ve  dis tin ct oscillat or m odes. In contrast with p re-
vious PIC18 enhanced microcontrollers, four of these
modes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 Configuration
bits to select one of these modes:
1. XT Crystal/Resonator
2. XTPLL Crystal/Resonator with PLL enabled
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator 
with PLL enabled
5. EC External Clock with FOSC/4 output
6. ECIO External Clock with I/O on RA6
7. ECPLL External Cl oc k with PLL ena ble d 
and FOSC/4 output on RA6
8. ECPIO External Cloc k with PLL ena ble d, 
I/O on RA6
9. INTHS Internal Oscillator used as 
microcontroller clock source, HS 
Oscillator used as USB clock source
10. INTXT Internal Oscillator used as
microcontroller clock source, XT 
Oscillator used as USB clock source
11. INTIO Internal Oscillator used as 
microcontroller clock source, EC
Oscillator used as USB clock source,
digi tal I/O on R A6
12. INTCKOInternal Oscillator used as 
microcontroller clock source, EC 
Oscillator used as USB clock source, 
FOSC/4 outp ut on RA6
2.2.1 OSCILLATOR MODES AND 
USB OPERATION
Because of the unique requirement s of the USB module,
a different approach to clock operation is necessary. In
previous PIC® devices, all core and peripheral clocks
were driven by a single oscillator source; the usual
sources were primary, secondary or the internal oscilla-
tor. With PIC18F2455/2550/4455/4550 devices, the pri-
mary oscillator becomes part of the USB module and
cannot be associated to any other clock source. Thus,
the USB module must be clocked from the primary cloc k
source; however, the microcontroller core and other
peripherals can be sep arately  clocked from  the second-
ary or internal oscillators as before.
Because of the timing requirements imposed by USB,
an int erna l c lock of either 6 MHz or 48 MHz is req uire d
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module  clock requi rement and sti ll provide fl exibil-
ity f or cloc king the r est of  the devi ce from  the pri mary
oscillator source. These are detailed in Section 2.3
“Oscillator Settings for USB”.

PIC18F2455/2550/4455/4550

FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

PIC18F2455/2550/4455/4550

FOSC3:FOSC0

Secondary Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for other Modules

OSC1

OSC2

Sleep

Primary Oscillator

XT, HS, EC, ECIO

T1OSC

CPU

Peripherals

IDLEN

INTOSC Po stscaler

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111

110

101

100

011

010

001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

Source

8 MHz

31 kHz (INTRC) 0

OSCTUNE<7>

and Two-Speed Start-up

96 MHz

PLL

PLLDIV

CPUDIV

÷ 2

PLL Prescaler

MUX

111

110

101

100

011

010

001

000

÷ 1

÷ 2

÷ 3

÷ 4

÷ 5

÷ 6

÷ 10

÷ 12

PLL Postscaler

÷ 2

÷ 3

÷ 4

÷ 6

USB

USBDIV

FOSC3:FOSC0

HSPLL, ECPLL,

Oscillator Post scaler

÷ 1

÷ 2

÷ 3

÷ 4

CPUDIV

Peripheral

FSEN

÷ 4

USB Clock Source

XTPLL, ECPIO

Primary

Clock

(4 MHz Input Only)

PIC18F2455/2550/4455/4550

2.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In HS, HSPLL, XT and XTPLL Oscillator modes, a

crystal or ceramic resonator is connected to the OSC1

and OSC2 pins to establish oscillation. Figure 2-2

shows the pin connections.

The oscillator design requires the use of a parallel cut

crystal.

FIGURE 2-2: CRYSTAL/CERAMIC

RESONATOR OPERATION

(XT, HS OR HSPLL

CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

T ABLE 2-2: CAPACITOR SELECTION FOR

CRYST AL OSCILLATOR

An internal postscaler allows users to select a clock

frequency other than that of the crystal or resonator.

Frequency division is determined by the CPUDIV

Configuration bits. Users may select a clock frequency

of the oscillator frequency, or 1/2, 1/3 or 1/4 of the

frequency.

An external clock may also be used when the micro-

controller is in HS Oscillator mode. In this case, the

OSC2/CLKO pin is left open (Figure 2-3).

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s

specifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 4.0 MHz 33 pF 33 pF

HS 8.0 MHz

16.0 MHz 27 pF

22 pF 27 pF

22 pF

Capacitor values are for design guidance only.

These capacitors were tested with the resonators

listed below for basic start-up and operation. These

values are not optimized.

Dif ferent cap acitor values may be required to produc e

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following Table 2-2 for additional

information.

Resonators Used:

4.0 MHz

8.0 MHz

16.0 MHz

Note 1: See Table 2-1 and Table 2-2 for initial values of

C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

Logic

PIC18FXXXX

RS(2)

Internal

Osc Type Crystal

Freq

Typical Ca pac itor Values

Tested:

C1 C2

XT 4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacito rs were tested with th e crystals listed

below for basic st art-up a nd ope rati on . These values

are not optimized.

Dif ferent capa citor values m ay be required to prod uce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following this table for additional

information.

Crystals Used:

4 MHz

8 MHz

20 MHz

Note 1: Higher capacit ance inc reases the st abilit y

of oscillator but also increases the

start-up time.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use the

HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always veri fy os ci lla tor performance ov er

the VDD and temperature range that is

expected for the application.

PIC18F2455/2550/4455/4550

FIGURE 2-3: EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

2.2.3 EXTERNAL CLOCK INPUT

The EC, ECIO, ECPLL and ECPIO Oscillator modes

require an external cl ock sourc e to be conne cted to the

OSC1 pin. There is no oscillator start-up time required

after a Power-on Reset or after an exit from Sleep

mode.

In the EC and ECPLL Oscillator modes, the oscillator

frequency divided by 4 is available on the OSC2 pin.

This signal may be used for test purposes or to

synchronize other logic. Figure 2-4 shows the pin

connections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

INPUT OPERATION

(EC AND ECPLL

CONFIGURATION)

The ECIO and EC PIO Oscil lator modes function like the

EC and ECPLL modes, except that the OSC2 pin

becomes an additional general purpose I/O pin. The I/O

pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows

the pin connections for the ECIO Osc illator mo de.

FIGURE 2-5: EXTERNAL CLOCK

INPUT OPERATION

(ECIO AND ECPIO

CONFIGURATION)

The internal postscaler for reducing clock frequency in

XT and HS modes is also available in EC and ECIO

modes.

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2 455/2550/4 255/4550 dev ices includ e a Phase

Locked Loop (PLL) circuit. This is provided specifically

for USB applications with lower speed oscillators and

can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and

ECPIO Oscillator modes. It is designed to produce a

fixed 96 MHz reference clock from a fixed 4 MHz input.

The output can then be divided and used for both the

USB and the microcontroller core clock. Because the

PLL has a fixed frequency input and output, there are

eight prescaling options to match the oscillator input

frequency to the PLL.

Ther e i s al so a s epara te pos tscal er op tio n for de rivi ng

the microcontroller clock from the PLL. This allows the

USB peripheral and microcontroller to use the same

oscillator input and still operate at different clock

speeds . In contrast to the post scaler for XT, HS and EC

modes, the available options are 1/2, 1/3, 1/4 and 1/6

of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use of

the HS mode oscillator for frequencies up to 48 MHz.

The pr es ca ler div id es the os ci ll ator inp ut by up to 12 to

produ ce the 4 MHz drive for the PLL. The XTPLL mode

can only us e an input frequ ency of 4 MHz whi ch drive s

the PLL directly.

FIGURE 2-6: PLL BLOCK DIAGRAM

(HS MODE)

OSC1

OSC2

Open

Clock from

Ext. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKO

FOSC/4

Clock from

Ext. System PIC18FXXXX

OSC1/CLKI

I/O (OSC2)

RA6

Clock from

Ext. System PIC18FXXXX

MUX

VCO

Loop

Filter

and

Prescaler

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

HS/EC/ECIO/X T Oscilla tor Enabl e

÷24

(from CONFIG1H Register)

Oscillator

PIC18F2455/2550/4455/4550

2.2.5 INTERNAL OSCILLATOR BLOCK

The PIC18F2455/2550/4455/4550 devices include an

internal oscillator block which generates two different

clock signals; either can be used as the microcontroller’s

clock source. If the USB peripheral is not used, the

internal oscillator may eliminate the need for external

oscillator circuit s on the O SC1 and/or OSC2 pins .

The main output (INTOSC) is an 8 MHz clock source

which can be used to directly drive the device clock. It

also driv es the INTO SC postsca ler which can prov ide a

range of clock frequencies from 31 kHz to 4 MHz. The

INTOSC output is enabled when a clock frequency

from 125 kHz to 8 MHz is select ed .

The other clock source is the internal RC oscillator

(INTRC) which provides a nominal 31 kHz output.

INTRC is enabled if it is selected as the device clock

sour ce; it is also ena bled automatic ally when an y of the

following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 25.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring

the IRCF bits of the OSCCON register (page 32).

2.2.5.1 Internal Oscillator Modes

When the internal oscillator is used as the micro-

controller clock source, one of the other oscillator

modes (External Clock or External Crystal/Resonator)

must be used as the USB clock source. The choice of

the USB clock source is determined by the particular

internal oscillator mode.

There are four distinct modes available:

1. INTHS mode: The USB clock is provided by the

oscillator in HS mode.

2. INTXT mode: The USB clock is provided by the

osci llator in X T mode.

3. INTCKO mode: The USB clock is provided by an

external clock input on OSC1/CLKI; the OSC2/

CLKO pin outputs FOSC/4.

4. INTIO mode: The USB clock is provided by an

external clock input on OSC1/CLKI; the OSC2/

CLKO pin functions as a digital I/O (RA6).

Of these four modes, only INTIO mode frees up an

additional pin (OSC2/CLKO/RA6) for port I/O use.

2.2.5.2 OSCTUNE Register

The internal oscillator’s output has been calibrated at

the factory but can be adjusted in the user’s applica-

tion. This is done by writing to the OSCTUNE register

(Register 2-1). The tuning sensitivity is constant

throughout the tuning range.

When the O SC TUN E reg is ter is mo di fied , the IN T O SC

and INTRC frequencies will begin shifting to the new

frequency. The INTRC clock will reach the new

frequency within 8 clock cycles (approximately,

8*32μs = 256 μs). The INTOSC clock will stabilize

within 1 ms. Code ex ecution continues during th is shi ft.

There is no indication that the shift has occurred.

The OSCTUNE register also contains the INTSRC bit.

The INTSRC bit allows users to select which internal

oscillator provides the clock source when the 31 kHz

frequenc y opt ion is se lected . This is cove red in greater

detail in Section 2.4.1 “Osc illator Control Regis ter”.

2.2.5.3 Internal Oscillator Output Frequency

and Drift

The internal oscillator block is calibrated at the factory

to produce an INTOSC output frequency of 8.0 MHz.

However, this frequency may drift as VDD or tempera-

ture changes, which can affect the controller operation

in a variety of ways.

The low -fre qu enc y IN TRC o sc il lat or o pe rates i ndepen-

dently of the INT OSC so urce. Any ch anges in INTO SC

across voltage and temperature are not necessarily

reflected by changes in INTRC and vice versa.

PIC18F2455/2550/4455/4550

2.2.5.4 Compensating for INTOSC Drift

It is possible to adjust the INTOSC frequency by

modifying the value in the OSCTUNE register . This has

no effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to

make the adjustment, in which direction it should be

made and in some cases, how large a change is

needed. When using the EUSART, for example, an

adjustm ent may be requir ed when it begins to generate

framing errors or receives data with errors while in

Asynchronous mode. Framing errors indicate that the

device clock frequency is too high; to adjust for this,

decrement the value in OSCTUNE to reduce the clock

frequency. On the other hand, errors in data may sug-

gest that the clock speed is too low; to compensate,

increm ent OSC T UNE to incr eas e the clo ck freque nc y.

It is also possible to verify device clock speed against

a reference clock. Two timers may be used: one timer

is clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator. Both timers are cleared but the timer

clocked by the reference generates interrupts. When

an interrupt occurs, the internally clocked timer is read

and both timers are cleared. If the internally clocked

timer value is greater than expected, then the internal

oscillator block is running too fast. To adjust for this,

decreme nt the OSCTUNE register.

Finally, a CCP module can use free-r unning T ime r1 (or

Timer 3), cl oc ke d by th e int ernal oscilla tor bl ock and an

external event with a known period (i.e., AC power

frequenc y). The ti me of the first ev ent is c aptured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the firs t eve nt i s su btra cte d fro m the tim e of th e

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

If the measured time is much greater than the calcu-

lated time, the internal oscillator block is running too

fast; to compensate, decrement the OSCTUNE register .

If the measured time is much less than the calculated

time, the int er nal osci llator block is r unning to o slow ; t o

compensate, increment the OSCTUNE register .

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC —— TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

0 = 31 kHz device clock derived directly from INTRC inter nal oscillator

bit 6-5 Unimplemented: Read as ‘0’

bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximu m frequency

• •

00001

00000 = Center frequency. Oscillator module is running at the calibrated frequency.

11111

• •

10000 = Minimum frequency

PIC18F2455/2550/4455/4550

2.3 Oscillator Settings for USB

When the PIC18F4550 is used for USB connectivity, it

must have either a 6 MHz or 48 MHz clock for USB

operation, depending on whether Low-Speed or

Full-Speed mode is bei ng used. This may req uire some

forethought in selecting an oscillator frequency and

programming the device.

The full range of possible oscillator configurations

compatible with USB operation is shown in Table 2-3.

2.3.1 LOW-SPEED OPERATION

The USB clock for Low-Speed mode is derived from

the primary oscillator chain and not directly from the

PLL. It is divided by 4 to produce the actual 6 MHz

clock. Because of this, the microcontroller can only use

a clock frequency of 24 MHz when the USB module is

active and the controller clock source is one of the

primary oscillator modes (XT, HS or EC, with or without

the PLL).

This restriction does not apply if the microcontroller

clock source is the secondary oscillator or internal

oscillator block.

2.3.2 RUNNING DIFFERENT USB AND

MICROCONTROLLER CLOCKS

The USB module, in either mode, can run asynchro-

nously with respect to the microcontroller core and

other peripherals. This means that applications can us e

the pr imary oscilla tor for the USB cloc k while the m icro-

controller runs from a separate clock source at a lower

speed. If it is necessary to run the entire application

from only one clock source, full-speed operation

provides a greater selection of microcontroller clock

frequencies.

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION

Input Oscillator

Frequency PLL Division

(PLLDIV2:PLLDIV0) Clock Mode

(FOSC3:FOSC0) MCU Clock Division

(CPUDIV1:CPUDIV0) Microcontroller

Clock Frequency

48 MHz N/A(1) EC, ECIO None (00)48MHz

÷2 (01)24 MHz

÷3 (10)16MHz

÷4 (11)12MHz

48 MHz ÷12 (111) EC, ECIO None (00)48MHz

÷2 (01)24 MHz

÷3 (10)16MHz

÷4 (11)12MHz

ECPL L, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

40 MHz ÷10 (110) EC, ECIO None (00)40MHz

÷2 (01)20MHz

÷3 (10) 13.33 MHz

÷4 (11)10MHz

ECPL L, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

24 MHz ÷6 (101) HS, EC, ECIO None (00)24 MHz

÷2 (01)12MHz

÷3 (10)8MHz

÷4 (11)6MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).

Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,

USB clock of 6 MHz).

Note 1: Only valid when the USBDIV Configuration bit is cleared.

PIC18F2455/2550/4455/4550

20 MHz ÷5 (100) HS, EC, ECIO None (00)20MHz

÷2 (01)10MHz

÷3 (10)6.67MHz

÷4 (11)5MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

16 MHz ÷4 (011) HS, EC, ECIO None (00)16MHz

÷2 (01)8MHz

÷3 (10)5.33MHz

÷4 (11)4MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

12 MHz ÷3 (010) HS, EC, ECIO None (00)12MHz

÷2 (01)6MHz

÷3 (10)4MHz

÷4 (11)3MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

8MHz ÷2 (001) HS, EC, ECIO None (00)8MHz

÷2 (01)4MHz

÷3 (10)2.67MHz

÷4 (11)2MHz

HSPLL, ECPLL, ECPIO ÷2 (00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

4MHz ÷1 (000) XT, HS, EC, ECIO None (00)4MHz

÷2 (01)2MHz

÷3 (10)1.33MHz

÷4 (11)1MHz

HSPLL, ECPLL, XTPLL,

ECPIO ÷2 ( 00)48MHz

÷3 (01)32MHz

÷4 (10)24 MHz

÷6 (11)16MHz

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)

Input Oscillator

Frequency PLL Division

(PLLDIV2:PLLDIV0) Clock Mode

(FOSC3:FOSC0) MCU Clock Division

(CPUDIV1:CPUDIV0) Microcontroller

Clock Frequency

Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).

Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,

USB clock of 6 MHz).

Note 1: Only valid when the USBDIV Configuration bit is cleared.

PIC18F2455/2550/4455/4550

2.4 Clock Sources and Oscillator

Switching

Like previous PIC18 enhanced devices, the

PIC18F2 455/2550/ 4455/4550 family in cludes a fe ature

that allo ws the dev ice clock so urce to be sw itched fro m

the main oscillator to an alternate low-frequency clock

source. PIC18F2455/2550/4455/4550 devices offer

two alternate clock sources. When an alternate clock

source is enabled, the various power-managed

operat in g mode s are ava il abl e.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillat ors

• Internal oscillator block

The primary oscillators include the External Crystal

and Resonator modes, the External Clock modes and

the internal oscillator block. The particular mode is

defi ned by t he FOS C3:F OSC 0 Co nf igur atio n b its. The

details of these modes are covered earlier in this

chapter.

The secondary oscillat ors are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18F2 455 /25 50/ 445 5/45 50 devices offer the Time r1

oscill ator as a seconda ry oscillator. This oscil lator , in all

power-managed modes, is often the time base for

functions such as a Real-Time Clock. Most often, a

32.768 kHz watch crystal is connected between the

RC0/T1OSO/T13CKI and RC1/T1OSI/UOE pins. Like

the XT and HS oscillator mode circuits, loading

cap acitors are also co nnected from eac h pin to ground.

The Timer1 oscillator is discussed in greater detail in

Section 12.3 “Timer1 Oscillator”.

In addi tion to be ing a prim ary clock s ource, the internal

oscillator block is available as a power-managed

mode cl oc k s ourc e. The INTRC s ou rce is also us ed a s

the clock source for several special features, such as

the WDT and Fail-Safe Clock Monitor.

2.4.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the device clock’s operation, both in full

power ope ratio n and in pow e r-ma nag ed mo des .

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC3:FOSC0 Configu-

ration bits), the secondary clock (Timer1 oscillator) and

the internal oscillator block. The clock source changes

immediately after one or more of the bits is written to,

following a brief clock transition interval. The SCS bits

are cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,

IRCF2:IRCF0, select the frequency output of the internal

oscillator block to drive the device clock. The ch oices are

the INTRC source, the INTOSC source (8 MHz) or one

of the frequencies derived from the INTOSC postscaler

(31 kHz to 4 MHz). If the internal oscillator block is

supplying the device clock, changing the states of these

bits will have an immediate c hange on the internal oscil-

lator’s output. On device Resets, the default output

frequency of the internal oscillator block is set at 1 MHz.

When an output frequency of 31 kHz is selected

(IRCF2:IRCF0 = 000), users may choose which inter-

nal oscillator acts as the source. This is done with the

INTSRC bit in th e OSCTUNE register (OSCTUNE<7>).

Setting this bit selects INTOSC as a 31.25 kHz clock

source by enabling the divide-by-256 output of the

INTOSC postscaler. Clearing INTSRC selects INTRC

(nominally 31 kHz) as the clock source.

This op tion allo ws use rs to sele ct the tun able and more

precise INTOSC as a clock source, while maintaining

power sa vings with a very lo w clock speed. Rega rdless

of the setting of INTSRC, INTRC always remains the

clock source for features such as the Watchdog Timer

and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock

source is currently providing the device clock. The OSTS

bit indicates that the Oscillator Start-up Timer has timed

out and the primary clock is providing the device clock in

primary clock modes. The IOFS bit indicates when the

internal oscillator block has stabilized and is providing

the device clock in RC Clock modes. The T1RUN bit

(T1CON<6>) indicates when the Timer1 oscillator is

providing the device c lock in s econdary clock mod es. In

power-managed mod es, only one of these three bit s will

be set at any time. If none of these bits are set, the

INTRC is providing the clock or the internal oscillator

block has just st arted and is not yet stable.

The IDL EN bi t dete rmines i f th e device goes into Sleep

mode, or one of the Idle modes, when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power -Mana ged Mod es ” .

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the T imer1 osc illator is

not enabled, then any attempt to select a

secondary clock s ource w ill be igno red .

2: It is recommended that the Timer1

oscillator be operating and stable prior to

switching to it as the clock source; other-

wise, a very long delay may occur while

the Timer1 oscillator starts.

PIC18F2455/2550/4455/4550

2.4.2 OSCIL LATOR TRANSITIONS

PIC18F2455/2550/4455/4550 devices contain circuitry

to prevent clock “glitches” when switching between

clock sources. A short p ause in the devic e clock occurs

during the clock switch. The length of this pause is the

sum of two cycles of the old clock source and three to

four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Id le mode on SLEEP instruction

0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly)

110 = 4 MHz

101 = 2 MHz

100 = 1 MHz(3)

011 = 500 kHz

010 = 250 kHz

001 = 125 kHz

000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running

0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable

0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock S elect bits

1x = Internal oscillator

01 = Timer1 oscillator

00 = Primary oscillator

Note 1: Depends on the state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.

3: Default output frequency of INTOSC on Reset.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 33
PIC18F2455/2550/4455/4550
2.5 Effects of Power-Managed Modes 
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating. 
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source.  The  31 kHz INTRC ou tput  can be  used d irectl y
to provide the clock and may be enabled to support
various special features regardless of the
power-managed mode (see Sect io n 25. 2 “Watch dog
Timer (WDT)”, Section 25.3 “Two-Speed Start-up”
and Section 25.4 “Fail-Safe C lock Moni tor ” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output is
disabled if the clock is provided directly from the INTRC
output.
Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device is
operating from a crystal or resonator-based oscillator,
that oscillator will continue to clock the USB module.
The core and all other modules will switch to the new
clock source.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Sleep mode should never be invoked while the USB
module is operating and connected. The only exception
is when the device has been issued a “Suspend”
command over the USB. Once the module has sus-
pended o peration and sh ifted to a low-p ower state, th e
microcontroller may be safely put into Sleep mode. 
Enabling any on-chip feature that will operate during
Sleep w ill increase  the current co nsumed during Sl eep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-T i me Clock. Other feat ures may be operati ng that
do not requ ire a dev ice cloc k source (i. e., MSSP slav e,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current”.
2.6 Power-up Delays
Power-up delays are controlled by two timers so th at no
external Reset c ircuitry is required for most  applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum-
stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-12). It is enabled by clearing (= 0) the
PWRTEN Configuration bit. 
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
inco mi ng cl ock  frequ enc y.
There is a delay of interval, TCSD (parameter 38,
Table 28-12), following POR, while the controller
become s ready to ex ecute instruc tions. This del ay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC or internal
oscill ato r  mo des  are  us ed a s th e pri ma ry c lock sourc e.
TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
Oscillator Mode OSC1 Pin OSC2 Pin
INTCKO Floating, pulled by external clock At logic low (clock/4 output)
INTI O Floating, pulled by exter nal clock Configu red as PORTA, bit 6
ECIO, ECPIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
XT and HS Feedback inverter disabled at quiescent 
voltage le vel Feedback inverter disabled at quiescent 
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

3.0 POWER- MANAGED MODES

PIC18F2455/2550/4455/4550 devices offer a total of

seven operating modes for more efficient power

management. These modes provide a variety of

options for selective power conservation in applications

where resources may be limited (i.e., battery-powered

devices).

There are three categories of power-managed modes:

• Run modes

• Idle mo des

• Sleep mode

These categories define which portions of the device

are clo cked and some times , what sp eed. The Ru n and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

block); the Sleep mode does not use a clock source.

The power-managed modes include several

power-saving features offered on previous PIC®

devic es. One is the clock swi tching featur e, offere d in

other PIC18 devices, allowing the controller to use the

Timer1 os cil la tor in pl ac e of the pr im ary osc il lato r. Also

includ ed is the Sleep mod e, off ered by all PIC devices ,

where all device clocks are stopped.

3.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions: if the CPU is to be clocked or not and the

selection of a clock source. The IDLEN bit

(OSCCON<7>) controls CPU clocking, while the

SCS1:SCS0 bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock sources

and af fected mod ules are sum mariz ed in Table 3-1.

3.1.1 CLOCK SOURCES

The SCS1: SCS0 bits allow the sele ction of one o f three

clock sources for power-managed modes. They are:

• The primary clock, as defined by the

FOSC3:FOSC0 Configuration bits

• The secondary clock (the Timer1 oscillator)

• The internal oscillator block (for RC modes)

3.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS1:SCS0 bi ts select the clock sourc e and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a c hange to a power-manag ed mode doe s

not always require setting all of these bits. Many

transitions may be done by changing the oscillator

select bit s, or chang ing th e IDLEN b it, prior t o i ssuing a

SLEEP instruction. If the IDLEN bit is already

configured correctly, it may only be necessary to

perform a SLEEP instruction to switch to the desired

mode.

TABLE 3-1: POWER-MANAGED MODES

Mode OSCCON Bit s Module Clockin g Available Clock and Oscillator Source

IDLEN(1) SCS1:SCS0 CPU Peripherals

Sleep 0N/A Off Off None – all clocks are disabled

PRI_RUN N/A 00 Clocked Clocked Primary – all oscillator modes.

This is the normal full power execution mode.

SEC_RUN N/A 01 Clocked Clock ed Secondary – Timer1 oscillator

RC_RUN N/A 1x Clocked Clocked Internal oscillator block(2)

PRI_IDLE 100Off Clocked Primary – all oscillator modes

SEC_IDLE 101Off Clocked Secondary – Timer1 oscillator

RC_IDLE 11xOff Clocked Internal oscillator block(2)

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

PIC18F2455/2550/4455/4550

3.1.3 CLOCK TRANSITIONS AND

STATUS INDICATORS

The length of the transition between clock sources is

the sum of two cyc les of the o ld clo ck so urce and thre e

to four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Three bits indicate the current clock source and its

status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a

given power-managed mode. When the OSTS bit is

set, the primary clock is providing the device clock.

When th e IOFS bit is set, the INTOSC outp ut is pro vid-

ing a stable 8 MHz clock source to a divider that

actually drives the de vice clock. When the T1RUN bit is

set, the Timer1 oscillator is providing the clock. If none

of these bits are set, then either the INTRC clock

source is cloc ki ng t he device, o r th e IN TOSC so urc e i s

not yet stable.

If the internal oscillator block is configured as the

primary clock source by the FOSC3:FOSC0 Con-

figuration bits, then both the OSTS and IOFS bits may

be set when in PRI_RUN or PRI_IDLE modes. This

indicates that the primary clock (INTOSC output) is

generati ng a stable 8 MHz output. En tering another RC

power-managed mode at the same frequency would

clear the OSTS bit.

3.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEP instruction is executed, the device will

enter the power-managed mo de s pe ci fie d by ID L EN at

that time. If IDLEN has changed, the device will enter

the new power-managed mode specified by the new

setting.

3.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock sour ce .

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution

mode of the microcontroller. This is also the default

mode upo n a devic e Reset un less Two-Speed St art-u p

is enabled (see Section 25.3 “Two-Speed Start-up”

for det ails). In thi s mode, the O STS bit is se t. The IOFS

bit may be set if the internal oscillator block is the

primary clock source (see Section 2.4.1 “Oscillator

Control Register”).

3.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clock ed from the T ime r1 oscill ator . This gives us ers the

option of lower power consumption while still using a

high accuracy clock source.

SEC_RUN mode is en tered by setting the SC S1:SCS0

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 3-1), the primary

oscillator is shut down, the T1RUN bit (T1CON<6>) is

set and the OSTS bit is cleared.

On transitions from SEC_RUN mode to PRI_RUN, the

peripherals and CPU continue to be clocked from the

Timer1 oscillator while the primary clock is started.

When t he prima ry clo ck becom es r eady, a cloc k switc h

back to the primary clock occurs (see Figure 3-2).

When the clock switch is complete, the T1RUN bit is

cleared, the OSTS bit is set and the primary clock is

providing the clock. The IDLEN and SCS bits are not

affected by the wake-up; the Timer1 oscillator

continues to run.

Note 1: Caution should be used when modifyi ng a

single IR CF bit. I f VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode, or

one of the Idle modes, depending on the

setting of the IDLEN bit.

Note: The Timer1 oscillator should already be

running pri or to entering SEC_RUN mod e.

If the T1OSCEN bit is not set when the

SCS1:SCS0 bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled but not yet

running, dev ice cloc ks wi ll be delayed until

the oscillator has started. In such

situations, initial oscillator operation is far

from stable and unpredictable operation

may re sult.

PIC18F2455/2550/4455/4550

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer; the primary clock is shut down.

When usin g the INTRC sourc e, this mode pro vides the

best power cons ervation of all the Ru n modes wh ile still

executing code. It works well for user applications

which are not highly timing sensitive or do not require

high-speed clocks at all times.

If the primary clock source is the internal oscillator

block (either INTRC or INTOSC), there are no distin-

guishable differences between the PRI_RUN and

RC_RUN modes during execution. However, a clock

switch delay will occur during entry to and exit from

RC_RUN mode. Therefore, if the primary cloc k source

is the internal oscillator block, the use of RC_RUN

mode is not recommended.

This mode is entered by setting SCS1 to ‘1’. Although

it is ignored, it is recommended that SCS0 also be

cleared; this is to maintain software compatibility with

future devices. When the clock source is switched to

the INTOSC multiplexer (see Figure 3-3), the primary

oscillator is shut down and the OSTS bit is cleared. The

IRCF bits may be modified at any time to immediately

change the clock speed.

Q4Q3Q2

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2PC

123

n-1

Clock Transition(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q1 Q3 Q4

OSC1

Peripheral

Program PC

T1OSI

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs w ithin 2-4 TOSC.

SCS1:SC S0 bi ts Changed

TPLL(1)

12 n-1n

Clock(2)

OSTS bit Set

Transition

TOST(1)

Note: Cau tio n s hou ld be u se d w he n m odi fy ing a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

PIC18F2455/2550/4455/4550

If the IRCF bits and the INTSRC bit are all clear, the

INTOSC output is not enabled and the IOFS bit will

remain clear; there will be no indication of the current

clock source. The INTRC source is providing the

device clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output), or if INTSRC is set, the

IOFS bit becomes set after the INTOSC output

becomes stable. Clocks to the device continue while

the INTOSC source stabilizes after an interval of

TIOBST.

If th e I RC F b its w ere pr e vi o us ly at a no n - zer o v al u e o r

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, the IOFS bit will

remain set.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multipl exer whil e the primary clo ck is st arted . When th e

primary clock becomes ready, a clock switch to the

primary clock occurs (see Figure 3-4). When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary clock is providing the device

clock. T he IDLEN an d SC S bit s are not af fe cte d by the

switch. The INTRC source will continue to run if either

the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-3: TRAN SITION TIMING TO R C_RUN MODE

FIGURE 3-4: TRAN SITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q4Q3Q2

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transi tion typi ca lly occ urs within 2-4 TOSC.

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTOSC

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock trans iti on typica ll y occurs withi n 2-4 TOSC.

SCS1:SCS0 bits Changed

TPLL(1)

12 n-1n

Clock(2)

OSTS bit Set

Transition

Multiplexer

TOST(1)

PIC18F2455/2550/4455/4550

3.3 Sleep Mode

The power-managed Sleep mode in the

PIC18F2455/2550/4455/4550 devices is identical to

the legac y Sleep mode offered in all other PIC devi ces.

It is entered by clearing the IDLEN bit (the default state

on device R eset) and executing the SLEEP instruction.

This shuts down the selected oscillator (Figure 3-5). All

clock source status bits are cleared.

Entering t he Sleep mode from any other mode does n ot

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the INTRC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake even t occurs i n Sleep mo de (by int errupt,

Reset or WDT time-o ut), the devi ce wil l not be clocke d

until the clock source selected by the SCS1:SCS0 bits

becomes ready (see Figure 3-6), or it will be clocked

from the internal oscillator block if either the

Two-Speed Start-up or the Fail-Safe Clock Monitor are

enabled (see Section 25.0 “Special Features of the

CPU”). In either case, the OSTS bit is set when the

primary clock is providing the device clocks. The

IDLEN and SCS bits are not affected by the wake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to ‘1’ when a SLEEP instructio n is

exec uted, the periph erals will be cl ocked fr om the cl ock

source selected using the SCS1 :SCS0 bits; however , the

CPU will not be clocked. The clock source status bits are

not affected. Setting IDLEN and executing a SLEEP

instr uction pro vides a qu ick method of switchi ng f rom a

given R u n m o de to its co rre sponding Id le mode.

If the WDT is selected, the INTRC source will continue

to operate . If the T imer1 oscillato r is enabled, it will also

continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

tim e-out or a Reset. When a wa ke even t occur s, CPU

execution is delayed by an interval of TCSD

(parameter 38, Table 28-12) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_ RUN mo de). The

IDLEN and SCS bits are not affected by the wake-up.

While i n any Idl e mode or Sl eep mode , a WDT tim e-out

will resul t in a WDT wak e-up to the Run mode curre ntly

specified by the SCS1:SCS0 bits.

FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program PC

PLL Clock

Q3 Q4

Output

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter PC + 6

PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST(1) TPLL(1)

OSTS bit Set

PC + 2

PIC18F2455/2550/4455/4550

3.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation, with its

more accurate primary clock source, since the clock

source does not have to “warm up” or transition from

another oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the C PU is disab led, th e periphe rals c ontinu e

to be clocked from the primary clock source specified

by the FOSC3:FOSC0 Configuration bits. The OSTS

bit remains set (see Figure 3-7).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the

wake-up, the OSTS bit remains set. The IDLEN and

SCS bits are not affected by the wake-up (see

Figure 3-8).

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator . This mode is entered from SEC_RUN by set-

ting the IDLEN bit and exec uting a SLEEP instruction. If

the devi ce is in another Ru n mode, set IDLEN first, then

set SCS1:SCS0 to ‘01’ an d ex ec ut e SLEEP. When the

clock source is switched to the Timer1 oscillator, the

primary oscillator is shut down, the OSTS bit is cleared

and the T1RUN bit is set.

When a w ake event o ccurs, the pe ripherals contin ue to

be clocked from the Timer1 oscillator. After an interval

of TCSD followi ng the wa ke eve nt, the CPU b egins exe-

cuting c ode being c locked by the Timer1 oscillat or . Th e

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 3-8).

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when the

SLEEP instruction is executed, the SLEEP

instruction will be ignored and entry to

SEC_IDLE mode will not occur. If the

Timer1 oscillator is enabled but not yet

running, peripheral clocks will be delayed

until the oscillator has started. In such

situations, initial oscillator operation is far

from stable and unpredictable operation

may re sult.

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Wake Event

TCSD

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 41
PIC18F2455/2550/4455/4550
3.4.3 RC_IDLE MODE
In RC_I DL E m od e, t he  C PU  is  d is abl ed  but  th e p erip h-
erals  co nti nue  to b e c loc ke d fro m the internal oscilla tor
block using the INTOSC multiplexer. This mode allows
for cont rollable  power c onservation  during  Idle periods .
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device  is in a nother Run m ode, first set  IDLEN, th en set
the SCS1 bit and execute SLEEP. Although its value is
ignored,  it is re comm ended  that SC S0 also  be cle ared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits be for e ex ecut in g the SLEEP instruction. When the
clock source is switched to  the INTOSC multiplex er, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 28-12). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled , the I OFS bit wi ll remain  clear and t here wil l be
no indication of the current clock source.
When a w ake event o ccurs, the pe ripherals  continue  to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins
executing code being clocked by the INTOSC multi-
plexer .  The IDLEN and SCS bit s are not affected by  the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”). 
3.5. 1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device  to exit  from an Id le mod e, or the  Sleep mo de, to
a Run mode. To enable this functionality, an interrupt
source m us t  be en ab led  by s etti ng i t s enable bit in on e
of the INTCON or PIE registers. The exit sequence is
initiate d when the c orresponding  interrupt flag  bit is set.
On all ex its from Idl e or Sleep mod es by interrupt,  code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed  delay of interval TCSD follo w in g th e w ak e ev en t
is required when leaving Sleep and Idle modes. This
del ay is required for the CPU t o prepare  for execut ion.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If th e dev ice is  not ex ecut ing  code ( all  Idle mo des a nd
Sleep mod e), th e time-o ut w ill res ul t in a n ex it fro m the
power-managed mode (see Section 3.2 “Run
Modes” a nd Section 3.3 “Sleep Mode ”). If the devic e
is executing code (all Run modes), the time-out will
result in a WDT Reset (see  Section 25.2 “Watchdog
Timer (WDT)”). 
The WDT timer and postscaler are cleared by execut-
ing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.
3.5. 3 EXIT BY  RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins e xe cu ting code. If th e in ternal oscil lat or bl oc k i s
the new clock source, the IOFS bit is set instead. 
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2 .
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 25.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 25.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the  Re set  sourc e ha s cle ared. Execution  is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.

PIC18F2455/2550/4455/4550
DS39632D-page 42 Preliminary © 2007 Microchip Technology Inc.
3.5.4 EXIT WITHOUT AN OSCILLATOR 
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source 
is not stopped; and
• the primary clock source is not any of the XT or 
HS modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an  oscillator s tart-up dela y (EC and any  internal
oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)  
Microcontroller Clock Source  Exit Delay Clock Ready Status 
Bit (OSCCON)
Before W ake -up After Wak e-up
Primary Device Clock
(PRI_IDLE mode)
XT, HS
None OSTS
XTPLL, HSPLL
EC
INTOSC(3) IOFS
T1OSC or INTRC(1)
XT, HS TOST(4)
OSTSXTPLL, HSPLL TOST + trc(4)
EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
INTOSC(3)
XT, HS TOST(4)
OSTSXTPLL, HSPLL TOST + trc(4)
EC TCSD(2)
INTOSC(3) None IOFS
None
(Sleep mode)
XT, HS TOST(4)
OSTSXTPLL, HSPLL TOST + trc(4)
EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (pa rameter  38, Table 28-12) is  a required del ay when waki ng from Sleep an d all Idle mod es and runs 
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer period (parameter 32, Table 28-12). trc is the PLL lock time-out 
(parameter F12, Table 28-9); it is also designated as TPLL.
5: Execution continues during TIOBST (parameter 39, Ta ble 28-12), the INTOSC stabilization period.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 43
PIC18F2455/2550/4455/4550
4.0 RESET
The PIC18F2455/2550/4455/4550 devices differentiate
between various kin ds of R eset: 
a) Power-on Reset (POR) 
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes 
d) Watchdog Timer (WDT) Reset (during 
execution)
e) Programmable Brown-out Reset (BOR) 
f) RESET Inst ruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BO R and  cov ers the  ope rati on of the variou s
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Re se ts ar e co v ere d i n Section 25.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is sh own i n Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indic ate that a spec ific Reset  event has oc curred. In
most ca ses, these b its can o nly be clear ed by the e vent
and mus t be s et b y the  app lic at ion  afte r the e ve nt. Th e
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT        
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC
(1)
POR Pulse
OST
10-Bit Ripple Counter
PWRT
Chip_Reset
11- Bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer S tack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 μs
MCLRE

PIC18F2455/2550/4455/4550

R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0

IPEN SBOREN —RITO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit(1)

If BOREN1:BOREN0 = 01:

1 = BOR is enabled

0 = BOR is disabled

If BOREN1:BOREN0 = 00, 10 or 11:

Bit is disabled and read as ‘0’.

bit 5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)

0 = The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instructi on

0 = Set by executi on of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit(2)

1 = A Power-on Reset has not occurred (set by firmware only)

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this

Note 1: It is recommende d that the PO R bit be set after a Power-on Reset has been detected so that subsequent

Power-on Resets may be detected.

2: Brown-out Res et is sai d to ha ve occ urre d when BO R is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after POR).

PIC18F2455/2550/4455/4550

4.2 Master Clear Reset (MCLR)

The MCLR pin provides a method for triggering an

external Reset of the device. A Reset is generated by

hold ing the pin low . T hese devi ces have a noise fi lter in

the MCLR Reset path which detects and ignores small

pulses.

The MCLR pin i s not dri ven l ow b y any i nter nal Res ets ,

including the WDT.

In PIC18F2455/2550/4455/4550 devices, the MCLR

input can be disabled with the MCLRE Configuration

bit. When MC LR is disabled, the pin becomes a digital

input. See Section 10.5 “PORTE, TRISE and LATE

Registers” for more information.

4.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advant age of the POR circuitry, tie the MCLR pin

through a resistor (1 kΩ to 10 kΩ) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. A minimum rise rate for

VDD is specified (parameter D004, Section 28.1 “DC

Characteristics”). For a slow rise time, see Figure 4-2.

When the device start s normal operation (i.e ., ex its the

Reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

POR events are captured by the POR bit (RCON<1>).

The state of the bit is set to ‘0’ whe never a POR occurs;

it does not change for any other Reset event. POR is

not reset to ‘1’ by any hardware event. To capture

multiple events, the user manually resets the bit to ‘1’

in software following any POR.

FIGURE 4-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, i n the event

of MCLR/VPP pin breakdown, due to Electro-

static Discharge (ESD) or Electrical

Overs tress (EOS).

VDD

MCLR

PIC18FXXXX

VDD

PIC18F2455/2550/4455/4550

4.4 Brown-out Reset (BOR)

PIC18F2455/2550/4455/4550 devices implement a

BOR circuit that provides the user with a number of

configuration and power-saving options. The BOR

is controlled by the BORV1:BORV0 and

BOREN1:BOREN0 Configuration bits. There are a tot al

of four BOR configurations which are summarized in

Table 4-1.

The BOR t hreshold is set b y the BOR V1:BOR V0 bi ts. If

BOR is enabled (any values of BOREN1:BOREN0

except ‘00’), any drop of VDD below VBOR (paramet er

D005, Section 28.1 “DC Characteristics”) for

greater than TBOR (parameter 35, Table 28-12) will

reset the device. A Reset may or may not occur if VDD

falls below VBOR for less than TBOR. The chip will

remain in Brown-out Reset until VDD rises above VBOR.

If the Po wer-up T imer is enabled, i t will be inv oked after

VDD rises above VBOR; it then will keep the chip in

Reset for an additional time delay, TPWRT

(parameter 33, Table 28-12). If VDD drops below VBOR

while the Power-up Timer is running, the chip will go

back into a Brown-out Reset and the Power-up Timer

will be initialized. Once VDD rises above VBOR, the

Power-up Timer will execute the additional time delay.

BOR and the Power-on Timer (PWRT) are

independently configured. Enabling BOR Reset does

not automatically enable t he PW RT.

4.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be

enabled or disabled by the user in software. This is

done with the control bit, SBOREN (RCON<6>).

Setting SBOREN enables the BOR to function as

previously described. Clearing SBOREN disables the

BOR entirely. The SBOREN bit operates only in this

mode; oth erwise, it is read as ‘0’.

Placing the BOR under software control gives the user

the additional flexibility of tailoring the application to its

environ me nt w it hou t ha vi ng to reprogram the de vi ce to

change BOR configuration. It also allows the user to

tailor device power consumption in software by elimi-

nating the incremental current that the BOR consumes.

While the BOR current is typically very small, it may

have some impact in low-power applications.

4.4.2 DETECTING BOR

When BO R is enab led, the BO R bit always resets to ‘0’

on any BOR or POR event. This makes it difficult to

determin e if a BOR eve nt ha s occ urre d jus t by reading

the state of BOR alone. A more reliable method is to

simultaneously check the state of both POR and BOR.

This as sumes that t he POR bit is re set to ‘1’ in softwa re

immediately after any POR event. IF BOR is ‘0’ while

POR is ‘1’, it can be reli ably assumed th at a BOR event

has occurred.

4.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains

under hardware control and operates as previously

described. Whenever the device enters Sleep mode,

howev er, the BOR is automati ca lly dis abl ed . When the

device returns to any other operating mode, BOR is

automatically re-enabled.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it save s additional po wer in Sleep mode

by eliminating the small incremental BOR current.

TABLE 4-1: BOR CONFIGURATIONS

Note: Even when BOR is under softwa re control,

the BOR Reset voltage level is still set by

the BORV1:BORV0 Configuration bits. It

cannot be changed in software.

BOR Configuration Status of

SBOREN

(RCON<6>) BOR Operation

BOREN1 BOREN0

00Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.

01Available BOR enabled in software; operation controlled by SBOREN.

10Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep

mode.

11Unavailable BOR enabled in hardware; must be disabled by reprogramming the

Configu ration bits.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 47
PIC18F2455/2550/4455/4550
4.5 Device Reset Timers
PIC18F2455/2550/4455/4550 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
execut ed. The se tim ers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-o ut
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Ti mer (PWRT) of the PIC18F2455/2550/
4455/4550 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs=65.6ms.
While the PWRT is counting, the device is held in
Reset.
The powe r-up tim e de lay  depe nd s on the  INTRC  cl oc k
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 (Table 28-12)
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit. 
4.5.2 OSCIL LAT OR START-UP 
TIMER (OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 28-12). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, HS and
HSPLL modes and only on Power-on Reset or on exit
from most pow er-manag ed mod es .
4.5.3 P LL LOCK TIME- OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to  p rov ide  a fixed  tim e-o ut  tha t is suf fi ci ent  fo r th e
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR condition has cleared, PWRT
time-out is invoked (if enabled). 
2. Then, the OST is activated. 
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figure s 4-3 through 4-6 also apply
to devices operating in XT mode. For devices in RC
mode and with the PWRT disabled, on the other hand,
there will be no time-out at all.
Since the  time-outs  occur from the PO R pulse, if MCLR
is kept  low  long e nough,  all ti me-outs wi ll exp ire. Brin g-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS  
Oscillator
Configuration
Power-up(2) and Brown-out Exit from 
Power-Managed Mode
PWRTEN = 0PWRTEN = 1
HS, XT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
HSPLL, XTPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
EC, ECIO 66 ms(1) ——
ECPLL, ECPIO 66 ms(1) + 2 ms(2) 2 ms(2) 2 ms(2)
INTIO, INTCKO 66 ms(1) ——
INTHS, INTXT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.

PIC18F2455/2550/4455/4550

FIGURE 4-3: T IME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTER N AL PO R

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

PIC18F2455/2550/4455/4550

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

INTER N AL PO R

PWRT TIME-OUT

OST TIME- OUT

INTERNAL RESET

0V 1V 5V

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-O UT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the Power-up Timer.

PIC18F2455/2550/4455/4550

4.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BO R, are set or cle ared dif ferently i n dif ferent

Reset situations as indicated in Table 4-3. These bits

are used in software to determine the nature of the

Reset.

Table 4-4 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition Program

Counter

RCON Register STKPTR Register

SBOREN RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 1 11100 0 0

RESET Instruction 0000h u(2) 0uuuu u u

Brown-out 0000h u(2) 111u0 u u

MCLR during Power-Managed

Run modes 0000h u(2) u1uuu u u

MCLR during Power-Managed

Idle modes and Sleep mode 0000h u(2) u10uu u u

WDT T ime-out during Full Power

or Power-Managed Run modes 0000h u(2) u0uuu u u

MCLR during Full Power

Execution 0000h u(2) uuuuu u u

Stack Full Reset (STVREN = 1) 0000h u(2) uuuuu 1 u

Stack Underflow Reset

(STVREN = 1)0000h u(2) uuuuu u 1

Stack Underflow Error (not an

actual Reset, STVREN = 0)0000h u(2) uuuuu u 1

WDT Time-out during

Power-Managed Idle or Sleep

modes

PC + 2 u(2) u00uu u u

Interrupt Exit from

Power-Managed modes PC + 2(1) u(2) uu0uu u u

Legend: u = unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

inter rupt ve cto r (008h or 0018 h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

PIC18F2455/2550/4455/4550

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-ou t Reset

MCLR Resets,

WDT R eset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

TOSU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---0 uuuu(1)

TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1)

TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1)

STKPTR 2455 2550 4455 4550 00-0 0000 uu-0 0000 uu-u uuuu(1)

PCLATU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC + 2(3)

TBLPTRU 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu

TBLPTRH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

TBLPTRL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

PRODH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuuu(2)

INTCON2 2455 2550 4455 4550 1111 -1-1 1111 -1-1 uuuu -u-u(2)

INTCON3 2455 2550 4455 4550 11-0 0-00 11-0 0-00 uu-u u-uu(2)

INDF0 2455 2550 4455 4550 N/A N/A N/A

POSTINC0 2455 2550 4455 4550 N/A N/A N/A

POSTDEC0 2455 2550 4455 4550 N/A N/A N/A

PREINC0 2455 2550 4455 4550 N/A N/A N/A

PLUSW0 2455 2550 4455 4550 N/A N/A N/A

FSR0H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu

FSR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

WREG 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 2455 2550 4455 4550 N/A N/A N/A

POSTINC1 2455 2550 4455 4550 N/A N/A N/A

POSTDEC1 2455 2550 4455 4550 N/A N/A N/A

PREINC1 2455 2550 4455 4550 N/A N/A N/A

PLUSW1 2455 2550 4455 4550 N/A N/A N/A

FSR1H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu

FSR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

BSR 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.

Note 1: When the w ake-up is d ue to an int errup t and the G IEL or G IEH bit is set, the TO SU, TOSH and T O SL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.

5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

PIC18F2455/2550/4455/4550

INDF2 2455 2550 4455 4550 N/A N/A N/A

POSTINC2 2455 2550 4455 4550 N/A N/A N/A

POSTDEC2 2455 2550 4455 4550 N/A N/A N/A

PREINC2 2455 2550 4455 4550 N/A N/A N/A

PLUSW2 2455 2550 4455 4550 N/A N/A N/A

FSR2H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu

FSR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS 2455 2550 4455 4550 ---x xxxx ---u uuuu ---u uuuu

TMR0H 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

TMR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu

OSCCON 2455 2550 4455 4550 0100 q000 0100 00q0 uuuu uuqu

HLVDCON 2455 2550 4455 4550 0-00 0101 0-00 0101 u-uu uuuu

WDTCON 2455 2550 4455 4550 ---- ---0 ---- ---0 ---- ---u

RCON(4) 2455 2550 4455 4550 0q-1 11q0 0q-q qquu uq-u qquu

TMR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 2455 2550 4455 4550 0000 0000 u0uu uuuu uuuu uuuu

TMR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

PR2 2455 2550 4455 4550 1111 1111 1111 1111 1111 1111

T2CON 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

SSPBUF 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

SSPCON1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

SSPCON2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

ADRESH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu

ADCON1 2455 2550 4455 4550 --00 0qqq --00 0qqq --uu uuuu

ADCON2 2455 2550 4455 4550 0-00 0000 0-00 0000 u-uu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-ou t Reset

MCLR Resets,

WDT R eset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.

Note 1: When the w ake-up is d ue to an int errup t and the G IEL or G IEH bit is set, the TO SU, TOSH and T O SL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.

5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

PIC18F2455/2550/4455/4550

CCPR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu

2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

CCPR2H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

BAUDCON 2455 2550 4455 4550 0100 0-00 0100 0-00 uuuu u-uu

ECCP1DEL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

ECCP1AS 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

CVRCON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

CMCON 2455 2550 4455 4550 0000 0111 0000 0111 uuuu uuuu

TMR3H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

T3CON 2455 2550 4455 4550 0000 0000 uuuu uuuu uuuu uuuu

SPBRGH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

SPBRG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

RCREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

TXREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

TXSTA 2455 2550 4455 4550 0000 0010 0000 0010 uuuu uuuu

RCSTA 2455 2550 4455 4550 0000 000x 0000 000x uuuu uuuu

EEADR 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

EEDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

EECON2 2455 2550 4455 4550 0000 0000 0000 0000 0000 0000

EECON1 2455 2550 4455 4550 xx-0 x000 uu-0 u000 uu-0 u000

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-ou t Reset

MCLR Resets,

WDT R eset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.

Note 1: When the w ake-up is d ue to an int errup t and the G IEL or G IEH bit is set, the TO SU, TOSH and T O SL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.

5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

PIC18F2455/2550/4455/4550

IPR2 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu

PIR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(2)

PIE2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

IPR1 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu

2455 2550 4455 4550 -111 1111 -111 1111 -uuu uuuu

PIR1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(2)

2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

PIE1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

OSCTUNE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu

TRISE 2455 2550 4455 4550 ---- -111 ---- -111 ---- -uuu

TRISD 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu

TRISC 2455 2550 4455 4550 11-- -111 11-- -111 uu-- -uuu

TRISB 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu

TRISA(5) 2455 2550 4455 4550 -111 1111(5) -111 1111(5) -uuu uuuu(5)

LATE 2455 2550 4455 4550 ---- -xxx ---- -uuu ---- -uuu

LATD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

LATC 2455 2550 4455 4550 xx-- -xxx uu-- -uuu uu-- -uuu

LATB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

LATA(5) 2455 2550 4455 4550 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)

PORTE 2455 2550 4455 4550 0--- x000 0--- x000 u--- uuuu

PORTD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 2455 2550 4455 4550 xxxx -xxx uuuu -uuu uuuu -uuu

PORTB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(5) 2455 2550 4455 4550 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-ou t Reset

MCLR Resets,

WDT R eset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.

Note 1: When the w ake-up is d ue to an int errup t and the G IEL or G IEH bit is set, the TO SU, TOSH and T O SL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.

5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

PIC18F2455/2550/4455/4550

UEP15 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP14 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP13 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP12 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP11 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP10 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP9 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP8 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP7 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP6 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP5 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP4 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP3 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP2 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP1 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UEP0 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu

UCFG 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu

UADDR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

UCON 2455 2550 4455 4550 -0x0 000- -0x0 000- -uuu uuu-

USTAT 2455 2550 4455 4550 -xxx xxx- -xxx xxx- -uuu uuu-

UEIE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu

UEIR 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu

UIE 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

UIR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu

UFRMH 2455 2550 4455 4550 ---- -xxx ---- -xxx ---- -uuu

UFRML 2455 2550 4455 4550 xxxx xxxx xxxx xxxx uuuu uuuu

SPPCON 2455 2550 4455 4550 ---- --00 ---- --00 ---- --uu

SPPEPS 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu

SPPCFG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

SPPDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-ou t Reset

MCLR Resets,

WDT R eset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.

Note 1: When the w ake-up is d ue to an int errup t and the G IEL or G IEH bit is set, the TO SU, TOSH and T O SL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt

vector (0008h or 0018h).

4: See Table 4-3 for Reset value for specific condition.

5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not

enabled as PORTA pins, they are disabled and read ‘0’.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

5.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard arc hitecture devices, the da ta and progra m

memories use separate busses; this allows for con-

current access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is ad dressed and accessed

through a set of control registers.

Additional detailed information on the operation of the

Flash program memory is provided in Section 6.0

“Flash Program Memory”. Data EEPROM is

discussed separately in Section 7.0 “Data EEPROM

Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter which is capable of addressing a 2-Mbyte

progra m memory sp ace. Acces sing a lo cation b etween

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s (a

NOP instr ucti on).

The PIC18F2455 and PIC18F4455 each have

24 Kbytes of Flas h memory an d can store up to 12,288

single-word instructions. The PIC18F2550 and

PIC18F4550 each have 32 Kbytes of Flash memory

and can store up to 16,384 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

The program memory maps for PIC18FX455 and

PIC18FX550 devices are shown in Figure 5-1.

FIGURE 5-1: PROGRAM MEMORY MAP AND ST ACK FOR PIC 18F2455/2550/4455/ 4550 DEVICES

PC<20:0>

Stack Level 1

•

S tack Level 31

Reset Vector

Low Priority Interrupt Vector

•

CALL, RCALL, RETURN,

RETFIE, RETLW, CALLW, 21

0000h

0018h

On-Chip

Program Memory

High Priority Interrupt Ve ctor 0008h

User Memory Space

1FFFFFh

6000h

5FFFh

Read ‘0’

200000h

PC<20:0>

Stack Level 1

•

S tack Level 31

Reset Vector

Low Priority Interrupt Vector

•

CALL, RCALL, RETURN,

RETFIE, RETLW, CALLW, 21

0000h

0018h

8000h

7FFFh

On-Chip

Program Mem ory

High Priority Interrupt Vect or 0008h

User Memory Space

Read ‘0’

1FFFFFh

200000h

PIC18FX455 PIC18FX550

ADDULNK, SUBULNK ADDULNK, SUBULNK

PIC18F2455/2550/4455/4550

5.1.1 PROGRAM COUNTER

The Progra m Counter (PC) s pecifies the address of the

instruction to fetch for execution. The PC is 21 bit s wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and wr itable. Th e high byt e, or PCH regi ster, con tains

the PC<1 5:8> bits; it is not directly re adable or writ able.

Update s to the PCH register are performe d through the

PCLATH register. The upper byte is called PCU. This

directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are tran sferred to PCL ATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 5.1.4.1 “Computed

GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of PCL is fixed to

a value of ‘0’. The PC increments by 2 to address

sequential instructions in the program memory.

The CALL, RCALL and GOTO program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The return address s t ac k al low s any comb in atio n of up

to 31 program calls and interrupts to occur. The PC is

pus hed o nt o th e stac k when a CALL or RCALL instruc-

tion is executed or an interrupt is Acknowledged. The

PC value i s pulled off the stac k on a RETURN, RETLW or

a RETFIE instruction. PCLATU and PCLATH are not

affected by any of the RETURN or CALL instructio ns.

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data sp ace. The Stack Point er

is readable and writable and the address on the top of

the stack is readable and writable through the

Top-of-Stack Special Function Registers. Data can also

be pushed to, or popped from the stack, using these

registers.

A CALL type inst ruct ion cause s a pus h onto t he stac k.

The Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURN type instruc ti on c au se s

a pop from the stack. The contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a Res et v alu e. Status bit s in dic ate if the st ac k i s

full, has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is

readable and writable. A set of three registers,

TOSU:T OSH:T OSL, hold the content s of the st ack loca-

tion pointed to by the STKP TR register (Figure 5-2). This

allows users to implement a s oftware stack if nec essary.

After a CALL, RCALL or interrupt, the software can read

the pushed value by reading the TOSU:TOSH:TOSL

registers. These val ues can be placed on a user-defined

software stack. At return time, the software can return

these values to T OSU:T O SH:T O SL and do a return.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack<20:0>

Top-of-Stack 000D58h

TOSLTOSHTOSU 34h1Ah00h STKPTR<4:0>

Top-of-Stack Regis ters Stack Pointer

PIC18F2455/2550/4455/4550

5.1.2.2 R eturn Stack Pointer (STKPTR)

The STKP TR register (Regis ter 5-1) conta ins the S tack

Pointer value, the STKFUL (Stack Full) status bit and

the STKU NF (Stack Underflow) status bit. Th e v al ue of

the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. On Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System (RTOS) for return stack maintenance.

After t he PC is pus hed o nto the stac k 31 times (witho ut

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack

Overflow Reset Enable) Configuration bit. (Refer to

Section 25.1 “Configurat ion Bits” for a desc ription of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is clea red, the STKFUL bi t will be se t on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and the STKPTR will remain at 31.

When the stack has been popped enough times to

unload th e stack, the ne xt pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

5.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability to pus h values onto the st ac k and pull value s off

the stack, without disturbing normal program execu-

tion, is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

T OSU, T OSH and T OS L can be m odifie d to plac e dat a

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: St ac k Unde rflo w Fla g bit(1)

1 = Stack underflow occurred

0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F2455/2550/4455/4550

5.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow

conditions are enabled by setting the STVREN bit in

Config ura tion Regi ster 4L. When STVREN i s set, a ful l

or underflow condition will set the appropriate STKFUL

or ST KUNF bi t and th en caus e a devi ce Rese t. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by user software or a Power-on Reset.

5.1.3 FAST REGISTER STACK

A Fast Register Stack is provided for the STATUS,

WREG and BSR registers to provide a “fast return”

option for interrupts. Each stack is only one level deep

and is neither readable nor writable. It is loaded with the

current value of the corresponding register when the

processor vectors for an interrupt. All interrupt sources

will push v alue s in to th e stac k regi ste rs. T he v alues in

the regi st ers ar e then load ed ba ck i nto th eir a ssociate d

registers if the RETFIE, FAST instruction is used to

return from the interrupt.

If both low and high priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low priority interrupts. If a high priority interrupt occurs

while servicing a low priority interrupt, the stack register

values stored by the low priority interrupt will be

overwritten. In these cases, users must save the key

registers in software during a low priority interrupt.

If interrupt pri ority is not used, all interrupts may use the

Fast Register Stack for returns from interrupt. If no

interrupts are used, the Fast Register Stack can be

used to restore the STATUS, WREG and BSR registe rs

at th e end of a subro utine cal l. To use the Fast R egister

Stack for a subroutine call, a CALL label, FAST

instruction must be executed to save the STATUS,

WREG and BSR registers to the Fast Register S t ack. A

RETURN, FAST instruction is then executed to restore

these registers from the Fast Register Stack.

Example 5-1 shows a source code example that uses

the Fast Register Stack during a subroutine call and

return.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

5.1.4 LOOK-UP TABLES IN PROGRAM

MEMORY

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1 Computed GOTO

A comput ed GOTO i s a cc om pli sh ed b y a ddi ng a n offset

to the program counter. An example is shown in

Example 5-2.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nn instructions. The

W register is loa ded with an offset int o the ta ble befo re

executi ng a c al l to tha t t a ble . Th e fi rst ins tru cti on o f th e

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be mu ltiples of 2 (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 5-2: COMPUTED GOTO USING

AN OFFSET VALUE

5.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory

allow s two bytes of dat a to be stored in each instruc tion

location.

Look-up table data may be stored two bytes per

program word by using table reads and writes. The

Table Pointer (TBLPTR) register specifies the byte

address and the Table Latch (TABLAT) register

cont ains the da ta that is read from o r written to pro gram

memory. Data is transferred to or from program

memory one byte at a time.

Table read and table write operations are discussed

further in Section 6.1 “Table Reads and Table

Writes”.

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1 •

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE

ORG nn00h

TABLE ADDWF PCL

RETLW nnh

PIC18F2455/2550/4455/4550

5.2 PIC18 Instruction Cycle

5.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Interna lly, the pro gram counter i s

incremented on every Q1; the instruction is fetched

from the progr am mem ory and lat ched int o the Instru c-

tion R egister (IR) d uring Q4. The ins truction is dec oded

and executed during the following Q1 through Q4. The

clocks and instruction execution flow are shown in

Figure 5-3.

5.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instructio n fetch and execute are pipe-

lined in such a manner that a fetch takes one instructio n

cycle, while the decode and execute takes another

instr ucti on cycl e. H oweve r, due to the pip eli ning, ea ch

instruction effectively executes in one cycle. If an

instruc tion causes the program counter to change (e.g.,

GOTO), then two cycles are required to complete the

instruction (Example 5-3).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q 3 and Q4 c ycles. Data mem ory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 5-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKO

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute IN ST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute IN ST (PC + 2)

Internal

Phase

Clock

Note: All ins truc ti ons are s in gle cy cl e, except for any prog ram bran ch es . Thes e t a ke two cycles si nce the fetc h

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fet ch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

PIC18F2455/2550/4455/4550

5.2.3 INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even add ress (LSb = 0). To maintain alignment

with i nstruction bo undaries , the PC i ncrement s in s teps

of 2 a nd the LSb wi ll always read ‘0’ (see Section 5.1.1

“Program Counter”).

Figure 5-4 show s an example of h ow in struction w ord s

are stored in the program memory.

The CALL and GOTO instructions have the absolute

program memory address embedded into the instruc-

tion. Since instructions are always stored on word

boundaries, the data contained in the instruction is a

word address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 5-4 shows how the

instruction, GOTO 0006h, is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same ma nner. The

of fset value stored in a branch instruction represent s the

number of single-word instructions that the PC will be

offset by. Section 26.0 “Instruction Set Summary”

provides further details of the instruction s et.

FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

5.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the se cond wor d of th e inst ruct ions al ways has

‘1111’ as its four M ost Si gnifican t bit s; the ot her 12 bit s

are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction

specifies a special form of NOP. If the instruction is

executed in proper sequence, immediately after the

first w ord, th e dat a i n t he se cond word is acc essed and

used by the instruction sequence. If the first word is

skipped for some reason and the second word is

executed by itself, a NOP is executed instead. This is

necessary for cases when the two-word instruction is

prec ed ed b y a co nd i ti ona l in st ru ct i on t h at c han ge s t he

PC. Example 5-4 shows how thi s works.

EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

Word Address

LSB = 1LSB = 0↓

Program Memory

Byte Locations → 000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

Note: See Section 5.5 “Program Memory and

the Extended Instruction Set” for

information on two-word instruction in the

extended instruction set.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F2455/2550/4455/4550

5.3 Data Memory Organization

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory space is divided into as many as

16 banks that contain 256 bytes each.

PIC18F2455/2550/4455/4550 devices implement eight

complete banks, for a total of 2048 bytes. Figure 5-5

show s the dat a memory o rga ni za ti on for the devices .

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and per ipheral functio ns, while GP Rs are used for dat a

storage and scratchpad operations in the user’s

applic ation. Any read of an unim plemente d locat ion will

read as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

To ensure that commonly used registers (SFRs and

select GP Rs) c an b e ac cess ed i n a singl e c ycle, PIC1 8

devices impl em ent an Ac ce ss Bank. This i s a 256 -by te

memor y space that provid es fa st acc ess to SFRs and

the lower portion of GPR Bank 0 without using the

BSR. Section 5.3.3 “Access Bank” provides a

detailed description of the Access RAM.

5.3.1 USB RAM

Banks 4 through 7 of the data memory are actually

mapped to special dual port RAM. When the USB

module is disabled, the GPRs in these banks are used

like any other GPR in the data memory space.

When the USB module is enabled, the memory in these

banks is allocated as buffer RAM for USB operation.

This area is shared between the microcontroller core

and the USB Serial Interface Engine (SIE) and is used

to transfer data directly between the two.

It is theore tically possib le to use the areas of USB RAM

that are not allocated as USB buffers for normal

scrat chpad mem ory or ot her va riab le s tora ge. In pr ac-

tice, the dyn am ic natu re of b uffer alloc at ion mak es thi s

risky at best. Additionally , Bank 4 is used for USB buffer

management when the module is enabled and should

not be used for any other purposes during that time.

Additional information on USB RAM and buffer

operation is provided in Section 17.0 “Universal

Serial Bus (USB)”.

5.3.2 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address doe s no t ne ed to be provided for each read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Most in struct ions in th e PIC18 instruct ion se t make us e

of the Ban k Pointer , kno wn as the Bank Select Regist er

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

eight Least Signific ant bits. Only the four lower bits of

the BSR are implemented (BSR3:BSR0). The upper

four bits are unused; they will always read ‘0’ and can-

not be written to. The BSR can be loaded directly by

using the MOVLB instruction.

The value of the BSR indicates the bank in data

memory. The e ight bit s in the instru ction sho w the loca-

tion in the b ank and can be thought of as an of fset from

the bank’s lower boundary. The relationship between

the BSR’s value and the bank division in data memory

is sh own i n Figure 5-6.

Since up to sixteen registers may share the same

low-order address, the user must always be careful to

ensure th at the proper b ank is sele cted before pe rform-

ing a data read or write. For example, writing what

should be program data to an 8-bit address of F9h,

while the BSR is 0Fh, will end up resetting the program

counter.

While any bank can be s el ec ted, only thos e banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 5-5 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source a nd target reg isters. This i nstruction ig nores the

BSR comple tely when it ex ecutes. All othe r instruction s

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their targ et regis te rs.

Note: The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 5.6 “Data Memory and the

Extended Instruction Set” for more

information.

PIC18F2455/2550/4455/4550

FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2455/2550/4455/4550 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access Bank

When a = 0:

The BSR is ignored and the

Access Bank is used.

The first 96 bytes are

general purpose RAM

(from Bank 0).

The remain ing 160 byt es are

Special Function Registers

(from Bank 15).

When a = 1:

The BSR specifies the bank

used by the instruction.

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

Access RAM High

Access RA M Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

800h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

GPR(1)

GPR

GPR(1)

FFh

= 0011

= 0100

= 0101

= 0111

= 1000

Unused

Read as 00h

= 1110

Note 1: T hese banks al so serve as RAM buf fer for USB operati on. See Section 5.3.1 “USB RAM” for more

information.

Unused

PIC18F2455/2550/4455/4550

FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

5.3.3 ACCESS BANK

While the use of the BSR, with an embedded 8-bit

address, allows users to address the entire range of

data mem ory, it al so mean s th at the user must a lwa ys

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

To streamlin e access for the most com monly used dat a

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 96 bytes of

memory (00h-5Fh) in Bank 0 and the last 160 bytes of

memory (60 h-FFh) in Block 15 . The lower half is known

as the “Access RAM” and is composed of GPRs. The

upper half is where the device’s SFRs are mapped.

These two areas are mapped contiguously in the

Access Bank and can be addressed in a linear fashion

by an 8-bit addre ss (Figure 5-5).

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, t he in st ru ct i on

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored enti r el y.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle without

updating the BSR first. For 8-bit addresses of 60h and

above, t his mean s that use rs can ev aluate an d opera te

on SFRs more efficiently. The Access RAM below 60h

is a goo d place for da ta values th at the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). T his is di scus sed in mo re deta il

in Section 5.6.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

5.3.4 GENERAL PURPOSE

PIC18 devices may have banked memory in the GPR

area. T his is da t a R AM which is ava il abl e fo r us e by al l

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom

of the SFR area. GPRs are not initialized by a

Power-on Reset and are unchanged on all other

Resets.

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

From Opcode(2)

0000

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Bank 3

through

Bank 13

0011 11111111

BSR(1)

PIC18F2455/2550/4455/4550

5.3.5 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implem ented as st atic RAM in th e dat a me mory sp ac e.

SFRs st art at th e top of dat a memory an d extend do wn-

ward to occupy the top segment of Bank 15, from F60h

to FFFh. A list of these registers is given in Table 5-1

and Table 5-2.

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The Reset and interrupt registers

are described in their respective chapters, while the

ALU’s STATUS register is described later in this

section. Registers related to the operation of a

peripheral feature are described in the chapter for that

peripheral.

The SFRs are typically distributed among the

periphera ls w ho se fun cti ons th ey c ontr ol. U nus ed SFR

locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2455/2550/4455/4550 DEVICES

Address Name Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh UEP15

FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh UEP14

FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh UEP13

FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) F7Ch UEP12

FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh UEP11

FFAh PCLATH FDAh FSR2H FBAh

CCP2CON

F9Ah —(2) F7Ah UEP10

FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) F79h UEP9

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) F78h UEP8

FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h —(2) F77h UEP7

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE(3) F76h UEP6

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) F75h UEP5

FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h UEP4

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h UEP3

FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h UEP2

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) F71h UEP1

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) F70h UEP0

FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) F6Fh UCFG

FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) F6Eh UADDR

FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) F6Dh UCON

FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) F6Ch USTAT

FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC F6Bh UEIE

FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah UEIR

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA F69h UIE

FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) F68h UIR

FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) F67h UFRMH

FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) F66h UFRML

FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) F65h SPPCON(3)

FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE F64h SPPEPS(3)

FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) F63h SPPCFG(3)

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SPPDATA(3)

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2)

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2)

Note 1: Not a physical register.

2: Unimplemented registers are read as ‘0’.

3: These registers are implemented only on 40/44-pin devices.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 67
PIC18F2455/2550/4455/4550
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 51, 58
TOSH Top-of-S tack High Byte (TOS<15:8>) 0000 0000 51, 58
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 51, 58
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 51, 59
PCLATU — — — Holding Regi ster for PC<20:16> ---0 0000 51, 58
PCLATH Holding Register for PC<15:8> 0000 0000 51, 58
PCL PC Low Byte (PC<7:0>) 0000 0000 51, 58
TBLPTRU ——bit 21
(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 51, 82
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 51, 82
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 51, 82
TABLAT Program Memory Table Latch 0000 0000 51, 82
PRODH Product Register High Byte xxxx xxxx 51, 95
PRODL Product Register Low Byte xxxx xxxx 51, 95
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 51, 99
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 51, 100
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 51, 101
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 51, 73
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 51, 74
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 51, 74
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 51, 74
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – 
value of FSR0 offset by W N/A 51, 74
FSR0H ———— Indirect Data Memory Address Pointer 0 High Byte ---- 0000 51, 73
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 51, 73
WREG Working Register xxxx xxxx 51
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 51, 73
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 51, 74
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 51, 74
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 51, 74
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – 
value of FSR1 offset by W N/A 51, 74
FSR1H ———— Indirect Data Memory Address Pointer 1 High Byte ---- 0000 51, 73
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 51, 73
BSR ———— Bank Select Register ---- 0000 52, 63
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 52, 73
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 52, 74
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 52, 74
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 52, 74
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – 
value of FSR2 offset by W N/A 52, 74
FSR2H ———— Indirect Data Memory Address Pointer 2 High Byte ---- 0000 52, 73
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 52, 73
STATUS — — —NOVZDCC---x xxxx 52, 71
TMR0H Timer0 Regi st er Hi gh Byte 0000 0000 52, 127
TMR0L Timer0 Register Low By te xxxx xxxx 52, 127
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 52, 125
Legend: x = unknow n , u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01;  otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are  read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only.

PIC18F2455/2550/4455/4550
DS39632D-page 68 Preliminary © 2007 Microchip Technology Inc.
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 52, 32
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 52, 279
WDTCON ———————SWDTEN--- ---0 52, 298
RCON IPEN SBOREN(2) —RITO PD POR BOR 0q-1 11q0 52, 44
TMR1H Timer1 Regi st er Hi gh Byte xxxx xxxx 52, 133
TMR1L Timer1 Register Low By te xxxx xxxx 52, 133
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 5 2, 129
TMR2 Timer2 R egist er 0000 0000 52, 136
PR2 Timer2 Period Register 1111 1111 52, 136
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 135
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 52, 194, 
202
SSPADD MSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C™ Master mode. 0000 0000 52, 202
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 52, 194,  
203
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 52, 19 5, 
204
SSPCON2 GCEN ACKSTAT ACKDT/
ADMSK5(7) ACKEN/
ADMSK4(7) RCEN/
ADMSK3(7) PEN/
ADMSK2(7) RSEN/
ADMSK1(7) SEN 0000 0000 5 2, 205
ADRESH A/D Result Register High Byte xxxx xxxx 52, 268
ADRESL A/D Result Register Low Byte xxxx xxxx 52, 268
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 5 2, 259
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 52, 260
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 5 2, 261
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 53, 142
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 53, 142
CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53, 141, 
149
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 53, 142
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 53, 142
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 53, 141
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 53, 240
ECCP1DEL PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 53, 158
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 53, 159
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 53, 275
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 53, 269
TMR3H Timer3 Regi st er Hi gh Byte xxxx xxxx 53, 139
TMR3L Timer3 Register Low By te xxxx xxxx 53, 139
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 53, 137
SPBRGH EUSART Baud Rate G ener ator Register High Byte 0000 0000 53, 241
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 53, 241
RCREG EUSART Receive Register 0000 0000 53, 250
TXREG EUSART Transmit Register 0000 0000 53, 247
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53, 238
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 5 3, 239
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page
Legend: x = unknow n , u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01;  otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are  read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 69
PIC18F2455/2550/4455/4550
EEADR EEPROM Address Register 0000 0000 53, 89
EEDATA EEPROM Data Register 0000 0000 53, 89
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 53, 80
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 53, 81
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 5 4, 107
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 54, 103
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 54, 105
IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 54, 106
PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 54, 102
PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 54, 104
OSCTUNE INTSRC —— TUN4 TUN3 TUN2 TUN1 TUN0 0--0 0000 54, 28
TRISE(3) ————— TRISE2 TRISE1 TRISE0 ---- -111 54, 124
TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 54, 122
TRISC TRISC7 TRISC6 ——— TRISC2 TRISC1 TRISC0 11-- -111 54, 119
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 54, 116
TRISA — TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 54, 113
LATE(3) ————— LATE2 LATE1 LATE0 ---- -xxx 54, 124
LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 54, 122
LATC LATC7 LATC6 ——— LATC2 LATC1 LATC0 xx-- -xxx 54, 119
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 54, 116
LATA —LATA6
(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 54, 113
PORTE RDPU(3) ———RE3
(5) RE2(3) RE1(3) RE0(3) 0--- x000 54, 123
PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 54, 122
PORTC RC7 RC6 RC5(6) RC4(6) — RC2 RC1 RC0 xxxx -xxx 54, 119
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54, 116
PORTA —RA6
(4) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 54, 113
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page
Legend: x = unknow n , u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01;  otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are  read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only.

PIC18F2455/2550/4455/4550
DS39632D-page 70 Preliminary © 2007 Microchip Technology Inc.
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 55, 166
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 5 5, 170
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —-0x0 000- 55, 164
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI —-xxx xxx- 5 5, 168
UEIE BTSEE —— BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 55, 182
UEIR BTSEF —— BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 55, 181
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 5 5, 180
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 55, 178
UFRMH ————— FRM10 FRM9 FRM8 ---- -xxx 5 5, 170
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 55, 170
SPPCON(3) —————— SPPOWN SPPEN ---- --00 55, 187
SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 55, 191
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 55, 188
SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 5 5, 192
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page
Legend: x = unknow n , u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01;  otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are  read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only.

PIC18F2455/2550/4455/4550

5.3.6 STATUS REGISTER

The STATUS register, shown in Register 5-2, contains

the arithmetic status of the ALU. As with any other SFR,

it can be the operand for any instruction.

If the STATUS register is the desti nati on for an ins tru c-

tion that affects the Z, DC, C, OV or N bits, the results

of the instruction are not written; instead, the STATUS

formed. Therefore, the result of an instruction with the

STATUS register as its destination may be different

than intended. As an example, CLRF STATUS will set

the Z bit and leave the remaining Status bits

unchanged (‘000u u1uu’).

It is recommended that only BCF, BSF, SWAPF, MOVFF

and MOVWF instructions are used to alter the STATUS

C, DC, OV or N bits in the STATUS register.

For other i ns truc tio ns that do not a ffect Status bi t s , se e

the instruction set summaries in Table 26-2 and

Table 26-3.

Note: The C and DC bits operate as the Borrow

and Digit Borrow bits, respectively, in

subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDC

(1) C(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative

(ALU MSB = 1).

1 = Result was neg ative

0 = Result was positive

bit 3 OV: Overflow bit

This bit is used fo r signe d arithm etic (2 ’s comp lement ). It indi cates an o verflow of the 7-bit m agni tude

which causes the sign bit (bit 7 of the result) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit(1)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(2)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow , th e polarity is reversed . A subtrac tion is exec uted by a dding the 2’s c omplement of the sec ond

operand. For ro tate (RRF, RLF) instruc tio ns , thi s bi t is loaded with either bit 4 or bit 3 of the sourc e re gis ter.

2: For Borrow, the pola rity is revers ed. A subt raction is ex ecuted b y adding the 2’ s compleme nt of the s econd

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the

source register.

PIC18F2455/2550/4455/4550
DS39632D-page 72 Preliminary © 2007 Microchip Technology Inc.
5.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the da ta m emory  sp ace can  be addr essed  in  several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
dependi ng on whic h operands are us ed and whe ther or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
•Direct
•Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”. 
5.4.1 INHERENT AND LITERAL 
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inher ent Add res sin g. Exa mp les  includ e SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include  CALL and GOTO, which include a 20-bit
program memory address.
5.4.2 DIRECT ADDRESSING
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register  address in
one of  the banks of d ata RAM ( Section 5.3.4 “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
source for the instruction. 
The Acc es s RAM  b it  ‘a’  de term in es  ho w  the  a ddre ss i s
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.2 “Bank Select Register (BSR)”) are
used with  the addres s to determ ine the com plete 12-b it
addr ess of t he regis ter. Wh en ‘a’ is  ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destin ation of the ope ration’ s result s is determine d
by the destination bit ‘d’. When ‘d’ is  ‘1’, the results are
stor ed  ba ck  in  t he s o ur c e re g is ter, over wr iti n g i ts or i gi -
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a  dest ination  that is  implicit  in the  inst ruction;  their
destination is either the target register being operated
on or the W register.
5.4.3 INDIRECT ADDRESSING
Indirect  Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as poi nters to the location s to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory. 
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit au tomati c mani pulati on of the poi nter val ue wi th
auto-incrementing, auto-decrementing or offsetting
with a not her value. This allo ws for efficient co de, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM 
(BANK 1) USING 
INDIRECT ADDRESSING   
Note: The ex ecutio n of some i nstruct ions in t he
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data
Memory and the Extended Instruction
Set” for more information.
LFSR FSR0, 100h ;   
NEXT  CLRF POSTINC0 ; Clear INDF 
; register then 
; inc pointer 
BTFSS FSR0H, 1 ; All done with
; Bank1? 
BRA NEXT ; NO, clear next 
CONTINUE ; YES, continue 

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5.4.3.1 FSR Regi sters and the

INDF Operand

At the core of Indirect Addressing are three sets of

registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers: FSRnH and FSRnL. The four

upper bit s of the FSRnH register are not used, s o each

FSR pair hol ds a 12 -bit valu e. Thi s re prese nts a va lue

that can address the entire range of the data memory

in a linear fashion. The FSR register pairs, then, serve

as pointers to data memory locations.

Indirect Addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers; they are

mapped in the SFR sp ace bu t are not ph ysic ally impl e-

mented. Reading or writing to a parti cular INDF register

actually accesses its corresponding FSR register pair.

A read from INDF1, for example, reads the data at the

address indicated by FSR1H:FSR1L. Instructions that

use the INDF registers as operands actually use the

contents of th eir corr esp ondin g FSR as a poin ter to th e

instruction’s target. The INDF operand is just a

convenient way of using the pointer.

Because Indirect Address ing uses a full 12-bit address,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

FIGURE 5-7: INDIRECT ADDRESSING

FSR1H:FSR1L

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

Using an instruction with one of the

indirect addressing registers as the

operand....

...uses the 12-bit address stored in

the FSR pair associated with that

...to determine the data memory

location to be used in that operation.

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added to that

of the W register and stored back in

ECCh.

xxxx1110 11001100

Bank 14

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5.4.3.2 F SR Registers and POST IN C,

POSTDEC, PREINC and PL USW

In additi on to the INDF o perand, each F SR register p air

also has four additional indirect operands. Like INDF,

these are “virtual” registers that cannot be indirectly

read or written to. Accessing these registers actually

accesses the associated FSR register pair, but also

performs a specific action on it stored value. They are:

• POSTDEC: acc es se s the FSR value, then

automatically decrements it by ‘1’ afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by ‘1’ afterwards

• PREINC: inc r ements the FSR value by ‘1’, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 12 8) to that of the FSR and uses

the new value in the operation.

In this context, accessing an INDF register uses the

value in the FSR regi sters without chan ging them. Sim-

ilarly, accessing a PLUSW register gives the FSR value

of fset by that in the W register; nei t her v alu e is ac tu all y

changed in the operation. Accessing the other virtual

registers changes the value of the FSR registers.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair; that is,

rollovers of the FSRnL register, from FFh to 00h, carry

over to the FSRnH register. On the other hand, results

of these operations do not change the value of any

flags in the STATUS register (e.g., Z, N, OV, etc.).

The PLUSW register can be used to implement a form

of Indexed Addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

5.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs

or virtual registers represent special cases. For exam-

ple, usin g an FSR to point to one of the virtual registers

will not result in successful operations. As a specific

case, assume that FSR0H:FSR0L contains FE7h, the

address of INDF1. Attempts to rea d the value of INDF1,

using INDF0 as an operand, will return 00h. Attempts

to write to INDF1, using INDF0 as the operand, will

result in a NOP.

On the other ha nd, using the v irtual regist ers to write to

an FS R pa ir may not occu r as plan ned. I n t hese cases,

the val ue will be written to the FSR p air bu t without any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses Indirect Addressing.

Similarly, operations by Indirect Addressing are gener-

ally pe rmitted on all other SFRs . Users should exerc ise

the appropriate caution that they do not inadvertently

change settings that might affect the operation of the

device.

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5.5 Program Memory and the

Extended Instruct ion Set

The operation of progra m m em ory is unaffected by th e

use of the extended instruction set.

Enabling the extended instruction set adds eight

additional two-word commands to the existing

PIC18 instruction set: ADDFSR, ADDULNK, CALLW,

MOVSF, MOVSS, PUSHL, SUBFSR a nd SUBULNK. These

instructions are executed as described in

Section 5.2.4 “Two-Word Instructions”.

5.6 Data Memory and the Extended

Instructi on Set

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing.

Specific ally , t he use of the Acce ss Bank for ma ny of the

core PIC18 instructions is different. This is due to the

introduction of a new addressing mode for the data

memory space. This mode also alters the behavior of

Indirect Addressing using FSR2 and its associated

operands.

What doe s not chan ge is ju st as im po rtant. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect Addressing

with FSR0 and FSR1 also remains unchanged.

5.6.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of Indirect Addressing using the FSR2

proper conditions, instructions that use the Access

Bank – that is, most bit-oriented and byte-oriented

instructio ns – can invok e a form of Ind exed Addressin g

using an offset specified in t he i nst ruc tio n. Thi s s pec ia l

address ing mod e is k nown as I ndexed A ddressing with

Literal Offset or Indexed Literal Offset mode.

When using the extended instruction set, this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);

and

• The file address argument is less than or equal

to 5Fh.

Under these conditions, the file address of the instruc-

tion is not interpreted as the lower byte of an address

(used with th e BSR in Direct Addres sing), or as an 8-bit

address in the Access Bank. Instead, the value is

interpreted as an offset value to an Address Pointer

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

5.6.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct

Addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set. Instruc-

tions that only use Inherent or Literal Addressing

modes are una ffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they use the Access Bank (Access

RAM bit is ‘1’) or incl ude a file address of 60h or above.

Instructions meeting these criteria will continue to

execute as before. A comparison of the different

possible addressing modes when the extended

instruction set is enabled in shown in Figure 5-8.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 26.2.1

“Extended Instruction Syntax”.

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FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When a = 0 and f ≥ 60h:

The instruction executes in

Direct Forced mode. ‘f’ is inter-

preted as a location in the

Access RAM between 060h

and 0FFh. This is the s ame as

the SFRs or locations F60h to

0FFh (Bank 15) of data

memory.

Locations below 60h are not

available in this addressing

mode.

When a = 0 and f ≤ 5Fh:

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpre ted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

address can be anywhere in

the data memory space.

Note that in this mode, the

correct syn tax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

When a = 1 (all val ues of f):

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is inter-

preted as a location in one of

the 16 banks of the data

memory space. The bank is

design ated by the Bank Sel ect

can be in any implemented

bank in the data memory

space.

000h

060h

100h

F00h

F60h

FFFh

Valid range

00h

60h

FFh

Data Memory

Access RAM

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

000h

080h

100h

F00h

F60h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

FSR2H FSR2L

ffffffff001001da

000h

080h

100h

F00h

F60h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

for ‘f’

BSR

00000000

080h

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5.6.3 MAPPING THE ACCESS BANK IN

INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode

effectively changes how the lower portion of Access

RAM (00h to 5Fh) is mapped. Rather than containing

just the contents of the bottom half of Bank 0, this mode

maps the contents from Bank 0 and a user-defined

“window” that can be located anywhere in the data

memory space. The value of FSR2 establishes the

lower boundary of the addresses mapped into the

window, while the upper boundary is defined by FSR2

plus 95 (5Fh). Addresses in the Access RAM above

5Fh are mapped as previously described (see

Section 5.3.3 “Access Bank”). An example of Access

Bank remapping in this addressing mode is shown in

Figure 5-9.

Remapping of the Access Bank applies only to opera-

tions u sing the I ndexed Lite ral Offs et mode. Ope rations

that use the BSR (Access RAM bit is ‘1’) will continue

to use Direct Addressing as before. Any indirect or

indexed operation that expli citly uses any of the indirec t

file operands (including FSR2) will continue to operate

as standard Indirect Addressing. Any instruction that

uses the Access Bank, but includes a register address

of greater than 05Fh, will use Direct Addressing and

the normal Access Bank map.

5.6.4 BSR IN INDEXED LITERAL

OFFSET MODE

Although the Access Bank is remapped when the

extended instruction set is enabled, the operation of the

BSR remai ns uncha nged. D irect Addr essin g, usin g the

BSR to select the data memory bank, operates in the

same manner as previously described.

FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL

OFFSET ADDRESSING

Data Memory

000h

100h

200h

F60h

F00h

FFFh

Bank 1

Bank 15

Bank 2

through

Bank 14

SFRs

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region

from the FSR2 Pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

Special Function Regis-

ters at F60h through FFFh

are mapped to 60h

through FFh as usual.

Bank 0 addresses below

5Fh are not available in

this mode. They can still

be addressed by using the

BSR.

Access Bank

00h

60h

FFh

Bank 0

SFRs

Bank 1 “Window”

Window

Example Situation:

120h

17Fh

5Fh

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NOTES:

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6.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable, during normal operation over the entire VDD

range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 32 bytes at a time. Program memory is

erased in blocks of 64 bytes at a time. A Bulk Erase

operation may not be issued from user code.

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value wri tten to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

6.1 Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program

memory and place it into the data RAM space.

Figure 6-1 shows the operation of a table read with

program memory and data RAM.

Ta ble wr ite opera tio ns sto re data fro m the data me mory

space into holding registers in program memory. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 6.5 “W riting

to Flash Program Memory”. Figure 6-2 shows the

operation of a table write with program memory and data

RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word-aligned. Therefore, a table block can

start and end at any byte address. If a t able write is being

used to write executable code into program memory,

program instructions will need to be word-aligned.

FIGURE 6-1: TABLE READ OPERATION

Table Pointer(1) Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory.

Program Memory

(TBLPTR)

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FIGURE 6-2: TABLE WRITE OPERATION

6.2 Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 6-1) is the control

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The EEPGD control bit determi nes if th e access will be

a program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

The CFGS control bit determines if the access will be

to the Confi guratio n/Ca librati on regis ter s or to pro gram

memory/data EEPROM memory. When set,

subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 25.0

“Special Features of the CPU”). When clear , memory

selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory

erase operation. When FREE is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enab led .

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bi t is

set in hardware when the WREN bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Table Pointer(1) Table Latc h (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by

TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “Writing to Flash Program Memory”.

Holding Registers

Program Memory

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset or a write operation was

attempted improperly.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be

cleared in software.

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R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR(1) WREN WR RD

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by

completion of erase operation)

0 = Perform write-only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Init i a t e s a da ta EEPROM erase/write cycle or a progra m m emor y e r a s e cyc l e or w r i te cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

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6.2.2 TABLE LATCH REGISTER (TABLAT)

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR sp ace. The Table Latc h register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

6.2.3 TA B LE PO INT E R RE GI ST E R

(TBLPTR)

The Table Pointe r (TBLPTR) reg ist er ad dre sses a by te

within the program memory . The TBLPTR is comprised

of three SFR regis ters: Table Point er Uppe r Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

progra m memory sp ace. Th e 22nd b it allows acce ss to

the device ID, the user ID and the Configuration bits.

The Table Poin ter, TBLP TR, is use d by the TBLRD an d

TBLWT instructions. These instructions can update the

TBLPTR in one of four ways based on the table opera-

tion. These operations are shown in Table 6-1. These

operations on the TBLPTR only affect the low-order

21 bits.

6.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

into TABLAT.

When a TBLWT is executed, the five LSbs of the Table

Pointer register (TBLP TR<4:0>) determine which of th e

32 program memory holding registers is written to.

When the timed write to program memory begins (via

the WR bit), the 16 MSbs of the TBLPTR

(TBLPTR<21:6>) determine which program memory

block of 32 bytes is written to. For more detail, see

Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the

16 MSbs of the T able Pointer register (TBLPTR<21:6>)

point to the 64-byte block that wi ll be erased. The Leas t

Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of the

TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*

TBLWT* TBLPTR is not modif ied

TBLRD*+

TBLWT*+ TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*- TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+* TBLPTR is incremen ted before the read /w rite

21 16 15 87 0

TABLE ER ASE

TABL E READ – TBLPTR<21:0>

TBLPTRLTBLPTRH

TBLPTRU

TBLPTR<21:6>

TABLE WRITE – TBLPTR<21:5>

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6.3 Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and places it into data RAM. Table

reads fro m program memory are pe rformed one byte at

a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

The interna l program memory is typically org anized by

words. The Least Significan t bit of th e address selects

between the high and low bytes of the word. Figure 6-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVF WORD_ODD

PIC18F2455/2550/4455/4550

6.4 Erasing Flash Program Memory

The mi nimum eras e block is 32 words or 64 byte s. Only

through the use of an external programmer, or through

ICSP control, can larger blocks of program memory be

Bulk Erased. Word Erase in the Flash array is not

supported.

When initiating an erase sequence from the micro-

controll er itsel f, a block of 64 by tes of program me mory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

The EECON1 regis te r com ma nds the era se operation.

The EEPGD bit must be set to point to the Flash

program m emory. The WREN bit must be set to enable

write op erations. The FREE bit i s set to selec t an erase

operation.

For protec tio n, t he w ri te i ni tiat e s equ enc e f or EEC ON 2

must be used.

A long w rite i s nec essary for erasing th e inte rnal Fl ash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

program ming timer.

6.4.1 FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory is:

1. Load Table Pointer register with address of row

being erased.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable int errup ts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the Row Erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_ROW

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Row Erase operation

BCF INTCON, GIE ; disable interrupts

Required MOVLW 55h

Sequence MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

PIC18F2455/2550/4455/4550

6.5 Writing to Flash Program Memory

The minimum programming block is 16 words or

32 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are 32 holding registers used by the table writes for

programming.

Since the Table Latch (TABLAT) is only a single byte, the

TBLWT instruction may ne ed to be ex ecuted 32 times for

each programming operation . All of the table write oper-

ations will essentially be short writes because only the

holding registers are written. At the end of updating the

32 holding registers, the EECON1 register must be

written to in order to start the programming operation

with a long write.

The long write is necessary for programming the

internal Flash. Ins tructio n execu tion is halted whil e in a

long write cycle. The long write will be terminated by

the internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

6.5.1 FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

4. Execute the Row Erase procedure.

5. Load Table Pointer register with address of first

byte being written.

6. Write 32 bytes into the holding registers with

auto-increment.

7. Set the EECON 1 register for the wri te operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

8. Disable int errup ts.

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will beg in the w rite cy cl e.

12. The C PU will stall for dura tion of t he write (a bout

2 ms using internal timer).

13. Re-enable interrupts.

14. Repeat steps 6 through 14 once more to write

64 bytes.

15. Verify the memory (table read).

This procedure will require about 8 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 6-3.

Note: The default value of the holding registers on

device Resets and after write operations is

FFh. A write of FFh to a holding register

does not modi fy th at byt e. T his mea ns th at

individual bytes of program memory may be

modified, provided that the change does not

attemp t to cha nge an y bit f rom a ‘0’ to a ‘1’.

When modifying individual bytes, it is not

necessary to load all 32 holding registers

before ex ec u t in g a write o pe rat io n.

TBLPTR = xxxx1FTBLPTR = xxxxx1TBLPTR = xxxxx0 TBLPTR = xxxxx2

Program Memory

Holding Register Holding Register Holding Register Holding Register

88 8 8

TABLAT

Write Register

Note: Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 32 bytes in

the holding regist er.

PIC18F2455/2550/4455/4550

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D'64’ ; number of bytes in erase block

MOVWF COUNTER

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_BLOCK

TBLRD*+ ; read into TABLAT, and inc

MOVF TABLAT, W ; get data

MOVWF POSTINC0 ; store data

DECFSZ COUNTER ; done?

BRA READ_BLOCK ; repeat

MODIFY_WORD

MOVLW DATA_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW DATA_ADDR_LOW

MOVWF FSR0L

MOVLW NEW_DATA_LOW ; update buffer word

MOVWF POSTINC0

MOVLW NEW_DATA_HIGH

MOVWF INDF0

ERASE_BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Row Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Required MOVWF EECON2 ; write 55h

Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

TBLRD*- ; dummy read decrement

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

MOVLW D’2’

MOVWF COUNTER1

WRITE_BUFFER_BACK

MOVLW D’32’ ; number of bytes in holding register

MOVWF COUNTER

WRITE_BYTE_TO_HREGS

MOVF POSTINC0, W ; get low byte of buffer data

MOVWF TABLAT ; present data to table latch

TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.

DECFSZ COUNTER ; loop until buffers are full

BRA WRITE_WORD_TO_HREGS

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 87
PIC18F2455/2550/4455/4550
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF 
WRITE OPERATION
If a wri te  is  term in ate d by an unpl an ned  ev en t, s uc h a s
loss of power or an unexpected Reset, the memory
locatio n jus t progra mmed  shou ld be  verifi ed and  repr o-
gramme d if needed. If t he write operatio n is interrupte d
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
6.5.4 PROTECTION AGAINST SPURIOUS 
WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Sectio n 25. 0 “S pec ial F eat ure s of  the
CPU” for more detail.
6.6 Flash Program Operation During 
Code Protection
See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY 
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2  ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DECFSZ COUNTER1
BRA WRITE_BUFFER_BACK
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
TBLPTRU ——bit 21
(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 51
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 51
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 51
TABLAT Program Memory Table Latch 51
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
EECON2 EEPROM Control Register 2 (not a physical register) 53
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 53
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the TBLPTRU allows access to the  device Co nfiguration bits.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

7.0 DAT A EEPROM MEMORY

The data EEPROM is a nonvolatile memory array,

separate from the dat a RAM and program memory, that

is used for long-term storage of program data. It is not

directly mapped in either the register file or program

memory space, but is indirectly addressed through the

Special Function Registers (SFRs). The EEPROM is

readable and writ able durin g normal ope ration over the

entire VDD range.

Four SFRs are used to read and write to the data

EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

The data EEPROM allows byte read and write. When

interfacing to the data memory block, EEDATA holds

the 8-bit data for read/write and the EEADR register

holds the address of the EEPROM location being

accessed.

The EEPROM data memory is rated for high erase/write

cycle endurance. A byte write automatically erases the

location and writes the new data (erase-before-write).

The write time is controlled by an on-chip timer; it will

vary with voltage and temperature as well as from chip

to chip. Please refer to parameter D122 (Table 28-1 in

Section 28.0 “Electrical Characteristics”) for exact

limits.

7.1 EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two

registers which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The EECON1 register (Register 7-1) is the control

bit, EEPGD, determines if the access will be to program

or data EEPROM memory. When clear, operations will

access the data EEPROM memory . When set, program

memor y is accessed.

Control bit, CFGS, determines if the access will be to

the Con fig urat ion reg ist ers or to pro gram m em ory/data

EEPROM memory. When set, subsequent operations

access Configuration registers. When CFGS is clear,

the EEPGD bit selects either program Flash or data

EEPROM memory.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bi t is

set in hardware when the WREN bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Control bits, RD and WR, start read and erase/write

operat ions, respec tively . These bi ts are set by fi rmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 6.1 “Table Reads

and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset or a write operation was

attempted improperly.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be

cleared in software.

PIC18F2455/2550/4455/4550

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR(1) WREN WR RD

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by

completion of erase operation)

0 = Perform write-only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Init i a t e s a da ta EEPROM erase/write cycle or a pr o g r a m m emor y e rase cyc le or writ e cy cl e

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

PIC18F2455/2550/4455/4550

7.2 Reading the Dat a EEPROM

Memory

To read a data memory location, the user must write th e

address to the EEADR register, clear the EEPGD

control bit (EECON1<7>) and then set control bit, RD

(EECON1<0>). The data is available on the very next

instruction cycle; therefore, the EEDATA register can

be read by the next instruction. EEDATA will hold this

value u ntil an other re ad opera tion o r unt il it is written to

by the user (during a write operation).

The basic process is shown in Example 7-1.

7.3 Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADR register and the data

written to the EEDATA register. The sequence in

Example 7-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly

followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution (i.e., runaway programs). The WREN bit should

be kept clear at all times except when updating the

EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1,

EEADR and EEDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. The WREN bit must be set on a previous instruc-

tion. Both WR a nd WREN c an not be se t with th e s am e

instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Interrupt Flag bit

(EEIF) is s et. The user may e ither e nable this interrup t,

or poll this bit. EEIF must be cleared by software.

7.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

EXAMPLE 7-1: DATA EEPROM READ

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Lower bits of Data Memory Address to read

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, RD ; EEPROM Read

MOVF EEDATA, W ; W = EEDATA

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Lower bits of Data Memory Address to write

MOVLW DATA_EE_DATA ;

MOVWF EEDATA ; Data Memory Value to write

BCF EECON1, EPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, WREN ; Enable writes

BCF INTCON, GIE ; Disable Interrupts

MOVLW 55h ;

Required MOVWF EECON2 ; Write 55h

Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

PIC18F2455/2550/4455/4550

7.5 Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

Configuration Words. External read and write

operations are disabled if code protection is enabled.

The mic rocontroll er its elf can bo th read and write to the

internal data EEPROM regardless of the state of the

code-protect Configuration bit. Refer to Section 25.0

“Special Features of the CPU” for additional

information.

7.6 Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM are bloc ked

during the Power-up Timer period (TPWRT,

parameter 33, Table 28-12).

The wri te in iti ate sequence an d the WREN bi t tog eth er

help prevent an accidental write during brown-out,

power glitch or software malfunction.

7.7 Using the Data EEPROM

The dat a EEPROM is a hi gh en dura nc e, byt e a ddr ess-

able array that has been optimized for the storage of

frequently changing information (e.g., program

variables or other data that are updated often).

Frequently changing values will typically be updated

more often than specification D124 or D124A. If this is

not t he ca se, an arra y re fres h mus t be perf orm ed. For

this reason, variables that change infreq uently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store

const a nts and/or data th at changes rarely,

an array refresh is likely not required. See

spec ification D124 or D124 A.

CLRF EEADR ; Start at address 0

BCF EECON1, CFGS ; Set for memory

BCF EECON1, EEPGD ; Set for Data EEPROM

BCF INTCON, GIE ; Disable interrupts

BSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh array

BSF EECON1, RD ; Read current address

MOVLW 55h ;

Required MOVWF EECON2 ; Write 55h

Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BTFSC EECON1, WR ; Wait for write to complete

BRA $-2

INCFSZ EEADR, F ; Increment address

BRA LOOP ; Not zero, do it again

BCF EECON1, WREN ; Disable writes

BSF INTCON, GIE ; Enable interrupts

PIC18F2455/2550/4455/4550

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51

EEADR EEPROM Address Register 53

EEDATA EEPROM Data Register 53

EECON2 EEPROM Control Register 2 (not a physical register) 53

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 53

IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54

PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54

PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier’s

operation does not affect any flags in the STATUS

Making multiplication a hardware operation allows it to

be com pl eted i n a single ins tru cti on cycle. Thi s has th e

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many applica-

tions previously reserved for digital signal processors.

A comparison of various hardware and software

multiply operations, along with the savings in memory

and execution time, is shown in Table 8-1.

8.2 Operation

Example 8-1 shows the instruction sequence for an

8 x 8 unsigned multiplication. Only one instruction is

required when one of the arguments is already loaded

in the WREG register.

Exampl e 8-2 shows the sequence t o do an 8 x 8 signed

multiplication. To account for the sign bits of the

argumen ts, e ach argu ment’ s Most Si gnificant bit (MSb)

is tested and the appropriate subtractions are done.

EXAMPLE 8- 1: 8 x 8 UNSIG NE D

MULTIP L Y ROU TI NE

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine Multiply Method Program

Memory

(Words)

Cycles

(Max)

Time

@ 40 MHz @ 10 MHz @ 4 MHz

8 x 8 unsigned Without hardware multiply 13 69 6.9 μs27.6 μs69 μs

Hardware multiply 1 1 100 ns 400 ns 1 μs

8 x 8 signed Without hardware multiply 33 91 9.1 μs36.4 μs91 μs

Hardware multiply 6 6 600 ns 2.4 μs6 μs

16 x 16 unsigned Without hardware multiply 21 242 24.2 μs96.8 μs 242 μs

Hardware multiply 28 28 2.8 μs 11.2 μs28 μs

16 x 16 signed Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs

Hardware multiply 35 40 4.0 μs16.0 μs40 μs

PIC18F2455/2550/4455/4550

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 8-1 shows the

algorith m that is us ed. The 32-b it result is st ored in fo ur

registers (RES3:RES0).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8- 3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES3:RES0). To account for the sign bits of the

arguments, the MSb for each argument pair is tested

and the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED

MU LTIPLY ROUTINE

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L,W

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWF RES2 ;

MOVF ARG1H, W ;

SUBWFB RES3

;

SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3

;

CONT_CODE

PIC18F2455/2550/4455/4550

9.0 INTERRUPTS

The PIC18F2455/2550/4455/4550 devices have

multiple interrupt sources and an interrupt priority

feature that allows each interrupt source to be assigned

a high priority level or a low priority level. The high

priority interrupt vector is at 000008h and the low

priority interrupt vector is at 000018h. High priority

interrupt events will interrupt any low priority interrupts

that may be in progress.

There are ten registers which are used to control

interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

It is recommended that the Microchip header files

suppli ed with MP LAB® IDE be used fo r the symb olic bit

names in these registers. This allows the assembler/

compil er to automa tical ly ta ke care of the pla ceme nt of

these bits within the specified register.

Each interrupt source has three bits to control its

operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globall y. Setting the GIEH bit (INTCO N<7>) enable s all

interrupts that have the priority bit set (high priority).

Setting the GIEL bit (INTCON<6>) enables all

inter rupts that have the pr iority bit cleared ( low prio rity).

When the interrupt flag, enable bit and appropriate

global interrupt enable bit are set, the interrupt will

vector immediately to address 000008h or 000018h,

depending on the priority bit setting. Individual inter-

rupts can be disabled through their corresponding

enable bits.

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

compatible with PIC® mid-range devices. In

Compatibility mode, the interrupt priority bits for each

source have no effect. INTCON<6> is the PEIE bit

which enables/dis ables all pe ripheral interru pt sources.

INTCON<7> is the GIE bit which enables/disables all

interrupt sources. All interrupts branch to address

000008h in Compatibility mode.

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is clear ed, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt. Low priority interrupts are not

processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bit s must be cleared in software be fore re-enab ling

interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrup t routine and set s the GIE bit (GIEH or GI EL

if priority levels are used) which re-enables interrupts.

For external interrupt events, such as the INT pins or

the POR TB input chang e interrupt, the i nterrupt latenc y

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set regardless of the

status of their corresponding enable bit or the GIE bit.

9.1 USB Interrupts

Unlike o ther p eripher als , the USB modu le is cap abl e of

generati ng a wid e range of interrupt s for m any types of

event s. The se in cl ude se veral t ypes of norm al com mu-

nication and status events and several module level

error events.

To handle these events, the USB module is equipped

with its own interrupt logic. The logic functions in a

manner similar to the microcontroller level inter rupt fun-

nel, with each interrupt source having separate flag and

enable bits. All events are funneled to a single device

level interrupt, USBIF (PIR2<5>). Unlike the device

level i nterrupt logic , the in divid ual USB i nterrupt events

cannot be individually assigned their own priority. This

is determined at the device level interrupt funnel for all

USB events by the USBIP bit.

For additional details on USB interrupt logic, refer to

Section 17.5 “USB Interrupts”.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

PIC18F2455/2550/4455/4550

FIGURE 9-1: INTERRUPT LOGIC

TMR0IE

GIE/GIEH

PEIE/GIEL

Wake-up if in Sleep Mode

Interrupt to CPU

Vector to Location

0008h

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

IPEN

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

PEIE/GIEL

Interrupt to CPU

Vector to Location

IPEN

0018h

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

TMR1IF

TMR1IE

TMR1IP

USBIF

USBIE

USBIP

Additional Peripheral Interrupts

TMR1IF

TMR1IE

TMR1IP

High Priority Interrupt Generation

Low Priority Interrupt Generation

USBIF

USBIE

USBIP

Additional Peripheral Interrupts

GIE/GIEH

From USB

Interrupt Logic

From USB

Interrupt Logic

PIC18F2455/2550/4455/4550

9.2 INTCON Registers

The INTCON registers are readable and writable

bits.

Note: Interru pt flag bit s ar e set when an inter rupt

condition occurs regardless of the state of

its corresponding enable bit or the global

interrupt enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows for software polling.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN = 1:

1 = Enables all high priority interrupts

0 = Disables all high priority interrupts

bit 6 PEIE/GIEL: Perip hera l Interru pt Enab le bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all low priority peripheral interrupts

0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change inte rrup t

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 re gister has overflowe d (must be cleare d in software)

0 = TMR0 re gister did no t overfl ow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)

0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit(1)

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and

allow the bit to be cleared.

PIC18F2455/2550/4455/4550

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on fallin g edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on fallin g edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on fallin g edge

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 = High priority

0 = Low priority

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F2455/2550/4455/4550

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt

0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt

0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)

0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)

0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F2455/2550/4455/4550

9.3 PIR Registers

The PIR regi sters c onta in the ind ividual fl ag bit s for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Request (Flag) registers (PIR1 and PIR2).

Note 1: Interrupt flag bits are set whe n an interrupt

conditi on occ urs regardle ss of th e st ate of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt and after servicing

that interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPPIF: Streaming Parallel Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or writ e has occurred

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

0 = The EUSART receive buffer is empty

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0 = The EUSART transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode .

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overf lowed (must be cleared in software)

0 = TMR1 register did not overflow

Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = System clock ope rati ng

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator inpu t has not changed

bit 5 USBIF: USB Interrupt Flag bit

1 = USB has requested an interrupt (must be cleared in software)

0 = No USB interrupt request

bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred (must be cleared in software)

0 = No bus collision occurred

bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit

1 = A high/low-voltage condition occurred (must be cleared in software)

0 = No high/low-voltage event has occurred

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overf lowed (must be cleared in software)

0 = TMR3 register did not overflow

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)

0 = No TMR1 or TMR3 register capture occurred

Compare mode:

1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)

0 = No TMR1 or TMR3 register compare match occurred

PWM mode:

Unused in this mode .

PIC18F2455/2550/4455/4550

9.4 PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Interrupt

Enable registers (PIE1 and PIE2). When IPEN = 0, the

PEIE bit must be set to enable any of these peripheral

interrupts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPPIE: Streaming Parallel Port Read/Write Interrupt Enable bit(1)

1 = Enables the SPP read/write interrupt

0 = Disables the SPP read/write interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interru pt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disables the EUSAR T rece iv e interr upt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disables the EUSAR T tr ansmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP 1 interru pt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 6 CMIE: Comparator I nterr upt Enab le bit

1 = Enabled

0 = Disabled

bit 5 USBIE: USB Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enabled

0 =Disabled

PIC18F2455/2550/4455/4550

9.5 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are two Peripheral

Interrupt Priority registers (IPR1 and IPR2). Using the

priority bits requires that the Interrupt Priority Enable

(IPEN) bit be set.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPPIP: Streaming Parallel Port Read/Write Interrupt Priority bit(1)

1 = High prior ity

0 = Low priority

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 = High prior ity

0 = Low priority

bit 5 RCIP: EUSART Receive Interrupt Priority bit

1 = High prior ity

0 = Low priority

bit 4 TXIP: EUSART Transmit Interrupt Priority bit

1 = High prior ity

0 = Low priority

bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1 = High prior ity

0 = Low priority

bit 2 CCP1IP: CCP1 Interrupt Priority bit

1 = High prior ity

0 = Low priority

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High prior ity

0 = Low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High prior ity

0 = Low priority

Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.

PIC18F2455/2550/4455/4550

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 CMIP: Comparator Interr upt Priority bit

1 = High priority

0 = Low priority

bit 5 USBIP: USB Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 BCLIP: Bus Collision Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 CCP2IP: CCP2 Interrupt Priority bit

1 = High priority

0 = Low priority

PIC18F2455/2550/4455/4550

9.6 RCON Register

The RCO N regist er conta ins flag b its whic h are used to

deter mine the caus e of the last R eset or wa ke -up from

Idle or Slee p mo des . R CO N als o co ntains the IPEN bit

which enables interrupt priorities.

R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0

IPEN SBOREN —RITO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit(1)

For details of bit operation, see Register 4-1.

bit 5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

For details of bit operation, see Register 4-1.

bit 3 TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-1.

bit 2 PD: Power-Down Detection Flag bit

For details of bit operation, see Register 4-1.

bit 1 POR: Power-on Reset Status bit(2)

For details of bit operation, see Register 4-1.

bit 0 BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-1.

Note 1: If SBOREN is ena bl ed, it s R eset s t a te is ‘1’; oth erwis e, i t i s ‘ 0’. See Re gis ter 4-1 for additiona l in form ation.

2: The actual Reset value of POR is determined by the typ e of de vi ce Res et. See Register 4-1 for additi onal

information.

PIC18F2455/2550/4455/4550

9.7 INTn Pin Interrupts

External interrupts on the RB0/AN12/INT0/FLT0/SDI/

SDA, RB1/AN10/INT1/SCK/SCL and RB2/AN8/INT2/

VMO pins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit, INTxIF, is set. This interrupt can be disabled by

clearin g th e c orre spo nd ing ena bl e bi t, INT xIE. Fla g bi t,

INTxIF, must be cleared in software in the Interrupt

Service Routine before re-enabling the interrupt.

All external interrupts (INT0, INT1 and INT2) can wake-

up the processor from the power-managed m odes if bit,

INTxIE, was set prior to going into the power-managed

modes. If the Globa l Interrupt Enable bit, GIE, is set, the

processor will branch to the interrupt vector following

wake-up.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a high

priority interrupt source.

9.8 TMR0 Interrupt

In 8-b it mod e (whic h is the de faul t), a n overfl ow in t he

TMR0 register (FFh →00h) wil l set flag bit, TM R0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TMR0IE (INTCON<5>). Interrupt priority for Timer0 is

determined by the value contained in the interrupt

priority bit, TMR0IP (INTCON2<2>). See Section 11.0

“Timer0 Module” for further details on the Timer0

module.

9.9 PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

9.10 Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 5.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR re gister s during an In terrupt Servic e

Routine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

10.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. Some pins

of the I/O ports are multiplexed with an alternate

function from the peripheral features on the device. In

general, when a perip heral is ena bled, that pi n may not

be used as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• POR T register (reads the levels on th e pins of the

device)

• LAT register (output latch)

The Data Latch register (LATA) is useful for read-

modify-write operations on the value driven by the I/O

pins.

A simplified model of a generic I/O port, without the

interf aces to other peripherals, is sho wn in Figure 10-1.

FIGURE 10-1: GENERIC I/O PORT

OPERATION

10.1 PORTA, TRISA and LATA Registers

PORTA is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISA bit (= 0) wi ll

make the correspon ding POR TA pin an output (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins; writing to it will write to the port latch.

The Data Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The RA6 pin

is multiplexed with the main oscillator pin; it is enabled

as an oscillator or I/O pin by the selection of the main

oscillator in Configuration Register 1H (see

Section 25.1 “Configuration Bits” for details). When

not used as a port pin, RA6 and its associated TRIS

and LAT bits are read as ‘0’.

RA4 is also multi plexe d wi th the USB m odule; it se rves

as a receiver input from an external USB transceiver.

For details on configuration of the USB module, see

Section 17.2 “USB Status and Control”.

Several PORT A pins are multiplexed with analog inputs,

the analog VREF+ and VREF- inputs and the comparator

voltage reference output. The operation of pins RA5

and RA3:RA0 as A/D converter inputs is selected by

clearing/setting the control bits in the ADCON1 register

(A/D Control Register 1).

All other PORTA pins have TTL input levels and full

CMOS out put driv ers .

The TRISA register controls the direction of the RA

pins, ev en w he n th ey a re being used as ana log inputs .

The user mu st ensure the bit s in the TRISA registe r are

maintained set when using them as analog inputs.

EXAMPLE 10-1: INITIALIZING PORTA

Data

Bus

WR LAT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or PORT

Note 1: I/O pins have diode protection to VDD and VSS.

Note: On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA4 is configured as a digital input.

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

CLRF LATA ; Alternate method

; to clear output

; data latches

MOVLW 0Fh ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 07h ; Configure comparators

MOVWF CMCON ; for digital input

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

PIC18F2455/2550/4455/4550

TABLE 10-1: PORTA I/O SUMMARY

Pin Function TRIS

Setting I/O I/O Type Description

RA0/AN0 RA0 0OUT DIG LATA<0> data output; not affected by analog input.

1IN TTL PORTA<0> data input; disabled when analog input enabled.

AN0 1IN ANA A /D input channel 0 and Comparator C1- input. Default configuration

on POR; does not affect digital output.

RA1/AN1 RA1 0OUT DIG LATA<1> data output; not affected by analog input.

1IN TTL PORTA<1> data input; reads ‘0’ on POR.

AN1 1IN ANA A /D input channel 1 and Comparator C2- input. Default configuration

on POR; does not affect digital output.

RA2/AN2/

VREF-/CVREF RA2 0OUT DIG LATA<2> data output; not affected by analog input. Disabled when

CVREF output enabled.

1IN TTL PORTA<2> data input. Disabled when analog functions enabled;

disabled when CVREF output enabled.

AN2 1IN ANA A/D input channel 2 and Comparator C2+ input. Default configuration

on POR; not affected by analog output.

VREF- 1IN ANA A/D and comparator voltage reference low input.

CVREF xOUT ANA Comparator voltage reference output. Enabling this feature disables

digital I/O.

RA3/AN3/

VREF+RA3 0OUT DIG LATA<3> data output; not affected by analog input.

1IN TTL PORTA<3> data input; disabled when analog input enabled.

AN3 1IN ANA A/D input channel 3 and Comparator C1+ input. Default configuration

on POR.

VREF+1IN ANA A/D and comparator voltage reference high input.

RA4/T0CKI/

C1OUT/RCV RA4 0OUT DIG LATA<4> data output; not affected by analog input.

1IN ST PORTA<4> data input; disabled when analog input enabled.

T0CKI 1IN ST Timer0 clock input.

C1OUT 0OUT DIG Comparator 1 output; takes priority over port data.

RCV xIN TTL External USB transceiver RCV input.

RA5/AN4/SS/

HLVDIN/C2OUT RA5 0OUT DIG LATA<5> data output; not affected by analog input.

1IN TTL PORTA<5> data input; disabled when analog input enabled.

AN4 1IN ANA A /D input channel 4. Default configuration on POR.

SS 1IN TTL Slave select input for SSP (MSSP module).

HLVDIN 1IN ANA High/Low-Voltage Detect external trip point input.

C2OUT 0OUT DIG Comparator 2 output; takes priority over port data.

OSC2/CLKO/

RA6 OSC2 xOUT ANA Main oscillator feedback output connect ion (all XT and HS modes).

CLKO xOUT DIG System cy cle clock output (FOSC/4); available in EC, ECPLL and

INTCKO modes.

RA6 0OUT DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO

modes; otherwise, reads as ‘0’.

1IN TTL PORTA<6> data input. Av ailable only in ECIO, ECPIO and INTIO

modes; otherwise, reads as ‘0’.

Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)

PIC18F2455/2550/4455/4550

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTA —RA6

(1) RA5 RA4 RA3 RA2 RA1 RA0 54

LATA —LATA6

(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 54

TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53

UCON —PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

PIC18F2455/2550/4455/4550

10.2 PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make th e corresp onding POR TB pi n an out put (i.e .,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

Each of th e POR TB pins has a we ak inte rnal pul l-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of the PORTB pins (RB7:RB4) have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur. Any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison. The pins are compared with

the old value latched on the last read of PORTB. The

“mismatch” outputs of RB7:RB4 are ORed together to

generate the RB Port Change Interrupt with Flag bit,

RBIF (INTCON<0>).

The interrupt-on-change can be used to wake the

device from Sleep. The user, in the Interrupt Service

Routine, can clear the int errupt in the following manner:

a) Any read or write of PORTB (except with the

MOVFF (ANY), PORTB instruction). This will

end the mismatch condition.

b) Clear flag bit, RBIF.

A mismatc h condi tion wi ll contin ue to set flag bi t, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

Pins, RB2 and RB3, are multiplexed with the USB

peripheral and serve as the differential signal outputs

for an external USB transceiver (TRIS configuration).

Refe r to Section 1 7.2.2.2 “External Transceiver” for

additional information on configuring the USB module

for operation with an external transceiver.

RB4 is multiplexed with CSSPP, the chip select

function for the Streaming Parallel Port (SPP) – TRIS

setting. Details of its operation are discussed in

Section 18.0 “Streaming Parallel Port”.

EXAMPLE 10-2: INITIALIZING PORTB

Note: On a Power-on Reset, RB4:RB0 are

configu red as analog inp uts by defau lt and

read as ‘0’; RB7:RB5 are configured as

digital inputs.

By programming the Configuration bit,

PBADEN (CONFIG3H<1>), RB4:RB0 will

alternatively be configured as digita l inputs

on POR.

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches

MOVLW 0Eh ; Set RB<4:0> as

MOVWF ADCON1 ; digital I/O pins

; (required if config bit

; PBADEN is set)

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

PIC18F2455/2550/4455/4550

TABLE 10-3: PORTB I/O SUMMARY

Pin Function TRIS

Setting I /O I/O Type Description

RB0/AN12/

INT0/FLT0/

SDI/SDA

RB0 0OUT DIG LATB<0> data output; not affected by analog input.

1IN TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN12 1IN ANA A/D input channel 12.(1)

INT0 1I N ST External interrupt 0 input.

FLT0 1IN ST Enhanced PWM Fault input (ECCP1 module); enabled in software.

SDI 1IN ST SPI data input (MSSP module).

SDA 1OUT DIG I2C™ data output (MSSP module); takes priority over port data.

1IN I2C/SMB I2C data input (MSSP module); input type depends on module setting.

RB1/AN10/

INT1/SCK/

SCL

RB1 0OUT DIG LATB<1> data output; not affected by analog input.

1IN TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN10 1IN ANA A/D input channel 10.(1)

INT1 1I N ST External interrupt 1 input.

SCK 0OUT DI G SPI clock output (MSSP module); takes priority over port data.

1IN ST SPI clock input (MSSP module).

SCL 0OUT DIG I2C clock output (MSSP module); takes priority over port data.

1IN I2C/SMB I2C clock input (MSSP module); input type depends on module setting.

RB2/AN8/

INT2/VMO RB2 0OUT DIG LAT B<2> data output; not affected by analog input.

1IN TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN8 1IN ANA A/D input channel 8.(1)

INT2 1I N ST External interrupt 2 input.

VMO 0OUT DIG External USB transceiver V MO data output.

RB3/AN9/

CCP2/VPO RB3 0OUT DIG LATB<3> data output; not affected by analog input.

1IN TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN9 1IN ANA A/D input channel 9.(1)

CCP2(2) 0OUT DIG CCP2 Compare and PWM output.

1IN ST CCP2 Capture input.

VPO 0OUT DIG External USB transceiver V PO data output.

RB4/AN11/

KBI0/CSSPP RB4 0OUT DIG LATB<4> data output; not affected by analog input.

1IN TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN11 1IN ANA A/D input channel 11.(1)

KBI0 1IN TT L Interrupt -on-pin change.

CSSPP(4) 0OUT DIG SPP chip select control output.

RB5/KBI1/

PGM RB5 0OUT DIG LAT B<5> data output.

1IN TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.

KBI1 1IN TT L Interrupt -on-pin change.

PGM xIN ST Single-Supply Programming mode entr y (ICSP™ ). Ena bled by LVP

Configuration bit; all other pin functions disabled.

Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

I2C/S M B = I2C/SMBus input buffe r, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is

overridden for this option)

Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when

PBADEN is set and digital inpu ts when PBADEN is cleared.

2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.

3: All other pin functions are disabled when ICSP™ or ICD operation is enabled.

4: 40/44-pin devices only.

PIC18F2455/2550/4455/4550
DS39632D-page 116 Preliminary © 2007 Microchip Technology Inc.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB        
RB6/KBI2/
PGC RB6 0OUT DIG LAT B<6> data output.
1IN TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2 1IN TTL Interrupt-on-pin change.
PGC xIN ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3)
RB7/KBI3/
PGD RB7 0OUT DIG LAT B<7> data output.
1IN TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3 1IN TTL Interrupt-on-pin change.
PGD xOUT DIG Serial execution data output for ICSP and ICD operation.(3)
xIN ST Serial execution data input for ICSP and ICD operation.(3)
TABLE 10-3: PORTB I/O SUMMARY (CONTINUED)
Pin Function TRIS 
Setting I /O I/O Type Description
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, 
I2C/S M B  = I2C/SMBus input buffe r, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is 
overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when 
PBADEN is set and digital inpu ts when PBADEN is cleared.
2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
3: All other pin functions are disabled when ICSP™ or ICD operation is enabled.
4: 40/44-pin devices only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 54
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP51
INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 51
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
SPPCON(1) — — — — — — SPPOWN SPPEN 55
SPPCFG(1) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55
UCON —PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1: These registers are uni mplemented  on 28-pin dev ic es .

PIC18F2455/2550/4455/4550

10.3 PORTC, TRISC and LATC

Registers

PORTC is a 7-bit wide, bidirectional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISC bit (= 0)

will mak e the correspo nding PORT C pin an ou tput (i.e.,

put the contents of the output latch on the selected pin).

In PIC18F2455/2550/4455/4550 devices, the RC3 pin

is no t implemented.

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

PORTC.

POR TC is primarily multiplexe d with serial comm unica-

tion modules, including the EUSART, MSSP module

and the U SB mod ule (Table 10-5). Exce pt fo r RC 4 and

RC5, PORTC uses Schmitt Trigger input buffers.

Pins RC4 and RC5 are multiplexed with the USB

module . Depen ding on the con figuration of the module,

they can serve as the differential data lines for the on-

chip USB transceiver, or the data inputs from an

external USB transceiver. Both RC4 and RC5 have

TTL inp ut b uffers i nst ead of the Schmitt Trig ger buffers

on the other pins.

Unlike other PORTC pins, RC4 and RC5 do not have

TRISC b its as so cia t ed wit h t he m. A s di gi ta l po rts, they

can only functi on as di git al inpu ts. When con figured for

USB operation, the data direction is determined by the

configuration and status of the USB module at a given

time. If an external transceiver is used, RC4 and RC5

always function as inputs from the transceiver. If the

on-chip transceiver is used, the data direction is

determined by the operation being performed by the

module at that time.

When the external transceiver is enabled, RC2 also

serves as the output enable control to the transceiver.

Additional information on configuring USB options is

provided in Section 17.2.2.2 “External Transceiver”.

When enabling peripheral functions on PORTC pins

other than RC4 and RC5, care should be taken in defin-

ing the TRIS bits. Some peripherals override the TRIS

bit to make a pin an output, while other peripherals

override the TRIS bit to make a pin an input. The user

should re fer to the cor respon ding periph eral section for

the correct TRIS bit settings.

The contents of the TRISC register are affected by

peripheral overrides. Reading TRISC always returns

the current contents, even though a peripheral device

may be overriding one or more of the pins.

EXAMPLE 10-3: INITIALIZING PORTC

Note: On a Power-on Reset, these pins, except

RC4 and RC5, are configured as digital

inputs. To use pins RC4 and RC 5 as dig i-

tal inputs, the USB module must be dis-

abled (UCON<3> = 0) and the on-chip

USB transceiver must be disabled

(UCFG<3> = 1).

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

CLRF LATC ; Alternate method

; to clear output

; data latches

MOVLW 07h ; Value used to

; initialize data

; direction

MOVWF TRISC ; RC<5:0> as outputs

; RC<7:6> as inputs

PIC18F2455/2550/4455/4550

TABLE 10-5: PORTC I/O SUMMARY

Pin Function TRIS

Setting I/O I/O Type Description

RC0/T1OSO/

T13CKI RC0 0OUT DIG LATC<0> data output.

1IN ST P ORTC<0> data input.

T1OSO xOUT A NA Timer1 oscillator output; enabled when Timer1 oscillator enabled.

Disables digital I/O.

T13CKI 1IN ST Timer1/Timer3 counter input.

RC1/T1OSI/

CCP2/UOE RC1 0OUT DIG LATC<1> data output.

1IN ST P ORTC<1> data input.

T1OSI xIN ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.

Disables digital I/O.

CCP2(1) 0OUT DIG CCP2 Compare and PWM output; takes priority over port data.

1IN ST CCP2 Capture input.

UOE 0OUT DIG External USB transceiver OE output.

RC2/CCP1/

P1A RC2 0OUT DIG LATC <2> data output.

1IN ST P ORTC<2> data input.

CCP1 0OUT DIG ECCP1 Compare and PWM output; takes priority over port data.

1IN S T ECCP1 Capt ure input.

P1A(3) 0OUT DIG ECCP1 Enhanced PWM outpu t, channel A; takes priority over port

data. May be configured for tri-state during Enhanced PWM shutdown

events.

RC4/D-/VM RC4 —(2) IN TTL PORTC<4> data input; disabled when USB module or on-chip

transceiver are enabled.

D- —(2) OUT XCVR USB bus differential minus line output (internal transceiver ).

—(2) IN XCVR USB bus differential minus line input (internal transceiv er).

VM —(2) IN TTL Exte rnal USB transceiver VM input.

RC5/D+/VP RC5 —(2) IN TTL PORTC<5> data input; disabled when USB module or on-chip

transceiver are enabled.

D+ —(2) OUT XCVR USB bus differential plus line output (internal transceiver).

—(2) IN XCVR USB bus differential plus line input (internal transceiver).

VP —(2) IN TTL External USB transceiver VP input.

RC6/TX/CK RC6 0OUT DIG LATC<6> data output.

1IN ST P ORTC<6> data input.

TX 0OUT DIG Asynchronous serial transmit data output (EUSART module); takes

priority over port data. User must configure as output.

CK 0OUT DIG Synchronous serial clock output (EUSART module); takes priority

over port data.

1IN S T S ynchr onous serial clock input (EUSART module).

Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

TTL = TTL Buffer Input, XCVR = USB transceiver , x = Don’t care (TRIS bit does not affect port direction or is overridden

for this option)

Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).

2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is

determined by the USB configuration.

3: 40/44-pin devices only.

PIC18F2455/2550/4455/4550

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

RC7/RX/DT/

SDO RC7 0OUT DIG LATC<7> data output.

1IN ST P ORTC<7> data input.

RX 1IN S T A sync hronous serial receive data input (EUSART module).

DT 1OUT DIG Synchronous serial data output (EUSART module); takes priority over

SPI and port data.

1IN ST Synchronous serial data input (EUSART module). User must

configure as an input.

SDO 0OUT DIG SPI data output (MSSP module); takes priority over port data.

TABLE 10-5: PORTC I/O SUMMARY (CONTINUED)

Pin Function TRIS

Setting I/O I/O Type Description

Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

TTL = TTL Buffer Input, XCVR = USB transceiver , x = Don’t care (TRIS bit does not affect port direction or is overridden

for this option)

Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).

2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is

determined by the USB configuration.

3: 40/44-pin devices only.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTC RC7 RC6 RC5(1) RC4(1) — RC2 RC1 RC0 54

LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 54

TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 54

UCON —PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.

Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

PIC18F2455/2550/4455/4550

10.4 PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will mak e the correspo nding PORT D pin an ou tput (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt

Trigger input buffers. Each pin is individually

configurable as an input or output.

Each of the PORTD pins has a weak internal pull-up. A

single control bit, RDPU (PORTE<7>), can turn on all

the pull-ups. This is performed by setting RDPU. The

weak pull-up is automatically turned off when the port

pin is configured as a digital output or as one of the

other multiplexed peripherals. The pull-ups are

disabled on a Power-on Reset. The PORTE register is

shown in Section 10.5 “PORTE, TRISE and LATE

Registers”.

Three of the PO RT D pins are mult iplexed w ith outp uts ,

P1B, P1C and P1D, of the Enhanced CCP module. The

operation of these additional PWM output pins is

covered in greater detail in Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

PORTD can also be configured as an 8-bit wide

Streaming Parallel Port (SPP). In this mode, the input

buffers are TTL. For additional information on con-

figuration and uses of the SPP, see Section 18.0

“Streaming Parallel Port”.

EXAMPLE 10-4: INITIALIZING PORTD

Note: PORTD is only available on 40/44-pin

devices.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

Note: When the Enhanced PWM mode is used

with either dual or quad outputs , the MSSP

functions of PORTD are automatically

disabled.

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

PIC18F2455/2550/4455/4550

TABLE 10-7: PORTD I/O SUMMARY

Pin Function TRIS

Setting I/O I/O Type Description

RD0/SPP0 RD0 0OUT DIG LATD<0> data output.

1IN ST PORTD<0> data input.

SPP0 1OUT DIG SPP<0> output data; takes priority over port data.

1IN TTL SPP<0> input data.

RD1/SPP1 RD1 0OUT DIG LATD<1> data output.

1IN ST PORTD<1> data input.

SPP1 1OUT DIG SPP<1> output data; takes priority over port data.

1IN TTL SPP<1> input data.

RD2/SPP2 RD2 0OUT DIG LATD<2> data output.

1IN ST PORTD<2> data input.

SPP2 1OUT DIG SPP<2> output data; takes priority over port data.

1IN TTL SPP<2> input data.

RD3/SPP3 RD3 0OUT DIG LATD<3> data output.

1IN ST PORTD<3> data input.

SPP3 1OUT DIG SPP<3> output data; takes priority over port data.

1IN TTL SPP<3> input data.

RD4/SPP4 RD4 0OUT DIG LATD<4> data output.

1IN ST PORTD<4> data input.

SPP4 1OUT DIG SPP<4> output data; takes priority over port data.

1IN TTL SPP<4> input data.

RD5/SPP5/P1B RD5 0OUT DIG LATD<5> data output

1IN ST PORTD<5> data input

SPP5 1OUT DIG SPP<5> output data; takes priority over port data.

1IN TTL SPP<5> input data.

P1B 0OUT D IG ECCP1 Enhanc ed PW M output, channel B; takes priority over

port and SPP data.(1)

RD6/SPP6/P1C RD6 0OUT DIG LATD<6> data output.

1IN ST PORTD<6> data input.

SPP6 1OUT DIG SPP<6> output data; takes priority over port data.

1IN TTL SPP<6> input data.

P1C 0OUT D IG ECCP1 Enhanc ed PWM output, channel C; takes priority over

port and SPP data.(1)

RD7/SPP7/P1D RD7 0OUT DIG LATD<7> data output.

1IN ST PORTD<7> data input.

SPP7 1OUT DIG SPP<7> output data; takes priority over port data.

1IN TTL SPP<7> input data.

P1D 0OUT D IG ECCP1 Enhanc ed PWM output, channel D; takes priority over

port and SPP data.(1)

Legend: OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buff er In put, TTL = TTL Buffer Input

Note 1: May be configured for tri-state during Enhanced PWM shutdown events.

PIC18F2455/2550/4455/4550

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Reset

Values

on page

PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54

LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 54

TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 54

PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 54

CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53

SPPCON(3) — — — — — — SPPOWN SPPEN 55

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.

Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e., 40/44-pin devices).

3: These registers and/or bits are unimplemented on 28-pin devices.

PIC18F2455/2550/4455/4550

10.5 PORTE, TRISE and LATE

Registers

Depending on the particular PIC18F2455/2550/4455/

4550 device selected, PORTE is implemented in two

different ways.

For 40/44-pin devices, PORTE is a 4-bit wide port.

Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP

and RE2/AN7/O ESPP ) are indivi du all y co nfi gura ble a s

inputs or outputs. These pins have Schmitt Trigger

input buffers. Wh en sel ec ted a s an ana log input, these

pins will read as ‘0’s.

The corresponding data direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e. , put th e c orrespo ndi ng outp ut

driver in a high-impedance mode). Clearing a TRISE bit

(= 0) will make the correspond ing POR TE pin an o utput

(i.e., pu t the co ntents o f the output latch on the selecte d

pin).

In addition to port data, the PORTE register

(Register 10-1) also contains the RDPU control bit

(PORTE<7>); this enables or disables the weak

pull-ups on PORTD.

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

The fourth pin of PORTE (MCLR/VPP/RE3) is an input

only pin. Its operat ion is controlled by the MCLRE Config-

urati on b it. Wh en se le cted as a po rt p in (MC LRE = 0), it

funct ions as a digi tal inpu t on ly p in; as such, it d oes n ot

have TRIS or LAT bits associated with its operation.

Otherwise, it functions as the device’s Master Clear input.

In either configuration, RE3 also functions as the

prog ramm ing vo lt age in put duri ng p rog rammin g.

EXAMPLE 10-5: INITIALIZING PORTE

10.5.1 PORTE IN 28-PIN DEVICES

For 28-pin devices, PORTE is only available when Mas-

ter Clear functionality is disabled (MCLRE = 0). In these

cases, PORTE is a sin gle bit, i nput only port compri sed

of RE3 only. The pin operates as previously described.

Note: On a Power-on Reset, RE2:RE0 are

configured as analog inputs.

Note: On a Pow er- on Re set, RE3 i s enab led as

a digital input only if Master Clear

functionality is disabled.

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

MOVLW 0Ah ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 03h ; Value used to

; initialize data

; direction

MOVLW 07h ; Turn off

MOVWF CMCON ; comparators

MOVWF TRISC ; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

R/W-0 U-0 U-0 U-0 R/W-x R/W-0 R/W-0 R/W-0

RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RDPU: PORTD Pull-up Enable bit

1 = PORTD pull-ups are enabled by individual port latch values

0 = All PORTD pull-ups are disabled

bit 6-4 Unimplemented: Read as ‘0’

bit 3-0 RE3:RE0: PORTE Data Input bits(1,2,3)

Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,

read as ‘0’.

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e., 40/44-pin devices).

3: Unimplemented in 28-pin devices; read as ‘0’.

PIC18F2455/2550/4455/4550

TABLE 10-9: PORTE I/O SUMMARY

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Pin Function TRIS

Setting I/O I/O Type Description

RE0/AN5/

CK1SPP RE0 0OUT DIG LATE<0> data output; not affected by analog input.

1IN ST PO RTE<0> data input; disabled when analog input enabled.

AN5 1IN ANA A/D input channel 5; default configuration on POR .

CK1SPP 0OUT DIG SPP clock 1 output (SPP enabled).

RE1/AN6/

CK2SPP RE1 0OUT DIG LATE<1> data output; not affected by analog input.

1IN ST PO RTE<1> data input; disabled when analog input enabled.

AN6 1IN ANA A/D input channel 6; default configuration on POR .

CK2SPP 0OUT DIG SPP clock 2 output (SPP enabled).

RE2/AN7/

OESPP RE2 0OUT DIG LAT E<2> data output; not affected by analog input.

1IN ST PO RTE<2> data input; disabled when analog input enabled.

AN7 1IN ANA A/D input channel 7; default configuration on POR .

OESPP 0OUT DIG S PP enable output (SPP enabled).

MCLR/VPP/

RE3 MCLR —(1) IN ST External Master Clear input; enabled when MCLRE Configuration bit

is set.

VPP — (1) IN ANA High-voltage detection, used for ICSP™ mode entry detection.

Always available regardless of pin mode.

RE3 — (1) I N ST PORTE<3> data input; enabled when MCLRE Configuration bit is

clear.

Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input

Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTE RDPU(3) — — —RE3

(1,2) RE2(3) RE1(3) RE0(3) 54

LATE(3) — — — — — LATE2 LATE1 LATE0 54

TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 54

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53

SPPCON(3) — — — — — — SPPOWN SPPEN 55

SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e., 40/44-pin devices).

3: These registers or bits are unimplemented on 28-pin devices.

PIC18F2455/2550/4455/4550

11.0 T IMER0 MODULE

The T imer0 module incorpo rates the following features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clock source (inte rnal or ex ternal)

• Edge select for external clock

• Interrupt on ov erflow

The T0CON register (Register 11-1) controls all

aspects of the module’s operation, including the

prescale selection. It is both readable and writable.

A simplified block diagram of the Timer0 m odule in 8-bit

mode is shown in Figure 11-1. Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0

0 = Stops Timer0

bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit

1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transit ion on T0CKI pin

0 = Internal instr uction cycle clock (CLKO)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit

1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0 = Timer0 prescaler is assigned. Timer0 clock in put comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits

111 = 1:256 Prescale value

110 = 1:128 Prescale value

101 = 1:64 Prescale value

100 = 1:32 Prescale value

011 = 1:16 Prescale value

010 = 1:8 Prescale value

001 = 1:4 Prescale value

000 = 1:2 Prescale value

PIC18F2455/2550/4455/4550

11.1 Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode is selected by clearing the T0CS bit

(T0CON<5>). In Timer mode, the module increments

on every clock by default unless a different prescaler

value is selected (see Section 11.3 “Prescaler”). If

the TMR0 register is written to, the increment is

inhibited for the following two instruction cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

The Counter mode is selected by setting the T0CS bit

(= 1). In Counter mode, Timer0 increments either on

every rising or falling edge of pin RA4/T0CKI. The

increm enting edg e is determin ed by the T imer0 Sourc e

Edge Select bit, T0SE (T0CON<4>); clearing this bit

selects the rising edge. Restrictions on the external

clock input are dis cu ssed below.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements to ensure

that the external clock can be synchronized with the

internal phase clock (TOSC). There is a delay between

synchronization and the onset of incrementing the

timer/counter.

11.2 Timer0 Reads and Wri tes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode. It is actually a buffered version of the real high

byte of Timer0 which is not directly readable nor

writable (refer to Figure 11-2). TMR0H is updated with

the conte nts of the h igh by te of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

T imer 0 without havi ng to verify tha t the read of the hig h

and low byte were valid, due to a rollover between

successive reads of the high an d low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register . The hig h

byte is updated with the contents of TMR0H when a

write o ccurs to TMR0L. Th is allows all 16 bits o f T imer0

to be updated at once.

FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS2:T0PS0

Set

TMR0IF

on Overflow

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS2:T0PS0

Set

TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

PIC18F2455/2550/4455/4550

11.3 Prescaler

An 8-bi t counter i s availabl e as a presc aler for the T imer0

module. The prescaler is not directly readable or writable;

its value is set by the PSA and T0PS2:T0PS0 bits

(T0CON<3:0>) which determine the prescaler

assi gn ment and presca le ratio.

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When it is assigned, prescale values

from 1:2 through 1:256, in power-of-2 increments, are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0,etc.) clear the prescaler count.

11.3.1 SWITCHI NG PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.4 Timer0 Int e rr u p t

The TMR0 interrupt is generated when the TMR0

from FFFFh to 0000h in 16-bit mode. This overflow set s

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit (INTCON<5>). Before re-

enabling the interrupt, the TMR0IF bit must be cleared

in software by the Interrupt Service Routine.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler is

assign ed to Timer0 will clear th e pr escal er

count but will not change the prescaler

assignment.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

TMR0L Timer0 Register Low Byte 52

TMR0H Timer0 Register High Byte 52

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP 51

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 52

TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54

Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.

Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,

all of the associated bits read ‘0’.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

12.0 TIMER1 MODULE

The Timer1 timer/counter module incorporates these

features:

• Software selectable op eration as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR1H

and TMR1L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt on ov erflow

• Module R eset on CC P Spec ial Even t Trigger

• Device clock status flag (T1RUN)

A simplified block diagram of the Timer1 module is

shown in Fi gure 12-1. A bl oc k di agr am of the module ’s

operatio n in Read /Wr ite mode is show n in Figure 12-2.

The module incorporates its own low-power oscillator

to provide an additional clocking option. The Timer1

oscillator can also be used as a low-power clock source

for the microcontroller in power-managed operation.

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications with only a minimal

addition of external components and code overhead.

Timer1 is controlled through the T1CON Control

Oscillator Enable bit (T1OSCEN). Timer1 can be

enabled or disabled by setting or clearing control bit,

TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer1 in one 16-bit operation

0 = Enables register read/write of Timer1 in two 8-bit operations

bit 6 T1RUN: Timer1 System Clock Status bit

1 = Device clock is deriv ed fr om Timer1 oscillat or

0 = Device clock is derived f rom another source

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Inp ut Clock Pre scale Select bits

11 = 1:8 Pres cale value

10 = 1:4 Pres cale value

01 = 1:2 Pres cale value

00 = 1:1 Pres cale value

bit 3 T1OSCEN: Timer1 Oscillator Enable bit

1 = Timer1 oscillator is enabled

0 = Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2 T1SYNC: Ti me r1 Extern al Cloc k Inpu t Sync hron iz ati on Sele ct bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

PIC18F2455/2550/4455/4550

12.1 Timer1 Operation

Timer1 can operate in one of these modes:

•Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). When TMR1CS is cleared

(= 0), Timer1 increments on every internal instruction

cycle ( F OSC/4). When the bit is set, Timer1 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

When Timer1 is enabled, the RC1/T1OSI/UOE and

RC0/T1OSO/T13CKI pins become inputs. This means

the val ues o f TRISC< 1:0> ar e igno red and the p ins a re

read as ‘0’.

FIGURE 12-1: T I MER1 BLOCK DIAGRAM

FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Sleep Inpu t

T1OSCEN(1)

FOSC/4

Internal

Clock

On/Off

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

TMR1ON

TMR1L TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer1

Set

TMR1IF

on Overflow

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

TMR1ON

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

On/Off

Timer1

PIC18F2455/2550/4455/4550

12.2 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON< 7>) is set, the add ress fo r TMR1H is mappe d

to a buffer r egist er fo r the high b yte o f Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, has

become invalid due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all

16 bit s to both the high and low bytes of T imer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

12.3 Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins T1OSI (input) and T1OSO (amplifier

output). It is enabled by setting the Timer1 Oscillator

Enable bit, T1OSCEN (T1CON<3>). The oscillator is a

low-power circuit rated for 32 kHz crystals. It will

continue to run during all power-managed modes. The

circuit for a typical LP oscillator is shown in Figure 12-3.

Table 12-1 shows the capacitor selection for the Timer1

oscillator.

The user m us t pro vi de a sof tware time delay to ensure

proper start-up of the Timer1 oscillator.

FIGURE 12-3: EXTERNAL

COMPONENTS FOR THE

TI MER1 LP OSCILLATOR

T ABLE 12-1: CAPACITOR SELECTION FOR

THE TIMER OSCILLATOR(2,3,4)

12.3.1 USING TIMER1 AS A CLOCK

SOURCE

The T imer1 oscillator is also available as a clock source

in p ower-m anaged mode s. By s etting t he cloc k select

bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device

switches to SEC_RUN mode. Both the CPU and

periphera ls are clocked from the T imer1 oscil lator . If the

IDLEN bit (OSCCON<7>) is cleared and a SLEEP

instruction is executed, the device enters SEC_IDLE

mode. Additional details are available in Section 3.0

“Power -Mana ged Mod es ” .

Whenever the Timer1 oscillator is providing the clock

source, the Timer1 system clock status flag, T1RUN

(T1CON< 6>), is set. Th is can be us ed to determine th e

controller ’s current clocking mode. It can also indicate

the clock source being currently used by the Fail-Safe

Clock Monitor. If the Clock Monitor is enabled and the

Timer1 oscillator fails while providing the clock, polling

the T1RUN bit will indicate wheth er the clock i s being

provided by the Timer1 oscillator or another source.

12.3.2 LOW-POWER TIMER1 OPTION

The Timer1 oscillator can operate at two distinct levels

of power consumption based on device configuration.

When the LPT1OSC Configuration bit is set, th e Timer1

oscillator operates in a low-power mode. When

LPT1OSC is not set, T imer1 operates at a higher po wer

level. Po we r co ns um ptio n fo r a p art ic ula r mo de is rel a-

tively constant, regardless of the device’s operating

mode. The default Timer1 configuration is the higher

power mode.

As the low-power Timer1 mode tends to be more

sensit ive to interferenc e, h igh noise envi ronm en ts may

cause some oscillator instability. The low-power option

is, therefore, best suited for low noise applications

where power conservation is an important design

consideration.

Note: See the Notes with Table 12-1 for additiona

information about capacitor selection.

XTAL

PIC18FXXXX

T1OSI

T1OSO

32.768 kHz

33 pF

Osc Type Freq C1 C2

LP 32 kHz 27 pF(1) 27 pF(1)

Note 1: Microchip suggests these values as a

starting point in validating the oscillator

circuit.

2: Higher capacit ance inc reases the st abilit y

of the oscillator but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Capacitor values are for design guidance

only.

PIC18F2455/2550/4455/4550

12.3.3 TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a hig h-s pee d cir cui t m us t b e loc ate d near the oscilla-

tor (such as the CCP1 pin in Output Compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 12-4, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 12-4: OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

12.4 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled or disabled

by setting or clearing the Timer1 Interrupt Enable bit,

TMR1IE (PIE1<0>).

12.5 Resetting Time r1 Using the CCP

Special Event Trigger

If eit her o f th e C CP modu le s is co n fig ur e d in C o mpare

mode to generate a Special Event Trigger

(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),

this sig nal wil l reset T i mer1. Th e trigge r from CCP2 wil l

also start an A/D conversion if the A/D module is

enabled (see Section 15.3.4 “ Specia l Event Trigger”

for more information).

The module must be configured as either a timer or a

synch rono us cou nte r to t ak e a dva nt age of this fe atur e.

When used this way, the CCPRH:CCPRL register pair

ef fe cti vely bec om es a period regi ste r for Timer1 .

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

12.6 Using Timer1 as a Real-Time

Clock

Adding an extern al LP os cilla tor to Timer1 (s uch a s the

one described in Section 12.3 “Timer1 Oscillator”)

gives users the option to include RTC functionality to

their applications. This is accomplished with an

inexpensive watch crystal to provide an accurate time

base and several lines of application code to calculate

the time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

the routine, which increments the seconds counter by

one. Additional counters for minutes and hours are

inc remented as t he previous count er overfl ows.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to pre-

load it. The simplest method is to set the MSb of

TMR1H with a BSF instruction. Note that the TMR1L

introduce cumulative error over many cycles.

For this m ethod to be a ccurate, T imer 1 must oper ate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1) as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

Note: The Special Event Triggers from the

CCP2 module will not set the TMR1IF

interrupt flag bit (PIR1<0>).

PIC18F2455/2550/4455/4550

EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

RTCinit

MOVLW 80h ; Preload TMR1 register pair

MOVWF TMR1H ; for 1 second overflow

CLRF TMR1L

MOVLW b’00001111’ ; Configure for external clock,

MOVWF T1OSC ; Asynchronous operation, external oscillator

CLRF secs ; Initialize timekeeping registers

CLRF mins ;

MOVLW d’12’

MOVWF hours

BSF PIE1, TMR1IE ; Enable Timer1 interrupt

RETURN

RTCisr

BSF TMR1H, 7 ; Preload for 1 sec overflow

BCF PIR1, TMR1IF ; Clear interrupt flag

INCF secs, F ; Increment seconds

MOVLW d’59’ ; 60 seconds elapsed?

CPFSGT secs

RETURN ; No, done

CLRF secs ; Clear seconds

INCF mins, F ; Increment minutes

MOVLW d’59’ ; 60 minutes elapsed?

CPFSGT mins

RETURN ; No, done

CLRF mins ; clear minutes

INCF hours, F ; Increment hours

MOVLW d’23’ ; 24 hours elapsed?

CPFSGT hours

RETURN ; No, done

MOVLW d’01’ ; Reset hours to 1

MOVWF hours

RETURN ; Done

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51

PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54

PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54

IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54

TMR1L Timer1 Register Low Byte 52

TMR1H TImer1 Register High Byte 52

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

13.0 TIMER2 MODULE

The Timer2 module timer incorporates the following

features:

• 8-bit timer and period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4 and

1:16)

• Software programmable postscaler (1:1 through

1:16)

• Interrupt on TMR2 to PR2 match

• Optional use as the shift clock for the MSSP

module

The module is controlled through the T2CON register

(Register 13-1) which enabl es or disables the timer and

configu res the prescaler and post scaler. T imer2 c an be

shut of f by clearin g c ontr ol b it, TM R2O N (T2C ON <2 >),

to minimize power consumption.

A simplified block diagram of the module is shown in

Figure 13-1.

13.1 Timer2 Operation

In normal operation, TMR2 is incremented from 00h on

each clock (FOSC/4). A 2-bit counter/prescaler on the

clock input gives direct input, divide-by-4 and divide-by-

16 prescale options. These are selected by the prescaler

control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The

value of TMR 2 is comp ared to that of the period register ,

PR2, on each clock cycle. When the two values match,

the comparator generates a match signal as the timer

output. This signal also reset s the value of TMR2 to 00h

on the next cycle and drives the output counter/

postscaler (see Section 13.2 “T imer 2 Interrupt”).

The TMR2 and PR2 registers are both directl y readable

and writable. The TMR2 register is cleared on any

device Reset, while the PR2 register initializes at FFh.

Both the p rescaler and post scale r counters ar e cleare d

on the following events:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: T imer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Pres cal e Select bit s

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

PIC18F2455/2550/4455/4550
DS39632D-page 136 Preliminary © 2007 Microchip Technology Inc.
13.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This  coun ter gen erat es th e TMR2 m atc h inter rupt  flag
which  is latched in TMR 2IF (P IR 1<1 >). Th e in terru pt i s
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range o f  16  po stscale  op tio ns  (fro m 1 :1  through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
13.3 TMR2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operat io ns in PWM mo de.  
T i mer2 ca n be op tion ally u sed as  the sh ift clo ck so urce
for the MSSP module operating in SPI mode.
Additional information is provided in Section 19.0
“Master Synchronous Serial Port (MSSP) Module”.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM       
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER      
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
Set TMR2IF
Inte rnal D a ta  B u s 8
Reset TMR2/PR2
8
8
(to PWM or MS SP)  
Match
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TMR2 Timer2 Register 52
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
PR2 Timer2 Period Register 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

14.0 TIMER3 MODULE

The Timer3 module timer/counter incorporates these

features:

• Software selectable op eration as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR3H

and TMR3L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt on ov erflow

• Module R eset on CC P Spec ial Even t Trigger

A simplified block diagram of the Timer3 module is

shown in Fi gure 14-1. A bl oc k di agr am of the module ’s

operatio n in Read /Wr ite mode is show n in Figure 14-2.

The Timer3 module is controlled through the T3CON

options for the CCP modules (see Section 15.1.1

“CCP Modules and Timer Resources” for more

information).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation

0 = Enables register read/write of Timer3 in two 8-bit operations

bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

1x = Timer3 is the capture/compare clock source for both CCP modules

01 = Timer3 is the capture/compare clock source for CCP2;

Timer1 is the capture/compare clock source for CCP1

00 = Timer1 is the capture/compare clock source for both CCP modules

bit 5-4 T3CKPS1:T3CKPS0: Timer3 Inp ut Clock Pre scale Select bits

11 = 1:8 Pres cale value

10 = 1:4 Pres cale value

01 = 1:2 Pres cale value

00 = 1:1 Pres cale value

bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the device clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1 TMR3CS: Timer3 Clock Source Select bit

1 = External clock input from Timer1 oscilla tor or T13CKI (on the rising edge after the first fall ing edge)

0 = Internal clock (FOSC/4)

bit 0 TMR3ON: Timer3 On bit

1 = Enables Timer3

0 = Stops Timer3

PIC18F2455/2550/4455/4550

14.1 Timer3 Operation

Timer3 can operate in one of three modes:

•Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>). When TMR3CS is cleared

(= 0), Timer3 increments on every internal instruction

cycle ( F OSC/4). When the bit is set, Timer3 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

As with Timer1, the RC1/T1OSI/UOE and RC0/

T1OSO/T13CKI pins become inputs when the Timer1

oscillator is enabled. This means the values of

TRISC<1:0> are ignored and the pins are read as ‘0’.

FIGURE 14-1: T I MER3 BLOCK DIAGRAM

FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

TMR3ON

TMR3L Se t

TMR3IF

on Overflow

TMR3

High Byte

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer3

CCP1/CCP2 Special Event Trigger

CCP1/CCP2 Select from T3CON<6,3> Cle ar TMR3

Timer1 Clock Input

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR3L

Internal Data Bus

Set

TMR3IF

on Overflow

TMR3

TMR3H

High Byte

Read TMR1L

Write TMR1L

TMR3ON

CCP1/CCP2 Special Event Trigger

Timer1 Oscillator

On/Off

Timer3

Timer1 Clock Input

CCP1/CCP2 Select from T3CON<6,3> Clear TMR3

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 139
PIC18F2455/2550/4455/4550
14.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON< 7>) is set,  the add ress fo r TMR3H is  mappe d
to a  buffer r egist er fo r the  high b yte o f Timer3.  A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bit s to both the high and low bytes of T imer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register. 
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3 Using the Timer1 Oscillator as the 
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting  the T1 OSCEN  (T1CON <3>) bi t. To use i t as th e
T imer3 clock  source, the  TMR3CS bit mu st also be set.
As previously noted, this also configures Timer3 to
increm ent on e very ri sin g edge  of the o scillato r so urce.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Us ing the CCP 
Special Event Trigger
If the CCP2 module is configured to generate a
Special Event Trigger in Compare mode
(CCP2M3:CCP2M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.). 
The module must be configured as either a timer or
synch rono us  cou nte r to t ak e a dva nt age of this fe atur e.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work. 
In the event that a write to Timer3 coincides with a
Special Event T rigger from a CCP module, the write will
take precedence. 
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER        
Note: The Special Event Triggers from the
CCP2 module will not set the TMR3IF
interrupt flag bit (PIR2<1>). 
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
TMR3L Timer 3 Register Low B y te 53
TMR3H Timer3 Register High Byte 53
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18F2455/2550/4455/4550 devices all have two

CCP (Capt ure/Comp are/PWM) modules. Each mo dule

cont ains a 16-bit register , whi ch can opera te as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle regist er.

In 28-pin devices, the two standard CCP modules (CCP1

and CCP2) operate as described in this chapter. In

40/44-pin devices, CCP1 is implemented as an

Enhanced CCP module, with standard Capture and

Compare modes and Enhanced PWM modes. The

ECCP implementation is discussed in Section 16.0

“Enh anced C apture/ Comp are/PWM (ECCP) M odule”.

The Ca pture and Comp are opera tions de scribed in this

chapter apply to all standard and Enhanced CCP

modules.

Note: Throughout this section and Section 16.0

“Enhanced Capture/Comp are/PWM (ECCP)

Module”, references to the register and bit

names for CCP modules are referred to gener-

ically by the use of ‘x’ or ‘y’ in place of the

specific module number. Thus, “CCPxCON”

might refer to the control register for CCP1,

CCP2 or ECCP1. “CCPxCON” is used

throughout these sections to refer to the

module control register regardless of whether

the CCP module is a standard or Enhanced

implementation.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—(1) —(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’(1)

bit 5-4 DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bit s are the two LSbs (bit 1 and bit 0) of th e 10-bit PWM duty cycle. The eig ht MSbs of th e duty

cycle are found in CCPR1L.

bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode: toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high

(CCPxIF bit is set)

1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low

(CCPxIF bit is set)

1010 = Compare mode: generate software interrupt on comp are match (C CP xIF bit is set,

CCPx pin reflects I/O st a te)

1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match

(CCPxIF bit is set)

11xx =PWM mode

Note 1: These bits are not implemented on 28-pin devices and are read as ‘0’.

PIC18F2455/2550/4455/4550

15.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and writable.

15.1.1 CCP MODULES AND TIMER

RESOURCES

The CCP modules utilize Timers 1, 2 or 3, depending

on the mo de selected. T imer1 and T imer3 are available

to modules in Capture or Compare modes, while

Timer2 is available for modules in PWM mode.

TABLE 15-1: CCP MODE – TIMER

RESOURCE

The assignment of a particular timer to a module is

determined by the Timer to CCP enable bits in the

T3CON register (Register 14-1). Both modules may be

acti ve at any given t ime an d may shar e the s ame tim er

resource if they are configured to operate in the same

mode (Capture/Compare or PWM) at the same time. The

interactions between the two modules are summarized in

Figure 15-2. In Timer1 in Asynchronous Counter mode,

the capture operation will not work.

15.1.2 CCP2 PIN ASSIGNMENT

The pin as signment fo r CCP2 (Capture inpu t, Compare

and PW M output) c an chang e, based o n device config-

uration. The CCP2MX Configuration bit determines

which pin CCP2 is multiplexed to. By default, it is

assign ed to RC1 (CC P2MX = 1). If the Configuration bit

is cleared, CCP2 is multiplexed with RB3.

Changing the pin assignment of CCP2 does not

automatically change any requirements for configuring

the port p in. Users m ust always veri fy that the app ropri-

ate TRIS register is configured correctly for CCP2

operation, regardless of where it is located.

TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES

CCP/ECCP Mode Timer Resource

Capture

Compare

PWM

Ti mer1 or Timer3

Timer2

CCP1 Mode CCP2 Mode Interaction

Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different

for each CCP.

Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). Automatic A/D conversions on trigger event

can also be done. Operation of CCP1 could be affected if it is using the same timer as a

time base.

Compare Capture CCP1 be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending

upon which time base is used). Operation of CCP2 could be affected if it is using the

same timer as a time base.

Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.

Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if

both modules are using the same time base.

Capture PWM(1) None

Compare PWM(1) None

PWM(1) Capture None

PWM(1) Compare None

PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).

Note 1: Includes standard and Enhanced PWM operation.

PIC18F2455/2550/4455/4550

15.2 Capture Mode

In Capture mode, the CCPRxH:CCPRxL register pair

captures the 16-bit value of the TMR1 or TMR3

registers when an event occurs on the corresponding

CCPx pin. An event is defined as one of the following:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

The event is selected by the mode select bits,

CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture

is made, the interrupt request flag bit, CCPxIF, is set; it

must be cleared in software. If another capture occurs

before the value in register CCPRx is read, the old

captured value is overwritten by the new captured value.

15.2.1 CCP PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

15.2.2 TIMER1/TIMER3 MODE SELECTION

The tim ers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchr oni zed Count er mode . I n As ynchr ono us Co unt er

mode, the capture operation will not work. The timer to be

used with each CCP module is selected in the T3CON

Resources”).

15.2.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit clear to avoid false

interrupts. The i nterrupt flag bit, CCPxIF, should also be

cleared following any such change in operating mode.

15.2.4 CCP PRESCALER

There are four prescaler settings in Capture mode.

They are specified as part of the operating mode

selected by the mode select bits (CCPxM3:CCPxM0).

Whenever the CCP module is turned off or Capture

mode is disabled, t he prescaler c ounter is cl eared. This

means that any Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleare d, therefore , the first cap ture may be from

a non-zero prescaler. Example 15-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 15-1: CHANGING BETWEEN

CAPTURE PRESCALERS

(CCP2 SHOWN)

FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

Note: If RB3/CCP2 or RC1/CCP2 is configured

as an output, a write to the port can cause

a capture condition.

CLRF CCP2CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP2CON ; Load CCP2CON with

; this value

CCPR1H CCPR1L

TMR1H TMR1L

Set CCP1IF TMR3

Enable

Q1:Q4

CCP1CON<3:0>

CCP1 pin Prescaler

÷ 1, 4, 16 and

Edge Detect TMR1

Enable

T3CCP2

CCPR2H CCPR2L

TMR1H TMR1L

Set CCP2IF

TMR3

Enable

CCP2CON<3:0>

CCP2 pin Prescaler

÷ 1, 4, 16

TMR3H TMR3L

TMR1

Enable

T3CCP2

T3CCP1

T3CCP2

T3CCP1

TMR3H TMR3L

and

Edge Detect

PIC18F2455/2550/4455/4550

15.3 Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against either the TMR1 or TMR3

can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain u nchanged (tha t is, reflect s the state of th e

I/O latch)

The acti on on the pin is b ased on the val ue of the mode

select bits (CCPxM3:CCPxM0). At the same time, the

interrupt flag bit, CCPxIF, is set.

15.3.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

15.3.2 TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

15.3.3 SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCPxM3:CCPxM0 = 1010), t h e c o r res po nd i ng C C Px

pin is not affected. Only a CCP interrupt is generated,

if enabled, and the CCPxIE bit is set.

15.3.4 SPECIAL E VENT TRIGG ER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the Compare Special Event Trigger mode

(CCPxM3:CCPxM0 = 1011).

For either CCP module , the Special Event Tr igger resets

the Timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programm able

period register for either timer.

The S pecial Event Trigge r for C CP2 can a lso start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM

Note: Clearing the CCP2CON register will force

the RB3 or RC1 compare output latch

(dependi ng on devi ce con figuration ) to the

default lo w level. This is not the POR TB or

PORTC I/O data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator Q

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 pin

TRIS

CCP1CON<3:0>

Output Enable

TMR3H TMR3L

CCPR2H CCPR2L

Comparator

T3CCP2

T3CCP1

Set CCP2IF

Compare

(Timer1/Timer3 Reset)

Output

Logic

Specia l Event Trigge r

CCP2 pin

TRIS

CCP2CON<3:0>

Output Enable

(Timer1/Timer3 Reset, A/D Trigger)

Match

Compare

Match

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 145
PIC18F2455/2550/4455/4550
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3    
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN(1) —RI TO PD POR BOR 52
PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 54
TMR1L Timer1 Register Low  Byte 52
TMR1H Timer1 Register High Byte 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
TMR3H Timer3 Register High Byte 53
TMR3L Timer3 Register Low  Byte 53
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
CCPR2L Capture/Compare/PWM Register 2 Low Byte 53
CCPR2H Capture/Compare/PWM Register 2 High Byte 53
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not use d by Captu r e/Co mpare, Timer1 or Timer3.
Note 1: The SBOREN bit is only avail abl e whe n BOREN< 1 :0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

15.4 PWM Mode

In Pulse-W idth Modulati on (PWM) mode, the CCPx pin

produces up to a 10-bit resolution PWM output. Since

the CCP2 pin is multiplexed with a PORTB or PORTC

data latch, the appropriate TRIS bit must be cleared to

make the CCP2 pin an output.

Figure 15-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a ste p-by-step proc edure on how t o set up the CC P

module for PWM operation, see Section 15.4.4

“Setup for PWM Operation”.

FIGURE 15-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 15-4) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 15-4: PWM OUTPUT

15.4.1 PWM PE RIO D

The PWM period is specified by writing to the PR2

following formula:

EQUATION 15-1:

PWM frequency is defined as 1/[PWM period].

When TM R2 is equal to PR2, t he following three event s

occur on the next increment cycle:

•TMR2 is cleared

• The CCPx pin is set (exception: if PWM duty

cycle = 0%, the CCPx pin will not be set)

• The PW M dut y cycle is l atched from CCPR xL into

CCPRxH

15.4.2 PWM DUTY CYCL E

The PWM duty cycle is specified by writing to the

CCPRxL register and to the CCPxCON<5:4> bits. Up

to 10-bit resolution is available. The CCPRxL contains

the eight MSbs and the CCPxCON<5:4> bits contain

the two LSbs. This 10-bit value is represented by

CCPRxL:CCPxCON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

EQUATION 15-2:

CCPRx L an d CC PxC O N<5 :4> c an be w ri tten to a t an y

time, but the duty cycle value is not latched into

CCPRxH until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPRxH is a read-only register.

Note: Clearing the CCP2CON register will force

the RB3 or RC1 output latch (depending

on device configuration) to the default low

level. This is not the PORTB or PORTC

I/O data latch.

CCPRxL

CCPRxH (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCPxCON<5:4>

Clear Timer,

CCPx pin and

latch D.C.

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit

internal Q clock, or 2 bits of the prescaler, to create the

10-bit time base.

CCPx

Corresponding

TRIS bit

Output

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The T imer2 post scalers (see Section 13.0

“Timer2 Module”) are not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Valu e)

PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •

TOSC • (TMR2 Prescale Value)

PIC18F2455/2550/4455/4550

The CCPRxH register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPRxH and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCPx pin is cleared.

The ma ximum P WM res olut ion (b its) fo r a giv en PWM

frequency is given by the equation:

EQUATION 15-3:

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

15.4.3 PWM AUTO -SHUTDOWN

(CCP1 ONLY)

The PWM auto-shutdown features of the Enhanced CCP

module are also available to CCP1 in 28-pin devices. The

operation of this feature is discussed in detail in

Section 16.4.7 “Enha nced PWM Auto- Shutdown” .

Auto-shutdown features are not available for CCP2.

15.4.4 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR xL register and CCPxCON<5:4 > bits.

3. Make the CCPx pin an output by clearing the

appropriate TRIS bit.

4. Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

5. Configure the CCPx module f or PWM operatio n.

Note: If the PWM d uty c ycle v alu e i s lon ger tha n

the PWM period, the CCPx pin will not be

cleared.

FOSC

FPWM

---------------

⎝⎠

⎛⎞

log

2()log

----------------------------- bits=

PWM Resolution (max)

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 10 8 7 6.58

PIC18F2455/2550/4455/4550
DS39632D-page 148 Preliminary © 2007 Microchip Technology Inc.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN(1) —RI TO PD POR BOR 52
PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 54
TMR2 Timer2 Register 52
PR2 Timer2 Period Register 52
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
CCPR2L Capture/Compare/PWM Register 2 Low Byte 53
CCPR2H Capture/Compare/PWM Register 2 High Byte 53
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 53
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: The SBOREN bit is only avail abl e whe n BOREN< 1 :0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

16.0 ENHANCED

CAPTURE/COMPARE/PWM

(ECCP) MODULE

In PIC18F4455/4550 devices, CCP1 is implemented

as a standard CCP module with Enhanced PWM

capabilities. These include the provision for 2 or 4

output channels, user-selectable polarity, dead-band

control and automatic shutdown and restart. The

Enhanced features are discussed in detail in

Section 16.4 “Enhanced PWM Mode”. Capture,

Compare and single output PWM functions of the

ECCP module are the same as described for the

standard CCP module.

The control register for the Enhanced CCP module is

shown in Register 16-1. It differs from the CCPxCON

registers in PIC18F2255/2550 devices in that the two

Most Significant bits are implemented to control PWM

functionality.

Note: The ECCP mo dule is impleme nte d onl y in

40/44-pin devices.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits

If CCP1M3:CCP1M2 = 00, 01, 10:

xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins

If CCP1M3:CCP1M2 = 11:

00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins

01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive

10 = Half-bridg e ou tpu t: P1A, P1B mo dul at ed w i th de ad -ba nd c on tro l; P1C, P1D ass ig ne d as p ort pi ns

11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B1:DC1B0: PWM Duty Cycle Bit 1 and Bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bit s are the tw o LSbs of t he 10-b it PWM d uty cy cle. T he eig ht MSbs of the d uty cy cle ar e found

in CCPR1L.

bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCP module)

0001 = Reserved

0010 = Compare mode, toggle output on match

0011 = Capture mode

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, initialize CCP1 pi n low, set out put on compare matc h (set CCP1IF)

1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)

1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state

1011 = Compare mode, trigger special event (CCP1 resets TMR1 or TMR3, sets CCP1IF bit)

1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high

1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low

1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high

1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low

PIC18F2455/2550/4455/4550
DS39632D-page 150 Preliminary © 2007 Microchip Technology Inc.
In addition to the expanded range of modes available
through  the C CP1CO N regis ter,  the ECC P mod ule ha s
two additional registers associated with Enhanced
PWM opera tion and aut o-shutdown f eatures. They a re:
• ECCP1DEL (Dead-Band Delay) 
• ECCP1AS (Auto-Shutdown Configuration)
16.1 ECCP Outputs and Configuration 
The E nhance d CCP  modul e may h ave up  to  four PW M
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the CCP operating
mode selected. The pin assignments are summarized
in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
P1M1:P1M0 and CCP1M3:CCP1M0 bits. The
appropriate TRISC and TRISD direction bits for the port
pins must also be set as outputs.
16.1.1 ECCP MODULES AND TIMER 
RESOURCES
Like the  standard CCP modules, the ECCP module ca n
utilize Timers 1, 2 or 3, depending on the mode
select ed. Timer1 and Timer3  are a va ila ble  for m od ule s
in Capture or Compare modes, while Timer2 is
available for modules in PWM mode. Interactions
between the standard and En hanced CCP mod ules are
identic al to those d escribed for s tandard  CCP modules.
Additional details on timer resources are provided in
Section 15.1.1 “CCP Modules and Timer
Resources”.
16.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare
Mode”.
16.2.1 SPECIAL E VENT TRIGG ER
The Special Event Trigger output of ECCP resets the
TMR1 o r TMR3 registe r pa ir , depe nding on w hich timer
resource is currently selected. This allows the
CCPR1H:CCPR1L registers to effectively be a 16-bit
programmable period register for Timer1 or Timer3.    
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode, as in Table 16-1.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES  
Note: When setting up single output PWM
operations, users are free to use either of
the processes described in Section 15.4.4
“Setup for PWM Operation” or
Section 16.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.
ECCP Mode CCP1CON
Configuration RC2 RD5 RD6 RD7
All PIC18F4455/4550 devices:
Compatible CCP 00xx 11xx CCP1 RD5/SPP5 RD6/SPP6 RD7/SPP7
Dual PWM 10xx 11xx P1A P1B RD6/SPP6 RD7/SPP7
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.

PIC18F2455/2550/4455/4550

16.4 Enhanced PWM Mode

The Enhanced PWM mode provides additional PWM

output options for a broader range of control applica-

tions. The module is a backwar d compatible version of

the st andard CCP m odule and o ffers up to four output s,

designated P1A through P1D. Users are also able to

select the polarity of the signal (either active-high or

active -low). The module’ s outpu t mode an d polarit y are

configured by setting the P1M1:P1M0 and

CCP1M3:CCP1M0 bits of the CCP1CON register.

Figure 16-1 shows a simplified block diagram of PWM

operatio n. All con trol regi sters are double -buf fe red and

are loaded at the beginning of a new PWM cycle (the

period boundary when Timer2 resets) in order to

prevent gl itches on any of th e output s. The except ion is

the PWM Dead-Band Delay register, ECCP1DEL,

which is loaded at either the duty cycle b oundary or th e

boundary period (whichever comes first). Because of

the buffering, the modul e w a it s un til the as s ign ed timer

resets instead of starting immediately. This means that

Enhanced PWM waveforms do not exactly match the

standard PWM waveforms, but are instead offset by

one full instruction cycle (4 TOSC).

As before, the user must manually configure the

appropriate TRIS bits for output.

16.4.1 PWM PE RIO D

The PWM period is specified by writing to the PR2

following equation:

EQUATION 16-1:

PWM frequency is defined as 1/[PWM period]. When

TMR2 is e qual to PR 2, the foll owing three event s occur

on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (if PW M duty cycle = 0%, the

CCP1 pin will not be set)

• The PWM du ty cy cl e is copi ed from CCPR1L into

CCPR1H

FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

Note: The Timer2 postscaler (see Section 13.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer,

set CCP1 pin and

latch D.C.

Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time

base.

TRISD<4>

CCP1/P1A

TRISD<5>

P1B

TRISD<6>

TRISD<7>

P1D

Output

Controller

P1M1:P1M0 2CCP1M3:CCP1M0

ECCP1DEL

CCP1/P1A

P1B

P1C

P1D

P1C

PIC18F2455/2550/4455/4550

16.4.2 PWM DUTY CYCL E

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The PWM duty cycle is

calculated by the following equation.

EQUATION 16-2:

CCPR1L and CC P1CON <5:4> c an be wr itten to at an y

time, but the duty cycle value is not copied into

CCPR1H until a m atch between PR2 and TM R2 occurs

(i.e., the period is complete). In PWM mode, CCPR1H

is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-b uf feri ng is esse ntial for g litchl ess PWM ope ra-

tion. When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or two bits

of the TMR2 prescaler, the CCP1 pin is cleared. The

maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation.

EQUATION 16-3:

16.4.3 PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allow

one of four configurations:

• Single Output

• Half-Bridge Output

• Full-Bridge Output, For ward mode

• Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM mode

discussed in Section 16.4 “Enhanced PWM Mode”.

The Half-Bridge and Full-Bridge Output modes are

covered in detail in the sections that follow.

The general relationship of the outputs in all

configurations is summarized in Figure 16-2 and

Figure 16-3.

TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4 > •

TOSC • (TMR2 Prescale Value)

Note: If the PWM d uty c ycle v alu e i s lon ger tha n

the PWM period, the CCP1 pin will not be

cleared.

()

PWM Resolution (max) =

FOSC

FPWM

log

log(2) bits

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 10 8 7 6.58

PIC18F2455/2550/4455/4550

FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

Period

SIGNAL PR2 + 1

CCP1CON

<7:6>

P1A Modulated

P1B Modulated

P1A Ac ti ve

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

Duty

Cycle

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Period

SIGNAL PR2 + 1

CCP1CON

<7:6>

P1A Modulated

P1B Modulated

P1A Ac ti ve

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

Duty

Cycle

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * TOSC * (ECCP1DEL<6:0>)

Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).

PIC18F2455/2550/4455/4550

16.4.4 HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as

outputs to drive push-pull loads. The PWM output sig-

nal is outp ut on the P1 A pin , whi le th e comp lem entary

PWM output signal is output on the P1B pin

(Figure 16-4). This mode can be used for half-bridge

applic ati ons , as sh own in Figu re 16-5, or for full-b ridg e

applications where four power switches are being

modulated with two PWM signals.

In Half-Bridge Output mode, the programmable

dead-ban d delay can be used t o preven t shoot-throug h

current in half-bridge power devices. The value of bits

PDC6:PDC0 sets the number of instruction cycles

befor e the output is driven acti ve. If the v alue is g reater

than the duty cycle, the corresponding output remains

inactive during the entire cycle. See Section 16.4.6

“Programmable Dead-Band Delay” for more details

of the dead-band delay operations.

Since the P1A and P1B outputs are multiplexed with

the PORTC<2> and PORTD<5> data latches, the

TRISC<2> and TRISD<5> bits must be cleared to

configure P1A and P1B as outputs.

FIGURE 16-4: HALF-BRIDGE PWM

OUTPUT

FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

Period

Duty Cycle

(1)

P1A(2)

P1B(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

PIC18FX455/X550

P1A

P1B

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

PIC18FX455/X550

P1A

P1B

Standard Half-Bridge Circuit (“Push-Pu ll”)

Half-Bridge Output Drivi ng a Full-Bridge Circu it

PIC18F2455/2550/4455/4550

16.4.5 FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as

outputs; however , only two outputs are active at a time.

In the Forward mode, pin P1A is continuously active

and pin P1D is modulated. In the Reverse mode, pin

P1C is continuously active and pin P1B is modulated.

These are illustrated in Figure 16-6.

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORTC<2>, PORTD<5>, PORTD<6> and

PORTD<7> data latches. The TRISC<2>, TRISD<5>,

TRISD<6> and TRISD<7> bits must be cleared to

make the P1A, P1B, P1C and P1D pins outputs.

FIGURE 16-6: FULL-BRIDGE PWM OUTPUT

Period

Duty Cycle

P1A(2)

P1B(2)

P1C(2)

P1D(2)

Forwar d Mo de

(1)

Period

Duty Cycle

P1A(2)

P1C(2)

P1D(2)

P1B(2)

Reverse Mode

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as active-high.

PIC18F2455/2550/4455/4550

FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION

16.4.5.1 Dire ction C hange in F ull-Bri dge Mod e

In the Full-Bridge Output mode, the P1M1 bit in the

CCP1CON register allows the user to control the

forward/reverse direction. When the application firm-

ware changes this direction control bit, the module will

assume the new direction on the next PWM cycle.

Just before the end of the current PWM period, the

modulated outputs (P1B and P1D) are placed in their

inactiv e state, whil e the unmodula ted outputs (P1A and

P1C) are switched to drive in the opposite direction.

This occurs in a time interval of (4 TOSC * (Timer2

Prescale Value) before the next PWM period begins.

The Timer2 prescaler will be either 1, 4 or 16,

depending on the value of the T2CKPS1:T2CKPS0 bits

(T2CON<1:0>). During the interval from the switch of

the unmodulated outputs to the beginning of the next

period, the modulated outputs (P1B and P1D) remain

inactive. This relationship is shown in Figure 16-8.

Note that in the Full-Bridge Output mode, the ECCP

module do es not provide any dead-b and delay. In gen-

eral, since only one output is modulated at all times,

dead-band delay is not required. However, there is a

situation where a dead-band delay might be required.

This situation occurs when both of the following

conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The tu rn-off ti me of the po wer swi tch, incl uding

the power device and driver circuit, is greater

than the turn-on tim e.

Figure 16-9 shows an example where the PWM direc-

tion changes from forward to reverse at a near 100%

duty cycle. At time t1, the outputs, P1A and P1D,

become inactive, while output P1C becomes active. In

this example, since the turn-off time of the power

device s is longer th an the turn-on time, a shoot-through

current may flow through power devices, QC and QD,

(see Figure 16-7) for the duration of ‘t’. The same

phenomenon will occur to power devices, QA and QB,

for PWM direction change from reverse to forward.

If changing PWM direction at high duty cycle is required

for an application, one of the following requirements

must b e met:

1. Reduce PWM for a PWM period before

changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

P1A

P1C

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

P1B

P1D

QB QD

PIC18FX455/X550

PIC18F2455/2550/4455/4550

FIGURE 16-8: PWM DIRECTION CHANGE

FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Period(1)

SIGNAL

Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals

of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals

are inactive at this time.

Period

(Note 2)

P1A (Active-High)

P1B (Active-High)

P1C (Active-High)

P1D (Active-High)

Forward Period Reverse Period

P1A(1)

tON(2)

tOFF(3)

t = tOFF – tON(2, 3)

P1B(1)

P1C(1)

P1D(1)

External Switch D(1)

Potential

Shoot-Through Current(1)

Note 1: All signals are shown as active-high.

2: tON is the turn-on delay of power switch QC and its driver.

3: tOFF is the turn-off delay of power switch QD and its driver.

External Switch C(1)

PIC18F2455/2550/4455/4550

16.4.6

PROGRAMMABLE DEAD-BAND

DELAY

In half-bridge applications where all power switches are

modulated at the PWM freque ncy at all times, the po wer

switches normally require more time to turn off than to

turn on. If both the upper and lower power switches are

switched at the same time (one turned on and the other

turned of f), both switches may be on for a short period of

time until one switch completely turns off. During this

brief interval, a very high current (shoot-through cu rrent)

may flow through both power switches, shorting the

bridge supply. To avoid this potentially destructive

shoot-through current from flowing during switching,

turning on either of the power switches is normally

delayed to allow the other switc h to comple tely turn off.

In the Half-Bridge Output mode, a digitally program-

mable dead-band delay is available to avoid

shoot-through current from destroying the bridge

powe r switc hes. T he del ay occu rs at t he sign al tran si-

tion from the non-active state to the active state. See

Figure 16-4 for illustration. Bits PDC6:PDC0 of the

ECCP1DEL register (Register 16-2) set the delay

period in terms of microcontroller instruction cycles

(TCY or 4 TOSC). These bits are not available on 28-pin

devi ces, as t he stand ard CCP m odule does not supp ort

half- brid ge ope rati on.

16.4.7

ENHANCED PWM AUTO-SHUTDOWN

When ECCP is programmed for any of the Enhanced

PWM modes, the active output pins may be configured

for auto-shutdown. Auto-shutdown immediately places

the Enhanced PWM output pins into a defined shutdown

state when a shut dow n even t occurs.

A shutdown event can be caused by either of the

comparator modules, a low level on the

RB0/AN12/INT0/FL T0/SDI/SDA pin, or any combination

of these three sources. The comparators may be used to

monitor a voltage input proportional to a current being

monitored in the bridge circuit. If the voltage exceeds a

threshold, the comparator switches state and triggers a

shutdown. Alternatively, a digital signal on the INT0 pin

can also trigger a shut down. The auto-shut down feature

can be disabled by not selecting any auto-shutdown

sources. The auto-shutdown sources to be used are

selected using the ECCPAS2:ECCPAS0 bits (bits<6:4>

of the ECCP1AS register).

When a shutdown occurs, the output pins are

asynchronously placed in their shutdown states,

specified by the PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits (ECCP1AS3:ECCP1AS0). Each

pin pair (P1A/P1C and P1B/P1D) may be set to drive

high, drive low or be tri-stated (not driving). The

ECCPASE bit (ECCP1AS<7>) is also set to hold the

Enhanced PWM outputs in their shut dow n st ates .

The ECCPASE bit is s et by hardware when a shutdow n

event o cc urs. If automati c re starts are no t e nab led , th e

ECCPASE bit is c leared by f irmware when t he caus e of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,

the PWM o utputs remain in their shutdown state for that

entire PW M peri od. Wh en the ECCPASE bi t is cle ared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

Note: Programmable dead-band delay is not

implemented in 28-pin devices with

standard CCP modules.

Note: Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the ECCP ASE bit clears automatically once the shutdown event goes away;

the PWM restarts automatically

0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM)

bit 6-0 PDC6:PDC0: PWM Delay Count bits(1)

Delay ti me, i n numb er o f FOSC/4 (4 * TOSC) cycles, betwee n the s ched uled a nd actual time for a PWM

signal to transition to active.

Note 1: Reserved on 28-pin devices; maintain these bits clear.

PIC18F2455/2550/4455/4550

CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; ECCP outputs are in shutdown state

0 = ECCP outputs are operating

bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits

111 = FLT0 or Comparator 1 or Comparator 2

110 = FLT0 or Comparator 2

101 = FLT0 or Comparator 1

100 = FLT0

011 = Either Co mparator 1 or 2

010 = Comparator 2 output

001 = Comparator 1 output

000 = Auto-shutdown is disabled

bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits

1x = Pins A and C tri-state (40/44-pin devices)

01 = Drive Pins A and C to ‘1’

00 = Drive Pins A and C to ‘0’

bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)

1x = Pins B and D tri-state

01 = Drive Pins B and D to ‘1’

00 = Drive Pins B and D to ‘0’

Note 1: Reserved on 28-pin devices; maintain these bits clear.

PIC18F2455/2550/4455/4550

16.4.7.1 Auto-Shutdown and Auto-Restart

The auto-shutdown feature can be configured to allow

automatic restarts of the module following a shutdown

event. This is enabled by setting the PRSEN bit of the

ECCP1DEL register (ECCP1DEL<7>).

In Shut down mode with PRSEN = 1 (Figure 16-10), the

ECCPASE bit will remain set for as long as the cause

of the shutdown continues. When the shutdown condi-

tion clears, the ECCP1ASE bit is cleared. If PRSEN = 0

(Fig ure 16 -11), o nce a s hutdo wn c ond iti on oc cur s, the

ECCPASE bit will remain set until it is cleared by

firmware. Once ECCPASE is cleared, the Enhanced

PWM will resume at the beginning of the next PWM

period.

Independent of the PRSEN bit setting, if the

auto-shutdown source is one of the comparators, the

shutdown condition is a level. The ECCPASE bit

cannot be cleared as long as the cause of the shutdown

persists.

The Auto-Shu tdown mode can be forced by writing a ‘1’

to the ECCPASE bit.

16.4.8 START-UP CONSIDERATIONS

When the ECCP mo dule is used in t he PWM mode, t he

application hardware must use the proper external pull-up

and/or pull-down resistors on the PWM output pins. When

the microcontroller is released from Reset, all of the I/O

pins are in the high-impedance state. The external circuits

must keep the power switch devices in the OFF state until

the microcontroller drives the I/O pins with the proper

signal levels or activates the PWM output(s).

The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow

the user to choose whether the PW M output signals are

active-high or active-low for each pair of PWM output

pins (P1A/P1C and P1B/P1D). The PWM output

polarities must be selected before the PWM pins are

configu red as output s. Changin g the p olarity conf igura-

tion while the PWM pins are configured as outputs is

not recom mended, sinc e it may result i n damage to th e

application circuits.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is initialized.

Enabling the P WM pins for outp ut at the sa me time as

the ECCP module may cause damage to the applica-

tion circuit . The ECCP module must be enabl ed in the

proper output mode and complete a full PWM cycle

before configuring the PWM pins as o utputs. The com-

pletion o f a f ull PWM c ycle is indicate d by the TMR2I F

bit being set as the second PWM period begins.

FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

Note: Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

Shutdown

PWM

ECCPASE bit

Activity

Event

PWM Period PWM Period PWM Period

Duty Cycle

Dead Time

Duty Cycle

Dead Time

Duty Cycle

Dead Time

Shutdown

PWM

ECCPASE b i t

Activity

Event

PWM Perio d PWM Period P W M Period

ECCPASE

Cleared by Firmware

Duty Cycle

Dead Time

Duty Cycle

Dead Time

Duty Cycle

PIC18F2455/2550/4455/4550

16.4.9 SET UP FOR PWM OP ERA TIO N

The following steps should be taken when configuring

the ECCP module for PWM operation:

1. Configure the PWM pins, P1A and P1B (and

P1C and P1D, if used), as inputs by setting the

corresponding TRIS bits.

2. Set the PWM period by loading the PR2 register .

3. If Auto-Shutdown is required do the following:

• Disable Auto-Shutdown (ECCPASE = 0)

• Configure source (FLT0, Comparator 1 or

Comparator 2)

• Wait for non-shutdown condition

4. Configure the ECCP module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

• Select one of the available output

configurations and direction with the

P1M1:P1M0 bits.

• Select the polarities of the PWM output

signals with the CCP1M3:CCP1M0 bits.

5. Set the PWM du ty cycle by loading the CCPR1L

6. For Half-Bridge Output mode, set the

dead-band delay by loading ECCP1DEL<6:0>

with the appropriate value.

7. If auto-shutdown operation is required, load the

ECCP1AS register:

• Select the auto- shutdown sources using the

ECCPAS2:ECCPAS0 bits.

• Select the shutdown states of the PWM

output pins using the PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits.

• Set the ECCPASE bit (ECCP1AS<7>).

• Config ure the c ompar ators us ing the CMCON

• Configure the comparator inputs as analog

inputs.

8. If auto-restart operation is required, set the

PRSEN bit (ECCP1DEL<7>).

9. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

10. Enable PWM outputs after a new PWM cycle

has started:

• W a it until TM Rn overflo ws (TM RnIF bit is se t).

• Enable the CCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respective TRIS

bits.

• Clear the ECCPASE bit (ECCP1AS<7>).

16.4.10 OPER ATI ON IN POWER-M AN AGED

MODES

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the ECCP pin is driving a value, it will continue

to drive that value. When the device wakes up, it will

continue from this state. If Two-Speed Start-ups are

enabled, the initial start-up frequency fro m INTOSC and

the postscaler may not be stable imm ediately.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

16.4.10.1 Operation with Fail-Safe

Clock Monitor

If the Fai l-Safe Cl ock Monito r is enabl ed, a clock failure

will forc e the d evice i nto the power-m anaged RC_RUN

mode and the OSCFIF bit (PIR2<7>) will be set. The

ECCP will then be clocked from the internal oscillator

clock source, which may have a different clock

frequency than the primary clock.

See the previous section for additional details.

16.4.11 EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

PIC18F2455/2550/4455/4550
DS39632D-page 162 Preliminary © 2007 Microchip Technology Inc.
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset  
Values 
on pa ge
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN(1) —RI TO PD POR BOR 52
IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 54
TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 54
TMR1L Timer1 Register Low Byte 52
TMR1H Timer1 Register High Byte 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
TMR2 Timer2 Module Register 52
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
PR2 Timer2 Period Register 52
TMR3L Timer3 Register Low Byte 53
TMR3H Timer3 Register High Byte 53
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53
CCPR1L Capture/Compare/PWM Register 1 (LSB) 53
CCPR1H Capture/Compare/PWM Register 1 (MSB) 53
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 53
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits or registers are unimplemented in 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

17.0 UNIVERSAL SERIAL BUS

(USB)

This section describes the details of the USB

peripheral. Because of the very specific nature of the

module, knowledge of USB is expected. Some

high-level USB information is provided in

Section 17.10 “O verview of USB” only for appl ication

design reference . Designe rs are encouraged to refer to

the official specification published by the USB Imple-

menters Forum (USB-IF) for the latest information.

USB Specification Revision 2.0 is the most current

specification at the time of publication of this document.

17.1 Overview of the USB Peripheral

The PIC18FX455/X550 device family contains a

full-speed and low-speed compatible USB Serial Inter-

face Engine (SIE) that allows fast communication

between any USB host and the PIC® microcontroller.

The SIE can be interfaced directly to the USB, utilizing

the intern al transceiv er, or it can be co nne cte d through

an external transceiver. An internal 3.3V regulator is

also available to power the internal transceiver in 5V

applications.

Some sp ecial hardw are features ha ve been inc luded to

improve performance. Dual port memory in the

device’s data memory space (USB RAM) has been

supplied to share direct memory access between the

microc ontroller core and th e SIE. Buffe r descriptors a re

also provided, allowing users to freely program end-

point memory usage within the USB RAM space. A

Streaming Parallel Port has been provided to support

the uninterrupted transfer of large volumes of data,

such as isochronous data, to external memory buffers.

Figure 17-1 presents a general overview of the USB

peripheral and its features.

FIGURE 17-1: USB PERIPHERAL AND OPTIONS

UOE(1)

1Kbyte

USB RAM

USB

SIE

USB Control and VM(1)

VP(1)

RCV(1)

VMO(1)

VPO(1)

Transceiver

External

Transceiver

3.3V Regulator

D+

D-

Internal Pull-u ps

UOE

VUSB External 3.3V

Supply(3)

FSEN

UPUEN

UTRDIS

USB Clock from the

Oscillator Module

VREGEN Optional

External

Pull-ups(2)

(Low

(Full

PIC18FX455/X550 Family

SPP7:SPP0

USB Bus

Speed) Speed)

Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).

2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.

3: Do not enable the internal regulator when using an external 3.3V supply.

Configuration

CK1SPP

CK2SPP

CSSPP

OESPP

PIC18F2455/2550/4455/4550

17.2 USB Status and Control

The operation of the USB module is configured and

manage d throu gh three co ntro l regi sters. In additio n, a

total of 22 registe rs are us ed to manage the actual USB

transactions. The registers are:

• USB Control register (UCON)

• USB Configuration register (UCFG)

• USB Transfer Status register (USTAT)

• USB Device Address register (UADDR)

• Frame Number regi sters (UFR MH:UF RML)

• Endpoint Enable registers 0 through 15 (UEPn)

17.2.1 USB CONTROL REGISTER (UCON)

The USB Control register (Register 17-1) contains bits

needed to control the module behavi or during transfers.

The register contains bits that control the following:

• Main USB Peripheral Enable

• Ping-Pong Buffer Pointer Reset

• Control of the Suspend mode

• Packet Transfer Disable

In addition, the USB Control register contains a status

bit, SE0 (UCON<5>), which is used to indicate the

occurrence of a single-ended zero on the bus. When

the USB module is enabled, this bit should be moni-

tored to determine whether the differential data lines

have come out of a single-ended zero condition. This

helps to differentiate the initial power-up state from the

USB Reset signal.

The overall operation of the USB module is controlled

by the USBEN b it (UCON<3>). Setting this bit activates

the module and resets all of the PPBI bits in the Buffer

Descriptor Table to ‘0’. This bit also activates the

on-chip voltage regulator and connects internal pull-up

resisto rs, if they are e nabled. Thus, this bit can be used

as a soft attach/detach to the USB. Although all status

and control bits are ignored when this bit is clear, the

module needs to be fully preconfigured prior to setting

this bit.

U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0

— PPBRST SE0 PKTDIS USBEN RESUME SUSPND —

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks

0 = Ping-Pong Buffer Pointers not being reset

bit 5 SE0: Live Single-Ended Zero Flag bit

1 = Single-ended zero active on the USB bus

0 = No single-ended zero detected

bit 4 PKTDIS: Packet Transfer Disable bit

1 = SIE token and packet processing disabled, automatically set when a SETUP token is received

0 = SIE token and packet processing enabled

bit 3 USBEN: USB Module Enable bit

1 = USB module and supporting circuitry enabled (device attached)

0 = USB module and supporting circuitry disabled (device detached)

bit 2 RESUME: Resume Signaling Enable bit

1 = Resume signaling activated

0 = Resume signaling disabled

bit 1 SUSPND: Suspend USB bit

1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive

0 = USB mo dule and sup porting circuitry in normal o peration, SIE cl ock clocked at the config ured rate

bit 0 Unimplemented: Read as ‘0’

PIC18F2455/2550/4455/4550

The PPBRST bi t (UCON<6>) con trols the Re set st atus

when Double-Buffering mode (ping-pong buffering) is

used. When the PPBRST bit is set, all Ping-Pong

Buffer Pointers are set to the Even buffers. PPBRST

has to be cleared by firmware. This bit is ignored in

buffering mode s not using ping-pong buffering.

The PKTD IS bit (UCON<4> ) is a fla g indicat ing that th e

SIE has disabled packet transmission and reception.

This bit is set by the SIE when a SETUP token is

received to allow setup processing. This bit cannot be

set by the microcontroller, only cleared; clearing it

allows the SIE to continue transmission and/or

reception. Any pending events within the Buffer

Descriptor Table will still be available, indicated within

the USTAT register’s FIFO buffer.

The RESUME bit (UCON<2>) allows the peripheral to

perform a remote wake-up by executing Resume

signaling. To generate a valid remote wake-up,

firmware must set RESUME for 10 ms and then clear

the bit. F or more info rmation o n Resume s ignaling , see

Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0

specification.

The SUSPND bit (UCON<1>) places the module and

supporting circuitry (i.e., voltage regulator) in a

low-power mode. The input clock to the SIE is also

disabled. This bit should be set by the software in

response to an IDLEIF interrupt. It should be reset by

the microcontroller firmware after an ACTVIF interrupt

is obs erved. When t his b it is active, t he dev ice r emain s

attached to the bus but the transceiver outputs remain

Idle. The voltage on the VUSB pin may vary depending

on the value of this bit. Setting this bit before a IDLEIF

request will result in unpredictable bus behavior.

17.2.2 USB CONFIGURATION REGISTER

(UCFG)

Prior to communicating over USB, the module’s

associated internal and/or external hardware must be

configured. Most of the configuration is performed with

the UCFG register (Register 17-2). The separate USB

voltage regulator (see Section 17.2.2.8 “Internal

Regulator”) is controlled through the Configuration

registers.

The UFCG register contains most of the bits that

control the system level behavior of the USB module.

These include:

• Bus Speed (full speed versus low speed)

• On-Ch ip Pull -up Resi st or Enable

• On-Chip Transceiver Enable

• Ping-Pong Buffer Usage

The UCFG register also contains two bits which aid in

module testing, debugging and USB certifications.

These bits control output enable state monitoring and

eye pattern generation.

17.2.2.1 Internal Transceiver

The USB peripheral has a built-in, USB 2.0, full-speed

and low-speed compliant transceiver, internally con-

nected to the SIE. This feature is useful for low-cost

single chip applications. The UTRDIS bit (UCFG<3>)

controls the transceiver; it is enabled by default

(UTRDIS = 0). The FSEN bit (UCFG<2>) controls the

transceiver speed; setting the bit enables full-speed

operation.

The on-chi p USB pull-up resistors are controlle d by the

UPUEN bit (UCFG<4>). They can only be selected

when the on-chip transceiver is enabled.

The USB specification requires 3.3V operation for

commun ica tio ns; ho wev er, the re st of t he ch ip may be

running at a higher voltage. Thus, the transceiver is

supplied power from a separate source, VUSB.

17.2.2. 2 Ex te rn al Transceive r

This module provides support for use with an off-chip

transceiver. The off-chip transceiver is intended for

applic ations w here phys ical co nditions dicta te the loc a-

tion of the transceiver to be away from the SIE. For

example, applications that require isolation from the

USB could use an external transceiver through some

isolation to the microcontroller’s SIE (Figure 17-2).

External transcei ver opera tion is enabled by setting the

UTRDIS bit.

FIGURE 17-2: TYPICAL EXTERNAL

TRANSCEIVER WITH

ISOLATION

Note: While in Suspend mode, a typical bus

powered USB device is limited to 500 μA

of current. This is the complete current

drawn by the PIC device and its support-

ing circuitry. Care should be taken to

assure minimum current draw when the

device enters Suspend mode.

Note: The USB speed, transceiver and pull-up

should only be c onf igured during the mo d-

ule setup phase. It is not recomme nded to

switch these settings while the module is

enabled.

PIC®

Microcontroller

Transceiver

VPO

UOE

Note: The above setting shows a simplified schematic

for a full-speed configuration using an external

transceiver with isolation.

RCV

VMO

D+

D-

Isolation 1.5 kΩ

3.3V Derived

from USB

VUSB

VDD

VDD Isolated

from USB

PIC18F2455/2550/4455/4550

There are 6 signals from the module to communicate

with and control an external transceiver:

• VM: Input from the single-ended D- line

• VP: Input from the single-ended D+ line

• RCV: Input from the differential receiver

• VMO: Output to the differential line driver

• VPO: Output to the differential line driver

•U

OE: Output enable

The VPO and VMO signa ls are outp uts from the SIE to

the external transceiver. The RCV signal is the output

from the external transceiver to the SIE; it represents

the differential signals from the serial bus translated

into a single pulse train. The VM and VP signals are

used to report conditions on the serial bus to the SIE

that can’t be captured with the RCV signal. The

combinations of states of these signals and their

interpretation are listed in Table 17-1 and Table 17-2.

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

UTEYE UOEMON(1) — UPUEN(2,3) UTRDIS(2) FSEN(2) PPB1 PPB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UTEYE: USB Eye Pattern Test Enable bit

1 = Eye pattern test enabled

0 = Eye pattern test disable d

bit 6 UOEMON: USB OE Monitor Enable bit(1)

1 =UOE signal active; it indicates intervals during which the D+/D- lines are driving

0 =UOE

signal inactive

bit 5 Unimplemented: Read as ‘0’

bit 4 UPUEN: USB On-Chip Pull-up Enable bit(2,3)

1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)

0 = On-chip pull-up disabled

bit 3 UTRDIS: On-Chip Transceiver Disable bit(2)

1 = On-chip transceiver disabled; digital transceiver interface enabled

0 = On-chip transceiver active

bit 2 FSEN: Full-Speed Enable bit(2)

1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz

0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz

bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits

11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15

10 = Even/Odd ping-pong buffers enabled for all endpoints

01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0

00 = Even/Odd ping-pong buffers disabled

Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.

2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These

values must be preconfigured prior to enabling the module.

3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ig nored.

PIC18F2455/2550/4455/4550

TABLE 17-1: DIFFERENTIAL OUTPUTS TO

TRANSCEIVER

TABLE 17-2: SINGLE-ENDED INPUTS

FROM TRANSCEIVER

The UOE signal tog gle s the stat e o f the e xte rnal tran s-

ceiver. This line is pulled low by the device to enable

the transmission of data from the SIE to an external

device.

17.2.2.3 Internal Pull-up Resistors

The PIC18FX455/X550 devices have built-in pull-up

resistors designed to meet the requirements for

low-speed and full-speed USB. The UPUEN bit

(UCFG<4>) enables the internal pull-ups. Figure 17-1

shows the pull-ups and their control.

17.2.2.4 External Pull-up Resistors

External pull-up may also be used. The V USB pin may be

used to pull up D+ or D-. The pull-up resistor must be

1.5 kΩ (±5%) as required by the USB specifications.

Figure 17-3 shows an example.

FIGURE 17-3: EXTERNAL CIRCUITRY

17.2.2.5 Ping-Pong Buffer Configuration

The usage of pin g-pong buff ers is configu red using the

PPB1:PPB0 bit s. Refe r to Section 17.4.4 “Ping-Pong

Buffering” for a complete explanation of the ping-pong

buffers.

17.2.2.6 USB Output Enable Monitor

The USB OE moni tor prov ides i ndica tion as to wheth er

the SIE is listening to the bus or actively driving the bus.

This is enabled by default when using an external

transceiver or when UCFG<6> = 1.

The USB OE monitoring is useful for initial system

debugging, as well as scope triggering during eye

pattern generation tests.

17.2.2.7 Eye Pattern Test Enable

An automatic eye pattern test can be generated by the

module when the UCFG<7> bit is set. The eye pattern

output will be observable based on module settings,

meaning that the user is first responsible for config uring

the SIE cloc k se ttings, pull-up resi stor and Transceiver

mode. In addition, the module has to be enabled.

Once UTEYE is set, the module emulates a switch from

a receive to transmit state and will start transmitting a

J-K-J-K bit sequence (K-J-K-J for full speed). The

sequence will be repeated indefinitely while the Eye

Pattern Test mode is ena ble d.

Note that this bit should never be set while the module

is connected to an actual USB system. This test mode

is intended for board verification to aid with USB certi-

ficatio n tests. It is intende d to show a system de veloper

the noise integrity of the USB signals which can be

affected by board traces, impedance mismatches and

proximity to other system components. It does not

properly test the transition from a receive to a transmit

state. Although the eye pattern is not meant to replace

the more complex USB certification test, it should aid

during first order system debugging.

17.2.2.8 Internal Regulator

The PIC18FX455/X550 devices have a built-in 3.3V reg-

ulator to provide power to the internal transceiver and

provide a source for the internal/external pull-ups. An

external 220 nF (±20%) capacitor is required for stability .

The regul ator is enabled b y default and can be disa bled

through the VREGEN Configuration bit. When enabled,

the voltage is visible on pin VUSB. When the regulator

is disabled, a 3.3V source must be provided through

the VUSB pin for the internal transceiver. If the internal

transceiver is disabled, VUSB is not used.

VPO VMO Bus State

00 Single-Ended Zero

01 Dif fere nti al ‘0’

10 Dif fere nti al ‘1’

11 Illegal Condition

VP VM Bus State

00 Single-Ended Zero

01 Low Speed

10 High Speed

11 Error

PIC®

Microcontroller Host

Controller/HUB

VUSB

D+

D-

Note: The above setting shows a typical connection

for a full-speed configuration using an on-chip

regulator and an external pull-up resistor.

1.5 kΩ

Note: The drive from VUSB is sufficient to only

drive an external pull-up in addition to the

internal transceiver.

Note 1: Do no t ena ble th e int ernal regul ator if an

external regulator is connected to VUSB.

2: VDD must be greater than VUSB at all

times, even with the regulator disabled.

PIC18F2455/2550/4455/4550

17.2.3 USB STATUS REGISTER (USTAT)

The USB Status register reports the transaction status

within the SIE. When the SIE issues a USB transfer

comple te interrupt, USTA T sho uld be read t o determine

the status of the transfer. USTAT contains the transfer

endpoint number, direction and Ping-Pong Buffer

Pointer value (if used).

The USTAT register is actually a read window into a

four-byte status FIFO, maintained by the SIE. It allows

the microcontroller to process one transfer while the

SIE processes additional endpoints (Figure 17-4).

When the SIE completes using a buffer for reading or

writing data, it updates the USTAT register. If another

USB transfer is performed before a transaction

complete interrupt is serviced, the SIE will store the

status of the next transfer into the status FIFO.

Clearing the transfer complete flag bit, TRNIF, causes

the SIE to advance the FIFO. If the next data in the

FIFO holding register is valid, the SIE will immediately

reassert the interrupt. If no additional data is present,

TRNIF will remain clear; USTAT data will no longer be

reliable.

FIGURE 17-4: USTAT FIFO

Note: The data in the USB S tatus registe r is valid

only when the TRNIF interrupt flag is

asserted.

Note: If an endpoint request is received while the

USTAT FIFO is full, the SIE will

automatically issue a NAK back to the

host.

Data Bus

USTAT from SIE

4-byte FIFO

for USTAT Clearing TRNIF

Advances FIFO

U-0 R-x R-x R-x R-x R-x R-x U-0

— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits

(represents the number of the BDT updated by the last USB transfer)

1111 = Endpoint 15

1110 = Endpoint 14

....

0001 = Endpoint 1

0000 = Endpoint 0

bit 2 DIR: Last BD Direction Indicator bit

1 = The last transaction was an IN token

0 = The last transaction was an OUT or SETUP token

bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)

1 = The last transaction was to the Odd BD bank

0 = The last transaction was to the Even BD bank

bit 0 Unimplemented: Read as ‘0’

Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.

PIC18F2455/2550/4455/4550

17.2.4 USB ENDPOINT CONTROL

Each of the 16 possible bidirectional endpoints has its

own ind ependent control registe r , UEPn (wh ere ‘n’ rep-

resents the endpoint number). Each register has an

identical complement of control bits. The prototype is

shown in Register 17-4.

The EPHSHK bit (UEPn<4>) controls handshaking for

the end point; setting this bit enables USB han dshaking.

Typically, this bit is always set except when using

isochro no us endpoints .

The EPCONDIS bit (UEPn<3>) is used to enable or

disable USB control operations (SETUP) through the

endpoint. Clearing this bit enables SETUP transac-

tions. Note that the corresponding EPINEN and

EPOUTEN bits must be set to enable IN and OUT

tran sa cti o ns . Fo r E n dp oi nt 0, t his bi t sh o ul d al w a ys be

cleared since the USB specifications identify

Endpoint 0 as the default control endpoint.

The EPOUTEN bit (U EPn<2>) is used to enable or dis -

able USB OUT transactions from the host. Setting this

bit enable s OUT transactions. Similarly , the EPINEN bit

(UEPn<1>) enables or disables USB IN transactions

from the host.

The EPSTALL bit (UEPn<0>) is used to indicate a

STALL co nd i tio n f o r t h e e n dp oin t . If a STALL i s i s su ed

on a particular endpoint, the EPSTALL bit for that end-

point pair will be set by the SIE. This bit remains set

until it is cleared through firmware, or until the SIE is

reset.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 EPHSHK: Endpoi nt Han dshak e Enab le bit

1 = Endpoint handshake enabled

0 = Endpoint handshake disabled (typically used for isochronous endpoints)

bit 3 EPCONDIS: Bidirectional Endpoint Control bit

If EPOUTEN = 1 and EPINEN = 1:

1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed

0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed

bit 2 EPOUTEN: Endpoi nt Out put Enab le bit

1 = Endpoint n output ena ble d

0 = Endpoint n output dis ab led

bit 1 EPINEN: Endpoint Input Enable bit

1 = Endpoint n input enab led

0 = Endpoint n input dis abl ed

bit 0 EPSTALL: Endpoi nt Stall Enable bit(1)

1 = Endpoint n is stalled

0 = Endpoint n is not stalled

Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.

PIC18F2455/2550/4455/4550

17.2.5 USB ADDRESS REGISTER

(UADDR)

The USB Address register contains the unique USB

address that the peripheral will decode when active.

UADDR is reset to 00h when a USB Re set is received,

indica ted by URSTIF, or when a R eset is receiv ed fro m

the microcontroller. The USB address must be written

by the microcontroller during the USB setup phase

(enumeration) as part of the Microchip USB firmware

support.

17.2.6 USB FRAME NUMBER REGISTERS

(UFRMH:UFRML)

The Frame Number registers contain the 11-bit frame

number. The low-order byte is contained in UFRML,

while the three high-order bits are contained in

UFRMH. The register pair is updated with the current

frame number whenever a SOF token is received. For

the microcontroller, these registers are read-only. The

Frame Number register is primarily used for

isochronous transfers.

17.3 USB RAM

USB dat a mo ves b etwe en the m icroc ontrol ler co re and

the SIE through a memory space known as the USB

RAM. This is a special dual port memory that is

mapped into the no rmal data memory sp ace in Ban ks 4

through 7 (400h to 7FFh) for a total of 1 Kbyte

(Figure 17-5).

Bank 4 (400h through 4FFh) is used specifically for

endpoint buffer control, while Banks 5 through 7 are

available for USB data. Depending on the type of

buffering being used, all but 8 bytes of Bank 4 may also

be avail able for use as USB buffer space.

Although USB RAM is available to the microcontroller

as data memory, the sections that are being accessed

by the SIE should not be accessed by the

microcontroller. A semaphore mechanism is used to

determine the access to a particular buffer at any given

time. This is discussed in Section 17.4.1.1 “Buffer

Ownership”.

FIGURE 17-5: IMPLEMENTATION OF

USB RAM IN DATA

MEMORY SPACE

400h

4FFh

7FFh

500h

USB Data or

Buffer Descriptors,

USB Data or User Data

User Data

Unused

SFRs

3FFh

000h

F60h

FFFh

Banks 0

Banks 4

Bank15

(USB RAM)

F00h

Banks 8

800h

to 14

to 3

to 7

PIC18F2455/2550/4455/4550

17.4 Buffer Descriptors and the Buffer

Descriptor Table

The registers in Bank 4 are used specifically for end-

point buffer control in a structure known as the Buffer

Descriptor Table (BDT). This provides a flexible method

for users to construct and control endpoint buffers of

various lengths and configuration.

The BDT i s composed of Buf fer Descript ors (BD) which

are used to define and control the actual buffers in the

USB RAM space. Each BD, in turn, consists of four reg-

isters, where n represents one of the 64 possible BDs

(range of 0 to 63):

• BDnSTAT: BD Status register

• BDnCNT: BD Byte Count register

• BDnADRL: BD Address Low register

• BDnADRH: BD Address High register

BDs alwa ys occu r as a four-byt e block in

the sequence,

BDnST AT:BDnCNT:BDnADRL:BDnADRH.

The address

of BDnSTAT is always an offset of (4n – 1) (in hexa-

decimal) from 400h, with n being the buffer descriptor

number.

Depending on the buffering configuration used

(Section 17.4.4 “Ping-Pong Buffering”), there are up

to 32, 33 o r 64 sets of buffer d escriptors. At a mi nimum,

the BDT mu st b e a t least 8 byt es lon g. This i s b ec aus e

the USB specification mand ates that every device must

have Endpoint 0 with both input and output for initial

setup. Depending on the endpoint and buffering

configuration, the BDT can be as long as 256 bytes.

Although they can be thought of as Special Function

Registers, the Buffer Descriptor Status and Address

registers are not hardware mapped, as conventional

microcontroller SFRs in Bank 15 are. If the endpoint cor-

respo nding to a p artic ular BD is no t enabled , its regis ters

are not used. Instead of appearing as unimplemented

addresses, however, they appear as available RAM.

Only when an endpoint is enabled by setting the

UEPn<1> bit does the memory at those addresses

become functional as BD registers. As with any address

in the data memory space, the BD registers have an

indeterminat e v alue on any devi ce Rese t.

An example of a BD for a 64-byte buffer, starting at

500h, is shown in Figure 17-6. A particular set of BD

been e nabled usi ng the UEPn re gister. All BD re giste rs

are available in USB RAM. The BD for each endpoint

should be set up prior to enabling the endpoint.

17.4.1 BD STATUS AND CONFIGURATION

Buffer descriptors not only define the size of an end-

point buffer, but also determine its configuration and

control. Most of the configuration is done with the BD

St at us reg is ter, BDnSTAT. Each BD h as i t s ow n un iqu e

and correspondingly numbered BDnSTAT register.

FIGURE 17-6: EXAMPLE OF A BUFFER

DESCRIPTOR

Unlike other control registers, the bit configuration for

the BDnSTAT register is context sensitive. There are

two distinct configurations, depending on whether the

microc ontroll er or the USB module is modif ying the BD

and buf f er at a p artic ular time . Only three b it defi nitions

are shared between the two.

17.4.1.1 Buffer Ownership

Because the buf fers and the ir BDs are shar ed between

the CPU and the USB module, a simple semaphore

mechanism is used to distinguish which is allowed to

update the BD and associated buffers in memory.

This is don e by usin g the UOWN bit (BDnSTA T <7>) as

a semaphore to distinguish which is allowed to update

the BD and associa ted buffers in memory. UOWN is the

only bit that is shared between the two configurations

of BDnSTAT.

When UOWN is clear, the BD entry is “owned” by the

microcontroller core. When the UOWN bit is set, the BD

entry and the buffer memory are “owned” by the USB

peripheral. The core should not modify the BD or its

corresponding data buffer during this time. Note that

the microcontroller core can still read BDnSTAT while

the SIE owns the buffer and vice versa.

The buffer descriptors have a different meaning based

on the source of the register update. Prior to placing

ownership with the USB peripheral, the user can con-

figure the bas ic oper ation of the periphera l thro ugh the

BDnSTAT bits. During this time, the byte count and

buffer location registers can also be set.

When U OW N is s et, the us er c an no lo nge r de pend on

the valu es that were writ ten to the BDs. Fr om this point,

the SIE updates the BDs as n ece ss ary, ove rwr iti ng th e

original BD values. The BDnSTAT register is updated

by the SIE with the token PID and the transfer count,

BDnCNT, is updated.

400h

USB Data

Buffer

BD0STAT

BD0CNT

BD0ADRL

BD0ADRH

401h

402h

403h

500h

53Fh

Descriptor

Note: Memory regions not to scale.

40h

00h

05h Starting

Size of Block

(xxh)

RegistersAddress Contents

Address

PIC18F2455/2550/4455/4550

The BDnSTAT byte of the BDT should always be the

last byte updated when preparing to arm an endpoint.

The SIE will clear the UOWN bit when a transaction

has co mplet ed. The on ly excep tion to th is is w hen KEN

is enabled and/or BSTALL is enabled.

No ha rdware mecha nism e xists t o bloc k acce ss when

the UOWN bit is set. Thus, unexpected behavior can

occur if the microcontroller attempts to modify memory

when the SIE owns it. Similarly, reading such memory

may produce inaccurate data until the USB peripheral

returns ownership to the microcontroller.

17.4.1.2 BDnSTAT Register (CPU Mode)

When UOWN = 0, the microcontroller core owns the

BD. At this point, the other seven bits of the register

take on control functions.

The Keep Enable bit, KEN (BDnSTAT<5>), determine s

if a BD stays enabled. If the bit is set, once the UOWN

bit is set, it will remain owned by the SIE independent

of the endpoint activity. This prevents the USTAT FIFO

from being updated, as well as the transaction

comple te interrupt from bei ng set for the endp oint. This

feature should only be enabled when the Streaming

Parallel Port is se lected as the data I/O channel instead

of USB RAM.

The Address Increment Disable bit, INCDIS

(BDnSTAT<4>), controls the SIE’s automatic address

increment function. Setting INCDIS disables the

auto-increment of the buffer address by the SIE for

each byte transmitted or received. This feature should

only be enabled when using the Streaming Parallel

Port, where each data byte is processed to or from the

same memory location.

The Data Toggle Sync Enable bit, DTSEN

(BDnSTAT<3>), controls data toggle parity checking.

Setting D TSEN enables dat a toggle sy nchronization b y

the SIE. When enabled, it checks the data packet’s par-

ity aga inst the v alue of DTS (BDnSTAT<6>). If a p acket

arri ves with an in correc t synchr onizati on, th e data wi ll

essentially be ignored. It will not be written to the USB

RAM and the USB transfer complete interrupt flag will

not be set. The SIE will send an ACK token b ack to the

host to Acknowledge receipt, however. The effects of

the DTSEN bit on the SIE are summarized in

Table 17-3.

The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides

support for control transfers, usually one-time stalls on

Endpoint 0. It also provides support for the

SET_FEATURE/CLEAR_FEATURE commands speci-

fied in Chapter 9 of the USB specification; typically,

continuous STALLs to any endpoint other than the

default control endpoint.

The BSTALL bit enables buffer stalls. Setting BSTALL

causes the SIE to re turn a STALL toke n to the host if a

received token would use the BD in that location. The

EPSTALL bit in the corresponding UEPn control regis-

ter is set and a STALL interrupt is generated when a

ST ALL is issued to the host. The UOWN bit remains set

and the BDs are n ot ch anged unle ss a SETUP token is

received. In this case, the STALL condition is cleared

and the ownership of the BD is returned to the

microcontroller core.

The BD9: BD8 bits (BDn ST AT<1:0>) store the two m ost

significant digits of the SIE byte count; the lower 8 digits

are stored in the corresponding BDnCNT register. See

Section 17.4.2 “BD Byte Count” for more

information.

TABLE 17-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION

OUT Packet

from Host

BDnSTAT Settings Device Response after Receiving Packet

DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status

DATA0 10ACK 01 Updated

DATA1 10ACK 10 Not Updated

DATA0 11ACK 01 Updated

DATA1 11ACK 10 Not Updated

Either 0xACK 01 Updated

Either, with error xxNAK 10 Not Updated

Legend: x = don’t care

PIC18F2455/2550/4455/4550

BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

UOWN(1) DTS(2) KEN INCDIS DTSEN BSTALL BC9 BC8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UOWN: USB Own bit(1)

0 = The microcontroller core owns the BD and its corresponding buffer

bit 6 DTS: Data Toggle Synchronization bit(2)

1 = Data 1 packet

0 = Data 0 packet

bit 5 KEN: BD Keep Enable bit

1 = USB will keep the BD indefinitely once UOWN is set (required for SPP endpoint configuration)

0 = USB will hand back the BD once a token has been processed

bit 4 INCDIS: Address Increment Disable bit

1 = Address increment disabled (required for SPP endpoint configuration)

0 = Address increment enabled

bit 3 DTSEN: Data Toggle Synchronization Enable bit

1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored

except for a SETUP transaction, which is accepted even if the data toggle bits do not match

0 = No data toggle synchronization is performed

bit 2 BSTALL: Buffer Stall Enable bit

1 = Buffer stall ena ble d; STALL handshake is su ed i f a tok en is rec ei ve d tha t woul d us e the BD in the

given location (UOWN bit remains set, BD value is unchanged)

0 = Buffer stall disabled

bit 1-0 BC9:BC8: Byte Count 9 and 8 bits

The byte count bits represent the number of bytes that will be transmitted for an IN token or received

during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.

Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.

2: This bit is ignored unless DTSEN = 1.

PIC18F2455/2550/4455/4550

17.4.1.3 BDnSTAT Register (SIE Mode)

When th e BD a nd it s buf fer ar e owned b y the SI E, most

of the bit s in BDnST A T t ake on a different meaning. The

configuration is shown in Register 17-6. Once UOWN

is set, any data or control settings previously written

there by the user will be overwritten with data from the

SIE.

The BDnSTAT register is updated by the SIE with the

token Packet Identifier (PID) which is stored in

BDnSTAT<5:3>. The transfer count in the correspond-

ing BDnCNT register is updated. Values that overflow

the 8-bit register carry over to the two most significant

digit s of the cou nt, sto red in BDnS TAT<1:0>.

17.4.2 BD BYTE COUNT

The byte count represents the total number of bytes

that will be tran smitted during an IN transfer . After an IN

transfer, the SIE will re turn the n umb er of byt es s en t to

the host.

For an OUT transfer, the byte count represents the

maximum number of bytes that can be received and

stored in USB RAM. After an OUT tran sfer, the SIE will

return the actual number of bytes received. If the

number of bytes received exceeds the corresponding

byte count, the data packet will be rejected and a NAK

handshake will be generated. When this happens, the

byte count will not be updated.

The 10 -bit by te coun t is di stribu ted ov er two re giste rs.

The lower 8 bits of the count reside in the BDnCNT

This represents a valid byte range of 0 to 1023.

17.4.3 BD ADDRESS VALIDATION

The BD Address register pair contains the starting RAM

address location fo r the corre spond ing end point bu ffe r.

For an endpoint starting location to be valid, it must fall

in the range of the USB RAM, 400h to 7FFh. No

mechanism is available in hardware to validate the BD

address.

If the value of the BD address does not point to an

address in the USB RAM, or if it points to an address

within ano ther endpoint’s buffer, data is li ke ly t o be lost

or overwritten. Similarly, overlapping a receive buffer

(OUT endpoint) with a BD location in use can yield

unexpected results. When developing USB

applications, the user may want to consider the

inc lusion of so ftwar e-bas ed ad dress valida tion in t heir

code.

BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE

MICROCONTROLLER)

R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

UOWN — PID3 PID2 PID1 PID0 BC9 BC8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UOWN: USB Own bit

1 = The SIE owns the BD and its corresponding buffer

bit 6 Reserved: Not written by the SIE

bit 5-2 PID3:PID0: Packet Identifier bits

The received token PID value of the last transfer (IN, OUT or SETUP transactions only).

bit 1-0 BC9:BC8: Byte Count 9 and 8 bits

These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer

and the actual number of bytes transmitted on an IN transfer.

PIC18F2455/2550/4455/4550

17.4.4 PING-P O NG BUFFERING

An endpoi nt is defined to have a ping-po ng buffer w hen

it has two sets of BD entries: one set for an Even

transfer and one set for an Odd transfer . This allows the

CPU to pr ocess one BD while the SIE is processi ng the

other BD. Double-buffering BDs in this way allows for

maximum thr oughput to/f rom the USB.

The USB module supports four modes of operation:

• No ping-p ong suppo rt

• Ping-pong buffer support for OUT Endpoint 0 only

• Ping-pong buffer support for all endpoints

• Ping-pong buffer support for all other Endpoints

except Endpoint 0

The ping-pong buffer settings are configured using the

PPB1:PPB0 bits in the UCFG register.

The USB modu le keep s trac k of the Ping-Pon g Pointer

individually for each endpoint. All pointers are initially

reset to the Even BD when the modul e is enabled. After

the completion of a transaction (UOWN cleared by the

SIE), the pointer is toggled to the Odd BD. After the

completion of the next transaction, the pointer is

toggled back to the Even BD and so on.

The Even /Odd s ta tus of the las t trans actio n is st ored i n

the PPBI bit of the USTAT register. The user can reset

all Ping-Pong Pointers to Even using the PPBRST bit.

Figure 17-7 shows the four different modes of

operation and how USB RAM is filled with the BDs.

BDs have a fixed relationship to a particular endpoint,

dependi ng on the bufferi ng configuration . The mappin g

of BDs to endpoints is detailed in Table 17-4. This

relationship also means that gaps may occur in the

BDT if endpoints are not enabled contiguously. This

theoretic ally means that the BDs fo r disabled endpoint s

could be used as buffer space. In practice, users

should avoid using such spaces in the BDT unless a

method of validating BD addresses is implemented.

FIGURE 17-7: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES

EP1 IN Even

EP1 OUT Even

EP1 OUT Odd

EP1 IN Odd

Descriptor

EP1 IN

EP15 IN

EP1 OUT

EP0 OUT

PPB1:PPB0 = 00

EP0 IN

EP1 IN

No Ping-Pong

EP15 IN

EP0 IN

EP0 OUT Even

PPB1:PPB0 = 01

EP0 OUT Odd

EP1 OUT

Ping-Pong Buffer

EP15 IN Odd

EP0 IN Even

EP0 OUT Even

PPB1:PPB0 = 10

EP0 OUT Odd

EP0 IN Odd

Ping-Pong Buffers

Descriptor

400h

4FFh 4FFh 4FFh

400h 400h

47Fh

483h

Available

Data RAM Available

Data RAM

Maxi mum Memory

Use d: 128 bytes

Maxi mum BDs:

32 (BD0 to BD31)

Maxi mum Memory

Used: 132 bytes

Maximum BDs:

33 (BD0 to BD32)

Maxi mum Memory

Used: 256 bytes

Maximum BDs: 6

4 (BD0 to BD63)

Note: Memory area not shown to scale.

Descriptor

Buffers on EP0 OUT on all EPs

EP1 IN Even

EP1 OUT Even

EP1 OUT Odd

EP1 IN Odd

Descriptor

EP15 IN Odd

EP0 OUT

PPB1:PPB0 = 11

EP0 IN

Ping-Pong Buffers

Descriptor

4FFh

400h

Maximum Memory

Used: 248 bytes

Maximum BDs:

62 (BD0 to BD61)

on all ot he r EPs

except EP0

Available

Data RAM

4F7h

PIC18F2455/2550/4455/4550

TABLE 17-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT

BUFFERING MODES

TABLE 17-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Endpoint

BDs Assigned to Endpoint

Mode 0

(No Ping-Pong) Mode 1

(Ping- Pong on EP0 OUT) Mode 2

(Ping-Pong on all EPs)

Mode 3

(Ping-P ong on all other EPs,

except EP0)

Out In Out In Out In Out In

0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1

1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O)

2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O)

3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)

4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)

5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)

6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)

7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)

8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O)

9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O)

10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O)

11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O)

12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O)

13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O)

14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O)

15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O)

Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BDnSTAT(1) UOWN DTS(4) PID3(2)

KEN(3) PID2(2)

INCDIS(3) PID1(2)

DTSEN(3) PID0(2)

BSTALL(3) BC9 BC8

BDnCNT(1) Byte Count

BDnADRL(1) Buf fer Addre ss Low

BDnADRH(1) Buffer Addre ss High

Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are

shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).

2: Bits 5 throug h 2 of t he BD nSTAT register ar e used by the SIE to re turn PID3:PI D0 valu es onc e the registe r

is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values

written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.

3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the

BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.

4: This bit is ignored unless DTSEN = 1.

PIC18F2455/2550/4455/4550

17.5 USB Interrupts

The USB module can generate multiple interrupt con-

ditions . To accommodat e all of these i nterrupt s ources ,

the module is provided with its own interrupt logic

structure, similar to that of the microcontroller. USB

interrupts are enabled with one set of control registers

and trapped with a separate set of flag registers. All

sources are funneled into a single USB interrupt

request, USBIF (PIR2<5>), in the microcontroller’s

inter rupt log ic .

Figure 17-8 shows the interrupt logic for the USB

module. There are two layers of interrupt registers in

the USB mo dul e. Th e top lev el c ons is t s of ov era ll US B

status interrupts; these are enabled and flagged in the

UIE and UIR registers, respectively. The second level

consists of USB error conditions, which are enabled

and flagged in the UEIR and UEIE registers. An

interrupt condition in any of these triggers a USB Error

Interrupt Flag (UERRIF) in the top level.

Interrupts may be used to tr ap rou tin e ev ents in a USB

transaction. Figure 17-9 shows some common events

within a USB frame and their corresponding interrupts.

FIGURE 17-8: USB INTERRUPT LOGIC FUNNEL

FIGURE 17-9: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

BTSEF

BTSEE

BTOEF

BTOEE

DFN8EF

DFN8EE

CRC16EF

CRC16EE

CRC5EF

CRC5EE

PIDEF

PIDEE

SOFIF

SOFIE

TRNIF

TRNIE

IDLEIF

IDLEIE

STALLIF

STALLIE

ACTVIF

ACTVIE

URSTIF

URSTIE

UERRIF

UERRIE

USBIF

Second Level USB Interrupts

(USB Error Conditions)

UEIR (Flag) and UEIE (Enable) Registers

Top Level USB Interrupts

(USB Status Interrupts)

UIR (Flag) and UIE (Enable) Registers

USB Reset

SOFRESET SETUP DATA STATUS SOF

SETUPToken Data ACK

OUT Token Empty Data ACK

START-OF-FRAME

IN Token Data ACK

SOFIF

URSTIF

1 ms Frame

Differential Data

From Host From Host To Host

From Host To Host From Host

From Host From H ost To Host

Transaction

Control Transfer(1)

Transaction

Complete

Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers

will spread across multiple frames.

Set TRNIF

PIC18F2455/2550/4455/4550

17.5.1 USB INTERRUPT STATUS

The USB Interrupt Status register (Register 17-7) con-

tains the flag bits for each of the USB status interrupt

sources. Each of these sources has a corresponding

interrupt enable bit in the UIE register. All of the USB

status flags are ORed together to generate the USBIF

interrupt flag for the microcontroller’s interrupt funnel.

Once an interrupt bit has been set by the SIE, it must

be cleared by software by writing a ‘0’. The flag bits

can also be set in software which can aid in firmware

debugging.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0

— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOFIF: START-OF-FRAME Token Interrupt bit

1 = A START-OF-FRAME token received by the SIE

0 = No START-OF-FRAME token received by the SIE

bit 5 STALLIF: A STALL Handshake Interrupt bit

1 = A STALL handshake was sent by the SIE

0 = A STALL handshake has not been sent

bit 4 IDLEIF: Idle Detect Interrupt bit(1)

1 = Idle condition detected (constant Idle state of 3 ms or more)

0 = No Idle condition detected

bit 3 TRNIF: Transaction Complete Interrupt bit(2)

1 = Processing of pending transaction is complete; read USTAT register for endpoint information

0 = Processing of pending transaction is not complete or no transaction is pending

bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)

1 = Activity on the D+/D- lines was detected

0 = No activity detected on the D+/D- lines

bit 1 UERRIF: USB Error Condition Interrupt bit(4)

1 = An unmasked error condition has occurred

0 = No unmasked error condition has occurred.

bit 0 URSTIF: USB Reset Interrupt bit

1 = Valid USB Reset occurred; 00h is loaded into UADDR register

0 = No USB Rese t has occurred

Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.

2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).

3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.

4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and

cannot be set or cleared by the user.

PIC18F2455/2550/4455/4550

17.5.1.1 Bus Activity Detect Interrupt Bit

(ACTVIF)

The ACTVIF bit cannot be cleared immediately after

the USB module wakes up from Suspend or while the

USB module is suspended. A few clock cycles are

required to synchronize the internal hardware state

machine before the ACTVIF bit can be cleared by

firmware. Clearing the ACTVIF bit before the internal

hardware is synchronized may not have an effect on

the value of ACTVIF. Additionally, if the USB module

uses the clo ck from the 96 M Hz PLL source, the n after

clearing the SUSPND bit, t he USB module may not be

immediately operational while waiting for the 96 MHz

PLL to lock. The application code should clear the

ACTVIF flag as shown in Example 17-1.

EXAMPLE 17-1: CLEARING ACTVIF BIT (UIR<2>)

Assembly:

BCF UCON, SUSPND

LOOP:

BTFSS UIR, ACTVIF

BRA DONE

BCF UIR, ACTVIF

BRA LOOP

DONE:

UCONbits.SUSPND = 0;

while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }

PIC18F2455/2550/4455/4550

17.5.2 USB INTERRUPT ENABLE

The USB Interrupt Enable register (Register 17-8)

contains the enable bits for the USB status interrupt

sources. Setting any of these bits will enable the

respective interrupt source in the UIR register.

The values in this register only affect the propagation

of an interrupt condition to the microcontroller’s inter-

rupt logic. The flag bits are still set by their interrupt

conditions, allowing them to be polled and serviced

without actually generating an interrupt.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOFIE: START-OF-FRAME Token Interrupt Enable bit

1 = START-OF-FRAME token interrupt enabled

0 = START-OF-FRAME token interrupt disabled

bit 5 STALLIE: STALL Handshake Interrupt Enable bit

1 = STALL interrupt enabled

0 = STALL interrupt disabled

bit 4 IDLEIE: Idle Detect Interrupt Enable bit

1 = Idle detect interrupt enabled

0 = Idle detect interrupt disabled

bit 3 TRNIE: Transaction Complete Interrupt Enable bit

1 = Transaction interrupt enabled

0 = Transaction interrupt disabled

bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit

1 = Bus activity detect interrupt enabled

0 = Bus activity detect interrupt disabled

bit 1 UERRIE: USB Error Interrupt Enable bit

1 = USB error interrupt enabled

0 = USB error interrupt disabled

bit 0 URSTIE: USB Reset Interrupt Enable bit

1 = USB Reset interrupt enabled

0 = USB Reset interrupt disabled

PIC18F2455/2550/4455/4550

17.5.3 USB ERROR INTERRUPT STATUS

The USB Error I nterrupt Status regi ster (Regi ster 17-9)

contains the flag bits for each of the error sources

within the USB peripheral. Each of these sources is

controlled by a corresponding interrupt enable bit in

the UEIE register. All of the USB error flags are ORed

together to generate the USB Error Interrupt Flag

(UERRIF ) at the top level of the interrup t logic .

Each error bit is set as soon as the error condition is

detected. Thus, the interrupt will typically not

correspond with the end of a token being processed.

Once an interrupt bit has been set by the SIE, it must

be cleared by software by writing a ‘0’.

R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

BTSEF —— BTOEF DFN8EF CRC16EF CRC5EF PIDEF

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTSEF: Bit Stuff Error Flag bit

1 = A bit stuff error has been detected

0 = No bit stuff error

bit 6-5 Unimplemented: Read as ‘0’

bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit

1 = Bus turnaro und tim e-out has o ccurred (more than 1 6 bit tim es of Idle from previou s EOP elap sed)

0 = No bus turnaround time-out

bit 3 DFN8EF: Data Field Size Error Flag bit

1 = The data field was not an integral number of bytes

0 = The data field was an integral number of bytes

bit 2 CRC16EF: CRC16 Failure Flag bit

1 = The CRC16 failed

0 = The CRC16 pas se d

bit 1 CRC5EF: CRC5 Host Error Flag bit

1 = The token packet was rejected due to a CRC5 error

0 = The token packet was accepted

bit 0 PIDEF: PID Check Failure Flag bit

1 = PID check failed

0 = PID check passed

PIC18F2455/2550/4455/4550

17.5.4 USB ERROR INTERRUPT ENABLE

The USB Error Interrupt Enable register

(Register 17-10) contains the enable bits for each of

the USB error interrupt sources. Setting any of these

bits will enable the respective error interrupt source in

the UEIR register to propagate into the UERR bit at

the top level of the interrupt logic.

As with the UIE register, the enable bits only affect the

propagation of an interrupt condition to the micro-

controller ’s interrupt logic. The flag bits are still set by

their interrupt conditions, allowing them to be polled

and serviced without actually generating an interrupt.

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BTSEE —— BTOEE DFN8EE CRC16EE CRC5EE PIDEE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = Bit stuff error interrupt enabled

0 = Bit stuff error interrupt disabled

bit 6-5 Unimplemented: Read as ‘0’

bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1 = Bus turnaround time-out error interrupt enabled

0 = Bus turnaround time-out error interrupt disabled

bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit

1 = Data field size error interrupt enabled

0 = Data field size error interrupt disabled

bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit

1 = CRC16 failure interrupt enabled

0 = CRC16 failure interrupt disabled

bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit

1 = CRC5 host error interrupt enabled

0 = CRC5 host error interrupt disabled

bit 0 PIDEE: PID Check Failure Interrupt Enable bit

1 = PID check failure interrupt enabled

0 = PID check failure interrupt disabled

PIC18F2455/2550/4455/4550

17.6 USB Power Modes

Many USB applicat ions wi ll likely have sev eral dif ferent

sets of power requirements and configuration. The

most common power modes encountered are Bus

Power Only, Self-Power Only and Dual Power with

Self-Power Dominance. The most common cases are

presented he re.

17.6.1 BUS POWER ONLY

In Bus Power Only mode, all power for the application

is drawn from the USB (Figure 17-10). This is

effectively the simplest power method for the device.

FIGURE 17-10: BUS POWER ONLY

17.6.2 SELF-POWER ONLY

In Self-Power Only mode, the USB ap plication provides

its own power, with very little power being pulled from

the USB. Fi gure 17-11 shows an exa mple. Note that a n

attach indication is added to indicate when the USB

has been connected.

FIGURE 17-11: SELF-POWER ONLY

17.6.3 DUAL POWER WITH SELF-POWER

DOMINANCE

Some applications may require a dual power option.

This allows the application to use internal power prima-

rily, but switch to powe r from the USB whe n no interna l

power is available. Figure 17-12 shows a simple Dual

Power with Self-Power Dominance example, which

automatically switches between Self-Power Only and

USB Bus Power Only modes.

FIGURE 17-12: DUAL POWER EXAMPLE

17.7 Streaming Parallel Port

The S t reaming Paralle l Port (SPP) is an alternate rou te

option for data besides USB RAM. Using the SPP, an

endpoint can be configured to send data to or receive

data dire ctl y from extern al hardware.

This methodology presents design possibilities where

the microcontroller acts as a data manager, allowing

the SPP to p ass la rge block s of dat a with out the mic ro-

controller actually processing it. An application

example might include a data acquisition system,

where da t a i s st rea med from an e xte rna l FIFO th roug h

USB to the host computer. In this case, endpoint

control i s manage d by the mi crocontrol ler and raw data

movement is processed externally.

The SPP is enabled as a USB endpoint port through

the associated endpoint buffer descriptor . The endpoint

must be enabled as follows:

1. Set BDnADRL:BDnADRH to point to FFFFh.

2. Set the KEN bit (BDnSTAT<5>) to let SIE keep

control of the buffer.

3. Set the INCDIS bit (BDnSTAT<4>) to disable

automat ic add res s inc rem ent .

Refer to Section 18.0 “Streaming Parallel Port” for

more information about the SPP.

VDD

VUSB

VSS

VBUS

~5V

VDD

VUSB

VSS

VSELF

~5V

I/O pin

Attach Sense

100 kΩ

VBUS

~5V 100 kΩ

Note: Users should keep in mind the limits for

devices drawing power from the USB.

According to USB Specification 2.0, this

cannot exceed 100 mA per low-power

dev i ce or 500 mA per high -power device.

Note 1: If an endpoint is configured to use the

SPP, the SPP module must also be

configured to use the USB module.

Otherwise, unexpected operation may

occur.

2: In additi on, if an endpoi nt i s c on figu r ed to

use the SPP, the da ta trans fer type o f that

endpoint must be isochronous only.

VDD

VUSB

I/O pin

VSS

Attac h Se n se

VBUS

VSELF

100 kΩ

~5V

100 kΩ

PIC18F2455/2550/4455/4550
DS39632D-page 184 Preliminary © 2007 Microchip Technology Inc.
17.8 Oscillator
The USB module has specific clock requirements. For
full-spe ed operation,  the clock s ource must be 48 MHz.
Even so, the mic rocontroller core and oth er peripherals
are not  required to run at th at clock spee d or even from
the same clock source. Available clocking options are
described in detail in Section 2.3 “Oscillato r Settings
fo r USB”.
17.9 USB Firmware and Drivers
Microchip provides a number of application specific
resources, such as USB firmware and driver support.
Refer to www .microchip.com for the latest firmware and
driver support. 
TABLE 17-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1) 
Name Bit 7 Bit 6 Bit 5 Bit  4 Bit  3 Bit 2 Bit 1 Bit 0 Det a ils  on 
page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 55
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI —55
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 55
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 55
UFRMH — — — — — FRM10 FRM9 FRM8 55
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 55
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 55
UEIR BTSEF —— BTOEF DFN8EF CRC16EF CRC5EF PIDEF 55
UEIE BTSEE —— BTOEE DFN8EE CRC16EE CRC5EE PIDEE 55
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer 
Descriptor registe rs, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.

PIC18F2455/2550/4455/4550

17.10 Overview of USB

This s ect ion present s s om e o f th e ba si c U SB co nc epts

and useful information necessary to design a USB

device. Although much information is provided in this

section, there is a plethora of information provided

within the USB specifications and class specifications.

Thus, the reader is encouraged to refer to the USB

specifications for more information (www.usb.org). If

you are very familiar with the details of USB, then this

section serves as a basic, high-level refresher of USB.

17.10.1 LAYERED FRAMEWORK

USB device functionality is structured into a layered

framework graphically shown in Figure 17-13. Each

level is associated with a functional level within the

device. The highest layer, other than the device, is the

configuration. A device may have multiple configura-

tions. For example, a particular device may have

multiple power requirements based on Self-Power Only

or Bus Power Only modes.

For each configuration, there may be multiple

interfaces. Each interface could support a particular

mode of that configuration.

Below the interface is the endpoint(s). Data is directly

moved at this level. There can be as many as

16 bidirectional endpoints. Endpoint 0 is always a

control endpoint and by default, when the device is on

the bus, Endpoint 0 must be available to configure the

device.

17.10.2 FRAMES

Information communicated on the bus is grouped into

1 ms time slots, referred to as frames. Each frame can

contain many transactions to various devices and

endpoints. Figure 17-9 shows an example of a

transaction within a frame.

17.10.3 TRANSFERS

There are four transfer types defined in the USB

specification.

•Isochronous: This type provides a tra nsfer

method for large amounts of data (up to

1023 bytes) with timely delivery ensured;

however, the data integrity is not ensured. This is

good for streaming applications where small data

loss is not critical, such as audio.

•Bulk: This type of transf er method all ows for large

amounts of data to be transferred with ensured

data integrity; however, the delivery timeliness is

not ensured.

•Interrupt: This type of transfer provides for

ens ured t imely deliver y for small bl ocks of data,

plus data integrity is ensured.

•Control: This type provides for device setup

control.

While full-speed devices support all transfer types,

low-speed devices are limited to interrupt and control

tran sfers only.

17.10.4 POWER

Power is available from the Universal Serial Bus. The

USB specification defines the bus power requirements.

Devices may either be self-powered or bus powered.

Self-powered devices draw power from an external

source, while bus p owered dev ices use po wer supplied

from the bus.

FIGURE 17-13 : USB LAYERS

Device

Configuration

Interface

Endpoint

Interface

Endpoint Endpoint Endpoint Endpoint

To other Configurations (if any)

To other Interfaces (if any)

PIC18F2455/2550/4455/4550

The USB specification limits the power taken from the

bus. Each device is ensured 100 mA at approximately

5V (one un it load). Addition al power may be reque sted,

up to a maximum of 500 mA. Note that power above

one unit load is a request and the host or hub is not

obligated to provide the extra current. Thus, a device

cap able of cons uming more than one unit lo ad must be

able to maintain a low-power configuration of a one unit

load or less, if necessary.

The USB specification also defines a Suspend mode.

In this situation, current must be limited to 500 μA,

averaged over 1 second. A device must enter a

Suspend state after 3 ms of inactivity (i.e., no SOF

tokens for 3 ms). A device entering Suspend mode

must drop current consumption within 10 ms after

Suspend. Likewise, when signaling a wake-up, the

devic e must sign al a wa ke-u p with in 1 0 ms of dr awi ng

current above the Suspend limit.

17.10.5 ENUMERATION

When the device is initiall y attached to the bus, the host

enters an enumeration process in an attempt to identify

the device. Essentially, the host interrogates the device,

gathering information su ch as power consum ption, dat a

rates and sizes, protocol and other descriptive

information; descriptors contain this information. A

typical enum era tion proces s would be as follows:

1. USB Reset: Reset the device. Thus, the device

is not conf igured and doe s not have an add res s

(address 0).

2. Get Device Descriptor: The host requests a

small port ion of the devic e descri pto r.

3. USB Reset: Reset th e device again.

4. Set Address: The host assigns an address to the

device.

5. Get Device Descriptor: The host retrieves the

device descriptor, gathering info such as

manufacturer, type of device, maximum control

packet size.

6. Get configuration descrip tors .

7. Get any other descriptors.

8. Set a configuration.

The exact enumeration process depends on the host.

17.10.6 DESCRIPTORS

There are eight different standard descriptor types of

which five are most important for this device.

17.10.6.1 Device Descriptor

The device descriptor provides general information,

such as manufacturer, product number, serial number,

the class of the device and the numbe r of configurations.

There is only one device d escriptor.

17.10.6.2 Configuration Descriptor

The configuration descriptor provides information on

the power requirements of the device and how many

different interfaces are supported when in this configu-

ration. The re may be more than o ne conf igur ation fo r a

device (i.e., low -power and h igh-power c onfigur ations).

17.10.6.3 Interface Descriptor

The interface descriptor details the number of end-

points used in this interface, as well as the class of the

interface. There may be more than one interface for a

configuration.

17.10.6.4 Endpoint Descriptor

The endpoint descriptor identifies the transfer type

(Section 17.10.3 “Transfers”) and direction, as well

as som e other sp ecifics fo r the endpo int. Th ere may b e

many endpoints in a device and endpoints may be

shared in different configurations.

17.10.6.5 String Des cri ptor

Many of the previous descriptors reference one or

more string descriptors. String descriptors provide

human readable information about the layer

(Section 17.10.1 “Layered Framework”) they

describe. Often these strings show up in the host to

help the user identify the device. String descriptors are

generally optional to save memory and are encoded in

a unicode form at.

17.10.7 BUS SPEED

Each USB device must indicate its bus presence and

speed to the host. This is accomplished through a

1.5 kΩ resistor which is connected to the bus at the

time of the attachment eve nt.

Depending on the speed of the device, the resistor

either pulls up the D+ or D- line to 3.3V. For a

low-s peed device, the pull-up resistor is connected to

the D- line. For a full-speed device, the pull-up resistor

is connected to the D+ line.

17.10.8 CLASS SPECIFICATIONS AND

DRIVERS

USB specifications include class specifications which

operating system vendors optionally support.

Examples of classes include Audio, Mass Storage,

Communications and Human Interface (HID). In most

cases , a driver is re quired at the h ost side to ‘ talk’ to th e

USB devi ce. In custo m appl icatio ns, a dr iver may need

to be developed. Fortunately, drivers are available for

most common host systems for the most common

class es of de vi ces . Thu s, the se drive r s ca n be reu se d.

PIC18F2455/2550/4455/4550

18.0 STREAMING PARALLEL PORT

PIC18F4455/4550 USB devices provide a Streaming

Parallel Port as a hi gh-s pe ed i nte rfac e for movin g da t a

to and from an external system. This parallel port

operates as a master port, complete with chip select

and clock outputs to control the movement of data to

slave de vices. Dat a can be channel led either directl y to

the USB SIE or to the micropr ocessor core. Figure 18-1

shows a block view of the SPP data path.

FIGURE 18-1: SPP DATA PATH

In addition, the SPP can provide time multiplexed

address ing information a long with th e data by u sing the

second strobe ou tput. Thu s, the USB end point nu mber

can be written in conjunction with the data for that

endpoint.

18.1 SPP Configuration

The opera tion of th e SPP is co ntrolled by t wo registers :

SPPCON and SPPCFG. The SPPCON register

(Register 18-1) controls the overall operation of the

paral lel port and determi nes if it operat es under USB or

microcontroller control. The SPPCFG register

(Register 18-2) controls timing configuration and pin

outputs.

18.1.1 ENABLING THE SPP

To enable the SPP, set the SPPEN bit (SPPCON<0>).

In addition, the TRIS bits for the corresponding SPP

pins must be properly configured. At a minimum:

• Bits TRISD<7:0> must be set (= 1)

• Bits TRIS E<2:1> must be cleared (= 0)

If CK1SPP is to be used:

• Bit TRISE<0> must be cleared (= 0)

If CSPP is to be used:

• Bit TRISB<4> must be cleared (= 0)

Note: The Streaming Parallel Port is only

available on 40/44-pin devices.

SPP

Logic

CK2SPP

OESPP

CSSPP

SPP<7:0>

CK1SPP

USB

CPU

PIC18F4455/4550

SIE

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — SPPOWN SPPEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1 SPPOWN: SPP Ownership bit

1 = USB peripheral controls the SPP

0 = Microcontroller directly controls the SPP

bit 0 SPPEN: SPP Enable bit

1 = SPP is enabled

0 = SPP is disabled

PIC18F2455/2550/4455/4550

18.1.2 CLOCKING DATA

The SPP has four control outputs:

• Two separate clock outputs (CK1SPP and

CK2SPP)

• Output enable (OESPP)

• Chip select (CSSPP)

Together, they allow for sev eral di ffe rent configurat ion s

for controlling the flow of data to slave devices. When

all contro l output s are used, the three ma in options are:

• CLK1 clocks endpoint address information while

CLK2 clocks data

• CLK1 clocks write operations while CLK2 clocks

reads

• CLK1 cl ocks Odd a ddress dat a while CLK2 c locks

Even address data

Additional control options are derived by disabling the

CK1SPP and CSSPP outputs. These are enabled or

disabled with the CLK1E N and CSEN bits, respectively ,

located in Register 18-2.

18.1.3 WAIT STATES

The SPP is designed with the capability of adding wait

state s to read and wr ite ope rations . This allo ws acc ess

to parallel devices that require extra time for access.

Wait state clocking is based on the data source clock.

If the SPP is co nfi gure d to oper ate a s a USB endp oin t ,

then w ait st ates are ba sed on the U SB clo ck. Like wis e,

if the SPP is configured to operate from the micro-

controll er, then wait states are based on the instruc tion

rate (FOSC/4).

The WS3:WS0 bits set the wait states used by the SPP,

with a range of no wait states to 30 wait states, in multi-

ples of two. The wait states are added symmetrically to

all transactions, with one-hal f added following each of the

two clock cycles normally required for the transaction.

Figure 18-3 and Figure 18-4 show signalling examples

with 4 wait states added to each transaction.

18.1.4 SPP PULL-UPS

The SPP data lines (SPP<7:0>) are equipped with

internal pull-ups for applic ations that m ay leave the port

in a high-impedance condition. The pull-ups are

enabled using the control bit, RDPU (PORTE<7>).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits

1x = CLK1 toggles on read or write of an Odd endpoint address;

CLK2 toggles on read or write of an Even endpoint address

01 = CLK1 toggles on write; CLK2 toggles on read

00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write

bit 5 CSEN: SPP Chip Select Pin Enable bit

1 = RB4 pin is controlled by the SPP module and functions as SPP CS output

0 = RB4 functions as a digital I/O port

bit 4 CLK1EN: SPP CLK1 Pin Enable bit

1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output

0 = RE0 functions as a digital I/O port

bit 3-0 WS3:WS0: SPP Wait States bits

1111 = 30 additional wait states

1110 = 28 additional wait states

• •

0001 = 2 additional wait states

0000 = 0 additional wait states

PIC18F2455/2550/4455/4550

FIGURE 18-2: TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND

READ DATA (NO WAIT STATES)

FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)

FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)

FOSC/4

OESPP

CK1SPP

CK2SPP

CSSPP

SPP<7:0>

MOVWF SPPEPS MOVWF SPPDATA

Write Address Write Data MOVF SPPDATA, W

Read Data

ADDR DATA DATA

USB Clock

OESPP

CK1SPP

CK2SPP

CSSPP

SPP<7:0>

2 Wait States 2 Wait States 2 Wait States 2 Wait States

Write DataWrite Address

USB Clock

OESPP

CK1SPP

CK2SPP

CSSPP

SPP<7:0> Write Address Read Data

2 Wait States 2 Wait States 2 Wait States 2 Wait States

PIC18F2455/2550/4455/4550

18.2 Setup for USB Control

When the SPP is configured for USB operation, data

can be c loc ke d d ire ctl y to a nd fro m the USB p erip heral

without intervention of the microcontroller; thus, no

process time is required. Data is clocked into or out

from the SPP with endpoint (address) information first,

followed by one or more bytes of data, as shown in

Figure 18-5. This is ideal for applications that require

isochronous, large vo lume data movement.

The following steps are required to set up the SPP for

USB control:

1. Configure the SPP as desired, including wait

states and clocks .

2. Set the SPPOWN bit for USB ownership.

3. Set the buffer descriptor starting address

(BDnADRL:BDnADRH) to FFFFh.

4. Set the KEN bit (BDnSTAT<5>) so the buffer

descriptor is kept indefinitely by the SIE.

5. Set the INCDIS bit (BDnSTAT<4>) to disable

automatic buffer address increment.

6. Set the SPPEN bit to enable the module.

18.3 Setup for Microcontroller Control

The SPP can also act as a parallel port for the

microcontroller. In this mode, the SPPEPS register

(Register 18-3) provides status and address write

control. Data is written to and read from the SPPDATA

microcontroller, the SPP clock is driven by the

instr ucti on clo ck (FOSC/4).

The following steps are required to set up the SPP for

microcontroller operation:

1. Configure the SPP as desired, including wait

states and clocks .

2. Clear the SPPOWN bit.

3. Set SPPEN to enable the module.

18.3.1 SPP INTERRUPTS

When owned by the microcontroller core, control can

generate an interrupt to notify the application when

each read and write operation is completed. The

interrupt flag bit is SPPIF (PIR1<7>) and is enabled by

the SPPIE bit (PIE1<7>). Like all other microcontroller

level interrupts, it can be set to a low or high priority.

This is done with the SPPIP bit (IPR1<7>).

18.3.2 WRITING TO THE SPP

Once configured, writing to the SPP is performed by

writing to the SPPEPS and SPPDATA registers. If the

SPP is configured to clock out endpoint address infor-

mation with the data, writing to the SPPEPS register

initiate s the a ddress write cycl e. Oth erwise, t he wri te is

started by writing the data to the SPPDATA register.

The SPPBUSY bit indicates the status of the address

and the data write cycles.

The following is an example write sequence:

1. Write the 4-bit address to the SPPEPS register.

The SPP automatically starts writing the

address. If address write is not used, then skip

to step 3.

2. Monitor the SPPBUSY bit to dete rmine when the

address has been sent. The duration depends

on the wait states.

3. Write the data to the SPPDATA register. The

SPP automaticall y st a rt s writing the data.

4. Monitor the SPPBUSY bit to dete rmine when the

data has been sent. The duration depends on

the wait states.

5. Go back to steps 1 or 3 to write a new address

or data.

FIGURE 18-5: TRANSFER OF DATA BETWEEN USB SIE AND SPP

Note: If a USB endpoint is configured to use the

SPP, the data transfer type of that

endpoint must be isochronous only.

Note: The SPPBUSY bit should be polled to

make certain that successive writes to the

SPPEPS or SPPDATA registers do not

overrun the wait time due to the wait state

setting.

Byte 0 B yt e 1 Byte 2 Byte 3 Byte n

Endpoint

Address

Write USB endpoint number to SPP

Write ou tbound USB data to SPP or

read inbound USB data from SP P

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18.3.3 READING FROM THE SPP

Reading from the SPP involves reading the SPPDATA

read op eration. W hen th e read i s fin is hed , i nd ica ted b y

the SPPBUSY b it, the SPPDAT A wi ll be loaded wit h the

current data.

The following is an example read sequence:

1. Write the 4-bit address to the SPPEPS register.

The SPP automatically starts writing the

address . If addres s write is not u sed then skip to

step 3.

2. Monitor the SPPBUSY bit to det ermine when the

address has been sent. The duration depends

on the wait states.

3. Read the data from the SPPDATA register; the

data from the previous read operation is

returned. The SPP automatically starts the read

cycle for the next read.

4. Monitor the SPPBUSY bit to dete rmine when the

data has been read. The duration depends on

the wait states.

5. Go back to step 3 to read the current byte from

the SPP and start the next read cycle.

R-0 R-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB)

1 = The last transaction was a read from the SPP

0 = The last transaction was not a read from the SPP

bit 6 WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB)

1 = The last transaction was a write to the SPP

0 = The last transaction was not a write to the SPP

bit 5 Unimplemented: Read as ‘0’

bit 4 SPPBUSY: SPP Handshaking Override bit

1 = The SPP is busy

0 = The SPP is ready to accept another read or write request

bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits

1111 = Endpoint Address 15

• •

0001

0000 = Endpoint Address 0

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TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

SPPCON(3) — — — — — — SPPOWN SPPEN 55

SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55

SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 55

SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 55

PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54

PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54

IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54

PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 54

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.

Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e., 40/44-pin devices).

3: These registers and/or bits are unimplemented on 28-pin devices.

PIC18F2455/2550/4455/4550

19.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

19.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

periphera l or m icroc ontroll er devic es. Th ese p eriphera l

devices may be serial EEPROMs, shift registers,

display d rivers, A/D converte rs, etc. The MSSP modul e

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C™)

- Full Master mode

- Slave mode (with general address call)

The I2C interface supports the following modes in

hardware:

•Master mode

• Multi-Master mode

• Slave mode

19.2 Control Registers

The MSSP module has three associated control regis-

ters. These include a status register (SSPSTAT) and

two control registers (SSPCON1 and SSPCON2). The

use of th ese registers and their ind ividual Configur ation

bits differ s ignificantly depending o n whether the M SSP

module is operated in SPI or I2C mode.

Additional details are provided under the individual

sections.

19.3 SPI Mode

The S PI mode allo ws 8 bits of dat a to be sy nchronousl y

transmitted and received simultaneously. All four

modes of the SPI are supported. To accomplish

communication, typically three pins are used:

• Serial Data Out (SDO) – RC7/RX/DT/SDO

• Serial Data In (SDI) –

RB0/AN12/INT0/FLT0/SDI/SDA

• Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT

Figure 19-1 shows the block diagram of the MSSP

module when operating in SPI mode.

FIGURE 19-1: MSSP BLOCK DIAGRAM

(SPI MODE)

( )

Read Write

Internal

Data Bus

SSPSR reg

SSPM3:SSPM0

bit0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

TRIS bit

SMP:CKE

SDO

SSPBUF reg

SDI

SCK

Note: Only those pin functions relevant to SPI

operation are shown here.

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19.3.1 REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1

the SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buff ered. A write to SSPBUF will write to bo th SSPBUF

and SSPSR.

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE(1) D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6 CKE: SPI Clock Select bit(1)

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

bit 5 D/A: Data/Addr ess bit

Used in I2C mode only.

bit 4 P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3 S: Start bit

Used in I2C mode only.

bit 2 R/W: Read /W ri te Information bit

Used in I2C mode only.

bit 1 UA: Update Address bit

Used in I2C mode only.

bit 0 BF: Buffer Full Status bit (Receive mode only)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV(1) SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collisio n Det ect bit (Transmit mode only)

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit(1)

SPI Slave mode:

1 = A new byte is received while the SSPBUF register is still holding the prev ious dat a. In case of over-

flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the

SSPBUF, even if only transmitting dat a, to avoid setting overflow (must be cleared in software).

0 = No overflow

bit 5 SSPEN: Master Synchronous Serial Port Enable bit

1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins(2)

bit 4 CKP: Clock Pola rity Selec t bit

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits

0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin (3)

0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled(3)

0011 = SPI Master mode, clock = TMR2 output/2(3)

0010 = SPI Master mode, clock = FOSC/64(3)

0001 = SPI Master mode, clock = FOSC/16(3)

0000 = SPI Master mode, clock = FOSC/4(3)

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

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19.3.2 OPERATION

When initializing the SPI, several options need to be

specif ied. This is done by progra mming the ap propriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP module consists of a transmit/receive shift

SSPSR shifts the data in and out of the device, MSb

first. The SSPBUF holds the data that was written to the

SSPSR until the rec eived dat a is read y. Once the eight

bits of data have been received, that byte is moved to

the SSPBUF register. Then, the Buffer Full detect bit,

BF (SSPSTA T <0>) and the i nterrupt flag bit , SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading t he data that was just re ceived. Any write to the

SSPBUF register during transmission /reception of dat a

will be ignored a nd the W rite Colli sion detec t bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determin ed if the foll ow-

ing write(s) to the SSPBUF register completed

successfully.

When the application software is expecting to receive

valid da ta, the SSPBUF shoul d be read before th e next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF (SSPSTAT<0>), indicates when

SSPBUF has been loaded with the received data

(transmiss ion is complete ). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmit ter . Generall y, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure

that a write collision does not occur. Example 19-1

shows the loading of the SSPBUF (SSPSR) for data

transmission.

The SSPSR is n ot directly reada ble or wri table and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP Status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

BRA LOOP ;No

MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

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19.3.3 ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reiniti alize the SSPCON

registers and then set the SSPEN bit. This configures

the SDI, SDO, SCK and SS pins as serial port pins. For

the pins to behav e as the serial port func tion, some must

have their data direction bits (in the TRIS register)

appropriately programmed as follow s:

• SDI is a uto matically c on trol led by the SPI module

• SDO must have TRISC<7> bit cleared

• SCK (Master mode) must have TRISB<1> bit

cleared

• SCK (Slave mode) must have TRISB<1> bit set

•SS

must have TRISA<5> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

19.3.4 TYPICAL CONNEC TI ON

Figure 19-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their

programmed clock edge and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to the same Clock Polarity (CKP), then both

controllers would send and receive data at the same

time. Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data – Slave sends dummy d ata

• Master sends data – Slave sends data

• Master sends dummy data – Slave sends data

FIGURE 19-2: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

PROC ESSOR 1

SCK

SPI Ma ster SS PM3:SSP M0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SS PM3:SSP M0 = 010xb

Serial Clock

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19.3.5 MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 19-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF registe r is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal p resent on the S DI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately

programming the CKP bit (SSPCON1<4>). This then,

would give waveforms for SPI communication as

shown in Figure 19-3, Figure 19-5 and Figure 19-6,

where t he MSB is tran smitted fi rst. In Ma ster mode , the

SPI clock ra te (bit rate) is user programmable t o be one

of the fo llowing:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 48 MHz) of

2.00 Mbps.

Figure 19-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

dat a is shown.

FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycl e

after Q2↓

bit 0

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19.3.6 SLAVE MODE

In Slave m ode , the dat a is transmi tted and rece iv ed a s

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device can be con-

figured to wake-up from Sleep.

19.3.7 SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with the SS pin control

enabled (SSPCON1<3:0> = 04h). When the SS pin is

low, transmission and reception are enabled and the

SDO pin is driven. When the SS pin goes high, the

SDO pin is no longer driven, even if in the middle of a

transmitted byte and becomes a floating output. Exter-

nal pull-up/pull-down resistors may be desirable

depending on the application.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an in put. This d isables transmissi ons from th e SDO.

The SDI can always be left as an input (SDI function)

since it cann ot cre ate a bus con flict.

FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SPI module is in Slave mode

with SS pin control enabled

(SSPCON1<3:0> = 0100), the SPI module

will reset if the SS pin is set to VDD.

2: If the SPI is us ed in Slave mo de with CK E

set, then the SS pin control must be

enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bi t 6 b i t 7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit 0

bit 7 bit 0

Next Q4 Cycle

after Q2↓

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FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7

SDO bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bi t 0

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPS R to

SSPBUF

Flag

Optional

Next Q4 Cycl e

after Q2↓

bit 0

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7 bit 0

SDO bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

Not Optional

Next Q4 Cycle

after Q2↓

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 201
PIC18F2455/2550/4455/4550
19.3.8 OPERATION IN POWER-MANAGED 
MODES
In SPI  Master mo de, modu le clo cks may be op erati ng
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In most id le modes, a c lock is  provid ed to the pe ripher-
als. That clock should be from the primary clock
source, the secondary clock (Timer1 oscillator) or the
INTOSC source. See Section 2.4 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP inte rrupts are en abled, they can  wake the con-
troller from  Sle ep m od e or on e of th e Id le m ode s whe n
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all eight bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
19.3.9 EFFECTS OF A RESET
A Reset disables  the MSSP module and terminat es the
current transfer.
19.3.10 BUS MODE COMPATIBILITY
Table 19-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits. 
TABLE 19-1: SPI BUS MODES          
There is also an SMP bit which controls when the data
is sampled.
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION       
Standard SPI Mode 
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54
TRISC TRISC7 TRISC6 ——— TRISC2 TRISC1 TRISC0 54
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 52
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 52
SSPSTAT SMP CKE D/A P S R/W UA BF 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, 
all of the associated bits read ‘0’.

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19.4 I2C Mode

The MSSP module in I2C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCL) – RB1/AN10/INT1/SCK/SCL

• Serial data (SDA) –

RB0/AN12/INT0/FLT0/SDI/SDA

The user mu st configur e these pi ns as inputs by settin g

the associated TRIS bits.

FIGURE 19-7: MSSP BLOCK DIAGRAM

(I2C™ MODE)

19.4.1 REGISTERS

The MSSP module has six registers for I2C operation.

These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

• MSSP Address Register (SSPADD)

SSPCON1, SSPCON2 and SSPSTAT are the control

and status registers in I2C mode operation. The

SSPCON1 and SSPCON2 registers are readable and

writable. The lower six bits of the SSPST A T are read-only .

The u p per two bi t s o f the S SPSTAT a re r ea d /wr it e.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

SSPADD registe r holds the sl ave devic e address whe n

the MSSP is configured in I2C Sl ave mo de. Whe n the

MSSP is configured in Master mode, the lower seven

bits of SSPADD act as the Ba ud Rate G enerator reloa d

value.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buff ered. A write to SSPBUF will write to bo th SSPBUF

and SSPSR.

Read Write

SSPSR reg

Mat ch Detect

SSPADD r eg

SSPBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

Shift

Clock

MSb LSb

Note: Only port I/O names ar e used in this diagram for

the sake of brevity . Ref er to the text for a full list of

multiplexed functions.

SCL

SDA

Start and

Stop bit Detect

Address Mask

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P(1) S(1) R/W(2,3) UA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6 CKE: SMBus Select bit

In Master or Slave mode:

1 = Enable SMBus specific inputs

0 = Disable SMBus specific inputs

bit 5 D/A: Data/Addr ess bit

In Master mode:

Reserved.

In Slave mode:

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit(1)

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

bit 3 S: Start bit(1)

1 = Indicates that a Start bit has been detected last

0 = Start bit was not detected last

bit 2 R/W: Read /W ri te Information bit(2,3)

In Slave mode:

1 = Read

0 = Write

In Master mode:

1 = Transmit is in progress

0 = Transmit is not in progress

bit 1 UA: Update Address bit (10-Bit Slave mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

In Transmit mode:

1 = SSPBUF is full

0 = SSPBUF is empty

In Receive mode:

1 = SSPBUF is full (does not include the ACK and Stop bits)

0 = SSPBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

In Master Transmit mode:

1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a

transmission to be started (must be cleared in software)

0 = No collision

In Slave Transmit mode:

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6 SSPOV: Receive Overflow Indicator bit

In Receive mode:

1 = A byte is received while t he SSPBUF register is sti ll ho lding the prev ious by te (mu st be c leared i n

software)

0 = No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mo de.

bit 5 SSPEN: Master Synchronous Serial Port Enable bit

1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins(1)

0 = Disables serial port and configures these pins as I/O port pins(1)

bit 4 CKP: SCK Release Control bit

In Slave mode:

1 = Release clock

0 = Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode .

bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled(2)

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled(2)

1011 = I2C Firmware Controlled Master mode (slave Idle)(2)

1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))(2)

0111 = I2C Slave mode, 10-bit address(2)

0110 = I2C Slave mode, 7-bit address(2)

Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output.

2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Ena ble bit (Slave mode only)

Unused in Mas te r mo de.

bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1 = Acknowledge was not received from slave

0 = Acknowledg e was received from slave

bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)

1 = Not Acknowledge

0 = Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit(2)

1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatica lly

cleared by hardware.

0 = Acknowledge sequence Idle

bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2)

1 = Enables Receive mode for I2C

0 = Receive Idle

bit 2 PEN: Stop Condition Enable bit(2)

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1 RSEN: Repeated Start Condition Enable bit(2)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repea ted Start condition Idle

bit 0 SEN: Start Condition Enable/Stretch Enable bit(2)

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition Idle

Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

2: If the I2C module is active, t hese bits may no t be s et (no s pooling) and th e SSPBUF ma y not be written (o r

writes to the SSPBUF are disabled).

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Ena ble bit (Slave mode only)

1 = Enable interrupt when a general call address (0000h) is received in the SSPSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit

Unused in Slave mod e.

bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits

1 = Masking of corresponding bits of SSPADD enabled

0 = Masking of corresponding bits of SSPADD disabled

bit 1 ADMSK1: Slave Address Mask Select bit

In 7-Bit Address mode:

1 = Masking of SPADD<1> only enabled

0 = Masking of SPADD<1> only disabled

In 10-Bit Address mode:

1 = Masking of SSPADD<1:0> enabled

0 = Masking of SSPADD<1:0> disabled

bit 0 SEN: Stretch Enable bit(1)

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

PIC18F2455/2550/4455/4550

19.4.2 OPERATION

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON1<5>).

The SSPCON1 register allows control of the I2C

operation. Four mode selection bits (SSPCON1<3:0>)

allow one of the following I2C modes to be selected:

•I

2C Master mode, cl ock

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

•I

2C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

•I

2C Firmware Controlled Master mode, slave is

Idle

Selection of any I2C mode with the SSPEN bit set

forces the SCL and SDA pins to be open-drain,

provided these pins are programmed as inputs by

setting the appropriate TRISC or TRISD bit s. To ensure

proper operation of the module, pull-up resistors must

be provided externally to the SCL and SDA pins.

19.4.3 SLAVE MODE

In Slave mode, the SCL and SDA pins must be

configured as inputs (TRISC<4:3> set). The MSSP

module will overrid e the in put sta te with th e output da ta

when required (slave-transmitter).

The I2C Slav e m od e h ardw a re wi ll always ge nerate an

interrupt on an address match. Address masking will

allow the hardware to generate an interrupt for more

than one address (up to 31 in 7-bit addressing and up

to 63 in 10-bit addressing). Through the mode select

bits, the user can also choose to interrupt on Start and

Stop bits.

When an add ress is match ed, or the d at a trans fer after

an address match is received, the hardware auto-

matically will generate the Acknowledge (ACK) pulse

and load the SSPBUF register with the received value

currently in the SSPSR register.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

• The overflow bit, SSPOV (SSPCON1<6>), was

set before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF is set. The BF bit is

cleared by reading the SSPBUF register, while bit

SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low fo r pro per op erati on. The high an d l ow ti me s o f th e

I2C specification, as well as the requirement of the

MSSP module , are shown in tim ing p arame ter 100 a nd

parameter 101.

19.4.3.1 Addressing

Once the MSSP module has been enabled, it waits for

a S t art conditio n to occur. Following the S t art co ndition,

the 8 bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

1. The SSPSR register value is loaded into the

SSPBUF register.

2. The Buffer Full bit, BF, is set.

3. An ACK pulse is generated.

4. The MSSP Interrupt Flag bit, SSPIF, is set (and

interrupt is generated, if enabled) on the falling

edge of the ninth SCL pulse.

In 10-Bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPST A T<2>) must specify a write so

the slave device will receive the second address byte.

For a 10-bit address, the first byte would equal ‘11110

A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the

address. The sequence of events for 10-bit address is as

follows, with step s 7 through 9 for the slav e-transmitter:

1. Receive first (high) byte of address (bits SSPIF,

BF and UA (SSPSTAT<1>) are set on address

match).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

5. Update t he SSPADD register wi th the firs t (hig h)

byte of a ddre ss . If m at ch rel ea ses SCL line, thi s

will clea r bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

7. Receive Repeated Start condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

PIC18F2455/2550/4455/4550

19.4.3.2 Address Masking

Masking an address bit causes that bit to become a

“don’t care”. When one address bit is masked, two

addresses will be Acknowledged and cause an

interrupt. It is possible to mask more than one address

bit at a time, wh ich mak es it pos sible to Ac knowled ge

up to 31 addresses in 7-bit mode and up to 63

addresses in 10-bit mode (see Example 19-2).

The I2C Sl ave beh aves th e same w ay wheth er addres s

masking is used or not. However, when address

masking is used, the I2C slave can Acknowledge

multiple addresses and cause interrupts. When this

occurs, it is necessary to determine which address

caused the interrupt by checking SSPBUF.

In 7-Bit Address mode, address mask bits

ADMSK<5:1> (SSPCON2<5:1>) mask the corre-

spondi ng add ress bit s i n the SSPADD register. For any

ADMSK bits that are set (ADMSK<n> = 1), the

corresponding address bit is ignored

(SSPADD<n> = x). For the mod ule to issue an address

Acknowledge, it is sufficient to match only on

addresses that do not have an active address mask.

In 10-Bit Address mode, bits ADMSK<5:2> mask the

corr es pon di n g ad d res s bi ts in th e SS PADD reg is ter. In

addition , ADMSK1 sim ultan eously m asks the two LSbs

of the address (SSPADD<1:0>). For any ADMSK bits

that are active (ADMSK<n> = 1), the corresponding

address bit is ignored (SSPADD<n> = x). Also note

that although in 10-Bit Addressing mode, the upper

address bits reuse part of the SSP ADD register bits, the

address mask bits do not interact with those bits. They

only affect the lower address bits.

EXAMPLE 19-2: ADDRESS MASKING EXAMP LES

Note 1: ADMSK1 ma sks the two Least Sign ificant

bits of the addres s.

2: The two Most Significant bits of the

address are not affected by address

masking.

7-bit addressi ng:

SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)

ADMSK<5:1> = 00111

Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh

10-bit addressing:

SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since

they are not affected by masking)

ADMSK<5:1> = 00111

Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,

AEh, AFh

PIC18F2455/2550/4455/4550

19.4.3.3 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Ack no w led ge (ACK ) pul se is g iv en. An ov erfl ow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. The Interrupt Flag bit, SSPIF, must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

If SEN is enabled (SSPCON2<0> = 1), RB1/AN10/

INT1/SCK/SCL will be h eld low (clock stretch) following

each data transfer. The clock must be released by

setting bit, CKP (SSPCON1<4>). See Section 19.4.4

“Clock Stretching” for more detail.

19.4.3.4 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RB1/AN10/INT1/SCK/

SCL is held low regardles s of SEN (see Section 19.4.4

“Clock Stretching” for more detail). By stretching the

clock , the mast er will be unable to asse rt anothe r cloc k

pulse until the slave is done preparing the transmit

data. The transmit data must be loaded into the

SSPBUF registe r which also load s the SSPSR register .

Then pin RB1/AN10/INT1/SCK/SCL should be enabled

by setting bi t, CKP (SSPCON1<4>). The eight data bits

are shifted out on the falling edge of the SCL input. Thi s

ensures that the SDA signal is valid during the SCL

high time (Figure 19-10).

The ACK pulse from the master-receiver is latched on

the rising edge of the nin th SCL input pu lse. If the SDA

line is high (not ACK), then the data transfer is

comple te. In thi s case , when the ACK i s la tc hed by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the Start bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register .

Again, p in R B1/AN1 0/INT1/SCK/SCL must b e ena ble d

by setting bit CKP (SSPCON1<4>).

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

PIC18F2455/2550/4455/4550

FIGURE 19-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S1234567891 2345 678912345 789 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(PIR1<3>)

CKP (CKP does not reset to ‘0’ whe n SE N = 0)

PIC18F2455/2550/4455/4550

FIGURE 19-9: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011

(RECEPTION, 7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S12345678912345678912345 789 P

A7 A6 A5 X A3 X X D7D6D5D4D3D2D1D0 D7D6D5D4D3 D1D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP (CKP does not reset to ‘0’ when SEN = 0)

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.

PIC18F2455/2550/4455/4550

FIGURE 19-10 : I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9

SSPBUF is w ritten in software

Cleared in software

Data in

sampled

ACK

Transmitting Data

R/W =

ACK

Receiving Address

A7 D7

D6 D5 D4 D3 D2 D1 D0

2 3 4 5 6 7 8 9

SSP BUF is wr it te n in s o ft w a r e

Cleared in software From SSPIF ISR

Transmitting Data

CKP

ACK

CK P is s e t in so f tw a re CKP is set in software

From SSPIF ISR

SCL held low

while CPU

responds to SSPIF

PIC18F2455/2550/4455/4550

FIGURE 19-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6 A5A4A3 A2A1 A0 D7 D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

(PIR1<3>)

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPADD is updated

with low byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPADD has

taken place

PIC18F2455/2550/4455/4550

FIGURE 19-12 : I2C™ SLAV E MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001

(RECEPTION, 10-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9 A8 A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPADD is updated

with low byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPADD has

taken place

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledg ed and cause an interru pt.

3: Note that the Most Significant bits of the address are not affected by the bit masking.

PIC18F2455/2550/4455/4550

FIGURE 19-13 : I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

11110A9A8 A7A6 A5 A4 A3 A2 A1 A0 11110A8

R/W = 1

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Bus master

terminates

transfer

(PIR1<3>)

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address.

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

Receive First Byte of Address

12345 789

D7 D6 D5 D4 D3 D1

ACK

Tran smitting Data Byte

Dummy read of SSPBUF

to clear BF flag

Cleared in software

Write of SSPBUF

initiates transmit

Cleared in software

Completion of

clears BF flag

CKP (SSPCON1<4>)

CKP is set in software

CKP is automatically cleared in hardware, holding SCL low

Clock is held low until

update of SSPADD has

taken place

data transmission

Clock is held low until

CKP is set to ‘1’

third address sequence

BF flag is clear

at the end of the

PIC18F2455/2550/4455/4550

19.4.4 CLOCK STRETCHING

Both 7-Bit and 10-Bit Slave modes implement

automatic cloc k s tre tch ing during a tran sm it sequenc e.

The SEN bit (SSPCON2<0>) al lows clock stretch ing to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

19.4.4.1 Clock Stretching for 7-Bit Slave

Receive Mode (SEN = 1)

In 7-Bit Slave R ecei ve m od e, on the fall ing edg e of the

ninth clock at the end of the ACK sequence if the BF

bit is set, the CKP bit in the SSPCON1 register is

automatically cleared, forcing the SCL output to be

held low. The CKP bit being cleared to ‘0’ will assert

the SCL lin e low. The CKP bit must be set in the user’s

ISR befo re recep tion i s allow ed to co ntinue . By hol ding

the SCL line low, the user has time to service the ISR

and read the contents of the SSPBUF before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring (see

Figure 19-15).

19.4.4.2 Clock Stretching for 10-Bit Slave

Receive Mode (SEN = 1)

In 10-Bit Slave Receive mode during the address

sequence, clock stretching automatically takes place

but CKP is not c lea red . Duri ng t his time, if th e UA b it i s

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

19.4.4.3 Clock Stretching for 7-Bit Slave

Transmit Mode

7-Bit Slave Transmit mode implements clock stretch-

ing by clearing the CKP bit after the falling edge of the

ninth clock if the BF bit is clear. This occurs regardless

of the state of the SEN bit.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 19-10).

19.4.4.4 Clock Stretching for 10-Bit Slave

Transmit Mode

In 10-Bit Slave Transmit mode, clock stretching is

controlled during the first two address sequences by

the state of the UA bit, just as it is in 10-Bit Slave

Receive mode. The first two addresses are followed

by a third address sequence which contains the high-

order bits of the 10-bit address and the R/W bit set to

‘1’. After the third address sequence is performed, the

UA bit is not set, the module is now configured in

Transmit mode and clock stretching is controlled by

the BF flag as in 7-Bit Slave Transmit mode (see

Figure 19-13).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

Note: If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ni nth c lock oc curs and i f

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a

data sequence, not an address sequence.

Note 1: If the u ser lo ads the conten t s of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will n ot occur .

2: The CKP bit can be set in software

regardless of the state of the BF bit.

PIC18F2455/2550/4455/4550

19.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCL output low until the SCL output is already

sampled low. Therefore, the CKP bit will not assert the

SCL line until an external I2C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I2C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 19-14).

FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX – 1DX

Write

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON1

CKP

Master device

deasser ts clock

Master device

asserts clock

PIC18F2455/2550/4455/4550

FIGURE 19-15 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S123456789 123456789 12345 789 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(PIR1<3>)

CKP

written

to ‘1’ in

If BF is cleared

prior to the falling

edge of the ninth clock,

CKP will not be reset

to ‘0’ and no clock

stretching will occur

software

Clock is held low until

CKP is set to ‘1’

Clock is not held low

because Buffer Full (BF) bit is

clear prior to falling edge

of ninth clock Clock is not held low

because ACK = 1

BF is set after falling

edge of the ninth clock,

CKP is reset to ‘0’ and

clock stretching occurs

PIC18F2455/2550/4455/4550

FIGURE 19-16 : I2C™ SLAV E MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address after falling edge

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address after falling edge

SSPBUF is writ ten with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

CKP written to ‘1’

Note: An update of th e SS PADD register before

the falling edge of the ninth clock will have

no effect on UA and UA will remain set.

Note: An update of the SSPADD

edge of the ninth clock will

have no effect on UA and

UA will remain set. in software

Clock is held low until

update of SSPADD has

taken place

of ninth clock

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

Dummy read of SSPBUF

to clear BF flag

Clock is held low until

CKP is set to ‘1’Clock is not held low

because ACK = 1

PIC18F2455/2550/4455/4550

19.4.5 GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Ena ble (GCEN) bit is enabl ed (SSPCON2<7>

set). Following a Start bit detect, 8 bits are shifted into

the SSPSR and the address is compared against the

SSPADD. It is also compared to the general call

address and fixed in hardware.

If the general call address matches, the SSPSR is

transferre d to the S SPBUF, the BF flag bit i s set (eigh th

bit) and on the falling edg e of the ninth bit (ACK b it), the

SSPIF interrupt flag bit is set.

When the interrupt is serviced, the source for the

interr upt can be checke d by reading t he cont ents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the seco nd half of the address to match an d the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-Bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set and the slave will begin receiving data after the

Acknowledge (Figure 19-17).

FIGURE 19-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

SDA

SCL S

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

Cleared in software

SSPBUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

GCEN (SSPCON2<7>)

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set inter rupt

‘0’

‘1’

PIC18F2455/2550/4455/4550

19.4.6 MASTER MODE

Master mode is enabled by setting and clearing the

appropria te SSPM bit s in SSPCON1 and by set ting the

SSPEN bit. In Master mode, the SCL and SDA lines

are man ipulated by the MSSP ha rdware if the TRIS bit s

are set.

Master mode operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I 2C bus may be taken when the P bit is

set or the bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit conditions.

Once Master mode is enabled, the user has six

options:

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configu re the I2C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and S CL.

The following events will cause the MSSP Interrupt

Flag bit, SSPIF, to be set (and MSSP interrupt, if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeat ed Start

FIGURE 19-18: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)

Note: The MSSP module, when configured in

I2C Mast er mode, does n ot allow que ueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit wi ll be set, indicating that a write

to the SSPBUF did not occur.

Read Write

SSPSR

Start bit, Stop bit,

SSPBUF

Internal

Data Bus

Set/ Rese t S, P, WCOL (SSP STAT, SSPCON1 );

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

End of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

Receive Enable

Clock Cntl

Clock Arbitrate/WCO L Detect

(hold off clock source)

SSPADD<6:0>

Baud

set SS PIF, BCLIF;

reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM3:SSPM0

Start bit De tect

PIC18F2455/2550/4455/4550

19.4.6.1 I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the S t a rt and Stop condition s. A transf er is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer , the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receivi ng device (seven bit s) and the Read/W rite (R/W)

bit. In t his c ase, th e R/W bit wi ll be log ic ‘0’. Ser ial data

is transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and

Stop conditions are output to indicate the beginning

and the end of a serial transfer.

In Master Rec eive mode, t he first byte transm itted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit wil l be

logic ‘1’ Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received eight bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The Baud Rate Generator used for the SPI mode

operation is used to set the SCL clock frequency for

either 100 kHz, 400 kHz or 1 MHz I2C operation. See

Section 19.4.7 “Baud Rate” for more detail.

A typical transmit sequence would go as follows:

1. The user generates a Start condition by setting

the Start Enable bit, SEN (SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

4. Address is shifted out the SDA pin until all eight

bits are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP mo dule g enerate s an interrup t at th e

end of th e ninth c lock cyc le by settin g the SSPIF

bit.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifte d out the SDA pin until all ei ght bit s

are transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module g enerate s an interrup t at th e

end of th e ninth c lock cyc le by settin g the SSPIF

bit.

11. The user generates a Stop condition by setting

the Stop Enable bit, PEN (SSPCON2<2>).

12. Interrupt is genera ted onc e the Stop condition i s

complete.

PIC18F2455/2550/4455/4550

19.4.7 BAUD RATE

In I2C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower seven bits of the

SSPADD register (Figure 19-19). When a write occurs

to SSPBUF, the Baud Rate Generator will automatically

begin c oun tin g. Th e BR G c oun ts down to ‘0’ an d s t ops

until an other re load h as t aken pl ace. Th e BRG c ount i s

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I2C Master mode, the BRG is

reloaded automatically.

Once the given operation is complete (i.e., transmis-

sion of th e last dat a bit is followed by ACK), the int ernal

clock will automatically stop counting and the SCL pin

will rema in in it s last state.

Table 19-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 19-3: I2C™ CLOCK RATE W/BRG

SSPM3:SSPM0

BRG Down Counter

CLKO FOSC/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control Reload

FCY FCY * 2 BRG Value FSCL

(2 Rollovers of BRG)

10 MHz 20 MHz 18h 400 kHz(1)

10 MHz 20 MHz 1Fh 312.5 kHz

10 MHz 20 MHz 63h 100 kH z

4 MHz 8 MHz 09h 400 kHz(1)

4 MHz 8 MHz 0Ch 308 kHz

4 MHz 8 MHz 27h 100 kHz

1 MHz 2 MHz 02h 333 kHz(1)

1 MHz 2 MHz 09h 100 kHz

1 MHz 2 MHz 00h 1 MHz(1)

Note 1: The I2C™ interf ace doe s not c onform to the 40 0 kHz I2C specificat ion (w hich appl ies to rates gre ater tha n

100 kHz) in all details, but may be used with care where higher rates are required by the application.

PIC18F2455/2550/4455/4550

19.4.7.1 Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 19-20).

FIGURE 19-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

SCL

SCL deasserted but slave holds

DX – 1DX

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration) SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

PIC18F2455/2550/4455/4550

19.4.8 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN (SSPCON2<0>). If the SDA and SCL

pins are sampled high, the Baud Rate Generator is

reloaded with the cont ent s of SSPADD<6:0> and s tart s

its count. If SC L and SDA are both sam pl ed hig h whe n

the Baud Rate Generator times out (TBRG), the SDA

pin is driven low. The action of the SDA being driven

low whil e SC L is hig h is the Start con di tion and cau se s

the S bit (SSPSTAT<3>) to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSPADD<6:0> and res um es it s cou nt. Wh en the Bau d

Rate Generator times out (TBRG), the SEN bit

(SSPCON2<0>) will be automatically cleared by

hardware, the Baud Rate Generator is suspended,

leavin g th e SD A l in e h eld lo w and th e Start co ndi tio n i s

complete.

19.4.8.1 WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL bit is set and the contents of

the buffer are unchanged (the write doesn’t occur).

FIGURE 19-21: FIRST START BIT TIMING

Note: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low , or if during the S tart condition, the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag, BCLIF, is

set, the Start condition is aborted and the

I2C module is reset into its Idle state.

Note: Because queueing of events is not

allowed, writing to the lower five bits of

SSPCON2 is disabled until the Start

conditi on is complete.

SDA

SCL

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of St art bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPSTAT<3>)

and sets SSPIF bit

PIC18F2455/2550/4455/4550

19.4.9 I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

(SSPCON2<1>) is programmed high and the I2C logic

module is in the Idle state. When the RSEN bit is set,

the SCL pin is asserted lo w. When the SCL pin is sam-

pled low, the Baud Rate Generator is loaded with the

contents of SSPADD<5:0> and begins counting. The

SDA pin is released (brought high) for one Baud Rate

Generator coun t (TBRG). When th e Baud Rate Gene ra-

tor times out, if SDA is sampled high, the SCL pin will

be deasserted (brought high). When SCL is sampled

high, the Baud Rate Generator is reloaded with the

contents of SSPADD<6:0> and begins counting. SDA

and SCL must be sampled high for one TBRG. This

action is then followed by assertion of the SDA pin

(SDA = 0) for one TBRG while SCL is high. Following

this, the RSEN bit (SSPCON2<1>) will be automatically

cleared and the Baud Rate Generator will not be

reloaded, leaving the SDA pin held low. As soon as a

Start condition is detected on the SDA and SCL pins,

the S bit (SSPSTAT<3>) will be set. The SSPIF bit will

not be set until the Baud Rate Generato r has timed out.

Immediately following the SSPIF bit getting set, the user

may write the SSPBUF with the 7-bit address in 7-bit

mode or the default first address in 10-bit mode. After the

first eight bits are transmitted and an ACK is received,

the user may then transmit an additional eight bits of

address (10-bit mode) or eight bit s of dat a (7-bit mode).

19.4.9.1 WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, the WCOL bit is set and the

contents of the bu f fer ar e unch anged (th e write doesn ’t

occur).

FIGURE 19-22: REPEATED START CONDITION WAV EFO RM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

conditi on occ urs if:

• SDA is sampled low when SCL go es

from low-to-hi gh.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Note: Because queueing of events is not

allowed, writing of the lower five bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

SDA

SCL

Sr = Repeated Start

Write to SSPCON 2

Writ e to SSPBUF occurs here

Falling edge of ninth clock,

end of Xmit

At completion of S tart bit,

hardware clears RSEN bit

1st bit

Set S (SSPSTAT<3>)

TBRG

SDA = 1,

SCL (no change). SCL = 1

occurs here.

TBRG TBRG TBRG

and sets SSPIF

PIC18F2455/2550/4455/4550

19.4.10 I2C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buf fer Ful l flag bi t, BF and allo w the Baud Rate

Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification

parameter 106). SCL is held low for one Baud Rate

Generator rollover count (TBRG). Data should be valid

befor e SCL is rele ased high (see data setup time spec-

ificati on param eter 107). When the SC L pin is released

high, it is held that way for TBRG. The data on the SDA

pin must rem ain st able f or that duratio n and some hol d

time after the next falli ng ed ge of SCL. After the eigh th

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit dur ing th e nint h bit time i f an

address match occurred, or if data was received

properly. The status of ACK is written into the ACKDT

bit on the falling edge of the ninth clock. If the master

receive s an Ack nowled ge, the Acknow ledg e S tatus bi t,

ACKSTA T, is cl eared. If not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 19-23).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDA pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

cloc k, the mast er wil l sam ple the SDA pin to see if t he

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT status bit

(SSPCON2<6>). Followi ng the falling edg e of the ninth

clock transmission of the address, the SSPIF is set, the

BF flag is cleared and the Baud Rate Generator is

turned off until another write to the SSPBUF takes

place, holding SCL low and allowing SDA to float.

19.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all eight bits are shifted out.

19.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write doesn’t occur) after

2TCY after the SSPBUF write. If SSPBUF is rewritten

within 2 TCY, the WCOL bit is set and SSPBUF is

updated. This may result in a corrupted transfer.

The user should verify that the WCOL is clear after

each wri te to SSPBUF to ensure the transfer is correct.

In all cases, WCOL must be cleared in software.

19.4.10.3 ACKSTAT Status Flag

In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK =0) and is set when the slav e does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

19.4.11 I2C M ASTER MODE RECEPTION

Master mode recepti on is enabl ed by progra mmin g the

Receive Enable bit, RCEN (SSPCON2<3>).

The Baud Rate Generator begins counting and on each

rollove r, the state of the SC L pin ch ang es (high -to-l ow /

low-to-high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bi t is set and the Baud Ra te Gener-

ator is s uspen ded from countin g, hold ing SC L low. The

MSSP is now in Idle state awaiting the next command.

When the buffer is read by the CPU, the BF flag bit is

automatically cleared. The user can then send an

Acknowledge bit at the end of reception by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>).

19.4.11.1 BF Status Flag

In receiv e op eration, the B F bit is s et whe n an add r es s

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

19.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPSR and the BF flag bit is

already set from a p revious reception.

19.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), th e WCOL bi t is set an d the conte nts of th e buffer

are unchanged (the write doesn’t occur).

Note: The MSSP module must be in an Idle state

before the RCEN bit is set or the RCEN bit

will be disregarded.

PIC18F2455/2550/4455/4550

FIGURE 19-23 : I2C™ MASTER MODE WAV EFORM (T RANSMISSION, 7 OR 10-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared in software service routine

SSPBUF is written in software

from MSSP interrupt

After Start condition, SEN cleared by hardware

SSPBUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSPIF

SEN = 0

of 10-bit Address

Write SSPCON2<0> SEN = 1,

Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>

ACKSTAT in

SSPCON2 = 1

Cleared in softwar e

SSPBUF written

PEN

R/W

Cleared in software

PIC18F2455/2550/4455/4550

FIGURE 19-24 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 12345678912345678 91234

Bus master

terminates

transfer

ACK Receiving Data from Slave

Receiving Data from Slave D0

D3D4

D6D7

ACK

R/W = 1

Transmit Address to Slave

SSPIF

ACK is not sent

Write to SSPCON2<0> (SEN = 1),

Write to SSPBUF occurs here, ACK from Slave

Master configured as a receiver

by programming SSPCON2<3> (RCEN = 1)PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared in software

start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

(SSPSTAT<0>)

ACK

Cleared in software

Set SSPIF interrupt

at end of receive

Set P bit

(SSPSTAT<4>)

and SSPIF

ACK from master,

Set SS PIF at end

Set SSPIF interrupt

at end of Acknowledge

sequence

Set SSPIF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence,

SDA = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSPCON2<4>

to start Acknowledge sequence

SDA = ACKDT (SSPCON2<5>) = 0

RCEN cleared

automatically

responds to SSPIF

ACKEN

begin Start Condition

Cleared in software

SDA = ACKDT = 0

Cleared in

software

SSPOV is set because

SSPBUF is still full

Last bit is shifted into SSPSR and

contents are unloaded into SSPBUF

PIC18F2455/2550/4455/4550

19.4.12 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the use r wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low . Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into an inactive state

(Figure 19-25).

19.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the bu f fer are un chang ed (the w rite doe sn ’t

occur).

19.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Enable bit, PEN

(SSPCON2<2>). At the end of a receive/transmit, the

SCL line is held low after the falling edge of the ninth

clock. When the PEN bit is set, the master will assert

the SDA line low. When the SDA line is sampled low,

the Baud R ate Gen erat or i s rel oad ed and count s do wn

to ‘0’. When the Baud Rate Generator times out, the

SCL pin will be broug ht high and on e TBRG (Baud R ate

Generator rollover count) later, the SDA pin will be

deasserted. When the SDA pin is sampled high while

SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG

later, the PEN bit is cleared and the SSPIF bit is set

(Figure 19-26).

19.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the bu f fer ar e unch anged (th e write doesn ’t

occur).

FIGURE 19-25: ACKNOWLEDGE SEQUENCE W A VEFORM

FIGURE 19-26: STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

Set SS PIF at the

Acknowledge sequence starts here,

write to SSPCON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

end of receive

ACKEN = 1, ACKDT = 0

SSPIF

software S et SS PIF at the end

of Acknowledge sequence

Cleared in

software

ACK

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2,

set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

ninth clock

SCL broug ht hi gh afte r TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

PIC18F2455/2550/4455/4550

19.4.14 SLEEP OPERATION

While in Sleep mode, the I2C module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

19.4.15 EFFECTS OF A RESET

A Reset disable s the MSSP module and terminates the

current transfer.

19.4.16 MULT I-MAS TER MO DE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

deter mination of when the bus i s free. The S top (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I 2C bus may

be taken when the P bit (SSPSTAT<4>) is set, or the

bus is Idle, with both the S and P bits clear. When the

bus is busy, enabling the MSSP interrupt will generate

the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed in

hardware with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfe r

• Data Transfer

• A Start Cond ition

• A Repeated Start Condition

• An Acknowledge Condition

19.4.17 MUL TI -MA STE R COM M UNI CAT ION ,

BUS COLLI SION AND BU S

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sample d on th e SDA pin = 0,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCLIF and reset the

I2C port to its Idle state (Figure 19-27).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are dea sserted and the

SSPBUF can b e written to . When the us er servic es th e

bus collision Interrupt Service Routine and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are deasserted and the respective control bits in

the SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine and if

the I2C bus is free, the user can resume com munication

by asserting a Start condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

A write to the SSPBUF bit will start the transmission of

data at the first data bit regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detectio n of Start and S top conditions allows the determi-

nation o f when th e bus is free. Control of the I2C bus can

be taken when the P bit is set in the SSPSTAT register,

or the bus is Idl e a nd the S and P bi ts are clea red .

FIGURE 19-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data doesn’t match what is driven

Bus collision has occurred.

Set Bus Collision

Interrupt Flag (BCLIF)

by the master.

by master

Data changes

while SCL = 0

PIC18F2455/2550/4455/4550

19.4.17.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sam pled low at th e beginning of

the Start condition (Figure 19-28).

b) SCL is sampled l ow be fore SDA is as se rted low

(Figure 19-29).

During a Start condition, both the SDA and the SCL

pins are monitored.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start conditi on is abort ed,

• the BCLIF flag is set and

• the MSSP module is reset to its inactive state

(Figure 19-28).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded from SSPADD<6:0>

and counts down to ‘0’. If the SCL pin is sampled low

while SDA is high, a bus collision occurs because it is

assumed that another master is attempting to drive a

data ‘1’ during the Start condition.

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 19-30). If, however , a ‘1’ is sampl ed on the SDA

pin, the S DA pin is asserted low at th e end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to ‘0’. If the SCL pin is sampled as ‘0’,

during this time a bus collision does not occur. At the

end of t he BRG co unt , the SCL pin is a sserted low.

FIGURE 19-28: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The reason that bus collision is not a factor

during a Start condition is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDA before the other.

This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address

following the Start condition. If the address

is the same, arbitration must be allowed to

continue into the data portion, Repeated

Sta rt or Stop condition s.

SDA

SCL

SEN SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPIF set because

MSSP module reset into Idle state.

SEN cleared aut omati cally because of bus coll isi on.

S bit and SSPIF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCLIF

SSPIF

SDA = 0, SCL = 1.

SSPIF and BCLIF are

cleared in software

SSPIF and BCLIF are

cleared in software

Set BCLIF,

Start condition. Set BCLIF.

PIC18F2455/2550/4455/4550

FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCL = 0)

FIGURE 19-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SEN bus collision occurs. Set BCLIF.

SCL = 0 before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupt cleared

in software

bus collision occurs. Set BCLIF.

SCL = 0 before BRG time-out,

‘0’‘0’

SDA

SCL

SEN

Set S

Less th an TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupts cleared

in software

set SS PIF

SDA = 0, SCL = 1,

SCL pulled low after BRG

time-out

Set SS PIF

‘0’

SDA pulled low by other master .

Reset BRG and assert SDA.

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

PIC18F2455/2550/4455/4550

19.4.17.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occu rs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user dea sserts SDA and the pin is a llowed to

float high, the BRG is loaded with SSPADD<6:0> and

count s down to ‘0’. Th e SCL pin is then deasserted an d

when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, see

Figure 19-31). If SDA is sampled high, the BRG is

reloaded and begins counting. If SDA goes from high-to-

low before the BRG times out, no bus collision occurs

because no two masters can assert SDA at exactly the

same time.

If SCL goes from high-to-low before the BRG times out

and SDA has not al ready been asserted, a bus collision

occurs. In this case, another master is attempting to

tran smit a data ‘1’ during the Repeated Start condition

(see Figure 19-32).

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 19-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 19-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCLIF

SSPIF

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

Cleared in software

‘0’

SDA

SCL

BCLIF

RSEN

SSPIF

Interrupt cleared

in software

SCL goes low before SDA,

set BCLIF. Release SDA and SCL.

TBRG TBRG

‘0’

PIC18F2455/2550/4455/4550

19.4.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),

the Baud R ate Generator is loaded w ith SSP AD D<6:0>

and counts down to ‘0’. After the BRG times out, SDA

is sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 19-33). If the SCL pin is

sample d lo w befo re SD A is allowed to float hi gh , a bu s

collis ion occ urs. This is anoth er case of anot her m aster

attempting to drive a data ‘0’ (Figure 19-34).

FIGURE 19-33: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 19-34: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

SDA asserted low

SDA sam ple d

low after TBRG,

set BCLIF

‘0’

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCLIF

‘0’

PIC18F2455/2550/4455/4550
DS39632D-page 236 Preliminary © 2007 Microchip Technology Inc.
TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION       
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
TRISC TRISC7 TRISC6 ——— TRISC2 TRISC1 TRISC0 54
TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 54
SSPBUF MSSP Receive Buffer/Transmit Register 52
SSPADD MSSP Address Register in I2C Slave mod e. 
MSSP Baud Rate Reload Register in I2C Master mode. 52
TMR2 Timer2 Register 52
PR2 Timer2 Period Register 52
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 52
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 52
SSPSTAT SMP CKE D/A PSR/WUA BF 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I2C™ mode.
Note 1: These registers or bits are not implemented in 28-pin devices.

PIC18F2455/2550/4455/4550

20.0 ENHANCED UNIVERSA L

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is one of the

two serial I/ O modules. (G enerically, the USAR T is also

known as a Serial Communications Interface or SCI.)

The EUSART can be configured as a full-duplex

asynchronous system that can communicate with

peripheral devices, such as CRT terminals and

personal computers. It can also be configu red as a half-

duplex synchronous system that can communicate

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs, etc.

The Enhanced USART module implements additional

features, including automatic baud rate detection and

calibration, automatic wake-up on Sync Break recep-

tion and 12-bit B reak chara cter transmit. These ma ke it

ideally suited for us e in Local I nterconnect Ne twork bus

(LIN bus) systems.

The EUSART can be configured in the following

modes:

• Asynchronous (full-duplex) with:

- Auto-wake-up on Break signal

- Auto-baud calibration

- 12-bit Break charac ter tran sm is si on

• Synchronous – Master (half-duplex) with

selectable clock polarity

• Synchronous – Slave (half-d uplex) with selectable

clock polarity

The pins of the Enhanced USART are multiplexed

with PORTC. In order to configure RC6/TX/CK and

RC7/RX/DT/SDO as an EUSART:

• bit SPEN (RCSTA<7>) must be set (= 1)

• bit TRISC<7> must be set (= 1)

• bit TRISC<6> must be set (= 1)

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These are detailed on the following pages in

respectively.

Note: The EUSART control will automatically

reconfigure the pin from input to output as

needed.

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-Bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send Sync Break on next transmission (cleared by hardware upon completion)

0 = Sync Break transmission completed

Synchronous mode:

Don’t care.

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode .

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous

Slave mode.

PIC18F2455/2550/4455/4550

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-Bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1 = En able s single rece ive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4 CREN: Conti nuous Receive Enab le bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enab le bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F2455/2550/4455/4550

R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)

0 = No BRG rollover has occurred

bit 6 RCIDL: Receive O perat ion Idle Status bit

1 = Receive operation is Idle

0 = Receive operation is active

bit 5 RXDTP: Received Data Polarity Select bit

Asynchronous mode:

1 = RX data is inverted

0 = RX data received is not inverted

Synchronous modes:

1 = CK cl ocks are inverted

0 = CK clocks are not inverted

bit 4 TXCKP: Clock and Data Polarity Select bit

Asynchronous mode:

1 = TX data is inverted

0 = TX data is not inverted

Synchronous modes:

1 = CK cl ocks are inverted

0 = CK clocks are not inverted

bit 3 BRG16: 16-Bit Baud Rate Register Enable bit

1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG

0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in

hardware on following rising edge

0 = RX pin not monitored or rising edge detected

Synchronous mode:

Unused in this mode .

bit 0 ABDEN: Auto-Baud Dete ct Enab le bit

Asynchronous mode:

1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);

cleared in hardware upon completion.

0 = Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode .

PIC18F2455/2550/4455/4550

20.1 Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit, or 16-bit, generator that

supports both the Asynchronous and Synchronous

modes of the EUSART. By default, the BRG operates

in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>)

selects 16-bit mode.

The SPBRGH:SPBRG regi ste r p air co ntro ls the perio d

of a free-running timer. In Asynchronous mode, bits

BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also

control the baud rate. In Synchronous mode, BRGH is

ignored. Table 20-1 shows the formula for c om putation

of the baud rate for different EUSART modes which

only a pply i n Mas te r mode (int ernall y gen erated clock ).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 20-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 20-1. Typical baud

rates and error values for the various Asynchronous

modes are shown in T able 20-2. It may be advantageous

to use the high baud rate (BRGH = 1), or the 16-bit BRG

to reduce the baud rate error, or achieve a slow baud

rate for a fast oscillator frequency.

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

20.1.1 OPE RATI ON IN POWE R-M AN AGED

MODES

The device clock is used to generate the desired baud

rate. When one of the power-managed modes is

entered, the new clock source may be operating at a

different frequency. This may require an adjustment to

the value in the SPBRG register pair.

20.1.2 SAMPLING

The data on the RX pin is sampled three times by a

majority detect circuit to determine if a high or a low

level is present at the RX pin.

TABLE 20-1: BAUD RATE FORMULAS

Configuration Bits BRG/EUSART Mode Baud Rate Formula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n + 1)]

001 8-bit/Asynchronous FOSC/[16 (n + 1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous FOSC/[4 (n + 1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair

PIC18F2455/2550/4455/4550

EXAMPLE 20-1: CALCULATING BAUD RATE ERROR

TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

For a device wit h F OSC of 16 MHz, desire d baud rat e of 960 0, Asynchronous mode, 8-b it BRG:

Desired B aud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

X=((FOSC/Desired Baud Rate)/ 64) – 1

= ((16000 000/9600)/6 4) – 1

= [25.042] = 25

Calcu lated Baud Rate = 16000000/(64 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desired Baud Rate)/De sired Baud Rat e

= (9615 – 9600)/9600 = 0.16%

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset V alues

on page

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53

BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH EUSART Baud Rate Generator Register High Byte 53

SPBRG EUSART Baud Rate Generator Register Low Byte 53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

PIC18F2455/2550/4455/4550

TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103

2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51

9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12

19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —

57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —

115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51

1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12

2.4 2.404 0.16 25 2403 -0.16 12 — — —

9.6 8.929 -6.99 6 — — — — — —

19.2 20.833 8.51 2 — — — — — —

57.6 62.500 8.51 0 — — — — — —

115.2 62.500 -45.75 0 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2————————————

2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207

9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 — — — — — — 300 -0.16 207

1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51

2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25

9.6 9.615 0.16 25 9615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

PIC18F2455/2550/4455/4550

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665

1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415

2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207

9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207

1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51

2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25

9.6 9.615 0.16 25 9615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665

1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665

2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832

9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207

19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103

57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34

115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832

1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207

2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103

9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25

19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12

57.6 58.824 2.12 16 55555 3.55 8 — — —

115.2 111.111 -3.55 8 — — — — — —

TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC18F2455/2550/4455/4550

20.1.3 AUTO-BAUD RATE DETECT

The Enhan ced USART module s up ports the autom ati c

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

The automatic baud rate measurement sequence

(Figure 20-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

In the Auto-Bau d Rate Detect (ABD) mode, the clock to

the BRG i s reversed. Rather than the BRG c locking the

incomi ng RX signal, the RX signal is tim ing the BRG. In

ABD mode, the internal Baud Rate Generator is used

as a coun ter to time the bit p eriod of the inco ming serial

byte stream.

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The Auto-Baud Rate

Detect must receive a byte with the value 55h (ASCII

“U”, which is also the LIN bus Sync character) in order to

calculate the proper bit rate. The measurement is taken

over both a low and a high bit time in order to minimize

any effec ts caused by asymmetry o f the incoming signal.

After a Start bit, the SPBRG begins counting up, using

the preselected clock source on the first rising edge of

RX. After eight bits on the RX pin, or the fifth rising edge,

an accumulated value tot alling the proper BRG period is

left in the SPBRGH:SPBRG register pair. Once the 5th

edge is seen (thi s should correspond to the S top bit), the

ABDEN bit is automatically clea red.

If a rollover of the BRG occurs (an overflow from FFFFh

to 0000h), the event is trapped by the ABDOVF status

bit (BAUDCON<7>). It is set in hardware by BRG

rollovers and can be set or cleared by the user in

software. ABD mode remains active after rollover

eve nts and the ABDEN bit remains set (Figure 20-2).

While calibrating the baud rate period, the BRG

registers are clocked at 1/8th the preconfigured clock

rate. Note that the BRG clock will be configured by the

BRG16 and BRGH bits. Independent of the BRG16 bit

setting, bo th the SPBRG and SPBRGH will b e use d a s

a 16-bit counter. This allows the user to verify that no

carry occurred for 8-bit modes by checking for 00h in

the SPBRGH register. Refer to Table 20-4 for counter

clock rates to the BRG.

While the ABD sequence takes place, the EUSART

state machine is held in Idle. The RCIF interrupt is set

once the fifth rising edge on RX is detected. The value

in the RCREG needs to be read to clear the RCIF

interrupt. The contents of RCREG should be discarded.

TABLE 20-4: BRG COUNTER

CLOCK RATES

20.1.3.1 ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisi-

tion, the EUSART transmitter cannot be used during

ABD. This means that whenever the ABDEN bit is set,

TXREG ca nnot be writte n to. Users shou ld also ensu re

that ABDEN does not become set during a transmit

sequenc e. Faili ng to do this m ay resul t in unp redict able

EUSART operation.

Note 1: If the WUE bit is set with the ABDEN bit,

Auto-Baud Rate Detection will occur on

the byte following the Break character.

2: It is up to the user to determine that the

incomi ng character ba ud rate is within th e

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible

due to bit error rates. Overall system

timing and communication baud rates

must be taken into consideration when

using the Auto-Baud Rate Detection

feature.

BRG16 BRGH BRG Counter Clock

00 FOSC/512

01 FOSC/128

10 FOSC/128

11 FOSC/32

Note: During the ABD sequence, SPBRG and

SPBRGH are both used as a 16-bit counter,

independent of the BRG16 setting.

PIC18F2455/2550/4455/4550

FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION

FIGURE 20-2: BRG OVERFLOW SEQUENCE

BRG Value

RX pin

ABDEN bit

RCIF bit

bit 0 bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto-Cleared

Set by User

XXXXh 0000h

Edge #1 bit 2 bit 3

Edge #2 bit 4 bit 5

Edge #3 bit 6 bit 7

Edge #4

001Ch

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

SPBRG XXXXh 1Ch

SPBRGH XXXXh 00h

Stop b i t

Edge #5

Start bit 0

XXXXh 0000h 0000h

FFFFh

BRG Clock

ABDEN bit

RX pin

ABDOVF bit

BRG Value

PIC18F2455/2550/4455/4550

20.2 EUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA<4>). In this mode, the

EUSART uses standard Non-Return-to-Zero (NRZ)

format (one Start bit, eight or nine data bits and one

Stop bit). The most common data format is 8 bits. An

on-chip dedicated 8-bit/16-bit Baud Rate Generator

can be used to derive standard baud rate frequencies

from the osci lla tor.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent but use the same data format and baud

rate. The Baud Rate Generator produces a clock, either

x16 or x64 of the bit shift rate depending on the BRGH

and BRG16 bits (TXST A<2> and BAUDCON<3>). Parity

is not supported by the hardware but can be

implemented in softw are and stored as the 9 th data bit.

The TXCKP (BAUDCON<4>) and RXDTP

(BAUDCON<5>) bits allow the TX and RX signals to be

inverted (polarity reversed). Devices that buffer signals

between TTL and RS-232 levels also invert the signal.

Setting the TXCKP and RXDTP bits allows for the use of

circuits that provide buffering without inverting the signal.

When operating in Asynchronous mode, the EUSART

module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

• Auto-Wake-up on Break signal

• 12-Bit Break Character Transmit

• Auto-Ba ud Rate Detec tio n

• Pin State Polarity

20.2.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 20-3. The heart of the transmitter is the T ransmit

(Serial) Shi ft R eg ist er (TSR). T he Sh ift re gis te r obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG register (if available).

Once the TXREG register transfers the data to the TSR

and the TXIF flag bit (PIR1<4>) is set. This interrupt can

be enab led or di sabled by s etting o r clearing the in terrupt

enable bit, TXIE (PIE1<4>). TXIF will be set regardless of

the state of TXIE; it cannot be cleared in software. TXIF

is also not cleared immediately upon loading TXREG, but

becomes valid in the second instruction cycle following

the lo ad i nstru ct ion. Poll ing T XIF imme diate ly f ollo win g a

load o f TXREG wi ll re tu rn invali d res ul t s .

While TXIF i ndi cates the st a tus of the TXR EG regi ste r,

another bit, TRMT (TXSTA<1>), shows the status of

the TSR register. TRMT is a read-only bit which is set

when the TSR register is empty. No interrupt logic is

tied to this bit so the user has to poll this bit in order to

determine if the TSR register is empty.

The TXCKP bit (BAUDCON<4>) allows the TX signal to

be inverted (polarity reversed). Devices that buffer

signals from TTL to RS-232 levels also invert the signal

(when TTL = 1, RS-232 = neg ative). Inverting the polar-

ity of the TX pin data by setting the TXCKP bit allows for

use of circuits that provide buf fering without inverting the

signal.

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asy nch ron ous seri al port by clearin g

bit SYNC and setting bit SPEN.

3. If the sig nal from the TX pin is to b e inverted , set

the TXCKP bit.

4. If interrupts are desired, set enable bit TXIE.

5. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

6. Enable the transmission by setting bit TXEN

which will also set bit TXIF.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Load data to the TXREG register (starts

transmission).

9. If using interrup ts, ensu re that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit T XIF is set when en able bit TXEN

is set.

PIC18F2455/2550/4455/4550

FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM

FIGURE 20-4: ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TX NOT INVERTED)

FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK),

TXCKP = 0 (TX NOT INVERTED)

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG Register

TSR Register

(8) 0

TX9

TRMT SPEN

TX pin

Pin Buffer

and Control

• • •

SPBRGH

BRG16

TXCKP

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREG

BRG Output

(Shift Clock)

TX (pin)

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Tran s mit Sh ift

Reg. Empty Flag)

1 TCY

Stop bit

Word 1

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

TX (pin)

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram s hows t wo consecutive transmissions.

1 TCY

Start bit

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 249
PIC18F2455/2550/4455/4550
TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION       
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Trans m it Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

20.2.2 EUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 20-6.

The data is receive d on th e R X pin an d driv es the da ta

recovery block. The data recovery block is actually a

high-sp eed shifter operating at x16 times the baud rat e,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

The RXDTP bit (BAUDCON<5>) allows the R X signal to

be inverted (polarity reversed). Devices that buffer

signals from RS-232 to TTL levels also perform an inver-

sion of the signal (when RS-232 = positive, TTL = 0).

Inverting the polarity of the RX pin data by setting the

RXDTP bit allows for the use of circuits that provide

buffe ring without inverting the si gnal.

To set up an Asynchronous Reception:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If the signal at the RX pin is to be inverted, set

the RXDTP bit.

4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.

6. Enable the reception by setting bit CREN.

7. Flag bit, RCIF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RCIE, was set.

8. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during r eception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

enable bit C RE N.

11. If usin g interrup ts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

20.2.3 SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This m ode w o uld ty pi cally be us ed in RS-485 sy ste ms .

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asy nch ron ous seri al port by clearin g

the SYNC bit and setting the SPEN bit.

3. If the signal at the RX pin is to be inverted, set

the RXDTP bi t. If t he signal from the TX pin is to

be inverted, set the TXCKP bit.

4. If in terrupts a re requ ired, se t the RCE N bit and

select the desired pr iority level with the RCIP bit.

5. Set the RX9 bit to enable 9-bit reception.

6. Set the ADDEN bit to enable address detect.

7. Enable reception by setting the CREN bit.

8. The RCIF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RCIE and GIE bits are set.

9. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if app lic able).

10. Read RCREG to determine if the device is being

addressed.

11. If any error occurred, clear the CREN bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 251
PIC18F2455/2550/4455/4550
FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM     
FIGURE 20-7: ASYNCHRONOUS RECEPTION, R XDTP = 0 (RX NOT INVERTED)          
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
RCREG EUSART Receive Reg is ter 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these b its clear.
x64 B aud Rate CLK
Baud Rate Generator
RX
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 7 1 0
RX9
•  •  •
SPBRGSPBRGH
BRG16
or
÷ 4
RXDTP
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0
Stop
bit
Start
bit Start
bitbit 7/8 Stop
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Inte rru pt Flag )
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.

PIC18F2455/2550/4455/4550

20.2.4 AUTO-WAKE-UP ON SYNC

BREAK CHARACTER

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper byte reception cannot be per-

formed. Th e auto-wak e-up feature al lows the cont roller

to wake-up due to activity on the RX/DT line while the

EUSART is operating in Asynchronous mode.

The auto-wake-up feature is enabled by setting the

WUE bit (BAUDCON<1>). Once set, the typical receive

sequence on RX/DT is disabled and the EUSART

remains in an Idle state, mon itoring for a wake-up event

independent of the CPU mode. A wake-up event

consists of a high-to-low transition on the RX/DT line.

(This coincides with the start of a Sync Break or a

Wake-up Sign al cha r acter for the LIN protoc ol .)

Following a wake-up event, the module generates an

RCIF interrupt. The interrupt is generated synchro-

nously to the Q clocks in normal operating modes

(Figure 20-8) and asynchronously, if the device is in

Sleep mode (Figure 20-9). The interrupt condition is

cleared by reading the RCREG register.

The WUE bit is automatically cleared once a low-to-

high transition is observed on the RX line following the

wake-u p e vent. At this point, the EUSART mo dul e i s in

Idle mode and retu rns to normal operation. This signals

to the user that the Sync Break event is over.

20.2.4.1 Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX/DT, information with any state

changes before the Stop bit may signal a false End-of-

Character and cause data or framing errors. To work

properly, therefore, the initial character in the trans-

missio n must be all ‘0’s. This can be 00h (8 bytes) for

stan dard RS-2 32 devi ces or 00 0h (12 bit s) for LIN bus.

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., XT or HS mode). The Sync

Break (or Wake-up Signal) character must be of

suf f icient length and be foll ow ed by a s uf f ic ien t inte rva l

to allow enough time for the selected oscillator to start

and provide proper initialization of the EUSART.

20.2.4.2 Special Considerations Using

the WUE Bit

The timi ng of WUE and R CIF events ma y cause so me

confusion when it comes to determining the validity of

received data. As noted, setting the WUE bit places the

EUSART in an Idle mode. The wake-up event causes a

receive interrupt by setting the RCIF bit. The WUE bit is

cleared after this when a rising edge is seen on RX/DT.

The interrupt condition is then cleared by reading the

RCREG register. Ordinarily, the data in RCREG will be

dummy data and should be disca rded.

The fact that the WUE bit has been cleared (or is still

set) and the RCIF flag is set should not be used as an

indicator of the integrity of the data in RCREG. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assu re th at n o act ual da ta is lo st, che ck th e RCID L

bit to ve rify th at a receive ope rati on is not in proces s. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(1)

RX/DT Line

RCIF

Note 1: The EUSART remains in Idle while the WUE bit is set.

Bit set by user

Cleared due to user read of RCREG

Auto-Cleared

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(2)

RX/DT Line

RCIF

Bit set by user

Cleared due to user read of RCREG

Sleep Command Executed

Note 1: If the wake-up eve nt requires long oscilla tor warm-up time, t he auto-clear of th e WUE bit can occur befor e the oscillator is r eady. Th is

sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

Note 1

Auto-Cleared

PIC18F2455/2550/4455/4550

20.2.5 BREAK CHARACTER SEQUENCE

The EUSART mod ule ha s t he c apabili ty of s en din g th e

special Break chara cter sequences that are required by

the LIN bus standard. The Break character transmit

cons ists of a Start bit, foll owed by tw elve ‘ 0’ bits and a

Stop bit. The Frame Break character is sent whenever

the SENDB and TXEN bits (TXSTA<3> and

TXSTA<5>) are set while the Transmit Shift register is

loaded with data. Note that the value of data written to

TXREG will be ignored and all ‘0’s will be transmitted.

The SENDB bit i s automaticall y reset by ha rdware after

the correspon din g Stop bit is sent. This al lo w s t he us er

to preloa d the trans mit FIFO with the n ext transm it byte

following the Break character (typically, the Sync

character in the LIN specification).

Note that the data value written to the TXREG for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 20-10 for the timing of the Break

character sequence.

20.2.5.1 Break and Sync Transmit Sequenc e

The following sequence will send a message frame

header ma de up of a Break, followed by an Auto-Bau d

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to set up the

Break character.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transm it FIFO buf fe r.

5. After the Break ha s been s ent, the SENDB bit i s

reset by hardware. The Sync character now

transmi t s in the prec onfigured mode.

When the TXR EG b ec om es em pty, as indicated by the

TXIF, the next data byte can be written to TXREG.

20.2.6 RECE IVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a freq uency of 9/ 13 the typi cal spee d. This allow s for

the Stop bit transition to be at the correct sampling

location (13 bits for Break versus Start bit and 8 data

bits for typic al dat a ) .

The second method uses the auto-wake-up feature

describ ed in Section 20.2.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two transitions on RX/DT,

cause an RCIF interru pt and receiv e the n ext da ta byte

follow ed by ano the r interru pt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. Fo r both methods, th e user can set the ABD bit

once the TXIF interrupt is observed.

FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE

Write to TXREG

BRG Output

(Shift Clock)

Start bit bit 0 bit 1 bit 11 Stop bit

Break

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TX (pin)

TRMT bit

(Transmi t Sh ift

Reg. Empty Flag)

SENDB

(Transmi t Sh ift

Reg. Empty Flag)

SENDB sampled here Auto-Cleared

Dummy Write

PIC18F2455/2550/4455/4550

20.3 EUSART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit,

SYNC (TXSTA<4>). In addition, enable bit, SPEN

(RCSTA<7>), is set in order to configure the TX and RX

pins to CK (clock) and DT (data) lines, respectively.

The Master mode indicates that the processor

transmits the master clock on the CK line.

Clock polarity (CK) is selected with the TXCKP bit

(BAUDCON<4>). Setting TXCKP set s t he Idl e stat e on

CK as high, while clearing the bit sets the Idle state as

low. Data polarity (DT) is selected with the RXDTP bit

(BAUDCON<5>). Setting RXDTP set s the Idle st ate on

DT as hi gh , w h il e c le ar in g th e bi t se ts t he Idl e stat e as

low. DT is sampled when CK returns to its idle state.

This option is provided to support Microwire devices

with this module.

20.3.1 EUSART SYNCHRONOUS MASTER

TRANSMISSION

The EUSART transmitter block diagram is shown in

Figure 20-3. The heart of the transmitter is the T ransmit

(Serial) Shi ft Reg ist er (TSR). T he Shift registe r obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

Once the TXR EG register tr ansfers the dat a to the TSR

the TXIF flag bit (PIR1<4>) is se t. The interrupt can be

enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF is set regardless of

the state of enable bit TXIE; it cannot be cleared in

softwa re. It wi ll res et onl y w hen n ew dat a is load ed in to

the TXREG register.

While flag bit, TXIF, indicates the status of the TXREG

status of the TSR register . TRMT is a read-only b it which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to deter-

mine if the TSR register is empty. The TSR is not

mapped in data memory so it is not available to the user .

To set up a Synchronous Master Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. If the signal fro m the CK pin is to be inverte d, set

the TXCKP bit. If the sig nal from the DT pin is to

be inverted, set the RXDTP bit.

4. If interrupts are desired, set enable bit TXIE.

5. If 9-bit transmission is desired, set bit TX9.

6. Enable the tr ansmission by setting bit TXEN.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. S tart transmission by loading da ta to the TXREG

9. If using interrup ts, ensu re that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 20-11: SYNCHRONOUS TRANSMISSION

bit 0 bit 1 bit 7

Word 1

Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2 bit 0 bit 1 bit 7

RC6/TX/CK pin

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT b it

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

RC6/TX/CK pin

(TXCKP = 0)

(TXCKP = 1)

RC7/RX/DT/

SDO pin

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 255
PIC18F2455/2550/4455/4550
FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)       
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION       
RC7/RX/DT/SDO pin
RC6/TX/CK pin
Write to
TXRE G  r e g
TXIF  b i t
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transm it Regis ter 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550
DS39632D-page 256 Preliminary © 2007 Microchip Technology Inc.
20.3.2 EUSART SYNCHRONOUS 
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled  by setting either the Single  Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable  bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If the signal fro m the CK pin is  to be inverte d, set
the TXCKP bit. If  the sig nal from the  DT pin  is to
be inverted, set the RXDTP bit.
5. If interrupts are desired, set enable bit RCIE.
6. If 9-bit reception is desired, set bit RX9.
7. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
8. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
9. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If any error occurred, clear the error by clearing
bit CREN.
12. If using interrupts, ensure that the GIE and PEIE bits
in the INT CON re gister ( INTCON< 7:6>) are  set.
FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)       
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION       
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
RCREG EUSART Receive Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RC7/RX/DT/SDO
RC6/TX/CK pin
Write  t o
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
‘
0
’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC6/TX/CK pin
pin
(TXCKP = 0)
(TXCKP = 1)

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 257
PIC18F2455/2550/4455/4550
20.4 EUSART Synchronous 
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchron ous Master  mode in that t he shift clock  is sup-
plied e xternally  at the C K pin (ins tead of be ing supp lied
internally in Master mode). This allows the device to
transfer or receive data while in any power-managed
mode.
20.4.1 EUSART SYNCHRONOUS 
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit. 
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set. 
d) When the first word has  been  shifted  out of  TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set. 
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep . If the g lobal interrupt i s enabled,
the program will branch to the interrupt vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If the signal fro m the CK pin is to be  inverted, set
the TXCKP bit. If  the sig nal from the  DT pin  is to
be inverted, set the RXDTP bit.
5. If 9-bit transmission is desired, set bit TX9.
6. Enable the transmission by setting enable bit
TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Start transmission by loading data to the
TXREGx register.
9. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION       
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Reset 
Values 
on pag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transmi t Regis ter 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550
DS39632D-page 258 Preliminary © 2007 Microchip Technology Inc.
20.4.2 EUSART SYNCHRONOUS SLAVE 
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR registe r will transfer the  data to the
RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the chip from the low-
power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If the signal fro m the CK pin is  to be inverte d, set
the TXCKP bit. If  the sig nal from the  DT pin  is to
be inverted, set the RXDTP bit.
4. If 9-bit reception is desired, set bit RX9.
5. To enable reception, set enable bit CREN.
6. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
bit CREN.
10. If using inte rrupts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION      
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
RCREG EUSART Receive Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Genera tor Regi ste r High Byte 53
SPBRG EUSART Baud Rate Generator Regi ster Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

PIC18F2455/2550/4455/4550

21.0 10-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has

10 inputs for the 28-pin devices and 13 for the

40/44-pin devices. This module a llows conversion of an

analog input signal to a corresponding 10-bit digital

number.

The module has five registers:

• A/D Result Hi gh Regi ste r (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Regis ter 0 (ADCO N0)

• A/D Control Regis ter 1 (ADCO N1)

• A/D Control Regis ter 2 (ADCO N2)

The ADCON0 register, shown in Register 21-1,

controls the operation of the A/D module. The

ADCON1 register, shown in Register 21-2, configures

the functions of the port pins. The ADCON2 register,

shown in Register 21-3, configures the A/D clock

source, p rogrammed acquisi tion time and justification.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS3:CHS0: Analog Channel Select bits

0000 = Channel 0 (AN0)

0001 = Channel 1 (AN1)

0010 = Channel 2 (AN2)

0011 = Channel 3 (AN3)

0100 = Channel 4 (AN4)

0101 = Channel 5 (AN5)(1,2)

0110 = Channel 6 (AN6)(1,2)

0111 = Channel 7 (AN7)(1,2)

1000 = Channel 8 (AN8)

1001 = Channel 9 (AN9)

1010 = Channel 10 (AN10)

1011 = Channel 11 (AN11)

1100 = Channel 12 (AN12)

1101 = Unimplemented(2)

1110 = Unimplemented(2)

1111 = Unimplemented(2)

bit 1 GO/DONE: A/D Conversion Status bit

When ADON = 1:

1 = A/D conversion in progress

0 = A/D Idle

bit 0 ADON: A/D On bit

1 = A/D converter module is enabled

0 = A/D converter module is disabled

Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return a floating input measurement.

PIC18F2455/2550/4455/4550

U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1)

—— VCFG0 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 VCFG0: Voltage Reference Configuration bit (VREF- source)

1 = VREF- (AN2)

0 = VSS

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)

1 = VREF+ (AN3)

0 = VDD

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:

Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When

PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.

2: AN5 through AN7 are available only on 40/44-pin devices.

A = Analog input D = Digital I/O

PCFG3:

PCFG0

AN12

AN11

AN10

AN9

AN8

AN7(2)

AN6(2)

AN5(2)

AN4

AN3

AN2

AN1

AN0

0000(1) AAAAAAAAAAAAA

0001 AAAAAAAAAAAAA

0010 AAAAAAAAAAAAA

0011 DAAAAAAAAAAAA

0100 DDAAAAAAAAAAA

0101 DDDAAAAAAAAAA

0110 DDDDAAAAAAAAA

0111(1) DDDDDAAAAAAAA

1000 DDDDDDAAAAAAA

1001 DDDDDDDAAAAAA

1010 DDDDDDDDAAAAA

1011 DDDDDDDDDAAAA

1100 DDDDDDDDDDAAA

1101 DDDDDDDDDDDAA

1110 DDDDDDDDDDDDA

1111 DDDDDDDDDDDDD

PIC18F2455/2550/4455/4550

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Forma t Select bit

1 = Right justified

0 = Left justified

bit 6 Unimplemented: Read as ‘0’

bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits

111 = 20 TAD

110 = 16 TAD

101 = 12 TAD

100 = 8 TAD

011 = 6 TAD

010 = 4 TAD

001 = 2 TAD

000 = 0 TAD(1)

bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits

111 = FRC (clock derived from A/D RC oscillator)(1)

110 = FOSC/64

101 = FOSC/16

100 = FOSC/4

011 = FRC (clock derived from A/D RC oscillator)(1)

010 = FOSC/32

001 = FOSC/8

000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D

clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F2455/2550/4455/4550

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS) or the voltage level on the

RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.

The A/D converter has a unique feature of being able

to operate while the device is in Sleep mode. To

operate in Sleep, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pi n associ ated with the A/D converter can be

configured as an analog input or as a digital I/O. The

ADRESH and ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is com-

plete, the result is loaded into the ADRESH:ADRESL

cleared and A/D Interrupt Flag bit, ADIF, is set. The

block diagram of the A/D module is shown in

Figure 21-1.

FIGURE 21-1: A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+

Reference

Voltage

VDD(2)

VCFG1:VCFG0

CHS3:CHS0

AN7(1)

AN6(1)

AN5(1)

AN4

AN3

AN2

AN1

AN0

0111

0110

0101

0100

0011

0010

0001

0000

10-Bit

Converter

VREF-

VSS(2)

A/D

AN12

AN11

AN10

AN9

AN8

1100

1011

1010

1001

1000

Note 1: Channels AN5 through AN7 are not available on 28-pin devices.

2: I/O pins have diode protection to VDD and VSS.

PIC18F2455/2550/4455/4550

The value in the ADRESH:ADRESL registers is not

modified for a Power-on Reset. The ADRESH:ADRESL

registers will contain unknown data after a Power-on

Reset.

After the A/D module has been configured as desired,

the sele cted channe l m ust be acquire d b efor e the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 21.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur bet ween setting th e GO/DONE bit an d the actual

start of the conversion.

The following steps should be followed to perform an

A/D conversion:

1. Configure th e A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Selec t A/D conve rsi on clock (ADCON2)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

• Set GO/DONE bit (ADCON0 register)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF, if required.

7. For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 3 TAD is

required before the next acquisition starts.

FIGURE 21-2: A/D TRANSFER FUNCTION

FIGURE 21-3: ANALOG INPUT MODEL

Digital Code Output

3FEh

003h

002h

001h

000h

0.5 LSB

1 LSB

1.5 LSB

2 LSB

2.5 LSB

1022 LSB

1022.5 LSB

3 LSB

Analog Inpu t Voltage

3FFh

1023 LSB

1023.5 LSB

VAIN CPIN

Rs ANx

5 pF

VT = 0.6V

VT = 0.6V ILEAKAGE

RIC ≤ 1k

Sampling

Switch

SS RSS

CHOLD = 25 pF

VSS

VDD

±100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/hold Capacitance (from DAC)

various junctions

= Sampling Switch Re sistanceRSS

VDD

Sampling Switch

1234

(kΩ)

PIC18F2455/2550/4455/4550

21.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 21-3. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance va ries ov er the dev ice vol tag e

(VDD). The sour ce impedanc e af fects th e offse t voltag e

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

To calculate the minimum acquisition time,

Equation 21-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 st eps for the A/D). The

1/2 LSb er ror is the ma ximu m error allow ed for the A/D

to meet its specified resolution.

Example 21-3 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following application system

assumptions:

CHOLD = 25 pF

Rs = 2.5 kΩ

Conversion Error ≤1/2 LSb

VDD =5V → RSS = 2 kΩ

Temperature = 85°C (system max.)

EQUATION 21-1: ACQUISITION TIME

EQUATION 21-2: A/D MINIMUM CHARGING TIME

EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note: When the conversion is started, the

holding cap ac itor i s di scon nected from the

input pin.

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP + TC + TCOFF

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))

TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)

TACQ =TAMP + TC + TCOFF

TAMP =0.2 μs

TCOFF = (Temp – 25°C)(0.02 μs/°C)

(85°C – 25°C)(0.02 μs/°C)

1.2 μs

Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.

TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs

-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs

1.05 μs

TACQ =0.2 μs + 1.05 μs + 1.2 μs

2.45 μs

PIC18F2455/2550/4455/4550

21.2 Selecting and Configuring

Acquisition Time

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set. It also gives users the option to use an

automatically determined acquisition time.

Acquisition time may be set with the ACQT2:ACQT0

bits (ADCON2<5:3>) which provide a range of 2 to

20 TAD. When the GO/DONE bit is set, th e A/D modul e

continues to sample the input for the selected acquisi-

tion time, then automatically begins a conversion.

Since the acquisition time is programmed, there may

be no need to wait for an acquisition time between

selecting a channel and setting the GO/DONE bit.

Manual acquisition is selected when

ACQT2:ACQT0 = 000. When the GO/DONE bit is set,

sampli ng is stopp ed and a conv ersion begi ns. The user

is responsible for ensuri ng the required acquisition time

has passed between selecting the desired input

channel and setting the GO/DONE bit. This option is

also the default Reset state of the ACQT2:ACQT0 bits

and is compatible with devices that do not offer

progra mmab le ac qui sition times.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

21.3 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D c on vers ion re qui res 11 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable. There are seven possible options for TAD:

•2 T

OSC

•4 TOSC

•8 TOSC

•16 TOSC

•32 TOSC

•64 TOSC

• Intern al RC Os cillator

For correct A/D conversions, the A/D conversion clock

(TAD) must be as sho rt as pos sible b ut greate r than the

minimum TAD (see parameter 130 in Table 28-29 for

more information).

Table 21-1 shows the resultant TAD tim es de ri ve d fr o m

the device operating frequencies and the A/D clock

source selected.

TABLE 21-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD) Maximum Device Frequency

Operation ADCS2:ADCS0 PIC18FXXXX PIC18LFXXXX(4)

2 TOSC 000 2.86 MHz 1.43 MHz

4 TOSC 100 5.71 MHz 2.86 MHz

8 TOSC 001 11.43 MHz 5.72 MHz

16 TOSC 101 22.86 MHz 11.43 MHz

32 TOSC 010 45.71 MHz 22.86 MHz

64 TOSC 110 48.0 MHz 45.71 MH z

RC(3) x11 1.00 MHz(1) 1.00 MHz(2)

Note 1: The RC source has a typical TAD time of 4 ms.

2: The R C source has a ty pical TAD time of 6 ms.

3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D

accuracy may be out of spec ificati on.

4: Low-power devices only.

PIC18F2455/2550/4455/4550

21.4 Operation in Power-Managed

Modes

The se lection of th e automa tic acquis ition ti me a nd A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed

mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT2:ACQT0 and

ADCS2:ADCS0 bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

sour ce unt il the con ve r si on has been co mpl eted.

If desired, the device may be placed into the

corr espondi ng Idle m ode dur ing th e conve rsi on. If the

device c loc k freq ue ncy is less tha n 1 MHz, the A/D R C

clock source should be selected.

Operation in the Sleep mode requires the A/D FRC

clock to be selected. If bits ACQT2:ACQT0 are set to

‘000’ and a con version is started, the conversion will be

delay ed on e ins tr uctio n cycl e to allo w exec uti on of the

SLEEP instruc tion and e ntry to Slee p mode. The IDLEN

bit (OSCCON<7>) must have already been cleared

prior to starting the conversion.

21.5 Configuring Analog Port Pins

The ADCON1, TRISA, TRISB and TRISE registers all

configure the A/D port pins. The port pins needed as

analog inputs must have their corresponding TRIS bits

set (input) . If the TRIS bit is cleare d (output), the digit al

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

Note 1: When reading the PORT register, all pins

configured as analog input channels will

read as c lea red (a lo w l evel). Pins co nfi g-

ured as digital inputs will convert as

analog inp ut s. Anal og level s on a digit all y

configured input will be accurately

converted.

2: Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

3: The PBADEN bit in Configuration

reset as analog or digital pins by control-

ling how the PCFG0 bits in ADCON1 are

reset.

PIC18F2455/2550/4455/4550

21.6 A/D Conversions

Figure 21-4 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are cleared. A conversion is

started after the following instruction to allow entry into

Sleep mode before the conversion begins.

Figure 21-5 shows the operation of the A/D converter

after the GO/DONE bit has been set, the

ACQT2:ACQT0 bits are set to ‘010’ and selecting a

4TAD acquisition time before the conversion starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will NOT be updated with the partially completed

A/D conversion sample. This means the

ADRESH:ADRESL registers will continue to contain

the value of the last completed conversion (or the last

value written to the ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

AD wait is required before th e next acquisition can b e

started. After this wait, acquisition on the selected

channel is automatically started.

21.7 Discharge

The discharge phase is used to initialize the value of

the capacitor array. The array is discharged before

every sample. This feature helps to optimize the

unity-gain amplifier as the circuit always needs to

charge the capacitor array, rather than

charge/discharge based on previous measurement

values.

FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note: The GO/DONE bit should NOT be set in

the sam e inst ructio n that tu rns on the A/D.

TAD1TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8 TAD11

Set GO/D ON E bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, ho lding capacitor is connected to analog input.

Conversion starts

b9 b6 b5 b4 b3 b2 b1

b8 b7

On the following cycle:

TAD1

Discharge

123 4 5 67811

Set GO/DONE bit

(Holding capacitor is disconnected)

910

Conversion starts

123 4

(Holding capacitor continues

acquiring input)

TACQ Cycles TAD Cycles

Automatic

Acquisition

Time

b0b9 b6 b5 b4 b3 b2 b1

b8 b7

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

On the following cycle:

TAD1

Discharge

PIC18F2455/2550/4455/4550
DS39632D-page 268 Preliminary © 2007 Microchip Technology Inc.
21.8 Use of the CCP2 Trigger
An A/D conv ersio n can  be st arted  by th e Speci al Eve nt
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and tha t the A/D modu le is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conv ersio n and the Time r1 (or T i mer3) c ounter w ill
be reset to  zero. T imer1 (or T imer3) i s reset to aut omat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D  module is not  enabled (A DON is c leared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
 
TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on pag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 SPPIF(4) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE(4) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP(4) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
ADRESH  A/D Result Register High Byte 52
ADRESL  A/D Result Register Low Byte 52
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 52
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 52
PORTA —RA6
(2) RA5 RA4 RA3 RA2 RA1 RA0 54
TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 54
PORTE RDPU(4) — — —RE3
(1,3) RE2(4) RE1(4) RE0(4) 54
TRISE(4) — — — — — TRISE2 TRISE1 TRISE0 54
LATE(4) — — — — — LATE2 LATE1 LATE0 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator 
configuration; otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registe r s and /or bit s  ar e not impl em en ted on 28-p in dev ic es.

PIC18F2455/2550/4455/4550

22.0 COMPARATOR MODULE

The analog comparator module contains two compara-

tors that can be configured in a variety of ways. The

inputs can be selected from the analog inputs multiplexed

with p ins RA0 th rough RA 5, as well a s the on- chip volt -

age reference (see Section 23.0 “Comparator Voltage

Reference Module”). The digital outputs (normal or

inverted) are available at the pin level and can also be

read th ro ug h the con tro l r egi s ter.

The CMCON register (Register 22-1) selects the

comparator input and output configuration. Block

diagrams of the various comparator configurations are

shown in Figure 22-1.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 = C2 VIN+ > C2 VIN-

0 = C2 VIN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN-

0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN-

0 = C1 VIN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN-

0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output inverted

0 = C2 output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 output inverted

0 = C1 output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM2:CM0 = 110:

1 =C1 VIN- connects to RA3/AN3/VREF+

C2 VIN- connects to RA2/AN2/VREF-/CVREF

0 =C1 VIN- connects to RA0/AN0

C2 VIN- connects to RA1/AN1

bit 2-0 CM2:CM0: Comparator Mode bits

Figure 22-1 shows the Comparator modes and the CM2:CM0 bit settings.

PIC18F2455/2550/4455/4550

22.1 Comparator Configuration

There are eight modes of operation for the compara-

tors, shown in Figure 22-1. Bits CM2:CM0 of the

CMCON register are used to select these modes. The

TRISA register controls the data direction of the

comparator pins for each mode. If the Comparator

mode is cha nged, the com p ara t or o utpu t le vel may not

be valid for the specified mode change delay shown in

Section 2 8.0 “Electrical Characteristics”.

FIGURE 22-1: COMPARATOR I/O OPERATING MODES

Note: Compara tor in terr upts sh ould be dis abled

during a Comparator mode change.

Otherwise, a false interrupt may occur.

RA0/AN0 VIN-

VIN+

RA3/AN3/ Off (Read as ‘0’)

Comparators Reset

CM2:CM0 = 000

RA1/AN1 VIN-

VIN+

RA2/AN2/ Off (Read as ‘0’)

VIN-

VIN+C1OUT

Two Independent Comparators

CM2:CM0 = 010

VIN-

VIN+C2OUT

VIN-

VIN+C1OUT

Two Common Reference Comparators

CM2:CM0 = 100

VIN-

VIN+C2OUT

VIN-

VIN+Off (Read as ‘0’)

One Independent Comparator with Output

CM2:CM0 = 001

VIN-

VIN+C1OUT

VIN-

VIN+Of f (Read as ‘0’)

Comparators Off (POR Default Value)

CM2:CM0 = 111

VIN-

VIN+Of f (Read as ‘0’)

VIN-

VIN+C1OUT

Four Inputs Multiplexed to Two Comparators

CM2:CM0 = 110

VIN-

VIN+C2OUT

From VREF Module

CIS = 0

CIS = 1

CIS = 0

CIS = 1

VIN-

VIN+C1OUT

Two Common Reference Comparators with Outputs

CM2:CM0 = 101

VIN-

VIN+C2OUT

A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch

CVREF

VIN-

VIN+C1OUT

Two Independent Comparators with Outputs

CM2:CM0 = 011

VIN-

VIN+C2OUT

RA5/AN4/SS/HLVDIN/C2OUT*

RA4/T0CKI/C1OUT*/RCV

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

VREF+

RA1/AN1

RA2/AN2/

VREF-/CVREF

RA4/T0CKI/C1OUT*/RCV

RA5/AN4/SS/HLVDIN/C2OUT*

RA0/AN0

RA3/AN3/

VREF+

RA1/AN1

RA2/AN2/

VREF-/CVREF

RA4/T0CKI/C1OUT*/

* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.

RCV

PIC18F2455/2550/4455/4550

22.2 Comparator Operation

A single comparator is shown in Figure 22-2, along with

the relationship between the analog input levels and

the digit al ou tput. When the an alog input a t VIN+ is less

than the analog input VIN-, the outp ut of the comp arator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 22-2 represent

the unce rt ainty, due to inpu t of fset s a nd resp onse t ime.

22.3 Comparator Reference

Depending on the comparator operating mode, either

an external or internal voltage reference may be used.

The analog signal present at VIN- is compared to the

signal at VIN+ and the digital output of the comparator

is adjusted accordingly (Figure 22-2).

FIGURE 22-2: SINGLE COMPARATOR

22.3.1 EXT ERN AL REFE RENCE SIGNA L

When external voltage references are used, the

comparator module can b e configured to have the com-

parators operate from the same or different reference

sour ces. How ever , th resho ld detecto r applica tions ma y

require th e s am e re fere nce. Th e reference sign al m us t

be between VSS and VDD and can be appl ied to eithe r

pin of the comparator(s).

22.3.2 INTERNAL REFERENCE SIGNAL

The com p a r ato r m odu le also al low s th e sel ec tion of an

internally generated voltage reference from the

comparator voltage reference module. This module is

describ ed in m ore de tai l in Section 23.0 “Comparator

Voltage Reference Module”.

The internal reference is only available in the mode

where four inputs are multiplexed to two comparators

(CM2:CM0 = 110). In this mode, the internal voltage

reference is applied to the VIN+ pin of both

comparators.

22.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal ref-

erence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise, the maximum delay of

the comparators should be used (see Section 28.0

“Electri cal Characteristics”).

22.5 Comparator Outputs

The comparator outputs are read through the CMCON

output s may al so be dire ctly output to the RA4 a nd RA5

I/O pins . When enab led, multipl exors in th e output p ath

of the RA4 and RA5 pins will switch and the output of

each pin will be the unsynchronized output of the

comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the specifications.

Figure 22-3 shows the comparator output block

diagram.

The TRISA bits will still function as an output enable/

disable for the RA4 and RA5 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<5:4 >).

–

VIN+

VIN-Output

Output

VIN-

VIN+

Note 1: When reading the PORT register, all pins

configu red a s anal og inp uts will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

2: Analog levels on any pin defined as a

digital input may cau se the in put bu f f e r to

consume more current than is specified.

PIC18F2455/2550/4455/4550

FIGURE 22-3: COMPARATOR OUTPUT BLOCK DIAGRAM

22.6 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

stat us of the out put bits, as rea d from CMCON<7:6> , to

determine the actual change that occurred. The CMIF

bit (PIR2<6>) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

Both the CMIE bit (PIE2<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit (INTCON<7>) must also be set. If

any of these bits are clear, the interrupt is not enabled,

though the CMIF bit will still be set if an interrupt

conditi on oc curs.

The use r , in the Interru pt Service Rout ine, can clear th e

inter rupt in the following manner:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

22.7 Comparator Operation

During Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode, when enabled.

Each operational comparator will consume additional

current, as shown in the comparator specifications. To

minimi ze power co nsumption wh ile in Sleep mod e, turn

off the comparators (CM2:CM0 = 111) before entering

Sleep. If the dev ice w ak es up fro m Sle ep, the c ontents

of the CMCON register are not affected.

22.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state , ca using the comp arat or modul es to be turn ed of f

(CM2:CM0 = 111). However, the input pins (RA0

through RA3) are configured as analog inputs by

default on device Rese t. The I/O configuration for these

pins is determined b y the sett ing of the PCF G3:PCFG0

bits (ADCON1<3:0>). Therefore, device current is

minimized when analog inputs are present at Reset

time.

To RA4 or

RA5 pin

Bus

Data

Set

MULTIPLEX

CMIF

bit

Port pins

Read CMCON

Reset From

other

Comparator

CxINV

EN CL

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR2<6>)

interrupt flag may not get set.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 273
PIC18F2455/2550/4455/4550
22.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 22-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betwee n
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 22-4: COMPARATOR ANALOG INPUT MODEL        
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE  
VA
RS < 10k
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE =  Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
Comparator
Input
Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
PORTA —RA6
(1) RA5 RA4 RA3 RA2 RA1 RA0 54
LATA —LATA6
(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 54
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various 
oscillator modes. When disabled, these bits read as ‘0’.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

23.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The comparator voltage reference is a 16-tap resistor

ladder network that provides a selectable reference

voltage. Although its primary purpose is to provide a

reference for the analog comparators, it may also be

used independently of them.

A block diagram of t he module is shown in Figure 23-1.

The resis tor ladder is segment ed to provide two range s

of CVREF values and has a power-down function to

conserve power when the reference is not being used.

The module’s supply reference can be provided from

either device VDD/VSS or an external voltage reference.

23.1 Configuring the Comparator

Voltage Reference

The vol tag e referen ce m odule i s control led th rough th e

CVRCON register (Register 23-1). The comparator

voltage reference provides two ranges of output

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary diffe rence between the rang es is the si ze of th e

steps selected by the CVREF Selection bits

(CVR3:C VR0), w it h on e ra nge offering finer resolutio n.

The equations used to calculate the output of the

comparator voltage reference are as follows:

If CVRR = 1:

CVREF = ((CVR3:CVR0)/24) x CVRSRC

If CVRR = 0:

CVREF = (CVRSRC/4) + (((CVR3:CVR0)/32) x

CVRSRC)

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF- that are multiplexed with RA2 and RA3. The

voltage source is selected by the CVRSS bit

(CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output (see Table 28-3 in Section 28.0 “Electrical

Characteristics”).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CVREN: Comp ara t or Voltage Referen ce Enab le bit

1 =CV

REF circuit powered on

0 =CV

REF circuit powered down

bit 6 CVROE: Comparator VREF Output Enable bit(1)

1 =CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin

0 =CV

REF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin

bit 5 CVRR: Comparator VREF Range Selection bit

1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low rang e)

0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (h igh range)

bit 4 CVRSS: Com p a rator VREF Source Selection bit

1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)

0 = Comparator reference source, CVRSRC = VDD – VSS

bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)

When CVRR = 1:

CVREF = ((CVR3:CVR0)/24) • (CVRSRC)

When CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)

Note 1: CVROE overrides the TRISA<2> bit setting.

PIC18F2455/2550/4455/4550

FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

23.2 Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 23-1) keep CVREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 28.0 “Electrical Characteristics”.

23.3 Operation During Sleep

When the device wakes up from Sleep through an

interr upt o r a Watchdo g Tim er tim e- out, t he content s of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

23.4 Effects of a Reset

A device Reset disables the voltage reference by

clearing bit, CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit, CVROE (CVRCON<6>) and selects the high-voltage

range by clearing bit, CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

23.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit and the CVROE bit are both set.

Enabling the voltage reference output onto RA2 when

it is con figured as a digital input w ill increase current

consumption. Connecting RA2 as a digital output with

CVRSS enabled will also increase current

consumption.

The RA2 pin can be used as a simple D/A output with

lim ite d dr i ve c apa bi lit y. Du e to t he l i mi te d c ur r e nt dr i ve

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 23-2 shows an example buffering technique.

16-to-1 MUX

CVR3:CVR0

CVREN

CVRSS = 0

VDD

VREF+CVRSS = 1

CVRSS = 0

VREF-CVRSS = 1

16 Steps

CVRR

CVREF

PIC18F2455/2550/4455/4550

FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

CVREF Output

–

CVREF

Module

Voltage

Reference

Output

Impedance

R(1)

RA2

Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.

PIC18FXXXX

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53

TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54

Legend: Shaded cells are not used with the comparator voltage reference.

Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various

oscillator modes. When disabled, these bits read as ‘0’.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

24.0 HIGH/LOW-VOLTAGE DETECT

(HLVD)

PIC18F2455/2550/4455/4550 devices have a

High/L ow-V olta ge Detect mod ule (HL VD ). This is a p ro-

gramma ble circui t that allows th e user to specify both a

device voltage trip point and the direction of change

from that point. If the device experiences an excursion

past the trip point in that direction, an interrupt flag is

set. If the interrupt is enabled, the program execution

will branch to the interrupt vector address and the

software can then respond to the interrupt.

The High/Low-Voltage Detect Control register

(Register 24-1) completely controls the operation of the

HLVD module. This allows the circuitry to be “turned

of f” by th e user un der softw are con trol whi ch minimi zes

the current consumption for the device.

The block diagram for the HLVD module is shown in

Figure 24-1.

R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1

VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VDIRMAG: Voltage Direction Magnitude Select bit

1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)

0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)

bit 6 Unimplemented: Read as ‘0’

bit 5 IRVST: Inter nal Reference Voltage Stable Flag bit

1 = Indicates that the volt age detect l ogic will genera te the interrup t flag at the spec ified volt age range

0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage

range and the HLVD interrupt should not be enabled

bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit

1 = HLVD enabled

0 = HLVD disabled

bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1)

1111 = External analog input is used (input comes from the HLVDIN pin)

1110 = Maximu m setting

0000 = Minimum setting

Note 1: See Table 28-6 in Secti on 28.0 “Electr ic al Characte r istic s” for specifications.

PIC18F2455/2550/4455/4550

The module is enabled by setting the HLVDEN bit.

Each time that the HLVD module is enabled, the

circuitry requires some time to stabilize. The IRVST bit

is a read-only bit and is used to indic ate when the circuit

is stable. The module can only generate an interrupt

after the circuit is stable and IRVST is set.

The VDIRMAG bit determines the overall operation of

the module. When VDIRMAG is cleared, the module

monitors for drops in VDD below a predetermined set

point. Wh en the bit is set, the mo dule moni tors for rises

in VDD above the set point.

24.1 Operation

When the HLVD module is enab led, a comp arator use s

an internally generated reference voltage as the set

point. The set point is compared with the trip point,

where each node in the resistor divider represents a

trip point voltage. The “trip point” voltage is the voltage

level at which the device detects a high or low-voltage

event, depending on the configuration of the module.

When the supply voltage is equal to the trip point, the

voltage tapped off of the resistor array is equal to the

internal reference voltage generated by the voltage

reference module. The comparator then generates an

interrupt signal by setting the HLVDIF bit.

The trip po int v ol tage is sof t ware p rogrammable to any

one of 16 values. The trip point is selected by

programming the HLVDL3:HLVDL0 bits

(HLVDCON<3:0>).

The HLVD mo dule has an add itional f eature that allo ws

the user to supply the trip voltage to the module fr om an

external source. This mode is enabled when bits,

HLVDL3:HLVDL0, are set to ‘1111’. In this state, the

comparator input is multiplexed from the external input

pin, HLVDIN. This gives users flexibility because it

allows them to configure the High/Low-Voltage Detect

interrupt to occur at any voltage in the valid operating

range.

FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Set

VDD

16-to-1 MUX

HLVDEN

HLVDCON

HLVDL3:HLVDL0 Register

HLVDIN

VDD

Externally Ge nerat ed

Trip Point

HLVDIF

HLVDEN

BOREN

Inter na l Voltage

Reference

VDIRMAG

1.2V Typical

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 281
PIC18F2455/2550/4455/4550
24.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Disa bl e t he modu le  by  cl ea ri ng  t he  HLVDEN  bi t
(HLVDCON<4>).
2. Write  the valu e to the HLVDL3:H LVDL0 bit s that
selects the desired HLVD trip point.
3. Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
4. Enable the HLVD module by setting the
HLVDEN bit.
5. Clear the HLVD Interrupt Flag, HLVDIF
(PIR2<2>), which may have been set from a
previous interrupt.
6. Enable the HLVD interrupt, if interrupts are
desired, by setting the HLVDIE and GIE/GIEH
bits (PIE2<2> and INTCON<7>). An interrupt
will not be generated until the IRVST bit is set.
24.3 Current Consumption
When the module is enabled, the HLVD comparator
and volt age divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022
(Section 28.2 “DC Characteristics”).
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be en abled  for short pe riods w here the  volt age
is checked. After doing the check, the HLVD module
may be disabled.
24.4 HLVD Start-up Time
The internal reference voltage of the HLVD module,
specified in electrical specification p arameter D420 (see
Table 28-6 in Section 28.0 “Electrical Characteris-
tics”), may be used by other internal circuitry, such as
the Programmable Brown-out Reset. If the HLVD or
other circuits usin g the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-volt age con dition can  be re liably d etected.
This start-up time, TIRVST, is an interval that is indepen-
dent of device clock speed. It is specified in electrical
specification parameter 36 (Table 28-12). 
The HLVD interru pt f lag  is  no t en abled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to
Figure 24-2 or Figure 24-3.
FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)    
VHLVD
VDD
HLVDIF
VHLVD
VDD
Enable HLVD
TIRVST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLV D IF cleared in software
HLV D IF cleared in software
HLVDIF cleared in software, 
CAS E  1:
CAS E  2:
HLVDIF remains set since HLVD condition still exists
TIRVST
Internal Reference is stable
Internal Reference is stable
IRVST
IRVST

PIC18F2455/2550/4455/4550

FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)

24.5 Applications

In many applications, the ability to detect a drop below

or rise above a particular threshold is desirable. For

example, the HLVD module could be periodically

enabled to de tec t U nivers al Seria l Bus (U SB) attach or

det ach. This a ssumes the dev ice is powered by a lower

voltage source than the USB when detached. An attach

would indicate a high -volt age dete ct from , for ex ampl e,

3.3V to 5V (the voltage on USB) and vice versa for a

detach. This feature could save a design a few extra

components and an attach signal (input pin).

For general battery applications, Figure 24-4 shows a

possible voltage curve. Over time, the device voltage

decreases. When the device voltage reaches voltage,

VA, the HLVD logic generates an interrupt at time, TA.

The interrupt could cause the execution of an ISR,

which would allow the application to perform “house-

keeping tasks” and perform a controlled shutdown

before the device voltage exits the valid operating

range at TB. The HLVD, thus, would give the applica-

tion a time window, represented by the difference

between TA and TB, to safely exit.

FIGURE 24-4: TYPICAL

HIGH/LOW-VOLTAGE

DETECT APPLICATION

VHLVD

VDD

HLVDIF

VHLVD

VDD

Enable HLVD

TIRVST

HLVDIF may not be set

Enable HLVD

HLVDIF

HLVDIF cleared in software

HLV DIF cleared in software,

CASE 1:

CASE 2:

HLV D IF remains set since HLVD condition still exists

TIRVST

IRVST

Internal Reference is stable

IRVST

Time

Voltage

TATB

VA = HLVD trip point

VB = Minimum valid device

operating voltage

Legend:

PIC18F2455/2550/4455/4550

24.6 Operation During Sleep

When en abled, the HLVD circuit ry con tinues to operate

during Sleep. If the device voltage crosses the trip

point, the HLVDIF bit will be set and the device will

wake-up from Sleep. Device execution will continue

from the interrupt vector address if interrupts have

been globally enabled.

24.7 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the HLVD module to be turned off.

TABLE 24-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 52

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51

PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54

PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54

IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

25.0 SPECIAL FEATURES OF THE

CPU

PIC18F2455/2550/4455/4550 devices include several

features intended to maximize reliability and minimize

cost through elimination of external components.

These are:

• Oscillator Selection

• Resets:

- Power -on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Ti mer (WDT)

• Fail-Safe Clock Monitor

• Two-Speed Start-up

• Code Protection

• ID Locations

• In-Circuit Serial Programming

The oscillator can be configured for the application

dependi ng on frequ ency, power , acc uracy and cost . All

of the options are discussed in detail in Section 2.0

“Oscillator Configurations”.

A complete discussion of device Resets and interrupts

is avail able in previous sections of this data sheet.

In addition to their Power-up and Oscillator S ta rt-up T im-

ers provided for Resets, PIC18F2455/2550/4455/4550

devices have a Watchdog Timer, which is either

permanently enabled via the Configuration bits or

software controlled (if con figured as dis abled).

The inclu sio n of an in ternal RC oscill ator also provides

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure.

Two-Speed Start-up enables code to be executed

almost immediate ly on st art-up, whi le the primary cl ock

source completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

PIC18F2455/2550/4455/4550

25.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (rea d as ‘1’) to select var ious

dev ice conf igurati ons. Th ese bits ar e mappe d starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h-3FFFFFh),

which can only be accessed using table reads and

table writes.

Programming the Configuration registers is done in a

manner s imilar to p rogrammin g the Flas h memo ry. The

WR bit in the EECON1 register starts a self-timed write

to the Configuration register . In normal operation m ode,

a TBLWT instruction, with the TBLPTR pointing to the

Configuration register, sets up the address and the

data f or the Configuration register write. Setting the WR

bit starts a long write to the Configuration register. The

Conf igu rati on regi ster s a re writ ten a by te a t a ti me. To

write or erase a configuration cell, a TBLWT instru ct ion

can writ e a ‘1’ or a ‘0’ into the cell. For additional details

on Flash programming, refer to Section 6.5 “Writing

to Flash Program Memory”.

TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value

300000h CONFIG1L —— USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000

300001h CONFIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101

300002h CONFIG2L —— VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111

300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111

300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011

300006h CONFIG4L DEBUG XINST ICPRT(3) ——LVP—STVREN100- -1-1

300008h CONFIG5L — — — —CP3

(1) CP2 CP1 CP0 ---- 1111

300009h CONFIG5H CPD CPB — — — — — — 11-- ----

30000Ah CONFIG6L — — — —WRT3

(1) WRT2 WRT1 WRT0 ---- 1111

30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----

30000Ch CONFIG7L — — — —EBTR3

(1) EBTR2 EBTR1 EBTR0 ---- 1111

30000Dh CONFIG7H —EBTRB— — — — — — -1-- ----

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2)

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010(2)

Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: Unimplemented in PIC18FX455 devices ; maintain this bit set.

2: See Register 25-13 and Register 25-14 for DEVID values. DEVID registers are read-only and cannot be programmed by

the user.

3: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.

PIC18F2455/2550/4455/4550

U-0 U-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0

—— USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-6 Unimplemented: Read as ‘0’

bit 5 USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)

1 = USB clock source comes from the 96 MHz PLL divided by 2

0 = USB clock source comes directly from the primary oscillator block with no postscale

bit 4-3 CPUDIV1:CPUDIV0: System Cloc k Postscaler Selection bits

For XT, HS, EC and ECIO Oscillator modes:

11 = Primary oscillator divided by 4 to derive system cloc k

10 = Primary oscillator divided by 3 to derive system cloc k

01 = Primary oscillator divided by 2 to derive system cloc k

00 = Primary oscillator used directly for system clock (no postscaler)

For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:

11 = 96 MHz PLL divided by 6 to derive system clock

10 = 96 MHz PLL divided by 4 to derive system clock

01 = 96 MHz PLL divided by 3 to derive system clock

00 = 96 MHz PLL divided by 2 to derive system clock

bit 2-0 PLLDIV2:PLLDIV0: PLL Prescaler Selection bits

111 = Divide by 12 (48 MHz oscillator input)

110 = Divide by 10 (40 MHz oscillator input)

101 = Divide by 6 (24 MHz oscillator input)

100 = Divide by 5 (20 MHz oscillator input)

011 = Divide by 4 (16 MHz oscillator input)

010 = Divide by 3 (12 MHz oscillator input)

001 = Divide by 2 (8 MHz oscillator input)

000 = No prescale (4 MHz oscillator input drives PLL directly)

PIC18F2455/2550/4455/4550

R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-0 R/P-1

IESO FCMEN ——FOSC3

(1) FOSC2(1) FOSC1(1) FOSC0(1)

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 IESO: Internal/External Oscillator Switchover bit

1 = Oscillator Switchover mode enabled

0 = Oscillator Switchover mode disabled

bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 FOSC3:FOSC0: Oscillator Selection bits(1)

111x = HS oscillator, PLL enabled (HSPLL)

110x = HS oscillator (HS)

1011 = Internal oscillator, HS oscillator used by USB (INTHS)

1010 = Internal oscillator, XT used by USB (INTXT)

1001 = Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)

1000 = Internal oscillator, port function on RA6, EC used by USB (INTIO)

0111 = EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)

0110 = EC oscillator, PLL enabled, port function on RA6 (ECPIO)

0101 = EC oscillator, CLKO function on RA6 (EC)

0100 = EC oscillator, port function on RA6 (ECIO)

001x = XT oscillator, PLL enabled (XTPLL)

000x = XT os cillator (XT)

Note 1: The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS and

EC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the

microcontroller uses the internal oscillator.

PIC18F2455/2550/4455/4550

U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

—— VREGEN BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2)

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-6 Unimplemented: Read as ‘0’

bit 5 VREGEN: USB Internal Voltage Regulator Enable bit

1 = USB voltage regulator enabled

0 = USB voltage regulator disabled

bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1)

11 = Minimum setting

00 = Maximum setting

bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2)

11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)

10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)

01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00 = Brown-out Reset disabled in hardware and software

bit 0 PWRTEN: Power-up Timer Enable bit(2)

1 = PWRT disabled

0 = PWRT enabled

Note 1: See Section 28.0 “Electrical Characteristics” for the specifications.

2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently

controlled.

PIC18F2455/2550/4455/4550

U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-5 Unimplemented: Read as ‘0’

bit 4-1 WDTPS3:WDTPS0: Watchdog Ti me r Post s ca le Sele ct bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

bit 0 WDTEN: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on the SWDTEN bit)

PIC18F2455/2550/4455/4550

R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1

MCLRE — — — — LPT1OSC PBADEN CCP2MX

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 MCLRE: MCLR Pin Enable bit

1 =MCLR pin enabled, RE3 input pin disabled

0 = RE3 input pin enabled, MCLR pin disabled

bit 6-3 Unimplemented: Read as ‘0’

bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit

1 = Timer1 configured for low-power operation

0 = Timer1 configured for higher power operation

bit 1 PBADEN: PORTB A/D Enable bit

(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)

1 = PORTB<4:0> pins are configured as analog input channels on Reset

0 = PORTB<4 :0> pins are configured as digital I/O on Rese t

bit 0 CCP2MX: CCP2 MUX bit

1 = CCP2 input/output is multiplexed with RC1

0 = CCP2 input/output is multiplexed with RB3

PIC18F2455/2550/4455/4550

R/P-1 R/P-0 R/P-0 U-0 U-0 R/P-1 U-0 R/P-1

DEBUG XINST ICPRT(1) ——LVP—STVREN

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

bit 6 XINST: Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5 ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)

1 = ICPORT enabled

0 = ICPORT disabled

bit 4-3 Unimplemented: Read as ‘0’

bit 2 LVP: Single-Supply ICSP™ Enable bit

1 = Single-Supply ICSP enabled

0 = Single-Supply ICSP disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 STVREN: Stack Full/Underflow Reset Enable bit

1 = Stack full/underflow will cause Reset

0 = Stack full/underflow will not cause Reset

Note 1: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all

other devices.

PIC18F2455/2550/4455/4550

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — —CP3

(1) CP2 CP1 CP0

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CP3: Code P rotecti on bit(1)

1 = Block 3 (006000-007FFFh) is not code-protected

0 = Block 3 (006000-007FFFh) is code- protect ed

bit 2 CP2: Code P rotecti on bit

1 = Block 2 (004000-005FFFh) is not code-protected

0 = Block 2 (004000-005FFFh) is code- protect ed

bit 1 CP1: Code P rotecti on bit

1 = Block 1 (002000-003FFFh) is not code-protected

0 = Block 1 (002000-003FFFh) is code-protected

bit 0 CP0: Code P rotecti on bit

1 = Block 0 (000800-001FFFh) is not code-protected

0 = Block 0 (000800-001FFFh) is code-protected

Note 1: Unimplement ed in PIC18FX455 devices; maintain this bit set.

R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

CPD CPB — — — — — —

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 CPD: Data EEPROM Code Protection bit

1 = Data EEPROM is not code-protected

0 = Data EEPROM is code-protected

bit 6 CPB: Boot Block Code Protection bit

1 = Boot block (000000-0007FFh) is not code-protected

0 = Boot block (000000-0007FFh) is code-protected

bit 5-0 Unimplemented: Read as ‘0’

PIC18F2455/2550/4455/4550

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — —WRT3

(1) WRT2 WRT1 WRT0

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRT3: Write Prote c tion bit(1)

1 = Block 3 (006000-007FFFh) is not write-protected

0 = Block 3 (006000-007FFFh ) is w rite-protected

bit 2 WRT2: Write Prote c tion bit

1 = Block 2 (004000-005FFFh) is not write-protected

0 = Block 2 (004000-005FFFh ) is w rite-protected

bit 1 WRT1: Write Pr otection bit

1 = Block 1 (002000-003FFFh) is not write-protected

0 = Block 1 (002000-003FFFh) is write-protected

bit 0 WRT0: Write Pr otection bit

1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not write-protected

0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is write-protected

Note 1: Unimplement ed in PIC18FX455 devices; maintain this bit set.

R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0

WRTD WRTB WRTC(1) — — — — —

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 WRTD: Data EEPROM Write Protection bit

1 = Data EEPROM is not write-protected

0 = Data EEPROM is write-protected

bit 6 WRTB: Boot Block Write Protection bit

1 = Boot block (000000-0007FFh) is not write-protected

0 = Boot block (000000-0007FFh) is write-protected

bit 5 WRTC: Configuration Register Write Protection bit(1)

1 = Configuration registers (300000-3000FFh) are not write-protected

0 = Configuration registers (300000-3000FFh) are write-protected

bit 4-0 Unimplemented: Read as ‘0’

Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.

PIC18F2455/2550/4455/4550

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — — EBTR3(1) EBTR2 EBTR1 EBTR0

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 Unimplemented: Read as ‘0’

bit 3 EBTR3: Table Read Protection bit(1)

1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks

0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks

bit 2 EBTR2: Table Read Protection bit

1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks

0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks

bit 1 EBTR1: Table Read Protection bit

1 = Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks

0 = Block 1 (002000-003FFFh) is protected from table reads executed in other blocks

bit 0 EBTR0: Table Read Protection bit

1 = Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks

0 = Block 0 (000800-001FFFh) is protected from table reads executed in other blocks

Note 1: Unimplement ed in PIC18FX455 devices; maintain this bit set.

U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

— EBTRB — — — — — —

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 Unimplemented: Read as ‘0’

bit 6 EBTRB: Boot Bl ock Table Read Protect ion bit

1 = Boot block (000000-0007FFh) is not protected from table reads executed in other blocks

0 = Boot block (000000-0007FFh) is protected from table reads executed in other blocks

bit 5-0 Unimplemented: Read as ‘0’

PIC18F2455/2550/4455/4550

RRRRRRRR

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-5 DEV2:DEV0: Device ID bits

011 = PIC18F2455

010 = PIC18F2550

001 = PIC18F4455

000 = PIC18F4550

bit 4-0 REV3:REV0: Revi si on ID bit s

These bits are used to indicate the device revision.

RRRRRRRR

DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1)

bit 7 bit 0

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-0 DEV10:DEV3: Device ID bits(1)

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number.

0001 0010 = PIC18F2455/2550/4455/4550 devices

Note 1: These values fo r DEV10 : DEV3 m ay be s hare d w i th o the r de vi ces . The speci f ic device is al w ay s identified

by using the entire DEV10:DEV0 bit sequence.

PIC18F2455/2550/4455/4550

25.2 Wat chdog Timer (WDT)

For PIC18F 245 5/2 550 /44 55/4 55 0 dev ic es , the WDT is

driven by the INTRC source. When the WDT is

enabled , the c lock sour ce is al so enable d. The nom inal

WDT period is 4 ms and has the same stability as the

INTRC osc il la tor.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in Configu-

ration Register 2H. Available periods range from 4 ms

to 131.072 seconds (2.18 minutes). The WDT and

post scaler are cleare d when any of the following events

occur: a SLEEP or CLRWDT instruction is executed, the

IRCF bits (OSCCON<6:4>) are changed or a clock

failure has occurred.

25.2.1 CONTROL REGISTER

Regi ste r 25-15 sh ow s t he WDT CON re gi s ter. This is a

readable and writab le re gis ter w h ic h co nt a ins a co ntro l

bit that allows software to override the WDT enable

Configuration bit, but only if the Configuration bit has

disabled the WDT.

FIGURE 25-1: WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: Changing the setting of the IRCF bits

(OSCCON<6:4>) clears the WDT and

postscaler counts.

3: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

INTRC Source

WDT

Wake-up from

Reset

WDT

WDT Counter

Program mabl e Pos tscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

Power-Managed

Reset

All Device Resets

SLEEP

INTRC Control

÷128

Change on IRC F bits Modes

PIC18F2455/2550/4455/4550

TABLE 25-2: SUMMARY OF WATCHDOG TIMER REGISTERS

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —SWDTEN

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)

1 = Watchdog Timer is on

0 = Watchdog Timer is off

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

RCON IPEN SBOREN(1) —RI TO PD POR BOR 52

WDTCON — — — — — — —SWDTEN52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.

PIC18F2455/2550/4455/4550

25.3 Two-Speed Start-up

The Two-Speed Start-up feature helps to minimize the

latency period, from oscillator start-up to code execu-

tion, by allowing the microcontroller to use the INTRC

oscillator as a clock source until the primary clock

source is available. It is enabled by setting the IESO

Configuration bit.

Two-Speed Start-up should be enabled only if the

primary oscillator mode is XT, HS, XTPLL or HSPLL

(Crystal-based modes). Other sources do not require

an OST start-up delay; for these, Two-Speed Start-up

should be disabled.

When ena bled, Resets and wake- ups from Sleep mode

cause the device to configure it self to run from the inter-

nal oscillator block as the clock source, following the

time-out of the Power-up T imer after a Power-on Res et

is enabled. This allows almost immediate code

execution while the primary oscillator starts and the

OST is running. Once the OST times out, the device

automatically switch es to PRI_RUN mode.

Because the OSCCON register is cleared on Reset

event s , the IN T O SC (or pos t s ca ler) clock source is not

initially available after a Reset event; the INTRC clock

is used directly at its base frequency. To use a higher

clock speed on wake-up, the INTOSC or postscaler

clock sour ces can be sele cted to provide a higher cloc k

speed by set ti ng bi ts, IR CF2: IRCF 0, im medi at ely aft er

Reset. For wake-ups from Sleep, the INTOSC or

postscaler clock sources can be selected by setting

IRCF2:IRCF0 prior to entering Sleep mode.

In all ot her power-managed modes, T wo-Speed S tart-up

is not used. The device will be clocked by the currently

selected clock source until the primary clock source

becomes available. The setting of the IESO bit is

ignored.

25.3.1 SPECIAL CONSIDERATIONS FOR

USING TWO-SPEED START-UP

While using the INTRC oscillator in T wo-Speed S tart-up,

the device still obeys the normal command sequences

for entering power-managed modes, including serial

SLEEP instructions (refer to Section 3.1.4 “Multiple

Sleep Commands”). In practice, this means that user

code can change the SCS1:SCS0 bit settings or issue

SLEEP instructions before the OST times out. This would

allow an application to briefly wake-up, perform routine

“housekeeping” tasks and return to Sleep before the

device starts to operate from the primary oscilla tor.

User code can a lso c heck if t he primar y clo ck s our ce i s

currently providing the devic e c loc ki ng by ch eck in g the

status of the OSTS bit (OSCCON<3>). If the bit is set,

the pr im ary osc il lat or i s p rovi di ng the clock . O the rw ise,

the internal oscillator block is providing the clock during

wake-up from Reset or Sleep mode.

FIGURE 25-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)

Q1 Q3 Q4

OSC1

Peripheral

Program PC PC + 2

INTOSC

PLL Clock

PC + 6

Output

Q3 Q4 Q1

CPU Clock

PC + 4

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

Wake from Interrupt Event

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition

Multiplexer

TOST(1)

PIC18F2455/2550/4455/4550

25.4 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the

microcontroller to continue operation in the event of an

external oscillator failure by automatically switching the

device clock to the internal oscillator block. The FSCM

function is ena bled b y s etting the FCMEN Configuration

bit.

When FSCM is enabled, the INTRC oscillator runs at

all times to monito r cl oc ks to peripherals and pr ov id e a

backup clock in the event of a clock failure. Clock

monitoring (shown in Figure 25-3) is accomplished by

crea ting a s ample clock signal, which i s the I NTRC o ut-

put divided by 64. This allows ample time between

FSCM sample clocks for a peripheral clock edge to

occur. The peripheral device clock and the sample

clock are present ed as inpu ts to the Clock Monitor latch

(CM). The CM is set on the falling edge of the device

clock source, but cleared on the rising edge of the

sample clock.

FIGURE 25-3: FSCM BLOCK DIAGRAM

Clock failure is tested for on the falling edge of the

sample clock. If a sample clock falling edge occurs

while CM is still set, a clock failure has been detected

(Figure 25-4). This causes the following:

• the FSCM generates an oscillator fail int erru pt by

setting bit, OSCFIF (PIR2<7>);

• the dev ice c lo ck s our ce is switc hed to th e internal

oscill ato r blo ck (O SCC ON i s not up dated to show

the current clock source – this is the fail-safe

condition); and

•the WDT is reset.

During switchover, the postscaler frequency from the

internal oscillator block may n ot be sufficiently st able for

timing sensitive applications. In these cases, it may be

desirable to select another cloc k configuration and enter

an alternate power-manag ed mode. This can be done to

attempt a partial recovery or execute a controlled shut-

down. See Section 3.1.4 “Multiple Sleep Commands”

and Section 25.3.1 “Special Considerations for

Using Two-Speed Start-up” for more detai ls.

To use a higher clock speed on wake-up, the INTOSC

or postscaler clock sources can be selected to provide

a higher clock speed by setting bits IRCF2:IRCF0

immediate ly a fter Reset. Fo r wak e-up s fro m Sle ep, th e

INTOSC or postscaler clock sources can be selected

by setting IRCF2:IRCF0 prior to entering Sleep mode.

The FS CM will dete ct failure s of the p rimary or sec ond-

ary clock sources only. If the internal oscillator block

fails, no failure would be detected, nor would any actio n

be possible.

25.4.1 FSCM AND THE W ATCHDOG TIMER

Both the FSCM and the WDT are clocked by the

INTRC oscillator. Since the WDT operates with a

separate divider and counter, disabling the WDT has

no ef fect on the op eration of the INTRC oscill ator when

the FSCM is enabled.

As already noted, the clock source is switched to the

INTOSC clock when a clock failure is detected.

Depending on the frequency selected by the

IRCF2:IRCF0 bits, this may mean a substantial change

in the speed of code execution. If the WDT is enabled

with a small prescale value, a decrease in clock speed

allows a WDT time-out to occur and a subsequent

device Reset. For this reason, Fail-Safe Clock Monitor

event s also res et the WDT and post scaler , all owing it to

start timing from when execution speed was changed

and dec reasing the li kelihood of an erroneou s time-out.

25.4.2 EXITING FAIL-SAFE OPERATION

The fail-safe condition is terminated by either a device

Reset or by entering a power-managed mode. On

Reset, the controller starts the primary clock source

specified in Configuration Register 1H (with any

start-up delays that are required for the oscillator mode,

such as OST or PLL timer). The INTOSC multiplexer

provi des the device clock until t he pri mary cl ock so urce

becomes ready (similar to a Two-Speed Start-up). The

clock source is then switched to the primary clock

(indicated by the OSTS bit in the OSCCON register

becoming set). The Fail-Safe Clock Monitor then

resumes monitoring the peripheral clock.

The primary clock source may never become ready

during st art-up. In this case, operatio n is clocked by the

INTOSC multiplexer . The OSCCON register will remain

in its Reset state until a power-managed mode is

entered.

Peripheral

INTRC ÷ 64

(32 μs) 488 Hz

(2.048 ms)

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Source

Clock

PIC18F2455/2550/4455/4550

FIGURE 25-4: FSCM TIMING DIAGRAM

25.4.3 FSCM INTERRUPTS IN

POWER-MANAGED MODES

By entering a power-managed mode, the clock

multiplexer selects the clock source selected by the

OSCCON register. Fail-Safe Clock Monitoring of the

power-managed clock source resumes in the

power-managed mode.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTOSC multiplexer. An automatic transition

back to the failed clock source will not occur.

If the interrupt is disabled, subsequent interrupts while

in Idle mode will cause the CPU to begin executing

instructions while being clocked by the INTOSC

source.

25.4.4 POR OR WAKE-UP FROM SLEEP

The FS CM is d esigned to de tect oscillato r failure at any

point after the device has exited Power-on Reset

(POR) or Low-Power Sleep mode. When the primary

device clock is either EC or INTRC, monitoring can

begin immediately following these events.

For oscillator modes involving a crystal or resonator

(HS, HSPLL or XT ), the situation is somewhat dif ferent.

Since the oscillator may require a start-up time con-

siderably longer than the FCSM sample clock time, a

false cl ock failu re may be dete cted. To preven t this, the

internal oscillator block is automatically configured as

the dev ice c lock and fu nctio ns unt il the prima ry clo ck i s

stable (the OST and PLL timers have timed out). This

is identical to Two-Speed Start-up mode. Once the

primary clo ck is stable, th e INTR C re turn s to its rol e a s

the FSCM source.

As noted in Section 25.3.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select ano ther clock confi guration and en ter an alternate

power-managed mode while waiting for the primary

clock to bec om e st a ble. Wh en the new power-manag ed

mode is s ele cted , the primary c loc k is dis abl ed.

OSCFIF

CM Output

Device

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this

example have been chosen for clarity.

(Q)

CM Test CM Test CM Test

Note: The sa me logi c tha t prevents false oscill a-

tor failure interrupts on POR or wake from

Sleep wi ll also preven t the detect ion of the

oscillator’s failure to start at all following

these events. This can be avoided by

monitoring the OSTS bit and using a

timing routine to determine if the oscillator

is taking too long to start. Even so, no

oscillator failure interrupt will be flagged.

PIC18F2455/2550/4455/4550

25.5 Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PIC® devices.

The user program memory is divided into five blocks.

One of these is a boot b lock of 2 Kb ytes. The remaind er

of the memory is divided into four blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 25-5 shows the program memory organization

for 24 and 32-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 25-3.

FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2455/2550/4455/4550

TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

300008h CONFIG5L ————CP3

(1) CP2 CP1 CP0

300009h CONFIG5H CPD CPB — — — — — —

30000Ah CONFIG6L ————WRT3

(1) WRT2 WRT1 WRT0

30000Bh CONFIG6H WRTD WRTB WRTC — — — — —

30000Ch CONFIG7L ———— EBTR3(1) EBTR2 EBTR1 EBTR0

30000Dh CONFIG7H — EBTRB — — — — — —

Legend: Shaded cells are uni mp lem en t ed .

Note 1: Unimplemented in PIC18FX455 devic es; maintain this bit set.

MEMORY SIZE/DEVICE Block Code Protection

Controlled By:

24 Kbytes

(PIC18F2455/2555) 32 Kbytes

(PIC18F2550/4550) Address

Range

Boot Block Boot Block 000000h

0007FFh CPB, WRTB, EBTRB

Block 0 Block 0 000800h

001FFFh CP0, WR T0 , EBTR0

Block 1 Block 1 002000h

003FFFh CP1, WR T1 , EBTR1

Block 2 Block 2 004000h

005FFFh CP2, WR T2 , EBTR2

Unimplemented

Read ‘0’s Block 3 006000h

007FFFh CP3, WR T3 , EBTR3

Unimplemented

Read ‘0’s Unimplemented

Read ‘0’s

008000h

1FFFFFh

(Unimplemented Memory Space)

PIC18F2455/2550/4455/4550

25.5.1 PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTn Configuration bit is ‘0’. The EBTRn

bits control table reads. For a block of user memory

with the EBTRn bit set to ‘0’, a table read instruction

that executes from within that block is allowed to read.

A table read instruction that executes from a location

outside of that block is not allowed to read and will

result in reading ‘0’s. Figures 25-6 through 25-8

illustrate table write and table read protection.

FIGURE 25-6: TABLE WRITE (WRTn) DISALLOWED

Note: Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

Chip Erase or Block Erase function. The

full Chip Erase and Block Erase functions

can only be initiat ed via IC SP operatio n or

an external programmer.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WRTB, EBTRB = 11

WR T0, EBTR0 = 01

WR T1, EBTR1 = 11

WR T2, EBTR2 = 11

WR T3, EBTR3 = 11

TBLWT*

TBLP T R = 0008 FFh

PC = 001FFEh

TBLWT*

PC = 005FFEh

Results: All table writes disabled to Blockn whenever WRTn = 0.

PIC18F2455/2550/4455/4550

FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

FIGURE 25-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLP T R = 0008 FFh

PC = 003FFEh

Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLP T R = 0008F Fh

PC = 001FFEh

Results: Table reads permitted within Blockn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

PIC18F2455/2550/4455/4550

25.5.2 DATA EEPROM

CODE PROTECTION

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits internal and external writes to data

EEPROM. The CPU can continue to read and write

data EEPROM regardless of the prote ction bit setti ngs.

25.5.3 CONFIGURATION REGISTER

PROTECTION

The Configuration registers can be write-protected.

The WRTC bit controls protection of the Configuration

registers. In normal execution mode, the WRTC bit is

readable only. WRTC can only be written via ICSP

operation or an external programmer.

25.6 ID Locations

Eight memory locations (200000h-200007h) are

designated as ID locations, where the user can store

checksum or other code identification numbers. These

locatio ns are b oth read abl e a nd w ri table durin g no rma l

execution through the TBLRD and TBLWT instructions

or du r ing p r ogr am / ve rif y. Th e ID lo cat io n s c a n be r e ad

when the de vice is code-protected.

25.7 In-Circuit Serial Programming

PIC18F2455/2550/4455/4550 microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data

and three other lines for power, ground and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

25.8 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This funct ion al lows s imple debug ging f unctio ns wh en

use d wi t h M PLA B® IDE. When the microcontroller has

this featu r e ena ble d, so me reso urc es are not av ail abl e

for gene ral us e. Table 25-4 show s whi ch res ource s are

required by the background debugger.

TABLE 25-4: DEBUGGER RESOURCES

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP/RE3, VDD,

VSS, RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip or one of

the third party develop m ent tool companies.

25.9 Special ICPORT Features

(Designated Packages Only)

Under specific circumstances, the No Connect (NC)

pins of PIC18F4455/4550 devices in 44-pin TQFP

packages can provide additional functionality. These

features are controlled by device Configu ration bits and

are available only in this package type and pin count.

25.9 .1 DEDICATED ICD/IC SP PORT

The 44-pin TQFP devices can use NC pins to provide

an alternate port for In-Circuit Debugging (ICD) and

In-Circuit Serial Programming (ICSP). These pins are

collectively known as the dedicated ICSP/ICD port,

since t hey are not sh ared with any o ther fun ction of the

device.

When implemented, the dedicated port activates three

NC pins to pro vide a n alte rnate de vice Reset, data an d

clock ports. None of these ports overlap with standard

I/O pins, making the I/O pins available to the user’s

application.

The dedicated ICSP/ICD port is enabled by setting the

ICPRT Configuration bit. The port functions the same

way as the legacy ICSP/ICD port on RB6/RB7.

Table 25-5 identifies the function ally equival ent pins for

ICSP and ICD purposes.

TABLE 25-5: EQUIVALENT PINS FOR

LEGACY AND DEDICATED

ICD/ICSP™ PORTS

I/O pins: RB 6, R B7

Stack: 2 leve ls

Program Memory: 512 bytes

Data Memory: 10 bytes

Pin Name Pin

Type Pin Functio n

Legacy

Port Dedicated

Port

MCLR/VPP/

RE3 NC/ICRST/

ICVPP P Device R eset and

Programming

Enable

RB6/KBI2/

PGC NC/ICCK/

ICPGC I Seria l Clo ck

RB7/KBI3/

PGD NC/ICDT/

ICPGD I/O Ser ial D ata

Legend: I = Input, O = Output, P = Power

PIC18F2455/2550/4455/4550

Even when the dedicated port is enabled, the ICSP and

ICD functi ons remain availab le through the legac y port.

When V IH is s een o n th e MC LR/VPP/RE3 pin , the sta te

of the ICRST/ICVPP pin is ignored.

25.9.2 28-PIN EMULATION

PIC18F4455/4550 devices in 44-pin TQFP packages

also have the ability to ch ange their configura tion under

external control for debugging purposes. This allows

the device to behave as if it were a PIC18F2455/2550

28-pin de vice.

This 28-pi n Configuration mo de is con trol led throu gh a

single pin, NC/ICPORTS. Connecting this pin to VSS

forces the device to function as a 28-pin device.

Features normally associated with the 40/44-pin

devices are disabled along with their corresponding

control registers and bits. This includes PORTD and

PORT E, the SPP and the Enhance d PWM fun ctionality

of CCP 1. On the o ther han d, conn ectin g the pi n to VDD

forces th e device to function in its default co nfigura tion.

The configuration option is only available when back-

ground debugging and the dedicated ICD/ICSP port

are both enabled (DEBUG Configuration bit is clear

and ICPRT Configuration bit is set). When disabled,

NC/ICPORTS is a No Connect pin.

25.10 Single-Supply ICSP Programming

The LVP Configuration bi t enab les Single-S upply ICSP

Programming (formerly known as Low-Voltage ICSP

Programming or LVP). When Single-Supply Program-

ming is enabled, the microcontroller can be

programmed without requiring high voltage being

applied to the MCLR/VPP/RE3 pin, but the

RB5/KBI1/PGM pin is then dedicated to controlling

Program mode entry and is not available as a general

purpose I/O pin.

While programming using Single-Supply Program-

ming, VDD is applied to the MCLR/VPP/RE3 pin as in

normal execution mode. To enter Programming mode,

VDD is applied to the PGM pin.

If Single-Supply ICSP Programming mode will not be

used, the LVP bit c an b e cl ear ed. R B5 /KBI1/PGM then

become s a vaila ble as the dig ita l I/O p in, RB 5. The LVP

bit may be set or cleared only when using standard

high-voltage programming (VIHH applied to the

MCLR/VPP/RE3 pin). Once LVP has been disabled,

only the standard high-voltage programming is

available and must be used to program the device.

Memory that is not code -protected ca n be erased usin g

either a Bloc k Erase, or erased row by row , the n written

at any s pecified VDD. If co de-protected m emory is to be

erase d, a Block Erase is required. If a Block Eras e is to

be performed when using Low-Voltage Programming,

the device must be supplied with VDD of 4.5V to 5.5V.

Note 1: The ICPRT Configuration bit can only be

programmed through the default ICSP

port.

2: The ICPRT Configuration bit must be

maintained clear for all 28-pin and 40-pin

devices; otherwise, unexpected operation

may occur.

Note 1: High-Voltage Programming is always

available, regardless of the state of the

LVP bit, by applying V IHH to the MCLR pin.

2: While in Lo w -Voltage IC SP Progra mmin g

mode, the RB5 pin c an no longe r be used

as a g eneral pu rpose I /O pin an d should

be held low during normal operation.

3: When using Low-Voltage ICSP Program-

ming (LVP) and the pull-ups on PORTB

are enabled, bit 5 in the TRISB register

must be cleared to disable the pull-up on

RB5 and ensure the proper operation of

the device.

4: If the device Master Clear is disabled,

verify that either of the following is done to

ensure proper entry into ICSP mode:

a) disable Low-Voltage Programming

(CONFIG4L<2> = 0); or

b) make certain that RB5/KBI1/PGM

is held low during entry into ICSP.

PIC18F2455/2550/4455/4550

26.0 INSTRUCTION SET SUMMARY

PIC18F2455/2550/4455/4550 devices incorporate the

standard set of 75 PIC18 core instructions, as well as

an extended set of eight new instructions for the

optimization of code that is recursive or that utilizes a

software stack. The extended set is discussed later in

this section.

26.1 Standard Instruction Set

The standard PIC18 instruction set adds many

enhancements to the previous PIC instruction sets,

while maintaining an easy migration from these PIC

instruction sets. Most instructions are a single program

memory word (16 bits) but there are four instructions

that require two program memory locations.

Each single-word instruction is a 16-bit word divided

into an o pcode, whi ch specifies the instructi on type and

one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal operati ons

•Control operations

The PIC18 instruction set summary in Table 26-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 26-1 shows the opcode field

descriptions.

Most byte-oriented in str uct ions have t hree op erands:

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which file

designator ‘d’ specifies where the result of the opera-

tion is to be placed. If ‘d’ is zero, the result is placed in

the WREG register. If ‘d’ is one, the result is placed in

the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

The bit field design ator ‘b’ sele cts the numb er of the bit

affected by the operation, while the file register

design ator ‘f’ represent s the numbe r of the fil e in w hich

the bit is located.

The literal ins truc tions may use so me of t he follo wing

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand requir ed

(specified by ‘—’)

The control instruct ions may u se some of t he followin g

operands:

• A program memory address (specified by ‘n’)

• The mode of the CALL or RETURN instruct ions

(specified by ‘s’)

• The mode of the table read and table write

ins tructions (specif ied by ‘m’)

• No operand requir ed

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bits. In the second word, the 4 MSbs are ‘1’s. If

this second word is executed as an instruction (by

it se lf), it will exe cu te as a NOP.

All single-word instructions are executed in a single

inst ruc tion c yc le , un le ss a conditional te st is true o r th e

program counter is changed as a result of the instruc-

tion. In th ese cases, the execution takes two i nstruction

cycles with the additional instruction cycle(s) executed

as a NOP.

The doub le-word inst ructions exe cute in two ins truction

cycles.

One in struction cycle consist s of f our oscil lator peri ods.

Thus, for an oscillator frequency of 4 MHz, the normal

inst ruction ex ecution ti me is 1 μs. If a cond itional tes t is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 μs.

Two-word branch instructions (if true) would take 3 μs.

Figur e 26-1 show s the gener al format s that the ins truc-

tions can have. All examples use the convention ‘nnh’

to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 26-2,

lists the standard instructions recognized by the

Microchip MPASMTM Assembler.

Section 26.1.1 “Standard Instruction Set” provides

a description of each instruction.

PIC18F2455/2550/4455/4550

TABLE 26-1: OPCODE FIELD DESCRIPTIONS

Field Description

aRAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb Bit address within an 8-bit file register (0 to 7).

BSR Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

dDestination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest Destination: either the WREG register or the specified register file location.

f8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

fs12-bit register file address (000h to FFFh). This is the source address.

fd12-bit register file address (000h to FFFh). This is the destination address.

GIE Global Interrupt Enable bit.

kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label Label name.

mm The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*No change to register (such as TBLPTR with table reads and writes)

*+ Post-Increment register (suc h as TBLPTR with table reads and writes)

*- Post-Decrement register (such as TBLPTR with table reads and writes)

+* Pre-Increment register (such as TBLPTR with table reads and writes)

nThe relative address (2’s complement number) for relative branch instructions or the direct address for

Call/Branch and Return instructions.

PC Program Counter.

PCL Program Counter Low Byte.

PCH Program Counter High Byte.

PCLATH Program Counter High Byte Latch.

PCLATU Program Counter Upper Byte Latch.

PD Power-Down bit.

PRODH Product of Multiply High Byte.

PRODL Product of Multiply Low Byte.

sFast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR 21-bit Table Pointer (points to a program memory location).

TABLAT 8-bit Table Latch.

TO Time-out bit.

TOS Top-of-Stack.

uUnused or unchanged.

WDT Watchdog Timer.

WREG Working register (accumulator).

xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the re comm ended form o f use for

compatibility with all Microchip software tools.

zs7-bit offset value for indirect addressing of register files (source).

zd7-bit offset value for indirect addressing of register files (destination).

{ } Optional argument.

[text] Indicates an indexed address.

(text) The contents of text.

[expr]<n> Specifies bit n of the register indicated by the pointer expr.

→Assigned to.

< > Register bit field.

∈In the set of.

italics User-defined term (font is Courier).

PIC18F2455/2550/4455/4550

FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG register

OPCODE d a f (FILE #)

d = 1 for result destina tion to be file register (f)

a = 0 to force Access Bank

Bit-oriented file register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in file register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bank

f = 8-bit file register address

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destination FILE #)

f = 12-bit file register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 7Fh

GOTO Label

15 8 7 0

OPCODE n<7:0> (literal)

15 12 11 0

1111 n<19:8> (literal)

CALL MYFUNC

15 11 10 0

OPCODE n<10:0> (literal)

S = Fast bit

BRA MYFUNC

15 8 7 0

OPCODE n<7:0> (literal) BC MYFUNC

PIC18F2455/2550/4455/4550

TABLE 26-2: PIC18FXXXX INSTRUCTION SET

Mnemonic,

Operands Description Cycles 16-Bit Inst ructio n Word Status

Affected Notes

MSb LSb

BYTE-ORIENT ED OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

COMF

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

INCFSZ

INFSNZ

IORWF

MOVF

MOVFF

MOVWF

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

SUBFWB

SUBWF

SUBWFB

SWAPF

TSTFSZ

XORWF

f, d, a

f, a

f, d, a

f, a

f, d, a

fs, fd

f, a

f, d, a

f, a

f, d, a

f, a

f, d, a

Add WREG and f

Add WREG and Carry bit to f

AND WREG with f

Clear f

Complement f

Compare f wit h W R EG, sk ip =

Compare f wit h W R EG, sk ip >

Compare f wit h W R EG, sk ip <

Decrem ent f

Decrement f, Skip if 0

Decrement f, Skip if Not 0

Increment f

Increment f, Skip if 0

Increment f, Skip if Not 0

Inclusive O R W R EG wi t h f

Move f

Move fs (source) to 1st word

fd (destination) 2nd word

Move WRE G to f

Multiply WREG with f

Negate f

Rotate Left f through Carry

Rotate Left f (No Carry)

Rotate Right f through Carry

Rotate Right f (No Carry)

Set f

Subtract f from WREG with

borrow

Subtract WREG from f

Subtract WREG from f with

borrow

Swap nibbles in f

Test f, skip if 0

Exclusive OR WREG with f

1 (2 or 3)

0010

0001

0110

0001

0110

0000

0010

0100

0010

0011

0100

0001

0101

1100

1111

0110

0000

0110

0011

0100

0011

0100

0110

0101

0011

0110

0001

01da

00da

01da

101a

11da

001a

010a

000a

01da

11da

10da

11da

10da

00da

ffff

111a

001a

110a

01da

00da

100a

01da

11da

10da

011a

10da

ffff

C, DC, Z, OV, N

Z, N

None

C, DC, Z, OV, N

None

C, DC, Z, OV, N

None

Z, N

None

C, DC, Z, OV, N

C, Z, N

Z, N

C, Z, N

Z, N

None

C, DC, Z, OV, N

None

Z, N

1, 2

1,2

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

Note 1: When a PORT register is mod i fied as a funct ion of itself (e.g . , MOVF PORTB, 1, 0), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configure d as an input an d is

driven low by an external device, the data will be written back with a ‘0’.

2: If this in st ru ct ion i s executed on the TMR 0 re gi st er (a nd w here app l icabl e, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If the Program Counter (PC) is modif ied or a condit io na l test i s true, the instruction requi r es two cycles . The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unles s t he f irst w or d of th e i nst r uct ion retrieves the inform a t io n em bedded i n these 16 bits. This ensures that al l

program memory locations have a valid instruction.

PIC18F2455/2550/4455/4550

BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a

f, d, a

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, S k ip if Set

Bit Toggle f

1 (2 or 3)

1001

1000

1011

1010

0111

bbba

ffff

None

1, 2

3, 4

1, 2

CONTROL OPERATIONS

BNC

BNN

BNOV

BNZ

BOV

BRA

CALL

CLRWDT

DAW

GOTO

NOP

POP

PUSH

RCALL

RESET

RETFIE

RETLW

RETURN

SLEEP

n, s

—

Branch if Carr y

Branch if Neg at i ve

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Ze ro

Branch if Ove rfl ow

Branch Unconditionally

Branch if Zero

Call subroutine 1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1 st word

2nd wo rd

No Operation

Pop top of return stack (TOS)

Push top of re tu rn stack (TOS)

Relative Call

Software device Reset

Return from interrupt enable

Return with literal in WREG

Return from Subroutine

Go into Standby mode

1 (2)

1110

1101

1110

1111

0000

1110

1111

0000

1111

0000

1101

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

1111

kkkk

0000

xxxx

0000

1nnn

0000

1100

0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

kkkk

0001

0000

nnnn

kkkk

0100

0111

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None

TO, PD

None

All

GIE/GIEH,

PEIE/GIEL

None

TO, PD

TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 16-Bit Inst ructio n Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is mod i fied as a funct ion of itself (e.g . , MOVF PORTB, 1, 0), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configure d as an input an d is

driven low by an external device, the data will be written back with a ‘0’.

2: If this in st ru ct ion i s executed on the TMR 0 r egi st er (a nd w here app l icabl e, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If the Program Counter (PC) is modif ied or a condit io na l test i s true, the instruction requi r es two cycles . The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unles s t he f irst w or d of th e i nst r uct ion retrieves the inform a t io n em bedded i n these 16 bits. This ensures that al l

program memory locations have a valid instruction.

PIC18F2455/2550/4455/4550

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

f, k

Add l i t eral and WREG

AND literal with WREG

Inclusive OR literal with WREG

Move liter al (1 2-b i t) 2nd word

to FSR(f) 1st wo rd

Move literal to BSR<3:0>

Move literal to WREG

Multiply lite ral with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

0000

1110

1111

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

00ff

kkkk

0000

kkkk

C, DC, Z, OV, N

Z, N

None

C, DC, Z, OV, N

Z, N

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Rea d

Table Rea d w ith post-increm ent

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-incr ement

Table Writ e w it h post-dec re me nt

Table Write with pr e- i ncr em ent

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 16-Bit Inst ructio n Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is mod i fied as a funct ion of itself (e.g . , MOVF PORTB, 1, 0), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configure d as an input an d is

driven low by an external device, the data will be written back with a ‘0’.

2: If this in st ru ct ion i s executed on the TMR 0 re gi st er (a nd w here app l icabl e, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If the Program Counter (PC) is modif ied or a condit io na l test i s true, the instruction requi r es two cycles . The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unles s t he f irst w or d of th e i nst r uct ion retrieves the inform a t io n em bedded i n these 16 bits. This ensures that al l

program memory locations have a valid instruction.

PIC18F2455/2550/4455/4550

26.1.1 STANDARD INSTRUCTION SET

ADDLW ADD Literal to W

Syntax: ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1111 kkkk kkkk

Description: The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proc ess

Data Wri te to W

Example: ADDLW 15h

Before Instruction

W = 10h

After Instruction

W = 25h

ADDWF ADD W to f

Syntax: ADDWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) + (f) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01da ffff ffff

Description: Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: ADDWF REG, 0, 0

Before Instruction

W = 17h

REG = 0C2h

After Instruction

W = 0D9h

REG = 0C2h

Note: All PIC18 instruc tions may t ake an op tional label arg ument, prec eding the instr uct ion mne monic, for u se in

symbolic addressing. If a label is used, the instruction format then becomes: {label} inst ruction argument(s).

PIC18F2455/2550/4455/4550

ADDWFC ADD W and Carry bit to f

Syntax: ADDWFC f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) + (f) + (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 00da ffff ffff

Description: Add W, the Carry flag and data memory

location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: ADDWFC REG, 0, 1

Before Instruction

Carry bit = 1

REG = 02h

W=4Dh

After Instruction

Carry bit = 0

REG = 02h

W = 50h

ANDLW AND Literal with W

Syntax: ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. k → W

Status Affected: N, Z

Encoding: 0000 1011 kkkk kkkk

Description: The contents of W are ANDed with the

8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ Process

Data Write to W

Example: ANDLW 05Fh

Before Instruction

W=A3h

After Instruction

W = 03h

PIC18F2455/2550/4455/4550

ANDWF AND W with f

Syntax: ANDWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .AND. (f) → dest

Status Affected: N, Z

Encoding: 0001 01da ffff ffff

Description: The contents of W are ANDed with

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: ANDWF REG, 0, 0

Before Instruction

W = 17h

REG = C2h

After Instruction

W = 02h

REG = C2h

BC Branch if Carry

Syntax: BC n

Operands: -128 ≤ n ≤ 127

Operation: if Carry bit is ‘1’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0010 nnnn nnnn

Description: If the Carry bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BC 5

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 1;

PC = address (HERE + 12)

If Carry = 0;

PC = address (HERE + 2)

PIC18F2455/2550/4455/4550

BCF Bit Clear f

Syntax: BCF f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 0 → f

Status Aff e cted: None

Encoding: 1001 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: BCF FLAG_REG, 7, 0

Before Instruction

FLAG_R EG = C7h

After Instruction

FLAG_REG = 47h

BN Branch if Negative

Syntax: BN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘1’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0110 nnnn nnnn

Description: If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 1;

PC = address (Jump)

If Negative = 0;

PC = address (HERE + 2)

PIC18F2455/2550/4455/4550

BNC Branch if Not Carry

Syntax: BNC n

Operands: -128 ≤ n ≤ 127

Operation: if Carry bit is ‘0’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0011 nnnn nnnn

Description: If the Carry bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. S ince the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNC Jump

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 0;

PC = address (Jump)

If Carry = 1;

PC = address (HERE + 2)

BNN Branch if Not Negative

Syntax: BNN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘0’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0111 nnnn nnnn

Description: If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 0;

PC = address (Jump)

If Negative = 1;

PC = address (HERE + 2)

PIC18F2455/2550/4455/4550

BNOV Branch if Not Overflow

Syntax: BNOV n

Operands: -128 ≤ n ≤ 127

Operation: if Overflow bit is ‘0’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0101 nnnn nnnn

Description: If the Overflow bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. S ince the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 0;

PC = address (Jump)

If Overflow = 1;

PC = address (HERE + 2)

BNZ Branch if Not Zero

Syntax: BNZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘0’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0001 nnnn nnnn

Description: If the Zero bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 0;

PC = address (Jump)

If Zero = 1;

PC = address (HERE + 2)

PIC18F2455/2550/4455/4550

BRA Unconditional Branch

Syntax: BRA n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1101 0nnn nnnn nnnn

Description: Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruct ion.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

Example: HERE BRA Jump

Before Instruction

PC = address (HERE)

After Instruction

PC = address (Jump)

BSF Bit Set f

Syntax: BSF f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 1 → f

Status Aff e cted: None

Encoding: 1000 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: BSF FLAG_REG, 7, 1

Before Instruction

FLAG_REG = 0Ah

After Instruction

FLAG_REG = 8Ah

PIC18F2455/2550/4455/4550

BTFSC Bit Tes t File, Sk ip if Clear

Syntax: BTFSC f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: skip if (f) = 0

Status Aff e cted: None

Encoding: 1011 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 26.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (TRUE)

If FLAG<1> = 1;

PC = address (FALSE)

BTFSS Bit Te s t Fi le , S k ip if Se t

Syntax: BTFSS f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation: skip if (f) = 1

Status Aff e cted: None

Encoding: 1010 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (FALSE)

If FLAG<1> = 1;

PC = address (TRUE)

PIC18F2455/2550/4455/4550

BTG Bit Toggle f

Syntax: BTG f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation: (f) → f

Status Aff e cted: None

Encoding: 0111 bbba ffff ffff

Description: Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: BTG PORTC, 4, 0

Before Instruction:

PORTC = 0111 0101 [75h]

After Instruc t ion:

PORTC = 0110 0101 [65h]

BOV Branch if O v e r flow

Syntax: BOV n

Operands: -128 ≤ n ≤ 127

Operation: if Overflow bit is ‘1’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0100 nnnn nnnn

Description: If the Overflow bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 1;

PC = address (Jump)

If Overflow = 0;

PC = address (HERE + 2)

PIC18F2455/2550/4455/4550

BZ Branch if Zero

Syntax: BZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘1’

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1110 0000 nnnn nnnn

Description: If the Zero bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. S ince the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 1;

PC = address (Jump)

If Zero = 0;

PC = address (HERE + 2)

CALL Subroutine Call

Syntax: CALL k {,s}

Operands: 0 ≤ k ≤ 1048575

s ∈ [0,1]

Operation: (PC) + 4 → TOS,

k → PC<20:1>,

if s = 1

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Status Aff e cted: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>) 1110

1111

110s

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description: Subroutine call of entire 2-Mbyt e

memory range. First, return address

(PC + 4) is pushed onto the return

stack. If ‘s’ = 1, the W, STATUS and

BSR

registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs (default). Then, the

20-bit value ‘k’ is loaded into PC<20:1>.

CALL is a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>, Push PC to

stack Read literal

‘k’<19:8>,

Write to PC

operation No

operation

Example: HERE CALL THERE,1

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 4)

WS = W

BSRS = BSR

STATUSS = STATUS

PIC18F2455/2550/4455/4550

CLRF Clear f

Syntax: CLRF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: 000h → f,

1 → Z

Status Aff ected: Z

Encoding: 0110 101a ffff ffff

Description: Clears the contents of the specified

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: CLRF FLAG_REG,1

Before Instruction

FLAG_REG = 5Ah

After Instruction

FLAG_REG = 00h

CLRWDT Clear Watchdog Timer

Syntax: CLRWDT

Operands: None

Operation: 000h → WDT,

000h → WDT postscaler,

1 → TO,

1 → PD

Status Aff ected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits, TO

and PD, are set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data No

operation

Example: CLRWDT

Before Instruction

WDT Counter = ?

After Instruction

WDT Counter = 00h

WDT Postscaler = 0

TO =1

PD =1

PIC18F2455/2550/4455/4550

COMF Complement f

Syntax: COMF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) → dest

Status Affected: N, Z

Encoding: 0001 11da ffff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: COMF REG, 0, 0

Before Instruction

REG = 13h

After Instruction

REG = 13h

W=ECh

CPFSEQ Compare f with W, Skip if f = W

Syntax: CPFSEQ f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) = (W)

(unsigned comparison)

Status Aff e cted: None

Encoding: 0110 001a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE CPFSEQ REG, 0

NEQUAL :

EQUAL :

Before Instruction

PC Address = HERE

W=?

REG = ?

After Instruction

If REG = W;

PC = Address (EQUAL)

If REG ≠ W;

PC = Address (NEQUAL)

PIC18F2455/2550/4455/4550

CPFSGT Compare f with W, Skip if f > W

Syntax: CPFSGT f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) > (W)

(unsigned comparison)

Status Aff e cted: None

Encoding: 0110 010a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruct ion.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG > W;

PC = Address (GREATER)

If REG ≤ W;

PC = Address (NGREATER)

CPFSLT Compare f with W, Skip if f < W

Syntax: CPFSLT f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) < (W)

(unsigned comparison)

Status Aff e cted: None

Encoding: 0110 000a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruct ion.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG < W;

PC = Address (LESS)

If REG ≥ W;

PC = Address (NLESS)

PIC18F2455/2550/4455/4550

DAW Decimal Adjust W Register

Syntax: DAW

Operands: None

Operation: If [W<3:0> > 9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

(W<3:0>) → W<3:0>

If [W <7:4> + DC > 9] or [C = 1] the n

(W<7:4>) + 6 + DC → W<7:4>;

else

(W<7:4>) + DC → W<7:4>

Status Aff ected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example 1: DAW

Before Instruction

W=A5h

C=0

DC = 0

After Instruction

W = 05h

C=1

DC = 0

Example 2:

Before Instruction

W=CEh

C=0

DC = 0

After Instruction

W = 34h

C=1

DC = 0

DECF Decrement f

Syntax: DECF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest

Status Affected: C, DC, N, OV, Z

Encoding: 0000 01da ffff ffff

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: DECF CNT, 1, 0

Before Instruction

CNT = 01h

Z=0

After Instruction

CNT = 00h

Z=1

PIC18F2455/2550/4455/4550

DECFSZ Decrement f, Skip if 0

Syntax: DECFSZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest,

skip if result = 0

Status Aff e cted: None

Encoding: 0010 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT – 1

If CNT = 0;

PC = Address (CONTINUE)

If CNT ≠0;

PC = Address (HERE + 2)

DCFSNZ Decremen t f, Skip if Not 0

Syntax: DCFSNZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest,

skip if result ≠ 0

Status Aff e cted: None

Encoding: 0100 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE DCFSNZ TEMP, 1, 0

ZERO :

NZERO :

Before Instruction

TEMP = ?

After Instruction

TEMP = T EM P – 1,

If TEMP = 0;

PC = Address (ZERO)

If TEMP ≠0;

PC = Address (NZERO)

PIC18F2455/2550/4455/4550

GOTO Unc onditional Branch

Syntax: GOTO k

Operands: 0 ≤ k ≤ 1048575

Operation: k → PC<20:1>

Status Aff e cted: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>) 1110

1111

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description: GOTO allows an unconditional branch

anywhere within the entire

2-Mbyte memory range. The 20-bit

value ‘k’ is loaded into PC<20:1>. GOTO

is always a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>, No

operation Read literal

‘k’<19:8>,

Write to PC

operation No

operation

Example: GOTO THERE

After Instruction

PC = Address (THERE)

INCF Increment f

Syntax: INCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest

Status Affected: C, DC, N, OV, Z

Encoding: 0010 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: INCF CNT, 1, 0

Before Instruction

CNT = FFh

Z=0

C=?

DC = ?

After Instruction

CNT = 00h

Z=1

C=1

DC = 1

PIC18F2455/2550/4455/4550

INCFSZ Increment f, Skip if 0

Syntax: INCFSZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest,

skip if result = 0

Status Aff e cted: None

Encoding: 0011 11da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’. (default)

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE INCFSZ CNT, 1, 0

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC = Address (ZERO)

If CNT ≠0;

PC = Address (NZERO)

INFSNZ Increment f, Skip if Not 0

Syntax: INFSNZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest,

skip if result ≠ 0

Status Aff e cted: None

Encoding: 0100 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE INFSNZ REG, 1, 0

ZERO

NZERO

Before Instruction

PC = Address (HERE)

After Instruction

REG = REG + 1

If REG ≠0;

PC = Address (NZERO)

If REG = 0;

PC = Address (ZERO)

PIC18F2455/2550/4455/4550

IORLW Inclusiv e OR Lite ra l wit h W

Syntax: IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → W

Status Affected: N, Z

Encoding: 0000 1001 kkkk kkkk

Description: The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Wri te to W

Example: IORLW 35h

Before Instruction

W=9Ah

After Instruction

W=BFh

IOR WF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .OR. (f) → dest

Status Affected: N, Z

Encoding: 0001 00da ffff ffff

Description: Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f ’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: IORWF RESULT, 0, 1

Before Instruction

RESULT = 13h

W = 91h

After Instruction

RESULT = 13h

W = 93h

PIC18F2455/2550/4455/4550

LFS R L oad FS R

Syntax: LF SR f, k

Operands: 0 ≤ f ≤ 2

0 ≤ k ≤ 4095

Operation: k → FSRf

Status Aff e cted: None

Encoding: 1110

1111

1110

0000

00ff

k7kkk

k11kkk

kkkk

Description: The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ MSB Process

Data Write

literal ‘k’ MSB

to FSR fH

Decode Read literal

‘k’ LSB Process

Data Write literal ‘k’

to FSRfL

Example: LFSR 2, 3ABh

After Instruction

FSR2H = 03h

FSR2L = ABh

MOVF Move f

Syntax: MOVF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: f → dest

Status Affected: N, Z

Encoding: 0101 00da ffff ffff

Description: The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write W

Example: MOVF REG, 0, 0

Before Instruction

REG = 22h

W=FFh

After Instruction

REG = 22h

W = 22h

PIC18F2455/2550/4455/4550

MOVFF Move f to f

Syntax: MOVFF fs,fd

Operands: 0 ≤ fs ≤ 4095

0 ≤ fd ≤ 4095

Operation: (fs) → fd

Status Aff e cted: None

Encoding:

1st word (source)

2nd word (destin.) 1100

1111

ffff

ffffs

ffffd

Description: The contents of source register ‘fs’ are

moved to destination register ‘fd’.

Location of source ‘f s’ can be anywhere

in the 4096-byte data space (000h to

FFFh) and location of destination ‘fd’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

MOVFF is particularly useful for

transferring a dat a memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

(src)

Process

Data No

operation

Decode No

operation

No dummy

read

operation Write

(dest)

Example: MOVFF REG1, REG2

Before Instruction

REG1 = 33h

REG2 = 11h

After Instruction

REG1 = 33h

REG2 = 33h

MOVLB Move Literal to Low Nibble in BSR

Syntax: MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → BSR

Status Aff e cted: None

Encoding: 0000 0001 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value

of BSR<7:4> always remains ‘0’

regardless of the value of k7:k4.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proc ess

Data Write litera l

‘k’ to BSR

Example: MOVLB 5

Before Instruction

BSR Register = 02h

After Instruction

BSR Register = 05h

PIC18F2455/2550/4455/4550

MOVLW M ov e Lite ral to W

Syntax: MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → W

Status Aff e cted: None

Encoding: 0000 1110 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ P rocess

Data Write to W

Example: MOVLW 5Ah

After Instruction

W=5Ah

MOVWF Move W to f

Syntax: MOVWF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1 ]

Operation: (W ) → f

Status Aff e cted: None

Encoding: 0110 111a ffff ffff

Description: Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, t he BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index ed

Literal Offset Mode ” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: MOVWF REG, 0

Before Instruction

W=4Fh

REG = FFh

After Instruction

W=4Fh

REG = 4Fh

PIC18F2455/2550/4455/4550

MULLW M ultipl y Literal with W

Syntax: MULLW k

Operands: 0 ≤ k ≤ 255

Operation: (W ) x k → PR O DH : PR O DL

Status Aff e cted: None

Encoding: 0000 1101 kkkk kkkk

Description: An unsigned mu ltiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in PRODH:PRODL register pair .

PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A zero result

is possible but not detected.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write

registers

PRODH:

PRODL

Example: MULLW 0C4h

Before Instruction

W=E2h

PRODH = ?

PRODL = ?

After Instruction

W=E2h

PRODH = ADh

PRODL = 08h

MULWF M ultiply W with f

Syntax: MULWF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (W) x (f) → PRODH:PRODL

Status Aff e cted: None

Encoding: 0000 001a ffff ffff

Description: An unsigned multiplication is carried

out between the contents of W and the

result is stored in the PRODH:PRODL

high byte. Both W and ‘f’ are

unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A zero

result is possible but not detected.

If ‘a’ is ‘0’, the Access Ban k is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 26.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

registers

PRODH:

PRODL

Example: MULWF REG, 1

Before Instruction

W=C4h

REG = B5h

PRODH = ?

PRODL = ?

After Instruction

W=C4h

REG = B5h

PRODH = 8Ah

PRODL = 94h

PIC18F2455/2550/4455/4550

NEGF Negate f

Syntax: NEGF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) + 1 → f

Status Affected: N, OV, C, DC, Z

Encoding: 0110 110a ffff ffff

Description: Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: NEGF REG, 1

Before Instruction

REG = 0011 1010 [3Ah]

After Instruction

REG = 1100 0110 [C6h]

NOP No Operation

Syntax: NOP

Operands: None

Operation: No operation

Status Aff e cted: None

Encoding: 0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

Description: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation

Example:

None.

PIC18F2455/2550/4455/4550

POP Pop Top of Return Stack

Syntax: POP

Operands: None

Operation: (TOS) → bit bu cket

Status Aff e cted: None

Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Pop TOS

value No

operation

Example: POP

GOTO NEW

Before Instruction

TOS = 0031A2h

Stack (1 level down) = 014332h

After Instruction

TOS = 014332h

PC = NEW

PUSH Push Top of Return Stack

Syntax: PUSH

Operands: None

Operation: (PC + 2) → TOS

Status Aff e cted: None

Encoding: 0000 0000 0000 0101

Description: The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Push PC + 2

onto return

stack

operation No

operation

Example: PUSH

Before Instruction

TOS = 345Ah

PC = 0124h

After Instruction

PC = 0126h

TOS = 0126h

Stack (1 level down) = 345Ah

PIC18F2455/2550/4455/4550

RCALL Relative Call

Syntax: RCALL n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 → TOS,

(PC) + 2 + 2n → PC

Status Aff e cted: None

Encoding: 1101 1nnn nnnn nnnn

Description: Subrout ine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number ‘2n’ to the PC. S ince the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruct ion.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Push PC to

stack

Process

Data Write to PC

operation No

operation

Example: HERE RCALL Jump

Before Instruction

PC = Address (HERE)

After Instruction

PC = Address (Jump)

TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are

affected by a MCLR Reset.

Status Aff ected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to

execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Start

Reset No

operation No

operation

Example: RESET

After Instruction

Registers = Reset Value

Flags* = Reset Value

PIC18F2455/2550/4455/4550

RETFIE Return from Interrupt

Syntax: RETFIE {s}

Operands: s ∈ [0,1]

Operation: (TOS) → PC,

1 → GIE/GI EH o r PEIE/GIEL,

if s = 1

(WS) → W,

(STATUSS) → STATUS ,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped

and Top-of- Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers WS,

STATUSS and BSRS are loaded into

their corresponding registers, W,

STATUS and BSR. If ‘s’ = 0, no update

of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation Pop PC from

stack

Set GIEH or

GIEL

operation No

operation

Example: RETFIE 1

After Interrupt

PC = TOS

W=WS

BSR = BSRS

STATUS = STATUSS

GIE/ GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax: RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → W,

(TOS) → PC,

PCLATU, PCLATH are unchanged

Status Aff e cted: None

Encoding: 0000 1100 kkkk kkkk

Description: W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proc ess

Data Pop PC from

stack, Write

to W

operation No

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL ; W = offset

RETLW k0 ; Begin table

RETLW k1 ;

RETLW kn ; End of table

Before Instruction

W = 07h

After Instruction

W = value of kn

PIC18F2455/2550/4455/4550

RETURN Return from Subroutine

Syntax: RETURN {s}

Operands: s ∈ [0,1]

Operation: (TOS) → PC,

if s = 1

(WS) → W,

(STATUSS) → STAT US,

(BSRS) → BSR ,

PCLATU, PCLATH are unchanged

Status Aff e cted: None

Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers WS, STATUSS and BSRS are

loaded into their corresponding

registers, W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data Pop PC

from stack

operation No

operation

Example: RETURN

After Instruc t ion:

PC = TOS

RLCF Rot ate Left f through Carry

Syntax: RLCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n + 1>,

(f<7>) → C,

Status Affected: C, N, Z

Encoding: 0011 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5F h). See Section 26.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: RLCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=1100 1100

C=1

Cregister f

PIC18F2455/2550/4455/4550

RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n + 1>,

(f<7>) → dest<0>

Status Affected: N, Z

Encoding: 0100 01da ffff ffff

Description: T he conte nts of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the resu lt is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh ). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructi ons in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: RLNCF REG, 1, 0

Before Instruction

REG = 1010 1011

After Instruction

REG = 0101 0111

RRCF Rotate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n – 1>,

(f<0>) → C,

Status Affected: C, N, Z

Encoding: 0011 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: RRCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=0111 0011

C=0

Cregister f

PIC18F2455/2550/4455/4550

RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n – 1>,

(f<0>) → dest<7>

Status Affected: N, Z

Encoding: 0100 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: RRNCF REG, 1, 0

Before Instruction

REG = 1101 0111

After Instruction

REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction

W=?

REG = 1101 0111

After Instruction

W=1110 1011

REG = 1101 0111

SETF Set f

Syntax: SETF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: FFh → f

Status Aff e cted: None

Encoding: 0110 100a ffff ffff

Description: The contents of the specified register

are set to FFh.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: SETF REG,1

Before Instruction

REG = 5Ah

After Instruction

REG = FFh

PIC18F2455/2550/4455/4550

SLEEP Enter Sleep m o d e

Syntax: SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT postscaler,

1 → TO ,

0 → PD

Status Aff ected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. Watchdog T imer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data Go to

Sleep

Example: SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake- up, this bit is cleared.

SUBFWB Subtract f from W with Borrow

Syntax: SUBFWB f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) – (f) – (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 01da ffff ffff

Description: Subtract register ‘f’ and Carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and t he extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 26.2.3

“Byte-Oriented and Bit-Oriented

Instruct ions in In dexed Literal O ffset

Mode” f or details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: SUBFWB REG, 1, 0

Before Instruction

REG = 3

W=2

C=1

After Instruction

REG = FF

W=2

C=0

Z=0

N = 1 ; result is negative

Example 2: SUBFWB REG, 0, 0

Before Instruction

REG = 2

W=5

C=1

After Instruction

REG = 2

W=3

C=1

Z=0

N = 0 ; result is positive

Example 3: SUBFWB REG, 1, 0

Before Instruction

REG = 1

W=2

C=0

After Instruction

REG = 0

W=2

C=1

Z = 1 ; result is zero

N=0

PIC18F2455/2550/4455/4550

SUBLW Subtract W from Literal

Syntax: SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k – (W) → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1000 kkkk kkkk

Description W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proc ess

Data Wri te to W

Example 1: SUBLW 02h

Before Instruction

W = 01h

C=?

After Instruction

W = 01h

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBLW 02h

Before Instruction

W = 02h

C=?

After Instruction

W = 00h

C = 1 ; result is zero

Z=1

N=0

Example 3: SUBLW 02h

Before Instruction

W = 03h

C=?

After Instruction

W = FFh ; (2’s complement)

C = 0 ; result is negative

Z=0

N=1

SUBWF Subtract W from f

Syntax: SUB W F f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – (W) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 11da ffff ffff

Description: Subt rac t W f rom register ‘f ’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and t he extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 26.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” f or details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: SUBWF REG, 1, 0

Before Instruction

REG = 3

W=2

C=?

After Instruction

REG = 1

W=2

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBWF REG, 0, 0

Before Instruction

REG = 2

W=2

C=?

After Instruction

REG = 2

W=0

C = 1 ; result is zero

Z=1

N=0

Example 3: SUBWF REG, 1, 0

Before Instruction

REG = 1

W=2

C=?

After Instruction

REG = FFh ;(2’s complement)

W=2

C = 0 ; result is negative

Z=0

N=1

PIC18F2455/2550/4455/4550

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – (W) – (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 10da ffff ffff

Description: Subt ract W and the Carry flag (borrow)

from register ‘f’ (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: SUBWFB REG, 1, 0

Before Instruction

REG = 19h (0001 1001)

W=0Dh (0000 1101)

C=1

After Instruction

REG = 0Ch (0000 1011)

W=0Dh (0000 1101)

C=1

Z=0

N = 0 ; result is positive

Example 2: SUBWFB REG, 0, 0

Before Instruction

REG = 1Bh (0001 1011)

W=1Ah (0001 1010)

C=0

After Instruction

REG = 1Bh (0001 1011)

W = 00h

C=1

Z = 1 ; resu l t is zero

N=0

Example 3: SUBWFB REG, 1, 0

Before Instruction

REG = 03h (0000 0011)

W=0Eh (0000 1101)

C=1

After Instruction

REG = F5h (1111 0100)

; [2’s co mp]

W=0Eh (0000 1101)

C=0

Z=0

N = 1 ; result is negative

SW APF Swap f

Syntax: SWAPF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Status Aff e cted: None

Encoding: 0011 10da ffff ffff

Description: The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: SWAPF REG, 1, 0

Before Instruction

REG = 53h

After Instruction

REG = 35h

PIC18F2455/2550/4455/4550

TBLRD Table Read

Syntax: TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR – No Change;

if TBLRD *+

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) + 1 → TBLPTR;

if TBLRD *-

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) – 1 → TBLPTR;

if TBLRD +*

(TBLPTR) + 1 → TBLPTR;

(Prog Mem (TBLPTR)) → TABLAT

Status Aff e cted: None

Encoding: 0000 0000 0000 10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLP TR[ 0] = 0: Least Significant Byte

of Program Memory

Word

TBLP TR[ 0] = 1: Most Significant Byte

of Program Memory

Word

The TBLRD instruction can modify the value

of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation

operation No oper atio n

(Read Program

Memory)

operation No operation

(Write

TABLAT)

TBLRD Table Read (Continued)

Example 1: TBLRD *+ ;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

MEMORY (00A356h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 00A357h

Example 2: TBLRD +* ;

Before Instruction

TABLAT = AAh

TBLPTR = 01A357h

MEMORY (01A357h) = 12h

MEMORY (01A358h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 01A358h

PIC18F2455/2550/4455/4550

TBLWT Table Write

Syntax: TBLWT ( *; *+; *-; +*)

Operands: None

Operation: if TBLWT*

(TABLAT) → Holding Register;

TBLPTR – No Change;

if TBLWT*+

(TABLAT) → Holding Register;

(TBLPTR) + 1 → TB L PT R ;

if TBLWT*-

(TABLAT) → Holding Register;

(TBLPTR) – 1 → TBL PT R ;

if TBLWT+*

(TBLPTR) + 1 → TB L PT R ;

(TABLAT) → Holding Register

Status Aff e cted: None

Encoding: 0000 0000 0000 11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction uses the 3 LSBs of TBLPTR

to determine which of the

8 holding registers the T ABLAT is written to.

The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 6.0

“Flash Program Memory” for additional

details on programming Flash memory.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range. The LSb of

the TBLPTR selects which byte of the

program memory location to access.

TBLPTR[0] = 0: Least Significant

Byte of Prog ram

Memory Word

TBLPTR[0] = 1: Mos t Significant

Byte of Prog ram

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity: Q1 Q2 Q3 Q4

Decode No

operation No

operation

operation No

operation

(Read

TABLAT)

operation No

operation

(Write to

Holding

TBLWT Table Write (Continued)

Example 1: TBLWT *+;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

HOLD ING REGIST ER

(00A356h) = FFh

After Instructions (table write completion)

TABLAT = 55h

TBLPTR = 00A357h

HOLD ING REGIST ER

(00A356h) = 55h

Example 2: TBLWT +*;

Before Instruction

TABLAT = 34h

TBLPTR = 01389Ah

HOLD ING REGIST ER

(01389Ah) = FFh

HOLD ING REGIST ER

(01389Bh) = FFh

After Instruction (table write completion)

TABLAT = 34h

TBLPTR = 01389Bh

HOLD ING REGIST ER

(01389Ah) = FFh

HOLD ING REGIST ER

(01389Bh) = 34h

PIC18F2455/2550/4455/4550

TST FSZ Test f, S k ip if 0

Syntax: TSTFSZ f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: skip if f = 0

Status Aff e cted: None

Encoding: 0110 011a ffff ffff

Description: If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE TSTFSZ CNT, 1

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h,

PC = Address (ZERO)

If CNT ≠00h,

PC = Address (NZERO)

XORLW Exclu sive OR Literal with W

Syntax: XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → W

Status Affected: N, Z

Encoding: 0000 1010 kkkk kkkk

Description: T he contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proc ess

Data Write to W

Example: XORLW 0AFh

Before Instruction

W=B5h

After Instruction

W=1Ah

PIC18F2455/2550/4455/4550

XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .XOR. (f) → dest

Status Affected: N, Z

Encoding: 0001 10da ffff ffff

Description: Exclusive OR the contents of W with

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 26.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: XORWF REG, 1, 0

Before Instruction

REG = AFh

W=B5h

After Instruction

REG = 1Ah

W=B5h

PIC18F2455/2550/4455/4550

26.2 Extended Instruction Set

In additi on to t he s t an dard 75 i nst ruc tions of the PIC18

instruction set, PIC18F2455/2550/4455/4550 devices

also provide an optional extension to the core CPU

functionality. The added features include eight addi-

tional instructions that augment Indirect and Indexed

Addressing operations and the implementation of

Indexed Literal Of fset Addressing mo de for many of the

standard PIC18 instructions.

The additional features of the extended instruction set

are d isabled by defa ult. To enable t hem, users m ust set

the XINST Configuration bit.

The instructions in the extended set can all be

class ified as literal operation s, which eith er manip ulate

the File Select Registers, or use them for Indexed

Addressing. Two of the instructions, ADDFSR and

SUBFSR, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK) allow for automatic return after execution.

The exte nded instr uctions are s pecifically im plemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

• Dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• Function Pointer invocation

• Software Stack Pointer manipulation

• Manipulation of variables located in a software

stack

A summary of the instructions in the extended instruc-

tion set is provide d in Table 26-3. Det aile d descr iption s

are pro vided in Section 26.2.2 “Extended Instruction

Set”. The opcode field descriptions in Table 26-1

(page 308) apply to both the standard and extended

PIC18 instruction sets.

26.2.1 EXTENDED INSTRU CTION SYNTAX

Most of the extended instructions use indexed

arguments, using one of the File Select Registers and

some offset to specify a source or destination register.

When an argument for an instruction serves as part of

Indexed Addressing, it is enclosed in square brackets

(“[ ]”). This is done to in dicate that the argument is used

as an index or offset. The MPASM™ Assembler will

flag an error if it determines that an index or offset value

is not bracketed.

When the ex tended ins truction s et is enabled, bra cket s

are also used to indicate index arguments in byte-

oriented and bit-orient ed instructions. This is in addition

to other changes in their syntax. For more details, see

Section 26.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note: The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is pro-

vided as a reference for u sers who may b e

reviewing code that has been generated

by a compiler.

Note: In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected

MSb LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add literal to FSR

Add literal to FSR2 and return

Call subroutine using WREG

Move zs (source) to 1st word

fd (destination) 2nd word

Move zs (source) to 1st word

zd (destination) 2nd word

Store liter al at FSR2,

decrement FSR2

Subtract literal from FSR

Subtract literal from FSR2 and

return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

PIC18F2455/2550/4455/4550

26.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR

Syntax: ADDFSR f, k

Operands: 0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

Operation: FSR(f) + k → FSR(f)

Status Aff ected: None

Encoding: 1110 1000 ffkk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of the FSR specified by ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ P rocess

Data Write to

FSR

Example: ADDFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 0422h

ADDULNK Ad d L it e ra l t o F SR 2 a n d R eturn

Syntax: ADDULNK k

Operands: 0 ≤ k ≤ 63

Operation: FSR2 + k → FSR2,

(TOS) → PC

Status Aff e cted: None

Encoding: 1110 1000 11kk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURN is then

executed by loading the PC with the

TOS.

The instruction takes two cycles to

execute; a NOP is performed during

the second cycle.

This may be thought of as a special

case of the ADDFSR instruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Wri te to

FSR

Operation No

Operation

Example: ADDULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 0422h

PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

PIC18F2455/2550/4455/4550

CALLW Subroutine Call Using WREG

Syntax: CALLW

Operands: None

Operation: (PC + 2) → TOS,

(W) → PCL,

(PCLATH) → PCH,

(PCLATU) → PCU

Status Aff e cted: None

Encoding: 0000 0000 0001 0100

Description First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOP instruction while the

new next instruction is fetched.

Unlike CALL, there is no option to

update W, STATUS or BSR.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

WREG Push PC to

stack No

operation

operation No

operation

Example: HERE CALLW

Before Instruction

PC = address (HERE)

PCLATH = 10h

PCLATU = 00h

W = 06h

After Instruction

PC = 001006h

TOS = address (HERE + 2)

PCLATH = 10h

PCLATU = 00h

W = 06h

MOV S F Move Indexed to f

Syntax: MOVSF [zs], fd

Operands: 0 ≤ zs ≤ 127

0 ≤ fd ≤ 4095

Operation: ((FSR2) + zs) → fd

Status Aff e cted: None

Encoding:

1st word (source)

2nd word (destin.) 1110

1111

1011

ffff

0zzz

ffff

zzzzs

ffffd

Description: The contents of the source register are

moved to destination register ‘fd’. The

actual address of the source register is

determined by adding the 7-bit literal

offset ‘zs’ in the first word to the value of

FSR2. The address of the destination

‘fd’ in the second word. Both addresses

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr Determine

source addr Read

source reg

Decode No

operation

No dummy

read

operation Write

(dest)

Example: MOVSF [05h], REG2

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 33h

PIC18F2455/2550/4455/4550

MOVSS Move Indexed to Indexed

Syntax: MOVSS [zs], [zd]

Operands: 0 ≤ zs ≤ 127

0 ≤ zd ≤ 127

Operation: ((FSR2) + zs) → ((FSR 2) + zd)

Status Aff e cted: None

Encoding:

1st word (source)

2nd word (dest.) 1110

1111

1011

xxxx

1zzz

xzzz

zzzzs

zzzzd

Description The contents of the source register are

moved to the destination register . The

addresses of the source and destination

registers are determined by adding the

7-bit literal offset s ‘zs’ or ‘zd’,

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

The MOVSS instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr Determine

source addr Read

source reg

Decode Determine

dest addr Determine

dest addr Write

to dest reg

Example: MOVSS [05h], [06h]

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 33h

PUSHL

Stor e Literal at FS R2, Decrement FSR 2

Syntax: PUSHL k

Operands: 0 ≤ k ≤ 255

Operation: k → (FSR2),

FSR2 – 1→ FSR2

S t at us Af fect ed: None

Encoding: 1111 1010 kkkk kkkk

Description: The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2

is decremented by ‘1’ after the operation.

This instruction allows users to push values

onto a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

data Write to

destination

Example: PUSHL 08h

Before Instruction

FSR2H:FSR2L = 01ECh

Memory (01ECh) = 00h

After Instruction

FSR2H:FSR2L = 01EBh

Memory (01ECh) = 08h

PIC18F2455/2550/4455/4550

SUBFSR Subtract Literal from FSR

Syntax: SUBFSR f, k

Operands: 0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

Operation: FSRf – k → FSRf

Status Aff e cted: None

Encoding: 1110 1001 ffkk kkkk

Description: The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified by

‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: SUBFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 03DCh

SUBULNK

Subtract Literal from FSR2 and Return

Syntax: SUBULNK k

Operands: 0 ≤ k ≤ 63

Operation: FSR2 – k → FSR2

(TOS) → PC

S t at us Af fect ed: None

Encoding: 1110 1001 11kk kkkk

Description: The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURN is then

executed by loading the PC with the TOS.

The instruction takes two cycles to

execute; a NOP is performed during the

second cycle.

This may be thought of as a special case of

the SUBFSR instruction, where f = 3 (binary

‘11’); it operates only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Operation No

Operation

Example: SUBULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 03DCh

PC = (TOS)

PIC18F2455/2550/4455/4550

26.2.3 BYTE- OR IENT ED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

In additio n to eight new comm ands in the extende d set,

enabling the extended instruction set also enables

Indexed Literal Offset Addre ssing mode (Section 5.6.1

“Indexed Addressing with Literal Offset”). This has

a sign ificant im pact on the way t hat many com mands of

the standard PIC18 instruction set are interpreted.

When the ex ten ded se t is di sabled, add r ess es em be d-

ded in opco des are treated as literal memory locations:

either as a location in the Access Bank (‘a’ = 0) or in a

GPR bank designated by the BSR (‘a’ = 1). When the

extended instruction set is enabled and ‘a’ = 0,

however, a file register argument of 5Fh or less is

interpreted as an offset from the pointer val ue in FSR2

and not as a literal address. For practical purposes, this

means that all i nstructio ns that us e the Acc ess RAM b it

as an argument – that is, all byte-oriented and bit-

oriented instructions, or almost half of the core PIC18

instructions – may behave differently when the

extended instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating backward

compatible code. If this technique is used, it may be

necessary to save the value of FSR2 and restore it

when moving back and forth between C and assembly

routines in order to preserve the Stack Pointer. Users

must also keep in mind the syntax requirements of the

extended instruction set (see Section 26.2.3.1

“Extended Instruction Syntax with Standard PIC18

Commands”).

Although the Indexed Literal Offset Addressing mode

can be very useful for dynamic stack and pointer

manipulation, it can also be very annoying if a simple

arithmetic operation is carried out on the wrong

programming must keep in mind that, when the

extende d inst ruction se t is ena bled, re giste r addres ses

of 5Fh or less are used for Indexed Literal Offset

Addressing.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

Address ing mode are pro vided on the f ollowing p age to

show how execution is affected. The operand

conditions shown in the examples are applicable to all

instructions of these types.

26.2.3.1 Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

bit-or iented command s is replaced with the li teral offs et

value, ‘k ’. As al rea dy no ted , this occ urs only when ‘f’ is

less t han or eq ual to 5Fh. When an of fset val ue is use d,

it must be indicated by square brackets (“[ ]”). As with

the exte nded ins tructions , the us e of brac kets indicate s

to the com pil er th at the val ue is to be in terp rete d as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within brackets, will generate an

error in the MPASM Assembler.

If the ind ex argume nt is pr operly brackete d for Indexe d

Literal Offset Addressing mode, the Access RAM

argument is never specified; it will automatically be

assumed to be ‘0’. This is in contrast to standard

operation (extended instruction set disabled) when ‘a’

is set on the basis of the target address. Declaring the

Access RAM bi t in this mode will also generat e an error

in the MPASM Assembler.

The destination argument, ‘d’, functions as before.

In the latest versions of the MPASM assembler,

languag e s upp ort for the extende d i ns truc tio n s et m ust

be explicitly invoked. This is done with either the

command line option, /y, or the PE directive in the

source lis tin g.

26.2. 4 CONSIDERATIONS W HEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is i mport ant to note that the exten sions to th e ins truc-

tion set may not be beneficial to all users. In particular,

users who are not writing code that uses a software

stack may not benefit from using the extensions to the

instruction se t.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instruc t ion s i n th e le gac y cod e m ay atte mp t to a dd r es s

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

When porting an application to the PIC18F2455/2550/

4455/4550, it is very important to consider the type of

code. A l arge, re-entrant application that is written in ‘C’

and wou ld bene fit from effi cient compi lation will do well

when using the instruction set extensions. Legacy

applic ations tha t heavily use the Ac cess Ban k will most

likely not benefit from using the extended instruction

set.

Note: Enabling the PIC18 instruction set

extension may cause legacy applications

to behave erratically or fail entirely.

PIC18F2455/2550/4455/4550

ADDWF ADD W to Indexed

(Indexed Literal Offset mode)

Syntax: ADDWF [k] {,d}

Operands: 0 ≤ k ≤ 95

d ∈ [0,1]

Operation: (W) + ((FSR2) + k) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01d0 kkkk kkkk

Description: The contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Proces s

Data Write to

destination

Example: ADDWF [OFST] ,0

Before Instruction

W = 17h

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 20h

After Instruction

W = 37h

Contents

of 0A2Ch = 20h

BSF Bit Set Indexed

(Indexed Literal Offset mode)

Syntax : BSF [k ], b

Operands: 0 ≤ f ≤ 95

0 ≤ b ≤ 7

Operation: 1 → ((FSR2) + k)

Status Aff e cted: None

Encoding: 1000 bbb0 kkkk kkkk

Description: Bit ‘b’ of the register indicated by FSR2,

offset by the value ‘k’, is set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: BSF [FLAG_OFST], 7

Before Instruction

FLAG_OFST = 0Ah

FSR2 = 0A00h

Contents

of 0A0Ah = 55h

After Instruction

Contents

of 0A0Ah = D5h

SETF Set Indexed

(Indexed Literal Offset mode)

Syntax: SETF [k]

Operands: 0 ≤ k ≤ 95

Operation: FFh → ((FSR2) + k)

Status Aff e cted: None

Encoding: 0110 1000 kkkk kkkk

Description: The contents of the register indicated by

FSR2, offset by ‘k’, are set to FFh.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data Write

Example: SETF [OFST]

Before Instruction

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 00h

After Instruction

Contents

of 0A2Ch = FFh

PIC18F2455/2550/4455/4550

26.2.5 SPECIAL CONSIDERATIONS WITH

MICROCHIP MPLAB ® IDE TOOLS

The latest versions of Microchip’s software tools have

been de signe d t o full y sup port th e exte nded i nstruc tion

set of the PIC18F2455/2550/4455/4550 family of

devices. This includes the MPLAB C18 C compiler,

MPASM Assembly language and MPLAB Integrated

Development Environment (IDE).

When selecting a target device for software

development, MPLAB IDE will automatically set default

Configuration bit s for that device. The default setting for

the XINST Configuration bit is ‘0’, disabling the

extended instruction set and Indexed Literal Offset

Address ing mod e. For pr oper e xecution of app licat ions

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Index ed Addressing mode in the ir languag e tool(s).

Depending on the enviro nment being used, this may be

done in several ways:

• A menu option, or dialog bo x within the

environ me nt, th at allows the user to conf igu r e th e

language tool and its settings for the project

• A command line option

• A directive in the source code

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to review the documentation accompany-

ing their development systems for the appropriate

information.

PIC18F2455/2550/4455/4550

27.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mm ers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

27.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separa tely)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC18F2455/2550/4455/4550

27.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

27.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 family of microcontrollers and

dsPIC30F family of digital signal controllers. These

compilers provide powerful integration capabilities,

superior code optimization and ease of use not found

with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

27.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, de letion and extraction

27.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linke d with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

27.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, as well as internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the laboratory environment, making it an excellent,

economical software development tool.

PIC18F2455/2550/4455/4550

27.7 MPLAB ICE 2000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC micro-

controllers. Software control of the MPLAB ICE 2000

In-Circuit Emulator is advanced by the MPLAB Inte-

grated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

27.8 MPLAB ICE 4000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 4000 In-Circuit Emu lator is intende d to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PIC MCUs and dsPIC DSCs. Software control of the

MPLAB ICE 4000 In-Circuit Emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environm ent.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

27.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

27.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is incl uded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions and

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

PIC18F2455/2550/4455/4550

27.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

27.12 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

PIC18F2455/2550/4455/4550

28.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)..........................................-0.3V to (VDD + 0.3V)

Vo lt a ge on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Vo lt a ge on MCLR with respect to VSS (Note 2)......................................................................................... 0V to +13.25V

Total po wer dissipation (Note 1) ...............................................................................................................................1.0W

Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA

Maximum curr ent i nto VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. ±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin....................................................................................................25 mA

Maximum curr ent su nk by all ports .......................................................................................................................200mA

Maximum current sourced by all ports..................................................................................................................200 mA

Note 1: Power diss ipation is calculated as follows :

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause

latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/

RE3 pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC18F2455/2550/4455/4550

FIGURE 28-1: PIC18F2455/2550/4455/4550 V OLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 28-2: PIC18LF2455/2550/4455/4550 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

48 MHz

5.0V

3.5V

3.0V

2.5V

PIC18FX455/X550

4.2V

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

48 MHz

5.0V

3.5V

3.0V

2.5V

PIC18LFX455/X550

Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application .

4 MHz

4.2V

25 MHz16 MHz

PIC18F2455/2550/4455/4550

28.1 DC Characteri stics: Supply Voltage

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550

(Industrial) Standard Opera ting C ondition s (u nl ess o the rwise stated)

Oper ati ng t em peratur e -4 0°C ≤ TA ≤ +85° C fo r industrial

PIC18F2455/2550/4455/4550

(Industrial) Standard Opera ting C ondition s (u nl ess o the rwise stated)

Oper ati ng t em peratur e -4 0°C ≤ TA ≤ +85° C fo r industrial

Param

No. Symbol Characteristic Min Typ Max Units Conditions

D001 VDD Sup ply Voltage 2.0 — 5.5 V EC, HS, XT and Internal Oscillator modes

3.0 — 5.5 V HSPL L, XTPL L, ECPIO and ECPLL

Oscillator modes

D002 VDR RAM Data Retention

Voltage(1) 1.5 — — V

D003 VPOR VDD Start Vo ltage

to en sure in ternal P o wer-on

Rese t si gnal

— — 0.7 V See Section 4.3 “Power-on Reset (POR)”

for details

D004 SVDD VDD Rise Rate

to en sure in ternal P o wer-on

Rese t si gnal

0.05 — — V/ms See Section 4.3 “Power-on Reset (POR)”

for details

D005 VBOR Brown-out Reset Volt age

BORV1:BORV0 = 11 2.00 2.05 2.16 V

BORV1:BORV0 = 10 2.65 2.79 2.93 V

BORV1:BORV0 = 01 4.11 4.33 4.55 V

BORV1:BORV0 = 00 4.36 4.59 4.82 V

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: This is the limit to which VDD can be lowere d in S le ep mode, or dur i ng a device R eset, without losing R AM data .

PIC18F2455/2550/4455/4550

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

Param

No. Device Typ Max Units Conditions

Power-Down Current (IPD)(1)

PIC18LFX455/X550 0.1 0.95 μA -40°C VDD = 2.0V

(Sleep mode)

0.1 1.0 μA +25°C

0.2 5 μA +85°C

PIC18LFX455/X550 0.1 1.4 μA-40°C VDD = 3.0V

(Sleep mode)

0.1 2 μA +25°C

0.3 8 μA +85°C

All de vices 0.1 1.9 μA-40°C VDD = 5.0V

(Sleep mode)

0.1 2.0 μA +25°C

0.4 15 μA +85°C

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g vol tage, frequency and mode. Other fact ors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

Supply Current (IDD)(2)

PIC18LFX455/X550 15 32 μA-40°C VDD = 2.0V

FOSC = 31 kH z

(RC_RUN mo de,

INTRC source)

15 30 μA+25°C

15 29 μA+85°C

PIC18LFX455/X550 40 63 μA-40°C VDD = 3.0V35 60 μA+25°C

30 57 μA+85°C

All de vices 1 05 168 μA-40°C VDD = 5.0V90 160 μA+25°C

80 152 μA+85°C

PIC18LFX455/X550 0.33 1 mA -40°C VDD = 2.0V

FOSC = 1 MHz

(RC_RUN mo de,

INTOSC source)

0.33 1 mA +25°C

0.33 1 mA +85°C

PIC18LFX455/X550 0.6 1.3 mA -40°C VDD = 3.0V0.6 1.2 mA +25°C

0.6 1.1 mA +85°C

All de vi ces 1.1 2.3 mA -4 0°C VDD = 5.0V1.1 2.2 mA +25°C

1.0 2.1 mA +85°C

PIC18LFX455/X550 0.8 2.1 mA -40°C VDD = 2.0V

FOSC = 4 MHz

(RC_RUN mo de,

INTOSC source)

0.8 2.0 mA +25°C

0.8 1.9 mA +85°C

PIC18LFX455/X550 1.3 3.0 mA -40°C VDD = 3.0V1.3 3.0 mA +25°C

1.3 3.0 mA +85°C

All de vi ces 2.5 5.3 mA -4 0°C VDD = 5.0V2.5 5.0 mA +25°C

2.5 4.8 mA +85°C

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g voltage, frequency and mode. Other fact or s, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

Supply Current (IDD)(2)

PIC18LFX455/X550 2.9 8 μA-40°C VDD = 2.0V

FOSC = 31 kH z

(RC_IDLE mode,

INTR C so urce)

3.1 8 μA+25°C

3.6 11 μA+85°C

PIC18LFX455/X550 4.5 11 μA-40°C VDD = 3.0V4.8 11 μA+25°C

5.8 15 μA+85°C

All de vices 9.2 16 μA-40°C VDD = 5.0V9.8 16 μA+25°C

11.4 36 μA+85°C

PIC18LFX455/X550 165 350 μA-40°C VDD = 2. 0V

FOSC = 1 MHz

(RC_IDLE mode,

INTOSC source)

175 350 μA+25°C

190 350 μA+85°C

PIC18LFX455/X550 250 500 μA-40°C VDD = 3. 0V270 500 μA+25°C

290 500 μA+85°C

All de vi ces 0. 50 1 mA -40°C VDD = 5.0V0.52 1 mA +25°C

0.55 1 mA +85°C

PIC18LFX455/X550 340 500 μA-40°C VDD = 2. 0V

FOSC = 4 MHz

(RC_IDLE mode,

INTOSC source)

350 500 μA+25°C

360 500 μA+85°C

PIC18LFX455/X550 520 900 μA-40°C VDD = 3. 0V540 900 μA+25°C

580 900 μA+85°C

All de vi ces 1.0 1.6 mA -4 0°C VDD = 5.0V1.1 1.5 mA +25°C

1.1 1.4 mA +85°C

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g vol tage, frequency and mode. Other fact ors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

Supply Current (IDD)(2)

PIC18LFX455/X550 250 500 μA-40°C VDD = 2. 0V

FOSC = 1 M HZ

(PRI_RUN,

EC oscillator)

250 500 μA+25°C

250 500 μA+85°C

PIC18LFX455/X550 550 650 μA-40°C VDD = 3. 0V480 650 μA+25°C

460 650 μA+85°C

All de vi ces 1.2 1.6 mA -4 0°C VDD = 5.0V1.1 1.5 mA +25°C

1.0 1.4 mA +85°C

PIC18LFX455/X550 0.74 2.0 mA -40°C VDD = 2.0V

FOSC = 4 MHz

(PRI_RUN,

EC oscillator)

0.74 2.0 mA +25°C

0.74 2.0 mA +85°C

PIC18LFX455/X550 1.3 3.0 mA -40°C VDD = 3.0V1.3 3.0 mA +25°C

1.3 3.0 mA +85°C

All de vi ces 2.7 6.0 mA -4 0°C VDD = 5.0V2.6 6.0 mA +25°C

2.5 6.0 mA +85°C

All de vi ces 15 35 mA -40°C VDD = 4.2V FOSC = 40 MHZ

(PRI_RUN,

EC oscillator)

16 35 mA +25°C

16 35 mA +85°C

All de vi ces 21 40 mA -40°C VDD = 5.0V21 40 mA +25°C

21 40 mA +85°C

All de vi ces 20 40 mA -40°C VDD = 4.2V FOSC = 48 MHZ

(PRI_RUN,

EC oscillator)

20 40 mA +25°C

20 40 mA +85°C

All de vi ces 25 50 mA -40°C VDD = 5.0V25 50 mA +25°C

25 50 mA +85°C

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g voltage, frequency and mode. Other fact or s, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

Supply Current (IDD)(2)

PIC18LFX455/X550 65 130 μA-40°C VDD = 2.0V

FOSC = 1 MHz

(PRI_IDLE mode,

EC oscillator)

65 120 μA+25°C

70 115 μA+85°C

PIC18LFX455/X550 120 270 μA-40°C VDD = 3. 0V120 250 μA+25°C

130 240 μA+85°C

All de vices 2 30 480 μA-40°C VDD = 5.0V240 450 μA+25°C

250 430 μA+85°C

PIC18LFX455/X550 255 475 μA-40°C VDD = 2. 0V

FOSC = 4 MHz

(PRI_IDLE mode,

EC oscillator)

260 450 μA+25°C

270 430 μA+85°C

PIC18LFX455/X550 420 900 μA-40°C VDD = 3. 0V430 850 μA+25°C

450 810 μA+85°C

All de vi ces 0.9 1.5 mA -4 0°C VDD = 5.0V0.9 1.4 mA +25°C

0.9 1.3 mA +85°C

All de vices 6.0 16 mA -40°C VDD = 4. 2V FOSC = 40 MH z

(PRI_IDLE mode,

EC oscillator)

6.2 16 mA +25°C

6.6 16 mA +85°C

All de vices 8.1 18 mA -40°C VDD = 5. 0V8.3 18 mA +25°C

9.0 18 mA +85°C

All de vices 8.0 18 mA -40°C VDD = 4. 2V FOSC = 48 MH z

(PRI_IDLE mode,

EC oscillator)

8.1 18 mA +25°C

8.2 18 mA +85°C

All de vices 9.8 21 mA -40°C VDD = 5. 0V10.0 21 mA +25°C

10.5 21 mA +85°C

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g vol tage, frequency and mode. Other fact ors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

Supply Current (IDD)(2)

PIC18LFX455/X550 14 40 μA-40°C VDD = 2.0V

FOSC = 32 k H z(3)

(SEC_RUN mode,

Ti mer1 as clock)

15 40 μA+25°C

16 40 μA+85°C

PIC18LFX455/X550 40 74 μA-40°C VDD = 3.0V35 70 μA+25°C

31 67 μA+85°C

All de vices 99 1 50 μA-40°C VDD = 5.0V81 150 μA+25°C

75 150 μA+85°C

PIC18LFX455/X550 2.5 12 μA-40°C VDD = 2.0V

FOSC = 32 k H z(3)

(SEC_IDLE mode,

Ti mer1 as clock)

3.7 12 μA+25°C

4.5 12 μA+85°C

PIC18LFX455/X550 5.0 15 μA-40°C VDD = 3.0V5.4 15 μA+25°C

6.3 15 μA+85°C

All de vices 8.5 25 μA-40°C VDD = 5.0V9.0 25 μA+25°C

10.5 36 μA+85°C

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g voltage, frequency and mode. Other fact or s, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

D022

(ΔIWDT)Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)

W atchdog Timer 1.3 3.8 μA-40°C VDD = 2.0V1.4 3.8 μA+25°C

2.0 3.8 μA+85°C

1.9 4.6 μA-40°C VDD = 3.0V2.0 4.6 μA+25°C

2.8 4.6 μA+85°C

4.0 10 μA-40°C VDD = 5. 0V5.5 10 μA+25°C

5.6 10 μA+85°C

D022A

(ΔIBOR)Brown-out Reset(4) 35 40 μA -40°C to +85°C VDD = 3.0V

40 45 μA -40°C to +85°C VDD = 5.0V

02μA -40°C to +85°C Sleep mode,

BOREN1:BOREN0 = 10

D022B

(ΔILVD)High/Low-Voltage

Detect(4) 22 38 μA -40°C to +85°C VDD = 2.0V

25 40 μA-40°C to +85°C VDD = 3.0V

29 45 μA -40°C to +85°C VDD = 5.0V

D025

(ΔIOSCB)Timer1 Osci llat or 2.1 4.5 μA-40°C VDD = 2.0V 32 kHz on Timer1(3)

1.8 4.5 μA+25°C

2.1 4.5 μA+85°C

2.2 6.0 μA-40°C VDD = 3.0V 32 kHz on Time r 1(3)

2.6 6.0 μA+25°C

2.9 6.0 μA+85°C

3.0 8.0 μA-40°C VDD = 5.0V 32 kHz on Time r 1(3)

3.2 8.0 μA+25°C

3.4 8.0 μA+85°C

D026

(ΔIAD)A/D Converter 1.0 2.0 μA -40°C to +85°C VDD = 2.0V A/D on, not converting1.0 2.0 μA -40°C to +85°C VDD = 3.0V

1.0 2.0 μA -40°C to +85°C VDD = 5.0V

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Oper atin g t em perature -40°C ≤ TA ≤ +85° C for in dustrial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g vol tage, frequency and mode. Other fact ors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

USB and Related Module Differential Currents (ΔIUSBx, ΔIPLL, ΔIUREG)

ΔIUSBxUSB Module

with On-Chi p Transceiver 8TBDmA +25°CVDD = 3.3V

TBD TBD mA +25°CVDD = 5.0V

ΔIPLL 9 6 MHz PL L

(Oscillato r Modul e ) 1.2 TBD mA +25°CVDD = 3.3V

TBD TBD TBD +25°CVDD = 5.0V

ΔIUREG USB Inte rnal Voltage

Regulator 80 TBD μA+25°CV

DD = 5.0V

28.2 DC Characteri stics: Power-Down and Supply Current

PIC18F2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

PIC18F2455/2550/4455/4550

(Industrial) Standar d Oper ating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu st rial

Param

No. Device Typ Max Units Conditions

Legend: TBD = To Be Det er m ined. Shading of rows is to assis t in re adability of the tab le .

Note 1: The po wer-d own curr ent i n Sle ep mo de do es not de pend o n th e osc il lator ty pe. P ower- dow n cur rent is m easur ed

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and al l fea tu re s th at

add del ta current disa bl ed ( suc h as WDT, Timer1 Oscillat or, B O R , etc .).

2: The supply current is mainly a function of operatin g voltage, frequency and mode. Other fact or s, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard low - cost 32 kHz crystals have an oper at ing t emperat ur e range of -10°C to +70 °C . Ext ended

tem per at ur e cr ystals are avai la ble at a m uch higher c o st.

4: BOR and HLVD enable inter nal band gap referen ce. W ith both modu le s enabled, cur re nt consumption will be

less than the su m of bo th specificat io ns.

PIC18F2455/2550/4455/4550

28.3 DC Characteri s tics: PIC18F2455/ 2550/4455/4550 (Industrial )

PIC18LF2455/2550/ 4455/4550 (Industrial)

DC CHARACTERISTICS Standard Opera ting Conditions (un less o therw ise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industr ial

Param

No. Symbol Characteristic Min Max Units Conditions

VIL Input Low Volta ge

I/O ports (except RC4/RC5 in

USB mode):

D030 with TTL buffer VSS 0.15 VDD VVDD < 4.5V

D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger buffer

RC3 and RC4 VSS

VSS 0.2 VDD

0.3 VDD V

D032 MCLR VSS 0.2 VDD V

D032A OSC1 and T1OSI VSS 0.3 VDD VXT, HS,

HSPLL modes (1)

D033 OSC1 VSS 0.2 VDD VEC mode

(1)

VILU D+/D- in put — 0.8 V VDD = 4.35V,

USB suspended(5)

VIH Input High Volt age

I/O ports (except RC4/RC5 in

USB mode):

D040 with TTL buffer 0.25 VDD + 0.8V VDD VVDD < 4.5V

D040A 2.0 VDD V4.5V ≤ VDD ≤ 5.5V

D041 with Schmitt Trigger buffer

RC3 and RC4 0.8 VDD

0.7 VDD VDD

VDD V

D042 MCLR 0.8 VDD VDD V

D042A OSC1 and T1OSI 0.7 VDD VDD VXT, HS,

HSPLL modes (1)

D043 OSC1 0.8 VDD VDD VEC mode

(1)

VIHU D+/D - in put 2.4 — V VDD = 4.35V,

USB suspended(5)

IIL Input Leakage Current (2,3)

D060 I/O ports — ±1μAV

SS ≤ VPIN ≤ VDD,

Pin at high-impe dan ce

D061 MCLR —±5μAVss ≤ VPIN ≤ VDD

D063 OSC1 — ±5μAVss ≤ VPIN ≤ VDD

IPU Weak Pull-up Current

D070 IPURB PORTB weak pull- up current 50 400 μAVDD = 5V, VPIN = VSS

Note 1: In RC oscillato r confi guration, t he OSC1/CLKI p in is a Sc hmitt T rigg er input. It is not rec ommended t hat the

PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Parameter is characterized but not tested.

5: D+ parameters per USB Specification 2.0.

PIC18F2455/2550/4455/4550

VOL Output Low Voltage

D080 I/O ports (except RC4/RC5 in

USB mode) —0.6VIOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

D083 OSC2/CLKO

(EC, ECIO modes) —0.6VI

OL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

VOLU D+/D - ou t — 0.3 VDD = 4.35V,

USB suspended(5)

VOH Output High Voltage(3)

D090 I/O ports (except RC4/RC5 in

USB mode) VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

D092 OSC2/CLKO

(EC, ECIO, ECPIO modes) VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

VOHU D+/D- ou t 2.8 3.6 V VDD = 4.35V,

USB suspended(5)

Capacitive Loading Specs

on Output Pins

D100(4) COSC2 OSC2 pin — 15 pF In XT and HS modes

when external clock is

used to drive OSC1

D101 CIO All I/O pins and OSC2

(in RC mode) — 50 pF To meet the AC Timing

Specifications

D102 CBSCL, SDA — 400 pF I2C™ Specification

28.3 DC Characteri s tics: PIC18F2455/ 2550/4455/4550 (Industrial )

PIC18LF2455/2550/ 4455/4550 (Industrial) ( Co ntinued)

DC CHARACTERISTICS Standard Opera ting Conditions (un less ot herw ise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industr ial

Param

No. Symbol Characteristic Min Max Units Conditions

Note 1: In RC oscillato r confi guration, t he OSC1/CLKI p in is a Sc hmitt T rigg er input. It is not rec ommended t hat the

PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Parameter is characterized but not tested.

5: D+ parameters per USB Specification 2.0.

PIC18F2455/2550/4455/4550

TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS

DC Character ist ics Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Internal Program Memory

Programming Specifications(1)

D110 VPP Voltage on MCLR/VPP/RE3 pin 9.00 — 13.25 V (Note 3)

D113 IDDP Supply Current during

Programming ——10mA

Data EEPROM Memory

D120 EDByte Endurance 100K 1M — E/W -40°C to +85°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time — 4 — ms

D123 TRETD Characteristic Retention 40 — — Year Provided no other

specifications are violated

D124 TREF Nu mber of Total Eras e/Writ e

Cycles before Re fresh(2) 1M 10M — E/W -40°C to +85°C

Program Flash Memory

D130 EPCell Endurance 10K 100K — E/W -40°C to +85°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP™ port

D132A VIW VDD for Externally Timed Erase

or Write 4.5 — 5.5 V Using ICSP port

D132B VPEW VDD for Self-Timed Write VMIN —5.5VVMIN = Minimum operating

voltage

D133 TIE ICSP Block Erase Cycle Ti me — 4 — ms VDD > 4.5V

D133A TIW ICSP E rase or Write Cycle Time

(externall y tim ed) 1——msVDD > 4.5V

D133A TIW Self-Timed Write Cycle Time — 2 — ms

D134 TRETD Characteristic Retention 40 100 — Year Provided no other

specifications are violated

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: These specifications are for programming the on-chip program memory through the use of table write

instructions.

2: Refer to Section 7.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM

endurance.

3: Required only if Si ng le-Su ppl y Progra mm in g is disabl ed.

PIC18F2455/2550/4455/4550

TABLE 28-2: COMPARATOR SPECIFICATIONS

TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV

D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V

D302 CMRR Common Mo de Re je cti on Ra tio * 55 — — dB

300 TRESP Response Time*(1) — 150 400 ns PIC18FXXXX

300A — 150 600 ns PIC18LFXXXX,

VDD = 2.0V

301 TMC2OV Comparator Mode Change to

Output Valid * ——10μs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

D310 VRES Resolution VDD/24 — VDD/32 LSb

D311 VRAA Absol ute Accuracy —

—1/4

—1

1/2 LSb

LSb Low Range (CVRR = 1)

High Range (CVRR = 0)

D312 VRUR Unit Resistor Value (R)* — 2k — Ω

310 TSET Settling Time*(1) — — 10 μs

* These parameters are characterized but not tested.

Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.

PIC18F2455/2550/4455/4550

TABLE 28-4: USB MODULE SPECIFICATIONS

TABLE 28-5: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).

Param

No. Sym Characteristic Min Typ Max Units Comments

D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on bus must be in this

range for proper USB

operation

D314 IIL Input Leakage on Pin — — ±1μAVSS ≤ VPAD ≤ VDD;

pin at high impedance

D315 VILUSB Input Low Voltage for USB

Buffer ——0.8VFor VUSB range

D316 VIHUSB Input High Voltage for USB

Buffer 2.0 — — V For VUSB range

D317 VCRS Crossover Voltage 1.3 2.0 V Voltage range for pad_dp and

pad_dm crossover to occur

D318 VDIFS D ifferential Input Sensitivity — — 0.2 V The difference between D+

and D- must exceed this value

while VCM is met

D319 VCM Differential Common Mode

Range 0.8 — 2.5 V

D320 ZOUT Driver Output Impedance 28 — 44 Ω

D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kΩ load connected to 3.6V

D322 VOH Voltage Output High 2.8 — 3.6 V 15 kΩ load connected to

ground

Operating Condit ions : -40°C < TA < +85°C (unless otherwise stated).

Param

No. Sym Characteristics Min Typ Max Units Comments

D323 VUSBANA Regulator Ou tpu t Voltage* 3.0 — 3.6 V

D324 CUSB External Fil ter Cap acito r

Value* 220 — — nF Must hold sufficient charge

for peak load with minimal

voltage drop

* These parameters are characterized but not tested. Parameter numbers not yet assigned for these

specifications.

PIC18F2455/2550/4455/4550

FIGURE 28-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

TABLE 28-6: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

VHLVD

HLVDIF

VDD

(HLV DIF set by hardware) (HLVDIF can be

cleared in software)

VHLVD

For VDIRMA G = 1:

For VDIRMA G = 0:VDD

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Typ Max Units Conditions

D420 HLVD Voltage on VDD

Transition High-to-Low HLVDL<3:0> = 0000 2.06 2.17 2.28 V

HLVDL<3:0> = 0001 2.12 2.23 2.34 V

HLVDL<3:0> = 0010 2.24 2.36 2.48 V

HLVDL<3:0> = 0011 2.32 2.44 2.56 V

HLVDL<3:0> = 0100 2.47 2.60 2.73 V

HLVDL<3:0> = 0101 2.65 2.79 2.93 V

HLVDL<3:0> = 0110 2.74 2.89 3.04 V

HLVDL<3:0> = 0111 2.96 3.12 3.28 V

HLVDL<3:0> = 1000 3.22 3.39 3.56 V

HLVDL<3:0> = 1001 3.37 3.55 3.73 V

HLVDL<3:0> = 1010 3.52 3.71 3.90 V

HLVDL<3:0> = 1011 3.70 3.90 4.10 V

HLVDL<3:0> = 1100 3.90 4.11 4.32 V

HLVDL<3:0> = 1101 4.11 4.33 4.55 V

HLVDL<3:0> = 1110 4.36 4.59 4.82 V

PIC18F2455/2550/4455/4550

28.4 AC (Timing) Characteristics

28.4.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

pp ad SPP address write m c MCLR

cc CCP1 osc OSC1

ck CLKO rd RD

cs CS rw RD or WR

da SPP data write sc SCK

di SDI ss SS

do SDO t0 T0CKI

dt Data in t1 T13CKI

io I/O port wr WR

Uppercase letters and their meanings:

SF Fall P Period

HHigh RRise

I Invalid (High-Impedance) V Valid

L Low Z High-Impedance

I2C only

AA output access High High

BUF Bus free Low L ow

TCC:ST (I2C specifications only)

CC HD Hold SU Setup

ST DAT DATA input hold STO Stop condition

STA Start condition

PIC18F2455/2550/4455/4550

28.4.2 TIMING CONDITIONS

The temperature and voltages specified in Table 28-7

apply to all timing specifications unless otherwise

noted. Figure 28-4 specifies the load conditions for the

timing specificati o n s.

TABLE 28-7: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 28-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Note: Because of space limitations, the generic

terms “PIC18FXXXX” and “PIC18LFXXXX”

are used throughout this section to refer to

the PIC18F2455/2550/4455/4550 and

PIC18LF2455/2550/4455/4550 families of

devices specifically and only those devices.

AC CHARACTERISTICS

Standard Opera ting Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Operating voltage VDD range as described in DC spec Section 28.1 and

Section 28.3.

LF parts operate for industrial temperatures only.

VDD/2

VSS

RL=464Ω

CL= 50 pF for all pins except OSC2 /CLKO

and including D and E outputs as ports

Load Cond iti on 1 Load Condition 2

PIC18F2455/2550/4455/4550

28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 28-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

23344

Param.

No. Symbol Characteristic Min Max Units Conditions

1A FOSC External CLKI Frequenc y(1)

Oscillator Frequency(1) DC 48 MHz EC, ECIO Oscillator mode

0.2 1 MHz XT, XTPLL Oscillator mode

4 25 MHz HS Oscillator mode

4 25 MHz HSPLL Oscillator mode

OSC External CLKI Period (1)

Oscillator Period(1) 20.8 — ns EC, ECIO Osci ll ator mode

1000 5000 ns XT Oscillator mode

40 250

250 ns

ns HS Oscillator mode

HSPLL Oscillator mode

CY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC

3 TosL,

TosH External Clock in (OSC1)

High or Low Time 30 — ns XT Oscillator mode

10 — ns HS Oscillator mode

4TosR,

TosF External Clock in (OSC1)

Rise or Fall Time — 20 ns XT Oscillator mode

— 7.5 ns HS Oscillator mode

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations

except PLL . Al l specified va lue s are bas ed on char ac teri zat ion dat a for that particular osci ll ator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result

in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested

to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock

input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

PIC18F2455/2550/4455/4550

TABLE 28-9: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 5.5V)

TABLE 28-10: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18F2455/2550/4455/4550 (INDUSTRIAL)

PIC18LF2455/2550/4455/4550 (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

F10 FOSC Oscillator Frequency Range 4 — 48 MHz

F11 FSYS On-Chip VCO System Frequency — 96 — MHz

F12 trc PLL Start -up Time (Lock Time) — — 2 ms

F13 ΔCLK CLKO Stability (Jitter) -0.25 — +0.25 %

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC18LF2455/2550/4455/4550

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for indu stri al

Param

No. Device Min Typ Max Units Conditions

INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)

PIC18LF2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 2.7-3.3V

-5 — 5 % -10°C to +85°C VDD = 2.7-3.3V

-10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V

PIC18F2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 4.5-5.5V

-5 — 5 % -10°C to +85°C VDD = 4.5-5.5V

-10 +/-1 10 %-40°C to +85°C VDD = 4.5-5.5V

INTRC Accuracy @ Freq = 31 kHz(2)

PIC18LF2455/2550/4455/4550 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V

PIC18F2455/2550/4455/4550 26.562 —35.938 kHz -4 0°C to +85°C VDD = 4.5-5.5V

Legend: Shading of rows is to assist in readability of the table.

Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.

2: INTRC frequency after calibration.

3: Change of INTRC frequency as VDD changes.

PIC18F2455/2550/4455/4550

FIGURE 28-6: CLKO AND I/O TIMING

TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS

Note: Refer to Figure 28-4 for load conditions.

OSC1

CLKO

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

Old Value New Value

Param

No. Symbol Characteristic Min Typ Max Units Conditions

10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1)

11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1)

12 TckR CLKO Rise Time — 35 100 ns (Note 1)

13 TckF CLKO Fall Time — 35 100 ns (Note 1)

14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)

15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1)

16 TckH2ioI Port In Hold after CLKO ↑ 0——ns(Note 1)

17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns

18 TosH2ioI OSC1 ↑ (Q2 cycle) to

Port Input Invalid

(I/O in hold time)

PIC18FXXXX 100 — — ns

18A PIC18LFXXXX 200 — — ns VDD = 2.0V

19 T ioV2osH Port Input V alid to OSC1 ↑ (I/O in setup time) 0 — — ns

20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns

20A PIC18LFXXXX — — 60 ns VDD = 2.0V

21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns

21A PIC18LFXXXX — — 60 ns VDD = 2.0V

22† TINP INT pin High or Low Time TCY ——ns

23† TRBP RB7:RB4 Change INT High or Low Time TCY ——ns

† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

PIC18F2455/2550/4455/4550

FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 28-8: BROWN-OUT RESET TIMING

TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — — μs

31 TWDT W atc hd og Timer Time -out Perio d

(no postscaler) —4.00TBDms

32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period

33 TPWRT Power-up Timer Period — 65.5 TBD ms

34 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset —2—μs

35 TBOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see D005)

36 TIRVST Time for Internal Reference

Voltage to become Stable —2050 μs

37 TLVD Low-Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD

38 TCSD CPU Start-up Time 5 — 10 μs

39 TIOBST Time for INTOSC to Stabilize — 1 — ms

Legend: TBD = To Be Determined

VDD

MCLR

Internal

POR

PWRT

Time-out

Oscillator

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

Note: Refer to Figure 28-4 for load conditions.

VDD BVDD 35 VBGAP = 1.2V

VIRVST

Enable Internal

Inte rn a l Referen ce 36

Reference Voltage

Voltage Stable

PIC18F2455/2550/4455/4550

FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Note: Refer to Figure 28-4 for load conditions.

T0CKI

T1OSO/T13CKI

TMR0 or

TMR1

Param

No. Symbol Characteristic Min Max Units Conditions

40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

41 Tt0L T 0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

42 Tt0P T0CKI Period No prescaler TCY + 10 — ns

With prescaler Greater of:

20 ns or

(TCY + 40)/N

—nsN = prescale

value

(1, 2, 4,..., 256)

45 Tt1H T13CKI High

Time Synchronous, no prescaler 0.5 TCY + 20 — ns

Synchronous,

with prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 25 — ns VDD = 2.0V

Asynchronous PIC18FXXXX 30 — ns

PIC18LFXXXX 50 — ns VDD = 2.0V

46 Tt1L T13CKI Low

Time Synchronous, no prescaler 0.5 TCY + 5 — ns

Synchronous,

with prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 25 — ns VDD = 2.0V

Asynchronous PIC18FXXXX 30 — ns

PIC18LFXXXX 50 — ns VDD = 2.0V

47 Tt1P T13CKI Input

Period Synchronous Greater of:

20 ns or

(TCY + 40)/N

—nsN = prescale

value (1, 2, 4, 8)

Asynchronous 60 — ns

Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz

48 Tck e2 tmr I Delay from Ext ernal T13CKI Clock Edge to T imer

Increment 2 TOSC 7 TOSC —

PIC18F2455/2550/4455/4550

FIGURE 28-10: CAPTURE/COMP ARE/PWM TIMINGS (ALL CCP MODULES)

TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)

Note: Refer to Figure 28-4 for load conditions.

CCPx

(Capture Mode)

50 51

CCPx

53 54

(Compare or PWM Mode)

Param

No. Symbol Characteristic Min Max Units Conditions

50 T ccL CCPx Input Low

Time No prescaler 0.5 TCY + 20 — ns

With

prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 20 — ns VDD = 2.0V

51 TccH CCP x Input

High Time No prescaler 0.5 TCY + 20 — ns

With

prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 20 — ns VDD = 2.0V

52 TccP CCPx Input Period 3 TCY + 40

N—nsN = prescale

value (1, 4 or 16)

53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

54 TccF CCPx Output Fall Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

PIC18F2455/2550/4455/4550

FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

Note: Refer to Figure 28-4 for load conditions.

MSb In

Param

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS ↓ to SCK ↓ or SCK ↑ Inpu t TCY —ns

71 TscH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Sing le Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Sing le Byte 40 — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns

73A Tb2b Last Clo ck Edg e of Byt e 1 to th e 1st Cl ock Ed ge

of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Data Output Fall Time — 25 ns

78 TscR SCK Output Rise Time

(Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after

SCK Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

Note 1: Requires the use of Parameter 73A.

2: Only if Parameter 71A and 72A are used.

PIC18F2455/2550/4455/4550

FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

No. Symbol Characteristic Min Max Units Conditions

71 Ts cH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns

73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Da ta Output Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Data Output Fall Time — 25 n s

78 TscR SCK Output Rise Time

(Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Va lid after

SCK Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

81 TdoV2scH,

TdoV2scL SDO Data Output Setup to SCK Edge TCY —ns

Note 1: Requires the use of Par ameter 73 A.

2: Only if Parameter 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note: Refer to Figure 28-4 for load conditions.

PIC18F2455/2550/4455/4550

FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY —ns

71 TscH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns

73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Data Output Fall Time — 25 ns

77 TssH2doZ SS ↑ to SDO Output High-Impedance 10 50 ns

78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

83 TscH2ssH,

TscL2ssH SS ↑ after SCK edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter 73A.

2: Only if Parameter 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

SDI

MSb LSb

bit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

Note: Refer to Figure 28-4 for load conditions.

PIC18F2455/2550/4455/4550

FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 28-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY —ns

71 TscH SCK Input High Time

(Slave mode) Cont inu ous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Cont inu ous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — n s

75 TdoR SDO Data Output Ris e Time PI C 18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Da ta Out pu t Fal l Ti me — 25 ns

77 TssH2doZ SS ↑ to SDO Ou tput Hig h-Impedance 10 50 ns

78 TscR SCK Output Rise Time

(Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Ti me (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after SCK

Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

82 TssL2doV SDO Data Output Valid af ter S S ↓

Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

83 TscH2ssH,

TscL2ssH SS ↑ after SCK Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter 73A.

2: Only if Parameter 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb bit 6 - - - - - -1 LSb

MSb In bit 6 - - - -1 LSb In

Note: Refer to Figure 28-4 for load conditions.

PIC18F2455/2550/4455/4550

FIGURE 28-15 : I2C™ BUS START/STOP BITS TIMING

TABLE 28-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

FIGURE 28-16 : I2C™ BUS DATA T I MING

Note: Refer to Figure 28-4 for load conditions.

SCL

SDA

Start

Condition Stop

Condition

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated

Start condition

Setup Time 400 kHz mode 600 —

91 THD:STA Start Conditio n 100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

Hold Time 400 kHz mode 600 —

92 TSU:STO Stop Condition 100 kH z mode 470 0 — ns

Setup Time 400 kHz mode 600 —

93 THD:STO Stop Condition 100 kHz mode 4000 — ns

Hold Time 400 kHz mode 600 —

Note: Refer to Figure 28-4 for load conditions.

91 92

100

101

103

106

109 109 110

102

SCL

SDA

Out

107

PIC18F2455/2550/4455/4550

TABLE 28-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate

at a minimum of 1.5 MHz

400 kHz mode 0.6 — μs PIC18FXXXX must operate

at a minimum of 10 MHz

MSSP Module 1.5 TCY —

101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate

at a minimum of 1.5 MHz

400 kHz mode 1.3 — μs PIC18FXXXX must operate

at a minimum of 10 MHz

MSSP Module 1.5 TCY —

102 TRSDA and SCL Rise

Time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

103 TFSDA and SCL Fall

Time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

90 TSU:STA St art C ond iti on

Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated

Start condition

400 kHz mode 0.6 — μs

91 THD:STA Start Condition

Hold Time 100 kHz mo de 4.0 — μs After this period, the first

clock pulse is generated

400 kHz mode 0.6 — μs

106 THD:DAT Data Input Hold

Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs

107 TSU:DAT Data Input Setup

Time 100 kHz mode 2 50 — ns (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition

Setup Time 100 kHz mode 4.7 — μs

400 kHz mode 0.6 — μs

109 TAA Output Valid from

Clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — μs

D102 CBBus Capacitive Loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system but the requirement,

TSU:DAT ≥250 ns, must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next dat a bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I2C bus specif ication), before the SCL li ne is released .

PIC18F2455/2550/4455/4550

FIGURE 28-17 : MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS

TABLE 28-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS

FIGURE 28-18 : MASTER SSP I2C™ BUS DATA TIMING

Note: Refer to Figure 28-4 for load conditions.

91 93

SCL

SDA

Start

Condition Stop

Condition

90 92

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start C ondition 100 kHz mod e 2(TOSC)(BRG + 1) — ns Only relevant for

Repeated Start

condition

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

91 THD:STA Start Condit ion 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the

first clock pulse is

generated

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — n s

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

Note: Refer to Figure 28-4 for load conditions.

90 91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC18F2455/2550/4455/4550

TABLE 28-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

102 TRSDA and SCL

Rise Time 100 kH z mode — 1000 n s CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

103 TFSDA and SCL

Fall Time 100 kHz mode — 30 0 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 100 ns

90 TSU:STA Start Condition

Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for

Repeated Start

condition

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

91 THD:STA Start Condition

Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first

clock pulse is generated

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

106 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 ms

107 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — n s (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition

Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

109 TAA Output Valid

from Clock 1 00 kHz mode — 3500 ns

400 kHz mode — 1000 ns

1 MHz mode(1) ——ns

110 TBUF Bus Free T ime 1 00 kHz mode 4.7 — ms T im e the bu s must be free

before a new transmission

can start

400 kHz mode 1.3 — ms

D102 CBBus Ca pacitive Loading — 400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: A Fast mode I2C bus dev ic e ca n b e used in a Stan dar d mod e I2C bus sy s tem but p arameter #107 ≥250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the

SCL line is released.

PIC18F2455/2550/4455/4550

FIGURE 28-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 28-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 28-20: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 28-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

121 121

120 122

RC6/TX/CK

RC7/RX/DT/SDO

Note: Refer to Figure 28-4 for load conditions.

Param

No. Symbol Characteristic Min Max Units Conditions

120 TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock High to Data Out Valid PIC18FXXXX — 40 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

121 Tckrf Clock Out Rise Time and Fall Time

(Master mode) PIC18FXXXX — 20 ns

PIC18LFXXXX — 50 ns VDD = 2.0V

122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns

PIC18LFXXXX — 50 ns VDD = 2.0V

125

126

RC6/TX/CK

RC7/RX/DT/SDO

Note: Refer to Figure 28-4 for load conditions.

Param.

No. Symbol Characteristic Min Max Units Conditions

125 TDTV2CKL SYNC RCV (MASTER & SLAVE)

Data Hold before CK ↓ (DT hold time) 10 — ns

126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns

PIC18F2455/2550/4455/4550

FIGURE 28-21 : USB SIGNA L TIMING

TABLE 28-25: USB LOW-SPEED TIMING REQUIREMENTS

TABLE 28-26: USB FULL-SPEED REQUIREMENTS

VCRS

USB Data Differential Lines

90%

10%

TLR, TFR TLF, TFF

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF

TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF

TLRFM Rise/Fall Time Matching 80 — 125 %

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TFR Transition Rise Time 4 — 20 ns CL = 50 pF

TFF Transition Fall Time 4 — 20 ns CL = 50 pF

TFRFM Rise/Fall Time Matching 90 — 111.1 %

PIC18F2455/2550/4455/4550

FIGURE 28-22: STREAMING PARALLEL PORT TIMING (PIC18F4455/4550)

TABLE 28-27: STREAMING PARALLEL PORT REQUIREMENTS (PIC18F4455/4550)

OESPP

CSSPP

SPP<7:0> Write Data

ToeF2adR

ToeF2adV ToeR2adI

ToeF2daR

ToeF2daV ToeR2adI

Note: Refer to Figure 28-4 for load conditions.

Write Address

Param.

No. Symbol Characteristic Min Max Units Conditions

ToeF2adR OESPP Falling Edge to CSSPP Rising Edge,

Address Out 05ns

ToeF2adV OESPP Falling Edge to Ad dress Out Valid 0 5 ns

ToeR2adI OESPP Rising Edge to Address Out Invalid 0 5 ns

ToeF2daR OESPP Falling Edge to CSSPP Rising Edge,

Data Out 05ns

ToeF2daV OESPP Falling Edge to Ad dress Out Valid 0 5 ns

ToeR2daI OESPP Rising Edge to Data Out Invalid 0 5 ns

PIC18F2455/2550/4455/4550

TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F2455/2550/4455/4550 (INDUSTRIAL)

PIC18LF2455/2550/4455/4550 (INDUSTRIAL)

FIGURE 28-23: A/D CONVE RSION TIMING

Param

No. Symbol Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 10 bit ΔVREF ≥ 3.0V

A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V

A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V

A06 EOFF Offset Error — — <±1.5 LSb ΔVREF ≥ 3.0V

A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V

A10 — Monotonicity Guaranteed(1) —VSS ≤ VAIN ≤ VREF

A20 ΔVREF Reference Voltage Range

(VREFH – VREFL)1.8

3—

——

—V

VVDD < 3.0V

VDD ≥ 3.0V

A21 VREFH Reference Voltage High VSS —VREFH V

A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V

A25 VAIN Analog Inpu t Vo lt a ge V REFL —VREFH V

A30 ZAIN Recommended Impedance of

Anal og Voltage Source ——2.5kΩ

A50 IREF VREF Input Current(2) —

——

—5

150 μA

μADuring VAIN acquisition.

During A/D conversion

cycle.

Note 1: The A/D conversi on resul t never decrea ses w ith an incr ease in the input vo lta ge and has no miss ing code s.

2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.

VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

987 21 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . . . . .

TCY(1)

PIC18F2455/2550/4455/4550

TABLE 28-29: A/D CONVERSION REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μsTOSC based, VREF ≥ 3.0V

PIC18LFXXXX 1.4 25.0(1) μsVDD = 2.0V,

TOSC based, VREF full range

PIC18FXXXX TBD 1 μs A/D RC mode

PIC18LFXXXX TBD 3 μsVDD = 2.0V,

A/D RC mode

131 TCNV Conversion Time

(not including acquisition time)(2) 11 12 TAD

132 TACQ Acquisition Time(3) 1.4

TBD —

—μs

μs-40°C to +85°C

0°C ≤ to ≤ +85°C

135 TSWC Switching Time from Convert → Sample — (Note 4)

137 TDIS Discharge Time 0.2 — μs

Legend: TBD = To Be Determined

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divide r.

2: ADRES registers may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” in put voltage when the voltag e changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.

PIC18F2455/2550/4455/4550

29.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs and tables are not available at this time.

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

30.0 PACKAGING INFORMATION

30.1 Package Marking Information

28-Lead PDIP (Skinny DIP)

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F2455-I/SP

0710017

28-Lead SO IC

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F2550-E/SO

0710017

40-Lead PDIP

XXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F4455-I/P

0710017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week c ode (week of January 1 is week ‘01 ’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microc hip p art num ber cann ot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for custom er-specific information.

PIC18F2455/2550/4455/4550

Package Marking Information (Continued)

44-Lead TQFP

XXXXXXXXXX

YYWWNNN

Example

PIC18F4550

-I/PT

0710017

XXXXXXXXXX

44-Lead QFN

XXXXXXXXXX

YYWWNNN

PIC18F4550

Example

-I/ML

0710017

PIC18F2455/2550/4455/4550

30.2 Package Details

The following sections give the technical details of the

packages.

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e .100 BSC

Top to Seating Plane A – – .200

Molded Package Thickness A2 .120 .135 .150

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .335

Molded Package Width E1 .240 .285 .295

Overall Length D 1.345 1.365 1.400

Tip to Seating Plane L .110 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .050 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – . 430

NOTE 1

Microchip Technology Drawing C04-070

PIC18F2455/2550/4455/4550

28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 1.27 BSC

Overall Height A – – 2.65

Molded Package Thickness A2 2.05 – –

Standoff § A1 0.10 – 0. 30

Overall Width E 10.30 BSC

Molded Package Width E 1 7.50 BSC

Overall Length D 17.90 BSC

Chamfer (optional) h 0.25 – 0.75

Foot Length L 0.40 – 1.27

Footprint L1 1.40 REF

Foot Angle Top φ0° – 8°

Lead Thickness c 0.18 – 0. 33

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

Microchip Technology Drawing C04-052

PIC18F2455/2550/4455/4550

40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 40

Pitch e .100 BSC

Top to Seating Plane A – – .250

Molded Package Thickness A2 .125 – .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .590 – .625

Molded Package Width E1 .485 – .580

Overall Length D 1.980 – 2.095

Tip to Seating Plane L .115 – .200

Lead Thickness c .008 – .015

Upper Lead Width b1 .030 – .070

Lower Lead Width b .014 – .023

Overall Row Spacing § eB – – .700

NOTE 1

123

A1 b1

Microchip Technology Drawing C04-016

PIC18F2455/2550/4455/4550

44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Chamfers at corners are optional; size may vary.

. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Leads N 44

Lead Pitch e 0.80 BS C

Overall Height A – – 1.20

Molded Package Thickness A2 0.95 1.00 1.05

Standoff A1 0.05 – 0.15

Foot Length L 0.45 0 .60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° 3.5° 7°

Overall Width E 12.00 BSC

Overall Length D 12.00 BSC

Molded Package Width E1 10.00 BSC

Molded Package Length D1 10.00 BSC

Lead Thickness c 0.09 – 0. 20

Lead Width b 0.30 0 .37 0. 45

Mold Draft Angle Top α11° 12° 13°

Mold Draft Angle Bottom β11° 12° 13°

NOTE 1 NOTE 2

123

Microchip Technology Drawing C04-076

PIC18F2455/2550/4455/4550

44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package is saw singulated.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 44

Pitch e 0.65 BSC

Overall Height A 0.80 0 .90 1. 00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Width E 8.00 BSC

Exposed Pad Width E2 6.30 6.45 6.80

Overall Length D 8.00 BSC

Exposed Pad Length D2 6.30 6.45 6.8 0

Contact Width b 0.25 0.30 0.38

Contact Length L 0.30 0.40 0.50

Contact-to-Exposed Pad K 0.20 – –

DEXPOSED

PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

A3A1

Microchip Technology Drawing C04-103

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

APPENDIX A: REVISION HISTORY

Revision A (May 2004)

Original data sheet for PIC18F2455/2550/4455/4550

devices.

Revision B (October 2004)

This rev is ion in cl ude s updates to the Elec tric al Spe ci fi-

cations in Section 28.0 “Electrical Characteristics”

and includes minor corrections to the data sheet text.

Revision C (February 2006)

This revision includes updates to Section 19.0 “Master

Synchronous Serial Port (MSSP) Module”,

Section 20.0 “Enhanced Universal Synchronous

Asynchronous Receiver T ransmitter (E USART)” and

the Electrical Specifications in Section 28.0 “Electrical

Characteristics” and includes minor corrections to the

data sheet text.

Revision D (January 2007)

This revision includes updates to the packaging

diagrams.

APPENDIX B: DEVICE

DIFFERENCES

The differences between the devices listed in this data

sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Program Memo ry (Bytes ) 24576 32768 24576 32768

Program Memo ry (Instructions) 12288 16384 12288 16384

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Capture/Compare/PWM Modules 2 2 1 1

Enhanced Capture/Compare/

PWM Modules 0011

Parallel Communications (SPP) No No Yes Yes

10-Bit Analog-to-Digital Module 10 input channels 10 input channels 13 input channels 13 input channels

Packages 28-pin PDIP

28-pin SOIC 28-pin PDIP

28-pin SOIC 40-pin P DIP

44-pin TQFP

44-pin QFN

40-pin P DIP

44-pin TQFP

44-pin QFN

PIC18F2455/2550/4455/4550

APPENDIX C: CONVERSION

CONSIDERATIONS

This appendix discusses the considerations for

converting from previous versions of a device to the

ones listed in this data sheet. Typically, these changes

are due to the differences in the process technology

used. An example of this type of conversion is from a

PIC16C74A to a PIC16C74B.

Not Applicable

APPENDIX D: MIGRATION FROM

BASELINE TO

ENHANCED DEVICES

This section disc usses how to migrate fr om a Baseline

device (i.e., PIC16C5X) to an Enhanced MCU device

(i.e., PIC18FXXX).

The following are the list of modifications over the

PIC16C5X mic roc on trol ler fam il y:

Not Currently Av ail able

PIC18F2455/2550/4455/4550

APPENDIX E: MIGRATION FROM

MID-RANGE TO

ENHANCED DEVICES

A detailed discussion of the differences between the

mid-range MCU devices (i.e., PIC16CXXX) and the

enhanced devices (i.e., PIC18FXXX) is provided in

AN716, “Migrating Designs from PIC16C74A/74B to

PIC18C442”. The changes discussed, while device

specific, are generally applicable to all mid-range to

enhanced device migrations.

This Ap plicatio n Note is availab le as L iterature Nu mber

DS00716.

APPENDIX F: MIGRATION FROM

HIGH-END TO

ENHANCED DEVICES

A detailed discussion of the migration pathway and

differences between the high-end MCU devices (i.e.,

PIC17CXXX) and the enhanced devices (i.e.,

PIC18FXXX) is provided in AN726, “PIC17CXXX to

PIC18CXXX Migration”. This Application Note is

available as Literature Number DS00726.

PIC18F2455/2550/4455/4550

NOTES:

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 413
PIC18F2455/2550/4455/4550
INDEX
A
A/D ................................................................................... 259
Acquisition Requirements  ......................... ............. ..264
ADCON0 Register ....................................................259
ADCON1 Register ....................................................259
ADCON2 Register ....................................................259
ADRESH Register  ............................................259, 262
ADRESL Register ....................................................259
Analog  Port Pins, Configur in g  .............................. ....266
Associ a te d  Re g i st e rs ............................ ...................26 8
Configuring the Module ............................................263
Conversion Clock (TAD) ........................................... 265
Conversi o n  Re quirements  ........................ ...............398
Conversion Status (GO/DONE Bit) ..........................262
Conversions .............................................................267
Converter Characteristics  ........................................397
Conv e rter In terru p t, Con fig u ri n g   ................ ..... ...... ...26 3
Discharge .................................................................267
Operation in Power-Managed Modes ......................266
Selecting and Configuring 
Acqui sition Time  ........ ..................... .................265
Special Event Trigger (CCP2)  ..................................268
Special Event Trigger (ECCP) .................................150
Use of the CCP2 Trigger ..........................................268
Absolute Maximum Ratings .............................................361
AC (Timing) Characteristics .............................................378
Load Conditions for Device Timing 
Specifications ...................................................379
Parame te r  Symbology  ......... ....................................378
Temperature and Voltage Specifications ................. 379
Timing Conditions ............ .. .... ..... .. .... .. .. .. .... ..... .... .. ..379
AC Characteristics
Internal RC Accuracy ...............................................381
Access Bank
Mapping with Indexed Literal Offset Mode .................77
ACKSTAT ........................................................................227
ACKSTAT Status Flag  .....................................................227
ADCON0 Register ............................................................259
GO/DONE Bit ...........................................................262
ADCON1 Register ............................................................259
ADCON2 Register ............................................................259
ADDFSR ..........................................................................350
ADDLW ............................................................................ 313
ADDULNK ........................................................................350
ADDWF ............................................................................ 313
ADDWFC .........................................................................314
ADRESH Register ............................................................259
ADRESL Register  ....................................................259, 262
Analog-to-Digital Converter. See A/D.
and BSR .......... .. .. .. .. ....... .. .. .. .. .. .... .. ..... .. .. .. .... .. .. .. ..... .... .. .. ..77
ANDLW ............................................................................ 314
ANDWF ............................................................................ 315
Assembler
MPASM Assembler ..................................................358
B
Baud Rate Generator . . .....................................................223
BC .................................................................................... 315
BCF ..................................................................................316
BF ....................................................................................227
BF Statu s Flag  .. ........................... ............................ ........227
Block Diagrams
A/D ........................................................................... 262
Analog Input Model .................................................. 263
Baud Rate Generator  .............................................. 223
Capture Mode Operation ......................... .. .... .. .. .. .. .. 143
Comparator Analog Input Model ........................ .. .. .. 273
Comparator I/O Operating Modes ........................... 270
Comparator Output ........... ..................... .................. 272
Comparator Voltage Reference ......................... .... .. 276
Comparator Voltage Reference Output 
Buffe r Ex a mple .............................. .................. 277
Compare Mode Operation ........................... .... .. .. .. .. 144
Device Clock .............................................................. 24
Enhanced PWM ..................................................... .. 151
EUSART Receive .................................................... 251
EUSART Transmit ................................................... 248
External Power-on Reset Circuit 
(Slow VDD Power-up)  ........................................ 45
Fail-Safe Clock Monitor ........................................... 300
Generic I/O Port  ....................................................... 111
High/Low-Voltage Detect with External Input  ........ .. 280
MSSP (I2C Master Mode) ........................................ 221
MSSP (I2C Mode) ................. .... .. .. .... .. ....... .. .. .... .. .. .. 202
MSSP (SPI Mode)  ................................................... 193
On-Chip  Rese t Circuit ................... ............... .............. 43
PIC18F2455/2550 ..................................................... 10
PIC18F4455/4550 ..................................................... 11
PLL (HS Mode) .......................................................... 26
PWM Operation (Simplified) .................................... 146
Reads from Flash Program Memory  ......................... 83
Single Comparator  ................................................... 271
SPP Data Path  ........................................................ 187
Table Read Operation ........................ ..... .... .. .. .... .. .. .. 79
Table Write Operation  ........................ ..................... .. 80
Table Writes to Flash Program Memory .............. ...... 85
Timer0 in 16-Bit Mode ............................................. 126
Timer0 in 8-Bit Mode ............................................... 126
Timer1 ..................................................................... 130
Timer1 (16-Bit Read/Write Mode) ............................ 130
Timer2 ..................................................................... 136
Timer3 ..................................................................... 138
Timer3 (16-Bit Read/Write Mode) ............................ 138
USB Interrupt Logic ................................................. 177
USB Peripheral and Options  ......................... .... .... .. 163
Watchdog Timer  .......... .. ....... .... .. .... .. .. ....... .... .. .. .... .. 297
BN .................................................................................... 316
BNC ................................................................................. 317
BNN ................................................................................. 317
BNOV .............................................................................. 318
BNZ ................................................................................. 318
BOR. See Brown-out Reset.
BOV ................................................................................. 321
BRA ................................................................................. 319
Break Character (12-Bit) Transmit and Receive .............. 253
BRG. See Baud Rate Generator.
Brown-o u t Re set (BOR) ......... ............... ..................... ........ 46
Detecting ................................................................... 46
Disabling in Sleep Mode ............................................ 46
Software Enabled  .......... ......... .... .. .... ....... .... .... .. .... .... 46
BSF .................................................................................. 319
BTFSC ............................................................................. 320
BTFSS ............................................................................. 320
BTG ................................................................................. 321
BZ .................................................................................... 322

PIC18F2455/2550/4455/4550
DS39632D-page 414 Preliminary © 2007 Microchip Technology Inc.
C
C Compilers
MPLAB C18 ................................. ..................... .......358
MPLAB C30 ................................. ..................... .......358
CALL ................................................................................ 322
CALLW .............................................................................351
Capture (CCP Module) .....................................................143
CCP Pin Configuration .............................................143
CCPRxH:CCPRxL Reg i s te rs  ..... ......... .............. .......143
Prescaler .................................................................. 143
Softwa re In terrupt  .............. ..................... .................143
Timer1/Timer3 Mode Selection ....................... .. .......143
Capture (ECCP Module) ................................. .. .... .. .... .....150
Capture/Compare (CCP Module)
Associ a te d  Re g i sters  ........... ........................... .........145
Capture/Compare/PWM (C CP) .............. ............... ...........141
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................142
CCP2 Pin Assignment  .............................................142
CCPRxH Regist e r .................... ............... .................142
CCPRxL Regi ster ............... ..................... .................142
Compare Mode. See Compare.
Interaction of Two CCP Modules for 
Timer Resources ..............................................142
Module Configuration ...............................................142
Clock Sources ....................................................................31
Effects of Power-Managed Modes .................. .... .......33
Selectin g  th e  31 k Hz So u r ce ............................. .........31
Selection  Using OSCCON Register ........ ........ ...........31
CLRF ................................................................................323
CLRWDT ..........................................................................323
Code Examples
16 x 16 Signed Multiply Routine  ................................96
16 x 16 Unsigned Multiply Routine  ............................96
8 x 8 Signed Multiply Routine  ..................... .. .. .. ....... ..95
8 x 8 Unsigned Multiply Routine  .............................. ..95
Changing Between Capture Prescalers ...................143
Computed  GOTO Usin g  a n  Offset Value ...... .............60
Data EEPROM Read ......... ..................... ...................91
Data EEPROM Refr e sh Rou tin e  ..................... ...........92
Data EEPROM Wr ite   ............... ..................... .............91
Erasing a  Fl a sh Pr o g ram Memory Row .. ............... ....84
Fast Register Stack ....................................................60
How to Clear RAM (Bank 1) Using 
Indirect Addressing ............................................72
Implementing a Real-Time Clock Using a 
Timer1 Interrupt Service  ..................................133
Initializing PORTA ....................................................111
Initializing PORTB ....................................................114
Initializing PORTC ....................................................117
Initializing PORTD ....................................................120
Initializing PORTE ....................................................123
Loading the SSPBUF (SSPSR) R egister .................196
Reading a Flash Program Memory Word  ..................83
Saving STATUS, WREG and BSR 
Registers in RAM .............................................109
Writing to Flash Program Memory  ... ....................86–87
Code Protection  ...............................................................285
COMF ...............................................................................324
Comparator ......................................................................269
Analog Input Connection Considerations . ................273
Associ a te d  Re g i sters  ........... ........................... .........273
Configuration ............................................................270
Effects of a Reset  .....................................................272
Interrupts .................................................................. 272
Operation ................................................................. 271
Operation During Sleep ........................................... 272
Outputs .................................................................... 271
Reference ................................................................ 271
External Signal  ................................................ 271
Internal Signal .................................................. 271
Response Time ............................. .... .... .... ......... .... .. 271
Comparat o r Spe cifications  ............. ............... ............... .... 375
Comparator Voltage Reference ................................. .. .. .. 275
Accura cy  a n d Err o r ................... ..................... .......... 276
Associ a te d  Re g i sters ... ............... ........................... .. 27 7
Configuring .............................................................. 275
Connection Considerations .............................. .... .. .. 276
Effects of a Reset  ................ ..................... ............... 276
Operation During Sleep ........................................... 276
Compare (CCP Module)  ................ ....... .... .. .... .. ....... .... .. .. 144
CCP Pin Configuration ............................................. 144
CCPRx Register  ......................... ..................... ........ 14 4
Softwar e  In terrupt .............. ..................... ................. 144
Special Event Trigger  .............................. 139, 144, 268
Timer1/Timer3 Mode Selection ................................ 144
Compare (ECCP Module) ............................. .. .... ....... .. .. .. 150
Special Event Trigger .............................................. 150
Configuration Bits  ............................................................ 286
Configuration Register Protection ....................................305
Context Saving During Interrupts ..................................... 109
Conversi on  Co nsid e rations ...... ............... ............... .......... 410
CPFSEQ .......................................................................... 324
CPFSGT .......................................................................... 325
CPFSLT ........................................................................... 325
Crystal Oscillator/Ceramic Resonator ... .. ........................... 25
Customer Change Notification Service .......................... .. 423
Custome r Notification Ser v ice  .......... .............. ............... .. 42 3
Customer Support .......................... ........... .... .... ........... .... 423
D
Data Addre ssing Modes  ............................... ..................... 72
Comparing Addressing Modes with the 
Extended Instruction Set Enabled ..................... 76
Direct ......................................................................... 72
Indexed  Literal Offset  ...... ..................... ..................... 75
Indirect ....................................................................... 72
Inherent and Literal  .................................................... 72
Data EEPROM
Code Protection ....................................................... 305
Data EEPRO M Mem ory ............. ..................... ................... 89
Associ a te d  Re g i sters ... ............... ........................... .... 93
EECON1 and EECON2 Regist e rs  ..................... ........ 89
Operation During Code-Protect ................................. 92
Protection Agains t Sp u rious Write ............................. 92
Reading ..................................................................... 91
Using ......................................................................... 92
Write Verify ................................................................ 91
Writing ....................................................................... 91
Data Memor y .......... ..................... ..................... ................. 63
Access Ban k ........................ .................................. .... 65
and the Extended Instruction Set  .............................. 75
Bank Select Register (BSR)  ......................................63
General Purpose Registers  ....................................... 65
Map for PIC18F2455/2550/4455/4550 Devices ......... 64
Special Function Registers ........................................66
Map .................................................................... 66
USB RAM  ............................ ............................ .......... 63
DAW ................................................................................ 326
DC and AC Characteristics
Graphs and Tables . ................................................. 399

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 415
PIC18F2455/2550/4455/4550
DC Characteristics ...........................................................372
Power-Down and Supply Current  ............................364
Supply Voltage .........................................................363
DCFSNZ ..........................................................................327
DECF ...............................................................................326
DECFSZ ...........................................................................327
Dedicate d  ICD/ICSP Port ........... ............................ ..........305
Development Support  ......................................................357
Device Differences ...........................................................409
Device Overview ..................................................................7
Features (table)  .................. ............................ ..............9
New Core Features ......................................................7
Other Special Features ................................................8
Device Reset Timers ..........................................................47
Oscillator Start-up Timer (OST) .................................47
PLL Lock Time-out .....................................................47
Power-up  Tim e r ( PWRT)   ... ..................... ............... ....47
Direct Add ressing .............................. ........................... ......73
E
Effect on Standard PIC Instructions ................ .. ....... .... .. ....75
Effect on Standard PIC MCU Instructions ........................354
Electrical Characteristics ..................................................361
Enhanced Capture/Compare/PWM (ECCP) ....................149
Associ a te d  Re g i sters .................... ...........................162
Capture and Compare Modes . .................................150
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration .......................................150
Pin Configurations for ECCP1  .................................150
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode  ...............................................150
Timer Resources ......................................................150
Enhanced Universal Synchronous As ynchr onous 
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acqui sition Time ................... ..................... ........264
A/D Minimu m Charging Time .... .............. .................264
Calculating the Minimum Required 
A/D Acqui sition Time  ........ ..................... ..........264
Errata ...................................................................................5
EUSART
Asynchronous Mode ................................................247
12-Bit Break Transmit and Receive .................253
Associated Registers, Receive ........................251
Associ a te d  Re g isters, Transmit .......... .............249
Auto-Wake-up on Sync Break Character .........252
Receiver ...........................................................250
Setting up 9-Bit Mode with 
Address Detect ........................................250
Transmitter .......................................................247
Baud Rate Generator
Operation in Power-Managed Modes ..............241
Baud Rate Generator (BRG)  . ...................................241
Associ a te d  Re g i sters ................ .......................242
Auto-Baud Rate Detect ..................... ...............245
Baud Rate Error, Calculating ..................... .... ..242
Baud Rates, Asynchronous Modes   .................243
High Baud Rate Select (BRGH Bit)  .................241
Sampling ..........................................................241
Synchronous Master Mode ......................................254
Associated Registers, Receive ........................256
Associ a te d  Re g isters, Transmit .......... .............255
Reception .........................................................256
Transmission ...................................................254
Synchronous Slave Mode ...................................... .. 257
Associa ted  Re gi sters, Receive .............. .......... 258
Associ a te d  Registers, Transmit ..... .................. 257
Reception ........................................................ 258
Transmission ................................................... 257
Extended Instruction Set  ................................................. 349
ADDFSR .................................................................. 350
ADDULNK ............................................................... 350
and Using MPLAB IDE Tools  .................................. 356
CALLW .................................................................... 351
Considerations for Use ............................................ 354
MOVSF .................................................................... 351
MOVSS .................................................................... 352
PUSHL ..................................................................... 352
SUBFSR .................................................................. 353
SUBULNK ................................................................ 353
Syntax ...................................................................... 349
External Clock Input ........................................................... 26
F
Fail-Safe Clock Monitor  ........................................... 285, 300
Exiting  th e  Op e ration .............. ..................... ............ 300
Interrupts in Power-Managed Modes  ...................... 301
POR or Wake-up from Sleep ................................... 301
WDT During Oscillator Failure .... ........ ......... ........ .... 300
Fast Register Stack  ........................................................... 60
Firmware Instructions ...................................................... 307
Flash Pr o g ram Memory ............................ ......................... 79
Associ a te d  Re g i sters ................................. ................ 87
Control Reg i s te rs ............................ ............... ............ 80
EECON1 and EECON2 .............. ..................... .. 80
TABLAT (Ta b l e  Lat ch) Register ........................ 82
TBLPTR (Tab l e  Po in ter) Registe r  ...................... 82
Erase Sequence ........................................................ 84
Erasing ...................................................................... 84
Operation During Code-Protect ................................. 87
Protection Agains t Sp u rious Writes .... ..................... .. 87
Reading ..................................................................... 83
Table Pointer
Boundaries Based on Operation  ................. .... .. 82
Table Pointer Boundaries ................. ................. ...... .. 82
Table Reads and Table Writes .......................... .... .. .. 79
Unexpected Termination o f Write ...................... ........ 87
Write Sequence ......................................................... 85
Write Verify ................................................................ 87
Writing To .................................................................. 85
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 328
H
Hardware Mult ip lier ....................... .............. ............... ........ 95
Introduction ................................................................ 95
Operation ................................................................... 95
Performance Comparison  .......................................... 95

PIC18F2455/2550/4455/4550
DS39632D-page 416 Preliminary © 2007 Microchip Technology Inc.
High/Lo w -V o ltage Detect  ................... ..................... .........279
Applications ..............................................................282
Associ a te d  Re g i sters  ........... ........................... .........283
Characteristics .........................................................377
Curren t Cons u mption ................. ..................... .........281
Effects of a Reset  .....................................................283
Operation .................................................................280
During Sleep ....................................................283
Setup ........................................................................281
Start- u p  Time  .... ........................... ..................... .......281
Typica l Ap p l ication ......... ..................... .....................282
HLVD. See High/Low-Voltage Detect. 
I
I/O Ports .......................... .................................. ...............111
I2C Mode (MSSP)
Acknowledge Sequence Timing ...............................230
Associ a te d  Re g i sters  ........... ........................... .........236
Baud Rate Generator . . .............................................223
Bus Collision
During a Repeated Start Condition ..................234
During a Stop Condition ...................................235
Clock Arbitration .......................................................224
Clock Stretching .......................................................216
10-Bit Slave Receive Mode (SEN = 1) .............216
10-Bit Slave Transmit Mode .............................216
7-Bit Slave Receive Mode (SEN = 1) ...............216
7-Bit Slave Transmit Mode ...............................216
Clock Synchronization a nd the CKP Bit .......... .........217
Effect of a Reset  ......................................................231
General Call Address Support  .................................220
I2C Clock Rate w/BRG .............................................223
Master Mode ............................................................221
Operation ......................................................... 222
Reception .........................................................227
Repeated Start Condition Timing .....................226
Start Condition Timing  ...................... .... .. .... .....225
Transmission ....................................................227
Transmit Sequence ......................... .... .... .. .......222
Multi-Master Communication, Bus Collision 
and Arbitration ............................. .. .. .. .. .. .. .. .......231
Multi-Master Mode  ...................................................231
Operation .................................................................207
Read/Write Bit Information (R/W Bit) ...............207, 209
Registers ..................................................................202
Serial  C l o c k (R B1/AN10/I N T1/S C K/SCL)  ............ ....209
Slave Mode ..............................................................207
Addressing ....................................................... 207
Addressing Masking .........................................208
Reception .........................................................209
Transmission ....................................................209
Sleep Operation .......................................................231
Stop Condition Timing .................. ..................... .......230
ID Locations .............................................................285, 305
Idle Modes ..........................................................................39
INCF ................................................................................. 328
INCFSZ ............................................................................329
In-Circuit Debugger ..........................................................305
In-Circuit Serial Programming (ICSP)  ......................285, 305
Indexed Literal Offset Addressing
and Standard PIC18 Instructions .............................354
Indexed Literal Offset Mode .................................75, 77, 354
Indirect Addressing  ............................................................73
INFSNZ ............................................................................329
Initialization Conditions for all Registers  . .....................51–55
Instruction Cycle ................................................................ 61
Clocking Scheme ....................................................... 61
Flow/Pipelining ........................................................... 61
Instruction Set .................................................................. 307
ADDLW .................................................................... 313
ADDWF .................................................................... 313
ADDWF (Indexed Literal Offset mode) .................... 355
ADDWFC ................................................................. 314
ANDLW .................................................................... 314
ANDWF .................................................................... 315
BC ............................................................................ 315
BCF ......................................................................... 316
BN ............................................................................ 316
BNC ......................................................................... 317
BNN ......................................................................... 317
BNOV ...................................................................... 318
BNZ ......................................................................... 318
BOV ......................................................................... 321
BRA ......................................................................... 319
BSF .......................................................................... 319
BSF (Indexed Literal Offset mode) .......................... 355
BTFSC ..................................................................... 320
BTFSS ..................................................................... 320
BTG ......................................................................... 321
BZ ............................................................................ 322
CALL ........................................................................322
CLRF ....................................................................... 323
CLRWDT ................................................................. 323
COMF ...................................................................... 324
CPFSEQ .................................................................. 324
CPFSGT .................................................................. 325
CPFSLT ................................................................... 325
DAW ........................................................................ 326
DCFSNZ .................................................................. 327
DECF ....................................................................... 326
DECFSZ .................................................................. 327
General Format ...................... ......... .... .... .... ......... .... 309
GOTO ...................................................................... 328
INCF ........................................................................ 328
INCFSZ .................................................................... 329
INFSNZ .................................................................... 329
IORLW ..................................................................... 330
IORWF ..................................................................... 330
LFSR ....................................................................... 331
MOVF ...................................................................... 331
MOVFF .................................................................... 332
MOVLB .................................................................... 332
MOVLW ................................................................... 333
MOVWF ................................................................... 333
MULLW .................................................................... 334
MULWF .................................................................... 334
NEGF ....................................................................... 335
NOP ......................................................................... 335
Opcode Field Descriptions ....................................... 308
POP ......................................................................... 336
PUSH ....................................................................... 336
RCALL ..................................................................... 337
RESET ..................................................................... 337
RETFIE .................................................................... 338
RETLW .................................................................... 338
RETURN .................................................................. 339
RLCF ....................................................................... 339
RLNCF ..................................................................... 340
RRCF ....................................................................... 340
RRNCF .................................................................... 341

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 417
PIC18F2455/2550/4455/4550
SETF ........................................................................341
SETF (Indexed Literal Offset mode) ........................355
SLEEP .....................................................................342
Standard Instructions ...............................................307
SUBFWB ..................................................................342
SUBLW .................................................................... 343
SUBWF .................................................................... 343
SUBWFB ..................................................................344
SWAPF .................................................................... 344
TBLRD .....................................................................345
TBLWT .....................................................................346
TSTFSZ ...................................................................347
XORLW ....................................................................347
XORWF ....................................................................348
INTCON Register
RBIF Bit .............................. ............................ ..........114
INTCON Registers .............................................................99
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block  .....................................................27
Adjustment ................................................................. 27
INTHS, INTXT, INTCKO and INTIO Modes ...............27
OSCTUNE Regis te r . .............. ............... .....................27
Internal RC Oscillator
Use with WDT ..........................................................297
Inter n e t Ad d ress ............. ........................... .......................423
Inter rupt Sourc es  ................... ........................... ...............285
A/D Convers i o n  Compl e te   ... ............... ............... ......263
Capture Co mplete (CCP) ..... ............... ............... ......143
Compare Complete (CCP) ..... ......... ............... ..........144
Interrupt-on-Change (RB7:RB4)  ................. .............114
INTn Pin ...................................................................109
PORTB, Interrupt-on-Change  ..................................109
TMR0 .......................................................................109
TMR0 Overflow ........................................................127
TMR1 Overflow ........................................................129
TMR2 to PR2 Match (PWM)  ............................146, 151
TMR3 Overflow ................................................137, 139
Interrupts ............................................................................97
Logic (diagram) ..........................................................98
USB ............................................................................97
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag 
(RBIF Bit) ..... ................................. ...................114
INTOSC Frequency Drift ............................. ...... ......... ...... ..27
INTO SC, INTRC.  See Internal Oscillator Block.
IORLW .............................................................................330
IORWF ............................................................................. 330
IPR Regist e rs .... ............... ..................... ..................... ......106
L
LFSR ................................................................................331
Low-Voltage ICSP Programmin g. See Single-Su pply 
ICSP Programm ing.
M
Master Clear Reset (MCLR) ..............................................45
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization .........................................................57
Data Memor y  .... ..................... ..................... ...............63
Program Memory .......................................................57
Mem o r y Prog ra m min g  Requireme n ts .... .. ...... ...... ..... .......374
Microc h i p  In ternet Web Site  ..... ..................... ...................42 3
Migration from Baseline to Enhanced Devices  ................410
Migration from High-End to Enhanced Devices ...............411
Migration from Mid-Range to Enhanced Devices  ............411
MOVF .............................................................................. 331
MOVFF ............................................................................ 332
MOVLB ............................................................................ 332
MOVLW ........................................................................... 333
MOVSF ............................................................................ 351
MOVSS ............................................................................ 352
MOVWF ........................................................................... 333
MPLAB ASM30 Assembler, Linker, Librarian .................. 358
MPLAB ICD 2 In-Circuit Debugger ............................ .... .. 359
MPLAB ICE 2000 High-Perf orm ance 
Universal In-Circuit Emula tor .............. ............... ...... 359
MPLAB ICE 4000 High-Perf orm ance 
Universal In-Circuit Emula tor .............. ............... ...... 359
MPLAB Integrated Development 
Environ ment Software  . ............................ ................ 357
MPLAB PM3 Device Programmer ................................... 359
MPLINK Object Linker/MPLIB Object Librarian ............... 358
MSSP
ACK Pulse ................... .. ....... .. .... .. .... .. ....... .. .... 207, 209
Control Registers (general)  ..................................... 193
I2C Mode. See I2C Mode.
Module Overview ..................................................... 193
SPI Master/Slave Connection  .................................. 197
SPI Mode. See SPI Mode.
SSPBUF .................................................................. 198
SSPSR .................................................................... 198
MULLW ............................................................................ 334
MULWF ............................................................................ 334
N
NEGF ............................................................................... 335
NOP ................................................................................. 335
O
Oscillator Configuration  . .................................................... 23
EC .............................................................................. 23
ECIO .......................................................................... 23
ECPIO ....................................................................... 23
ECPLL ....................................................................... 23
HS .............................................................................. 23
HSPLL ....................................................................... 23
INTCKO ..................................................................... 23
Internal Oscillator Block ............................................. 27
INTHS ........................................................................ 23
INTIO ......................................................................... 23
INTXT ........................................................................ 23
Oscillator Modes and USB Operation ........................ 23
XT .............................................................................. 23
XTPLL ........................................................................ 23
Oscillat o r Selection .... ............... .............. ............... .......... 285
Oscillato r S ettings for USB ......... .............. ......... ........ ........ 29
Oscillator S tart-up Timer (OST) ......................... .......... 33, 47
Oscillat or S wi tching  ..... ........ ......... .............. ............... ........ 31
Oscillato r Trans itions ..... ....................... ......... .................... 32
Oscillator, Timer1 ..................................................... 129, 139
Oscillator, Timer3 ............................................................. 137
P
Packagi n g  In fo rmation ....... ............... ........................... .... 401
Details ...................................................................... 403
Marking .................................................................... 401
PICSTART Plus Development Programmer  .................... 360
PIE Registers  ................................................................... 104

PIC18F2455/2550/4455/4550
DS39632D-page 418 Preliminary © 2007 Microchip Technology Inc.
Pin Functions
MCLR/VPP/RE3 ....................................................12, 16
NC/ICCK/ICPGC ........................................................21
NC/ICDT/ICPGD ........................................................ 21
NC/ICPORTS .............................................................21
NC/ICRST/ICVPP .......................................................21
OSC1/CLKI ..........................................................12, 16
OSC2/CLKO/RA6 ................................................12, 16
RA0/AN0 .............................................................. 13, 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF-/CVREF ........................................ 13, 17
RA3/AN3/VREF+ ...................................................13, 17
RA4/T0CKI/C1OUT/RCV ..................................... 13, 17
RA5/AN4/SS/HLVDIN/C2OUT .............................13, 17
RB0/AN12/INT0/FLT0/SDI/SDA ..........................14, 18
RB1/AN10/INT1/SCK/SCL ................................... 14, 18
RB2/AN8/INT2/VMO ............................................ 14, 18
RB3/AN9/CCP2/VPO ........................................... 14, 18
RB4/AN11/KBI0 .........................................................14
RB4/AN11/KBI0/CSSPP ............................................ 18
RB5/KBI1/PGM .................................................... 14, 18
RB6/KBI2/PGC ....................................................14, 18
RB7/KBI3/PGD ....................................................14, 18
RC0/T1OSO/T13CKI ...........................................15, 19
RC1/T1OSI/CCP2/UOE ....................................... 15, 19
RC2/CCP1 .................................................................15
RC2/CCP1/P1A .........................................................19
RC4/D-/VM ...........................................................15, 19
RC5/D+/VP ..........................................................15, 19
RC6/TX/CK ..........................................................15, 19
RC7/RX/DT/SDO .................................................15, 19
RD0/SPP0 ..................................................................20
RD1/SPP1 ..................................................................20
RD2/SPP2 ..................................................................20
RD3/SPP3 ..................................................................20
RD4/SPP4 ..................................................................20
RD5/SPP5/P1B .......................................................... 20
RD6/SPP6/P1C ..........................................................20
RD7/SPP7/P1D ..........................................................20
RE0/AN5/CK1SPP ..................................................... 21
RE1/AN6/CK2SPP ..................................................... 21
RE2/AN7/OESPP .......................................................21
VDD .......................................................................15, 21
VSS .......................................................................15, 21
VUSB .....................................................................15, 21
Pinout I/O Descriptions
PIC18F2455/2550 ......................................................12
PIC18F4455/4550 ......................................................16
PIR Regist e rs ........ ............... ..................... .............. .........102
PLL Frequency Multiplier  ...................................................26
HSPLL, XTPLL, ECPLL and ECPIO 
Oscillator Modes ................................................26
PLL Lock Time-out .............................................................47
POP ..................................................................................336
POR. See Power-on Reset.
PORTA
Associ a te d  Re g i sters  ........... ........................... .........113
I/O Summary ................ ................................. ...........112
LATA Register ..........................................................111
PORTA Register ......................................................111
TRISA Register ........................................................111
PORTB
Associ a te d  Re g i sters ... ............... ........................... .. 11 6
I/O Summary ..... ............................ ........................... 115
LATB Register  ..... ..................... ........................... .... 114
PORTB Register ...................................................... 114
RB1/ AN10 /I N T1/S C K / S C L Pi n   .. .. ...... ...... .. ..... ...... .. . 209
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 114
TRISB Register  ........................................................ 114
PORTC
Associ a te d  Re g i sters ... ............... ........................... .. 11 9
I/O Summary ..... ............................ ........................... 118
LATC Register .........................................................117
PORTC Register ...................................................... 117
TRISC Regist e r . ..................... ..................... ............. 117
PORTD
Associ a te d  Re g i sters ... ............... ........................... .. 12 2
I/O Summary ..... ............................ ........................... 121
LATD Register .........................................................120
PORTD Register ...................................................... 120
TRISD Regist e r . ..................... ..................... ............. 120
PORTE
Associ a te d  Re g i sters ... ............... ........................... .. 12 4
I/O Summary ..... ............................ ........................... 124
LATE Register  ..... ..................... ........................... .... 123
PORTE Register ...................................................... 123
TRISE Register  ........................................................ 123
Postscaler, WDT
Assignment (PSA Bit ) ........................................ ...... 127
Rate Select (T0PS2:T0PS0 Bits)  ............................. 12 7
Power-Managed Modes ............................................... .... .. 35
and Multiple Sleep Commands .................................. 36
and PWM Operation ................................................ 161
Clock Sources ............................................................ 35
Clock Transitions and Status Indicators  .................... 36
Entering ..................................................................... 35
Exiting Idle and Sleep Modes .............................. .... .. 41
by Interrupt  ........................................................ 41
by Reset  ............................................................ 41
by WDT Time-out  .............................................. 41
Without an Oscillator Start-up Delay  .................42
Idle ............................................................................. 39
Idle Modes
PRI_IDLE ........................................................... 40
RC_IDLE ........................................................... 41
SEC_IDLE ......................................................... 40
Run Modes  ................................................................ 36
PRI_RUN ...........................................................36
RC_RUN ............................................................ 37
SEC_RUN ......................................................... 36
Selecting .................................................................... 35
Sleep ......................................................................... 39
Summary (table) .. ..................... ........................... ...... 35
Power-on Reset (POR) ...................................................... 45
Oscillato r Start-up Timer (OST) ......................... ........ 47
Power-up Timer (PWRT) ........................................... 47
Time-out Sequence  .................................. ......... .. .... .. 47
Power-up Delays  ............................................................... 33
Power-up Timer (PWRT) ............................................. 33, 47
Prescaler
Timer2 ..................................................................... 152
Presca le r, Timer0  .................... ..................... ................... 127
Assignment (PSA Bit ) ........................................ ...... 127
Rate Select (T0PS2:T0PS0 Bits)  ............................. 12 7

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 419
PIC18F2455/2550/4455/4550
Presca le r, Timer2 ............. ..................... ..................... ......147
PRI_IDLE Mode .................................................................40
PRI_RUN Mode .................................................................36
Program Counter  ...............................................................58
PCL, PCH and PCU Registers ............................... ....58
PCLATH and PCLATU Registers  .................... .... .... ..58
Program Mem ory
and the Extended Instruction Set ...............................75
Code Protection .......................................................303
Instructions .................................................................62
Two-Word ..........................................................62
Inter rupt Vector  ............................. .............................57
Look-up Tables  ............ .... .... ......... .... .... .... ........... .... ..60
Map and Stack (diagram)  ...........................................57
Reset Vec to r ........ ........................... ...........................57
Program Verification and Code Protection .......................302
Associ a te d  Re g i sters .................... ...........................302
Programming, Device Instructions ...................................307
Pulse-Width Modulation. See PWM (CCP Module) 
and PWM (ECCP Module).
PUSH ............................................................................... 336
PUSH and PO P In structions .... .................................. ........59
PUSHL ............................................................................. 352
PWM (CCP Module)
Associ a te d  Re g i sters .................... ...........................148
Auto-Shutdown (CCP1 Only) ...................................147
Duty Cycle .................. ............... ..................... ..........146
Example Frequencies/Resolutions  ..........................147
Period .......................................................................146
Setup for PWM Operation ......... ..................... ..........147
TMR2 to PR2 Match  ................................................146
PWM (ECCP Modul e) ........................... ..................... ......151
CCPR1H:CCPR1L Registers ...................................151
Direction Change in Full-Bridge 
Output Mode .............. .. .. ..... .... .. .. .. .. .. ....... .. .. .. ..156
Duty Cycle .................. ............... ..................... ..........152
Effects of a Reset .....................................................161
Enhanced PWM Auto-Shutdown  .............................158
Enhanced PWM Mode ..... .... ........... .... .... .... ........... ..151
Example Frequencies/Resolutions  ..........................152
Full-Bridge Application Example ..............................156
Full-Bridge Mode ..................................... .. ......... .... ..155
Half-Bridge Mode .....................................................154
Half-Bridge Output Mode 
Applications Example  ......................................154
Operation in Power-Managed Modes ......................161
Operation with Fail-Safe Clock Monitor  ...................161
Output Co nf ig u r a tio n s ............... ..................... ..........152
Output Relatio n s h i ps (Active-High) ... .......................153
Output Re latio n ships (Activ e -Low )  ................... ........153
Period .......................................................................151
Programmable Dead-Band Delay ............. ......... .... ..158
Setup for PWM Operation ......... ..................... ..........161
Start- u p Co nsid e rations ............ .............. .................160
TMR2 to PR2 Match  ................................................151
Q
Q Clock  ................................ .... .. .... ....... .... .. .... .. .......147, 152
R
RAM. See Data Memory .
RC_IDLE Mode ..................................................................41
RC_RUN Mode ..................................................................37
RCALL .............................................................................337
RCON Register
Bit Sta tu s  Dur i n g  Initializatio n  ................... ............... ..50
Reader Response ............................................................ 424
Register File ................... ..................... ..................... .......... 65
Register File Summary ............................................ .... 67–70
Registers
ADCON0 (A/D Contr o l 0 ) ...... .............. ............... ...... 259
ADCON1 (A/D Contr o l 1 ) ...... .............. ............... ...... 260
ADCON2 (A/D Contr o l 2 ) ...... .............. ............... ...... 261
BAUDCON (Baud Rate Control) .............................. 240
BDnSTAT (Buffer Desc riptor n Status, 
CPU Mode) .......................................... .... .... .... 173
BDnSTAT (Buffer Desc riptor n Status, 
SIE Mode)  ....................................................... 174
CCP1CON (ECCP Control) .. .............. ......... ............ 149
CCPxCON (Standard CCPx Control)  ...................... 141
CMCON (Compara tor Control) ....... ......... .............. .. 269
CONFIG1H (Configuration 1 High) .......................... 288
CONFIG1L (Configuration 1 Low) ........................... 287
CONFIG2H (Configuration 2 High) .......................... 290
CONFIG2L (Configuration 2 Low) ........................... 289
CONFIG3H (Configuration 3 High) .......................... 291
CONFIG4L (Configuration 4 Low) ........................... 292
CONFIG5H (Configuration 5 High) .......................... 293
CONFIG5L (Configuration 5 Low) ........................... 293
CONFIG6H (Configuration 6 High) .......................... 294
CONFIG6L (Configuration 6 Low) ........................... 294
CONFIG7H (Configuration 7 High) .......................... 295
CONFIG7L (Configuration 7 Low) ........................... 295
CVRCON (Comparator Voltage 
Reference Control) .......................................... 275
DEVID1 (De vice  ID 1) ..................... ..................... .... 296
DEVID2 (De vice  ID 2) ..................... ..................... .... 296
ECCP1AS (Enhanced Capture/Compare/PWM 
Auto-Shutdown Control) .................................. 159
ECCP1DEL (PWM Dead-Band Delay) ................ .. .. 158
EECON1 (Data EEPROM Control 1) ............... .... 81, 90
HLVDCON (High/Low-Voltage 
Detect Control) ................................................ 279
INTCON (Interrupt Control)  ....................................... 99
INTCON2 (Interrupt Control 2)  ................................ 100
INTCON3 (Interrupt Control 3)  ................................ 101
IPR1 (Peripheral Interrupt Priority 1) .... ................... 106
IPR2 (Peripheral Interrupt Priority 2) .... ................... 107
OSCCON (Oscillator Control) .................................... 32
OSCTUNE (Oscillator Tuning ) ...... ............... .............. 28
PIE1 (Peripheral Interrupt Enable 1)  . ...................... 104
PIE2 (Peripheral Interrupt Enable 2)  . ...................... 105
PIR1 (Peripheral Interrupt Request 
(Flag) 1 ) .................... ..................... .................. 102
PIR2 (Peripheral Interrupt Request 
(Flag) 2 ) .................... ..................... .................. 103
PORTE .................................................................... 123
RCON (Reset Control) ....................................... 44, 108
RCSTA (Receive Status and Control)  ............. .... .. .. 239
SPPCFG (SP P Configuration)  ........ ............... .......... 188
SPPCON (SPP Control) .......................................... 187
SPPEPS (SPP Endpoint Address 
and Status) ...................................................... 191
SSPCON 1 (M SSP Control 1, I2C Mode)  ................. 204
SSPCON1 (M SSP  Control 1, SPI Mode)  ................ 195
SSPCON 2 (M SSP Control 2, I2C 
Master Mode)  .......................................... .... .... 205
SSPCON 2 (M SSP Control 2, I2C 
Slave Mode)  .................................................... 206
SSPSTAT (MSS P St atus,  I2C Mode)  ...... .. .... .. .. .... .. 203
SSPSTA T  (MSS P St atus, SPI  Mode) ......... ............ . 194

PIC18F2455/2550/4455/4550
DS39632D-page 420 Preliminary © 2007 Microchip Technology Inc.
STATUS ..................................................................... 71
STKPTR (St a ck Poin ter) .. ..................... .............. .......59
T0CON (Timer0 Con trol) ........ ............... .............. .....125
T1CON (Timer1 Con trol) ........ ............... .............. .....129
T2CON (Timer2 Con trol) ........ ............... .............. .....135
T3CON (Timer3 Con trol) ........ ............... .............. .....137
TXSTA (Transmit Status and Control)  .....................238
UCFG (USB Configuration)  .... ............... ...................166
UCON (USB Control)  ........................ ..................... ..164
UEIE (USB Error Interrupt Enable)  ..........................182
UEIR (USB Err o r Interrupt Status) ........ ...................181
UEPn (USB Endpoint n Control) ..............................169
UIE (USB Interrupt Enable) ......................... .... .........180
UIR (USB In te rrupt Sta tu s)  ......................................178
USTAT (USB Status)  ...............................................168
WDTCON (Watchdog Tim er Contro l) .......................298
RESET .............................................................................337
Reset St a te  o f Registers ........................ ............................50
Resets ........................................................................ 43, 285
Brown-out Reset (BOR) ...........................................285
Oscillator Start-up Timer (OST)  . ..............................285
Power-on  Res e t (POR) ................ ..................... .......285
Power-up  Tim e r ( PWRT)  ............. ............... .............285
RETFIE ............................................................................338
RETLW .............................................................................338
RETURN ..........................................................................339
Return Add ress Stack ...................... ..................................58
and Associated Registers  ....................... ...... .... .........58
Return Stack Pointer ( STKPTR)  ........................... .............59
Revision History ...............................................................409
RLCF ................................................................................339
RLNCF .............................................................................340
RRCF ...............................................................................340
RRNCF .............................................................................341
S
SCK ..................................................................................193
SDI ...................................................................................193
SDO .................................................................................193
SEC_IDLE Mode ........... .... ......... .. .... .... ......... .. .... .... .... .......40
SEC_RUN Mode ................................................................36
Serial Clock, SCK .............................................................193
Serial Data In (SDI) ..........................................................193
Serial Data Out (SDO)  .....................................................193
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 341
Slave Select (SS) ............................................................. 193
SLEEP ..............................................................................342
Sleep
OSC1 and OSC2 Pin States ..................... .. .. .. .... ..... ..33
Sleep Mode ........................................................................39
Softwa re Simulator (MP L AB SIM) ................... .................358
Special Event Trigger. See Compare (CCP Module).
Special Event Trigger. See Compare (ECCP Module).
Speci a l Feat u res of the CPU ........ ............... .............. .......285
Special ICPORT Features ................................................305
SPI Mode (MSSP )
Associ a te d  Re g i sters  ........... ........................... .........201
Bus Mode Compatibility .......................... ........ .........201
Effects of a Reset  .....................................................201
Enabling SPI I/O  ......................................................197
Master Mode ............................................................198
Master/Slave Connection ........................ .. .... .. .. .......197
Operation .................................................................196
Operation in Power-Managed Modes  ......................201
Serial Clock ..............................................................193
Serial Data In ...........................................................193
Serial Data Out ........................................................ 193
Slave Mode ............................ ......... .... .... .. ......... .... .. 199
Slave Select ..................... ........................... ............. 193
Slave Select Synchron i zation ..... ........................... ..199
SPI Clock ................................................................. 198
Typical Connection ........................... .... .. .. ....... .... .. .. 197
SPP. See Streaming Parallel Port. 
SS .................................................................................... 193
SSPOV ............................................................................227
SSPOV Status Flag  ......................................................... 227
SSPSTAT Register
R/W Bit  .................................................................... 209
SSPxSTAT Register
R/W Bit  .................................................................... 207
Stack Full/Underflow Resets ........................................ .... .. 60
STATUS Regi ster ........ ..................... ..................... ............ 71
Streaming Parallel  Port .............. ..................... ................. 187
Associ a te d  Re g i sters ... ............... ........................... .. 19 2
Clocking Data  .......................................................... 188
Configuration ........................................................... 187
Internal Pull-ups ....................................................... 188
Interrupts ................................................................. 190
Microco n troller Contro l Setu p  ........................ .......... 190
Reading from (Microcontroller Mode) ...................... 191
Transfer of Data Between USB SIE 
and SPP (diagram) .......................................... 190
USB Contro l Setu p  ..................... .............. ............... 190
Wait States .............................................................. 188
Writing to (Microcontroller Mode) ............................. 190
SUBFSR .......................................................................... 353
SUBFWB ......................................................................... 342
SUBLW ............................................................................343
SUBULNK ........................................................................ 353
SUBWF ............................................................................343
SUBWFB ......................................................................... 344
SWAPF ............................................................................344
T
T0CON Register
PSA Bit .................................................................... 127
T0CS Bit .................................................................. 126
T0PS2:T0 PS0 Bits ............. ............................ .......... 127
T0SE Bit  ....... ............................ ........................... .... 126
Table Pointer Operat io n s ( ta b l e ) ............... ......................... 82
Table Reads/Table Writes  ......... .. ....... .. .. .. .... .. .. .. ....... .. .. .. .. 60
TBLRD ............................................................................. 345
TBLWT ............................................................................. 346
Time - o ut in Vari o u s Si tuati o n s (tab l e)  .. .. ...... ...... ..... .. ...... .. . 47
Timer0 .............................................................................. 125
16-Bit Mode Timer Reads and Writes ...................... 126
Associ a te d  Re g i sters ... ............... ........................... .. 12 7
Clock Source Edge Select (T0SE Bit)  ..................... 126
Clock Source Select (T0CS Bit) ............................... 126
Operation ................................................................. 126
Overflow  In terrupt ........ ..................... ....................... 127
Prescaler ................................................................. 127
Switching Assignment  ..................................... 127
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 129
16-Bit Read/Write Mode  ........................... .. ....... .. .. .. 131
Associ a te d  Re g i sters ... ............... ........................... .. 13 3
Interrupt ................................................................... 132
Operation ................................................................. 130

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 421
PIC18F2455/2550/4455/4550
Oscillator ..........................................................129, 131
Layout Cons id e r a tions . ............... .....................132
Low-Power Option ...........................................131
Using Timer1 as a Clock Source .....................131
Overflow Interrupt  ..................... ..................... ..........129
Resetting, Using a Special Event 
Trigger Output (CCP) ........................ ...............132
Special Event Trigger (ECCP) .................................150
TMR1H Register ......................................................129
TMR1L Register .......................................................129
Use as a Real-Time Clock .......................................132
Timer2 ..............................................................................135
Associ a te d  Re g i sters .................... ...........................136
Interrupt ....................................................................136
Operation ................................................................. 135
Output ...................................................................... 136
PR2 Register ....................................................146, 151
TMR2 to PR2 Match Interrupt ..........................146, 151
Timer3 ..............................................................................137
16-Bit Read/Write Mode ........................ .... .. ..... .. .... ..139
Associ a te d  Re g i sters .................... ...........................139
Operation ................................................................. 138
Oscillator ..........................................................137, 139
Overflow Interrupt  ................................... .. .......137, 139
Special Event Trigger (CCP)  ....................................139
TMR3H Register ......................................................137
TMR3L Register .......................................................137
Timing Diagrams
A/D Conversion ...... ..................... ..................... ........397
Acknowledge Sequence  ..........................................230
Asynchronous Re ception (TXCK P = 0, 
TX Not Inver ted)  ............................. .................251
Asynchronous Transmission (TXCKP = 0, 
TX Not Inver ted)  ............................. .................248
Asynchronous Transmission, Back to Back 
(TXCKP  = 0, TX Not Inv e rted) ............ .............248
Automatic Baud Rate Calculation ............................246
Auto-Wake-up Bit (WUE) During 
Normal Operation  ............................................252
Auto-Wake-up Bit (WUE) During Sleep ...................252
Baud Rate Generator with Clock Arbitration ............224
BRG Overflow Sequence .........................................246
BRG Reset Due to SDA Arbitration 
During Start Condition  .....................................233
Brown-out Reset (BOR) ...........................................383
Bus Collision During a Repeated Start 
Condition (Case 1) ...........................................234
Bus Collision During a Repeated Start 
Condition (Case 2) ...........................................234
Bus Collision During a Start 
Condition (SCL = 0) .........................................233
Bus Collision During a Start 
Condition (SDA only)  .......................................232
Bus Collision During a Stop 
Condition (Case 1) ...........................................235
Bus Collision During a Stop 
Condition (Case 2) ...........................................235
Bus Collision for Transmit and 
Acknowledge ...................................................231
Capture/Compare/PWM  
(All CCP Modules)  ...........................................385
CLKO and I/O  ..........................................................382
Clock Synchronization  .............................................217
Clock/Instruction Cycle .............................................. 61
EUSART Synchronous  Receive 
(Master/Slave) ................................................. 394
EUSART Synchronous  Transmission 
(Master/Slave) ................................................. 394
Example SPI Master Mode (CK E = 0) ..................... 386
Example SPI Master Mode (CK E = 1) ..................... 387
Example SPI Slave Mode (CKE = 0) ....................... 388
Example SPI Slave Mode (CKE = 1) ....................... 389
External Clock (All Modes Except PLL) ................... 380
Fail-Safe Clock Monitor ........................................... 301
First Start Bit Timi n g ................. ............................... 225
Full-Bridge PWM Output ...................................... .... 155
Half-Bridge PWM Output ......................................... 154
High/Low-Voltage Detect Characteristics ................ 377
High-Voltage Detect (VDIRMAG = 1) ...................... 282
I2C Bus Data ............................................................ 390
I2C Bus Start/Stop Bits ............................................ 390
I2C Master Mode (7 or 10-Bit Transmission) ........... 228
I2C Master Mode (7-Bit Reception)  ......................... 229
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 213
I2C Slave Mode (10-Bit Reception, 
SEN = 0, ADMSK 01001) ................................ 214
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 219
I2C Slave Mode (10-Bit Transmission) .................... 215
I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 210
I2C Slave Mode (7-bit Reception, SEN = 0, 
ADMSK = 01011)  ............. .. .... .. .. ....... .. .... .. .. .... 211
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 218
I2C Slave Mode (7-Bit Transmission) ...................... 212
I2C Slave Mode General Call Address 
Sequence (7 or 10-Bit Address Mode) ............ 220
Low-Voltage Detect (VDIRMAG = 0) ....................... 281
Master SSP I 2C Bus Data  ....................................... 392
Master SSP I 2C Bus Start/Stop Bits ........................ 392
PWM Auto-Shutdown (PRSEN = 0, 
Auto-R e start Disabled ) ..... ........................... .... 160
PWM Auto-Shutdown (PRSEN = 1, 
Auto-Restart Enabled) ..................................... 160
PWM Direction Change ......................................... .. 157
PWM Direction Change at Near 
100% Duty Cycle ............................................. 157
PWM Output  .... ........................... ..................... ........ 146
Repeated Start Condition  ..... .. .. .. .... .. .. ..... .. .. .. .. .. .... .. 226
Reset, Watchdog Timer (WDT), Oscillator 
Start-up Timer (OST) and Power-up 
Timer (PWRT)  ................................................. 383
Send Break Character Sequenc e ............................ 253
Slave Synchronization .................... ..................... .... 199
Slow Rise Time (MCLR Tied to VDD, 
VDD Rise > TPWRT) ............................................ 49
SPI Mode (Master Mode)  ........................................ 198
SPI Mode (Slave Mode with CKE = 0) ..................... 200
SPI Mode (Slave Mode with CKE = 1) ..................... 200
SPP Write Address and Data for USB 
(4 Wait States) ................................................. 189
SPP Write Address and Read Data for USB 
(4 Wait States) ................................................. 189
SPP Write Address, Write and Read Data 
(No Wait States) .............................................. 189
Stop Condition Receive or Transmit Mode .............. 230
Streaming Parallel Port (PIC18F4455/4550) ........... 396
Synchronous Reception 
(Master Mode, SREN) ..................................... 256

PIC18F2455/2550/4455/4550
DS39632D-page 422 Preliminary © 2007 Microchip Technology Inc.
Synchronous Transmission ................................. .....254
Synchronous Transmission (T hrough TXEN)   ..........255
Time-out Sequence on POR w/PLL Enabled 
(MCLR Tied to VDD) ........................................... 49
Time-out Sequence on Power-up 
(MCLR Not Tied to VDD), Case 1 ...... .................48
Time-out Sequence on Power-up 
(MCLR Not Tied to VDD), Case 2 ...... .................48
Time-out Sequence on Power-up 
(MCLR Tied to VDD, VDD Rise TPWRT) ..............48
Timer0 and Timer1 External Clock  ..........................384
Transition for Entry to Idle Mode ................. .... .. .. .......40
Transition for Entry to SEC_RUN Mode  ....................37
Transition for Entry to Sleep Mode  ............................39
Transition for Two-Speed Start-up 
(INTOSC to  HSPLL) ........................ .................299
Transition for Wake from Idle to Run Mode  ...............40
Transition for Wake from Sleep (HSPLL) ...................39
Transition From RC_RUN Mode to 
PRI_RUN Mode .................................................38
Transition from SEC_RUN Mode to 
PRI_RUN Mode (HSPLL)  ..................................37
Transition to RC_RUN Mode .....................................38
USB Signal ............ .. ....... .... .. .. .... .. ....... .... .. .. .... .. .. .....395
Timing Diagrams and Specifications ................................380
Capture/Compare/PWM Requirements 
(All CCP Modules)  ...........................................385
CLKO and I/O Requirements ...................................382
EUSART Synchronous Receiv e 
Requirements ...................................................394
EUSART Synchronous T ransm ission 
Requirements ...................................................394
Example SPI Mode Requirements 
(Master Mode, CKE = 0) ..................................386
Example SPI Mode Requirements 
(Master Mode, CKE = 1) ..................................387
Example SPI Mode Requirements 
(Slave Mode, CKE = 0) ............................... .....388
Example SPI Mode Requirements 
(Slave Mode, CKE = 1) ............................... .....389
External Clock Requirements  ..................................380
I2C Bus Data Requirements (Slave Mode)  ..............391
I2C Bus Start/Stop Bits Requirements  .....................390
Master SSP I2C Bus Data Requirements  ................393
Master SSP I2C Bus Start /S top Bits 
Requirements ...................................................392
PLL Clock .................................................................381
Reset, Watchdog Timer, Oscillator Start-up 
Timer, Power-up Timer and Brown-out 
Reset Requirements ......................... ...............383
Streaming Parallel Port Requirements 
(PIC18F4455/4550) .........................................396
Timer0 and Timer1 External Clock 
Requirements ...................................................384
USB Full-Speed Requirements ................... .... .. .......395
USB Low-Speed Requirements .......................... .....395
Top-of-Stack Access ..........................................................58
TQFP Packages and Special Features ............................305
TSTFSZ ............................................................................347
Two-Speed Start-up .................................................285, 299
Two-Word Instruc tions
Example Cases ..........................................................62
TXSTA Register
BRGH Bit  .................................................................241
U
Universal Serial Bus  ...... ..................... .............. ................. 63
Address Register (UADDR) ..................................... 170
and Streaming Parallel Port ..................................... 183
Associ a te d  Re g i sters ... ............... ........................... .. 18 4
Buffe r Desc riptor Table  .... ............... ..................... .... 171
Buffe r Desc riptors ..................... ..................... .......... 171
Address Validation ........................................... 174
Assignment in Different 
Buffering Modes  ......................... ......... ....176
BDnSTAT Register (CPU Mode) ..................... 172
BDnSTAT Register (SIE Mode) ....................... 174
Byte Count ....................................................... 174
Example ........................................................... 171
Memory Map .................................................... 175
Ownership .......................................................171
Ping-Pong Buffering  ........................................ 175
Register Summary ..................................... ...... 176
Status and Configuration .............. .. .... ....... .. .... 171
Class Specifications and Drivers ............................. 186
Descriptors .... ..................... ............................ .......... 186
Endpoint Control .................... ....... .. .. .... .. .. ....... .. .... .. 169
Enumeration ............................................................ 186
External Pull-up Resistors ....................................... 167
External Transceiver  ................................................ 165
Eye Pattern Test Enable .......................................... 167
Firmware and Drivers  .............................................. 184
Frame Number Registers  ........................................ 170
Frames .................................................................... 185
Internal Pull-up Resistors ......................................... 167
Internal Transceiver ................................................. 165
Internal Voltage Regulator ....................................... 167
Interrupts ................................................................. 177
and USB Transactions ..................................... 177
Layered Framework ................................ ................. 185
Oscillator Requirements  .... ...................................... 184
Output Enable Monitor ................ .. .. .. .. .. .... .. ..... .. .. .. .. 167
Overview .......................................................... 163, 185
Ping-Pong Buffer Configuration .......... .... .. ....... .. .... .. 167
Power ...................................................................... 185
Power Modes ........................................ .... ............. .. 183
Bus Power On ly ................ .............. ................. 183
Dual Power with Self-Power 
Dominance .............................................. 183
Self-P o w er On ly  .................... ..................... ...... 183
RAM ......................................................................... 170
Memory Map .................................................... 170
Speed ...................................................................... 186
Status and Control .................................. .. ......... .. .... 164
Transfe r Types ............. ..................... ....................... 185
UFRMH:UFRML Registers ......................................170
USB. See Universal Serial Bus.

© 2007 Microchip Technology Inc. Preliminary DS39632D-page 423
PIC18F2455/2550/4455/4550
V
Voltage Reference Specifications ....................... ....... .... ..375
W
Watchdog Timer (WDT) .................................. .... .....285, 297
Associ a te d  Re g i sters .................... ...........................298
Control Reg i ster ............... ............... ..................... ....297
During Oscillator Failure  ..........................................300
Programming Considerations  ......... ............... ..........297
WCOL  ................... .. .. ..... .... .. .. .. .. .. .. ....... .. .225, 226, 227, 230
WCOL Status Flag ................. .. .. .. ....... .. .. .225, 226, 227, 230
WWW Address  .................................................................423
WWW, On-Line Support  ......................................................5
X
XORLW ............................................................................ 347
XORWF ............................................................................348

PIC18F2455/2550/4455/4550

NOTES:

PIC18F2455/2550/4455/4550

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PIC18F2455/2550/4455/4550

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DS39632DPIC18F2455/2550/4455/4550

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PIC18F2455/2550/4455/4550

PIC18F2455/2550/4455/4550 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device PIC18F2455/2550(1), PIC18F4455/4550(1),

PIC18F2455/2550T(2), PIC18F4455/4550T(2);

VDD range 4.2V to 5.5V

PIC18LF2455/2550(1), PIC18L F 44 55 / 45 5 0(1),

PIC18LF2455/2550T(2), PIC18LF4455/4550T(2);

VDD range 2.0V to 5.5V

Temp er atu re R ang e I = -40°C to +85°C (Industrial)

E= -40°C to +125°C (Extended)

Package PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny Plastic DIP

P=PDIP

ML = QFN

Pattern QTP, SQTP, Code or Special Requirements

(blank oth erwi se )

Examples:

a) PIC18LF4550-I/P 301 = Industrial temp., PDIP

package, Extended VDD limits, QTP pattern

#301.

b) PIC18LF2455-I/SO = Industrial temp., SOIC

package, Extended VDD limits.

c) PIC18F4455-I/P = Industrial temp., PDIP

package, normal VDD limits.

Note 1: F = Standard Voltage Range

LF = Wide Voltage Range

2: T = in tape and reel TQFP

packages only.

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12/08/06