0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
COUT
CIN
CSS
VBIAS
CBIAS
VOUT
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS748
SBVS074L –JANUARY 2007–REVISED MARCH 2017
TPS748 1.5-A Low-Dropout Linear Regulator With Programmable Soft-Start
1
1 Features
1• VOUT Range: 0.8 V to 3.6 V
• Ultralow VIN Range: 0.8 V to 5.5 V
• VBIAS Range 2.7 V to 5.5 V
• Low Dropout: 60 mV Typical at 1.5 A, VBIAS =5V
• Power Good (PG) Output Allows Supply
Monitoring or Provides a Sequencing Signal for
Other Supplies
• 2% Accuracy Over Line, Load, and Temperature
• Programmable Soft-Start Provides Linear Voltage
Startup
• VBIAS Permits Low VIN Operation With Good
Transient Response
• Stable With Any Output Capacitor ≥2.2 μF
• Available in a Small, 3-mm × 3-mm × 1-mm
VSON-10 and 5 × 5 QFN-20 Packages
2 Applications
• FPGA Applications
• DSP Core and I/O Voltages
• Post-Regulation Applications
• Applications With Special Start-up Time or
Sequencing Requirements
• Hot-Swap and Inrush Controls
3 Description
The TPS748 low-dropout (LDO) linear regulator
provides an easy-to-use robust power management
solution for a wide variety of applications. User-
programmable soft-start minimizes stress on the input
power source by reducing capacitive inrush current
on start-up. The soft-start is monotonic and well-
suited for powering many different types of
processors and ASICs. The enable input and power
good output allow easy sequencing with external
regulators. This complete flexibility permits the user to
configure a solution that meets the sequencing
requirements of FPGAs, DSPs, and other
applications with special start-up requirements.
A precision reference and error amplifier deliver 2%
accuracy over load, line, temperature, and process.
The device is stable with any type of capacitor
greater than or equal to 2.2 μF, and is fully specified
for TJ= –40°C to 125°C. The TPS748 is offered in a
small, 3-mm × 3-mm, VSON-10 package, yielding a
highly compact, total solution size. The device is also
available in a 5 × 5 QFN-20 package for compatibility
with the TPS744.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS748 VSON (10) 3.00 mm x 3.00 mm
VQFN (20) 5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
SPACE
SPACE
Typical Application Circuit (Adjustable) Turnon Response
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Typical Characteristics IOUT = 50 mA ....................... 8
6.7 Typical Characteristics IOUT = 1 A .......................... 11
7 Detailed Description............................................ 12
7.1 Overview................................................................. 12
7.2 Functional Block Diagram....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
7.5 Programming .......................................................... 14
8 Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 19
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
10.3 Estimating Junction Temperature ......................... 25
11 Device and Documentation Support................. 27
11.1 Device Support...................................................... 27
11.2 Documentation Support ....................................... 27
11.3 Receiving Notification of Documentation Updates 27
11.4 Community Resources.......................................... 27
11.5 Trademarks........................................................... 27
11.6 Electrostatic Discharge Caution............................ 27
11.7 Glossary................................................................ 28
12 Mechanical, Packaging, and Orderable
Information........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (February 2015) to Revision L Page
• Added active pulldown to Functional Block Diagram ........................................................................................................... 12
• Added Equation 1 and corresponding description to Enable/Shutdown section.................................................................. 13
Changes from Revision J (January 2012) to Revision K Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed part number as printed in document from TPS74801 to TPS748 ......................................................................... 1
• Changed SON-10 package references in document to VSON-10......................................................................................... 1
• Changed second paragraph of Description section .............................................................................................................. 1
• Changed pin descriptions throughout Pin Functions table .................................................................................................... 4
• Changed condition statement for Absolute Maximum Ratings .............................................................................................. 5
• Changed "free-air" to "junction" temperature in condition statement for Recommended Operating Conditions.................... 5
• Changed values for both packages in Thermal Information .................................................................................................. 6
• Changed test condition for output noise voltage from 0.001 µF to 1 nF................................................................................ 7
• Changed y-axis title in Figure 3 from abbreviation (IOUT) to text (Output Current)................................................................. 8
• Changed y-axis title in Figure 4 from abbreviation (IOUT) to text (Output Current) ................................................................ 8
• Changed title for Figure 4 ...................................................................................................................................................... 8
• Changed y-axis and x-axis titles in Figure 5 from abbreviations to text................................................................................. 8
• Changed x-axis title in Figure 6 from abbreviation (VDC) to text (Dropout Voltage) .............................................................. 8
• Changed x-axis title in Figure 7 from abbreviation (VDO) to text (Dropout Voltage) .............................................................. 8
• Changed y-axis and x-axis titles in Figure 8 from abbreviations to text ................................................................................ 8
• Changed y-axis and x-axis titles in Figure 13 from abbreviations to text .............................................................................. 9
• Changed title for Figure 13 .................................................................................................................................................... 9
3
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• Changed x-axis title in Figure 14 from abbreviation (IBIAS) to text (Bias Current) .................................................................. 9
• Changed Figure 24; added capacitor size indication for CSS .............................................................................................. 16
Changes from Revision I (November 2010) to Revision J Page
• Changed TJrange in Absolute Maximum Ratings table......................................................................................................... 5
Changes from Revision H (October, 2010) to Revision I Page
• Corrected equation for Table 2............................................................................................................................................. 15
Changes from Revision G (August, 2010) to Revision H Page
• Corrected typo in Figure 38.................................................................................................................................................. 25
IN
IN
IN
PG
BIAS
OUT
OUT
OUT
NC
FB
TPS74801
IN
EN 11
GND 12
NC 13
NC 14
SS 15
6
7
8
9
10
20
19
18
17
16
5
NC4
NC3
NC2
OUT1
GND
OUT
OUT
FB
SS
GND
10
9
8
7
6
IN
IN
PG
BIAS
EN
1
2
3
4
5
Thermal
Pad
4
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Thermal Pad
Top View RGW Package
20-Pin VQFN
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME VSON VQFN
BIAS 4 10 I Bias input voltage for error amplifier, reference, and internal control circuits. A 1-µF or
larger input capacitor is recommended for optimal performance. If IN is connected to
BIAS, a 4.7-µF or larger capacitor must be used.
EN 5 11 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the
regulator into shutdown mode. This pin must not be left unconnected.
FB 8 16 I Feedback pin. The feedback connection to the center tap of an external resistor
divider network that sets the output voltage. This pin must not be left floating.
GND 6 12 — Ground
IN 1, 2 5-8 I Input to the device. A 1-µF or larger input capacitor is recommended for optimal
performance.
NC N/A 2-4, 13, 14,
17 —No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
OUT 9, 10 1, 18-20 O Regulated output voltage. A small capacitor (total typical capacitance ≥2.2 μF,
ceramic) is needed from this pin to ground to assure stability.
PG 3 9 O
Power Good pin. An open-drain, active-high output that indicates the status of VOUT.
When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance
state. When VOUT is below this threshold the pin is driven to a low-impedance state. A
pull-up resistor from 10 kΩto 1 MΩshould be connected from this pin to a supply of
up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin
can be left unconnected if output monitoring is not necessary.
SS 7 15 — Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this
pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs.
Thermal pad — Must be soldered to the ground plane for increased thermal performance. Internally
connected to ground.
5
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
At TJ= –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND.(1)
MIN MAX UNIT
Input voltage VIN, VBIAS –0.3 6 V
Enable voltage VEN –0.3 6 V
Power good voltage VPG –0.3 6 V
PG sink current IPG 0 1.5 mA
Soft-start voltage VSS –0.3 6 V
Feedback voltage VFB –0.3 6 V
Output voltage VOUT –0.3 VIN + 0.3 V
Maximum output current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power
dissipation PDISS See Thermal Information
Temperature Operating junction, TJ–40 150 °C
Storage, Tstg –55 150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2) ±500
(1) BIAS supply is required when VIN is below VOUT + 1.62 V.
(2) VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
(3) If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Input supply voltage VOUT + VDO (VIN) VOUT + 0.3 5.5 V
VEN Enable supply voltage 0 VIN 5.5 V
VBIAS(1) BIAS supply voltage VOUT + VDO (VBIAS)(2) VOUT + 1.6(2) 5.5 V
VOUT Output voltage 0.8 3.3 V
IOUT Output current 0 1.5 A
COUT Output capacitor 2.2 µF
CIN Input capacitor(3) 1 µF
CBIAS Bias capacitor 0.1 1 µF
TJOperating junction temperature –40 125 °C
6
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.
.ii. DRC: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
(b) i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
.ii. DRC: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Estimating Junction Temperature section of this data
sheet.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.4 Thermal Information
THERMAL METRIC(1) TPS748(2)
UNITRGW (VQFN) DRC (VSON)
20 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance(3) 35.6 44.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(4) 33.3 50.3 °C/W
RθJB Junction-to-board thermal resistance(5) 15 19.6 °C/W
ψJT Junction-to-top characterization parameter(6) 0.4 0.7 °C/W
ψJB Junction-to-board characterization parameter(7) 15.2 17.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(8) 3.8 4.3 °C/W
7
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(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.
6.5 Electrical Characteristics
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ=
–40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS BIAS pin voltage range 2.7 5.5 V
VREF Internal reference (Adj.) TJ= 25°C 0.796 0.8 0.804 V
VOUT(ΔVIN)
Output voltage range VIN = 5 V, IOUT = 1.5 A VREF 3.6 V
Accuracy(1) 2.97 V ≤VBIAS ≤5.5 V,
50 mA ≤IOUT ≤1.5 A –2% ±0.5% 2%
VOUT(ΔIOUT) Line regulation VOUT(nom) + 0.3 ≤VIN ≤5.5 V 0.03 %/V
VOUT Load regulation 50 mA ≤IOUT ≤1.5 A 0.09 %/A
VDO VIN dropout voltage(2) IOUT = 1.5 A,
VBIAS – VOUT(nom) ≥3.25 V(3) 60 165 mV
VBIAS dropout voltage(2) IOUT = 1.5 A, VIN = VBIAS 1.31 1.6 V
ICL Current limit VOUT = 80% × VOUT(nom) 2 5.5 A
IBIAS BIAS pin current 1 2 mA
ISHDN Shutdown supply current
(IGND)VEN ≤0.4 V 1 50 μA
IFB Feedback pin current –1 0.150 1 μA
PSRR
Power-supply rejection
(VIN to VOUT)
1 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V 60 dB
300 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V 30
Power-supply rejection
(VBIAS to VOUT)
1 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V 50 dB
300 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V 30
VnOutput noise voltage 100 Hz to 100 kHz,
IOUT = 1.5 A, CSS = 1 nF 25 × VOUT μVRMS
tSTR Minimum startup time RLOAD for IOUT = 1.0 A, CSS = open 200 μs
ISS Soft-start charging current VSS = 0.4 V 440 nA
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 50 mV
VEN(dg) Enable pin deglitch time 20 μs
IEN Enable pin current VEN = 5 V 0.1 1 μA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.3 V
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT 0.1 1 μA
TJOperating junction
temperature –40 125 °C
TSD Thermal shutdown
temperature Shutdown, temperature increasing 165 °C
Reset, temperature decreasing 140
100
90
80
70
60
50
40
30
20
10
0
00.5 1.0
Dropout Voltage (mV)
Output Current (A)
1.5
+125 C°
+25 C°
- °40 C
1.2
1.0
0.8
0.6
0.4
0.2
0
010 20 30 40
Change in V (%)
OUT
Output Current (mA)
50
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.05 0.5 1.0
Change in V (%)
OUT
Output Current (A)
1.5
+125 C°
+25 C°- °40 C
0.20
0.15
0.10
0.05
0
-0.05
-0.01
-0.15
-0.20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
ChangeinV (%)
OUT
V V-
IN OUT (V)
5.0
+125 C°
+25 C°
- °40 C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
ChangeinV (%)
OUT
V V-
BIAS OUT (V)
4.0
+125 C°+25 C°
- °40 C
8
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6.6 Typical Characteristics IOUT = 50 mA
At TJ= 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF,
unless otherwise noted.
Figure 1. VIN Line Regulation Figure 2. VBIAS Line Regulation
Figure 3. Load Regulation Figure 4. Load Regulation at Light Load
Figure 5. VIN Dropout Voltage vs IOUT and Temperature (TJ)Figure 6. VIN Dropout Voltage vs (VBIAS – VOUT) and
Temperature (TJ)
90
80
70
60
50
40
30
20
10
0
00.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Power-SupplyRejectionRatio(dB)
V V-
IN OUT (V)
2.25
1kHz
10kHz
100kHz
500kHz
VOUT =1.2V
IOUT =1.5A
CSS =1nF
1
0.1
0.01
100 1k 10k
OutputSpectralNoiseDensity(mV/Ö)
Hz
Frequency(Hz)
100k
C =1nF
SS
C =0nF
SS
C =10nF
SS
I =100mA
OUT
V =1.2V
OUT
90
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
V =5V
BIAS
C =1nF
SS
I =0.5A
OUT
I =0.1A
OUT I =1.5A
OUT
80
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-Supply Rejection Ratio (dB)
Frequency (Hz)
10M
V = 1.8V
IN
V = 1.2V
OUT
C = 1nF
SS
I = 100mA
OUT
I = 1.5A
OUT
V = 5V
BIAS
2200
2000
1800
1600
1400
1200
1000
800
600
00.5 1.0
Dropout Voltage (mV)
Output Current (A)
1.5
+125 C°
+25 C°
- °40 C
9
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Typical Characteristics IOUT = 50 mA (continued)
At TJ= 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF,
unless otherwise noted.
Figure 7. VIN Dropout Voltage vs (VBIAS – VOUT) and
Temperature (TJ)Figure 8. VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)
Figure 9. VBIAS PSRR vs Frequency Figure 10. VIN PSRR vs Frequency
Figure 11. VIN PSRR vs (VIN – VOUT) Figure 12. Noise Spectral Density
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
CurrentLimit(A)
V V-
BIAS OUT (V)
5.0
+125 C°
+25 C°
- °40 C
V =0.8V
OUT
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V Low-LevelPGVoltage(V)
OL
02 4 6 8 10 12
PGCurrent(mA)
500
475
450
425
400
375
350
325
300
-50 -25 0 25 50 75 100
I (nA)
SS
JunctionTemperature( C)°
125
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Bias Current (mA)
V (V)
BIAS
5.5
+125 C°
+25 C°
- °40 C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
00.2 0.4 0.6 0.8 1.0 1.2 1.4
Bias Current (mA)
Output Current (A)
1.6
+125 C°
+25 C°
- °40 C
10
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Typical Characteristics IOUT = 50 mA (continued)
At TJ= 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF,
unless otherwise noted.
Figure 13. BIAS Pin Current vs Output Current and
Temperature (TJ)Figure 14. BIAS Pin Current vs VBIAS and Temperature (TJ)
Figure 15. Soft-Start Charging Current (ISS) vs
Temperature (TJ)Figure 16. Low-Level PG Voltage vs Current
Figure 17. Current Limit vs (VBIAS – VOUT)
1V/div
Time(20ms/div)
V (500mV/div)
PG
VOUT
V =V =V
IN BIAS EN
100mV/div
100mV/div
1A/div
100mV/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
1A/ sm
50mA
C =470 F(OSCON)OUT m
C =1nF
SS
1.5A
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
100mV/div
1V/div
Time(50 s/div)m
C =10 F(Ceramic)
OUT m
3.8V
1V/ sm
1.8V
C =1nF
SS
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6.7 Typical Characteristics IOUT = 1 A
At TJ= 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and
COUT = 10 μF, unless otherwise noted.
Figure 18. VBIAS Line Transient Figure 19. VIN Line Transient
Figure 20. Output Load Transient Response Figure 21. Turnon Response
Figure 22. Power-Up/Power-Down
Thermal
Limit
Soft-Start
Discharge
OUT VOUT
FB
PG
IN
BIAS
SS
EN Hysteresis
and Deglitch
Current
Limit
UVLO
0.44 µA
0.8-V
Reference
0.9 x VREF
GND
CSS
R1
R2
833
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7 Detailed Description
7.1 Overview
The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators
use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate
very low input and output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable
with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies,
particularly for low VIN applications.
The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic
start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG)
output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with
hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often required by processor-intensive systems.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Enable/Shutdown
The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4 V turns
the regulator off, while VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has
hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the
TPS748 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically
has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in the VEN
signal.
The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature
variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V
and 1.1-V limits. If precise turnon timing is required, a fast rise-time signal must be used to enable the TPS748.
833
833 LOUT
L
RC
R
W
§ ·
u
u
¨ ¸
© ¹
13
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Feature Description (continued)
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close
as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the
enable circuit.
The TPS748 has an internal active pulldown circuit that connects the output to GND through an 833-Ωresistor
when the device is disabled. This resistor discharges the output with a time constant of:
(1)
7.3.2 Power Good
The power good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an
external pull-up resistor. This pin requires at least 1.1 V on VBIAS in order to have a valid output. The PG output is
high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the
open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled.
The recommended operating condition of PG pin sink current is up to 1 mA, so the pull-up resistor for PG should
be in the range of 10 kΩto 1 MΩ. If output voltage monitoring is not needed, the PG pin can be left floating.
7.3.3 Internal Current Limit
The TPS748 features a factory-trimmed current limit that is flat over temperature and supply voltage. The current
limit allows the device to supply surges of up to 2 A and maintain regulation. The current limit responds in
approximately 10 μs to reduce the current during a short-circuit fault.
The internal current limit protection circuitry of the TPS748 is designed to protect against overload conditions. It
is not intended to allow operation above the rated current of the device. Continuously running the TPS748 above
the rated current degrades device reliability.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in
a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40°C
above the maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS748 is designed to protect against overload conditions. It is not
intended to replace proper heatsinking. Continuously running the TPS748 into thermal shutdown degrades
device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage and bias voltage are both at least at the respective minimum specifications.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
t =
SSCL
(V C )´
OUT(NOM) OUT
ICL(MIN)
t =
SS
(V C )´
REF SS
ISS
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Device Functional Modes (continued)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input or bias voltages are below the respective minimum specifications.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE PARAMETER
VIN VEN VBIAS IOUT TJ
Normal mode VIN > VOUT(nom) + VDO (VIN) VEN > VEN(high) VBIAS ≥VOUT + 1.6 V I OUT < ICL TJ< 125°C
Dropout mode VIN < VOUT(nom) + VDO (VIN) VEN > VEN(high) VBIAS < VOUT + 1.6 V — TJ< 125°C
Disabled mode
(any true condition disables
the device) VIN < VIN(min) VEN < VEN(low) VBIAS < VBIAS(min) — TJ> 165°C
7.5 Programming
7.5.1 Programmable Soft-Start
The TPS748 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization
problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also
reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus.
To achieve a linear and monotonic soft-start, the TPS748 error amplifier tracks the voltage ramp of the external
soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-
start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and can be
calculated using Equation 2:
(2)
If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up
time. In this case, the start-up time is given by Equation 3:
where
• VOUT(nom) is the nominal output voltage,
• COUT is the output capacitance, and
• ICL(min) is the minimum current limit for the device. (3)
In applications where monotonic startup is required, the soft-start time given by Equation 2 should be set greater
than Equation 3.
TPS74801
GND SS
OUT
FB
EN
IN
BIAS
VIN VOUT
R2
R1
CSS
CIN
C
VBIAS
CBIAS
R
COUT
t (s) =
SS
V C
I
REF SS
SS
×0.8V C (F)
0.44 A
SS
m
×
=
15
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Programming (continued)
The maximum recommended soft-start capacitor is 15 nF. Larger soft-start capacitors can be used and do not
damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-
start capacitor when enabled. Soft-start capacitors larger than 15 nF could be a problem in applications where it
is necessary to rapidly pulse the enable pin and still require the device to soft-start from ground. CSS must be
low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested soft-start
capacitor values.
(1) where tSS(s) = soft-start time in seconds.
Table 2. Standard Capacitor Values for Programming the Soft-Start Time(1)
CSS SOFT-START TIME
Open 0.1 ms
270 pF 0.5 ms
560 pF 1 ms
2.7 nF 5 ms
5.6 nF 10 ms
10 nF 18 ms
Another option to set the start-up rate is to use a feedforward capacitor; see the Pros and Cons of Using a
Feedforward Capacitor with a Low-Dropout Regulator application report for more information.
7.5.2 Sequencing Requirements
VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the soft-
start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable
for most applications, as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster than the
set soft-start ramp rate.
There are several different start-up responses that are possible, but not typical:
• If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply
minus the dropout voltage until it reaches the set output voltage.
• If EN is connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS.
• If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN.
• If the soft-start time has not expired, the output tracks VIN until VOUT reaches the value set by the charging
soft-start capacitor.
Figure 23 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also
be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and
VBIAS are present.
Figure 23. Soft-Start Delay Using an RC Circuit to Enable the Device
VOUT
COUT
10 Fm
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
CIN
1 Fm
CSS
1 nF
VBIAS
CBIAS
1 Fm
V = 0.8 ´
OUT 1 + R1
R2
)(
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators
use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate
very low input and output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable
with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies,
particularly for low VIN applications.
The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic
start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG)
output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with
hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often required by processor-intensive systems.
8.1.1 Adjusting the Output Voltage
Figure 24 shows the typical application circuit for the TPS748 adjustable output device.
Figure 24. Typical Application Circuit for the TPS748 (Adjustable)
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Application Information (continued)
R1and R2can be calculated for any output voltage using the formula shown in Figure 24.Table 3 lists sample
resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2should
be ≤4.99 kΩ.
(1) VOUT = 0.8 × (1 + R1/R2).
Table 3. Standard 1% Resistor Values for Programming the Output Voltage(1)
R1(kΩ) R2(kΩ) VOUT (V)
Short Open 0.8
0.619 4.99 0.9
1.13 4.53 1.0
1.37 4.42 1.05
1.87 4.99 1.1
2.49 4.99 1.2
4.12 4.75 1.5
3.57 2.87 1.8
3.57 1.69 2.5
3.57 1.15 3.3
SPACE
NOTE
When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately
50 μA of current from OUT. Although this condition does not cause any damage to the
device, the output current may charge up the OUT node if total resistance between OUT
and GND (including external feedback resistors) is greater than 10 kΩ.
8.1.2 Input, Output, and Bias Capacitor Requirements
The device is designed to be stable for all available types and values of output capacitors ≥2.2 μF. The device is
also stable with multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN is 1 μF and minimum
recommended capacitor for VBIAS is 0.1 µF. If VIN and VBIAS are connected to the same supply, the recommended
minimum capacitor for VBIAS is 4.7 μF. Good quality, low ESR capacitors should be used on the input; ceramic
X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for
optimum performance.
8.1.3 Transient Response
The TPS748 was designed to have excellent transient response for most applications with a small amount of
output capacitance. In some cases, the transient response may be limited by the transient response of the input
supply. This limitation is especially true in applications where the difference between the input and output is less
than 300 mV. In this case, adding additional input capacitance improves the transient response much more than
just adding additional output capacitance would do. With a solid input supply, adding additional output
capacitance reduces undershoot and overshoot during a transient event; refer to Figure 20 in the Typical
Characteristics section. Because the TPS748 is stable with output capacitors as low as 2.2 μF, many
applications may then need very little capacitance at the LDO output. For these applications, local bypass
capacitance for the powered device may be sufficient to meet the transient requirements of the application. This
design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO
output.
V ( V )=25m
N RMS xV (V)
OUT
mVRMS
V
( )
Efficiency »
V I
OUT OUT
´
V (I
IN IN Q
+ I )´
at I I
OUT Q
>>
V
V
OUT
IN
»
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(1) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.
8.1.4 Dropout Voltage
The TPS748 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT
applications. The low dropout of the TPS748 allows the device to be used in place of a dc/dc converter and still
achieve good efficiency. Equation 4 provides a quick estimate of the efficiency.
(4)
This efficiency provides designers with the power architecture for their applications to achieve the smallest,
simplest, and lowest cost solutions.
There are two different specifications for dropout voltage with the TPS748. The first specification (see Figure 25)
is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low dropout. This
specification assumes that VBIAS is at least 3.25 V(1) above VOUT, which is the case for VBIAS when powered by a
5.0-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT +3.25 V(1), VIN dropout is less
than specified.
The second specification (illustrated in Figure 31) is referred to as VBIAS Dropout and applies to applications
where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary
bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications
because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.6 V above VOUT. Because of
this usage, IN and BIAS tied together become a highly inefficient solution that can consume large amounts of
power. Pay attention not to exceed the power rating of the IC package.
8.1.5 Output Noise
The TPS748 provides low output noise when a soft-start capacitor is used. When the device reaches the end of
the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 1-nF soft-start
capacitor, the output noise is reduced by half and is typically 30 μVRMS for a 1.2-V output (10 Hz to 100 kHz).
Further increasing CSS has little effect on noise. Because most of the output noise is generated by the internal
reference, the noise is a function of the set output voltage. The RMS noise with a 1-nF soft-start capacitor is
given in Equation 5:
(5)
The low output noise of the TPS748 makes it a good choice for powering transceivers, PLLs, or other noise-
sensitive circuitry.
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN V =5V 5%
BIAS ±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
COUT
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8.2 Typical Applications
8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
Figure 25. Typical Application of the TPS748 Using an Auxiliary Bias Rail
8.2.1.1 Design Requirements
This application powers the I/O rails of an FPGA , at VOUT(nom) = 1.5 V and IOUT(dc) = 1.5 A. The available external
supply voltages are 1.8 V, 3.3 V and 5 V.
8.2.1.2 Detailed Design Procedure
First, determine what supplies to use for the input and bias rails. A 1.8-V input can be stepped down to 1.5 V at
1.5 A if an external bias is provided, because the maximum dropout voltage is 165 mV if VBIAS is at least 3.25 V
higher than VOUT. To achieve this voltage step, the bias rail is supplied by the 5-V supply. The approximation in
Equation 4 estimates the efficiency at 83.3%.
The output voltage then must be set to 1.5 V. As Table 3 describes, set R1= 4.12 kΩand R2= 4.75 kΩto obtain
the required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint;
refer to Input, Output, and Bias Capacitor Requirements for CIN = 1 µF, CBIAS = 1 µF, and COUT = 2.2 µF. Use
CSS = 1 nF for a typical 1.8-ms start-up time.
Figure 25 shows a simplified version of the final circuit.
1V/div
Time(20ms/div)
V (500mV/div)
PG
VOUT
V =V =V
IN BIAS EN
100mV/div
100mV/div
1A/div
100mV/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
1A/ sm
50mA
C =470 F(OSCON)OUT m
C =1nF
SS
1.5A
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
100mV/div
1V/div
Time(50 s/div)m
C =10 F(Ceramic)
OUT m
3.8V
1V/ sm
1.8V
C =1nF
SS
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Typical Applications (continued)
8.2.1.3 Application Curves
Figure 26. VBIAS Line Transient Figure 27. VIN Line Transient
Figure 28. Output Load Transient Response Figure 29. Turnon Response
Figure 30. Power-Up/Power-Down
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN
VIN
V =3.3V 5%
BIAS ±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
COUT
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Typical Applications (continued)
8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
Figure 31. Typical Application of the TPS748 Without an Auxiliary Bias Rail
8.2.2.1 Design Requirements
The application powers the I/O rails of an FPGA, at VOUT(nom) = 1.5 V and IOUT(max) = 1.5 A. The only available rail
is 3.3 V. The I/O pins are driven for only short durations with a 5% duty cycle, so thermal issues are not a
concern.
8.2.2.2 Detailed Design Procedure
There is only one available rail; therefore, the input supply and the bias supply are connected together on the
3.3-V input supply.
The output voltage must be set to 1.5 V. As Table 3 describes, set R1= 4.12 kΩand R2= 4.75 kΩto obtain the
required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer
to Input, Output, and Bias Capacitor Requirements for CIN = CBIAS = 4.7 µF, and COUT = 2.2 µF. Use CSS = 1 nF
for a typical 1.8-ms start-up time.
Figure 31 shows the TPS748 configured without a bias rail.
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
CurrentLimit(A)
V V-
BIAS OUT (V)
5.0
+125 C°
+25 C°
- °40 C
V =0.8V
OUT
100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
2200
2000
1800
1600
1400
1200
1000
800
600
00.5 1.0
Dropout Voltage (mV)
Output Current (A)
1.5
+125 C°
+25 C°
- °40 C
90
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
V =5V
BIAS
C =1nF
SS
I =0.5A
OUT
I =0.1A
OUT I =1.5A
OUT
80
22
TPS748
SBVS074L –JANUARY 2007–REVISED MARCH 2017
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Typical Applications (continued)
8.2.2.3 Application Curves
Figure 32. VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)Figure 33. VBIAS PSRR vs Frequency
Figure 34. Current Limit vs (VBIAS – VOUT)
Figure 35. VBIAS Line Transient
9 Power Supply Recommendations
The TPS748 is designed to operate from an input voltage up to 5.5 V, provided the bias rail is at least 1.62 V
higher than the input supply and dropout requirements are met. The bias rail and the input supply should both
provide adequate headroom and current for the device to operate normally. Connect a low output impedance
power supply directly to the IN pin of the TPS748. This supply must have at least 1 μF of capacitance near the IN
pin for optimal performance. A supply with similar requirements must also be connected directly to the bias rail
with a separate 1-μF or larger capacitor. If the IN pin is tied to the bias pin, a minimum 4.7 μF of capacitance is
needed for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or
ferrite bead before the input capacitor.
140
120
100
80
60
40
20
0
qJA ( C/W)
°
0 1 2 3 4 5 678 9 10
Board Copper Area ( )in2
DRC
RGW
R =
qJA
(+125 C T )° - A
PD
P =(V V ) I- ´
D IN OUT OUT
23
TPS748
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10 Layout
10.1 Layout Guidelines
An optimal layout can greatly improve transient performance, PSR, and noise. To minimize the voltage drop on
the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as
possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the
input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the
top side of R1in Figure 24 should be connected as close as possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense point of the input supply as possible. This connection
minimizes the voltage drop on BIAS during transient conditions and can improve the turnon response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad
is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends
on input voltage and load conditions and can be calculated using Equation 6:
(6)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On both the VSON (DRC) and QFN (RGW) packages, the primary conduction path for heat is through the
exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however,
it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The
maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum
device junction temperature, and power dissipation of the device and can be calculated using Equation 7:
(7)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 36.
Note: θJA value at board size of 9 in2(that is, 3 in × 3i n) is a JEDEC standard.
Figure 36. ΘJA vs Board Size
Figure 36 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, TI strongly recommends using ΨJT
and ΨJB, as explained in Estimating Junction Temperature.
2
15
17
20
15
11
10
6
9
8
3
18
4
7 19
12 13 14
16
OUT
OUT
NC
OUT
OUT
NC
NC
NC
IN
FB/
SNS
IN
IN
PG
IN
BIAS
SS
NC
NC
GND
EN
CSS
CBIAS
R(PULLUP)
R1
R2
CIN
COUT
R1 and R2 should
be connected
close to the load,
COUT should be as
near to the LDO as
possible
Input GND Plane
VIN Plane VOUT Plane
Output GND Plane
Thermal Pad
Keep the ground planes on
the same side of the PCB if
possible to improve thermal
disappation
(1) Denotes thermal vias
(2) Denotes vias used for application purposes
24
TPS748
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10.2 Layout Example
Figure 37. Layout Example (RGW Package)
(a) Example DRC (SON) Package Measurement
T on PCB
B
T on of Itop
TC
1mm
(b) Example RGW (QFN) Package Measurement
1mm
T on top
of IC
T
T on PCB
surface
B
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
25
TPS748
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Submit Documentation FeedbackCopyright © 2007–2017, Texas Instruments Incorporated
10.3 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 8). For backwards compatibility, an older θJC,Top
parameter is listed as well.
(8)
Where PDis the power dissipation shown by Equation 6, TTis the temperature at the center-top of the IC
package, and TBis the PCB temperature measured 1 mm away from the IC package on the PCB surface
(Figure 38).
NOTE
Both TTand TBcan be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TTand TB, see the Using New Thermal Metrics application note, available
for download at www.ti.com.
Figure 38. Measuring Points for TTand TB
12
10
8
6
4
2
0
Y Yand ( C/W)
JT JB °
0 2 46 8 10
Board Copper Area (in )
2
51 3 7 9
YJT
YJB
DRC
RGW
26
TPS748
SBVS074L –JANUARY 2007–REVISED MARCH 2017
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Estimating Junction Temperature (continued)
By looking at Figure 39, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 8 is a good way to estimate TJby simply measuring TTor TB, regardless of the
application board size.
Figure 39. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
see the Using New Thermal Metrics application report, available for download at www.ti.com. For further
information, see the IC Package Thermal Metrics application report, also available on the TI website.
27
TPS748
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Submit Documentation FeedbackCopyright © 2007–2017, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS48.
The TPS74801EVM-177 evaluation module (and related user's guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS748 is available through the product folders under Tools
& Software.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•Using New Thermal Metrics
•IC Package Thermal Metrics
•Ultimate Regulation of with Fixed Output Versions of the TPS742xx, TPS743xx, and TPS744xx
•Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
•TPS74801EVM-177 Evaluation Module User Guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
28
TPS748
SBVS074L –JANUARY 2007–REVISED MARCH 2017
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Submit Documentation Feedback Copyright © 2007–2017, Texas Instruments Incorporated
11.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Mar-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS74801DRCR ACTIVE VSON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO
TPS74801DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO
TPS74801DRCT ACTIVE VSON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO
TPS74801DRCTG4 ACTIVE VSON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO
TPS74801RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
74801
TPS74801RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
74801
TPS74801RGWT ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
74801
TPS74801RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS
74801
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Mar-2017
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS74801 :
•Automotive: TPS74801-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS74801DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS74801DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS74801RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS74801RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jan-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS74801DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS74801DRCT VSON DRC 10 250 210.0 185.0 35.0
TPS74801RGWR VQFN RGW 20 3000 367.0 367.0 35.0
TPS74801RGWT VQFN RGW 20 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jan-2018
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRC 10 VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4204102-3/M
www.ti.com
PACKAGE OUTLINE
C
10X 0.30
0.18
2.4 0.1
2X
2
1.65 0.1
8X 0.5
1.0
0.8
10X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
4X (0.25)
2X (0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
10X (0.24)
(2.4)
(2.8)
8X (0.5)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
10X (0.6)
(R0.05) TYP
(3.4)
(0.25)
(0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
SYMM
1
56
10
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
11
SYMM
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
10X (0.24)
10X (0.6)
2X (1.5)
2X
(1.06)
(2.8)
(0.63)
8X (0.5)
(0.5)
4X (0.34)
4X (0.25)
(1.53)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
56
10
EXPOSED METAL
TYP
11
SYMM
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