Stellaris®LM3S6950 Microcontroller
DATA SHEET
Copyright ©2007-2012
Texas Instruments Incorporated
DS-LM3S6950-12746.2515
SPMS142H
TEXAS INSTRUMENTS-PRODUCTION DATA
Copyright
Copyright ©2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare®are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
June 18, 20122
Texas Instruments-Production Data
Table of Contents
Revision History ............................................................................................................................. 24
About This Document .................................................................................................................... 30
Audience .............................................................................................................................................. 30
About This Manual ................................................................................................................................ 30
Related Documents ............................................................................................................................... 30
Documentation Conventions .................................................................................................................. 31
1 Architectural Overview .......................................................................................... 33
1.1 Product Features .......................................................................................................... 33
1.2 Target Applications ........................................................................................................ 41
1.3 High-Level Block Diagram ............................................................................................. 42
1.4 Functional Overview ...................................................................................................... 44
1.4.1 ARM Cortex™-M3 ......................................................................................................... 44
1.4.2 Motor Control Peripherals .............................................................................................. 45
1.4.3 Analog Peripherals ........................................................................................................ 46
1.4.4 Serial Communications Peripherals ................................................................................ 46
1.4.5 System Peripherals ....................................................................................................... 48
1.4.6 Memory Peripherals ...................................................................................................... 48
1.4.7 Additional Features ....................................................................................................... 49
1.4.8 Hardware Details .......................................................................................................... 49
2 The Cortex-M3 Processor ...................................................................................... 51
2.1 Block Diagram .............................................................................................................. 52
2.2 Overview ...................................................................................................................... 53
2.2.1 System-Level Interface .................................................................................................. 53
2.2.2 Integrated Configurable Debug ...................................................................................... 53
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 54
2.2.4 Cortex-M3 System Component Details ........................................................................... 54
2.3 Programming Model ...................................................................................................... 55
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 55
2.3.2 Stacks .......................................................................................................................... 55
2.3.3 Register Map ................................................................................................................ 56
2.3.4 Register Descriptions .................................................................................................... 57
2.3.5 Exceptions and Interrupts .............................................................................................. 70
2.3.6 Data Types ................................................................................................................... 70
2.4 Memory Model .............................................................................................................. 70
2.4.1 Memory Regions, Types and Attributes ........................................................................... 72
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 72
2.4.3 Behavior of Memory Accesses ....................................................................................... 72
2.4.4 Software Ordering of Memory Accesses ......................................................................... 73
2.4.5 Bit-Banding ................................................................................................................... 74
2.4.6 Data Storage ................................................................................................................ 76
2.4.7 Synchronization Primitives ............................................................................................. 77
2.5 Exception Model ........................................................................................................... 78
2.5.1 Exception States ........................................................................................................... 79
2.5.2 Exception Types ............................................................................................................ 79
2.5.3 Exception Handlers ....................................................................................................... 82
3June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
2.5.4 Vector Table .................................................................................................................. 82
2.5.5 Exception Priorities ....................................................................................................... 83
2.5.6 Interrupt Priority Grouping .............................................................................................. 84
2.5.7 Exception Entry and Return ........................................................................................... 84
2.6 Fault Handling .............................................................................................................. 86
2.6.1 Fault Types ................................................................................................................... 87
2.6.2 Fault Escalation and Hard Faults .................................................................................... 87
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 88
2.6.4 Lockup ......................................................................................................................... 88
2.7 Power Management ...................................................................................................... 88
2.7.1 Entering Sleep Modes ................................................................................................... 89
2.7.2 Wake Up from Sleep Mode ............................................................................................ 89
2.8 Instruction Set Summary ............................................................................................... 90
3 Cortex-M3 Peripherals ........................................................................................... 93
3.1 Functional Description ................................................................................................... 93
3.1.1 System Timer (SysTick) ................................................................................................. 93
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 94
3.1.3 System Control Block (SCB) .......................................................................................... 96
3.1.4 Memory Protection Unit (MPU) ....................................................................................... 96
3.2 Register Map .............................................................................................................. 101
3.3 System Timer (SysTick) Register Descriptions .............................................................. 103
3.4 NVIC Register Descriptions .......................................................................................... 107
3.5 System Control Block (SCB) Register Descriptions ........................................................ 120
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 147
4 JTAG Interface ...................................................................................................... 157
4.1 Block Diagram ............................................................................................................ 158
4.2 Signal Description ....................................................................................................... 158
4.3 Functional Description ................................................................................................. 159
4.3.1 JTAG Interface Pins ..................................................................................................... 159
4.3.2 JTAG TAP Controller ................................................................................................... 161
4.3.3 Shift Registers ............................................................................................................ 162
4.3.4 Operational Considerations .......................................................................................... 162
4.4 Initialization and Configuration ..................................................................................... 165
4.5 Register Descriptions .................................................................................................. 165
4.5.1 Instruction Register (IR) ............................................................................................... 165
4.5.2 Data Registers ............................................................................................................ 168
5 System Control ..................................................................................................... 170
5.1 Signal Description ....................................................................................................... 170
5.2 Functional Description ................................................................................................. 170
5.2.1 Device Identification .................................................................................................... 171
5.2.2 Reset Control .............................................................................................................. 171
5.2.3 Power Control ............................................................................................................. 175
5.2.4 Clock Control .............................................................................................................. 176
5.2.5 System Control ........................................................................................................... 181
5.3 Initialization and Configuration ..................................................................................... 182
5.4 Register Map .............................................................................................................. 183
5.5 Register Descriptions .................................................................................................. 184
June 18, 20124
Texas Instruments-Production Data
Table of Contents
6 Hibernation Module .............................................................................................. 237
6.1 Block Diagram ............................................................................................................ 238
6.2 Signal Description ....................................................................................................... 238
6.3 Functional Description ................................................................................................. 239
6.3.1 Register Access Timing ............................................................................................... 239
6.3.2 Clock Source .............................................................................................................. 240
6.3.3 Battery Management ................................................................................................... 241
6.3.4 Real-Time Clock .......................................................................................................... 241
6.3.5 Battery-Backed Memory .............................................................................................. 242
6.3.6 Power Control ............................................................................................................. 242
6.3.7 Initiating Hibernate ...................................................................................................... 242
6.3.8 Interrupts and Status ................................................................................................... 243
6.4 Initialization and Configuration ..................................................................................... 243
6.4.1 Initialization ................................................................................................................. 243
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 243
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 244
6.4.4 External Wake-Up from Hibernation .............................................................................. 244
6.4.5 RTC/External Wake-Up from Hibernation ...................................................................... 244
6.5 Register Map .............................................................................................................. 244
6.6 Register Descriptions .................................................................................................. 245
7 Internal Memory ................................................................................................... 258
7.1 Block Diagram ............................................................................................................ 258
7.2 Functional Description ................................................................................................. 258
7.2.1 SRAM Memory ............................................................................................................ 258
7.2.2 Flash Memory ............................................................................................................. 259
7.3 Flash Memory Initialization and Configuration ............................................................... 260
7.3.1 Flash Programming ..................................................................................................... 260
7.3.2 Nonvolatile Register Programming ............................................................................... 261
7.4 Register Map .............................................................................................................. 262
7.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 263
7.6 Flash Register Descriptions (System Control Offset) ...................................................... 271
8 General-Purpose Input/Outputs (GPIOs) ........................................................... 284
8.1 Signal Description ....................................................................................................... 284
8.2 Functional Description ................................................................................................. 290
8.2.1 Data Control ............................................................................................................... 291
8.2.2 Interrupt Control .......................................................................................................... 292
8.2.3 Mode Control .............................................................................................................. 292
8.2.4 Commit Control ........................................................................................................... 292
8.2.5 Pad Control ................................................................................................................. 292
8.2.6 Identification ............................................................................................................... 293
8.3 Initialization and Configuration ..................................................................................... 293
8.4 Register Map .............................................................................................................. 294
8.5 Register Descriptions .................................................................................................. 296
9 General-Purpose Timers ...................................................................................... 331
9.1 Block Diagram ............................................................................................................ 332
9.2 Signal Description ....................................................................................................... 332
9.3 Functional Description ................................................................................................. 333
9.3.1 GPTM Reset Conditions .............................................................................................. 333
5June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
9.3.2 32-Bit Timer Operating Modes ...................................................................................... 333
9.3.3 16-Bit Timer Operating Modes ...................................................................................... 335
9.4 Initialization and Configuration ..................................................................................... 339
9.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 339
9.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 340
9.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 340
9.4.4 16-Bit Input Edge Count Mode ..................................................................................... 341
9.4.5 16-Bit Input Edge Timing Mode .................................................................................... 341
9.4.6 16-Bit PWM Mode ....................................................................................................... 342
9.5 Register Map .............................................................................................................. 342
9.6 Register Descriptions .................................................................................................. 343
10 Watchdog Timer ................................................................................................... 368
10.1 Block Diagram ............................................................................................................ 369
10.2 Functional Description ................................................................................................. 369
10.3 Initialization and Configuration ..................................................................................... 370
10.4 Register Map .............................................................................................................. 370
10.5 Register Descriptions .................................................................................................. 371
11 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 392
11.1 Block Diagram ............................................................................................................ 393
11.2 Signal Description ....................................................................................................... 393
11.3 Functional Description ................................................................................................. 394
11.3.1 Transmit/Receive Logic ............................................................................................... 394
11.3.2 Baud-Rate Generation ................................................................................................. 395
11.3.3 Data Transmission ...................................................................................................... 395
11.3.4 Serial IR (SIR) ............................................................................................................. 396
11.3.5 FIFO Operation ........................................................................................................... 397
11.3.6 Interrupts .................................................................................................................... 397
11.3.7 Loopback Operation .................................................................................................... 398
11.3.8 IrDA SIR block ............................................................................................................ 399
11.4 Initialization and Configuration ..................................................................................... 399
11.5 Register Map .............................................................................................................. 400
11.6 Register Descriptions .................................................................................................. 401
12 Synchronous Serial Interface (SSI) .................................................................... 435
12.1 Block Diagram ............................................................................................................ 435
12.2 Signal Description ....................................................................................................... 436
12.3 Functional Description ................................................................................................. 436
12.3.1 Bit Rate Generation ..................................................................................................... 436
12.3.2 FIFO Operation ........................................................................................................... 437
12.3.3 Interrupts .................................................................................................................... 437
12.3.4 Frame Formats ........................................................................................................... 438
12.4 Initialization and Configuration ..................................................................................... 445
12.5 Register Map .............................................................................................................. 446
12.6 Register Descriptions .................................................................................................. 447
13 Inter-Integrated Circuit (I2C) Interface ................................................................ 473
13.1 Block Diagram ............................................................................................................ 474
13.2 Signal Description ....................................................................................................... 474
13.3 Functional Description ................................................................................................. 474
June 18, 20126
Texas Instruments-Production Data
Table of Contents
13.3.1 I2C Bus Functional Overview ........................................................................................ 475
13.3.2 Available Speed Modes ............................................................................................... 477
13.3.3 Interrupts .................................................................................................................... 478
13.3.4 Loopback Operation .................................................................................................... 478
13.3.5 Command Sequence Flow Charts ................................................................................ 478
13.4 Initialization and Configuration ..................................................................................... 486
13.5 Register Map .............................................................................................................. 487
13.6 Register Descriptions (I2C Master) ............................................................................... 488
13.7 Register Descriptions (I2C Slave) ................................................................................. 501
14 Ethernet Controller .............................................................................................. 510
14.1 Block Diagram ............................................................................................................ 510
14.2 Signal Description ....................................................................................................... 511
14.3 Functional Description ................................................................................................. 513
14.3.1 MAC Operation ........................................................................................................... 513
14.3.2 Internal MII Operation .................................................................................................. 516
14.3.3 PHY Operation ............................................................................................................ 516
14.3.4 Interrupts .................................................................................................................... 518
14.4 Initialization and Configuration ..................................................................................... 518
14.4.1 Hardware Configuration ............................................................................................... 518
14.4.2 Software Configuration ................................................................................................ 519
14.5 Ethernet Register Map ................................................................................................. 520
14.6 Ethernet MAC Register Descriptions ............................................................................. 521
14.7 MII Management Register Descriptions ......................................................................... 540
15 Analog Comparators ............................................................................................ 559
15.1 Block Diagram ............................................................................................................ 560
15.2 Signal Description ....................................................................................................... 560
15.3 Functional Description ................................................................................................. 561
15.3.1 Internal Reference Programming .................................................................................. 562
15.4 Initialization and Configuration ..................................................................................... 563
15.5 Register Map .............................................................................................................. 563
15.6 Register Descriptions .................................................................................................. 564
16 Pulse Width Modulator (PWM) ............................................................................ 572
16.1 Block Diagram ............................................................................................................ 573
16.2 Signal Description ....................................................................................................... 574
16.3 Functional Description ................................................................................................. 575
16.3.1 PWM Timer ................................................................................................................. 575
16.3.2 PWM Comparators ...................................................................................................... 575
16.3.3 PWM Signal Generator ................................................................................................ 576
16.3.4 Dead-Band Generator ................................................................................................. 577
16.3.5 Interrupt Selector ......................................................................................................... 577
16.3.6 Synchronization Methods ............................................................................................ 578
16.3.7 Fault Conditions .......................................................................................................... 578
16.3.8 Output Control Block ................................................................................................... 578
16.4 Initialization and Configuration ..................................................................................... 578
16.5 Register Map .............................................................................................................. 579
16.6 Register Descriptions .................................................................................................. 581
7June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
17 Quadrature Encoder Interface (QEI) ................................................................... 610
17.1 Block Diagram ............................................................................................................ 610
17.2 Signal Description ....................................................................................................... 611
17.3 Functional Description ................................................................................................. 612
17.4 Initialization and Configuration ..................................................................................... 614
17.5 Register Map .............................................................................................................. 614
17.6 Register Descriptions .................................................................................................. 615
18 Pin Diagram .......................................................................................................... 628
19 Signal Tables ........................................................................................................ 630
19.1 100-Pin LQFP Package Pin Tables ............................................................................... 630
19.1.1 Signals by Pin Number ................................................................................................ 630
19.1.2 Signals by Signal Name ............................................................................................... 634
19.1.3 Signals by Function, Except for GPIO ........................................................................... 639
19.1.4 GPIO Pins and Alternate Functions .............................................................................. 642
19.2 108-Ball BGA Package Pin Tables ................................................................................ 644
19.2.1 Signals by Pin Number ................................................................................................ 644
19.2.2 Signals by Signal Name ............................................................................................... 648
19.2.3 Signals by Function, Except for GPIO ........................................................................... 653
19.2.4 GPIO Pins and Alternate Functions .............................................................................. 656
19.3 Connections for Unused Signals ................................................................................... 657
20 Operating Characteristics ................................................................................... 660
21 Electrical Characteristics .................................................................................... 661
21.1 DC Characteristics ...................................................................................................... 661
21.1.1 Maximum Ratings ....................................................................................................... 661
21.1.2 Recommended DC Operating Conditions ...................................................................... 661
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 662
21.1.4 GPIO Module Characteristics ....................................................................................... 662
21.1.5 Power Specifications ................................................................................................... 662
21.1.6 Flash Memory Characteristics ...................................................................................... 664
21.1.7 Hibernation ................................................................................................................. 664
21.1.8 Ethernet Controller ...................................................................................................... 664
21.2 AC Characteristics ....................................................................................................... 664
21.2.1 Load Conditions .......................................................................................................... 664
21.2.2 Clocks ........................................................................................................................ 665
21.2.3 JTAG and Boundary Scan ............................................................................................ 666
21.2.4 Reset ......................................................................................................................... 668
21.2.5 Sleep Modes ............................................................................................................... 670
21.2.6 Hibernation Module ..................................................................................................... 670
21.2.7 General-Purpose I/O (GPIO) ........................................................................................ 670
21.2.8 Synchronous Serial Interface (SSI) ............................................................................... 671
21.2.9 Inter-Integrated Circuit (I2C) Interface ........................................................................... 672
21.2.10 Ethernet Controller ...................................................................................................... 673
21.2.11 Analog Comparator ..................................................................................................... 676
A Serial Flash Loader .............................................................................................. 677
A.1 Serial Flash Loader ..................................................................................................... 677
A.2 Interfaces ................................................................................................................... 677
A.2.1 UART ......................................................................................................................... 677
June 18, 20128
Texas Instruments-Production Data
Table of Contents
A.2.2 SSI ............................................................................................................................. 677
A.3 Packet Handling .......................................................................................................... 678
A.3.1 Packet Format ............................................................................................................ 678
A.3.2 Sending Packets ......................................................................................................... 678
A.3.3 Receiving Packets ....................................................................................................... 678
A.4 Commands ................................................................................................................. 679
A.4.1 COMMAND_PING (0X20) ............................................................................................ 679
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 679
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 679
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 680
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 680
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 680
B Register Quick Reference ................................................................................... 682
C Ordering and Contact Information ..................................................................... 705
C.1 Ordering Information .................................................................................................... 705
C.2 Part Markings .............................................................................................................. 705
C.3 Kits ............................................................................................................................. 706
C.4 Support Information ..................................................................................................... 706
D Package Information ............................................................................................ 707
D.1 100-Pin LQFP Package ............................................................................................... 707
D.1.1 Package Dimensions ................................................................................................... 707
D.1.2 Tray Dimensions ......................................................................................................... 709
D.1.3 Tape and Reel Dimensions .......................................................................................... 709
D.2 108-Ball BGA Package ................................................................................................ 711
D.2.1 Package Dimensions ................................................................................................... 711
D.2.2 Tray Dimensions ......................................................................................................... 713
D.2.3 Tape and Reel Dimensions .......................................................................................... 714
9June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S6950 Microcontroller High-Level Block Diagram ............................... 43
Figure 2-1. CPU Block Diagram ............................................................................................. 53
Figure 2-2. TPIU Block Diagram ............................................................................................ 54
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 56
Figure 2-4. Bit-Band Mapping ................................................................................................ 76
Figure 2-5. Data Storage ....................................................................................................... 77
Figure 2-6. Vector Table ........................................................................................................ 83
Figure 2-7. Exception Stack Frame ........................................................................................ 85
Figure 3-1. SRD Use Example ............................................................................................... 99
Figure 4-1. JTAG Module Block Diagram .............................................................................. 158
Figure 4-2. Test Access Port State Machine ......................................................................... 162
Figure 4-3. IDCODE Register Format ................................................................................... 168
Figure 4-4. BYPASS Register Format ................................................................................... 168
Figure 4-5. Boundary Scan Register Format ......................................................................... 169
Figure 5-1. Basic RST Configuration .................................................................................... 172
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 173
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 173
Figure 5-4. Power Architecture ............................................................................................ 176
Figure 5-5. Main Clock Tree ................................................................................................ 178
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 238
Figure 6-2. Clock Source Using Crystal ................................................................................ 240
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 241
Figure 7-1. Flash Block Diagram .......................................................................................... 258
Figure 8-1. GPIO Port Block Diagram ................................................................................... 290
Figure 8-2. GPIODATA Write Example ................................................................................. 291
Figure 8-3. GPIODATA Read Example ................................................................................. 291
Figure 9-1. GPTM Module Block Diagram ............................................................................ 332
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 337
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 338
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 339
Figure 10-1. WDT Module Block Diagram .............................................................................. 369
Figure 11-1. UART Module Block Diagram ............................................................................. 393
Figure 11-2. UART Character Frame ..................................................................................... 395
Figure 11-3. IrDA Data Modulation ......................................................................................... 397
Figure 12-1. SSI Module Block Diagram ................................................................................. 435
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 438
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 439
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 440
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 440
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 441
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 442
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 442
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 443
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 444
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 445
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 445
June 18, 201210
Texas Instruments-Production Data
Table of Contents
Figure 13-1. I2C Block Diagram ............................................................................................. 474
Figure 13-2. I2C Bus Configuration ........................................................................................ 475
Figure 13-3. START and STOP Conditions ............................................................................. 475
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 476
Figure 13-5. R/S Bit in First Byte ............................................................................................ 476
Figure 13-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 476
Figure 13-7. Master Single SEND .......................................................................................... 480
Figure 13-8. Master Single RECEIVE ..................................................................................... 481
Figure 13-9. Master Burst SEND ........................................................................................... 482
Figure 13-10. Master Burst RECEIVE ...................................................................................... 483
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 484
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 485
Figure 13-13. Slave Command Sequence ................................................................................ 486
Figure 14-1. Ethernet Controller ............................................................................................. 511
Figure 14-2. Ethernet Controller Block Diagram ...................................................................... 511
Figure 14-3. Ethernet Frame ................................................................................................. 513
Figure 14-4. Interface to an Ethernet Jack .............................................................................. 519
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 560
Figure 15-2. Structure of Comparator Unit .............................................................................. 562
Figure 15-3. Comparator Internal Reference Structure ............................................................ 562
Figure 16-1. PWM Unit Diagram ............................................................................................ 573
Figure 16-2. PWM Module Block Diagram .............................................................................. 574
Figure 16-3. PWM Count-Down Mode .................................................................................... 576
Figure 16-4. PWM Count-Up/Down Mode .............................................................................. 576
Figure 16-5. PWM Generation Example In Count-Up/Down Mode ........................................... 577
Figure 16-6. PWM Dead-Band Generator ............................................................................... 577
Figure 17-1. QEI Block Diagram ............................................................................................ 611
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 613
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 628
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 629
Figure 21-1. Load Conditions ................................................................................................ 665
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 667
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 667
Figure 21-4. JTAG TRST Timing ............................................................................................ 668
Figure 21-5. External Reset Timing (RST) .............................................................................. 668
Figure 21-6. Power-On Reset Timing ..................................................................................... 669
Figure 21-7. Brown-Out Reset Timing .................................................................................... 669
Figure 21-8. Software Reset Timing ....................................................................................... 669
Figure 21-9. Watchdog Reset Timing ..................................................................................... 669
Figure 21-10. Hibernation Module Timing ................................................................................. 670
Figure 21-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 671
Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 672
Figure 21-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 672
Figure 21-14. I2C Timing ......................................................................................................... 673
Figure 21-15. External XTLP Oscillator Characteristics ............................................................. 675
Figure D-1. Stellaris LM3S6950 100-Pin LQFP Package Dimensions ..................................... 707
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 709
11June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 710
Figure D-4. Stellaris LM3S6950 108-Ball BGA Package Dimensions ...................................... 711
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 713
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 714
June 18, 201212
Texas Instruments-Production Data
Table of Contents
List of Tables
Table 1. Revision History .................................................................................................. 24
Table 2. Documentation Conventions ................................................................................ 31
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 56
Table 2-2. Processor Register Map ....................................................................................... 57
Table 2-3. PSR Register Combinations ................................................................................. 62
Table 2-4. Memory Map ....................................................................................................... 70
Table 2-5. Memory Access Behavior ..................................................................................... 72
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 74
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 75
Table 2-8. Exception Types .................................................................................................. 80
Table 2-9. Interrupts ............................................................................................................ 81
Table 2-10. Exception Return Behavior ................................................................................... 86
Table 2-11. Faults ................................................................................................................. 87
Table 2-12. Fault Status and Fault Address Registers .............................................................. 88
Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 90
Table 3-1. Core Peripheral Register Regions ......................................................................... 93
Table 3-2. Memory Attributes Summary ................................................................................ 96
Table 3-3. TEX, S, C, and B Bit Field Encoding ..................................................................... 99
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 100
Table 3-5. AP Bit Field Encoding ........................................................................................ 100
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 100
Table 3-7. Peripherals Register Map ................................................................................... 101
Table 3-8. Interrupt Priority Levels ...................................................................................... 126
Table 3-9. Example SIZE Field Values ................................................................................ 154
Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 158
Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 159
Table 4-3. JTAG Port Pins Reset State ............................................................................... 159
Table 4-4. JTAG Instruction Register Commands ................................................................. 166
Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 170
Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 170
Table 5-3. Reset Sources ................................................................................................... 171
Table 5-4. Clock Source Options ........................................................................................ 177
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 179
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 179
Table 5-7. System Control Register Map ............................................................................. 183
Table 5-8. RCC2 Fields that Override RCC fields ................................................................. 198
Table 6-1. Hibernate Signals (100LQFP) ............................................................................. 238
Table 6-2. Hibernate Signals (108BGA) .............................................................................. 239
Table 6-3. Hibernation Module Register Map ....................................................................... 245
Table 7-1. Flash Protection Policy Combinations ................................................................. 259
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 262
Table 7-3. Flash Register Map ............................................................................................ 262
Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 285
Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 285
Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 286
Table 8-4. GPIO Signals (100LQFP) ................................................................................... 287
13June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 8-5. GPIO Signals (108BGA) ..................................................................................... 288
Table 8-6. GPIO Pad Configuration Examples ..................................................................... 293
Table 8-7. GPIO Interrupt Configuration Example ................................................................ 294
Table 8-8. GPIO Register Map ........................................................................................... 295
Table 9-1. Available CCP Pins ............................................................................................ 332
Table 9-2. General-Purpose Timers Signals (100LQFP) ....................................................... 333
Table 9-3. General-Purpose Timers Signals (108BGA) ......................................................... 333
Table 9-4. 16-Bit Timer With Prescaler Configurations ......................................................... 335
Table 9-5. Timers Register Map .......................................................................................... 342
Table 10-1. Watchdog Timer Register Map ............................................................................ 370
Table 11-1. UART Signals (100LQFP) .................................................................................. 393
Table 11-2. UART Signals (108BGA) .................................................................................... 394
Table 11-3. UART Register Map ........................................................................................... 400
Table 12-1. SSI Signals (100LQFP) ...................................................................................... 436
Table 12-2. SSI Signals (108BGA) ........................................................................................ 436
Table 12-3. SSI Register Map .............................................................................................. 447
Table 13-1. I2C Signals (100LQFP) ...................................................................................... 474
Table 13-2. I2C Signals (108BGA) ........................................................................................ 474
Table 13-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 477
Table 13-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 487
Table 13-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 492
Table 14-1. Ethernet Signals (100LQFP) ............................................................................... 512
Table 14-2. Ethernet Signals (108BGA) ................................................................................ 512
Table 14-3. TX & RX FIFO Organization ............................................................................... 515
Table 14-4. Ethernet Register Map ....................................................................................... 520
Table 15-1. Analog Comparators Signals (100LQFP) ............................................................. 560
Table 15-2. Analog Comparators Signals (108BGA) .............................................................. 561
Table 15-3. Internal Reference Voltage and ACREFCTL Field Values ..................................... 562
Table 15-4. Analog Comparators Register Map ..................................................................... 564
Table 16-1. PWM Signals (100LQFP) ................................................................................... 574
Table 16-2. PWM Signals (108BGA) ..................................................................................... 574
Table 16-3. PWM Register Map ............................................................................................ 580
Table 17-1. QEI Signals (100LQFP) ...................................................................................... 611
Table 17-2. QEI Signals (108BGA) ....................................................................................... 611
Table 17-3. QEI Register Map .............................................................................................. 614
Table 19-1. Signals by Pin Number ....................................................................................... 630
Table 19-2. Signals by Signal Name ..................................................................................... 634
Table 19-3. Signals by Function, Except for GPIO ................................................................. 639
Table 19-4. GPIO Pins and Alternate Functions ..................................................................... 642
Table 19-5. Signals by Pin Number ....................................................................................... 644
Table 19-6. Signals by Signal Name ..................................................................................... 648
Table 19-7. Signals by Function, Except for GPIO ................................................................. 653
Table 19-8. GPIO Pins and Alternate Functions ..................................................................... 656
Table 19-9. Connections for Unused Signals (100-pin LQFP) ................................................. 658
Table 19-10. Connections for Unused Signals, 108-pin BGA .................................................... 659
Table 20-1. Temperature Characteristics ............................................................................... 660
Table 20-2. Thermal Characteristics ..................................................................................... 660
Table 20-3. ESD Absolute Maximum Ratings ........................................................................ 660
June 18, 201214
Texas Instruments-Production Data
Table of Contents
Table 21-1. Maximum Ratings .............................................................................................. 661
Table 21-2. Recommended DC Operating Conditions ............................................................ 661
Table 21-3. LDO Regulator Characteristics ........................................................................... 662
Table 21-4. GPIO Module DC Characteristics ........................................................................ 662
Table 21-5. Detailed Power Specifications ............................................................................ 663
Table 21-6. Flash Memory Characteristics ............................................................................ 664
Table 21-7. Hibernation Module DC Characteristics ............................................................... 664
Table 21-8. Ethernet Controller DC Characteristics ................................................................ 664
Table 21-9. Phase Locked Loop (PLL) Characteristics ........................................................... 665
Table 21-10. Actual PLL Frequency ........................................................................................ 665
Table 21-11. Clock Characteristics ......................................................................................... 665
Table 21-12. Crystal Characteristics ....................................................................................... 666
Table 21-13. JTAG Characteristics ......................................................................................... 666
Table 21-14. Reset Characteristics ......................................................................................... 668
Table 21-15. Sleep Modes AC Characteristics ......................................................................... 670
Table 21-16. Hibernation Module AC Characteristics ............................................................... 670
Table 21-17. GPIO Characteristics ......................................................................................... 671
Table 21-18. SSI Characteristics ............................................................................................ 671
Table 21-19. I2C Characteristics ............................................................................................. 672
Table 21-20. 100BASE-TX Transmitter Characteristics ............................................................ 673
Table 21-21. 100BASE-TX Transmitter Characteristics (informative) ......................................... 673
Table 21-22. 100BASE-TX Receiver Characteristics ................................................................ 674
Table 21-23. 10BASE-T Transmitter Characteristics ................................................................ 674
Table 21-24. 10BASE-T Transmitter Characteristics (informative) ............................................. 674
Table 21-25. 10BASE-T Receiver Characteristics .................................................................... 674
Table 21-26. Isolation Transformers ....................................................................................... 674
Table 21-27. Ethernet Reference Crystal ................................................................................ 675
Table 21-28. External XTLP Oscillator Characteristics ............................................................. 676
Table 21-29. Analog Comparator Characteristics ..................................................................... 676
Table 21-30. Analog Comparator Voltage Reference Characteristics ........................................ 676
Table C-1. Part Ordering Information ................................................................................... 705
15June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
List of Registers
The Cortex-M3 Processor ............................................................................................................. 51
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 58
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 58
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 58
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 58
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 58
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 58
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 58
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 58
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 58
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 58
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 58
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 58
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 58
Register 14: Stack Pointer (SP) ........................................................................................................... 59
Register 15: Link Register (LR) ............................................................................................................ 60
Register 16: Program Counter (PC) ..................................................................................................... 61
Register 17: Program Status Register (PSR) ........................................................................................ 62
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 66
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 67
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 68
Register 21: Control Register (CONTROL) ........................................................................................... 69
Cortex-M3 Peripherals ................................................................................................................... 93
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 104
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 106
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 107
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 108
Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................ 109
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 110
Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................ 111
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 112
Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 113
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 114
Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 115
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 116
Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 117
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 118
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 118
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 118
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 118
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 118
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 118
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 118
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 118
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 118
June 18, 201216
Texas Instruments-Production Data
Table of Contents
Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 118
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 118
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 120
Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 121
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 122
Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 125
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 126
Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 128
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 130
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 132
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 133
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 134
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 135
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 139
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 145
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 146
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 147
Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 148
Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 149
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 151
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 152
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 152
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 152
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 152
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 154
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 154
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 154
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 154
System Control ............................................................................................................................ 170
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 185
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 187
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 188
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 189
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 190
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 191
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 192
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 193
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 197
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 198
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 200
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 201
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 203
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 204
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 206
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 208
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 210
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 212
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 214
17June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 216
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 218
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 221
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 224
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 227
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 229
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 231
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 233
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 234
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 236
Hibernation Module ..................................................................................................................... 237
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 246
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 247
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 248
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 249
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 250
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 252
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 253
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 254
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 255
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 256
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 257
Internal Memory ........................................................................................................................... 258
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 264
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 265
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 266
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 268
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 269
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 270
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 272
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 273
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 274
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 275
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 276
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 277
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 278
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 279
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 280
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 281
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 282
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 283
General-Purpose Input/Outputs (GPIOs) ................................................................................... 284
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 297
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 298
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 299
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 300
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 301
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 302
June 18, 201218
Texas Instruments-Production Data
Table of Contents
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 303
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 304
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 305
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 306
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 308
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 309
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 310
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 311
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 312
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 313
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 314
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 315
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 316
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 317
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 319
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 320
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 321
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 322
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 323
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 324
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 325
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 326
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 327
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 328
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 329
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 330
General-Purpose Timers ............................................................................................................. 331
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 344
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 345
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 347
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 349
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 352
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 354
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 355
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 356
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 358
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 359
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 360
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 361
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 362
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 363
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 364
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 365
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 366
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 367
Watchdog Timer ........................................................................................................................... 368
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 372
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 373
19June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 374
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 375
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 376
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 377
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 378
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 379
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 380
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 381
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 382
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 383
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 384
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 385
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 386
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 387
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 388
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 389
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 390
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 391
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 392
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 402
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 404
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 406
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 408
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 409
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 410
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 411
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 413
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 415
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 417
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 419
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 420
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 421
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 423
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 424
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 425
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 426
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 427
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 428
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 429
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 430
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 431
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 432
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 433
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 434
Synchronous Serial Interface (SSI) ............................................................................................ 435
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 448
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 450
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 452
June 18, 201220
Texas Instruments-Production Data
Table of Contents
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 453
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 455
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 456
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 458
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 459
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 460
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 461
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 462
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 463
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 464
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 465
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 466
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 467
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 468
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 469
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 470
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 471
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 472
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 473
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 489
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 490
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 494
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 495
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 496
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 497
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 498
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 499
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 500
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 502
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 503
Register 12: I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 505
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 506
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 507
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 508
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 509
Ethernet Controller ...................................................................................................................... 510
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 522
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 525
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 526
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 527
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 528
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 530
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 531
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 532
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 534
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 535
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 536
21June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 537
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 538
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 539
Register 15: Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 540
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 541
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 543
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 545
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 546
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 547
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 549
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 550
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 551
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 553
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 555
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 556
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 557
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 558
Analog Comparators ................................................................................................................... 559
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 565
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 566
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 567
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 568
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 569
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 569
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 569
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 570
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 570
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 570
Pulse Width Modulator (PWM) .................................................................................................... 572
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 582
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 583
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 584
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 585
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 586
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 587
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 588
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 589
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 590
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 591
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 591
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 591
Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 593
Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084 ...................................................... 593
Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4 ...................................................... 593
June 18, 201222
Texas Instruments-Production Data
Table of Contents
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 595
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 595
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 595
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 596
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 596
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 596
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 597
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 597
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 597
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 598
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 598
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 598
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 599
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 599
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 599
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 600
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 600
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 600
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 601
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 601
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 601
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 604
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 604
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 604
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 607
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 607
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 607
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 608
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 608
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 608
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 609
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 609
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 609
Quadrature Encoder Interface (QEI) .......................................................................................... 610
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 616
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 618
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 619
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 620
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 621
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 622
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 623
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 624
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 625
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 626
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 627
23June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S6950
data sheet.
Table 1. Revision History
DescriptionRevisionDate
■ Corrected missing interrupt 9 in "Interrupts" table.
■ Removed extended temperature package.
■ Minor data sheet clarifications and corrections.
12746.2515June 2012
■ Added module-specific pin tables to each chapter in the new Signal Description sections.
■ In Hibernation chapter:
– Changed terminology from non-volatile memory to battery-backed memory.
– Clarified Hibernation module register reset conditions.
■ In Timer chapter, clarified that in 16-Bit Input Edge Time Mode, the timer is capable of capturing
three types of events: rising edge, falling edge, or both.
■ In UART chapter, clarified interrupt behavior.
■ In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)".
■ In Signal Tables chapter:
–Corrected pin numbers in table "Connections for Unused Signals" (other pin tables were correct).
– Corrected buffer type for PWMn signals in pin tables.
■ In Electrical Characteristics chapter:
– Added parameter "Input voltage for a GPIO configured as an analog input" to the "Maximum
Ratings" table.
–Corrected Nom values for parameters "TCK clock Low time" and "TCK clock High time" in "JTAG
Characteristics" table.
■ Additional minor data sheet clarifications and corrections.
11108November 2011
June 18, 201224
Texas Instruments-Production Data
Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
■In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.
■ Added "Reset Sources" table to System Control chapter.
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be four-bits
wide, bits[7:4].
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■Changed I2C slave register base addresses and offsets to be relative to the I2C module base address
of 0x4002.0000 , so register bases and offsets were changed for all I2C slave registers. Note that
the hw_i2c.h file in the StellarisWare®Driver Library uses a base address of 0x4002.0800 for the
I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that
StellarisWare uses the old slave base address for these offsets.
■ Added GNDPHY and VCCPHY to Connections for Unused Signals tables.
■ Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (VNON parameter in Maximum Ratings table).
■ Additional minor data sheet clarifications and corrections.
9102January 2011
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control
and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the
Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register.
■ Added clarification of instruction execution during Flash operations.
■ Modified Figure 8-1 on page 290 to clarify operation of the GPIO inputs when used as an alternate
function.
■Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
wide, bits[7:0].
■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Electrical Characteristics chapter:
– Added ILKG parameter (GPIO input leakage current) to Table 21-4 on page 662.
– Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 21-18 on page 671.
– Added "Ethernet Controller DC Characteristics" table (see Table 21-8 on page 664).
■ Added dimensions for Tray and Tape and Reel shipping mediums.
7787September 2010
25June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 1. Revision History (continued)
DescriptionRevisionDate
■ Corrected base address for SRAM in architectural overview chapter.
■ Clarified system clock operation, adding content to “Clock Control” on page 176.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
■ Additional minor data sheet clarifications and corrections.
7393June 2010
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Removed erroneous text about restoring the Flash Protection registers.
■ Added note about RST signal routing.
■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
■ Corrected XTALNPHY pin description.
■ Additional minor data sheet clarifications and corrections.
7007April 2010
■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
6712January 2010
■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
■Deleted reset value for 16-bit mode from GPTMTAILR,GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Made these changes to the Electrical Characteristics chapter:
– Removed VSIH and VSIL parameters from Operating Conditions table.
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
6462October 2009
Corrected ordering numbers.5920July 2009
June 18, 201226
Texas Instruments-Production Data
Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■Added explanation of reset value to FMPRE0/1/2/3,FMPPE0/1/2/3,USER_DBG, and USER_REG0/1
registers.
■ Added description for Ethernet PHY power-saving modes.
■ Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
5902July 2009
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 164).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 21-4 on page 662).
■ Additional minor data sheet clarifications and corrections.
5367April 2009
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Added "Hardware Configuration" section to Ethernet Controller chapter.
■ Additional minor data sheet clarifications and corrections.
4660January 2009
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
4283November 2008
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ In the Ethernet chapter, major improvements were made including a rewrite of the conceptual
information and the addition of new figures to clarify how to use the Ethernet Controller interface.
■Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
4149October 2008
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
3447August 2008
27June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 1. Revision History (continued)
DescriptionRevisionDate
■ Corrected resistor value in ERBIAS signal description.
■ Additional minor data sheet clarifications and corrections.
3108July 2008
■ As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported:
TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit
fields in the MR23 register are now marked as reserved.
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS.
A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device
revisions (see “Functional Description” on page 513).
■ Additional minor data sheet clarifications and corrections.
2972May 2008
2881April 2008 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
■The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter
was changed from a max of 100 to 250.
■The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical
Characteristics" chapter was changed from 4 to 3.
■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).
■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.
■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).
■ Two figures on clock source were added to the "Hibernation Module":
– Clock Source Using Crystal
– Clock Source Using Dedicated Oscillator
■ The following notes on battery management were added to the "Hibernation Module" chapter:
– Battery voltage is not measured while in Hibernate mode.
– System level factors may affect the accuracy of the low battery detect circuit. The designer
should consider battery type, discharge characteristics, and a test load during battery voltage
measurements.
■ A note on high-current applications was added to the GPIO chapter:
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
June 18, 201228
Texas Instruments-Production Data
Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
■ A note on Schmitt inputs was added to the GPIO chapter:
Pins configured as digital inputs are Schmitt-triggered.
■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.
■ The "Differential Sampling Range" figures in the ADC chapter were clarified.
■The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
■ Additional minor data sheet clarifications and corrections.
Started tracking revision history.2550March 2008
29June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
About This Document
This data sheet provides reference information for the LM3S6950 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Stellaris®web site at www.ti.com/stellaris:
■Stellaris® Errata
■ARM® Cortex™-M3 Errata
■Cortex™-M3/M4 Instruction Set Technical User's Manual
■Stellaris® Graphics Library User's Guide
■Stellaris® Peripheral Driver Library User's Guide
The following related documents are also referenced:
■ARM® Debug Interface V5 Architecture Specification
■ARM® Embedded Trace Macrocell Architecture Specification
■IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
June 18, 201230
Texas Instruments-Production Data
About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 31.
Table 2. Documentation Conventions
MeaningNotation
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 70.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. Writing to it with any value clears the register.R/WC
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
R/W1S
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Reset Value
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin/Signal Notation
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
31June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 2. Documentation Conventions (continued)
MeaningNotation
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
June 18, 201232
Texas Instruments-Production Data
About This Document
1 Architectural Overview
The Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The Stellaris family offers efficient performance and extensive integration, favorably positioning the
device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris LM3S6000 series combines both a 10/100 Ethernet Media Access Control
(MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with
an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an
ARM architecture MCU.
The LM3S6950 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S6950 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S6950 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S6950 microcontroller perfectly for
battery applications.
In addition, the LM3S6950 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6950 microcontroller is code-compatible
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 705 for ordering information for Stellaris family devices.
1.1 Product Features
The LM3S6950 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
–System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
33June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 34 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
–Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
–Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
• Serial Wire JTAG Debug Port (SWJ-DP)
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
June 18, 201234
Texas Instruments-Production Data
Architectural Overview
– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
– Integrated ARM Serial Wire Debug (SWD)
■ Hibernation
– System power control using discrete external regulator
– Dedicated pin for waking from an external signal
– Low-battery detection, signaling, and interrupt generation
– 32-bit real-time clock (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
– RTC predivider trim for making fine adjustments to the clock rate
– 64 32-bit words of non-volatile memory
– Programmable interrupts for RTC match, external wake, and low battery events
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ GPIOs
– 1-46 GPIOs, depending on configuration
– 5-V-tolerant in input configuration
– Fast toggle capable of a change every two clock cycles
– Programmable control for GPIO interrupts
• Interrupt generation masking
35June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
• Edge-triggered on rising, falling, or both
• Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
• Input edge count capture
June 18, 201236
Texas Instruments-Production Data
Architectural Overview
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– Line-break generation and detection
– Fully programmable serial interface characteristics
• 5, 6, 7, or 8 data bits
• Even, odd, stick, or no-parity bit generation/detection
• 1 or 2 stop bit generation
– IrDA serial-IR (SIR) encoder/decoder providing
• Programmable use of IrDA Serial Infrared (SIR) or UART input/output
•Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
• Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
• Programmable internal clock generator enabling division of reference clock by 1 to 256
for low-power mode bit duration
■ Synchronous Serial Interface (SSI)
37June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
– Two SSI modules, each with the following features:
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ I2C
– Devices on the I2C bus can be designated as either a master or a slave
• Supports both sending and receiving data as either a master or a slave
• Supports simultaneous master and slave operation
– Four I2C modes
• Master transmit
• Master receive
• Slave transmit
• Slave receive
– Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
– Master and slave interrupt generation
• Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)
• Slave generates interrupts when data has been sent or requested by a master
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ 10/100 Ethernet Controller
–Conforms to the IEEE 802.3-2002 specification
• 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation
transformer interface to the line
• 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
• Full-featured auto-negotiation
June 18, 201238
Texas Instruments-Production Data
Architectural Overview
– Multiple operational modes
• Full- and half-duplex 100 Mbps
• Full- and half-duplex 10 Mbps
• Power-saving and power-down modes
– Highly configurable
• Programmable MAC address
• LED activity selection
• Promiscuous mode support
• CRC error-rejection control
• User-configurable interrupts
– Physical media manipulation
• Automatic MDI/MDI-X cross-over correction
• Register-programmable transmit amplitude
• Automatic polarity correction and 10BASE-T signal reception
– IEEE 1588 Precision Time Protocol - provides highly accurate time stamps for individual
packets
■ Analog Comparators
– Three independent integrated analog comparators
– Configurable for output to drive an output pin or generate an interrupt
–Compare external pin input to external pin input or to internal programmable voltage reference
– Compare a test voltage against any one of these voltages
• An individual external reference voltage
• A shared single external reference voltage
• A shared internal reference voltage
■ PWM
– Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM
signal generator, a dead-band generator, and an interrupt selector
– One fault input in hardware to promote low-latency shutdown
– One 16-bit counter
• Runs in Down or Up/Down mode
39June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
■ QEI
– Position integrator that tracks the encoder position
– Velocity capture using built-in timer
– The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
– Interrupt generation on:
• Index pulse
• Velocity-timer expiration
• Direction change
• Quadrature error detection
June 18, 201240
Texas Instruments-Production Data
Architectural Overview
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Industrial temperature 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
41June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 1-1. Stellaris LM3S6950 Microcontroller High-Level Block Diagram
ARM®
Cortex™-M3
(50MHz)
NVIC MPU
Flash
(256KB)
DCodebus
ICodebus
JTAG/SWD
System
Controland
Clocks
(w/ Precis. Osc.)
Bus Matrix
System Bus
SRAM
(64KB)
SYSTEM PERIPHERALS
Watchdog
Timer
(1)
Hibernation
Module
General-
Purpose
Timer (4)
GPIOs
(1-46)
SERIAL PERIPHERALS
UART
(3)
I2C
(1)
SSI
(2)
Ethernet
MAC/PHY
ANALOG PERIPHERALS
Analog
Comparator
(3)
MOTION CONTROL PERIPHERALS
QEI
(1)
PWM
(6)
Advanced Peripheral Bus (APB)
LM3S6950
43June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6950 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 705.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 51)
All members of the Stellaris product family, including the LM3S6950 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.4.1.2 Memory Map (see page 70)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S6950 controller can be found in Table 2-4 on page 70. Register addresses are given as a
hexadecimal increment, relative to the module's base address as shown in the memory map.
1.4.1.3 System Timer (SysTick) (see page 93)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 94)
The LM3S6950 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 34 interrupts.
June 18, 201244
Texas Instruments-Production Data
Architectural Overview
1.4.1.5 System Control Block (SCB) (see page 96)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.4.1.6 Memory Protection Unit (MPU) (see page 96)
The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model.
The MPU provides full support for protection regions, overlapping protection regions, access
permissions, and exporting memory attributes to the system.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6950 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S6950, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 572)
The LM3S6950 PWM module consists of three PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt. The control block determines the
polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 338)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
Fault Pin (see page 578)
The LM3S6950 PWM module includes one fault-condition handling input to quickly provide low-latency
shutdown and prevent damage to the motor being controlled.
1.4.2.2 QEI (see page 610)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
45June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
1.4.3 Analog Peripherals
For support of analog signals, the LM3S6950 microcontroller offers three analog comparators.
1.4.3.1 Analog Comparators (see page 559)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6950 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt .
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
1.4.4 Serial Communications Peripherals
The LM3S6950 controller supports both asynchronous and synchronous serial communications
with:
■ Three fully programmable 16C550-type UARTs
■ Two SSI modules
■ One I2C module
■ Ethernet controller
1.4.4.1 UART (see page 392)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S6950 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
June 18, 201246
Texas Instruments-Production Data
Architectural Overview
1.4.4.2 SSI (see page 435)
Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications
interface.
The LM3S6950 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 473)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S6950 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Ethernet Controller (see page 510)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
47June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 284)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris GPIO module is comprised of seven physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 1-46 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 630 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.
1.4.5.2 Four Programmable Timers (see page 331)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 368)
A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S6950 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 258)
The LM3S6950 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
June 18, 201248
Texas Instruments-Production Data
Architectural Overview
1.4.6.2 Flash (see page 259)
The LM3S6950 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 JTAG TAP Controller (see page 157)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST,TCK,TMS,TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
1.4.7.2 System Control and Clocks (see page 170)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.3 Hibernation Module (see page 237)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 628
■ “Signal Tables” on page 630
49June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
2 The Cortex-M3 Processor
The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ Compact core.
■Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motor control.
51June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor,
including the programming model, the memory model, the exception model, fault handling, and
power management.
For technical details on the instruction set, see the Cortex™-M3/M4 Instruction Set Technical User's
Manual.
2.1 Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including a range of single-cycle and SIMD multiplication
and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction
set based on Thumb-2 technology, ensuring high code density and reduced program memory
requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a
modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI)
and provides eight interrupt priority levels. The tight integration of the processor core and NVIC
provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
June 18, 201252
Texas Instruments-Production Data
The Cortex-M3 Processor
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Debug
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Overview
2.2.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris
implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification
for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
53June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 54.
Figure 2-2. TPIU Block Diagram
ATB
Interface Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 93).
■ Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 94).
■ System Control Block (SCB)
June 18, 201254
Texas Instruments-Production Data
The Cortex-M3 Processor
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 96).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 96).
2.3 Programming Model
This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M3 has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 69) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
55June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 59).
In Thread mode, the CONTROL register (see page 69) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 56.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Stack UsedPrivilege LevelUseProcessor Mode
Main stack or process stack a
Privileged or unprivileged a
ApplicationsThread
Main stackAlways privilegedException handlersHandler
a. See CONTROL (page 69).
2.3.3 Register Map
Figure 2-3 on page 56 shows the Cortex-M3 register set. Table 2-2 on page 57 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP‡
PSP‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡Banked version of SP
June 18, 201256
Texas Instruments-Production Data
The Cortex-M3 Processor
Table 2-2. Processor Register Map
See
page
DescriptionResetTypeNameOffset
58Cortex General-Purpose Register 0-R/WR0-
58Cortex General-Purpose Register 1-R/WR1-
58Cortex General-Purpose Register 2-R/WR2-
58Cortex General-Purpose Register 3-R/WR3-
58Cortex General-Purpose Register 4-R/WR4-
58Cortex General-Purpose Register 5-R/WR5-
58Cortex General-Purpose Register 6-R/WR6-
58Cortex General-Purpose Register 7-R/WR7-
58Cortex General-Purpose Register 8-R/WR8-
58Cortex General-Purpose Register 9-R/WR9-
58Cortex General-Purpose Register 10-R/WR10-
58Cortex General-Purpose Register 11-R/WR11-
58Cortex General-Purpose Register 12-R/WR12-
59Stack Pointer-R/WSP-
60Link Register0xFFFF.FFFFR/WLR-
61Program Counter-R/WPC-
62Program Status Register0x0100.0000R/WPSR-
66Priority Mask Register0x0000.0000R/WPRIMASK-
67Fault Mask Register0x0000.0000R/WFAULTMASK-
68Base Priority Mask Register0x0000.0000R/WBASEPRI-
69Control Register0x0000.0000R/WCONTROL-
2.3.4 Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 56.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
57June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type R/W, reset -
16171819202122232425262728293031
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
Register data.-R/WDATA31:0
June 18, 201258
Texas Instruments-Production Data
The Cortex-M3 Processor
Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type R/W, reset -
16171819202122232425262728293031
SP
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
SP
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
This field is the address of the stack pointer.-R/WSP31:0
59June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 86 for the values and
description.
Link Register (LR)
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
LINK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
LINK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
This field is the return address.0xFFFF.FFFFR/WLINK31:0
June 18, 201260
Texas Instruments-Production Data
The Cortex-M3 Processor
Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type R/W, reset -
16171819202122232425262728293031
PC
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
PC
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
This field is the current program address.-R/WPC31:0
61June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: Program Status Register (PSR)
Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■Application Program Status Register (APSR), bits 31:27,
■Execution Program Status Register (EPSR), bits 26:24, 15:10
■Interrupt Program Status Register (IPSR), bits 5:0
The PSR,IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 84).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 62 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
CombinationTypeRegister
APSR,EPSR, and IPSRR/Wa,b
PSR
EPSR and IPSRROIEPSR
APSR and IPSRR/Wa
IAPSR
APSR and EPSRR/Wb
EAPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type R/W, reset 0x0100.0000
16171819202122232425262728293031
reservedTHUMBICI / ITQVCZN
ROROROROROROROROROROROR/WR/WR/WR/WR/WType
0000000010000000Reset
0123456789101112131415
ISRNUMreservedICI / IT
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
June 18, 201262
Texas Instruments-Production Data
The Cortex-M3 Processor
DescriptionResetTypeNameBit/Field
APSR Negative or Less Flag
DescriptionValue
The previous operation result was negative or less than.1
The previous operation result was positive, zero, greater than,
or equal.
0
The value of this bit is only meaningful when accessing PSR or APSR.
0R/WN31
APSR Zero Flag
DescriptionValue
The previous operation result was zero.1
The previous operation result was non-zero.0
The value of this bit is only meaningful when accessing PSR or APSR.
0R/WZ30
APSR Carry or Borrow Flag
DescriptionValue
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
1
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
0
The value of this bit is only meaningful when accessing PSR or APSR.
0R/WC29
APSR Overflow Flag
DescriptionValue
The previous operation resulted in an overflow.1
The previous operation did not result in an overflow.0
The value of this bit is only meaningful when accessing PSR or APSR.
0R/WV28
APSR DSP Overflow and Saturation Flag
DescriptionValue
DSP Overflow or saturation has occurred.1
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
0
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
0R/WQ27
63June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
0x0ROICI / IT26:25
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■ The BLX,BX and POP{PC} instructions
■ Restoration from the stacked xPSR value on an exception return
■ Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 88 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
1ROTHUMB24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved23:16
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM,STM,PUSH
or POP instruction, the processor stops the load multiple or store multiple
instruction operation temporarily and stores the next register operand
in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes
execution of the multiple load or store instruction. When EPSR holds
the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
0x0ROICI / IT15:10
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved9:6
June 18, 201264
Texas Instruments-Production Data
The Cortex-M3 Processor
DescriptionResetTypeNameBit/Field
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
DescriptionValue
Thread mode0x00
Reserved0x01
NMI0x02
Hard fault0x03
Memory management fault0x04
Bus fault0x05
Usage fault0x06
Reserved0x07-0x0A
SVCall0x0B
Reserved for Debug0x0C
Reserved0x0D
PendSV0x0E
SysTick0x0F
Interrupt Vector 00x10
Interrupt Vector 10x11
......
Interrupt Vector 430x3B
Reserved0x3C-0x3F
See “Exception Types” on page 79 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
0x00ROISRNUM5:0
65June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on these instructions.
For more information on exception priority levels, see “Exception Types” on page 79.
Priority Mask Register (PRIMASK)
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PRIMASKreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
Priority Mask
DescriptionValue
Prevents the activation of all exceptions with configurable
priority.
1
No effect.0
0R/WPRIMASK0
June 18, 201266
Texas Instruments-Production Data
The Cortex-M3 Processor
Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see “Exception
Types” on page 79.
Fault Mask Register (FAULTMASK)
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FAULTMASK
reserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
Fault Mask
DescriptionValue
Prevents the activation of all exceptions except for NMI.1
No effect.0
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
0R/WFAULTMASK0
67June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 79.
Base Priority Mask Register (BASEPRI)
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBASEPRIreserved
ROROROROROR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
DescriptionValue
All exceptions are unmasked.0x0
All exceptions with priority level 1-7 are masked.0x1
All exceptions with priority level 2-7 are masked.0x2
All exceptions with priority level 3-7 are masked.0x3
All exceptions with priority level 4-7 are masked.0x4
All exceptions with priority level 5-7 are masked.0x5
All exceptions with priority level 6-7 are masked.0x6
All exceptions with priority level 7 are masked.0x7
0x0R/WBASEPRI7:5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved4:0
June 18, 201268
Texas Instruments-Production Data
The Cortex-M3 Processor
Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 86).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex™-M3/M4 Instruction Set Technical User's Manual, or perform an exception
return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 86.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Control Register (CONTROL)
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TMPLASPreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Active Stack Pointer
DescriptionValue
PSP is the current stack pointer.1
MSP is the current stack pointer0
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
0R/WASP1
Thread Mode Privilege Level
DescriptionValue
Unprivileged software can be executed in Thread mode.1
Only privileged software can be executed in Thread mode.0
0R/WTMPL0
69June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
2.3.5 Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 84 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 94 for more information.
2.3.6 Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 72 for more information.
2.4 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S6950 controller is provided in Table 2-4 on page 70. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 74).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 93).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
For details,
see page ...
DescriptionEndStart
Memory
263On-chip Flash0x0003.FFFF0x0000.0000
-Reserved0x1FFF.FFFF0x0004.0000
258Bit-banded on-chip SRAM0x2000.FFFF0x2000.0000
-Reserved0x21FF.FFFF0x2001.0000
258Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
0x221F.FFFF0x2200.0000
-
Reserved0x3FFF.FFFF0x2220.0000
FiRM Peripherals
371Watchdog timer 00x4000.0FFF0x4000.0000
-Reserved0x4000.3FFF0x4000.1000
296GPIO Port A0x4000.4FFF0x4000.4000
296GPIO Port B0x4000.5FFF0x4000.5000
296GPIO Port C0x4000.6FFF0x4000.6000
296GPIO Port D0x4000.7FFF0x4000.7000
447SSI00x4000.8FFF0x4000.8000
June 18, 201270
Texas Instruments-Production Data
The Cortex-M3 Processor
Table 2-4. Memory Map (continued)
For details,
see page ...
DescriptionEndStart
447SSI10x4000.9FFF0x4000.9000
-Reserved0x4000.BFFF0x4000.A000
401UART00x4000.CFFF0x4000.C000
401UART10x4000.DFFF0x4000.D000
401UART20x4000.EFFF0x4000.E000
-
Reserved0x4001.FFFF0x4000.F000
Peripherals
488I2C 00x4002.0FFF0x4002.0000
-Reserved0x4002.3FFF0x4002.1000
296GPIO Port E0x4002.4FFF0x4002.4000
296GPIO Port F0x4002.5FFF0x4002.5000
296GPIO Port G0x4002.6FFF0x4002.6000
-Reserved0x4002.7FFF0x4002.7000
581PWM0x4002.8FFF0x4002.8000
-Reserved0x4002.BFFF0x4002.9000
615QEI00x4002.CFFF0x4002.C000
-Reserved0x4002.FFFF0x4002.D000
343Timer 00x4003.0FFF0x4003.0000
343Timer 10x4003.1FFF0x4003.1000
343Timer 20x4003.2FFF0x4003.2000
343Timer 30x4003.3FFF0x4003.3000
-Reserved0x4003.BFFF0x4003.4000
559Analog Comparators0x4003.CFFF0x4003.C000
-Reserved0x400F.BFFF0x4003.D000
245Hibernation Module0x400F.CFFF0x400F.C000
263Flash memory control0x400F.DFFF0x400F.D000
184System control0x400F.EFFF0x400F.E000
-Reserved0x41FF.FFFF0x400F.F000
-Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000
-
Reserved0xDFFF.FFFF0x4400.0000
Private Peripheral Bus
53Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000
53Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000
53Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000
-Reserved0xE000.DFFF0xE000.3000
101Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB)0xE000.EFFF0xE000.E000
-Reserved0xE003.FFFF0xE000.F000
54Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000
-
Reserved0xFFFF.FFFF0xE004.1000
71June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
2.4.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 73).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3 Behavior of Memory Accesses
Table 2-5 on page 72 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 72 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 70 for more information).
Table 2-5. Memory Access Behavior
DescriptionExecute
Never
(XN)
Memory TypeMemory RegionAddress Range
This executable region is for program code.
Data can also be stored here.
-NormalCode0x0000.0000 - 0x1FFF.FFFF
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 74).
-NormalSRAM0x2000.0000 - 0x3FFF.FFFF
This region includes bit band and bit band
alias areas (see Table 2-7 on page 75).
XNDevicePeripheral0x4000.0000 - 0x5FFF.FFFF
This executable region is for data.-NormalExternal RAM0x6000.0000 - 0x9FFF.FFFF
June 18, 201272
Texas Instruments-Production Data
The Cortex-M3 Processor
Table 2-5. Memory Access Behavior (continued)
DescriptionExecute
Never
(XN)
Memory TypeMemory RegionAddress Range
This region is for external device memory.XNDeviceExternal device0xA000.0000 - 0xDFFF.FFFF
This region includes the NVIC, system
timer, and system control block.
XNStrongly
Ordered
Private peripheral
bus
0xE000.0000- 0xE00F.FFFF
---Reserved0xE010.0000- 0xFFFF.FFFF
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 96.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
2.4.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 72 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
–If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
73June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M3/M4 Instruction Set
Technical User's Manual.
2.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 74. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 75. For the specific address range of the bit-band regions,
see Table 2-4 on page 70.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Instruction and Data AccessesMemory Region
Address Range
EndStart
Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
SRAM bit-band region0x2000.FFFF0x2000.0000
June 18, 201274
Texas Instruments-Production Data
The Cortex-M3 Processor
Table 2-6. SRAM Memory Bit-Banding Regions (continued)
Instruction and Data AccessesMemory Region
Address Range
EndStart
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
SRAM bit-band alias0x221F.FFFF0x2200.0000
Table 2-7. Peripheral Memory Bit-Banding Regions
Instruction and Data AccessesMemory Region
Address Range
EndStart
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
Peripheral bit-band
region
0x400F.FFFF0x4000.0000
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
Peripheral bit-band alias0x43FF.FFFF0x4200.0000
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 76 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
75June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
Figure 2-4. Bit-Band Mapping
0x23FF.FFE4
0x2200.0004
0x23FF.FFE00x23FF.FFE80x23FF.FFEC0x23FF.FFF00x23FF.FFF40x23FF.FFF80x23FF.FFFC
0x2200.00000x2200.00140x2200.00180x2200.001C 0x2200.00080x2200.0010 0x2200.000C
32-MB Alias Region
0
7 0
07
0x2000.00000x2000.00010x2000.00020x2000.0003
654321 07654321 7654321 07654321
07654321 65432107654321 07654321
0x200F.FFFC0x200F.FFFD0x200F.FFFE0x200F.FFFF
1-MB SRAM Bit-Band Region
2.4.5.1 Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2 Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 72 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6 Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 77 illustrates how data is stored.
June 18, 201276
Texas Instruments-Production Data
The Cortex-M3 Processor
Figure 2-5. Data Storage
Memory Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 16 15 8 7 0
B0
B1
B2
B3
2.4.7 Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
77June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M3/M4
Instruction Set Technical User's Manual.
2.5 Exception Model
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 80 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 34 interrupts (listed in Table 2-9 on page 81).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 94.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 94 for more information on exceptions
and interrupts.
June 18, 201278
Texas Instruments-Production Data
The Cortex-M3 Processor
2.5.1 Exception States
Each exception is in one of the following states:
■Inactive. The exception is not active and not pending.
■Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2 Exception Types
The exception types are:
■Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
79June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 81 lists the interrupts on the LM3S6950 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 80 shows as having
configurable priority (see the SYSHNDCTRL register on page 135 and the DIS0 register on page 110).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 86.
Table 2-8. Exception Types
ActivationVector Address or
Offsetb
Prioritya
Vector
Number
Exception Type
Stack top is loaded from the first
entry of the vector table on reset.
0x0000.0000-0-
Asynchronous0x0000.0004-3 (highest)1Reset
Asynchronous0x0000.0008-22Non-Maskable Interrupt
(NMI)
-0x0000.000C-13Hard Fault
Synchronous0x0000.0010programmablec
4Memory Management
Synchronous when precise and
asynchronous when imprecise
0x0000.0014programmablec
5Bus Fault
Synchronous0x0000.0018programmablec
6Usage Fault
Reserved--7-10-
Synchronous0x0000.002Cprogrammablec
11SVCall
Synchronous0x0000.0030programmablec
12Debug Monitor
Reserved--13-
June 18, 201280
Texas Instruments-Production Data
The Cortex-M3 Processor
Table 2-8. Exception Types (continued)
ActivationVector Address or
Offsetb
Prioritya
Vector
Number
Exception Type
Asynchronous0x0000.0038programmablec
14PendSV
Asynchronous0x0000.003Cprogrammablec
15SysTick
Asynchronous0x0000.0040 and aboveprogrammabled
16 and aboveInterrupts
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 82.
c. See SYSPRI1 on page 132.
d. See PRIn registers on page 118.
Table 2-9. Interrupts
DescriptionVector Address or
Offset
Interrupt Number (Bit
in Interrupt Registers)
Vector Number
Processor exceptions0x0000.0000 -
0x0000.003C
-0-15
GPIO Port A0x0000.0040016
GPIO Port B0x0000.0044117
GPIO Port C0x0000.0048218
GPIO Port D0x0000.004C319
GPIO Port E0x0000.0050420
UART00x0000.0054521
UART10x0000.0058622
SSI00x0000.005C723
I2C00x0000.0060824
PWM Fault0x0000.0064925
PWM Generator 00x0000.00681026
PWM Generator 10x0000.006C1127
PWM Generator 20x0000.00701228
QEI00x0000.00741329
Reserved-14-1730-33
Watchdog Timer 00x0000.00881834
Timer 0A0x0000.008C1935
Timer 0B0x0000.00902036
Timer 1A0x0000.00942137
Timer 1B0x0000.00982238
Timer 2A0x0000.009C2339
Timer 2B0x0000.00A02440
Analog Comparator 00x0000.00A42541
Analog Comparator 10x0000.00A82642
Analog Comparator 20x0000.00AC2743
System Control0x0000.00B02844
Flash Memory Control0x0000.00B42945
GPIO Port F0x0000.00B83046
GPIO Port G0x0000.00BC3147
81June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 2-9. Interrupts (continued)
DescriptionVector Address or
Offset
Interrupt Number (Bit
in Interrupt Registers)
Vector Number
Reserved-3248
UART20x0000.00C43349
SSI10x0000.00C83450
Timer 3A0x0000.00CC3551
Timer 3B0x0000.00D03652
Reserved-37-4153-57
Ethernet Controller0x0000.00E84258
Hibernation Module0x0000.00EC4359
2.5.3 Exception Handlers
The processor handles exceptions using:
■Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4 Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 80. Figure 2-6 on page 83 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
June 18, 201282
Texas Instruments-Production Data
The Cortex-M3 Processor
Figure 2-6. Vector Table
Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
Systick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
OffsetException number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ43
17 0x0048
0x004C
59
.
.
.
.
.
.
0x00EC
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
43
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 82). Note
that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary.
2.5.5 Exception Priorities
As Table 2-8 on page 80 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 132 and
page 118.
Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means
that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always
have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
83June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 126.
2.5.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
■Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 84 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 85 more information.
■Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 86 for
more information.
■Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
June 18, 201284
Texas Instruments-Production Data
The Cortex-M3 Processor
return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1 Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 66, FAULTMASK on page 67, and BASEPRI on page 68). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
Figure 2-7. Exception Stack Frame
Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
...
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless
stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN
bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during
stacking.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
85June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
2.5.7.2 Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 86
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
DescriptionEXC_RETURN[31:0]
Reserved0xFFFF.FFF0
Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF1
Reserved0xFFFF.FFF2 - 0xFFFF.FFF8
Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF9
Reserved0xFFFF.FFFA - 0xFFFF.FFFC
Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
0xFFFF.FFFD
Reserved0xFFFF.FFFE - 0xFFFF.FFFF
2.6 Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 78). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
■ An internally detected error such as an undefined instruction or an attempt to change state with
aBX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
June 18, 201286
Texas Instruments-Production Data
The Cortex-M3 Processor
2.6.1 Fault Types
Table 2-11 on page 87 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 139 for more
information about the fault status registers.
Table 2-11. Faults
Bit NameFault Status RegisterHandlerFault
VECTHard Fault Status (HFAULTSTAT)Hard faultBus error on a vector read
FORCEDHard Fault Status (HFAULTSTAT)Hard faultFault escalated to a hard fault
IERR a
Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
instruction access
DERRMemory Management Fault Status
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
data access
MSTKEMemory Management Fault Status
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
exception stacking
MUSTKEMemory Management Fault Status
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
exception unstacking
BSTKEBus Fault Status (BFAULTSTAT)Bus faultBus error during exception stacking
BUSTKEBus Fault Status (BFAULTSTAT)Bus faultBus error during exception unstacking
IBUSBus Fault Status (BFAULTSTAT)Bus faultBus error during instruction prefetch
PRECISEBus Fault Status (BFAULTSTAT)Bus faultPrecise data bus error
IMPREBus Fault Status (BFAULTSTAT)Bus faultImprecise data bus error
NOCPUsage Fault Status (UFAULTSTAT)Usage faultAttempt to access a coprocessor
UNDEFUsage Fault Status (UFAULTSTAT)Usage faultUndefined instruction
INVSTATUsage Fault Status (UFAULTSTAT)Usage faultAttempt to enter an invalid instruction
set state b
INVPCUsage Fault Status (UFAULTSTAT)Usage faultInvalid EXC_RETURN value
UNALIGNUsage Fault Status (UFAULTSTAT)Usage faultIllegal unaligned load or store
DIV0Usage Fault Status (UFAULTSTAT)Usage faultDivide by 0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.
2.6.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 132). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 135).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 78.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
87June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
2.6.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 88.
Table 2-12. Fault Status and Fault Address Registers
Register DescriptionAddress Register NameStatus Register NameHandler
page 145-Hard Fault Status (HFAULTSTAT)Hard fault
page 139
page 146
Memory Management Fault
Address (MMADDR)
Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
page 139
page 147
Bus Fault Address
(FAULTADDR)
Bus Fault Status (BFAULTSTAT)Bus fault
page 139-Usage Fault Status (UFAULTSTAT)Usage fault
2.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
2.7 Power Management
The Cortex-M3 processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 128). For more information about the behavior of the sleep modes, see “System
Control” on page 181.
June 18, 201288
Texas Instruments-Production Data
The Cortex-M3 Processor
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1 Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 89). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.3 Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2 Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.
2.7.2.1 Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 66 and page 67.
2.7.2.2 Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
89June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 128.
2.8 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 90 lists the
supported instructions.
Note: In Table 2-13 on page 90:
■ Angle brackets, <>, enclose alternative forms of the operand
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
FlagsBrief DescriptionOperandsMnemonic
N,Z,C,VAdd with carry{Rd,} Rn, Op2ADC, ADCS
N,Z,C,VAdd{Rd,} Rn, Op2ADD, ADDS
N,Z,C,VAdd{Rd,} Rn , #imm12ADD, ADDW
-Load PC-relative addressRd, labelADR
N,Z,CLogical AND{Rd,} Rn, Op2AND, ANDS
N,Z,CArithmetic shift rightRd, Rm, <Rs|#n>ASR, ASRS
-BranchlabelB
-Bit field clearRd, #lsb, #widthBFC
-Bit field insertRd, Rn, #lsb, #widthBFI
N,Z,CBit clear{Rd,} Rn, Op2BIC, BICS
-Breakpoint#immBKPT
-Branch with linklabelBL
-Branch indirect with linkRmBLX
-Branch indirectRmBX
-Compare and branch if non-zeroRn, labelCBNZ
-Compare and branch if zeroRn, labelCBZ
-Clear exclusive-CLREX
-Count leading zerosRd, RmCLZ
N,Z,C,VCompare negativeRn, Op2CMN
N,Z,C,VCompareRn, Op2CMP
-Change processor state, disable
interrupts
iCPSID
-Change processor state, enable
interrupts
iCPSIE
-Data memory barrier-DMB
-Data synchronization barrier-DSB
June 18, 201290
Texas Instruments-Production Data
The Cortex-M3 Processor
Table 2-13. Cortex-M3 Instruction Summary (continued)
FlagsBrief DescriptionOperandsMnemonic
N,Z,CExclusive OR{Rd,} Rn, Op2EOR, EORS
-Instruction synchronization barrier-ISB
-If-Then condition block-IT
-Load multiple registers, increment afterRn{!}, reglistLDM
-Load multiple registers, decrement
before
Rn{!}, reglistLDMDB, LDMEA
-Load multiple registers, increment afterRn{!}, reglistLDMFD, LDMIA
-Load register with wordRt, [Rn, #offset]LDR
-Load register with byteRt, [Rn, #offset]LDRB, LDRBT
-Load register with two bytesRt, Rt2, [Rn, #offset]LDRD
-Load register exclusiveRt, [Rn, #offset]LDREX
-Load register exclusive with byteRt, [Rn]LDREXB
-Load register exclusive with halfwordRt, [Rn]LDREXH
-Load register with halfwordRt, [Rn, #offset]LDRH, LDRHT
-Load register with signed byteRt, [Rn, #offset]LDRSB, LDRSBT
-Load register with signed halfwordRt, [Rn, #offset]LDRSH, LDRSHT
-Load register with wordRt, [Rn, #offset]LDRT
N,Z,CLogical shift leftRd, Rm, <Rs|#n>LSL, LSLS
N,Z,CLogical shift rightRd, Rm, <Rs|#n>LSR, LSRS
-Multiply with accumulate, 32-bit resultRd, Rn, Rm, RaMLA
-Multiply and subtract, 32-bit resultRd, Rn, Rm, RaMLS
N,Z,CMoveRd, Op2MOV, MOVS
N,Z,CMove 16-bit constantRd, #imm16MOV, MOVW
-Move topRd, #imm16MOVT
-Move from special register to general
register
Rd, spec_regMRS
N,Z,C,VMove from general register to special
register
spec_reg, RmMSR
N,ZMultiply, 32-bit result{Rd,} Rn, RmMUL, MULS
N,Z,CMove NOTRd, Op2MVN, MVNS
-No operation-NOP
N,Z,CLogical OR NOT{Rd,} Rn, Op2ORN, ORNS
N,Z,CLogical OR{Rd,} Rn, Op2ORR, ORRS
-Pop registers from stackreglistPOP
-Push registers onto stackreglistPUSH
-Reverse bitsRd, RnRBIT
-Reverse byte order in a wordRd, RnREV
-Reverse byte order in each halfwordRd, RnREV16
-Reverse byte order in bottom halfword
and sign extend
Rd, RnREVSH
N,Z,CRotate rightRd, Rm, <Rs|#n>ROR, RORS
N,Z,CRotate right with extendRd, RmRRX, RRXS
91June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 2-13. Cortex-M3 Instruction Summary (continued)
FlagsBrief DescriptionOperandsMnemonic
N,Z,C,VReverse subtract{Rd,} Rn, Op2RSB, RSBS
N,Z,C,VSubtract with carry{Rd,} Rn, Op2SBC, SBCS
-Signed bit field extractRd, Rn, #lsb, #widthSBFX
-Signed divide{Rd,} Rn, RmSDIV
-Send event-SEV
-Signed multiply with accumulate
(32x32+64), 64-bit result
RdLo, RdHi, Rn, RmSMLAL
-Signed multiply (32x32), 64-bit resultRdLo, RdHi, Rn, RmSMULL
QSigned saturateRd, #n, Rm {,shift #s}SSAT
-Store multiple registers, increment afterRn{!}, reglistSTM
-Store multiple registers, decrement
before
Rn{!}, reglistSTMDB, STMEA
-Store multiple registers, increment afterRn{!}, reglistSTMFD, STMIA
-Store register wordRt, [Rn {, #offset}]STR
-Store register byteRt, [Rn {, #offset}]STRB, STRBT
-Store register two wordsRt, Rt2, [Rn {, #offset}]STRD
-Store register exclusiveRt, Rt, [Rn {, #offset}]STREX
-Store register exclusive byteRd, Rt, [Rn]STREXB
-Store register exclusive halfwordRd, Rt, [Rn]STREXH
-Store register halfwordRt, [Rn {, #offset}]STRH, STRHT
-Store register signed byteRt, [Rn {, #offset}]STRSB, STRSBT
-Store register signed halfwordRt, [Rn {, #offset}]STRSH, STRSHT
-Store register wordRt, [Rn {, #offset}]STRT
N,Z,C,VSubtract{Rd,} Rn, Op2SUB, SUBS
N,Z,C,VSubtract 12-bit constant{Rd,} Rn, #imm12SUB, SUBW
-Supervisor call#immSVC
-Sign extend a byte{Rd,} Rm {,ROR #n}SXTB
-Sign extend a halfword{Rd,} Rm {,ROR #n}SXTH
-Table branch byte[Rn, Rm]TBB
-Table branch halfword[Rn, Rm, LSL #1]TBH
N,Z,CTest equivalenceRn, Op2TEQ
N,Z,CTestRn, Op2TST
-Unsigned bit field extractRd, Rn, #lsb, #widthUBFX
-Unsigned divide{Rd,} Rn, RmUDIV
-Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
RdLo, RdHi, Rn, RmUMLAL
-Unsigned multiply (32x 2), 64-bit resultRdLo, RdHi, Rn, RmUMULL
QUnsigned SaturateRd, #n, Rm {,shift #s}USAT
-Zero extend a Byte{Rd,} Rm, {,ROR #n}UXTB
-Zero extend a Halfword{Rd,} Rm, {,ROR #n}UXTH
-Wait for event-WFE
-Wait for interrupt-WFI
June 18, 201292
Texas Instruments-Production Data
The Cortex-M3 Processor
3 Cortex-M3 Peripherals
This chapter provides information on the Stellaris®implementation of the Cortex-M3 processor
peripherals, including:
■ SysTick (see page 93)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 94)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 96)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 96)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Table 3-1 on page 93 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Description (see page ...)Core PeripheralAddress
93System Timer0xE000.E010-0xE000.E01F
94Nested Vectored Interrupt Controller0xE000.E100-0xE000.E4EF
0xE000.EF00-0xE000.EF03
96System Control Block0xE000.ED00-0xE000.ED3F
96Memory Protection Unit0xE000.ED90-0xE000.EDB8
3.1 Functional Description
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.
3.1.1 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
93June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
Note: When the processor is halted for debugging, the counter does not decrement.
3.1.2 Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 34 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
June 18, 201294
Texas Instruments-Production Data
Cortex-M3 Peripherals
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 95 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2 Hardware and Software Control of Interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 112 or SWTRIG on page 120.
A pending interrupt remains pending until one of the following:
■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
95June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4 Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 72 for more information).
Table 3-2 on page 96 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Stellaris Microcontroller” on page 100 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
DescriptionMemory Type
All accesses to Strongly Ordered memory occur in program order.Strongly Ordered
Memory-mapped peripheralsDevice
Normal memoryNormal
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
June 18, 201296
Texas Instruments-Production Data
Cortex-M3 Peripherals
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1 Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER),MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
97June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable
This operation can be done in two words for pre-packed information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 152) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 154) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
June 18, 201298
Texas Instruments-Production Data
Cortex-M3 Peripherals
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 99 shows.
Figure 3-1. SRD Use Example
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
3.1.4.2 MPU Access Permission Attributes
The access permission bits, TEX,S,C,B,AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 99 shows the encodings for the TEX,C,B, and Saccess permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M3 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Stellaris Microcontroller” on page 100 for information on programming the MPU for Stellaris
implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
Other AttributesShareabilityMemory TypeBCSTEX
-ShareableStrongly Ordered00xa
000b
-ShareableDevice10xa
000
Outer and inner
write-through. No write
allocate.
Not shareableNormal010000
ShareableNormal011000
Not shareableNormal110000
ShareableNormal111000
Outer and inner
noncacheable.
Not shareableNormal000001
ShareableNormal001001
--Reserved encoding10xa
001
--Reserved encoding01xa
001
Outer and inner
write-back. Write and
read allocate.
Not shareableNormal110001
ShareableNormal111001
Nonshared Device.Not shareableDevice00xa
010
--Reserved encoding10xa
010
--Reserved encodingxa
1xa
010
99June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
Other AttributesShareabilityMemory TypeBCSTEX
Cached memory (BB =
outer policy, AA = inner
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
Not shareableNormalAA01BB
ShareableNormalAA11BB
a. The MPU ignores the value of this bit.
Table 3-4 on page 100 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Corresponding Cache PolicyEncoding, AA or BB
Non-cacheable00
Write back, write and read allocate01
Write through, no write allocate10
Write back, no write allocate11
Table 3-5 on page 100 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
DescriptionUnprivileged
Permissions
Privileged
Permissions
AP Bit Field
All accesses generate a permission fault.No accessNo access000
Access from privileged software only.No accessR/W001
Writes by unprivileged software generate a
permission fault.
ROR/W010
Full access.R/WR/W011
Reserved.UnpredictableUnpredictable100
Reads by privileged software only.No accessRO101
Read-only, by privileged or unprivileged software.RORO110
Read-only, by privileged or unprivileged software.RORO111
MPU Configuration for a Stellaris Microcontroller
Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should
be programmed as shown in Table 3-6 on page 100.
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers
Memory Type and AttributesBCSTEXMemory Region
Normal memory, non-shareable, write-through010000bFlash memory
Normal memory, shareable, write-through011000bInternal SRAM
Normal memory, shareable, write-back,
write-allocate
111000bExternal SRAM
Device memory, shareable101000bPeripherals
June 18, 2012100
Texas Instruments-Production Data
Cortex-M3 Peripherals
In current Stellaris microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.
3.1.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 70 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 139 for more information.
3.2 Register Map
Table 3-7 on page 101 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU and SCB registers. The
offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-7. Peripherals Register Map
See
page
DescriptionResetTypeNameOffset
System Timer (SysTick) Registers
104SysTick Control and Status Register0x0000.0000R/WSTCTRL0x010
106SysTick Reload Value Register0x0000.0000R/WSTRELOAD0x014
107SysTick Current Value Register0x0000.0000R/WCSTCURRENT0x018
Nested Vectored Interrupt Controller (NVIC) Registers
108Interrupt 0-31 Set Enable0x0000.0000R/WEN00x100
109Interrupt 32-43 Set Enable0x0000.0000R/WEN10x104
110Interrupt 0-31 Clear Enable0x0000.0000R/WDIS00x180
111Interrupt 32-43 Clear Enable0x0000.0000R/WDIS10x184
112Interrupt 0-31 Set Pending0x0000.0000R/WPEND00x200
113Interrupt 32-43 Set Pending0x0000.0000R/WPEND10x204
114Interrupt 0-31 Clear Pending0x0000.0000R/WUNPEND00x280
115Interrupt 32-43 Clear Pending0x0000.0000R/WUNPEND10x284
116Interrupt 0-31 Active Bit0x0000.0000ROACTIVE00x300
117Interrupt 32-43 Active Bit0x0000.0000ROACTIVE10x304
118Interrupt 0-3 Priority0x0000.0000R/WPRI00x400
118Interrupt 4-7 Priority0x0000.0000R/WPRI10x404
118Interrupt 8-11 Priority0x0000.0000R/WPRI20x408
118Interrupt 12-15 Priority0x0000.0000R/WPRI30x40C
118Interrupt 16-19 Priority0x0000.0000R/WPRI40x410
101June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 3-7. Peripherals Register Map (continued)
See
page
DescriptionResetTypeNameOffset
118Interrupt 20-23 Priority0x0000.0000R/WPRI50x414
118Interrupt 24-27 Priority0x0000.0000R/WPRI60x418
118Interrupt 28-31 Priority0x0000.0000R/WPRI70x41C
118Interrupt 32-35 Priority0x0000.0000R/WPRI80x420
118Interrupt 36-39 Priority0x0000.0000R/WPRI90x424
118Interrupt 40-43 Priority0x0000.0000R/WPRI100x428
120Software Trigger Interrupt0x0000.0000WOSWTRIG0xF00
System Control Block (SCB) Registers
121CPU ID Base0x411F.C231ROCPUID0xD00
122Interrupt Control and State0x0000.0000R/WINTCTRL0xD04
125Vector Table Offset0x0000.0000R/WVTABLE0xD08
126Application Interrupt and Reset Control0xFA05.0000R/WAPINT0xD0C
128System Control0x0000.0000R/WSYSCTRL0xD10
130Configuration and Control0x0000.0000R/WCFGCTRL0xD14
132System Handler Priority 10x0000.0000R/WSYSPRI10xD18
133System Handler Priority 20x0000.0000R/WSYSPRI20xD1C
134System Handler Priority 30x0000.0000R/WSYSPRI30xD20
135System Handler Control and State0x0000.0000R/WSYSHNDCTRL0xD24
139Configurable Fault Status0x0000.0000R/W1CFAULTSTAT0xD28
145Hard Fault Status0x0000.0000R/W1CHFAULTSTAT0xD2C
146Memory Management Fault Address-R/WMMADDR0xD34
147Bus Fault Address-R/WFAULTADDR0xD38
Memory Protection Unit (MPU) Registers
148MPU Type0x0000.0800ROMPUTYPE0xD90
149MPU Control0x0000.0000R/WMPUCTRL0xD94
151MPU Region Number0x0000.0000R/WMPUNUMBER0xD98
152MPU Region Base Address0x0000.0000R/WMPUBASE0xD9C
154MPU Region Attribute and Size0x0000.0000R/WMPUATTR0xDA0
152MPU Region Base Address Alias 10x0000.0000R/WMPUBASE10xDA4
154MPU Region Attribute and Size Alias 10x0000.0000R/WMPUATTR10xDA8
152MPU Region Base Address Alias 20x0000.0000R/WMPUBASE20xDAC
154MPU Region Attribute and Size Alias 20x0000.0000R/WMPUATTR20xDB0
June 18, 2012102
Texas Instruments-Production Data
Cortex-M3 Peripherals
Table 3-7. Peripherals Register Map (continued)
See
page
DescriptionResetTypeNameOffset
152MPU Region Base Address Alias 30x0000.0000R/WMPUBASE30xDB4
154MPU Region Attribute and Size Alias 30x0000.0000R/WMPUATTR30xDB8
3.3 System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
103June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
COUNTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ENABLEINTENCLK_SRCreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:17
Count Flag
DescriptionValue
The SysTick timer has not counted to 0 since the last time
this bit was read.
0
The SysTick timer has counted to 0 since the last time
this bit was read.
1
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.
0ROCOUNT16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved15:3
Clock Source
DescriptionValue
External reference clock. (Not implemented for most Stellaris
microcontrollers.)
0
System clock1
Because an external reference clock is not implemented, this bit must
be set in order for SysTick to operate.
0R/WCLK_SRC2
June 18, 2012104
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Interrupt Enable
DescriptionValue
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
0
An interrupt is generated to the NVIC when SysTick counts
to 0.
1
0R/WINTEN1
Enable
DescriptionValue
The counter is disabled.0
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
1
0R/WENABLE0
105June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
Note: This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
RELOADreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RELOAD
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:24
Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
0x00.0000R/WRELOAD23:0
June 18, 2012106
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
16171819202122232425262728293031
CURRENTreserved
R/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CURRENT
R/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:24
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
0x00.0000R/WCCURRENT23:0
3.4 NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 125.
107June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Note: This register can only be accessed from privileged mode.
The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 81 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Enable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
0x0000.0000R/WINT31:0
June 18, 2012108
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104
Note: This register can only be accessed from privileged mode.
The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 32-43 Set Enable (EN1)
Base 0xE000.E000
Offset 0x104
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Interrupt Enable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS1 register.
0x000R/WINT11:0
109June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Note: This register can only be accessed from privileged mode.
The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt
31.
See Table 2-9 on page 81 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Disable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
1
0x0000.0000R/WINT31:0
June 18, 2012110
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184
Note: This register can only be accessed from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt
43. See Table 2-9 on page 81 for interrupt assignments.
Interrupt 32-43 Clear Enable (DIS1)
Base 0xE000.E000
Offset 0x184
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Interrupt Disable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN1
register, disabling interrupt [n].
1
0x000R/WINT11:0
111June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Note: This register can only be accessed from privileged mode.
The PEND0 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 81 for interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Set Pending
DescriptionValue
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
1
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
0x0000.0000R/WINT31:0
June 18, 2012112
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204
Note: This register can only be accessed from privileged mode.
The PEND1 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for
interrupt assignments.
Interrupt 32-43 Set Pending (PEND1)
Base 0xE000.E000
Offset 0x204
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Interrupt Set Pending
DescriptionValue
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
1
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND1 register.
0x000R/WINT11:0
113June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Note: This register can only be accessed from privileged mode.
The UNPEND0 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 81 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Clear Pending
DescriptionValue
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
0x0000.0000R/WINT31:0
June 18, 2012114
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284
Note: This register can only be accessed from privileged mode.
The UNPEND1 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table
2-9 on page 81 for interrupt assignments.
Interrupt 32-43 Clear Pending (UNPEND1)
Base 0xE000.E000
Offset 0x284
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Interrupt Clear Pending
DescriptionValue
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND1
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
0x000R/WINT11:0
115June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
Note: This register can only be accessed from privileged mode.
The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31
corresponds to Interrupt 31.
See Table 2-9 on page 81 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 0-31 Active Bit (ACTIVE0)
Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
16171819202122232425262728293031
INT
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INT
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Active
DescriptionValue
The corresponding interrupt is not active.0
The corresponding interrupt is active, or active and pending.1
0x0000.0000ROINT31:0
June 18, 2012116
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304
Note: This register can only be accessed from privileged mode.
The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit
11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 32-43 Active Bit (ACTIVE1)
Base 0xE000.E000
Offset 0x304
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Interrupt Active
DescriptionValue
The corresponding interrupt is not active.0
The corresponding interrupt is active, or active and pending.1
0x000ROINT11:0
117June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420
Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428
Note: This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible.
Each register holds four priority fields that are assigned to interrupts as follows:
InterruptPRIn Register Bit Field
Interrupt [4n+3]Bits 31:29
Interrupt [4n+2]Bits 23:21
Interrupt [4n+1]Bits 15:13
Interrupt [4n]Bits 7:5
See Table 2-9 on page 81 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 126) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reservedINTCreservedINTD
ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
reservedINTAreservedINTB
ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType
0000000000000000Reset
June 18, 2012118
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
0x0R/WINTD31:29
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved28:24
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
0x0R/WINTC23:21
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved20:16
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
0x0R/WINTB15:13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved12:8
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
0x0R/WINTA7:5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved4:0
119June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00
Note: Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 81 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 130) is
set, unprivileged software can access the SWTRIG register.
Software Trigger Interrupt (SWTRIG)
Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTIDreserved
WOWOWOWOWOWOROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:6
Interrupt ID
This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.
0x00WOINTID5:0
3.5 System Control Block (SCB) Register Descriptions
This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
June 18, 2012120
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 26: CPU ID Base (CPUID), offset 0xD00
Note: This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and
implementation information.
CPU ID Base (CPUID)
Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x411F.C231
16171819202122232425262728293031
CONVARIMP
ROROROROROROROROROROROROROROROROType
1111100010000010Reset
0123456789101112131415
REVPARTNO
ROROROROROROROROROROROROROROROROType
1000110001000011Reset
DescriptionResetTypeNameBit/Field
Implementer Code
DescriptionValue
ARM0x41
0x41ROIMP31:24
Variant Number
DescriptionValue
The rn value in the rnpn product revision identifier, for example,
the 1 in r1p1.
0x1
0x1ROVAR23:20
Constant
DescriptionValue
Always reads as 0xF.0xF
0xFROCON19:16
Part Number
DescriptionValue
Cortex-M3 processor.0xC23
0xC23ROPARTNO15:4
Revision Number
DescriptionValue
The pn value in the rnpn product revision identifier, for example,
the 1 in r1p1.
0x1
0x1ROREV3:0
121June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04
Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
VECPENDreservedISRPENDISRPRE
reservedPENDSTCLRPENDSTSETUNPENDSV
PENDSVreservedNMISET
ROROROROROROROROROWOR/WWOR/WROROR/WType
0000000000000000Reset
0123456789101112131415
VECACTreservedRETBASEVECPEND
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
NMI Set Pending
DescriptionValue
On a read, indicates an NMI exception is not pending.
On a write, no effect.
0
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
1
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
0R/WNMISET31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved30:29
PendSV Set Pending
DescriptionValue
On a read, indicates a PendSV exception is not pending.
On a write, no effect.
0
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
1
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
0R/WPENDSV28
June 18, 2012122
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
PendSV Clear Pending
DescriptionValue
On a write, no effect.0
On a write, removes the pending state from the PendSV
exception.
1
This bit is write only; on a register read, its value is unknown.
0WOUNPENDSV27
SysTick Set Pending
DescriptionValue
On a read, indicates a SysTick exception is not pending.
On a write, no effect.
0
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
1
This bit is cleared by writing a 1 to the PENDSTCLR bit.
0R/WPENDSTSET26
SysTick Clear Pending
DescriptionValue
On a write, no effect.0
On a write, removes the pending state from the SysTick
exception.
1
This bit is write only; on a register read, its value is unknown.
0WOPENDSTCLR25
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved24
Debug Interrupt Handling
DescriptionValue
The release from halt does not take an interrupt.0
The release from halt takes an interrupt.1
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
0ROISRPRE23
Interrupt Pending
DescriptionValue
No interrupt is pending.0
An interrupt is pending.1
This bit provides status for all interrupts excluding NMI and Faults.
0ROISRPEND22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved21:18
123June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
DescriptionValue
No exceptions are pending0x00
Reserved0x01
NMI0x02
Hard fault0x03
Memory management fault0x04
Bus fault0x05
Usage fault0x06
Reserved0x07-0x0A
SVCall0x0B
Reserved for Debug0x0C
Reserved0x0D
PendSV0x0E
SysTick0x0F
Interrupt Vector 00x10
Interrupt Vector 10x11
......
Interrupt Vector 430x3B
Reserved0x3C-0x3F
0x00ROVECPEND17:12
Return to Base
DescriptionValue
There are preempted active exceptions to execute.0
There are no active exceptions, or the currently executing
exception is the only active exception.
1
This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).
0RORETBASE11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved10:6
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn),Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn),Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 62).
0x00ROVECACT5:0
June 18, 2012124
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 28: Vector Table Offset (VTABLE), offset 0xD08
Note: This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
OFFSETBASEreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROType
0000000000000000Reset
0123456789101112131415
reservedOFFSET
ROROROROROROROROR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:30
Vector Table Base
DescriptionValue
The vector table is in the code memory region.0
The vector table is in the SRAM memory region.1
0R/WBASE29
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 43
interrupts, the offset must be aligned on a 256-byte boundary.
0x000.00R/WOFFSET28:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:0
125June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note: This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-8 on page 126 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.
Table 3-8. Interrupt Priority Levels
SubprioritiesGroup
Priorities
Subpriority FieldGroup Priority FieldBinary Pointa
PRIGROUP Bit Field
18None[7:5]bxxx.0x0 - 0x4
24[5][7:6]bxx.y0x5
42[6:5][7]bx.yy0x6
81[7:5]Noneb.yyy0x7
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
16171819202122232425262728293031
VECTKEY
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1010000001011111Reset
0123456789101112131415
VECTRESET
VECTCLRACT
SYSRESREQ
reservedPRIGROUPreserved
ENDIANESS
WOWOWOROROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
0xFA05R/WVECTKEY31:16
Data Endianess
The Stellaris implementation uses only little-endian mode so this is
cleared to 0.
0ROENDIANESS15
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved14:11
June 18, 2012126
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-8 on page 126 for more information).
0x0R/WPRIGROUP10:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:3
System Reset Request
DescriptionValue
No effect.0
Resets the core and all on-chip peripherals except the Debug
interface.
1
This bit is automatically cleared during the reset of the core and reads
as 0.
0WOSYSRESREQ2
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0WOVECTCLRACT1
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0WOVECTRESET0
127June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 30: System Control (SYSCTRL), offset 0xD10
Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedSLEEPEXITSLEEPDEEPreservedSEVONPEND
reserved
ROR/WR/WROR/WROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:5
Wake Up on Pending
DescriptionValue
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
0
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
1
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
0R/WSEVONPEND4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Deep Sleep Enable
DescriptionValue
Use Sleep mode as the low power mode.0
Use Deep-sleep mode as the low power mode.1
0R/WSLEEPDEEP2
June 18, 2012128
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Sleep on ISR Exit
DescriptionValue
When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
0
When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.
1
Setting this bit enables an interrupt-driven application to avoid returning
to an empty main application.
0R/WSLEEPEXIT1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
129June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 31: Configuration and Control (CFGCTRL), offset 0xD14
Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 120).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BASETHR
MAINPENDreservedUNALIGNED
DIV0reserved
BFHFNMIGNSTKALIGN
reserved
R/WR/WROR/WR/WROROROR/WR/WROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:10
Stack Alignment on Exception Entry
DescriptionValue
The stack is 4-byte aligned.0
The stack is 8-byte aligned.1
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
0R/WSTKALIGN9
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
DescriptionValue
Data bus faults caused by load and store instructions cause a
lock-up.
0
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
1
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
0R/WBFHFNMIGN8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:5
June 18, 2012130
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
DescriptionValue
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
0
Trap on divide by 0.1
0R/WDIV04
Trap on Unaligned Access
DescriptionValue
Do not trap on unaligned halfword and word accesses.0
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
1
Unaligned LDM,STM,LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
0R/WUNALIGNED3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
Allow Main Interrupt Trigger
DescriptionValue
Disables unprivileged software access to the SWTRIG register.0
Enables unprivileged software access to the SWTRIG register
(see page 120).
1
0R/WMAINPEND1
Thread State Control
DescriptionValue
The processor can enter Thread mode only when no exception
is active.
0
The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 86 for more information).
1
0R/WBASETHR0
131June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18
Note: This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reservedUSAGEreserved
ROROROROROR/WR/WR/WROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedMEMreservedBUS
ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:24
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
0x0R/WUSAGE23:21
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved20:16
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
0x0R/WBUS15:13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved12:8
Memory Management Fault Priority
This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
0x0R/WMEM7:5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved4:0
June 18, 2012132
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C
Note: This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.
System Handler Priority 2 (SYSPRI2)
Base 0xE000.E000
Offset 0xD1C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reservedSVC
ROROROROROROROROROROROROROR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
0x0R/WSVC31:29
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.0000ROreserved28:0
133June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20
Note: This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.
System Handler Priority 3 (SYSPRI3)
Base 0xE000.E000
Offset 0xD20
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reservedPENDSVreservedTICK
ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
reservedDEBUGreserved
ROROROROROR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
0x0R/WTICK31:29
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved28:24
PendSV Priority
This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.
0x0R/WPENDSV23:21
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved20:8
Debug Priority
This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
0x0R/WDEBUG7:5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0.0000ROreserved4:0
June 18, 2012134
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note: This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modied after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modied.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
MEMBUSUSAGEreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MEMABUSA
reserved
USGAreservedSVCAMON
reserved
PNDSVTICKUSAGEPMEMPBUSPSVC
R/WR/WROR/WROROROR/WR/WROR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:19
Usage Fault Enable
DescriptionValue
Disables the usage fault exception.0
Enables the usage fault exception.1
0R/WUSAGE18
Bus Fault Enable
DescriptionValue
Disables the bus fault exception.0
Enables the bus fault exception.1
0R/WBUS17
135June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Memory Management Fault Enable
DescriptionValue
Disables the memory management fault exception.0
Enables the memory management fault exception.1
0R/WMEM16
SVC Call Pending
DescriptionValue
An SVC call exception is not pending.0
An SVC call exception is pending.1
This bit can be modified to change the pending status of the SVC call
exception.
0R/WSVC15
Bus Fault Pending
DescriptionValue
A bus fault exception is not pending.0
A bus fault exception is pending.1
This bit can be modified to change the pending status of the bus fault
exception.
0R/WBUSP14
Memory Management Fault Pending
DescriptionValue
A memory management fault exception is not pending.0
A memory management fault exception is pending.1
This bit can be modified to change the pending status of the memory
management fault exception.
0R/WMEMP13
Usage Fault Pending
DescriptionValue
A usage fault exception is not pending.0
A usage fault exception is pending.1
This bit can be modified to change the pending status of the usage fault
exception.
0R/WUSAGEP12
SysTick Exception Active
DescriptionValue
A SysTick exception is not active.0
A SysTick exception is active.1
This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.
0R/WTICK11
June 18, 2012136
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
PendSV Exception Active
DescriptionValue
A PendSV exception is not active.0
A PendSV exception is active.1
This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.
0R/WPNDSV10
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved9
Debug Monitor Active
DescriptionValue
The Debug monitor is not active.0
The Debug monitor is active.1
0R/WMON8
SVC Call Active
DescriptionValue
SVC call is not active.0
SVC call is active.1
This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.
0R/WSVCA7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved6:4
Usage Fault Active
DescriptionValue
Usage fault is not active.0
Usage fault is active.1
This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.
0R/WUSGA3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
Bus Fault Active
DescriptionValue
Bus fault is not active.0
Bus fault is active.1
This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.
0R/WBUSA1
137June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Memory Management Fault Active
DescriptionValue
Memory management fault is not active.0
Memory management fault is active.1
This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.
0R/WMEMA0
June 18, 2012138
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28
Note: This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
■Usage Fault Status (UFAULTSTAT), bits 31:16
■Bus Fault Status (BFAULTSTAT), bits 15:8
■Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
■ The complete FAULTSTAT register, with a word access to offset 0xD28
■ The MFAULTSTAT, with a byte access to offset 0xD28
■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
■ The BFAULTSTAT, with a byte access to offset 0xD29
■ The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
UNDEFINVSTATINVPCNOCPreservedUNALIGNDIV0reserved
R/W1CR/W1CR/W1CR/W1CROROROROR/W1CR/W1CROROROROROROType
0000000000000000Reset
0123456789101112131415
IERRDERR
reserved
MUSTKEMSTKEreservedMMARVIBUSPRECISEIMPREBUSTKEBSTKEreservedBFARV
R/W1CR/W1CROR/W1CR/W1CROROR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CROROR/W1CType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:26
139June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Divide-by-Zero Usage Fault
DescriptionValue
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
0
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 130).
This bit is cleared by writing a 1 to it.
0R/W1CDIV025
Unaligned Access Usage Fault
DescriptionValue
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
0
The processor has made an unaligned memory access.1
Unaligned LDM,STM,LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 130).
This bit is cleared by writing a 1 to it.
0R/W1CUNALIGN24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved23:20
No Coprocessor Usage Fault
DescriptionValue
A usage fault has not been caused by attempting to access a
coprocessor.
0
The processor has attempted to access a coprocessor.1
This bit is cleared by writing a 1 to it.
0R/W1CNOCP19
Invalid PC Load Usage Fault
DescriptionValue
A usage fault has not been caused by attempting to load an
invalid PC value.
0
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
0R/W1CINVPC18
June 18, 2012140
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Invalid State Usage Fault
DescriptionValue
A usage fault has not been caused by an invalid state.0
The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
0R/W1CINVSTAT17
Undefined Instruction Usage Fault
DescriptionValue
A usage fault has not been caused by an undefined instruction.0
The processor has attempted to execute an undefined
instruction.
1
When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.
0R/W1CUNDEF16
Bus Fault Address Register Valid
DescriptionValue
The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
0
The FAULTADDR register is holding a valid fault address.1
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.
0R/W1CBFARV15
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved14:13
141June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Stack Bus Fault
DescriptionValue
No bus fault has occurred on stacking for exception entry.0
Stacking for an exception entry has caused one or more bus
faults.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CBSTKE12
Unstack Bus Fault
DescriptionValue
No bus fault has occurred on unstacking for a return from
exception.
0
Unstacking for a return from exception has caused one or more
bus faults.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CBUSTKE11
Imprecise Data Bus Error
DescriptionValue
An imprecise data bus error has not occurred.0
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
1
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.
0R/W1CIMPRE10
Precise Data Bus Error
DescriptionValue
A precise data bus error has not occurred.0
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
1
When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
0R/W1CPRECISE9
June 18, 2012142
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Instruction Bus Error
DescriptionValue
An instruction bus error has not occurred.0
An instruction bus error has occurred.1
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
0R/W1CIBUS8
Memory Management Fault Address Register Valid
DescriptionValue
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
0
The MMADDR register is holding a valid fault address.1
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
0R/W1CMMARV7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved6:5
Stack Access Violation
DescriptionValue
No memory management fault has occurred on stacking for
exception entry.
0
Stacking for an exception entry has caused one or more access
violations.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CMSTKE4
143June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Unstack Access Violation
DescriptionValue
No memory management fault has occurred on unstacking for
a return from exception.
0
Unstacking for a return from exception has caused one or more
access violations.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CMUSTKE3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
Data Access Violation
DescriptionValue
A data access violation has not occurred.0
The processor attempted a load or store at a location that does
not permit the operation.
1
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CDERR1
Instruction Access Violation
DescriptionValue
An instruction access violation has not occurred.0
The processor attempted an instruction fetch from a location
that does not permit execution.
1
This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CIERR0
June 18, 2012144
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note: This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reservedFORCEDDBG
ROROROROROROROROROROROROROROR/W1CR/W1CType
0000000000000000Reset
0123456789101112131415
reserved
VECTreserved
ROR/W1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
0R/W1CDBG31
Forced Hard Fault
DescriptionValue
No forced hard fault has occurred.0
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
1
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
0R/W1CFORCED30
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved29:2
Vector Table Read Fault
DescriptionValue
No bus fault has occurred on a vector table read.0
A bus fault occurred on a vector table read.1
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
0R/W1CVECT1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
145June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34
Note: This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 139).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type R/W, reset -
16171819202122232425262728293031
ADDR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
ADDR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
-R/WADDR31:0
June 18, 2012146
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38
Note: This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 139).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type R/W, reset -
16171819202122232425262728293031
ADDR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
ADDR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
-R/WADDR31:0
3.6 Memory Protection Unit (MPU) Register Descriptions
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.
147June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 40: MPU Type (MPUTYPE), offset 0xD90
Note: This register can only be accessed from privileged mode.
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.
MPU Type (MPUTYPE)
Base 0xE000.E000
Offset 0xD90
Type RO, reset 0x0000.0800
16171819202122232425262728293031
IREGIONreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SEPARATE
reservedDREGION
ROROROROROROROROROROROROROROROROType
0000000000010000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:24
Number of I Regions
This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.
0x00ROIREGION23:16
Number of D Regions
DescriptionValue
Indicates there are eight supported MPU data regions.0x08
0x08RODREGION15:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:1
Separate or Unified MPU
DescriptionValue
Indicates the MPU is unified.0
0ROSEPARATE0
June 18, 2012148
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 41: MPU Control (MPUCTRL), offset 0xD94
Note: This register can only be accessed from privileged mode.
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:
■For privileged accesses, the default memory map is as described in “Memory Model” on page 70.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.
■ Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.
Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPU is not implemented (see Table 2-5 on page 72 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.
MPU Control (MPUCTRL)
Base 0xE000.E000
Offset 0xD94
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ENABLE
HFNMIENAPRIVDEFEN
reserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
149June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
MPU Default Region
This bit enables privileged software access to the default memory map.
DescriptionValue
If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
0
If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.
1
When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.
0R/WPRIVDEFEN2
MPU Enabled During Faults
This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
DescriptionValue
The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
0
The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
1
When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.
0R/WHFNMIENA1
MPU Enable
DescriptionValue
The MPU is disabled.0
The MPU is enabled.1
When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.
0R/WENABLE0
June 18, 2012150
Texas Instruments-Production Data
Cortex-M3 Peripherals
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98
Note: This register can only be accessed from privileged mode.
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 152). This write updates the value of the REGION field.
MPU Region Number (MPUNUMBER)
Base 0xE000.E000
Offset 0xD98
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
NUMBERreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
MPU Region to Access
This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.
0x0R/WNUMBER2:0
151June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
Note: This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:Nof the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of Nwhere:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.
MPU Region Base Address (MPUBASE)
Base 0xE000.E000
Offset 0xD9C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
ADDR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
REGION
reserved
VALIDADDR
R/WR/WR/WROWOR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Base Address Mask
Bits 31:Nin this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000R/WADDR31:5
June 18, 2012152
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Region Number Valid
DescriptionValue
The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
0
The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.
1
This bit is always read as 0.
0WOVALID4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Region Number
On a write, contains the value to be written to the MPUNUMBER register.
On a read, returns the current region number in the MPUNUMBER
register.
0x0R/WREGION2:0
153June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note: This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN,AP,TEX,S,C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-9 on page 154 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.
Table 3-9. Example SIZE Field Values
NoteValue of Na
Region SizeSIZE Encoding
Minimum permitted size532 B00100b (0x4)
-101 KB01001b (0x9)
-201 MB10011b (0x13)
-301 GB11101b (0x1D)
Maximum possible sizeNo valid ADDR field in MPUBASE; the
region occupies the complete
memory map.
4 GB11111b (0x1F)
a. Refers to the N parameter in the MPUBASE register (see page 152).
MPU Region Attribute and Size (MPUATTR)
Base 0xE000.E000
Offset 0xDA0
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
BCSTEXreservedAP
reserved
XNreserved
R/WR/WR/WR/WR/WR/WROROR/WR/WR/WROR/WROROROType
0000000000000000Reset
0123456789101112131415
ENABLESIZEreservedSRD
R/WR/WR/WR/WR/WR/WROROR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
June 18, 2012154
Texas Instruments-Production Data
Cortex-M3 Peripherals
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:29
Instruction Access Disable
DescriptionValue
Instruction fetches are enabled.0
Instruction fetches are disabled.1
0R/WXN28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27
Access Privilege
For information on using this bit field, see Table 3-5 on page 100.
0R/WAP26:24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved23:22
Type Extension Mask
For information on using this bit field, see Table 3-3 on page 99.
0x0R/WTEX21:19
Shareable
For information on using this bit, see Table 3-3 on page 99.
0R/WS18
Cacheable
For information on using this bit, see Table 3-3 on page 99.
0R/WC17
Bufferable
For information on using this bit, see Table 3-3 on page 99.
0R/WB16
Subregion Disable Bits
DescriptionValue
The corresponding subregion is enabled.0
The corresponding subregion is disabled.1
Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 98 for more information.
0x00R/WSRD15:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:6
Region Size Mask
The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-9 on page 154 for more
information.
0x0R/WSIZE5:1
155June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Region Enable
DescriptionValue
The region is disabled.0
The region is enabled.1
0R/WENABLE0
June 18, 2012156
Texas Instruments-Production Data
Cortex-M3 Peripherals
4 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST,TCK,TMS,TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Stellaris®JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
The Stellaris JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.
157June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
4.1 Block Diagram
Figure 4-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
TRST
4.2 Signal Description
Table 4-1 on page 158 and Table 4-2 on page 159 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The JTAG/SWD controller signals are under commit protection and require a special process to be
configured as GPIOs, see “Commit Control” on page 292. The column in the table below titled "Pin
Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in
the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) is set to choose the
JTAG/SWD function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 284.
Table 4-1. JTAG_SWD_SWO Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
JTAG/SWD CLK.TTLI80SWCLK
JTAG TMS and SWDIO.TTLI/O79SWDIO
JTAG TDO and SWO.TTLO77SWO
JTAG/SWD CLK.TTLI80TCK
JTAG TDI.TTLI78TDI
JTAG TDO and SWO.TTLO77TDO
JTAG TMS and SWDIO.TTLI/O79TMS
JTAG TRST.TTLI89TRST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 18, 2012158
Texas Instruments-Production Data
JTAG Interface
Table 4-2. JTAG_SWD_SWO Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
JTAG/SWD CLK.TTLIA9SWCLK
JTAG TMS and SWDIO.TTLI/OB9SWDIO
JTAG TDO and SWO.TTLOA10SWO
JTAG/SWD CLK.TTLIA9TCK
JTAG TDI.TTLIB8TDI
JTAG TDO and SWO.TTLOA10TDO
JTAG TMS and SWDIO.TTLI/OB9TMS
JTAG TRST.TTLIA8TRST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
4.3 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 158. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST,TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-4 on page 166 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 666 for JTAG timing diagrams.
4.3.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK,TMS,TDI, and TDO. These pins and
their associated reset state are given in Table 4-3 on page 159. Detailed information on each pin
follows.
Table 4-3. JTAG Port Pins Reset State
Drive ValueDrive StrengthInternal Pull-DownInternal Pull-UpData DirectionPin Name
N/AN/ADisabledEnabledInputTRST
N/AN/ADisabledEnabledInputTCK
N/AN/ADisabledEnabledInputTMS
N/AN/ADisabledEnabledInputTDI
High-Z2-mA driverDisabledEnabledOutputTDO
159June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
4.3.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
4.3.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
4.3.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 4-2 on page 162.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
4.3.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
June 18, 2012160
Texas Instruments-Production Data
JTAG Interface
4.3.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
4.3.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 4-2 on page 162. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
161June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 4-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 11
1 1
1
1 1
1 1
1 1
1 1
1 10 0
00
00
0 0
0 0
0 0
00
0
0
4.3.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 165.
4.3.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
June 18, 2012162
Texas Instruments-Production Data
JTAG Interface
4.3.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris microcontroller. If the program code loaded into ash immediately changes the JTAG pins
to their GPIO functionality, the debugger may not have enough time to connect and halt the controller
before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be
avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 306) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 316) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 317) have been set to 1.
Recovering a "Locked" Device
Note: The mass erase of the flash memory caused by the below sequence erases the entire flash
memory, regardless of the settings in the Flash Memory Protection Program Enable n
(FMPPEn) registers. Performing the sequence below does not affect the nonvolatile registers
discussed in “Nonvolatile Register Programming” on page 261.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Apply power to the device.
3. Perform the JTAG-to-SWD switch sequence.
4. Perform the SWD-to-JTAG switch sequence.
5. Perform the JTAG-to-SWD switch sequence.
6. Perform the SWD-to-JTAG switch sequence.
7. Perform the JTAG-to-SWD switch sequence.
8. Perform the SWD-to-JTAG switch sequence.
9. Perform the JTAG-to-SWD switch sequence.
10. Perform the SWD-to-JTAG switch sequence.
163June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
11. Perform the JTAG-to-SWD switch sequence.
12. Perform the SWD-to-JTAG switch sequence.
13. Release the RST signal.
14. Wait 400 ms.
15. Power-cycle the device.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 164. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence in the section called
“JTAG-to-SWD Switching” on page 164 must be performed.
4.3.4.2 Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
4.3.4.3 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Debug Interface V5 Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
June 18, 2012164
Texas Instruments-Production Data
JTAG Interface
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
4.4 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to
enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG
pins (PB7 andPC[3:0]) should be reverted to their default settings.
4.5 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
4.5.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 4-4 on page 166. A detailed explanation of each instruction, along
with its associated Data Register, follows.
165June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 4-4. JTAG Instruction Register Commands
DescriptionInstructionIR[3:0]
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
EXTEST0000
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
INTEST0001
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
SAMPLE / PRELOAD0010
Shifts data into the ARM Debug Port Abort Register.ABORT1000
Shifts data into and out of the ARM DP Access Register.DPACC1010
Shifts data into and out of the ARM AC Access Register.APACC1011
Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
IDCODE1110
Connects TDI to TDO through a single Shift Register chain.BYPASS1111
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
ReservedAll Others
4.5.1.1 EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan
Data Register can be accessed to sample and shift out the current data and load new data into the
Boundary Scan Data Register.
4.5.1.2 INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary
Scan Data Register can be accessed to sample and shift out the current data and load new data
into the Boundary Scan Data Register.
4.5.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
June 18, 2012166
Texas Instruments-Production Data
JTAG Interface
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 168 for more information.
4.5.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 169 for more
information.
4.5.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 169 for more information.
4.5.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 169 for more information.
4.5.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 168 for more
information.
4.5.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 168 for
more information.
167June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
4.5.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
4.5.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3 on page 168. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure
themselves to work correctly with the Cortex-M3 during debug.
Figure 4-3. IDCODE Register Format
Version Part Number Manufacturer ID 1
31 28 27 12 11 1 0
TDOTDI
4.5.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4 on page 168. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
Figure 4-4. BYPASS Register Format
0TDOTDI
0
4.5.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 169. Each GPIO
pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
June 18, 2012168
Texas Instruments-Production Data
JTAG Interface
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 4-5. Boundary Scan Register Format
OTDOTDI O
I
N E
U
T
O
O
I
N E
U
T
O
O
I
N E
U
T
O
O
I
N E
U
T
I
N
... ...
RSTGPIO PB6 GPIO m GPIO m+1 G PIO n
4.5.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
169June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
5 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
5.1 Signal Description
Table 5-1 on page 170 and Table 5-2 on page 170 list the external signals of the System Control
module and describe the function of each. The NMI signal is the alternate function for and functions
as a GPIO after reset. under commit protection and require a special process to be configured as
any alternate function or to subsequently return to the GPIO function, see “Commit
Control” on page 292. The column in the table below titled "Pin Assignment" lists the GPIO pin
placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 306) should be set to choose the NMI function. For more information on configuring
GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284. The remaining signals (with the
word "fixed" in the Pin Assignment column) have a fixed pin assignment and function.
Table 5-1. System Control & Clocks Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLI65CMOD0
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLI76CMOD1
Main oscillator crystal input or an external clock reference
input.
AnalogI48OSC0
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
AnalogO49OSC1
System reset input.TTLI64RST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 5-2. System Control & Clocks Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLIE11CMOD0
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLIB10CMOD1
Main oscillator crystal input or an external clock reference
input.
AnalogIL11OSC0
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
AnalogOM11OSC1
System reset input.TTLIH11RST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
5.2 Functional Description
The System Control module provides the following capabilities:
■ Device identification (see “Device Identification” on page 171)
June 18, 2012170
Texas Instruments-Production Data
System Control
■ Local control, such as reset (see “Reset Control” on page 171), power (see “Power
Control” on page 175) and clock control (see “Clock Control” on page 176)
■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 181
5.2.1 Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0,DID1, and DC0-DC4 registers.
5.2.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.2.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
5.2.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion; see “External RST Pin” on page 172.
2. Power-on reset (POR); see “Power-On Reset (POR)” on page 172.
3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 173.
4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 174.
5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 174.
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
On-Chip Peripherals Reset?JTAG Reset?Core Reset?Reset Source
YesYesYesPower-On Reset
YesPin Config OnlyYesRST
YesNoYesBrown-Out Reset
YesNoYesSoftware System Request
Reseta
Yesb
NoNoSoftware Peripheral Reset
YesNoYesWatchdog Reset
a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
171June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
5.2.2.3 Power-On Reset (POR)
Note: The power-on reset also resets the JTAG controller. An external reset does not.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 172.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 21-6 on page 669.
5.2.2.4 External RST Pin
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 172.
Figure 5-1. Basic RST Configuration
PU
RST
Stellaris®
R
VDD
RPU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 157). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 668).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
June 18, 2012172
Texas Instruments-Production Data
System Control
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 173.
Figure 5-2. External Circuitry to Extend Power-On Reset
PU
C1
RST
Stellaris®
R
VDD
RPU = 1 kΩ to 100 kΩ
C1= 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 5-3 on page 173 shows the
proper circuitry to use.
Figure 5-3. Reset Circuit Controlled by Switch
PU
C1
RS
RST
Stellaris®
R
VDD
Typical RPU = 10 kΩ
Typical RS= 470 Ω
C1= 10 nF
The RPU and C1components define the power-on delay.
The external reset timing is shown in Figure 21-5 on page 668.
5.2.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
173June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
The brown-out reset is equivalent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 21-7 on page 669.
5.2.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 181). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 21-8 on page 669.
5.2.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The watchdog reset timing is shown in Figure 21-9 on page 669.
June 18, 2012174
Texas Instruments-Production Data
System Control
5.2.3 Power Control
The Stellaris®microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the controller's internal logic. For power reduction, the LDO regulator provides
software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range
of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of
the VADJ field in the LDO Power Control (LDOPCTL) register.
Figure 5-4 on page 176 shows the power architecture.
Note: On the printed circuit board, use the LDO output as the source of VDD25 input. Do not use
an external regulator to supply the voltage to VDD25. In addition, the LDO requires decoupling
capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 662.
VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA
is the supply for all of the analog circuitry on the device, including the LDO and the clock
circuitry.
175June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 5-4. Power Architecture
I/O Buffers
Analog circuits
Low-noise
LDO
Internal
Logic and PLL
GND
GND
GND
GND
GNDA
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDDA
VDDA
VDD25
VDD25
VDD25
VDD25
LDO
+3.3V
Ethernet
PHY
GNDPHY
GNDPHY
GNDPHY
GNDPHY
VCCPHY
VCCPHY
VCCPHY
VCCPHY
GNDA
VDD
5.2.4 Clock Control
System control determines the control of clocks in this part.
5.2.4.1 Fundamental Clock Sources
There are multiple clock sources for use in the device:
■Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
June 18, 2012176
Texas Instruments-Production Data
System Control
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 193).
■Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■External Real-Time Oscillator. The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (see “Hibernation Module” on page 237) and
may also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 5-4 on page 177 shows how the various clock sources can be used in a system.
Table 5-4. Clock Source Options
Used as SysClk?Drive PLL?Clock Source
BYPASS = 1, OSCSRC = 0x1YesBYPASS = 1NoInternal Oscillator (12 MHz)
BYPASS = 1, OSCSRC = 0x2YesBYPASS = 1NoInternal Oscillator divide by 4 (3
MHz)
BYPASS = 1, OSCSRC = 0x0YesBYPASS = 0, OSCSRC =
0x0
YesMain Oscillator
BYPASS = 1, OSCSRC = 0x3YesBYPASS = 1NoInternal 30-kHz Oscillator
BYPASS = 1, OSCSRC2 = 0x7YesBYPASS = 1NoExternal Real-Time Oscillator
5.2.4.2 Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
177June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
■ Clock divisors
■ Crystal input selection
Figure 5-5 on page 178 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled. The PWM clock signal is a
synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV
in RCC).
Figure 5-5. Main Clock Tree
PLL
(400 MHz)
Main OSC
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
÷ 4
Hibernation
Module
(32.768 kHz) ÷ 25
PWRDN
ADC Clock
System Clock
XTALa
PWRDN b
MOSCDIS a
IOSCDISa
OSCSRCb,d
BYPASS b,d
SYSDIVb,d
USESYSDIVa,d
PWMDW a
USEPWMDIV a
PWM Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
÷ 2
÷ 50 CAN Clock
Note: The figure above shows all features available on all Stellaris® Fury-class devices. Not all peripherals may be
available on this device.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
June 18, 2012178
Texas Instruments-Production Data
System Control
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 177.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
StellarisWare Parametera
Frequency (BYPASS=1)Frequency
(BYPASS=0)
DivisorSYSDIV
SYSCTL_SYSDIV_1b
Clock source frequency/2reserved/10x0
SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x1
SYSCTL_SYSDIV_3Clock source frequency/3reserved/30x2
SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x3
SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x4
SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x5
SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x6
SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x7
SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x8
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x9
SYSCTL_SYSDIV_11Clock source frequency/1118.18 MHz/110xA
SYSCTL_SYSDIV_12Clock source frequency/1216.67 MHz/120xB
SYSCTL_SYSDIV_13Clock source frequency/1315.38 MHz/130xC
SYSCTL_SYSDIV_14Clock source frequency/1414.29 MHz/140xD
SYSCTL_SYSDIV_15Clock source frequency/1513.33 MHz/150xE
SYSCTL_SYSDIV_16Clock source frequency/1612.5 MHz (default)/160xF
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-4 on page 177.
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
StellarisWare Parametera
Frequency (BYPASS2=1)Frequency
(BYPASS2=0)
DivisorSYSDIV2
SYSCTL_SYSDIV_1b
Clock source frequency/2reserved/10x00
SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x01
SYSCTL_SYSDIV_3Clock source frequency/3reserved/30x02
SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x03
SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x04
SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x05
SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x06
179June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
StellarisWare Parametera
Frequency (BYPASS2=1)Frequency
(BYPASS2=0)
DivisorSYSDIV2
SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x07
SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x08
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x09
...............
SYSCTL_SYSDIV_64Clock source frequency/643.125 MHz/640x3F
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
5.2.4.3 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 193) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
5.2.4.4 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 197). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 21-10 on page 665 shows the actual PLL frequency and error
for a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 193)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2
field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7.
5.2.4.5 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 193 and page 198).
June 18, 2012180
Texas Instruments-Production Data
System Control
5.2.4.6 PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
21-9 on page 665). During the relock time, the affected PLL is not usable as a clock reference.
PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
the PLL from being used as a system clock until the TREADY condition is met after one of the two
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
5.2.5 System Control
For power-savings purposes, the RCGCn ,SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
There are four levels of operation for the device defined as:
■Run Mode. In Run mode, the controller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt)
instruction. Any properly configured interrupt event in the system will bring the processor back
into Run mode. See “Power Management” on page 88 for more details.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep
modes are entered on request from the code. Deep-Sleep mode is entered by first writing the
Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
aWFI instruction. Any properly configured interrupt event in the system will bring the processor
back into Run mode. See “Power Management” on page 88 for more details.
181June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register,
up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system
clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling
the clocks that had been stopped during the Deep-Sleep duration.
■Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode conguration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or ash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source and allows
for the new PLL configuration to be validated before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
June 18, 2012182
Texas Instruments-Production Data
System Control
5.4 Register Map
Table 5-7 on page 183 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 5-7. System Control Register Map
See
page
DescriptionResetTypeNameOffset
185Device Identification 0-RODID00x000
201Device Identification 1-RODID10x004
203Device Capabilities 00x00FF.007FRODC00x008
204Device Capabilities 10x0010.30DFRODC10x010
206Device Capabilities 20x070F.1137RODC20x014
208Device Capabilities 30xBF00.FFFFRODC30x018
210Device Capabilities 40x5100.007FRODC40x01C
187Brown-Out Reset Control0x0000.7FFDR/WPBORCTL0x030
188LDO Power Control0x0000.0000R/WLDOPCTL0x034
233Software Reset Control 00x00000000R/WSRCR00x040
234Software Reset Control 10x00000000R/WSRCR10x044
236Software Reset Control 20x00000000R/WSRCR20x048
189Raw Interrupt Status0x0000.0000RORIS0x050
190Interrupt Mask Control0x0000.0000R/WIMC0x054
191Masked Interrupt Status and Clear0x0000.0000R/W1CMISC0x058
192Reset Cause-R/WRESC0x05C
193Run-Mode Clock Configuration0x078E.3AD1R/WRCC0x060
197XTAL to PLL Translation-ROPLLCFG0x064
198Run-Mode Clock Configuration 20x0780.2810R/WRCC20x070
212Run Mode Clock Gating Control Register 00x00000040R/WRCGC00x100
218Run Mode Clock Gating Control Register 10x00000000R/WRCGC10x104
227Run Mode Clock Gating Control Register 20x00000000R/WRCGC20x108
214Sleep Mode Clock Gating Control Register 00x00000040R/WSCGC00x110
221Sleep Mode Clock Gating Control Register 10x00000000R/WSCGC10x114
229Sleep Mode Clock Gating Control Register 20x00000000R/WSCGC20x118
216Deep Sleep Mode Clock Gating Control Register 00x00000040R/WDCGC00x120
183June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 5-7. System Control Register Map (continued)
See
page
DescriptionResetTypeNameOffset
224Deep Sleep Mode Clock Gating Control Register 10x00000000R/WDCGC10x124
231Deep Sleep Mode Clock Gating Control Register 20x00000000R/WDCGC20x128
200Deep Sleep Clock Configuration0x0780.0000R/WDSLPCLKCFG0x144
5.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
June 18, 2012184
Texas Instruments-Production Data
System Control
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
16171819202122232425262728293031
CLASSreservedVER
reserved
ROROROROROROROROROROROROROROROROType
1000000000001000Reset
0123456789101112131415
MINORMAJOR
ROROROROROROROROROROROROROROROROType
----------------Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
DescriptionValue
Second version of the DID0 register format.0x1
0x1ROVER30:28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved27:24
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
DescriptionValue
Stellaris® Fury-class devices.0x1
0x1ROCLASS23:16
185June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
DescriptionValue
Revision A (initial device)0x0
Revision B (first base layer revision)0x1
Revision C (second base layer revision)0x2
and so on.
-ROMAJOR15:8
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
DescriptionValue
Initial device, or a major revision update.0x0
First metal layer change.0x1
Second metal layer change.0x2
and so on.
-ROMINOR7:0
June 18, 2012186
Texas Instruments-Production Data
System Control
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
BORIORreserved
ROR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:2
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
0R/WBORIOR1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
187June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
VADJreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
VOUT (V)Value
2.500x00
2.450x01
2.400x02
2.350x03
2.300x04
2.250x05
Reserved0x06-0x3F
2.750x1B
2.700x1C
2.650x1D
2.600x1E
2.550x1F
0x0R/WVADJ5:0
June 18, 2012188
Texas Instruments-Production Data
System Control
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
BORRISreservedPLLLRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
0ROPLLLRIS6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
0ROBORRIS1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
189June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
BORIMreservedPLLLIMreserved
ROR/WROROROROR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Interrupt Mask
This bit specifies whether a PLL Lock interrupt is promoted to a controller
interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set;
otherwise, an interrupt is not generated.
0R/WPLLLIM6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
0R/WBORIM1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
June 18, 2012190
Texas Instruments-Production Data
System Control
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 189).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
BORMISreservedPLLLMISreserved
ROR/W1CROROROROR/W1CROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
0R/W1CPLLLMIS6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
0R/W1CBORMIS1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
191June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EXTPORBORWDTSWreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
-----00000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:5
Software Reset
When set, indicates a software reset is the cause of the reset event.
-R/WSW4
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
-R/WWDT3
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
-R/WBOR2
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
-R/WPOR1
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
-R/WEXT0
June 18, 2012192
Texas Instruments-Production Data
System Control
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AD1
16171819202122232425262728293031
reserved
PWMDIV
USEPWMDIVreservedUSESYSDIV
SYSDIVACGreserved
ROR/WR/WR/WR/WROR/WR/WR/WR/WR/WR/WROROROROType
0111000111100000Reset
0123456789101112131415
MOSCDISIOSCDISreservedOSCSRCXTAL
reserved
BYPASS
reserved
PWRDNreserved
R/WR/WROROR/WR/WR/WR/WR/WR/WROR/WROR/WROROType
1000101101011100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:28
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
0R/WACG27
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-5 on page 179 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 204), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
0xFR/WSYSDIV26:23
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.
0R/WUSESYSDIV22
193June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved21
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
0R/WUSEPWMDIV20
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
DivisorValue
/20x0
/40x1
/80x2
/160x3
/320x4
/640x5
/640x6
/64 (default)0x7
0x7R/WPWMDIV19:17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved16:14
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1R/WPWRDN13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1ROreserved12
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-5 on page 179 for programming guidelines.
1R/WBYPASS11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved10
June 18, 2012194
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz (see Table
21-10 on page 665 for more information).
Crystal Frequency (MHz) Using
the PLL
Crystal Frequency (MHz) Not
Using the PLL
Value
reserved1.0000x0
reserved1.84320x1
reserved2.0000x2
reserved2.45760x3
3.579545 MHz0x4
3.6864 MHz0x5
4 MHz0x6
4.096 MHz0x7
4.9152 MHz0x8
5 MHz0x9
5.12 MHz0xA
6 MHz (reset value)0xB
6.144 MHz0xC
7.3728 MHz0xD
8 MHz0xE
8.192 MHz0xF
0xBR/WXTAL9:6
Oscillator Source
Selects the input source for the OSC. The values are:
Input SourceValue
MOSC
Main oscillator
0x0
IOSC
Internal oscillator (default)
0x1
IOSC/4
Internal oscillator / 4
0x2
30 kHz
30-KHz internal oscillator
0x3
For additional oscillator sources, see the RCC2 register.
0x1R/WOSCSRC5:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
0R/WIOSCDIS1
195June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Main Oscillator Disable
0: Main oscillator is enabled .
1: Main oscillator is disabled (default).
1R/WMOSCDIS0
June 18, 2012196
Texas Instruments-Production Data
System Control
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 193).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RFreserved
ROROROROROROROROROROROROROROROROType
--------------00Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:14
PLL F Value
This field specifies the value supplied to the PLL’s F input.
-ROF13:5
PLL R Value
This field specifies the value supplied to the PLL’s R input.
-ROR4:0
197June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 5-8, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 5-8. RCC2 Fields that Override RCC fields
Overrides RCC FieldRCC2 Field...
SYSDIV, bits[26:23]SYSDIV2, bits[28:23]
PWRDN, bit[13]PWRDN2, bit[13]
BYPASS, bit[11]BYPASS2, bit[11]
OSCSRC, bits[5:4]OSCSRC2, bits[6:4]
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2810
16171819202122232425262728293031
reservedSYSDIV2reservedUSERCC2
ROROROROROROROR/WR/WR/WR/WR/WR/WROROR/WType
0000000111100000Reset
0123456789101112131415
reservedOSCSRC2reservedBYPASS2
reserved
PWRDN2reserved
ROROROROR/WR/WR/WROROROROR/WROR/WROROType
0000100000010100Reset
DescriptionResetTypeNameBit/Field
Use RCC2
When set, overrides the RCC register fields.
0R/WUSERCC231
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved30:29
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 5-6 on page 179 for programming guidelines.
0x0FR/WSYSDIV228:23
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved22:14
Power-Down PLL
When set, powers down the PLL.
1R/WPWRDN213
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12
June 18, 2012198
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Bypass PLL
When set, bypasses the PLL for the clock source.
See Table 5-6 on page 179 for programming guidelines.
1R/WBYPASS211
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved10:7
Oscillator Source
Selects the input source for the OSC. The values are:
DescriptionValue
MOSC
Main oscillator
0x0
IOSC
Internal oscillator
0x1
IOSC/4
Internal oscillator / 4
0x2
30 kHz
30-kHz internal oscillator
0x3
Reserved0x4
Reserved0x5
Reserved0x6
32 kHz
32.768-kHz external oscillator
0x7
0x1R/WOSCSRC26:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:0
199June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
16171819202122232425262728293031
reservedDSDIVORIDEreserved
ROROROROROROROR/WR/WR/WR/WR/WR/WROROROType
0000000111100000Reset
0123456789101112131415
reservedDSOSCSRCreserved
ROROROROR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:29
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
0x0FR/WDSDIVORIDE28:23
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved22:7
Clock Source
Specifies the clock source during Deep-Sleep mode.
DescriptionValue
MOSC
Use main oscillator as source.
0x0
IOSC
Use internal 12-MHz oscillator as source.
0x1
Reserved0x2
30 kHz
Use 30-kHz internal oscillator as source.
0x3
Reserved0x4
Reserved0x5
Reserved0x6
32 kHz
Use 32.768-kHz external oscillator as source.
0x7
0x0R/WDSOSCSRC6:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:0
June 18, 2012200
Texas Instruments-Production Data
System Control
Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
16171819202122232425262728293031
PARTNOFAMVER
ROROROROROROROROROROROROROROROROType
0100111000001000Reset
0123456789101112131415
QUALROHSPKGTEMPreservedPINCOUNT
ROROROROROROROROROROROROROROROROType
--1-----00000010Reset
DescriptionResetTypeNameBit/Field
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
DescriptionValue
Second version of the DID1 register format.0x1
0x1ROVER31:28
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
DescriptionValue
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
0x0ROFAM27:24
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
DescriptionValue
LM3S69500x72
0x72ROPARTNO23:16
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
DescriptionValue
100-pin or 108-ball package0x2
0x2ROPINCOUNT15:13
201June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12:8
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
DescriptionValue
Commercial temperature range (0°C to 70°C)0x0
Industrial temperature range (-40°C to 85°C)0x1
Extended temperature range (-40°C to 105°C)0x2
-ROTEMP7:5
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
DescriptionValue
SOIC package0x0
LQFP package0x1
BGA package0x2
-ROPKG4:3
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1ROROHS2
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
DescriptionValue
Engineering Sample (unqualified)0x0
Pilot Production (unqualified)0x1
Fully Qualified0x2
-ROQUAL1:0
June 18, 2012202
Texas Instruments-Production Data
System Control
Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.007F
16171819202122232425262728293031
SRAMSZ
ROROROROROROROROROROROROROROROROType
1111111100000000Reset
0123456789101112131415
FLASHSZ
ROROROROROROROROROROROROROROROROType
1111111000000000Reset
DescriptionResetTypeNameBit/Field
SRAM Size
Indicates the size of the on-chip SRAM memory.
DescriptionValue
64 KB of SRAM0x00FF
0x00FFROSRAMSZ31:16
Flash Size
Indicates the size of the on-chip flash memory.
DescriptionValue
256 KB of Flash0x007F
0x007FROFLASHSZ15:0
203June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0,SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0010.30DF
16171819202122232425262728293031
reservedPWMreserved
ROROROROROROROROROROROROROROROROType
0000100000000000Reset
0123456789101112131415
JTAGSWDSWOWDTPLL
reserved
HIBMPUreservedMINSYSDIV
ROROROROROROROROROROROROROROROROType
1111101100001100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:21
PWM Module Present
When set, indicates that the PWM module is present.
1ROPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:16
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
DescriptionValue
Specifies a 50-MHz CPU clock with a PLL divider of 4.0x3
0x3ROMINSYSDIV15:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:8
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the "Cortex-M3 Peripherals" chapter in the
Stellaris Data Sheet for details on the MPU.
1ROMPU7
Hibernation Module Present
When set, indicates that the Hibernation module is present.
1ROHIB6
June 18, 2012204
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
1ROPLL4
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
1ROWDT3
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1ROSWO2
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1ROSWD1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
1ROJTAG0
205June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1,SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x070F.1137
16171819202122232425262728293031
TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved
ROROROROROROROROROROROROROROROROType
1111000011100000Reset
0123456789101112131415
UART0UART1UART2
reserved
SSI0SSI1reservedQEI0reservedI2C0reserved
ROROROROROROROROROROROROROROROROType
1110110010001000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:27
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
1ROCOMP226
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
1ROCOMP125
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
1ROCOMP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:20
Timer 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
1ROTIMER319
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
1ROTIMER218
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
1ROTIMER117
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
1ROTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
June 18, 2012206
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
1ROI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:9
QEI0 Present
When set, indicates that QEI module 0 is present.
1ROQEI08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
SSI1 Present
When set, indicates that SSI module 1 is present.
1ROSSI15
SSI0 Present
When set, indicates that SSI module 0 is present.
1ROSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
UART2 Present
When set, indicates that UART module 2 is present.
1ROUART22
UART1 Present
When set, indicates that UART module 1 is present.
1ROUART11
UART0 Present
When set, indicates that UART module 0 is present.
1ROUART00
207June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBF00.FFFF
16171819202122232425262728293031
reservedCCP0CCP1CCP2CCP3CCP4CCP5
reserved
32KHZ
ROROROROROROROROROROROROROROROROType
0000000011111101Reset
0123456789101112131415
PWM0PWM1PWM2PWM3PWM4PWM5C0MINUSC0PLUSC0OC1MINUSC1PLUSC1OC2MINUSC2PLUSC2O
PWMFAULT
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
1RO32KHZ31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved30
CCP5 Pin Present
When set, indicates that Capture/Compare/PWM pin 5 is present.
1ROCCP529
CCP4 Pin Present
When set, indicates that Capture/Compare/PWM pin 4 is present.
1ROCCP428
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
1ROCCP327
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
1ROCCP226
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
1ROCCP125
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
1ROCCP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:16
PWM Fault Pin Present
When set, indicates that the PWM Fault pin is present.
1ROPWMFAULT15
C2o Pin Present
When set, indicates that the analog comparator 2 output pin is present.
1ROC2O14
June 18, 2012208
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
1ROC2PLUS13
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
1ROC2MINUS12
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
1ROC1O11
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
1ROC1PLUS10
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
1ROC1MINUS9
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
1ROC0O8
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
1ROC0PLUS7
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
1ROC0MINUS6
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
1ROPWM55
PWM4 Pin Present
When set, indicates that the PWM pin 4 is present.
1ROPWM44
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
1ROPWM33
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
1ROPWM22
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
1ROPWM11
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
1ROPWM00
209June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2,SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5100.007F
16171819202122232425262728293031
reservedE1588reservedEMAC0
reserved
EPHY0
reserved
ROROROROROROROROROROROROROROROROType
0000000010001010Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGreserved
ROROROROROROROROROROROROROROROROType
1111111000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
Ethernet PHY0 Present
When set, indicates that Ethernet PHY module 0 is present.
1ROEPHY030
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29
Ethernet MAC0 Present
When set, indicates that Ethernet MAC module 0 is present.
1ROEMAC028
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:25
1588 Capable
When set, indicates that that EMAC0 is 1588-capable.
1ROE158824
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:7
GPIO Port G Present
When set, indicates that GPIO Port G is present.
1ROGPIOG6
GPIO Port F Present
When set, indicates that GPIO Port F is present.
1ROGPIOF5
GPIO Port E Present
When set, indicates that GPIO Port E is present.
1ROGPIOE4
June 18, 2012210
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
GPIO Port D Present
When set, indicates that GPIO Port D is present.
1ROGPIOD3
GPIO Port C Present
When set, indicates that GPIO Port C is present.
1ROGPIOC2
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1ROGPIOB1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
1ROGPIOA0
211June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
16171819202122232425262728293031
reservedPWMreserved
ROROROROR/WROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedHIBreserved
ROROROR/WROROR/WROROROROROROROROROType
0000001000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:21
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:7
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
1R/WHIB6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:4
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WWDT3
June 18, 2012212
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
213June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
16171819202122232425262728293031
reservedPWMreserved
ROROROROR/WROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedHIBreserved
ROROROR/WROROR/WROROROROROROROROROType
0000001000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:21
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:7
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
1R/WHIB6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:4
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WWDT3
June 18, 2012214
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
215June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
16171819202122232425262728293031
reservedPWMreserved
ROROROROR/WROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedHIBreserved
ROROROR/WROROR/WROROROROROROROROROType
0000001000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:21
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:7
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
1R/WHIB6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:4
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WWDT3
June 18, 2012216
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
217June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved
R/WR/WR/WR/WROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1UART2
reserved
SSI0SSI1reservedQEI0reservedI2C0reserved
R/WR/WR/WROR/WR/WROROR/WROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:27
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP226
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP125
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:20
June 18, 2012218
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER319
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER218
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER117
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:9
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WQEI08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI15
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI04
219June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART22
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART11
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART00
June 18, 2012220
Texas Instruments-Production Data
System Control
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved
R/WR/WR/WR/WROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1UART2
reserved
SSI0SSI1reservedQEI0reservedI2C0reserved
R/WR/WR/WROR/WR/WROROR/WROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:27
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP226
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP125
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:20
221June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER319
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER218
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER117
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:9
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WQEI08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI15
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI04
June 18, 2012222
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART22
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART11
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART00
223June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved
R/WR/WR/WR/WROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1UART2
reserved
SSI0SSI1reservedQEI0reservedI2C0reserved
R/WR/WR/WROR/WR/WROROR/WROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:27
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP226
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP125
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WCOMP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:20
June 18, 2012224
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER319
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER218
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER117
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:9
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WQEI08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI15
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI04
225June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART22
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART11
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART00
June 18, 2012226
Texas Instruments-Production Data
System Control
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
16171819202122232425262728293031
reservedEMAC0
reserved
EPHY0
reserved
ROROROROROROROROROROROROR/WROR/WROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WEPHY030
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WEMAC028
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOG6
227June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOF5
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOE4
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOD3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOC2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOB1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOA0
June 18, 2012228
Texas Instruments-Production Data
System Control
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
16171819202122232425262728293031
reservedEMAC0
reserved
EPHY0
reserved
ROROROROROROROROROROROROR/WROR/WROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WEPHY030
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WEMAC028
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOG6
229June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOF5
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOE4
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOD3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOC2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOB1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOA0
June 18, 2012230
Texas Instruments-Production Data
System Control
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
16171819202122232425262728293031
reservedEMAC0
reserved
EPHY0
reserved
ROROROROROROROROROROROROR/WROR/WROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WEPHY030
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WEMAC028
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOG6
231June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOF5
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOE4
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOD3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOC2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOB1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOA0
June 18, 2012232
Texas Instruments-Production Data
System Control
Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
16171819202122232425262728293031
reservedPWMreserved
ROROROROR/WROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedHIBreserved
ROROROR/WROROR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:21
PWM Reset Control
Reset control for PWM module.
0R/WPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:7
HIB Reset Control
Reset control for the Hibernation module.
0R/WHIB6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:4
WDT Reset Control
Reset control for Watchdog unit.
0R/WWDT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
233June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved
R/WR/WR/WR/WROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1UART2
reserved
SSI0SSI1reservedQEI0reservedI2C0reserved
R/WR/WR/WROR/WR/WROROR/WROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:27
Analog Comp 2 Reset Control
Reset control for analog comparator 2.
0R/WCOMP226
Analog Comp 1 Reset Control
Reset control for analog comparator 1.
0R/WCOMP125
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
0R/WCOMP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:20
Timer 3 Reset Control
Reset control for General-Purpose Timer module 3.
0R/WTIMER319
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
0R/WTIMER218
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
0R/WTIMER117
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Reset Control
Reset control for I2C unit 0.
0R/WI2C012
June 18, 2012234
Texas Instruments-Production Data
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:9
QEI0 Reset Control
Reset control for QEI unit 0.
0R/WQEI08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
SSI1 Reset Control
Reset control for SSI unit 1.
0R/WSSI15
SSI0 Reset Control
Reset control for SSI unit 0.
0R/WSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
UART2 Reset Control
Reset control for UART unit 2.
0R/WUART22
UART1 Reset Control
Reset control for UART unit 1.
0R/WUART11
UART0 Reset Control
Reset control for UART unit 0.
0R/WUART00
235June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
16171819202122232425262728293031
reservedEMAC0
reserved
EPHY0
reserved
ROROROROROROROROROROROROR/WROR/WROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
PHY0 Reset Control
Reset control for Ethernet PHY unit 0.
0R/WEPHY030
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved29
MAC0 Reset Control
Reset control for Ethernet MAC unit 0.
0R/WEMAC028
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:7
Port G Reset Control
Reset control for GPIO Port G.
0R/WGPIOG6
Port F Reset Control
Reset control for GPIO Port F.
0R/WGPIOF5
Port E Reset Control
Reset control for GPIO Port E.
0R/WGPIOE4
Port D Reset Control
Reset control for GPIO Port D.
0R/WGPIOD3
Port C Reset Control
Reset control for GPIO Port C.
0R/WGPIOC2
Port B Reset Control
Reset control for GPIO Port B.
0R/WGPIOB1
Port A Reset Control
Reset control for GPIO Port A.
0R/WGPIOA0
June 18, 2012236
Texas Instruments-Production Data
System Control
6 Hibernation Module
The Hibernation Module manages removal and restoration of power to provide a means for reducing
power consumption. When the processor and peripherals are idle, power can be completely removed
with only the Hibernation module remaining powered. Power can be restored based on an external
signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can
be independently supplied from a battery or an auxiliary power supply.
The Hibernation module has the following features:
■ System power control using discrete external regulator
■ Dedicated pin for waking from an external signal
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time clock (RTC)
■ Two 32-bit RTC match registers for timed wake-up and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
■ RTC predivider trim for making fine adjustments to the clock rate
■ 64 32-bit words of non-volatile memory
■ Programmable interrupts for RTC match, external wake, and low battery events
237June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
6.1 Block Diagram
Figure 6-1. Hibernation Module Block Diagram
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
Pre-Divider
/128
XOSC0
XOSC1
HIBCTL.CLK32EN
HIBCTL.CLKSEL
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
RTC
Interrupts
Power
Sequence
Logic
MATCH0/1
WAKE
Interrupts
to CPU
Low Battery
Detect
LOWBAT
VDD
VBAT
HIB
HIBCTL.LOWBATEN HIBCTL.PWRCUT
HIBCTL.EXTWEN
HIBCTL.RTCWEN
HIBCTL.VABORT
Non-Volatile
Memory
64 words
HIBDATA
32.768 kHz
4.194304 MHz
6.2 Signal Description
Table 6-1 on page 238 and Table 6-2 on page 239 list the external signals of the Hibernation module
and describe the function of each. These signals have dedicated functions and are not alternate
functions for any GPIO signals.
Table 6-1. Hibernate Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODO51HIB
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
Power-55VBAT
An external input that brings the processor out of Hibernate
mode when asserted.
TTLI50WAKE
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
AnalogI52XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
AnalogO53XOSC1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 18, 2012238
Texas Instruments-Production Data
Hibernation Module
Table 6-2. Hibernate Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODOM12HIB
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
Power-L12VBAT
An external input that brings the processor out of Hibernate
mode when asserted.
TTLIM10WAKE
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
AnalogIK11XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
AnalogOK12XOSC1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
6.3 Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage
source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate
voltage source. The Hibernation module also has a separate clock source to maintain a real-time
clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on
the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain
value. The Hibernation module can also detect when the battery voltage is low, and optionally
prevent hibernation when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR).
6.3.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
restriction on timing for back-to-back reads from the Hibernation module. The following registers
are subject to this timing restriction:
■Hibernation RTC Counter (HIBRTCC)
■Hibernation RTC Match 0 (HIBRTCM0)
■Hibernation RTC Match 1 (HIBRTCM1)
■Hibernation RTC Load (HIBRTCLD)
■Hibernation RTC Trim (HIBRTCT)
■Hibernation Data (HIBDATA)
239June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
6.3.2 Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature is not used.
An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can
be connected to the XOSC0 pin. See Figure 6-2 on page 240 and Figure 6-3 on page 241. Note that
these diagrams only show the connection to the Hibernation pins and not to the full system. See
“Hibernation Module” on page 670 for specific values.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128,
resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must
leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the
Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator
is used for the clock source, no delay is needed.
Figure 6-2. Clock Source Using Crystal
Open drain
external wake
up circuit
3 V
Battery
GND
C2
C1
RL
X1
VBAT
EN
Input
Voltage
Regulator
or Switch
XOSC1
XOSC0
VDD
HIB
WAKE
OUTIN
Stellaris Microcontroller
RPU
Note: X1= Crystal frequency is fXOSC_XTAL.
C1,2 = Capacitor value derived from crystal vendor load capacitance specifications.
RL= Load resistor is RXOSC_LOAD.
RPU = Pull-up resistor (1 M½).
See “Hibernation Module” on page 670 for specific parameter values.
June 18, 2012240
Texas Instruments-Production Data
Hibernation Module
Figure 6-3. Clock Source Using Dedicated Oscillator
Open drain
external wake
up circuit
EN
3 V
Battery
GND
Stellaris Microcontroller
Input
Voltage
Regulator
or Switch
Clock
Source
(fEXT_OSC)
N.C. XOSC1
XOSC0
VDD
HIB
WAKE VBAT
OUTIN
RPU
Note: RPU = Pull-up resistor (1 M½).
6.3.3 Battery Management
The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage drops below
VLOWBAT. When this happens, an interrupt can be generated. The module can also be configured
so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery
voltage is not measured while in Hibernate mode.
Important: System level factors may affect the accuracy of the low battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD is
available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 243).
6.3.4 Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 240). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF,
and is used for one second out of every 64 seconds to divide the input clock. This allows the software
to make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.
241June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 243). As long as the RTC is enabled and a valid VBAT is present, the
RTC continues counting, regardless of whether VDD is present or if the part is in hibernation.
6.3.5 Battery-Backed Memory
The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The battery-backed memory can be accessed through the HIBDATA registers.
6.3.6 Power Control
Important: The Hibernation Module requires special system implementation considerations when
using HIB to control power, as it is intended to power-down all other sections of its host
device. All system signals and power supplies that connect to the chip must be driven
to 0 VDC or powered down with the same regulator controlled by HIB. See “Hibernation
Module” on page 670 for more details.
The Hibernation module controls power to the microcontroller through the use of the HIB pin. This
pin is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V
and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the
external regulator is turned off and no longer powers the system. The Hibernation module remains
powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake
event. Power to the device is restored by deasserting the HIB signal, which causes the external
regulator to turn power back on to the chip.
6.3.7 Initiating Hibernate
Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register.
Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or
by using an RTC match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. Software
can detect that the power-on was due to a wake from hibernation by examining the raw interrupt
status register (see “Interrupts and Status” on page 243) and by looking for state data in the
battery-backed memory (see “Battery-Backed Memory” on page 242).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.
June 18, 2012242
Texas Instruments-Production Data
Hibernation Module
6.3.8 Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.
6.4 Initialization and Configuration
The Hibernation module can be set in several different configurations. The following sections show
the recommended programming sequence for various scenarios. The examples below assume that
a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set
to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the
Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the system, software
must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 239). The registers that require a delay are listed in a note in “Register
Map” on page 244 as well as in each register description.
6.4.1 Initialization
The Hibernation module clock source must be enabled first, even if the RTC feature is not used. If
a 4.194304-MHz crystal is used, perform the following steps:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.
If a 32.678-kHz oscillator is used, then perform the following steps:
1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
2. No delay is necessary.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
6.4.2 RTC Match Functionality (No Hibernation)
Use the following steps to implement the RTC match functionality of the Hibernation module:
243June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
6.4.3 RTC Match/Wake-Up from Hibernation
Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
6.4.4 External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
6.4.5 RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
6.5 Register Map
Table 6-3 on page 245 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled
before the registers can be programmed (see page 212). There must be a delay of 3 system clocks
after the Hibernation module clock is enabled before any Hibernation module registers are accessed.
Important: The Hibernation module registers are reset under two conditions:
1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are
both cleared.
June 18, 2012244
Texas Instruments-Production Data
Hibernation Module
2. A cold POR, when both the VDD and VBAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
Table 6-3. Hibernation Module Register Map
See
page
DescriptionResetTypeNameOffset
246Hibernation RTC Counter0x0000.0000ROHIBRTCC0x000
247Hibernation RTC Match 00xFFFF.FFFFR/WHIBRTCM00x004
248Hibernation RTC Match 10xFFFF.FFFFR/WHIBRTCM10x008
249Hibernation RTC Load0xFFFF.FFFFR/WHIBRTCLD0x00C
250Hibernation Control0x8000.0000R/WHIBCTL0x010
252Hibernation Interrupt Mask0x0000.0000R/WHIBIM0x014
253Hibernation Raw Interrupt Status0x0000.0000ROHIBRIS0x018
254Hibernation Masked Interrupt Status0x0000.0000ROHIBMIS0x01C
255Hibernation Interrupt Clear0x0000.0000R/W1CHIBIC0x020
256Hibernation RTC Trim0x0000.7FFFR/WHIBRTCT0x024
257Hibernation Data-R/WHIBDATA
0x030-
0x12C
6.6 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
245June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
16171819202122232425262728293031
RTCC
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCC
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
RTC Counter
A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.
0x0000.0000RORTCC31:0
June 18, 2012246
Texas Instruments-Production Data
Hibernation Module
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
RTCM0
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
RTCM0
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
0xFFFF.FFFFR/WRTCM031:0
247June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
RTCM1
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
RTCM1
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
0xFFFF.FFFFR/WRTCM131:0
June 18, 2012248
Texas Instruments-Production Data
Hibernation Module
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is the 32-bit value loaded into the RTC counter.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
RTCLD
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
RTCLD
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
0xFFFF.FFFFR/WRTCLD31:0
249June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x8000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCENHIBREQCLKSELRTCWENPINWEN
LOWBATEN
CLK32ENVABORTreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Power Cut Abort Enable
DescriptionValue
Power cut occurs during a low-battery alert.0
Power cut is aborted.1
0R/WVABORT7
Clocking Enable
DescriptionValue
Disabled0
Enabled1
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
0R/WCLK32EN6
Low Battery Monitoring Enable
DescriptionValue
Disabled0
Enabled1
When set, low battery voltage detection is enabled (VBAT < VLOWBAT).
0R/WLOWBATEN5
External WAKE Pin Enable
DescriptionValue
Disabled0
Enabled1
When set, an external event on the WAKE pin will re-power the device.
0R/WPINWEN4
June 18, 2012250
Texas Instruments-Production Data
Hibernation Module
DescriptionResetTypeNameBit/Field
RTC Wake-up Enable
DescriptionValue
Disabled0
Enabled1
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
0R/WRTCWEN3
Hibernation Module Clock Select
DescriptionValue
Use Divide by 128 output. Use this value for a
4.194304-MHz crystal.
0
Use raw output. Use this value for a 32.768-kHz
oscillator.
1
0R/WCLKSEL2
Hibernation Request
DescriptionValue
Disabled0
Hibernation initiated1
After a wake-up event, this bit is cleared by hardware.
0R/WHIBREQ1
RTC Timer Enable
DescriptionValue
Disabled0
Enabled1
0R/WRTCEN0
251June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.0000ROreserved31:4
External Wake-Up Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WEXTW3
Low Battery Voltage Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WLOWBAT2
RTC Alert1 Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WRTCALT11
RTC Alert0 Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WRTCALT00
June 18, 2012252
Texas Instruments-Production Data
Hibernation Module
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.0000ROreserved31:4
External Wake-Up Raw Interrupt Status0ROEXTW3
Low Battery Voltage Raw Interrupt Status0ROLOWBAT2
RTC Alert1 Raw Interrupt Status0RORTCALT11
RTC Alert0 Raw Interrupt Status0RORTCALT00
253June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.0000ROreserved31:4
External Wake-Up Masked Interrupt Status0ROEXTW3
Low Battery Voltage Masked Interrupt Status0ROLOWBAT2
RTC Alert1 Masked Interrupt Status0RORTCALT11
RTC Alert0 Masked Interrupt Status0RORTCALT00
June 18, 2012254
Texas Instruments-Production Data
Hibernation Module
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.0000ROreserved31:4
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
0R/W1CEXTW3
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
0R/W1CLOWBAT2
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
0R/W1CRTCALT11
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
0R/W1CRTCALT00
255June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TRIM
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111110Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
0x7FFFR/WTRIM15:0
June 18, 2012256
Texas Instruments-Production Data
Hibernation Module
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store state information and does not lose power during a power-cut
operation as long as a battery is present.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset -
16171819202122232425262728293031
RTD
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
RTD
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
Hibernation Module NV Registers[63:0]-R/WRTD31:0
257June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
7 Internal Memory
The LM3S6950 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1 Block Diagram
Figure 7-1 on page 258 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 7-1. Flash Block Diagram
Flash Control
FMA
FMD
FCIM
FCMISC
Flash Array
Cortex-M3
Bridge
SRAM Array
System
Bus
Icode Bus
Dcode Bus
Flash Protection
FMPREn
FMPPEn
Flash Timing
USECRL
User Registers
USER_DBG
USER_REG0
USER_REG1
FMC
FCRIS
7.2 Functional Description
This section describes the functionality of the SRAM and Flash memories.
7.2.1 SRAM Memory
The internal SRAM of the Stellaris®devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
June 18, 2012258
Texas Instruments-Production Data
Internal Memory
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 74.
7.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 677 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
7.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
7.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 259.
Table 7-1. Flash Protection Policy Combinations
ProtectionFMPREnFMPPEn
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
00
259June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 7-1. Flash Protection Policy Combinations (continued)
ProtectionFMPREnFMPPEn
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
01
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
10
No protection. The block may be written, erased, executed or read.11
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register. Details on programming these bits
are discussed in “Nonvolatile Register Programming” on page 261.
7.2.2.3 Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 269) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 268).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 270).
7.3 Flash Memory Initialization and Configuration
7.3.1 Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA,FMD, and FMC.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.
June 18, 2012260
Texas Instruments-Production Data
Internal Memory
7.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
7.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
7.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
7.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the Flash memory itself.
These registers exist in a separate space from the main Flash memory array and are not affected
by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0
with a write operation. Prior to being committed, the register contents are unaffected by any reset
condition except power-on reset, which returns the register contents to the original value. By
committing the register values using the COMT bit in the FMC register, the register contents become
nonvolatile and are therefore retained following power cycling. Once the register contents are
committed, the contents are permanent, and they cannot be restored to their factory default values.
With the exception of the USER_DBG register, the settings in these registers can be tested before
committing them to Flash memory. For the USER_DBG register, the data to be written is loaded
into the FMD register before it is committed. The FMD register is read only and does not allow the
USER_DBG operation to be tried before committing it to nonvolatile memory.
Important: The Flash memory registers can only have bits changed from 1 to 0 by user programming
and can only be committed once. After being committed, these registers cannot be
restored to their factory default values.
In addition, the USER_REG0,USER_REG1,USER_REG2,USER_REG3, and USER_DBG registers
each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be
changed from 1 to 0. These five registers can only be committed once whereas the Flash memory
protection registers may be committed multiple times. Table 7-2 on page 262 provides the FMA
address required for commitment of each of the registers and the source of the data to be written
when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user
may poll the FMC register to wait for the commit operation to complete.
261June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 7-2. User-Programmable Flash Memory Resident Registers
Data SourceFMA ValueRegister to be Committed
FMPRE00x0000.0000FMPRE0
FMPRE10x0000.0002FMPRE1
FMPRE20x0000.0004FMPRE2
FMPRE30x0000.0006FMPRE3
FMPPE00x0000.0001FMPPE0
FMPPE10x0000.0003FMPPE1
FMPPE20x0000.0005FMPPE2
FMPPE30x0000.0007FMPPE3
USER_REG00x8000.0000USER_REG0
USER_REG10x8000.0001USER_REG1
USER_REG20x8000.0002USER_REG2
USER_REG30x8000.0003USER_REG3
FMD0x7510.0000USER_DBG
7.4 Register Map
Table 7-3 on page 262 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA,FMD,FMC,FCRIS,FCIM, and FCMISC register
offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory
protection register offsets are relative to the System Control base address of 0x400F.E000.
Table 7-3. Flash Register Map
See
page
DescriptionResetTypeNameOffset
Flash Memory Control Registers (Flash Control Offset)
264Flash Memory Address0x0000.0000R/WFMA0x000
265Flash Memory Data0x0000.0000R/WFMD0x004
266Flash Memory Control0x0000.0000R/WFMC0x008
268Flash Controller Raw Interrupt Status0x0000.0000ROFCRIS0x00C
269Flash Controller Interrupt Mask0x0000.0000R/WFCIM0x010
270Flash Controller Masked Interrupt Status and Clear0x0000.0000R/W1CFCMISC0x014
Flash Memory Protection Registers (System Control Offset)
273Flash Memory Protection Read Enable 00xFFFF.FFFFR/WFMPRE00x130
273Flash Memory Protection Read Enable 00xFFFF.FFFFR/WFMPRE00x200
274Flash Memory Protection Program Enable 00xFFFF.FFFFR/WFMPPE00x134
274Flash Memory Protection Program Enable 00xFFFF.FFFFR/WFMPPE00x400
272USec Reload0x31R/WUSECRL0x140
275User Debug0xFFFF.FFFER/WUSER_DBG0x1D0
276User Register 00xFFFF.FFFFR/WUSER_REG00x1E0
June 18, 2012262
Texas Instruments-Production Data
Internal Memory
Table 7-3. Flash Register Map (continued)
See
page
DescriptionResetTypeNameOffset
277User Register 10xFFFF.FFFFR/WUSER_REG10x1E4
278Flash Memory Protection Read Enable 10xFFFF.FFFFR/WFMPRE10x204
279Flash Memory Protection Read Enable 20xFFFF.FFFFR/WFMPRE20x208
280Flash Memory Protection Read Enable 30xFFFF.FFFFR/WFMPRE30x20C
281Flash Memory Protection Program Enable 10xFFFF.FFFFR/WFMPPE10x404
282Flash Memory Protection Program Enable 20xFFFF.FFFFR/WFMPPE20x408
283Flash Memory Protection Program Enable 30xFFFF.FFFFR/WFMPPE30x40C
7.5 Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
263June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
OFFSETreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
OFFSET
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:18
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register
Programming” on page 261 for details on values for this field).
0x0R/WOFFSET17:0
June 18, 2012264
Texas Instruments-Production Data
Internal Memory
Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Data Value
Data value for write operation.
0x0R/WDATA31:0
265June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 264). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 265) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
WRKEY
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
WRITEERASEMERASECOMTreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
0x0WOWRKEY31:16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved15:4
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
0R/WCOMT3
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
0R/WMERASE2
June 18, 2012266
Texas Instruments-Production Data
Internal Memory
DescriptionResetTypeNameBit/Field
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
0R/WERASE1
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 µs.
0R/WWRITE0
267June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ARISPRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:2
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC register bits (see page 266).
DescriptionValue
The programming cycle has completed.1
The programming cycle has not completed.0
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
0ROPRIS1
Access Raw Interrupt Status
DescriptionValue
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
1
No access has tried to improperly program or erase the Flash
memory.
0
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
0ROARIS0
June 18, 2012268
Texas Instruments-Production Data
Internal Memory
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMASKPMASKreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:2
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
DescriptionValue
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
1
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WPMASK1
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
DescriptionValue
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
1
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WAMASK0
269June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMISCPMISCreserved
R/W1CR/W1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:2
Programming Masked Interrupt Status and Clear
DescriptionValue
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 268).
1
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
0R/W1CPMISC1
Access Masked Interrupt Status and Clear
DescriptionValue
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 268).
1
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
0
0R/W1CAMISC0
June 18, 2012270
Texas Instruments-Production Data
Internal Memory
7.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
271June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
USECreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
1000110000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:8
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x31 (50 MHz) whenever the flash is being erased or programmed.
0x31R/WUSEC7:0
June 18, 2012272
Texas Instruments-Production Data
Internal Memory
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
DescriptionValue
Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
0xFFFFFFFF
0xFFFFFFFFR/WREAD_ENABLE31:0
273June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
0xFFFFFFFF
0xFFFFFFFFR/WPROG_ENABLE31:0
June 18, 2012274
Texas Instruments-Production Data
Internal Memory
Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to
0 disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and
is controlled through hardware to ensure that the register is only committed once. Prior to being
committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on
reset; any other type of reset does not affect this register. Once committed, this register cannot be
restored to the factory default value.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
16171819202122232425262728293031
DATANW
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
DBG0DBG1DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0111111111111111Reset
DescriptionResetTypeNameBit/Field
User Debug Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
1R/WNW31
User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
0x1FFFFFFFR/WDATA30:2
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1R/WDBG11
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0R/WDBG00
275June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
DATANW
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
1R/WNW31
User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
0x7FFFFFFFR/WDATA30:0
June 18, 2012276
Texas Instruments-Production Data
Internal Memory
Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
DATANW
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
1R/WNW31
User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
0x7FFFFFFFR/WDATA30:0
277June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
DescriptionValue
Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
0xFFFFFFFF
0xFFFFFFFFR/WREAD_ENABLE31:0
June 18, 2012278
Texas Instruments-Production Data
Internal Memory
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 256 KB of flash.0xFFFFFFFF
0xFFFFFFFFR/WREAD_ENABLE31:0
279June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 256 KB of flash.0xFFFFFFFF
0xFFFFFFFFR/WREAD_ENABLE31:0
June 18, 2012280
Texas Instruments-Production Data
Internal Memory
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
DescriptionValue
Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
0xFFFFFFFF
0xFFFFFFFFR/WPROG_ENABLE31:0
281June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 256 KB of flash.0xFFFFFFFF
0xFFFFFFFFR/WPROG_ENABLE31:0
June 18, 2012282
Texas Instruments-Production Data
Internal Memory
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 256 KB of flash.0xFFFFFFFF
0xFFFFFFFFR/WPROG_ENABLE31:0
283June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
8 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports 1-46
programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ 1-46 GPIOs, depending on configuration
■ 5-V-tolerant in input configuration
■ Fast toggle capable of a change every two clock cycles
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
8.1 Signal Description
GPIO signals have alternate hardware functions. Table 8-4 on page 287 and Table 8-5 on page 288
list the GPIO pins and the digital alternate functions. Other analog signals are 5-V tolerant and are
connected directly to their circuitry (C0-,C0+,C1-, C1+,C2-,C2+). These signals are configured
by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware
functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select
(GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control
(GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be
programmed individually; no type of grouping is implied by the columns in the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
June 18, 2012284
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Table 8-1. GPIO Pins With Non-Zero Reset Values
GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins
0x10011UART0PA[1:0]
0x10011SSI0PA[5:2]
0x10011I2C0PB[3:2]
0x31011JTAG/SWDPC[3:0]
Table 8-2. GPIO Pins and Alternate Functions (100LQFP)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
U0Rx26PA0
U0Tx27PA1
SSI0Clk28PA2
SSI0Fss29PA3
SSI0Rx30PA4
SSI0Tx31PA5
CCP134PA6
CCP435PA7
PWM266PB0
PWM367PB1
I2C0SCL70PB2
I2C0SDA71PB3
C0-92PB4
C1-91PB5
C0oC0+90PB6
TRST89PB7
SWCLKTCK80PC0
SWDIOTMS79PC1
TDI78PC2
SWOTDO77PC3
CCP525PC4
C1oC1+24PC5
C2oC2+23PC6
C2-22PC7
PWM010PD0
PhA011PD1
U1Rx12PD2
U1Tx13PD3
CCP095PD4
CCP296PD5
Fault99PD6
IDX0100PD7
SSI1Clk72PE0
285June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 8-2. GPIO Pins and Alternate Functions (100LQFP) (continued)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
SSI1Fss73PE1
SSI1Rx74PE2
SSI1Tx75PE3
CCP36PE4
5PE5
PWM42PE6
PWM51PE7
PhB047PF0
PWM161PF1
LED160PF2
LED059PF3
U2Rx19PG0
U2Tx18PG1
Table 8-3. GPIO Pins and Alternate Functions (108BGA)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
U0RxL3PA0
U0TxM3PA1
SSI0ClkM4PA2
SSI0FssL4PA3
SSI0RxL5PA4
SSI0TxM5PA5
CCP1L6PA6
CCP4M6PA7
PWM2E12PB0
PWM3D12PB1
I2C0SCLC11PB2
I2C0SDAC12PB3
C0-A6PB4
C1-B7PB5
C0oC0+A7PB6
TRSTA8PB7
SWCLKTCKA9PC0
SWDIOTMSB9PC1
TDIB8PC2
SWOTDOA10PC3
CCP5L1PC4
C1oC1+M1PC5
C2oC2+M2PC6
C2-L2PC7
PWM0G1PD0
June 18, 2012286
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Table 8-3. GPIO Pins and Alternate Functions (108BGA) (continued)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
PhA0G2PD1
U1RxH2PD2
U1TxH1PD3
CCP0E1PD4
CCP2E2PD5
FaultF2PD6
IDX0F1PD7
SSI1ClkA11PE0
SSI1FssB12PE1
SSI1RxB11PE2
SSI1TxA12PE3
CCP3D1PE4
D2PE5
PWM4C2PE6
PWM5C1PE7
PhB0M9PF0
PWM1H12PF1
LED1J11PF2
LED0J12PF3
U2RxK1PG0
U2TxK2PG1
Table 8-4. GPIO Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
GPIO port A bit 0.TTLI/O26PA0
GPIO port A bit 1.TTLI/O27PA1
GPIO port A bit 2.TTLI/O28PA2
GPIO port A bit 3.TTLI/O29PA3
GPIO port A bit 4.TTLI/O30PA4
GPIO port A bit 5.TTLI/O31PA5
GPIO port A bit 6.TTLI/O34PA6
GPIO port A bit 7.TTLI/O35PA7
GPIO port B bit 0.TTLI/O66PB0
GPIO port B bit 1.TTLI/O67PB1
GPIO port B bit 2.TTLI/O70PB2
GPIO port B bit 3.TTLI/O71PB3
GPIO port B bit 4.TTLI/O92PB4
GPIO port B bit 5.TTLI/O91PB5
GPIO port B bit 6.TTLI/O90PB6
GPIO port B bit 7.TTLI/O89PB7
GPIO port C bit 0.TTLI/O80PC0
287June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 8-4. GPIO Signals (100LQFP) (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
GPIO port C bit 1.TTLI/O79PC1
GPIO port C bit 2.TTLI/O78PC2
GPIO port C bit 3.TTLI/O77PC3
GPIO port C bit 4.TTLI/O25PC4
GPIO port C bit 5.TTLI/O24PC5
GPIO port C bit 6.TTLI/O23PC6
GPIO port C bit 7.TTLI/O22PC7
GPIO port D bit 0.TTLI/O10PD0
GPIO port D bit 1.TTLI/O11PD1
GPIO port D bit 2.TTLI/O12PD2
GPIO port D bit 3.TTLI/O13PD3
GPIO port D bit 4.TTLI/O95PD4
GPIO port D bit 5.TTLI/O96PD5
GPIO port D bit 6.TTLI/O99PD6
GPIO port D bit 7.TTLI/O100PD7
GPIO port E bit 0.TTLI/O72PE0
GPIO port E bit 1.TTLI/O73PE1
GPIO port E bit 2.TTLI/O74PE2
GPIO port E bit 3.TTLI/O75PE3
GPIO port E bit 4.TTLI/O6PE4
GPIO port E bit 5.TTLI/O5PE5
GPIO port E bit 6.TTLI/O2PE6
GPIO port E bit 7.TTLI/O1PE7
GPIO port F bit 0.TTLI/O47PF0
GPIO port F bit 1.TTLI/O61PF1
GPIO port F bit 2.TTLI/O60PF2
GPIO port F bit 3.TTLI/O59PF3
GPIO port G bit 0.TTLI/O19PG0
GPIO port G bit 1.TTLI/O18PG1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 8-5. GPIO Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
GPIO port A bit 0.TTLI/OL3PA0
GPIO port A bit 1.TTLI/OM3PA1
GPIO port A bit 2.TTLI/OM4PA2
GPIO port A bit 3.TTLI/OL4PA3
GPIO port A bit 4.TTLI/OL5PA4
GPIO port A bit 5.TTLI/OM5PA5
GPIO port A bit 6.TTLI/OL6PA6
GPIO port A bit 7.TTLI/OM6PA7
June 18, 2012288
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Table 8-5. GPIO Signals (108BGA) (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
GPIO port B bit 0.TTLI/OE12PB0
GPIO port B bit 1.TTLI/OD12PB1
GPIO port B bit 2.TTLI/OC11PB2
GPIO port B bit 3.TTLI/OC12PB3
GPIO port B bit 4.TTLI/OA6PB4
GPIO port B bit 5.TTLI/OB7PB5
GPIO port B bit 6.TTLI/OA7PB6
GPIO port B bit 7.TTLI/OA8PB7
GPIO port C bit 0.TTLI/OA9PC0
GPIO port C bit 1.TTLI/OB9PC1
GPIO port C bit 2.TTLI/OB8PC2
GPIO port C bit 3.TTLI/OA10PC3
GPIO port C bit 4.TTLI/OL1PC4
GPIO port C bit 5.TTLI/OM1PC5
GPIO port C bit 6.TTLI/OM2PC6
GPIO port C bit 7.TTLI/OL2PC7
GPIO port D bit 0.TTLI/OG1PD0
GPIO port D bit 1.TTLI/OG2PD1
GPIO port D bit 2.TTLI/OH2PD2
GPIO port D bit 3.TTLI/OH1PD3
GPIO port D bit 4.TTLI/OE1PD4
GPIO port D bit 5.TTLI/OE2PD5
GPIO port D bit 6.TTLI/OF2PD6
GPIO port D bit 7.TTLI/OF1PD7
GPIO port E bit 0.TTLI/OA11PE0
GPIO port E bit 1.TTLI/OB12PE1
GPIO port E bit 2.TTLI/OB11PE2
GPIO port E bit 3.TTLI/OA12PE3
GPIO port E bit 4.TTLI/OD1PE4
GPIO port E bit 5.TTLI/OD2PE5
GPIO port E bit 6.TTLI/OC2PE6
GPIO port E bit 7.TTLI/OC1PE7
GPIO port F bit 0.TTLI/OM9PF0
GPIO port F bit 1.TTLI/OH12PF1
GPIO port F bit 2.TTLI/OJ11PF2
GPIO port F bit 3.TTLI/OJ12PF3
GPIO port G bit 0.TTLI/OK1PG0
GPIO port G bit 1.TTLI/OK2PG1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
289June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
8.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 290). The LM3S6950 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
Figure 8-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
MUXMUXDEMUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
June 18, 2012290
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
8.2.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
8.2.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 298) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
8.2.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 297) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-2 on page 291, where uis data unchanged by the write.
Figure 8-2. GPIODATA Write Example
0 10 0 1 10 0 0
u 1u u 0 1u u
9876543210
1 11 0 0 11 1
76543210
GPIODATA
0xEB
0x098
ADDR[9:2]
0
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 291.
Figure 8-3. GPIODATA Read Example
0 10 1 0 00 1 0 0
0 10 1 0 00 0
9876543210
0 11 1 1 11 0
76543210
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
291June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
8.2.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■GPIO Interrupt Sense (GPIOIS) register (see page 299)
■GPIO Interrupt Both Edges (GPIOIBE) register (see page 300)
■GPIO Interrupt Event (GPIOIEV) register (see page 301)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 302).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 303 and page 304). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 305).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS,GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
8.2.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 306), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
8.2.4 Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 306) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 316) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 317) have been set to 1.
8.2.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R,GPIODR4R,GPIODR8R,GPIOODR,
GPIOPUR,GPIOPDR,GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
June 18, 2012292
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
8.2.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.3 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-6 on page 293
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-7 on page 294 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-6. GPIO Pad Configuration Examples
GPIO Register Bit Valuea
Configuration SLRDR8RDR4RDR2RPDRPURDENODRDIRAFSEL
XXXX??1000Digital Input (GPIO)
??????1010Digital Output (GPIO)
????XX1110Open Drain Output
(GPIO)
????XX11X1Open Drain
Input/Output (I2C)
XXXX??10X1Digital Input (Timer
CCP)
XXXX??10X1Digital Input (QEI)
??????10X1Digital Output (PWM)
??????10X1Digital Output (Timer
PWM)
??????10X1Digital Input/Output
(SSI)
??????10X1Digital Input/Output
(UART)
XXXX000000Analog Input
(Comparator)
??????10X1Digital Output
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
293June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 8-7. GPIO Interrupt Configuration Example
Pin 2 Bit Valuea
Desired
Interrupt
Event
Trigger
Register 01234567
XX0XXXXX0=edge
1=level
GPIOIS
XX0XXXXX0=single
edge
1=both
edges
GPIOIBE
XX1XXXXX0=Low level,
or negative
edge
1=High level,
or positive
edge
GPIOIEV
001000000=masked
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
8.4 Register Map
Table 8-8 on page 295 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
Note that the GPIO module clock must be enabled before the registers can be programmed (see
page 227). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect, and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL,GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
June 18, 2012294
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-committable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 8-8. GPIO Register Map
See
page
DescriptionResetTypeNameOffset
297GPIO Data0x0000.0000R/WGPIODATA0x000
298GPIO Direction0x0000.0000R/WGPIODIR0x400
299GPIO Interrupt Sense0x0000.0000R/WGPIOIS0x404
300GPIO Interrupt Both Edges0x0000.0000R/WGPIOIBE0x408
301GPIO Interrupt Event0x0000.0000R/WGPIOIEV0x40C
302GPIO Interrupt Mask0x0000.0000R/WGPIOIM0x410
303GPIO Raw Interrupt Status0x0000.0000ROGPIORIS0x414
304GPIO Masked Interrupt Status0x0000.0000ROGPIOMIS0x418
305GPIO Interrupt Clear0x0000.0000W1CGPIOICR0x41C
306GPIO Alternate Function Select-R/WGPIOAFSEL0x420
308GPIO 2-mA Drive Select0x0000.00FFR/WGPIODR2R0x500
309GPIO 4-mA Drive Select0x0000.0000R/WGPIODR4R0x504
310GPIO 8-mA Drive Select0x0000.0000R/WGPIODR8R0x508
311GPIO Open Drain Select0x0000.0000R/WGPIOODR0x50C
312GPIO Pull-Up Select-R/WGPIOPUR0x510
313GPIO Pull-Down Select0x0000.0000R/WGPIOPDR0x514
314GPIO Slew Rate Control Select0x0000.0000R/WGPIOSLR0x518
315GPIO Digital Enable-R/WGPIODEN0x51C
316GPIO Lock0x0000.0001R/WGPIOLOCK0x520
317GPIO Commit--GPIOCR0x524
319GPIO Peripheral Identification 40x0000.0000ROGPIOPeriphID40xFD0
320GPIO Peripheral Identification 50x0000.0000ROGPIOPeriphID50xFD4
321GPIO Peripheral Identification 60x0000.0000ROGPIOPeriphID60xFD8
322GPIO Peripheral Identification 70x0000.0000ROGPIOPeriphID70xFDC
323GPIO Peripheral Identification 00x0000.0061ROGPIOPeriphID00xFE0
324GPIO Peripheral Identification 10x0000.0000ROGPIOPeriphID10xFE4
325GPIO Peripheral Identification 20x0000.0018ROGPIOPeriphID20xFE8
326GPIO Peripheral Identification 30x0000.0001ROGPIOPeriphID30xFEC
295June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 8-8. GPIO Register Map (continued)
See
page
DescriptionResetTypeNameOffset
327GPIO PrimeCell Identification 00x0000.000DROGPIOPCellID00xFF0
328GPIO PrimeCell Identification 10x0000.00F0ROGPIOPCellID10xFF4
329GPIO PrimeCell Identification 20x0000.0005ROGPIOPCellID20xFF8
330GPIO PrimeCell Identification 30x0000.00B1ROGPIOPCellID30xFFC
8.5 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
June 18, 2012296
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 298).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 291 for examples of
reads and writes.
0x00R/WDATA7:0
297June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x400
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Data Direction
The DIR values are defined as follows:
DescriptionValue
Pins are inputs.0
Pins are outputs.1
0x00R/WDIR7:0
June 18, 2012298
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x404
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ISreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Sense
The IS values are defined as follows:
DescriptionValue
Edge on corresponding pin is detected (edge-sensitive).0
Level on corresponding pin is detected (level-sensitive).1
0x00R/WIS7:0
299June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 299) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 301). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IBEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Both Edges
The IBE values are defined as follows:
DescriptionValue
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 301).
0
Both edges on the corresponding pin trigger an interrupt.1
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
0x00R/WIBE7:0
June 18, 2012300
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 299). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IEVreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Event
The IEV values are defined as follows:
DescriptionValue
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
0x00R/WIEV7:0
301June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x410
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Mask Enable
The IME values are defined as follows:
DescriptionValue
Corresponding pin interrupt is masked.0
Corresponding pin interrupt is not masked.1
0x00R/WIME7:0
June 18, 2012302
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 302). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x414
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
DescriptionValue
Corresponding pin interrupt requirements not met.0
Corresponding pin interrupt has met requirements.1
0x00RORIS7:0
303June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x418
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
DescriptionValue
Corresponding GPIO line interrupt not active.0
Corresponding GPIO line asserting interrupt.1
0x00ROMIS7:0
June 18, 2012304
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ICreserved
W1CW1CW1CW1CW1CW1CW1CW1CROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Clear
The IC values are defined as follows:
DescriptionValue
Corresponding interrupt is unaffected.0
Corresponding interrupt is cleared.1
0x00W1CIC7:0
305June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 306) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 316) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 317) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris®microcontroller. If the program code loaded into ash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x420
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AFSELreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
June 18, 2012306
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
DescriptionResetTypeNameBit/Field
GPIO Alternate Function Select
The AFSEL values are defined as follows:
DescriptionValue
Software control of corresponding GPIO line (GPIO mode).0
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
-R/WAFSEL7:0
307June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DRV2reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
1111111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
0xFFR/WDRV27:0
June 18, 2012308
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x504
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DRV4reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
0x00R/WDRV47:0
309June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x508
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DRV8reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
0x00R/WDRV87:0
June 18, 2012310
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 315).
Corresponding bits in the drive strength registers (GPIODR2R,GPIODR4R,GPIODR8R, and
GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain
input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the
GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no
effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see
examples in “Initialization and Configuration” on page 293).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ODEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad Open Drain Enable
The ODE values are defined as follows:
DescriptionValue
Open drain configuration is disabled.0
Open drain configuration is enabled.1
0x00R/WODE7:0
311June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 313).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x510
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PUEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Pad Weak Pull-Up Enable
DescriptionValue
The corresponding pin's weak pull-up resistor is disabled.0
The corresponding pin's weak pull-up resistor is enabled.1
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL,GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
-R/WPUE7:0
June 18, 2012312
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 312).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x514
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PDEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Pad Weak Pull-Down Enable
DescriptionValue
The corresponding pin's weak pull-down resistor is disabled.0
The corresponding pin's weak pull-down resistor is enabled.1
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
0x00R/WPDE7:0
313June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 310).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x518
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SRLreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
DescriptionValue
Slew rate control disabled.0
Slew rate control enabled.1
0x00R/WSRL7:0
June 18, 2012314
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x51C
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DENreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Digital Enable
The DEN values are defined as follows:
DescriptionValue
Digital functions disabled.0
Digital functions enabled.1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
-R/WDEN7:0
315June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 317). Writing
0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x520
Type R/W, reset 0x0000.0001
16171819202122232425262728293031
LOCK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
LOCK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
GPIO Lock
A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR)
register for write access.
A write of any other value or a write to the GPIOCR register reapplies
the lock, preventing any register updates. A read of this register returns
the following values:
DescriptionValue
Locked0x0000.0001
Unlocked0x0000.0000
0x0000.0001R/WLOCK31:0
June 18, 2012316
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed.
If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the
GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR
register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be
committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR
register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted
to GPIOs through a deliberate set of writes to the GPIOLOCK,GPIOCR, and the
corresponding registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSELregister bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x524
Type -, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CRreserved
--------ROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
317June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-committable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
--CR7:0
June 18, 2012318
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[7:0]0x00ROPID47:0
319June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[15:8]0x00ROPID57:0
June 18, 2012320
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[23:16]0x00ROPID67:0
321June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[31:24]0x00ROPID77:0
June 18, 2012322
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
1000011000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x61ROPID07:0
323June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID17:0
June 18, 2012324
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x18ROPID27:0
325June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x01ROPID37:0
June 18, 2012326
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
0x0DROCID07:0
327June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
0xF0ROCID17:0
June 18, 2012328
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
0x05ROCID27:0
329June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
0xB1ROCID37:0
June 18, 2012330
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
9 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1,
Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer
resources include the System Timer (SysTick) (see 93) and the PWM timer in the PWM module
(see “PWM Timer” on page 575).
The General-Purpose Timers provide the following features:
■Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters.
Each GPTM can be configured to operate independently:
– As a single 32-bit timer
– As one 32-bit Real-Time Clock (RTC) to event capture
– For Pulse Width Modulation (PWM)
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock when using an external 32.768-KHz clock as the input
– User-enabled stalling when the controller asserts CPU Halt flag during debug
■ 16-bit Timer modes
–General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– User-enabled stalling when the controller asserts CPU Halt flag during debug
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
331June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
9.1 Block Diagram
Note: In Figure 9-1 on page 332, the specific CCP pins available depend on the Stellaris device.
See Table 9-1 on page 332 for the available CCPs.
Figure 9-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 9-1. Available CCP Pins
Odd CCP PinEven CCP Pin16-Bit Up/Down CounterTimer
-CCP0TimerATimer 0
CCP1-TimerB
-CCP2TimerATimer 1
CCP3-TimerB
-CCP4TimerATimer 2
CCP5-TimerB
--TimerATimer 3
--TimerB
9.2 Signal Description
Table 9-2 on page 333 and Table 9-3 on page 333 list the external signals of the GP Timer module
and describe the function of each. The GP Timer signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the GP Timer
June 18, 2012332
Texas Instruments-Production Data
General-Purpose Timers
function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 284.
Table 9-2. General-Purpose Timers Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Capture/Compare/PWM 0.TTLI/O95CCP0
Capture/Compare/PWM 1.TTLI/O34CCP1
Capture/Compare/PWM 2.TTLI/O96CCP2
Capture/Compare/PWM 3.TTLI/O6CCP3
Capture/Compare/PWM 4.TTLI/O35CCP4
Capture/Compare/PWM 5.TTLI/O25CCP5
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 9-3. General-Purpose Timers Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Capture/Compare/PWM 0.TTLI/OE1CCP0
Capture/Compare/PWM 1.TTLI/OL6CCP1
Capture/Compare/PWM 2.TTLI/OE2CCP2
Capture/Compare/PWM 3.TTLI/OD1CCP3
Capture/Compare/PWM 4.TTLI/OM6CCP4
Capture/Compare/PWM 5.TTLI/OL1CCP5
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
9.3 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 344),
the GPTM TimerA Mode (GPTMTAMR) register (see page 345), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 347). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
9.3.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 358) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 359). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 362) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 363).
9.3.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
333June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 358
■GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 359
■GPTM TimerA (GPTMTAR) register [15:0], see page 366
■GPTM TimerB (GPTMTBR) register [15:0], see page 367
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
9.3.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 345), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 349), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 354), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 356). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTMIMR) register (see page 352), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 355).
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
9.3.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 360) by the controller.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
June 18, 2012334
Texas Instruments-Production Data
General-Purpose Timers
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the
GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
9.3.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 344). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an nto
reference both.
9.3.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 9-4. 16-Bit Timer With Prescaler Configurations
UnitsMax Time#Clock (T c)a
Prescale
mS1.3107100000000
mS2.6214200000001
mS3.9322300000010
------------------
mS332.922925411111101
mS334.233625511111110
335June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 9-4. 16-Bit Timer With Prescaler Configurations (continued)
UnitsMax Time#Clock (T c)a
Prescale
mS335.544325611111111
a. Tc is the clock period.
9.3.3.2 16-Bit Input Edge Count Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 9-2 on page 337 shows how input edge count mode works. In this case, the timer start value
is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that
four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMTnMATCHR register.
June 18, 2012336
Texas Instruments-Production Data
General-Purpose Timers
Figure 9-2. 16-Bit Input Edge Count Mode Example
Input Signal
Timer stops,
flags
asserted
Timer reload
on next cycle Ignored Ignored
Count
0x000A
0x0006
0x0007
0x0008
0x0009
9.3.3.3 16-Bit Input Edge Time Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). The timer is capable of capturing three
types of events: rising edge, falling edge, or both. The timer is placed into Edge Time mode by
setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is
determined by the TnEVENT fields of the GPTMCTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMTnILR register.
Figure 9-3 on page 338 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
337June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 9-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
9.3.3.4 16-Bit PWM Mode
Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM
frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 on page 339 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is
GPTMTnMATCHR=0x411A.
June 18, 2012338
Texas Instruments-Production Data
General-Purpose Timers
Figure 9-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
9.4 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1,TIMER2, and TIMER3 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
9.4.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
339June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 340. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.4.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the
RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware
reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register.
9.4.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
June 18, 2012340
Texas Instruments-Production Data
General-Purpose Timers
In One-Shot mode, the timer stops counting after step 8 on page 340. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.4.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 341
through step 9 on page 341.
9.4.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
341June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
9.4.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
9.5 Register Map
Table 9-5 on page 342 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
■ Timer3: 0x4003.3000
Note that the Timer module clock must be enabled before the registers can be programmed (see
page 218). There must be a delay of 3 system clocks after the Timer module clock is enabled before
any Timer module registers are accessed.
Table 9-5. Timers Register Map
See
page
DescriptionResetTypeNameOffset
344GPTM Configuration0x0000.0000R/WGPTMCFG0x000
345GPTM TimerA Mode0x0000.0000R/WGPTMTAMR0x004
347GPTM TimerB Mode0x0000.0000R/WGPTMTBMR0x008
June 18, 2012342
Texas Instruments-Production Data
General-Purpose Timers
Table 9-5. Timers Register Map (continued)
See
page
DescriptionResetTypeNameOffset
349GPTM Control0x0000.0000R/WGPTMCTL0x00C
352GPTM Interrupt Mask0x0000.0000R/WGPTMIMR0x018
354GPTM Raw Interrupt Status0x0000.0000ROGPTMRIS0x01C
355GPTM Masked Interrupt Status0x0000.0000ROGPTMMIS0x020
356GPTM Interrupt Clear0x0000.0000W1CGPTMICR0x024
358GPTM TimerA Interval Load0xFFFF.FFFFR/WGPTMTAILR0x028
359GPTM TimerB Interval Load0x0000.FFFFR/WGPTMTBILR0x02C
360GPTM TimerA Match0xFFFF.FFFFR/WGPTMTAMATCHR0x030
361GPTM TimerB Match0x0000.FFFFR/WGPTMTBMATCHR0x034
362GPTM TimerA Prescale0x0000.0000R/WGPTMTAPR0x038
363GPTM TimerB Prescale0x0000.0000R/WGPTMTBPR0x03C
364GPTM TimerA Prescale Match0x0000.0000R/WGPTMTAPMR0x040
365GPTM TimerB Prescale Match0x0000.0000R/WGPTMTBPMR0x044
366GPTM TimerA0xFFFF.FFFFROGPTMTAR0x048
367GPTM TimerB0x0000.FFFFROGPTMTBR0x04C
9.6 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
343June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPTMCFGreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
GPTM Configuration
The GPTMCFG values are defined as follows:
DescriptionValue
32-bit timer configuration.0x0
32-bit real-time clock (RTC) counter configuration.0x1
Reserved0x2
Reserved0x3
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
0x0R/WGPTMCFG2:0
June 18, 2012344
Texas Instruments-Production Data
General-Purpose Timers
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAMRTACMRTAAMSreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
DescriptionValue
Capture mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
0R/WTAAMS3
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
DescriptionValue
Edge-Count mode0
Edge-Time mode1
0R/WTACMR2
345June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
GPTM TimerA Mode
The TAMR values are defined as follows:
DescriptionValue
Reserved0x0
One-Shot Timer mode0x1
Periodic Timer mode0x2
Capture mode0x3
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
0x0R/WTAMR1:0
June 18, 2012346
Texas Instruments-Production Data
General-Purpose Timers
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBMRTBCMRTBAMSreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
DescriptionValue
Capture mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
0R/WTBAMS3
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
DescriptionValue
Edge-Count mode0
Edge-Time mode1
0R/WTBCMR2
347June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
GPTM TimerB Mode
The TBMR values are defined as follows:
DescriptionValue
Reserved0x0
One-Shot Timer mode0x1
Periodic Timer mode0x2
Capture mode0x3
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
0x0R/WTBMR1:0
June 18, 2012348
Texas Instruments-Production Data
General-Purpose Timers
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAENTASTALLTAEVENTRTCEN
reserved
TAPWML
reserved
TBENTBSTALLTBEVENTreservedTBPWML
reserved
R/WR/WR/WR/WR/WROR/WROR/WR/WR/WR/WROROR/WROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:15
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
DescriptionValue
Output is unaffected.0
Output is inverted.1
0R/WTBPWML14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved13:12
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
DescriptionValue
Positive edge0x0
Negative edge0x1
Reserved0x2
Both edges0x3
0x0R/WTBEVENT11:10
349June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
DescriptionValue
Timer B continues counting while the processor is halted by the
debugger.
0
Timer B freezes counting while the processor is halted by the
debugger.
1
If the processor is executing normally, the TBSTALL bit is ignored.
0R/WTBSTALL9
GPTM TimerB Enable
The TBEN values are defined as follows:
DescriptionValue
TimerB is disabled.0
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0R/WTBEN8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
DescriptionValue
Output is unaffected.0
Output is inverted.1
0R/WTAPWML6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5
GPTM RTC Enable
The RTCEN values are defined as follows:
DescriptionValue
RTC counting is disabled.0
RTC counting is enabled.1
0R/WRTCEN4
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
DescriptionValue
Positive edge0x0
Negative edge0x1
Reserved0x2
Both edges0x3
0x0R/WTAEVENT3:2
June 18, 2012350
Texas Instruments-Production Data
General-Purpose Timers
DescriptionResetTypeNameBit/Field
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
DescriptionValue
Timer A continues counting while the processor is halted by the
debugger.
0
Timer A freezes counting while the processor is halted by the
debugger.
1
If the processor is executing normally, the TASTALL bit is ignored.
0R/WTASTALL1
GPTM TimerA Enable
The TAEN values are defined as follows:
DescriptionValue
TimerA is disabled.0
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0R/WTAEN0
351June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOIMCAMIMCAEIMRTCIMreservedTBTOIMCBMIMCBEIMreserved
R/WR/WR/WR/WROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCBEIM10
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCBMIM9
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WTBTOIM8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
June 18, 2012352
Texas Instruments-Production Data
General-Purpose Timers
DescriptionResetTypeNameBit/Field
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WRTCIM3
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCAEIM2
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCAMIM1
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WTATOIM0
353June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATORISCAMRISCAERISRTCRISreservedTBTORISCBMRISCBERISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
0ROCBERIS10
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
0ROCBMRIS9
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
0ROTBTORIS8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:4
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
0RORTCRIS3
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
0ROCAERIS2
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
0ROCAMRIS1
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0ROTATORIS0
June 18, 2012354
Texas Instruments-Production Data
General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOMISCAMMISCAEMISRTCMISreservedTBTOMISCBMMISCBEMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
0ROCBEMIS10
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
0ROCBMMIS9
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
0ROTBTOMIS8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:4
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
0RORTCMIS3
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
0ROCAEMIS2
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
0ROCAMMIS1
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0ROTATOMIS0
355June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOCINT
CAMCINTCAECINTRTCCINTreserved
TBTOCINT
CBMCINTCBECINTreserved
W1CW1CW1CW1CROROROROW1CW1CW1CROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCBECINT10
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCBMCINT9
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CTBTOCINT8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:4
June 18, 2012356
Texas Instruments-Production Data
General-Purpose Timers
DescriptionResetTypeNameBit/Field
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CRTCCINT3
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCAECINT2
GPTM CaptureA Match Interrupt Clear
The CAMCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCAMCINT1
GPTM TimerA Time-Out Interrupt Clear
The TATOCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CTATOCINT0
357June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x028
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
TAILRH
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
TAILRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
0xFFFFR/WTAILRH31:16
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
0xFFFFR/WTAILRL15:0
June 18, 2012358
Texas Instruments-Production Data
General-Purpose Timers
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBILRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
0xFFFFR/WTBILRL15:0
359June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
TAMRH
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
TAMRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
0xFFFFR/WTAMRH31:16
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
0xFFFFR/WTAMRL15:0
June 18, 2012360
Texas Instruments-Production Data
General-Purpose Timers
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x034
Type R/W, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBMRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
0xFFFFR/WTBMRL15:0
361June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x038
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAPSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 9-4 on page 335 for more details and an example.
0x00R/WTAPSR7:0
June 18, 2012362
Texas Instruments-Production Data
General-Purpose Timers
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x03C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBPSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 9-4 on page 335 for more details and an example.
0x00R/WTBPSR7:0
363June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x040
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAPSMRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
0x00R/WTAPSMR7:0
June 18, 2012364
Texas Instruments-Production Data
General-Purpose Timers
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x044
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBPSMRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
0x00R/WTBPSMR7:0
365June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x048
Type RO, reset 0xFFFF.FFFF
16171819202122232425262728293031
TARH
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
0123456789101112131415
TARL
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
0xFFFFROTARH31:16
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.
0xFFFFROTARL15:0
June 18, 2012366
Texas Instruments-Production Data
General-Purpose Timers
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x04C
Type RO, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBRL
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.
0xFFFFROTBRL15:0
367June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the controller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
June 18, 2012368
Texas Instruments-Production Data
Watchdog Timer
10.1 Block Diagram
Figure 10-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
10.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
369June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
10.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
10.4 Register Map
Table 10-1 on page 370 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 10-1. Watchdog Timer Register Map
See
page
DescriptionResetTypeNameOffset
372Watchdog Load0xFFFF.FFFFR/WWDTLOAD0x000
373Watchdog Value0xFFFF.FFFFROWDTVALUE0x004
374Watchdog Control0x0000.0000R/WWDTCTL0x008
375Watchdog Interrupt Clear-WOWDTICR0x00C
376Watchdog Raw Interrupt Status0x0000.0000ROWDTRIS0x010
377Watchdog Masked Interrupt Status0x0000.0000ROWDTMIS0x014
378Watchdog Test0x0000.0000R/WWDTTEST0x418
379Watchdog Lock0x0000.0000R/WWDTLOCK0xC00
380Watchdog Peripheral Identification 40x0000.0000ROWDTPeriphID40xFD0
381Watchdog Peripheral Identification 50x0000.0000ROWDTPeriphID50xFD4
382Watchdog Peripheral Identification 60x0000.0000ROWDTPeriphID60xFD8
383Watchdog Peripheral Identification 70x0000.0000ROWDTPeriphID70xFDC
384Watchdog Peripheral Identification 00x0000.0005ROWDTPeriphID00xFE0
385Watchdog Peripheral Identification 10x0000.0018ROWDTPeriphID10xFE4
386Watchdog Peripheral Identification 20x0000.0018ROWDTPeriphID20xFE8
June 18, 2012370
Texas Instruments-Production Data
Watchdog Timer
Table 10-1. Watchdog Timer Register Map (continued)
See
page
DescriptionResetTypeNameOffset
387Watchdog Peripheral Identification 30x0000.0001ROWDTPeriphID30xFEC
388Watchdog PrimeCell Identification 00x0000.000DROWDTPCellID00xFF0
389Watchdog PrimeCell Identification 10x0000.00F0ROWDTPCellID10xFF4
390Watchdog PrimeCell Identification 20x0000.0005ROWDTPCellID20xFF8
391Watchdog PrimeCell Identification 30x0000.00B1ROWDTPCellID30xFFC
10.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
371June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
WDTLoad
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
WDTLoad
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Watchdog Load Value0xFFFF.FFFFR/WWDTLoad31:0
June 18, 2012372
Texas Instruments-Production Data
Watchdog Timer
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
16171819202122232425262728293031
WDTValue
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
0123456789101112131415
WDTValue
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Watchdog Value
Current value of the 32-bit down counter.
0xFFFF.FFFFROWDTValue31:0
373June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTENRESENreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Watchdog Reset Enable
The RESEN values are defined as follows:
DescriptionValue
Disabled.0
Enable the Watchdog module reset output.1
0R/WRESEN1
Watchdog Interrupt Enable
The INTEN values are defined as follows:
DescriptionValue
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
Interrupt event enabled. Once enabled, all writes are ignored.1
0R/WINTEN0
June 18, 2012374
Texas Instruments-Production Data
Watchdog Timer
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
16171819202122232425262728293031
WDTIntClr
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
0123456789101112131415
WDTIntClr
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
DescriptionResetTypeNameBit/Field
Watchdog Interrupt Clear-WOWDTIntClr31:0
375June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
WDTRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0ROWDTRIS0
June 18, 2012376
Texas Instruments-Production Data
Watchdog Timer
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
WDTMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0ROWDTMIS0
377June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedSTALLreserved
ROROROROROROROROR/WROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:9
Watchdog Stall Enable
When set to 1, if the Stellaris microcontroller is stopped with a debugger,
the watchdog timer stops counting. Once the microcontroller is restarted,
the watchdog timer resumes counting.
0R/WSTALL8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:0
June 18, 2012378
Texas Instruments-Production Data
Watchdog Timer
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
WDTLock
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
WDTLock
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
DescriptionValue
Locked0x0000.0001
Unlocked0x0000.0000
0x0000R/WWDTLock31:0
379June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[7:0]0x00ROPID47:0
June 18, 2012380
Texas Instruments-Production Data
Watchdog Timer
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[15:8]0x00ROPID57:0
381June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[23:16]0x00ROPID67:0
June 18, 2012382
Texas Instruments-Production Data
Watchdog Timer
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[31:24]0x00ROPID77:0
383June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[7:0]0x05ROPID07:0
June 18, 2012384
Texas Instruments-Production Data
Watchdog Timer
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[15:8]0x18ROPID17:0
385June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[23:16]0x18ROPID27:0
June 18, 2012386
Texas Instruments-Production Data
Watchdog Timer
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[31:24]0x01ROPID37:0
387June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[7:0]0x0DROCID07:0
June 18, 2012388
Texas Instruments-Production Data
Watchdog Timer
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[15:8]0xF0ROCID17:0
389June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[23:16]0x05ROCID27:0
June 18, 2012390
Texas Instruments-Production Data
Watchdog Timer
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[31:24]0xB1ROCID37:0
391June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
11 Universal Asynchronous Receivers/Transmitters
(UARTs)
Each Stellaris®Universal Asynchronous Receiver/Transmitter (UART) has the following features:
■ Three fully programmable 16C550-type UARTs with IrDA support
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
June 18, 2012392
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
11.1 Block Diagram
Figure 11-1. UART Module Block Diagram
TxFIFO
16 x 8
.
.
.
RxFIFO
16 x 8
.
.
.
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
Interrupt Control
UARTDR
Control/Status
Transmitter
(with SIR
Transmit
Encoder)
Baud Rate
Generator
Receiver
(with SIR
Receive
Decoder)
UnTx
UnRx
System Clock
Interrupt
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTIBRD
UARTFBRD
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
11.2 Signal Description
Table 11-1 on page 393 and Table 11-2 on page 394 list the external signals of the UART module
and describe the function of each. The UART signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default
to the UART function. The column in the table below titled "Pin Assignment" lists the possible GPIO
pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 306) should be set to choose the UART function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284.
Table 11-1. UART Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLI26U0Rx
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO27U0Tx
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLI12U1Rx
393June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 11-1. UART Signals (100LQFP) (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO13U1Tx
UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLI19U2Rx
UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO18U2Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 11-2. UART Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIL3U0Rx
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOM3U0Tx
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIH2U1Rx
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOH1U1Tx
UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIK1U2Rx
UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOK2U2Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
11.3 Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 413). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
11.3.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 11-2 on page 395 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
June 18, 2012394
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 11-2. UART Character Frame
1
05-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
11.3.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 409) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 410). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 411), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■UARTIBRD write, UARTFBRD write, and UARTLCRH write
■UARTFBRD write, UARTIBRD write, and UARTLCRH write
■UARTIBRD write and UARTLCRH write
■UARTFBRD write and UARTLCRH write
11.3.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 406) is asserted as soon as
395June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 394).
The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it
is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle
of Baud16 (that is, one bit period later) according to the programmed length of the data characters.
The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the
UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
11.3.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 408 for more
information on IrDA low-power pulse-duration configuration.
Figure 11-3 on page 397 shows the UART transmit and receive signals, with and without IrDA
modulation.
June 18, 2012396
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 11-3. IrDA Data Modulation
1
010 001101
Data bits
1
010 001101
Data bits
Start
bit
Start Stop
Bit period Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal
as an alternate function must be configured as the UnRx signal and pulled High.
11.3.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 402). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 411).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 406) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE,TXFF,RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 415). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
11.3.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
397June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 420).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 417) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 419).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 421).
The receive interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of the following events occurs:
■If the FIFOs are enabled and the transmit FIFO reaches the programmed trigger level, the TXRIS
bit is set. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes
greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
11.3.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 413). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
June 18, 2012398
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
11.3.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
11.4 Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0,UART1, or UART2
bits in the RCGC1 register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 395, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 409) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 410) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
399June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
11.5 Register Map
Table 11-3 on page 400 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 218). There must be a delay of 3 system clocks after the UART module clock is enabled before
any UART module registers are accessed.
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 413)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-3. UART Register Map
See
page
DescriptionResetTypeNameOffset
402UART Data0x0000.0000R/WUARTDR0x000
404UART Receive Status/Error Clear0x0000.0000R/WUARTRSR/UARTECR0x004
406UART Flag0x0000.0090ROUARTFR0x018
408UART IrDA Low-Power Register0x0000.0000R/WUARTILPR0x020
409UART Integer Baud-Rate Divisor0x0000.0000R/WUARTIBRD0x024
410UART Fractional Baud-Rate Divisor0x0000.0000R/WUARTFBRD0x028
411UART Line Control0x0000.0000R/WUARTLCRH0x02C
413UART Control0x0000.0300R/WUARTCTL0x030
415UART Interrupt FIFO Level Select0x0000.0012R/WUARTIFLS0x034
417UART Interrupt Mask0x0000.0000R/WUARTIM0x038
419UART Raw Interrupt Status0x0000.000FROUARTRIS0x03C
420UART Masked Interrupt Status0x0000.0000ROUARTMIS0x040
421UART Interrupt Clear0x0000.0000W1CUARTICR0x044
423UART Peripheral Identification 40x0000.0000ROUARTPeriphID40xFD0
424UART Peripheral Identification 50x0000.0000ROUARTPeriphID50xFD4
425UART Peripheral Identification 60x0000.0000ROUARTPeriphID60xFD8
426UART Peripheral Identification 70x0000.0000ROUARTPeriphID70xFDC
427UART Peripheral Identification 00x0000.0011ROUARTPeriphID00xFE0
428UART Peripheral Identification 10x0000.0000ROUARTPeriphID10xFE4
429UART Peripheral Identification 20x0000.0018ROUARTPeriphID20xFE8
430UART Peripheral Identification 30x0000.0001ROUARTPeriphID30xFEC
June 18, 2012400
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Table 11-3. UART Register Map (continued)
See
page
DescriptionResetTypeNameOffset
431UART PrimeCell Identification 00x0000.000DROUARTPCellID00xFF0
432UART PrimeCell Identification 10x0000.00F0ROUARTPCellID10xFF4
433UART PrimeCell Identification 20x0000.0005ROUARTPCellID20xFF8
434UART PrimeCell Identification 30x0000.00B1ROUARTPCellID30xFFC
11.6 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
401June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: UART Data (UARTDR), offset 0x000
Important: This register is read-sensitive. See the register description for details.
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAFEPEBEOEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
UART Overrun Error
The OE values are defined as follows:
DescriptionValue
There has been no data loss due to a FIFO overrun.0
New data was received when the FIFO was full, resulting in
data loss.
1
0ROOE11
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
0ROBE10
June 18, 2012402
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
DescriptionResetTypeNameBit/Field
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0ROPE9
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
0ROFE8
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
0R/WDATA7:0
403June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Reads
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FEPEBEOEreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
0ROOE3
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
0ROBE2
June 18, 2012404
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
DescriptionResetTypeNameBit/Field
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0ROPE1
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0ROFE0
Writes
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
DATAreserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0WOreserved31:8
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
0WODATA7:0
405June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF,RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBUSYRXFETXFFRXFFTXFEreserved
ROROROROROROROROROROROROROROROROType
0000100100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
1ROTXFE7
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
0RORXFF6
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
0ROTXFF5
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
1RORXFE4
June 18, 2012406
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
DescriptionResetTypeNameBit/Field
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
0ROBUSY3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
407June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ILPDVSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
0x00R/WILPDVSR7:0
June 18, 2012408
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 395
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x024
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIVINT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:16
Integer Baud-Rate Divisor0x0000R/WDIVINT15:0
409June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 395
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x028
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIVFRACreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Fractional Baud-Rate Divisor0x000R/WDIVFRAC5:0
June 18, 2012410
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x02C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BRKPENEPSSTP2FENWLENSPSreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
0R/WSPS7
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
DescriptionValue
8 bits0x3
7 bits0x2
6 bits0x1
5 bits (default)0x0
0R/WWLEN6:5
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
0R/WFEN4
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
0R/WSTP23
411June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
0R/WEPS2
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
0R/WPEN1
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0R/WBRK0
June 18, 2012412
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UARTENSIRENSIRLPreservedLBETXERXEreserved
R/WR/WR/WROROROROR/WR/WR/WROROROROROROType
0000000011000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:10
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
1R/WRXE9
413June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
1R/WTXE8
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
0R/WLBE7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved6:3
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 408 for more
information.
0R/WSIRLP2
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
0R/WSIREN1
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0R/WUARTEN0
June 18, 2012414
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x034
Type R/W, reset 0x0000.0012
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TXIFLSELRXIFLSELreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0100100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
DescriptionValue
RX FIFO ≥ ⅛ full0x0
RX FIFO ≥ ¼ full0x1
RX FIFO ≥ ½ full (default)0x2
RX FIFO ≥ ¾ full0x3
RX FIFO ≥ ⅞ full0x4
Reserved0x5-0x7
0x2R/WRXIFLSEL5:3
415June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
DescriptionValue
TX FIFO ≤ ⅞ empty0x0
TX FIFO ≤ ¾ empty0x1
TX FIFO ≤ ½ empty (default)0x2
TX FIFO ≤ ¼ empty0x3
TX FIFO ≤ ⅛ empty0x4
Reserved0x5-0x7
0x2R/WTXIFLSEL2:0
June 18, 2012416
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXIMTXIMRTIMFEIMPEIMBEIMOEIMreserved
ROROROROR/WR/WR/WR/WR/WR/WR/WROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
0R/WOEIM10
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
0R/WBEIM9
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
0R/WPEIM8
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
0R/WFEIM7
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
0R/WRTIM6
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
0R/WTXIM5
417June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
0R/WRXIM4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved3:0
June 18, 2012418
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.000F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXRISTXRISRTRISFERISPERISBERISOERISreserved
ROROROROROROROROROROROROROROROROType
1111000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROOERIS10
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROBERIS9
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROPERIS8
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROFERIS7
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0RORTRIS6
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROTXRIS5
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0RORXRIS4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0xFROreserved3:0
419June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXMISTXMISRTMISFEMISPEMISBEMISOEMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROOEMIS10
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROBEMIS9
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROPEMIS8
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROFEMIS7
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0RORTMIS6
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROTXMIS5
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0RORXMIS4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:0
June 18, 2012420
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXICTXICRTICFEICPEICBEICOEICreserved
ROROROROW1CW1CW1CW1CW1CW1CW1CROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1COEIC10
Break Error Interrupt Clear
The BEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CBEIC9
Parity Error Interrupt Clear
The PEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CPEIC8
421June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Framing Error Interrupt Clear
The FEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CFEIC7
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CRTIC6
Transmit Interrupt Clear
The TXIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CTXIC5
Receive Interrupt Clear
The RXIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CRXIC4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved3:0
June 18, 2012422
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID47:0
423June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID57:0
June 18, 2012424
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID67:0
425June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID77:0
June 18, 2012426
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE0
Type RO, reset 0x0000.0011
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
1000100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x11ROPID07:0
427June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID17:0
June 18, 2012428
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x18ROPID27:0
429June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x01ROPID37:0
June 18, 2012430
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
0x0DROCID07:0
431June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
0xF0ROCID17:0
June 18, 2012432
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
0x05ROCID27:0
433June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
0xB1ROCID37:0
June 18, 2012434
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
12 Synchronous Serial Interface (SSI)
The Stellaris®microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI
is a master or slave interface for synchronous serial communication with peripheral devices that
have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
Each Stellaris SSI module has the following features:
■ Two SSI modules, each with the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
12.1 Block Diagram
Figure 12-1. SSI Module Block Diagram
Transmit /
Receive
Logic
Clock
Prescaler
SSICPSR
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x16
.
.
.
RxFIFO
8 x16
.
.
.
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification
Registers
SSIPCellID0 0 SSIPeriphID 4
SSIPCellID1 1 SSIPeriphID 5
SSIPCellID2 2 SSIPeriphID 6
SSIPCellID3 SSIPeriphID 3 SSIPeriphID 7
Control/ Status
SSIPeriphID
SSIPeriphID
SSIPeriphID
435June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
12.2 Signal Description
Table 12-1 on page 436 and Table 12-2 on page 436 list the external signals of the SSI module and
describe the function of each. The SSI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset., with the exception of the SSI0Clk,SSI0Fss,SSI0Rx, and
SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 306) should be set to choose the SSI function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284.
Table 12-1. SSI Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
SSI module 0 clockTTLI/O28SSI0Clk
SSI module 0 frame signalTTLI/O29SSI0Fss
SSI module 0 receiveTTLI30SSI0Rx
SSI module 0 transmitTTLO31SSI0Tx
SSI module 1 clockTTLI/O72SSI1Clk
SSI module 1 frame signalTTLI/O73SSI1Fss
SSI module 1 receiveTTLI74SSI1Rx
SSI module 1 transmitTTLO75SSI1Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 12-2. SSI Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
SSI module 0 clockTTLI/OM4SSI0Clk
SSI module 0 frame signalTTLI/OL4SSI0Fss
SSI module 0 receiveTTLIL5SSI0Rx
SSI module 0 transmitTTLOM5SSI0Tx
SSI module 1 clockTTLI/OA11SSI1Clk
SSI module 1 frame signalTTLI/OB12SSI1Fss
SSI module 1 receiveTTLIB11SSI1Rx
SSI module 1 transmitTTLOA12SSI1Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
12.3 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
12.3.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
June 18, 2012436
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
(SSICPSR) register (see page 455). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 448).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 671 to view SSI timing parameters.
12.3.2 FIFO Operation
12.3.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 452), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a µDMA request when the FIFO is empty.
12.3.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
12.3.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 456). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
437June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 458 and page 459, respectively).
12.3.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
12.3.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 12-2 on page 438 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
June 18, 2012438
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 12-3 on page 439 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB
LSB
SSIClk
SSIFss
SSITx/SSIRx
4 to 16 bits
12.3.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
12.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 12-4 on page 440 and Figure 12-5 on page 440.
439June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx Q
SSITx MSB
MSB
LSB
LSB
4 to 16 bits
Note: Q is undefined.
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
LSB MSB
MSB
MSB
LSB
4 to16 bits
In this configuration, during idle periods:
■SSIClk is forced Low
■SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
June 18, 2012440
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
12.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
12-6 on page 441, which covers both single and continuous transfers.
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q
MSB
LSB
LSB
4 to 16 bits
Q
Note: Q is undefined.
In this configuration, during idle periods:
■SSIClk is forced Low
■SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 12-7 on page 442 and Figure 12-8 on page 442.
441June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
QMSB
MSB LSB
LSB
4 to 16 bits
Note: Q is undefined.
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
LSB MSB
4 to 16 bits
In this configuration, during idle periods:
■SSIClk is forced High
■SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
June 18, 2012442
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
12.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
12-9 on page 443, which covers both single and continuous transfers.
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
MSB
LSB
LSB
4 to 16 bits
Q
Note: Q is undefined.
In this configuration, during idle periods:
■SSIClk is forced High
■SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.3.4.7 MICROWIRE Frame Format
Figure 12-10 on page 444 shows the MICROWIRE frame format, again for a single frame. Figure
12-11 on page 445 shows the same format when back-to-back frames are transmitted.
443June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 12-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx 0
SSITx
8-bit control
4 to 16 bits
output data
LSB
MSB
MSB
LSB
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■SSIClk is forced Low
■SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
June 18, 2012444
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
LSB
MSB
SSIRx 0
SSITx LSB
LSB
MSB
4 to 16 bits
output data
8-bit control
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 12-12 on page 445 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk
)
tHold=tSSIClk
12.4 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
445June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
12.5 Register Map
Table 12-3 on page 447 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 218). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
June 18, 2012446
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Table 12-3. SSI Register Map
See
page
DescriptionResetTypeNameOffset
448SSI Control 00x0000.0000R/WSSICR00x000
450SSI Control 10x0000.0000R/WSSICR10x004
452SSI Data0x0000.0000R/WSSIDR0x008
453SSI Status0x0000.0003ROSSISR0x00C
455SSI Clock Prescale0x0000.0000R/WSSICPSR0x010
456SSI Interrupt Mask0x0000.0000R/WSSIIM0x014
458SSI Raw Interrupt Status0x0000.0008ROSSIRIS0x018
459SSI Masked Interrupt Status0x0000.0000ROSSIMIS0x01C
460SSI Interrupt Clear0x0000.0000W1CSSIICR0x020
461SSI Peripheral Identification 40x0000.0000ROSSIPeriphID40xFD0
462SSI Peripheral Identification 50x0000.0000ROSSIPeriphID50xFD4
463SSI Peripheral Identification 60x0000.0000ROSSIPeriphID60xFD8
464SSI Peripheral Identification 70x0000.0000ROSSIPeriphID70xFDC
465SSI Peripheral Identification 00x0000.0022ROSSIPeriphID00xFE0
466SSI Peripheral Identification 10x0000.0000ROSSIPeriphID10xFE4
467SSI Peripheral Identification 20x0000.0018ROSSIPeriphID20xFE8
468SSI Peripheral Identification 30x0000.0001ROSSIPeriphID30xFEC
469SSI PrimeCell Identification 00x0000.000DROSSIPCellID00xFF0
470SSI PrimeCell Identification 10x0000.00F0ROSSIPCellID10xFF4
471SSI PrimeCell Identification 20x0000.0005ROSSIPCellID20xFF8
472SSI PrimeCell Identification 30x0000.00B1ROSSIPCellID30xFFC
12.6 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
447June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DSSFRFSPOSPHSCR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
0x0000R/WSCR15:8
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
0R/WSPH7
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
0R/WSPO6
June 18, 2012448
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
DescriptionResetTypeNameBit/Field
SSI Frame Format Select
The FRF values are defined as follows:
Frame FormatValue
Freescale SPI Frame Format0x0
Texas Instruments Synchronous Serial Frame Format0x1
MICROWIRE Frame Format0x2
Reserved0x3
0x0R/WFRF5:4
SSI Data Size Select
The DSS values are defined as follows:
Data SizeValue
Reserved0x0-0x2
4-bit data0x3
5-bit data0x4
6-bit data0x5
7-bit data0x6
8-bit data0x7
9-bit data0x8
10-bit data0x9
11-bit data0xA
12-bit data0xB
13-bit data0xC
14-bit data0xD
15-bit data0xE
16-bit data0xF
0x00R/WDSS3:0
449June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LBMSSEMSSODreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
DescriptionValue
SSI can drive SSITx output in Slave Output mode.0
SSI must not drive the SSITx output in Slave mode.1
0R/WSOD3
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
DescriptionValue
Device configured as a master.0
Device configured as a slave.1
0R/WMS2
June 18, 2012450
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
DescriptionResetTypeNameBit/Field
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
DescriptionValue
SSI operation disabled.0
SSI operation enabled.1
Note: This bit must be set to 0 before any control registers
are reprogrammed.
0R/WSSE1
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
DescriptionValue
Normal serial port operation enabled.0
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0R/WLBM0
451June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: SSI Data (SSIDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
0x0000R/WDATA15:0
June 18, 2012452
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TFETNFRNERFFBSYreserved
R0ROROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:5
SSI Busy Bit
The BSY values are defined as follows:
DescriptionValue
SSI is idle.0
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
0ROBSY4
SSI Receive FIFO Full
The RFF values are defined as follows:
DescriptionValue
Receive FIFO is not full.0
Receive FIFO is full.1
0RORFF3
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
DescriptionValue
Receive FIFO is empty.0
Receive FIFO is not empty.1
0RORNE2
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
DescriptionValue
Transmit FIFO is full.0
Transmit FIFO is not full.1
1ROTNF1
453June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
SSI Transmit FIFO Empty
The TFE values are defined as follows:
DescriptionValue
Transmit FIFO is not empty.0
Transmit FIFO is empty.1
1R0TFE0
June 18, 2012454
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CPSDVSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
0x00R/WCPSDVSR7:0
455June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORIMRTIMRXIMTXIMreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
DescriptionValue
TX FIFO half-empty or less condition interrupt is masked.0
TX FIFO half-empty or less condition interrupt is not masked.1
0R/WTXIM3
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
DescriptionValue
RX FIFO half-full or more condition interrupt is masked.0
RX FIFO half-full or more condition interrupt is not masked.1
0R/WRXIM2
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
DescriptionValue
RX FIFO time-out interrupt is masked.0
RX FIFO time-out interrupt is not masked.1
0R/WRTIM1
June 18, 2012456
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
DescriptionResetTypeNameBit/Field
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
DescriptionValue
RX FIFO overrun interrupt is masked.0
RX FIFO overrun interrupt is not masked.1
0R/WRORIM0
457June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
Type RO, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORRISRTRISRXRISTXRISreserved
ROROROROROROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half empty or less, when set.
1ROTXRIS3
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
0RORXRIS2
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
0RORTRIS1
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0RORORRIS0
June 18, 2012458
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORMISRTMISRXMISTXMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half empty or less, when set.
0ROTXMIS3
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
0RORXMIS2
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
0RORTMIS1
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0RORORMIS0
459June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORICRTICreserved
W1CW1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
DescriptionValue
No effect on interrupt.0
Clears interrupt.1
0W1CRTIC1
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
DescriptionValue
No effect on interrupt.0
Clears interrupt.1
0W1CRORIC0
June 18, 2012460
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x00ROPID47:0
461June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID57:0
June 18, 2012462
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x00ROPID67:0
463June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x00ROPID77:0
June 18, 2012464
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
Type RO, reset 0x0000.0022
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
0100010000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x22ROPID07:0
465June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID17:0
June 18, 2012466
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
0x18ROPID27:0
467June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
0x01ROPID37:0
June 18, 2012468
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
0x0DROCID07:0
469June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
0xF0ROCID17:0
June 18, 2012470
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
0x05ROCID27:0
471June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
0xB1ROCID37:0
June 18, 2012472
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
13 Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S6950 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
The Stellaris®I2C interface has the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both sending and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been sent or requested by a master
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
473June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
13.1 Block Diagram
Figure 13-1. I2C Block Diagram
I2C I/O Select
I2C Master Core
Interrupt
I2C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICRI2CMMIS
I2C Control
13.2 Signal Description
Table 13-1 on page 474 and Table 13-2 on page 474 list the external signals of the I2C interface and
describe the function of each. The I2C interface signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which
default to the I2C function. The column in the table below titled "Pin Assignment" lists the possible
GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 306) should be set to choose the I2C function. Note that the I2C pins
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284.
Table 13-1. I2C Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
I2C module 0 clock.ODI/O70I2C0SCL
I2C module 0 data.ODI/O71I2C0SDA
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 13-2. I2C Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
I2C module 0 clock.ODI/OC11I2C0SCL
I2C module 0 data.ODI/OC12I2C0SDA
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3 Functional Description
The I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 13-2 on page 475.
See “Inter-Integrated Circuit (I2C) Interface” on page 672 for I2C timing diagrams.
June 18, 2012474
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Figure 13-2. I2C Bus Configuration
RPUP
StellarisTM
I2CSCL I2CSDA
RPUP
3rd Party Device
with I2C Interface
SCL SDA
I2
C Bus
SCL
SDA
3rd Party Device
with I2C Interface
SCL SDA
13.3.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 475) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
13.3.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
13-3 on page 475.
Figure 13-3. START and STOP Conditions
START
condition
SD
A
SCL
STOP
condition
SD
A
SCL
13.3.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 13-4 on page 476. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
475June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 13-4. Complete Data Transfer with a 7-Bit Address
DataSlave address
ACKLSBMSBACKR/SLSBMSB
SD
A
SCL 1 2 7 8 9 1 2 7 8 9
The first seven bits of the first byte make up the slave address (see Figure 13-5 on page 476). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 13-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
13.3.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 13-6 on page 476).
Figure 13-6. Data Validity During Bit Transfer on the I2C Bus
Change
of data
allowed
Data line
stable
SDA
SCL
13.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 476.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
13.3.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
June 18, 2012476
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
13.3.2 Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD,TIMER_PRD,SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 495).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 13-3 on page 477 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 13-3. Examples of I2C Master Timer Period versus Speed Mode
Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
--100 Kbps0x014 MHz
--100 Kbps0x026 MHz
312 Kbps0x0189 Kbps0x0612.5 MHz
278 Kbps0x0293 Kbps0x0816.7 MHz
333 Kbps0x02100 Kbps0x0920 MHz
312 Kbps0x0396.2 Kbps0x0C25 MHz
330 Kbps0x0497.1 Kbps0x1033 MHz
400 Kbps0x04100 Kbps0x1340 MHz
357 Kbps0x06100 Kbps0x1850 MHz
477June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
13.3.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
13.3.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C
master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I2C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
13.3.3.2 I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register.
Software determines whether the module should write (transmit) or read (receive) data from the I2C
Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit
in the I2C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
13.3.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
13.3.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
June 18, 2012478
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
13.3.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
479June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 13-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0?
NO
Write ---0-111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
June 18, 2012480
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Figure 13-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0?
NO
Write ---00111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
481June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 13-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011 to
I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
ARBLST bit=1?
Write data to
I2CMDR
Write ---0-100 to
I2CMCS
Index=n?
NO
Error Service
Idle
YES
Write ---0-001 to
I2CMCS
Write ---0-101 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
June 18, 2012482
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Figure 13-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0?
NO
Write ---01011 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0? NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100 to
I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101 to
I2CMCS
YES
Idle
Read data from
I2CMDR
Error Service
ERROR bit=0?
YES
Write ---01001 to
I2CMCS
Read I2CMCS
BUSY bit=0? NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
483June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 13-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
June 18, 2012484
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Figure 13-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
13.3.5.2 I2C Slave Command Sequences
Figure 13-13 on page 486 presents the command sequence available for the I2C slave.
485June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 13-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1? NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
13.4 Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
June 18, 2012486
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
13.5 Register Map
Table 13-4 on page 487 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C 0: 0x4002.0000
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 218). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
The hw_i2c.h file in the StellarisWare®Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare
uses an offset between 0x000 and 0x018 with the slave base address.
Table 13-4. Inter-Integrated Circuit (I2C) Interface Register Map
See
page
DescriptionResetTypeNameOffset
I2C Master
489I2C Master Slave Address0x0000.0000R/WI2CMSA0x000
490I2C Master Control/Status0x0000.0000R/WI2CMCS0x004
494I2C Master Data0x0000.0000R/WI2CMDR0x008
495I2C Master Timer Period0x0000.0001R/WI2CMTPR0x00C
496I2C Master Interrupt Mask0x0000.0000R/WI2CMIMR0x010
497I2C Master Raw Interrupt Status0x0000.0000ROI2CMRIS0x014
498I2C Master Masked Interrupt Status0x0000.0000ROI2CMMIS0x018
499I2C Master Interrupt Clear0x0000.0000WOI2CMICR0x01C
500I2C Master Configuration0x0000.0000R/WI2CMCR0x020
487June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 13-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
See
page
DescriptionResetTypeNameOffset
I2C Slave
502I2C Slave Own Address0x0000.0000R/WI2CSOAR0x800
503I2C Slave Control/Status0x0000.0000ROI2CSCSR0x804
505I2C Slave Data0x0000.0000R/WI2CSDR0x808
506I2C Slave Interrupt Mask0x0000.0000R/WI2CSIMR0x80C
507I2C Slave Raw Interrupt Status0x0000.0000ROI2CSRIS0x810
508I2C Slave Masked Interrupt Status0x0000.0000ROI2CSMIS0x814
509I2C Slave Interrupt Clear0x0000.0000WOI2CSICR0x818
13.6 Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 501.
June 18, 2012488
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R/SSAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0R/WSA7:1
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
DescriptionValue
Send.0
Receive.1
0R/WR/S0
489June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN,START,STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Reads
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BUSYERRORADRACKDATACKARBLSTIDLEBUSBSYreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:7
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
0ROBUSBSY6
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
0ROIDLE5
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
0ROARBLST4
June 18, 2012490
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
DescriptionResetTypeNameBit/Field
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
0RODATACK3
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
0ROADRACK2
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
0ROERROR1
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0ROBUSY0
Writes
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
RUNSTARTSTOPACKreserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00WOreserved31:4
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 13-5 on page 492.
0WOACK3
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 13-5 on page 492.
0WOSTOP2
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 13-5 on page 492.
0WOSTART1
491June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 13-5 on page 492.
0WORUN0
Table 13-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Description
I2CMCS[3:0]I2CMSA[0]
Current
State RUNSTARTSTOPACKR/S
START condition followed by SEND (master goes to the
Master Transmit state).
110Xa
0
Idle
START condition followed by a SEND and STOP
condition (master remains in Idle state).
111X0
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
11001
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
11101
START condition followed by RECEIVE (master goes
to the Master Receive state).
11011
Illegal.11111
NOP.All other combinations not listed are non-operations.
SEND operation (master remains in Master Transmit
state).
100XX
Master
Transmit
STOP condition (master goes to Idle state).001XX
SEND followed by STOP condition (master goes to Idle
state).
101XX
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
110X0
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
111X0
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
11001
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
11101
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
11011
Illegal.11111
NOP.All other combinations not listed are non-operations.
June 18, 2012492
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Table 13-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued)
Description
I2CMCS[3:0]I2CMSA[0]
Current
State RUNSTARTSTOPACKR/S
RECEIVE operation with negative ACK (master remains
in Master Receive state).
1000X
Master
Receive
STOP condition (master goes to Idle state).b
001XX
RECEIVE followed by STOP condition (master goes to
Idle state).
1010X
RECEIVE operation (master remains in Master Receive
state).
1001X
Illegal.1011X
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
11001
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
11101
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
11011
Repeated START condition followed by SEND (master
goes to Master Transmit state).
110X0
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
111X0
NOP.All other combinations not listed are non-operations.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
493June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Data Transferred
Data transferred during transaction.
0x00R/WDATA7:0
June 18, 2012494
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TPRreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:7
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
0x1R/WTPR6:0
495June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0R/WIM0
June 18, 2012496
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
0RORIS0
497June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0ROMIS0
June 18, 2012498
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ICreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0WOIC0
499June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LPBKreservedMFESFEreserved
R/WROROROR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
0R/WSFE5
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
0R/WMFE4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved3:1
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
0R/WLPBK0
June 18, 2012500
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800
This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C 0 base: 0x4002.0000
Offset 0x800
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
OARreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:7
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
0x00R/WOAR6:0
June 18, 2012502
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR,RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and
receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that
the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the
I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into
the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I2C slave operation.
Reads
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
Offset 0x804
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RREQTREQFBRreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0ROFBR2
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
0ROTREQ1
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0RORREQ0
503June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Writes
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
Offset 0x804
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DAreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Device Active
DescriptionValue
Disables the I2C slave operation.0
Enables the I2C slave operation.1
Once this bit has been set, it should not be set again unless it has been
cleared by writing a 0 or by a reset, otherwise transfer failures may
occur.
0WODA0
June 18, 2012504
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 12: I2C Slave Data (I2CSDR), offset 0x808
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C 0 base: 0x4002.0000
Offset 0x808
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
0x0R/WDATA7:0
505June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
Offset 0x80C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAIMreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
0R/WDATAIM0
June 18, 2012506
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
Offset 0x810
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATARISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Data Raw Interrupt Status
This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I2C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.
0RODATARIS0
507June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
Offset 0x814
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Data Masked Interrupt Status
This bit specifies the interrupt state for data received and data requested
(after masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
0RODATAMIS0
June 18, 2012508
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C 0 base: 0x4002.0000
Offset 0x818
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAICreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Data Interrupt Clear
This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.
0WODATAIC0
509June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
14 Ethernet Controller
The Stellaris®Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface. The Ethernet Controller conforms to IEEE 802.3 specifications
and fully supports 10BASE-T and 100BASE-TX standards.
The Stellaris Ethernet Controller module has the following features:
■Conforms to the IEEE 802.3-2002 specification
–10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– Automatic MDI/MDI-X cross-over correction
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
■ IEEE 1588 Precision Time Protocol - provides highly accurate time stamps for individual packets
14.1 Block Diagram
As shown in Figure 14-1 on page 511, the Ethernet Controller is functionally divided into two layers:
the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers
correspond to the OSI model layers 2 and 1. The CPU accesses the Ethernet Controller via the
MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC
layer also provides the interface to the PHY layer via an internal Media Independent Interface (MII).
The PHY layer communicates with the Ethernet bus.
June 18, 2012510
Texas Instruments-Production Data
Ethernet Controller
Figure 14-1. Ethernet Controller
ARM Cortex M3
Ethernet Controller
Media
Access
Controller
Physical
Layer Entity
MAC
(Layer 2)
PHY
(Layer 1)
RJ45
Magnetics
Figure 14-2 on page 511 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 14-2. Ethernet Controller Block Diagram
MACRIS
MACIACK
MACIM
Interrupt
Control
MACRCTL
MACNP
Receive
Control
MACTCTL
MACTHR
MACTR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIA0
MACIA1
Individual
Address
MACMCTL
MACMDV
MII
Control
MACDDATA
Data
Access
TXOP
TXON
RXIP
RXIN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect
XTALNPHY
XTALPPHY
LED0
LED1
MACMTXD
MACMRXD
Interrupt
MACTS
Timer
Support
14.2 Signal Description
Table 14-1 on page 512 and Table 14-2 on page 512 list the external signals of the Ethernet Controller
and describe the function of each. The Ethernet LED signals are alternate functions for GPIO signals
and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists
the GPIO pin placement for the LED signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 306) should be set to choose the LED function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284. The remaining
signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment
and function.
511June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 14-1. Ethernet Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
AnalogI41ERBIAS
GND of the Ethernet PHY.Power-42
85
86
GNDPHY
Ethernet LED 0.TTLO59LED0
Ethernet LED 1.TTLO60LED1
MDIO of the Ethernet PHY.TTLI/O58MDIO
RXIN of the Ethernet PHY.AnalogI37RXIN
RXIP of the Ethernet PHY.AnalogI40RXIP
TXON of the Ethernet PHY.AnalogO46TXON
TXOP of the Ethernet PHY.AnalogO43TXOP
VCC of the Ethernet PHY.Power-36
83
84
VCCPHY
Ethernet PHY XTALN 25-MHz oscillator crystal output.
Connect this pin to ground when using a single-ended 25-MHz
clock input connected to the XTALPPHY pin.
TTLO17XTALNPHY
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
TTLI16XTALPPHY
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 14-2. Ethernet Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
AnalogIK3ERBIAS
GND of the Ethernet PHY.Power-C8
C9
K4
GNDPHY
Ethernet LED 0.TTLOJ12LED0
Ethernet LED 1.TTLOJ11LED1
MDIO of the Ethernet PHY.TTLI/OL9MDIO
RXIN of the Ethernet PHY.AnalogIL7RXIN
RXIP of the Ethernet PHY.AnalogIM7RXIP
TXON of the Ethernet PHY.AnalogOL8TXON
TXOP of the Ethernet PHY.AnalogOM8TXOP
VCC of the Ethernet PHY.Power-C10
D10
D11
VCCPHY
Ethernet PHY XTALN 25-MHz oscillator crystal output.
Connect this pin to ground when using a single-ended 25-MHz
clock input connected to the XTALPPHY pin.
TTLOJ1XTALNPHY
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
TTLIJ2XTALPPHY
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 18, 2012512
Texas Instruments-Production Data
Ethernet Controller
14.3 Functional Description
Note: A 12.4-kΩ resistor should be connected between the ERBIAS and ground. The 12.4-kΩ
resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS
pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used.
The functional description of the Ethernet Controller is discussed in the following sections.
14.3.1 MAC Operation
The following sections decribe the operation of the MAC unit, including an overview of the Ethernet
frame format, the MAC layer FIFOs, Ethernet transmission and reception options, packet timestamps,
and LED indicators.
14.3.1.1 Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
14-3 on page 513.
Figure 14-3. Ethernet Frame
Preamble SFD Destination Address Source Address Length/
Type FCSData
7
Bytes
6
Bytes
6
Bytes
2
Bytes
1
Byte
4
Bytes
46 - 1500
Bytes
The seven fields of the frame are transmitted from left to right. The bits within the frame are
transmitted from least to most significant bit.
■ Preamble
The Preamble field is used to synchronize with the received frame’s timing. The preamble is 7
octets long.
■ Start Frame Delimiter (SFD)
The SFD field follows the preamble pattern and indicates the start of the frame. Its value is
1010.1011.
■ Destination Address (DA)
This field specifies destination addresses for which the frame is intended. The LSB (bit 16 of DA
oct 1 in the frame, see Table 14-3 on page 515) of the DA determines whether the address is an
individual (0), or group/multicast (1) address.
■ Source Address (SA)
The source address field identifies the station from which the frame was initiated.
■ Length/Type Field
The meaning of this field depends on its numeric value. This field can be interpreted as length
or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type
field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If
the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The
meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified
by the IEEE 802.3 standard. However, the Ethernet Controller assumes type interpretation if the
513June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
value of the Length/Type field is greater than 1500 decimal. The definition of the Type field is
specified in the IEEE 802.3 standard. The first of the two octets in this field is most significant.
■ Data
The data field is a sequence of octets that is at least 46 in length, up to 1500 in length. Full data
transparency is provided so any values can appear in this field. A minimum frame size of 46
octets is required to meet the IEEE standard. If the frame size is too small, the Ethernet Controller
automatically appends extra bits (a pad), thus the pad can have a size of 0 to 46 octets. Data
padding can be disabled by clearing the PADEN bit in the Ethernet MAC Transmit Control
(MACTCTL) register.
For the Ethernet Controller, data sent/received can be larger than 1500 bytes without causing
a Frame Too Long error. Instead, a FIFO overrun error is reported using the FOV bit in the
Ethernet MAC Raw Interrupt Status(MACRIS) register when the frame received is too large
to fit into the Ethernet Controller’s 2K RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The CRC is
computed over the destination address, source address, length/type, and data (including pad)
fields using the CRC-32 algorithm. The Ethernet Controller computes the FCS value one nibble
at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless
disabled by clearing the CRC bit in the MACTCTL register. For received frames, this field is
automatically checked. If the FCS does not pass, the frame is not placed in the RX FIFO, unless
the FCS check is disabled by clearing the BADCRC bit in the MACRCTL register.
14.3.1.2 MAC Layer FIFOs
The Ethernet Controller is capable of simultaneous transmission and reception. This feature is
enabled by setting the DUPLEX bit in the MACTCTL register.
For Ethernet frame transmission, a 2 KB transmit FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes (as the first 16 bytes in the FIFO are reserved for destination address, source
address and length/type information).
For Ethernet frame reception, a 2-KB receive FIFO is provided that can be used to store multiple
frames, up to a maximum of 31 frames. If a frame is received, and there is insufficient space in the
RX FIFO, an overflow error is indicated using the FOV bit in the MACRIS register.
For details regarding the TX and RX FIFO layout, refer to Table 14-3 on page 515. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the Length/Type bytes and the FCS bits.
If FCS generation is disabled by clearing the CRC bit in the MACTCTL register, the last word in the
TX FIFO must contain the FCS bytes for the frame that has been written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not be
aligned on a word boundary in the FIFO. However, for the RX FIFO the beginning of the next frame
is always on a word boundary.
June 18, 2012514
Texas Instruments-Production Data
Ethernet Controller
Table 14-3. TX & RX FIFO Organization
RX FIFO (Read)TX FIFO (Write)Word Bit FieldsFIFO Word Read/Write
Sequence
Frame Length Least
Significant Byte
Data Length Least Significant
Byte
7:01st
Frame Length Most Significant
Byte
Data Length Most Significant
Byte
15:8
DA oct 123:16
DA oct 231:24
DA oct 37:02nd
DA oct 415:8
DA oct 523:16
DA oct 631:24
SA oct 17:03rd
SA oct 215:8
SA oct 323:16
SA oct 431:24
SA oct 57:04th
SA oct 615:8
Len/Type Most Significant Byte23:16
Len/Type Least Significant Byte31:24
data oct n7:05th to nth
data oct n+115:8
data oct n+223:16
data oct n+331:24
FCS 17:0last
FCS 215:8
FCS 323:16
FCS 431:24
Note: If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the
correct CRC. If the CRC bit is set, the Ethernet Controller automatically writes the FCS bytes.
14.3.1.3 Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at
the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test
purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing
the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded
into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is
set. This feature can be disabled by clearing the PADEN bit.
The transmitter must be enabled by setting the TXEN bit in the TCTL register.
515June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
14.3.1.4 Ethernet Reception Options
The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should
first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL)
register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register.
The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case,
a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the
BADCRC bit in the MACRCTL register.
In normal operating mode, the receiver accepts only those frames that have a destination address
that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0)
and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can
also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the
MACRCTL register.
14.3.1.5 Packet Timestamps
For applications requiring very high-precision synchronization packets, the Ethernet Controller
provides a means of generating precision timestamps in support of the IEEE Precision Time Protocol
(IEEE-1588). This feature is enabled by setting the TSEN bit in the Ethernet MAC Timer Support
(MATCS) register. Note that when this feature is enabled, General-Purpose Timer 3 (GPT3) must
be dedicated to the Ethernet Controller. GPT3 must be configured to 16-bit edge capture mode,
see page 345. Timer A of GPT3 stores the transmit time, and Timer B stores the receive time. One
other General-Purpose Timer can be set up as a 16-bit free-running timer to synchronize the receiver
and transmitter timers and provide a timestamp with which to compare the timestamps stored in
GPT3.
14.3.2 Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer auto-negotiates the link parameters by default.
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider
(MACMDV) register contains the divider used for scaling down the system clock. See page 535 for
more details about the use of this register.
14.3.3 PHY Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
14.3.3.1 Clock Selection
The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external
oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY
June 18, 2012516
Texas Instruments-Production Data
Ethernet Controller
and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY
pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
14.3.3.2 Auto-Negotiation
The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3
standard for 10/100 Mbps operation over copper wiring. This function is controlled via register
settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet
PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the
auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management
Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link
partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the Ethernet PHY Management
Register 18 - Diagnostic (MR18) register reflect the actual speed and duplex condition. If
auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects
this and auto-negotiation restarts from the beginning. Setting the RANEG bit in the MR0 register also
causes auto-negotiation to restart.
14.3.3.3 Polarity Correction
The Ethernet Controller is capable of either automatic or manual polarity reversal for 10BASE-T
and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the Ethernet PHY Management
Register 16 - Vendor-Specific (MR16) control this feature. The default is automatic mode, where
APOL is clear and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter
manual mode, APOL should be set. In manual mode RVSPOL controls the signal polarity.
14.3.3.4 MDI/MDI-X Configuration
The Ethernet Controller supports the MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. The MDI/MDI-X configuration eliminates the need for cross-over cables when connecting
to another device, such as a hub. The algorithm is controlled via settings in the Ethernet PHY
Management Register 24 - MDI/MIDIX Control (MR24). Refer to page 558 for additional details
about these settings.
14.3.3.5 Power Management
The PHY has two power-saving modes:
■ Power-Down
■ Receive Power Management
Power-down mode is activated by setting the PWRDN bit in the MR0 register. When the PHY is in
power-down mode, it consumes minimum power. While in the power-down state, the Ethernet
Controller still responds to management transactions.
Receive power management (RXCC mode) is activated by setting the RXCC bit in the MR16 register.
In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all
other receive circuitry are powered down. As soon as a valid signal is detected, all circuits are
automatically powered up to resume normal operation. Note that the RXCC mode is not supported
during 10BASE-T operation.
517June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
14.3.3.6 LED Indicators
The Ethernet Controller supports two LED signals that can be used to indicate various states of
operation. These signals are mapped to the LED0 and LED1 pins. By default, these pins are
configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be
reconfigured to their alternate function. See “General-Purpose Input/Outputs (GPIOs)” on page 284
for additional details. The function of these pins is programmable via the PHY layer Ethernet PHY
Management Register 23 - LED Configuration (MR23). Refer to page 557 for additional details on
how to program these LED functions.
14.3.4 Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with inadequate room in the RX FIFO (overrun)
■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
14.4 Initialization and Configuration
The following sections describe the hardware and software configuration required to set up the
Ethernet Controller.
14.4.1 Hardware Configuration
Figure 14-4 on page 519 shows the proper method for interfacing the Ethernet Controller to a
10/100BASE-T Ethernet jack.
June 18, 2012518
Texas Instruments-Production Data
Ethernet Controller
Figure 14-4. Interface to an Ethernet Jack
6
5
8
4
2
3
1
7
1CT: 1
TX+
TX-
RX+
RX-
1CT: 1
Y+
Y-
G+
G-
3
8
7
4
5
6
11
12
2
1
GL
GR
9
10
NC
GND
P2
J3011G21DNL
R5
49.9
+3.3V
C13
0.01UF
R4
49.9
R8
49.9
R9
49.9
C4
0.1UF
+3.3V
C5
0.1UF
+3.3V
C7
10pF
C2
10pF
C3
10pF
R6
330
R3
10K
+3.3V
R7
330
+3.3V
+3.3V
PF2/LED1
PF3/LED0
C6
10pF
10/100BASE-T Ethernet Jack
+3.3V
PF2/LED1 60
PF3/LED0 59
MDIO 58
TXON 46
TXOP 43
RXIP 40
RXIN 37
Stellaris
Microcontroller
The following isolation transformers have been tested and are known to successfully interface to
the Ethernet PHY layer.
■ Isolation Transformers
– TDK TLA-6T103
– Bel-Fuse S558-5999-46
– Halo TG22-3506ND
– Pulse PE-68515
– Valor ST6118
– YCL 20PMT04
■ Isolation transformers in low profile packages (0.100 in/2.5 mm or less)
– TDK TLA-6T118
– Halo TG110-S050
– PCA EPF8023G
■ Isolation transformers with integrated RJ45 connector
– TDK TLA-6T704
– Delta RJS-1A08T089A
■ Isolation transformers with integrated RJ45 connector, LEDs and termination resistors
– Pulse J0011D21B/E
– Pulse J3011G21DNL
14.4.2 Software Configuration
To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the
RCGC2 register (see page 227). The following steps can then be used to configure the Ethernet
Controller for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value should be 0x03 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
519June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
14.5 Ethernet Register Map
Table 14-4 on page 520 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000. Note that the Ethernet module clock must be enabled
before the registers can be programmed (see page 227). There must be a delay of 3 system clocks
after the Ethernet module clock is enabled before any Ethernet module registers are accessed.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 14-4 on page 520 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation. Vendor-specific registers not listed are reserved.
Table 14-4. Ethernet Register Map
See
page
DescriptionResetTypeNameOffset
Ethernet MAC
522Ethernet MAC Raw Interrupt Status/Acknowledge0x0000.0000R/W1CMACRIS/MACIACK0x000
525Ethernet MAC Interrupt Mask0x0000.007FR/WMACIM0x004
526Ethernet MAC Receive Control0x0000.0008R/WMACRCTL0x008
527Ethernet MAC Transmit Control0x0000.0000R/WMACTCTL0x00C
528Ethernet MAC Data0x0000.0000R/WMACDATA0x010
530Ethernet MAC Individual Address 00x0000.0000R/WMACIA00x014
531Ethernet MAC Individual Address 10x0000.0000R/WMACIA10x018
532Ethernet MAC Threshold0x0000.003FR/WMACTHR0x01C
534Ethernet MAC Management Control0x0000.0000R/WMACMCTL0x020
June 18, 2012520
Texas Instruments-Production Data
Ethernet Controller
Table 14-4. Ethernet Register Map (continued)
See
page
DescriptionResetTypeNameOffset
535Ethernet MAC Management Divider0x0000.0080R/WMACMDV0x024
536Ethernet MAC Management Transmit Data0x0000.0000R/WMACMTXD0x02C
537Ethernet MAC Management Receive Data0x0000.0000R/WMACMRXD0x030
538Ethernet MAC Number of Packets0x0000.0000ROMACNP0x034
539Ethernet MAC Transmission Request0x0000.0000R/WMACTR0x038
540Ethernet MAC Timer Support0x0000.0000R/WMACTS0x03C
MII Management
541Ethernet PHY Management Register 0 – Control0x3100R/WMR0-
543Ethernet PHY Management Register 1 – Status0x7849ROMR1-
545
Ethernet PHY Management Register 2 – PHY Identifier
1
0x000EROMR2-
546
Ethernet PHY Management Register 3 – PHY Identifier
2
0x7237ROMR3-
547
Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement
0x01E1R/WMR4-
549
Ethernet PHY Management Register 5 – Auto-Negotiation
Link Partner Base Page Ability
0x0000ROMR5-
550
Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion
0x0000ROMR6-
551
Ethernet PHY Management Register 16 –
Vendor-Specific
0x0140R/WMR16-
553
Ethernet PHY Management Register 17 – Interrupt
Control/Status
0x0000R/WMR17-
555Ethernet PHY Management Register 18 – Diagnostic0x0000ROMR18-
556
Ethernet PHY Management Register 19 – Transceiver
Control
0x4000R/WMR19-
557
Ethernet PHY Management Register 23 – LED
Configuration
0x0010R/WMR23-
558
Ethernet PHY Management Register 24 –MDI/MDIX
Control
0x00C0R/WMR24-
14.6 Ethernet MAC Register Descriptions
The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by
address offset. Also see “MII Management Register Descriptions” on page 540.
521June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge
(MACRIS/MACIACK), offset 0x000
The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this
register gives the current status value of the corresponding interrupt prior to masking. On a write,
setting any bit clears the corresponding interrupt status bit.
Reads
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTTXERTXEMPFOVRXERMDINTPHYINTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:7
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occurred. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
0ROPHYINT6
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
0ROMDINT5
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
0RORXER4
FIFO Overrun
When set, indicates that an overrun was encountered on the receive
FIFO.
0ROFOV3
June 18, 2012522
Texas Instruments-Production Data
Ethernet Controller
DescriptionResetTypeNameBit/Field
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
0ROTXEMP2
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
■ The data length field stored in the TX FIFO exceeds 2032 decimal
(buffer length - 16 bytes of header data). The frame is not sent when
this error occurs.
■ The retransmission attempts during the backoff process have
exceeded the maximum limit of 16 decimal.
0ROTXER1
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
0RORXINT0
Writes
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTTXERTXEMPFOVRXERMDINTPHYINTreserved
W1CW1CW1CW1CW1CW1CW1CROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:7
Clear PHY Interrupt
Setting this bit clears the PHYINT interrupt in the MACRIS register.
0W1CPHYINT6
Clear MII Transaction Complete
Setting this bit clears the MDINT interrupt in the MACRIS register.
0W1CMDINT5
Clear Receive Error
Setting this bit clears the RXER interrupt in the MACRIS register.
0W1CRXER4
Clear FIFO Overrun
Setting this bit clears the FOV interrupt in the MACRIS register.
0W1CFOV3
523June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Clear Transmit FIFO Empty
Setting this bit clears the TXEMP interrupt in the MACRIS register.
0W1CTXEMP2
Clear Transmit Error
Setting this bit clears the TXER interrupt in the MACRIS register and
resets the TX FIFO write pointer.
0W1CTXER1
Clear Packet Received
Setting this bit clears the RXINT interrupt in the MACRIS register.
0W1CRXINT0
June 18, 2012524
Texas Instruments-Production Data
Ethernet Controller
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the
interrupt, while setting the bit enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTMTXERMTXEMPMFOVMRXERMMDINTMPHYINTMreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
1111111000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:7
Mask PHY Interrupt
Clearing this bit masks the PHYINT bit in the MACRIS register from
being set.
1R/WPHYINTM6
Mask MII Transaction Complete
Clearing this bit masks the MDINT bit in the MACRIS register from being
set.
1R/WMDINTM5
Mask Receive Error
Clearing this bit masks the RXER bit in the MACRIS register from being
set.
1R/WRXERM4
Mask FIFO Overrun
Clearing this bit masks the FOV bit in the MACRIS register from being
set.
1R/WFOVM3
Mask Transmit FIFO Empty
Clearing this bit masks the TXEMP bit in the MACRIS register from being
set.
1R/WTXEMPM2
Mask Transmit Error
Clearing this bit masks the TXER bit in the MACRIS register from being
set.
1R/WTXERM1
Mask Packet Received
Clearing this bit masks the RXINT bit in the MACRIS register from being
set.
1R/WRXINTM0
525June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register configures the receiver and controls the types of frames that are received.
It is important to note that when the receiver is enabled, all valid frames with a broadcast address
of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO,
even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXENAMULPRMSBADCRCRSTFIFOreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:5
Clear Receive FIFO
When set, this bit clears the receive FIFO. This should be done when
software initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), before a
reset is initiated (RSTFIFO = 1). This sequence flushes and resets the
RX FIFO.
This bit is automatically cleared when read.
0R/WRSTFIFO4
Enable Reject Bad CRC
When set, the BADCRC bit enables the rejection of frames with an
incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit
in the MACRIS register is set and the receiver FIFO is reset.
1R/WBADCRC3
Enable Promiscuous Mode
When set, the PRMS bit enables Promiscuous mode, which accepts all
valid frames, regardless of the specified Destination Address.
0R/WPRMS2
Enable Multicast Frames
When set, the AMUL bit enables the reception of multicast frames.
0R/WAMUL1
Enable Receiver
When set the RXEN bit enables the Ethernet receiver. When this bit is
clear, the receiver is disabled and all frames are ignored.
0R/WRXEN0
June 18, 2012526
Texas Instruments-Production Data
Ethernet Controller
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register configures the transmitter and controls the frames that are transmitted.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TXENPADENCRC
reserved
DUPLEXreserved
R/WR/WR/WROR/WROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:5
Enable Duplex Mode
When set, this bit enables Duplex mode, allowing simultaneous
transmission and reception.
0R/WDUPLEX4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Enable CRC Generation
When set this bit enables the automatic generation of the CRC and its
placement at the end of the packet. If this bit is clear, the frames placed
in the TX FIFO are sent exactly as they are written into the FIFO.
Note that this bit should generally be set.
0R/WCRC2
Enable Packet Padding
When set, this bit enables the automatic padding of packets that do not
meet the minimum frame size.
Note that this bit should generally be set.
0R/WPADEN1
Enable Transmitter
When set, this bit enables the transmitter. When this bit is clear, the
transmitter is disabled.
0R/WTXEN0
527June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: Ethernet MAC Data (MACDATA), offset 0x010
Important: This register is read-sensitive. See the register description for details.
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer. The read pointer is then auto incremented to the next RX FIFO location. Reading from
the RX FIFO when a frame has not been received or is in the process of being received will return
indeterminate data and not increment the read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is the auto incremented to the next TX FIFO location. Writing more data into the
TX FIFO than indicated in the length field will result in the data being lost. Writing less data into the
TX FIFO than indicated in the length field will result in indeterminate data being appended to the
end of the frame to achieve the indicated length. Attempting to write the next frame into the TX FIFO
before transmission of the first has completed will result in the data being lost.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
Reads
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
16171819202122232425262728293031
RXDATA
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXDATA
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Receive FIFO Data
The RXDATA bits represent the next word of data stored in the RX FIFO.
0x0000.0000RORXDATA31:0
June 18, 2012528
Texas Instruments-Production Data
Ethernet Controller
Writes
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
16171819202122232425262728293031
TXDATA
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
TXDATA
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Transmit FIFO Data
The TXDATA bits represent the next word of data to place in the TX
FIFO for transmission.
0x0000.0000WOTXDATA31:0
529June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014
This register enables software to program the first four bytes of the hardware MAC address of the
Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte Individual Address
is compared against the incoming Destination Address fields to determine whether the frame should
be received.
Ethernet MAC Individual Address 0 (MACIA0)
Base 0x4004.8000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
MACOCT3MACOCT4
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
MACOCT1MACOCT2
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
MAC Address Octet 4
The MACOCT4 bits represent the fourth octet of the MAC address used
to uniquely identify the Ethernet Controller.
0x00R/WMACOCT431:24
MAC Address Octet 3
The MACOCT3 bits represent the third octet of the MAC address used
to uniquely identify the Ethernet Controller.
0x00R/WMACOCT323:16
MAC Address Octet 2
The MACOCT2 bits represent the second octet of the MAC address used
to uniquely identify the Ethernet Controller.
0x00R/WMACOCT215:8
MAC Address Octet 1
The MACOCT1 bits represent the first octet of the MAC address used to
uniquely identify the Ethernet Controller.
0x00R/WMACOCT17:0
June 18, 2012530
Texas Instruments-Production Data
Ethernet Controller
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MACOCT5MACOCT6
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
0x00R/WMACOCT615:8
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify the Ethernet Controller.
0x00R/WMACOCT57:0
531June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C
In order to increase the transmission rate, it is possible to program the Ethernet Controller to begin
transmission of the next frame prior to the completion of the transmission of the current frame. Note:
Extreme care must be used when implementing this function. Software must be able to guarantee
that the complete frame is able to be stored in the transmission FIFO prior to the completion of the
transmission frame.
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature
is disabled, and transmission does not start until the NEWTX bit is set in the MACTR register.
Writing the THRESH bits to any value besides 0x3F enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown
below, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame
begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit
field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore,
a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02
makes the wait equal to 68 bytes of written data. In general, early transmission starts when:
Number of Bytes >= 4 (THRESH x8+1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is transmitted. Because under-run checking is not performed, if any event, such as an interrupt,
delays the filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO.
In this event, indeterminate values are transmitted rather than the end of the frame. Therefore,
sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must
be set with an explicit write. This initiates the transmission of the frame even though the threshold
limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the
MACRIS is not set meaning that the CPU receives no indication that a transmit error happened.
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
THRESHreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
1111110000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:6
June 18, 2012532
Texas Instruments-Production Data
Ethernet Controller
DescriptionResetTypeNameBit/Field
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds the value represented by the above
equation, transmission of the packet begins.
0x3FR/WTHRESH5:0
533June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional
description of each of these registers can be found in Table 14-4 on page 520 and in “MII Management
Register Descriptions” on page 540.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
cleared during the same cycle that the START bit is set.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set
during the same cycle that the START bit is set.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
STARTWRITE
reserved
REGADRreserved
R/WR/WROR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction. Refer to
Table 14-4 on page 520 for the PHY register offsets.
Note that any address that is not valid in the register map should not be
written to and any data read should be ignored.
0x0R/WREGADR7:3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation is a write; if
WRITE is clear, the next transaction is a read.
0R/WWRITE1
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When this bit is set, the MII register located at
REGADR is read (WRITE=0) or written (WRITE=1).
0R/WSTART0
June 18, 2012534
Texas Instruments-Production Data
Ethernet Controller
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
The clock divider must be written with a value that ensures that the MDC clock does not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIVreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
Clock Divider
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY layers over the serial MII
interface.
0x80R/WDIV7:0
535June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset
0x02C
This register holds the next value to be written to the MII Management registers.
Ethernet MAC Management Transmit Data (MACMTXD)
Base 0x4004.8000
Offset 0x02C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MDTX
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
MII Register Transmit Data
The MDTX bits represent the data that will be written in the next MII
management transaction.
0x0000R/WMDTX15:0
June 18, 2012536
Texas Instruments-Production Data
Ethernet Controller
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MDRX
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
0x0000R/WMDRX15:0
537June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034
This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there
are no frames in the RX FIFO, and the RXINT bit is clear. When NPR is any other value, at least
one frame is in the RX FIFO, and the RXINT bit in the MACRIS register is set.
Note: The FCS bytes are not included in the NPR value. As a result, the NPR value could be zero
before the FCS bytes are read from the FIFO. In addition, a new packet could be received
before the NPR value reaches zero. To ensure that the entire packet is received, either use
the DriverLib EthernetPacketGet() API or compare the number of bytes received to the
Length field from the frame to determine when the packet has been completely read.
Ethernet MAC Number of Packets (MACNP)
Base 0x4004.8000
Offset 0x034
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
NPRreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:6
Number of Packets in Receive FIFO
The NPR bits represent the number of packets stored in the RX FIFO.
While the NPR field is greater than 0, the RXINT interrupt in the MACRIS
register is set.
0x00RONPR5:0
June 18, 2012538
Texas Instruments-Production Data
Ethernet Controller
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been
encountered, the NEWTX bit is automatically cleared.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
NEWTXreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
0R/WNEWTX0
539June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 15: Ethernet MAC Timer Support (MACTS), offset 0x03C
This register enables software to enable highly precise timing on the transmission and reception of
frames. To enable this function, set the TSEN bit.
Ethernet MAC Timer Support (MACTS)
Base 0x4004.8000
Offset 0x03C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TSENreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
Time Stamp Enable
When set, the TSEN bit multiplexes the TX and RX interrupts to the CCP
inputs of General-Purpose Timer 3.
0R/WTSEN0
14.7 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers. All addresses given
are absolute. Addresses not listed are reserved; these addresses should not be written to and any
data read should be ignored. Also see “Ethernet MAC Register Descriptions” on page 521.
June 18, 2012540
Texas Instruments-Production Data
Ethernet Controller
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY layer. The default settings of
these registers are designed to initialize the Ethernet Controller to a normal operational mode without
configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
0123456789101112131415
reservedCOLTDUPLEXRANEGISOPWRDNANEGENSPEEDSLLOOPBKRESET
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000010001100Reset
DescriptionResetTypeNameBit/Field
Reset Registers
When set, this bit resets the PHY layer registers to their default state
and reinitializes internal state machines. Once the reset operation has
completed, this bit is cleared by hardware.
0R/WRESET15
Loopback Mode
When set, this bit enables the Loopback mode of operation. The receiver
ignores external inputs and receives the data that is transmitted by the
transmitter.
0R/WLOOPBK14
Speed Select
DescriptionValue
Enables the 100 Mb/s mode of operation (100BASE-TX).1
Enables the 10 Mb/s mode of operation (10BASE-T).0
1R/WSPEEDSL13
Auto-Negotiation Enable
When set, this bit enables the auto-negotiation process.
1R/WANEGEN12
Power Down
When set, this bit places the PHY layer into a low-power consuming
state. All data on the data inputs is ignored.
0R/WPWRDN11
Isolate
When set, this bit isolates the transmit and receive data paths and
ignores all data being transmitted and received.
0R/WISO10
Restart Auto-Negotiation
When set, this bit restarts the auto-negotiation process. Once the restart
has initiated, this bit is cleared by hardware.
0R/WRANEG9
541June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Set Duplex Mode
DescriptionValue
Enables the Full-Duplex mode of operation. This bit can be
set by software in a manual configuration process or by the
auto-negotiation process.
1
Enables the Half-Duplex mode of operation.0
1R/WDUPLEX8
Collision Test
When set, this bit enables the Collision Test mode of operation. The
COLT bit is set after the initiation of a transmission and is cleared once
the transmission is halted.
0R/WCOLT7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
These bits should always be written as zero.
0x00R/Wreserved6:0
June 18, 2012542
Texas Instruments-Production Data
Ethernet Controller
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY layer and perform its
initialization and operation appropriately.
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
0123456789101112131415
EXTDJABLINKANEGARFAULTANEGCMFPSreserved10T_H10T_F100X_H100X_F
reserved
RORCRORORCROROROROROROROROROROROType
1001001000011110Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15
100BASE-TX Full-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
supporting 100BASE-TX Full-Duplex mode.
1RO100X_F14
100BASE-TX Half-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
supporting 100BASE-TX Half-Duplex mode.
1RO100X_H13
10BASE-T Full-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
10BASE-T Full-Duplex mode.
1RO10T_F12
10BASE-T Half-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
supporting 10BASE-T Half-Duplex mode.
1RO10T_H11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved10:7
Management Frames with Preamble Suppressed
When set, this bit indicates that the Management Interface is capable
of receiving management frames with the preamble suppressed.
1ROMFPS6
Auto-Negotiation Complete
When set, this bit indicates that the auto-negotiation process has been
completed and that the extended registers defined by the
auto-negotiation protocol are valid.
0ROANEGC5
Remote Fault
When set, this bit indicates that a remote fault condition has been
detected. This bit remains set until it is read, even if the condition no
longer exists.
0RCRFAULT4
Auto-Negotiation
When set, this bit indicates that the Ethernet Controller has the ability
to perform auto-negotiation.
1ROANEGA3
543June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Link Made
When set, this bit indicates that a valid link has been established by the
Ethernet Controller.
0ROLINK2
Jabber Condition
When set, this bit indicates that a jabber condition has been detected
by the Ethernet Controller. This bit remains set until it is read, even if
the jabber condition no longer exists.
0RCJAB1
Extended Capabilities
When set, this bit indicates that the Ethernet Controller provides an
extended set of capabilities that can be accessed through the extended
register set.
1ROEXTD0
June 18, 2012544
Texas Instruments-Production Data
Ethernet Controller
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2),
address 0x02
This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)
Base 0x4004.8000
Address 0x02
Type RO, reset 0x000E
0123456789101112131415
OUI[21:6]
ROROROROROROROROROROROROROROROROType
0111000000000000Reset
DescriptionResetTypeNameBit/Field
Organizationally Unique Identifier[21:6]
This field, along with the OUI[5:0] field in MR3, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
0x000EROOUI[21:6]15:0
545June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3),
address 0x03
This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)
Base 0x4004.8000
Address 0x03
Type RO, reset 0x7237
0123456789101112131415
RNMNOUI[5:0]
ROROROROROROROROROROROROROROROROType
1110110001001110Reset
DescriptionResetTypeNameBit/Field
Organizationally Unique Identifier[5:0]
This field, along with the OUI[21:6] field in MR2, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
0x1CROOUI[5:0]15:10
Model Number
The MN field represents the Model Number of the PHY.
0x23ROMN9:4
Revision Number
The RN field represents the Revision Number of the PHY implementation.
0x7RORN3:0
June 18, 2012546
Texas Instruments-Production Data
Ethernet Controller
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement (MR4), address 0x04
This register provides the advertised abilities of the Ethernet Controller used during auto-negotiation.
Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to
auto-negotiate to an alternate common technology. Writing to this register has no effect until
auto-negotiation is re-initiated by setting the RANEG bit in the MR0 register.
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)
Base 0x4004.8000
Address 0x04
Type R/W, reset 0x01E1
0123456789101112131415
SA0A1A2A3reservedRF
reserved
NP
ROROROROROR/WR/WR/WR/WROROROROR/WROROType
1000011110000000Reset
DescriptionResetTypeNameBit/Field
Next Page
When set, this bit indicates the Ethernet Controller is capable of Next
Page exchanges to provide more detailed information on the PHY layer’s
capabilities.
0RONP15
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved14
Remote Fault
When set, this bit indicates to the link partner that a Remote Fault
condition has been encountered.
0R/WRF13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved12:9
Technology Ability Field[3]
When set, this bit indicates that the Ethernet Controller supports the
100Base-TX full-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register.
1R/WA38
Technology Ability Field[2]
When set, this bit indicates that the Ethernet Controller supports the
100Base-TX half-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register.
1R/WA27
Technology Ability Field[1]
When set, this bit indicates that the Ethernet Controller supports the
10BASE-T full-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register..
1R/WA16
547June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Technology Ability Field[0]
When set, this bit indicates that the Ethernet Controller supports the
10BASE-T half-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register..
1R/WA05
Selector Field
The Sfield encodes 32 possible messages for communicating between
Ethernet Controllers. This field is hard-coded to 0x01, indicating that
the Stellaris Ethernet Controller is IEEE 802.3 compliant.
0x1ROS4:0
June 18, 2012548
Texas Instruments-Production Data
Ethernet Controller
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link
Partner Base Page Ability (MR5), address 0x05
This register provides the advertised abilities of the link partner’s Ethernet Controller that are received
and stored during auto-negotiation.
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Base 0x4004.8000
Address 0x05
Type RO, reset 0x0000
0123456789101112131415
SA[7:0]RFACKNP
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Next Page
When set, this bit indicates that the link partner’s Ethernet Controller is
capable of Next page exchanges to provide more detailed information
on the Ethernet Controller’s capabilities.
0RONP15
Acknowledge
When set, this bit indicates that the Ethernet Controller has successfully
received the link partner’s advertised abilities during auto-negotiation.
0ROACK14
Remote Fault
Used as a standard transport mechanism for transmitting simple fault
information from the link partner.
0RORF13
Technology Ability Field
The A[7:0] field encodes individual technologies that are supported
by the Ethernet Controller. See the MR4 register for definitions. Note
that bits 12:9 describe functions that are not implemented on the Stellaris
Ethernet Controller. Refer to the IEEE 802.3 standard for definitions.
0x00ROA[7:0]12:5
Selector Field
The Sfield encodes possible messages for communicating between
Ethernet Controllers.
DescriptionValue
Reserved0x00
IEEE Std 802.30x01
IEEE Std 802.9 ISLAN-16T0x02
IEEE Std 802.50x03
IEEE Std 13940x04
Reserved0x05–0x1F
0x00ROS4:0
549June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion (MR6), address 0x06
This register enables software to determine the auto-negotiation and next page capabilities of the
Ethernet Controller and the link partner after auto-negotiation.
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)
Base 0x4004.8000
Address 0x06
Type RO, reset 0x0000
0123456789101112131415
LPANEGAPRX
reserved
LPNPAPDFreserved
RORCRORORCROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved15:5
Parallel Detection Fault
When set, this bit indicates that more than one technology has been
detected at link up. This bit is cleared when read.
0RCPDF4
Link Partner is Next Page Able
When set, this bit indicates that the link partner is enabled to support
next page.
0ROLPNPA3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
New Page Received
When set, this bit indicates that a new page has been received from the
link partner and stored. This bit remains set until the register is read.
0RCPRX1
Link Partner is Auto-Negotiation Able
When set, this bit indicates that the link partner is enabled to support
auto-negotiation.
0ROLPANEGA0
June 18, 2012550
Texas Instruments-Production Data
Ethernet Controller
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the Ethernet
Controller.
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
0123456789101112131415
RXCCPCSBPreservedRVSPOLAPOLreservedNL10SQEITXHIM
reserved
INPOLRPTR
R/WR/WROROR/WR/WROROROROR/WR/WR/WROR/W0R/WType
0000001010000000Reset
DescriptionResetTypeNameBit/Field
Repeater Mode
When set, this bit enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity.
0R/WRPTR15
Interrupt Polarity
DescriptionValue
Sets the polarity of the PHY interrupt to be active High.1
Sets the polarity of the PHY interrupt to active Low.0
Important: Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
0R/W0INPOL14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved13
Transmit High Impedance Mode
When set, this bit enables the transmitter High Impedance mode. In this
mode, the TXOP and TXON transmitter pins are put into a high impedance
state. The RXIP and RXIN pins remain fully functional.
0R/WTXHIM12
SQE Inhibit Testing
When set, this bit prohibits 10BASE-T SQE testing.
When clear, the SQE testing is performed by generating a collision pulse
following the completion of the transmission of a frame.
0R/WSQEI11
Natural Loopback Mode
When set, this bit enables the 10BASE-T Natural Loopback mode. In
this mode, the transmission data received by the Ethernet Controller is
looped back onto the receive data path when 10BASE-T mode is
enabled.
0R/WNL1010
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x5ROreserved9:6
551June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Auto-Polarity Disable
When set, this bit disables the Ethernet Controller’s auto-polarity function.
If this bit is clear, the Ethernet Controller automatically inverts the
received signal due to a wrong polarity connection during
auto-negotiation when in 10BASE-T mode.
0R/WAPOL5
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
if RVSPOL is set, it indicates that the receive data is inverted; if RVSPOL
is clear, it indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted; clearing RVSPOL does not invert the receive
data.
0R/WRVSPOL4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
PCS Bypass
When set, this bit enables the bypass of the PCS and
scrambling/descrambling functions in 100BASE-TX mode. This mode
is only valid when auto-negotiation is disabled and 100BASE-TX mode
is enabled.
0R/WPCSBP1
Receive Clock Control
When set, this bit enables the Receive Clock Control power saving mode
if the Ethernet Controller is configured in 100BASE-TX mode. This mode
shuts down the receive clock when no data is being received to save
power. This mode should not be used when PCSBP is enabled and is
automatically disabled when the LOOPBK bit in the MR0 register is set.
0R/WRXCC0
June 18, 2012552
Texas Instruments-Production Data
Ethernet Controller
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events which trigger a PHY layer
interrupt in the MACRIS register. This register can also be used in a polling mode via the Media
Independent Interface as a means to observe key events within the PHY layer via one register
address. Bits 0 through 7 are status bits which are each set based on an event. These bits are
cleared after the register is read. Bits 8 through 15 of this register, when set, enable the corresponding
bit in the lower byte to signal a PHY layer interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
0123456789101112131415
ANEGCOMP_INTRFAULT_INT
LSCHG_INTLPACK_INT
PDF_INTPRX_INT
RXER_INT
JABBER_INTANEGCOMP_IE
RFAULT_IELSCHG_IELPACK_IE
PDF_IEPRX_IERXER_IE
JABBER_IE
RCRCRCRCRCRCRCRCR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Jabber Interrupt Enable
When set, this bit enables system interrupts when a Jabber condition
is detected by the Ethernet Controller.
0R/WJABBER_IE15
Receive Error Interrupt Enable
When set, this bit enables system interrupts when a receive error is
detected by the Ethernet Controller.
0R/WRXER_IE14
Page Received Interrupt Enable
When set, this bit enables system interrupts when a new page is received
by the Ethernet Controller.
0R/WPRX_IE13
Parallel Detection Fault Interrupt Enable
When set, this bit enables system interrupts when a Parallel Detection
Fault is detected by the Ethernet Controller.
0R/WPDF_IE12
LP Acknowledge Interrupt Enable
When set, this bit enables system interrupts when FLP bursts are
received with the ACK bit in the MR5 register during auto-negotiation.
0R/WLPACK_IE11
Link Status Change Interrupt Enable
When set, this bit enables system interrupts when the link status changes
from OK to FAIL.
0R/WLSCHG_IE10
Remote Fault Interrupt Enable
When set, this bit enables system interrupts when a remote fault
condition is signaled by the link partner.
0R/WRFAULT_IE9
Auto-Negotiation Complete Interrupt Enable
When set, this bit enables system interrupts when the auto-negotiation
sequence has completed successfully.
0R/WANEGCOMP_IE8
Jabber Event Interrupt
When set, this bit indicates that a Jabber event has been detected by
the 10BASE-T circuitry.
0RCJABBER_INT7
553June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Receive Error Interrupt
When set, this bit indicates that a receive error has been detected by
the Ethernet Controller.
0RCRXER_INT6
Page Receive Interrupt
When set, this bit indicates that a new page has been received from the
link partner during auto-negotiation.
0RCPRX_INT5
Parallel Detection Fault Interrupt
When set, this bit indicates that a parallel detection fault has been
detected by the Ethernet Controller during the auto-negotiation process.
0RCPDF_INT4
LP Acknowledge Interrupt
When set, this bit indicates that an FLP burst has been received with
the ACK bit set in the MR5 register during auto-negotiation.
0RCLPACK_INT3
Link Status Change Interrupt
When set, this bit indicates that the link status has changed from OK to
FAIL.
0RCLSCHG_INT2
Remote Fault Interrupt
When set, this bit indicates that a remote fault condition has been
signaled by the link partner.
0RCRFAULT_INT1
Auto-Negotiation Complete Interrupt
When set, this bit indicates that the auto-negotiation sequence has
completed successfully.
0RCANEGCOMP_INT0
June 18, 2012554
Texas Instruments-Production Data
Ethernet Controller
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous auto-negotiation.
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
0123456789101112131415
reservedRX_LOCKRXSDRATEDPLXANEGFreserved
RORORORORORORORORORORORORCROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved15:13
Auto-Negotiation Failure
When set, this bit indicates that no common technology was found during
auto-negotiation and auto-negotiation has failed. This bit remains set
until read.
0RCANEGF12
Duplex Mode
When set, this bit indicates that Full-Duplex was the highest common
denominator found during the auto-negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
0RODPLX11
Rate
When set, this bit indicates that 100BASE-TX was the highest common
denominator found during the auto-negotiation process. Otherwise,
10BASE-T was the highest common denominator found.
0RORATE10
Receive Detection
When set, this bit indicates that receive signal detection has occurred
(in 100BASE-TX mode) or that Manchester-encoded data has been
detected (in 10BASE-T mode).
0RORXSD9
Receive PLL Lock
When set, this bit indicates that the Receive PLL has locked onto the
receive signal for the selected speed of operation (10BASE-T or
100BASE-TX).
0RORX_LOCK8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:0
555June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 26: Ethernet PHY Management Register 19 – Transceiver Control
(MR19), address 0x13
This register enables software to set the gain of the transmit output to compensate for transformer
loss.
Ethernet PHY Management Register 19 – Transceiver Control (MR19)
Base 0x4004.8000
Address 0x13
Type R/W, reset 0x4000
0123456789101112131415
reservedTXO
ROROROROROROROROROROROROROROR/WR/WType
0000000000000010Reset
DescriptionResetTypeNameBit/Field
Transmit Amplitude Selection
The TXO field sets the transmit output amplitude to account for transmit
transformer insertion loss.
DescriptionValue
Gain set for 0.0dB of insertion loss0x0
Gain set for 0.4dB of insertion loss0x1
Gain set for 0.8dB of insertion loss0x2
Gain set for 1.2dB of insertion loss0x3
0x1R/WTXO15:14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved13:0
June 18, 2012556
Texas Instruments-Production Data
Ethernet Controller
Register 27: Ethernet PHY Management Register 23 – LED Configuration
(MR23), address 0x17
This register enables software to select the source that causes the LED1 and LED0 signals to toggle.
Ethernet PHY Management Register 23 – LED Configuration (MR23)
Base 0x4004.8000
Address 0x17
Type R/W, reset 0x0010
0123456789101112131415
LED0[3:0]LED1[3:0]reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:8
LED1 Source
The LED1 field selects the source that toggles the LED1 signal.
DescriptionValue
Link OK0x0
RX or TX Activity (Default LED1)0x1
Reserved0x2
Reserved0x3
Reserved0x4
100BASE-TX mode0x5
10BASE-T mode0x6
Full-Duplex0x7
Link OK & Blink=RX or TX Activity0x8
0x1R/WLED1[3:0]7:4
LED0 Source
The LED0 field selects the source that toggles the LED0 signal.
DescriptionValue
Link OK (Default LED0)0x0
RX or TX Activity0x1
Reserved0x2
Reserved0x3
Reserved0x4
100BASE-TX mode0x5
10BASE-T mode0x6
Full-Duplex0x7
Link OK & Blink=RX or TX Activity0x8
0x0R/WLED0[3:0]3:0
557June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
0123456789101112131415
MDIX_SDMDIX_CMMDIXAUTO_SWPD_MODEreserved
R/WR/WR/WR/WROR/WR/WR/WROROROROROROROROType
0000001100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:8
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when auto-negotiation is not enabled.
1R/WPD_MODE7
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
1R/WAUTO_SW6
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
0R/WMDIX5
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
0ROMDIX_CM4
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
0x0R/WMDIX_SD3:0
June 18, 2012558
Texas Instruments-Production Data
Ethernet Controller
15 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
Note: Not all comparators have the option to drive an output pin.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
The Stellaris®Analog Comparators module has the following features:
■ Three independent integrated analog comparators
■ Configurable for output to drive an output pin or generate an interrupt
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of these voltages
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
559June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
15.1 Block Diagram
Figure 15-1. Analog Comparator Module Block Diagram
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
C1-
C1+ output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
C1o
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
C0-
C0o
C2o
Interrupt Control
ACRIS
ACMIS
ACINTEN
interrupt
15.2 Signal Description
Table 15-1 on page 560 and Table 15-2 on page 561 list the external signals of the Analog Comparators
and describe the function of each. The Analog Comparator output signals are alternate functions
for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled
"Pin Assignment" lists the possible GPIO pin placements for the Analog Comparator signals. The
AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set
to choose the Analog Comparator function. The positive and negative input signals are configured
by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284.
Table 15-1. Analog Comparators Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Analog comparator 0 positive input.AnalogI90C0+
Analog comparator 0 negative input.AnalogI92C0-
Analog comparator 0 output.TTLO90C0o
June 18, 2012560
Texas Instruments-Production Data
Analog Comparators
Table 15-1. Analog Comparators Signals (100LQFP) (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Analog comparator 1 positive input.AnalogI24C1+
Analog comparator 1 negative input.AnalogI91C1-
Analog comparator 1 output.TTLO24C1o
Analog comparator 2 positive input.AnalogI23C2+
Analog comparator 2 negative input.AnalogI22C2-
Analog comparator 2 output.TTLO23C2o
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 15-2. Analog Comparators Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Analog comparator 0 positive input.AnalogIA7C0+
Analog comparator 0 negative input.AnalogIA6C0-
Analog comparator 0 output.TTLOA7C0o
Analog comparator 1 positive input.AnalogIM1C1+
Analog comparator 1 negative input.AnalogIB7C1-
Analog comparator 1 output.TTLOM1C1o
Analog comparator 2 positive input.AnalogIM2C2+
Analog comparator 2 negative input.AnalogIL2C2-
Analog comparator 2 output.TTLOM2C2o
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 15-2 on page 562, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
561June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 15-2. Structure of Comparator Unit
output
reference input
ACCTL
IntGen
2
1
0
CINV
interrupt
internal
bus
ACSTAT
(alternate)
+ve input
+ve input
-ve input
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS,ACRIS, and ACINTEN).
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin.
Important: The ASRCP bits in the ACCTLn register must be set before using the analog
comparators.
15.3.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 15-3 on page 562. This is controlled by a
single configuration register (ACREFCTL). Table 15-3 on page 562 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 15-3. Comparator Internal Reference Structure
8R R R
8R
R
•••
••• 0
Decoder
115 14
AVDD
EN
internal
reference
VREF
RNG
Table 15-3. Internal Reference Voltage and ACREFCTL Field Values
Output Reference Voltage Based on VREF Field Value
ACREFCTL Register
RNG Bit ValueEN Bit Value
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and
VREF=0 for the least noisy ground reference.
RNG=XEN=0
June 18, 2012562
Texas Instruments-Production Data
Analog Comparators
Table 15-3. Internal Reference Voltage and ACREFCTL Field Values (continued)
Output Reference Voltage Based on VREF Field Value
ACREFCTL Register
RNG Bit ValueEN Bit Value
Total resistance in ladder is 31 R.
The range of internal reference in this mode is 0.85-2.448 V.
RNG=0
EN=1 Total resistance in ladder is 23 R.
The range of internal reference for this mode is 0-2.152 V.
RNG=1
15.4 Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output by
writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
15.5 Register Map
Table 15-4 on page 564 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
Note that the analog comparator module clock must be enabled before the registers can be
programmed (see page 218). There must be a delay of 3 system clocks after the ADC module clock
is enabled before any ADC module registers are accessed.
563June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 15-4. Analog Comparators Register Map
See
page
DescriptionResetTypeNameOffset
565Analog Comparator Masked Interrupt Status0x0000.0000R/W1CACMIS0x000
566Analog Comparator Raw Interrupt Status0x0000.0000ROACRIS0x004
567Analog Comparator Interrupt Enable0x0000.0000R/WACINTEN0x008
568Analog Comparator Reference Voltage Control0x0000.0000R/WACREFCTL0x010
569Analog Comparator Status 00x0000.0000ROACSTAT00x020
570Analog Comparator Control 00x0000.0000R/WACCTL00x024
569Analog Comparator Status 10x0000.0000ROACSTAT10x040
570Analog Comparator Control 10x0000.0000R/WACCTL10x044
569Analog Comparator Status 20x0000.0000ROACSTAT20x060
570Analog Comparator Control 20x0000.0000R/WACCTL20x064
15.6 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
June 18, 2012564
Texas Instruments-Production Data
Analog Comparators
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1IN2reserved
R/W1CR/W1CR/W1CROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Comparator 2 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0R/W1CIN22
Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0R/W1CIN11
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0R/W1CIN00
565June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1IN2reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Comparator 2 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
2.
0ROIN22
Comparator 1 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
1.
0ROIN11
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
0ROIN00
June 18, 2012566
Texas Instruments-Production Data
Analog Comparators
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1IN2reserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Comparator 2 Interrupt Enable
When set, enables the controller interrupt from the comparator 2 output
0R/WIN22
Comparator 1 Interrupt Enable
When set, enables the controller interrupt from the comparator 1 output.
0R/WIN11
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
0R/WIN00
567June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
VREFreservedRNGENreserved
R/WR/WR/WR/WROROROROR/WR/WROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:10
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
0R/WEN9
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 31 R. If 1, the resistor ladder has a total
resistance of 23 R.
0R/WRNG8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:4
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
15-3 on page 562 for some output reference voltage examples.
0x00R/WVREF3:0
June 18, 2012568
Texas Instruments-Production Data
Analog Comparators
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
OVALreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
0ROOVAL1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
569June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x024
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
CINVISENISLVALreservedASRCPreserved
ROR/WR/WR/WR/WROROROROR/WR/WROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
FunctionValue
Pin value0x0
Pin value of C0+0x1
Internal voltage reference0x2
Reserved0x3
0x00R/WASRCP10:9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved8:5
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
0R/WISLVAL4
June 18, 2012570
Texas Instruments-Production Data
Analog Comparators
DescriptionResetTypeNameBit/Field
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
FunctionValue
Level sense, see ISLVAL0x0
Falling edge0x1
Rising edge0x2
Either edge0x3
0x0R/WISEN3:2
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
0R/WCINV1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
571June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16 Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The Stellaris®PWM module consists of three PWM generator blocks and a control block. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals
(other than being based on the same timer and therefore having the same frequency) or a single
pair of complementary signals with dead-band delays inserted. The output of the PWM generation
blocks are managed by the output control block before being passed to the device pins.
The Stellaris PWM module provides a great deal of flexibility. It can generate simple PWM signals,
such as those required by a simple charge pump. It can also generate paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver. Three generator blocks can
also generate the full six channels of gate controls required by a 3-phase inverter bridge.
Each Stellaris PWM module has the following features:
■ Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM
signal generator, a dead-band generator, and an interrupt selector
■ One fault input in hardware to promote low-latency shutdown
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
–Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
June 18, 2012572
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
■ Flexible output control block with PWM output enable of each PWM signal
– PWM output enable of each PWM signal
– Optional output inversion of each PWM signal (polarity control)
– Optional fault handling for each PWM signal
– Synchronization of timers in the PWM generator blocks
– Interrupt status summary of the PWM generator blocks
16.1 Block Diagram
Figure 16-1 on page 573 provides the Stellaris PWM module unit diagram and Figure 16-2 on page 574
provides a more detailed diagram of a Stellaris PWM generator. The LM3S6950 controller contains
three generator blocks (PWM0, PWM1, and PWM2) and generates six independent PWM signals
or three paired PWM signals with dead-band delays inserted.
Figure 16-1. PWM Unit Diagram
PWMINTEN
Interrupt
PWMRIS
PWMISC
PWMCTL
Control and
Status
PWMSYNC
PWMSTATUS
PWM
Generator 0
PWM
Generator 1
PWM
Generator 2
PWM 0
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM
Output
Control
Logic
PWM Clock
System Clock
Interrupts
Triggers
PWM0_A
PWM0_B
PWM1_A
PWM1_B
PWM2_A
PWM2_B
PWM0_Fault
PWM1_Fault
PWM2_Fault
Fault
PWMENABLE
Output
PWMINVERT
PWMFAULT
573June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 16-2. PWM Module Block Diagram
PWMnCMPA
Comparators
PWMnCMPB
PWMnLOAD
Timer
PWMnCOUNT
PWMnDBCTL
Dead-Band
Generator
PWMnDBRISE
PWMnDBFALL
PWMnCTL
Control
PWM Clock
PWM Generator Block
Signal
Generator
PWMnGENA
PWMnGENB
PWMnINTEN
Interrupt and
Trigger
Generator
PWMnRIS
PWMnISC
Fault(s)
PWMn_A
PWMn_B
Interrupts /
Triggers
PWMn_Fault
cmp A
cmp B
zero
load
dir
PWMnFLTSRC0
Fault
Condition
PWMnMINFLTPER
PWMnFLTSEN
PWMnFLTSTAT0
16.2 Signal Description
Table 16-1 on page 574 and Table 16-2 on page 574 list the external signals of the PWM module and
describe the function of each. The PWM controller signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for these PWM signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 306) should be set to choose the PWM function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284.
Table 16-1. PWM Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
PWM Fault.TTLI99Fault
PWM 0. This signal is controlled by PWM Generator 0.TTLO10PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLO61PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLO66PWM2
PWM 3. This signal is controlled by PWM Generator 1.TTLO67PWM3
PWM 4. This signal is controlled by PWM Generator 2.TTLO2PWM4
PWM 5. This signal is controlled by PWM Generator 2.TTLO1PWM5
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 16-2. PWM Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
PWM Fault.TTLIF2Fault
PWM 0. This signal is controlled by PWM Generator 0.TTLOG1PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLOH12PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLOE12PWM2
June 18, 2012574
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Table 16-2. PWM Signals (108BGA) (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
PWM 3. This signal is controlled by PWM Generator 1.TTLOD12PWM3
PWM 4. This signal is controlled by PWM Generator 2.TTLOC2PWM4
PWM 5. This signal is controlled by PWM Generator 2.TTLOC1PWM5
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
16.3 Functional Description
16.3.1 PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse.
16.3.2 PWM Comparators
There are two comparators in each PWM generator that monitor the value of the counter; when
either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down
mode, these comparators match both when counting up and when counting down; they are therefore
qualified by the counter direction signal. These qualified pulses are used in the PWM generation
process. If either comparator match value is greater than the counter load value, then that comparator
never outputs a High pulse.
Figure 16-3 on page 576 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 16-4 on page 576 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode.
575June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 16-3. PWM Count-Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
ADown
BDown
Figure 16-4. PWM Count-Up/Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
BUp
AUp ADown
BDown
16.3.3 PWM Signal Generator
The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM
signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load,
match A down, and match B down. In Count-Up/Down mode, there are six events that can affect
the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match
A or match B events are ignored when they coincide with the zero or load events. If the match A
and match B events coincide, the first signal, PWMA, is generated based only on the match A event,
and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 16-5 on page 577 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.
June 18, 2012576
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Figure 16-5. PWM Generation Example In Count-Up/Down Mode
Load
Zero
CompB
CompA
PWMB
PWMA
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.
16.3.4 Dead-Band Generator
The two PWM signals produced by the PWM generator are passed to the dead-band generator. If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal
is the input signal with the rising edge delayed by a programmable amount. The second output
PWM signal is the inversion of the input signal with a programmable delay added between the falling
edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a programmable
amount of time at transitions where both are Low. These signals are therefore suitable for driving
a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the
power electronics. Figure 16-6 on page 577 shows the effect of the dead-band generator on an input
PWM signal.
Figure 16-6. PWM Dead-Band Generator
Input
PWMA
PWMB
Rising Edge
Delay
Falling Edge
Delay
16.3.5 Interrupt Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt. Any of these events or a set of these events can be selected as a source for an interrupt;
when any of the selected events occur, an interrupt is generated. The selection of events allows
the interrupt to occur at a specific position within the PWM signal. Note that interrupts are based on
the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken
into account.
577June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16.3.6 Synchronization Methods
There is a global reset capability that can synchronously reset any or all of the counters in the PWM
generators. If multiple PWM generators are configured with the same counter load value, this can
be used to guarantee that they also have the same count value (this does imply that the PWM
generators must be configured before they are synchronized). With this, more than two PWM signals
can be produced with a known relationship between the edges of those signals since the counters
always have the same values.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly
short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global synchronized
update signal is asserted, at which point the new value is used as soon as the counter reaches
zero. This second mode allows multiple items in multiple PWM generators to be updated
simultaneously without odd effects during the update; everything runs from the old values until a
point at which they all run from the new values. The Update mode of the load and comparator match
values can be individually configured in each PWM generator block. It typically makes sense to use
the synchronous update mechanism across PWM generator blocks when the timers in those blocks
are synchronized, though this is not required in order for this mechanism to function properly.
16.3.7 Fault Conditions
There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interrupt.
Each PWM generator can also be configured to stop counting during a stall condition. The user can
select for the counters to run until they reach zero then stop, or to continue counting and reloading.
A stall condition does not generate a controller interrupt.
16.3.8 Output Control Block
With each PWM generator block producing two raw PWM signals, the output control block takes
care of the final conditioning of the PWM signals before they go to the pins. Via a single register,
the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for
example, to perform commutation of a brushless DC motor with a single register write (and without
modifying the individual PWM generators, which are modified by the feedback control loop). Similarly,
fault control can disable any of the PWM signals as well. A final inversion can be applied to any of
the PWM signals, making them active Low instead of the default active High.
16.4 Initialization and Configuration
The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes
the system clock is 20 MHz.
June 18, 2012578
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
5. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
■ Write the PWM0GENB register with a value of 0x0000.080C.
6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field
in the PWM0LOAD register to the requested period minus one.
■ Write the PWM0LOAD register with a value of 0x0000.018F.
7. Set the pulse width of the PWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
8. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
9. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
10. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
16.5 Register Map
Table 16-3 on page 580 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000. Note that the PWM module
clock must be enabled before the registers can be programmed (see page 212). There must be a
delay of 3 system clocks after the PWM module clock is enabled before any PWM module registers
are accessed.
579June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 16-3. PWM Register Map
See
page
DescriptionResetTypeNameOffset
582PWM Master Control0x0000.0000R/WPWMCTL0x000
583PWM Time Base Sync0x0000.0000R/WPWMSYNC0x004
584PWM Output Enable0x0000.0000R/WPWMENABLE0x008
585PWM Output Inversion0x0000.0000R/WPWMINVERT0x00C
586PWM Output Fault0x0000.0000R/WPWMFAULT0x010
587PWM Interrupt Enable0x0000.0000R/WPWMINTEN0x014
588PWM Raw Interrupt Status0x0000.0000ROPWMRIS0x018
589PWM Interrupt Status and Clear0x0000.0000R/W1CPWMISC0x01C
590PWM Status0x0000.0000ROPWMSTATUS0x020
591PWM0 Control0x0000.0000R/WPWM0CTL0x040
593PWM0 Interrupt Enable0x0000.0000R/WPWM0INTEN0x044
595PWM0 Raw Interrupt Status0x0000.0000ROPWM0RIS0x048
596PWM0 Interrupt Status and Clear0x0000.0000R/W1CPWM0ISC0x04C
597PWM0 Load0x0000.0000R/WPWM0LOAD0x050
598PWM0 Counter0x0000.0000ROPWM0COUNT0x054
599PWM0 Compare A0x0000.0000R/WPWM0CMPA0x058
600PWM0 Compare B0x0000.0000R/WPWM0CMPB0x05C
601PWM0 Generator A Control0x0000.0000R/WPWM0GENA0x060
604PWM0 Generator B Control0x0000.0000R/WPWM0GENB0x064
607PWM0 Dead-Band Control0x0000.0000R/WPWM0DBCTL0x068
608PWM0 Dead-Band Rising-Edge Delay0x0000.0000R/WPWM0DBRISE0x06C
609PWM0 Dead-Band Falling-Edge-Delay0x0000.0000R/WPWM0DBFALL0x070
591PWM1 Control0x0000.0000R/WPWM1CTL0x080
593PWM1 Interrupt Enable0x0000.0000R/WPWM1INTEN0x084
595PWM1 Raw Interrupt Status0x0000.0000ROPWM1RIS0x088
596PWM1 Interrupt Status and Clear0x0000.0000R/W1CPWM1ISC0x08C
597PWM1 Load0x0000.0000R/WPWM1LOAD0x090
598PWM1 Counter0x0000.0000ROPWM1COUNT0x094
599PWM1 Compare A0x0000.0000R/WPWM1CMPA0x098
600PWM1 Compare B0x0000.0000R/WPWM1CMPB0x09C
601PWM1 Generator A Control0x0000.0000R/WPWM1GENA0x0A0
604PWM1 Generator B Control0x0000.0000R/WPWM1GENB0x0A4
June 18, 2012580
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Table 16-3. PWM Register Map (continued)
See
page
DescriptionResetTypeNameOffset
607PWM1 Dead-Band Control0x0000.0000R/WPWM1DBCTL0x0A8
608PWM1 Dead-Band Rising-Edge Delay0x0000.0000R/WPWM1DBRISE0x0AC
609PWM1 Dead-Band Falling-Edge-Delay0x0000.0000R/WPWM1DBFALL0x0B0
591PWM2 Control0x0000.0000R/WPWM2CTL0x0C0
593PWM2 InterruptEnable0x0000.0000R/WPWM2INTEN0x0C4
595PWM2 Raw Interrupt Status0x0000.0000ROPWM2RIS0x0C8
596PWM2 Interrupt Status and Clear0x0000.0000R/W1CPWM2ISC0x0CC
597PWM2 Load0x0000.0000R/WPWM2LOAD0x0D0
598PWM2 Counter0x0000.0000ROPWM2COUNT0x0D4
599PWM2 Compare A0x0000.0000R/WPWM2CMPA0x0D8
600PWM2 Compare B0x0000.0000R/WPWM2CMPB0x0DC
601PWM2 Generator A Control0x0000.0000R/WPWM2GENA0x0E0
604PWM2 Generator B Control0x0000.0000R/WPWM2GENB0x0E4
607PWM2 Dead-Band Control0x0000.0000R/WPWM2DBCTL0x0E8
608PWM2 Dead-Band Rising-Edge Delay0x0000.0000R/WPWM2DBRISE0x0EC
609PWM2 Dead-Band Falling-Edge-Delay0x0000.0000R/WPWM2DBFALL0x0F0
16.6 Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
581June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GlobalSync0GlobalSync1GlobalSync2
reserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Update PWM Generator 2
Same as GlobalSync0 but for PWM generator 2.
0R/WGlobalSync22
Update PWM Generator 1
Same as GlobalSync0 but for PWM generator 1.
0R/WGlobalSync11
Update PWM Generator 0
Setting this bit causes any queued update to a load or comparator
register in PWM generator 0 to be applied the next time the
corresponding counter becomes zero. This bit automatically clears when
the updates have completed; it cannot be cleared by software.
0R/WGlobalSync00
June 18, 2012582
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing
multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred;
reading them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Sync0Sync1Sync2reserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Reset Generator 2 Counter
Performs a reset of the PWM generator 2 counter.
0R/WSync22
Reset Generator 1 Counter
Performs a reset of the PWM generator 1 counter.
0R/WSync11
Reset Generator 0 Counter
Performs a reset of the PWM generator 0 counter.
0R/WSync00
583June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example, when the time bases
are synchronized) without driving PWM signals to the pins. When bits in this register are set, the
corresponding PWM signal is passed through to the output stage, which is controlled by the
PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is
also passed to the output stage.
PWM Output Enable (PWMENABLE)
Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWM0EnPWM1EnPWM2EnPWM3EnPWM4EnPWM5Enreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
PWM5 Output Enable
When set, allows the generated PWM5 signal to be passed to the device
pin.
0R/WPWM5En5
PWM4 Output Enable
When set, allows the generated PWM4 signal to be passed to the device
pin.
0R/WPWM4En4
PWM3 Output Enable
When set, allows the generated PWM3 signal to be passed to the device
pin.
0R/WPWM3En3
PWM2 Output Enable
When set, allows the generated PWM2 signal to be passed to the device
pin.
0R/WPWM2En2
PWM1 Output Enable
When set, allows the generated PWM1 signal to be passed to the device
pin.
0R/WPWM1En1
PWM0 Output Enable
When set, allows the generated PWM0 signal to be passed to the device
pin.
0R/WPWM0En0
June 18, 2012584
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWM0InvPWM1InvPWM2InvPWM3InvPWM4InvPWM5Invreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Invert PWM5 Signal
When set, the generated PWM5 signal is inverted.
0R/WPWM5Inv5
Invert PWM4 Signal
When set, the generated PWM4 signal is inverted.
0R/WPWM4Inv4
Invert PWM3 Signal
When set, the generated PWM3 signal is inverted.
0R/WPWM3Inv3
Invert PWM2 Signal
When set, the generated PWM2 signal is inverted.
0R/WPWM2Inv2
Invert PWM1 Signal
When set, the generated PWM1 signal is inverted.
0R/WPWM1Inv1
Invert PWM0 Signal
When set, the generated PWM0 signal is inverted.
0R/WPWM0Inv0
585June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault inputs and debug events are considered fault conditions. On a fault condition, each PWM signal
can be passed through unmodified or driven Low. For outputs that are configured for pass-through,
the debug event handling on the corresponding PWM generator also determines if the PWM signal
continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Fault0Fault1Fault2Fault3Fault4Fault5reserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
PWM5 Fault
When set, the PWM5 output signal is driven Low on a fault condition.
0R/WFault55
PWM4 Fault
When set, the PWM4 output signal is driven Low on a fault condition.
0R/WFault44
PWM3 Fault
When set, the PWM3 output signal is driven Low on a fault condition.
0R/WFault33
PWM2 Fault
When set, the PWM2 output signal is driven Low on a fault condition.
0R/WFault22
PWM1 Fault
When set, the PWM1 output signal is driven Low on a fault condition.
0R/WFault11
PWM0 Fault
When set, the PWM0 output signal is driven Low on a fault condition.
0R/WFault00
June 18, 2012586
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
IntFault
reserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntPWM0IntPWM1IntPWM2reserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:17
Fault Interrupt Enable
When set, an interrupt occurs when the fault input is asserted.
0R/WIntFault16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:3
PWM2 Interrupt Enable
When set, an interrupt occurs when the PWM generator 2 block asserts
an interrupt.
0R/WIntPWM22
PWM1 Interrupt Enable
When set, an interrupt occurs when the PWM generator 1 block asserts
an interrupt.
0R/WIntPWM11
PWM0 Interrupt Enable
When set, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.
0R/WIntPWM00
587June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 589).
The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared
via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that
are active; zero bits indicate that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
IntFault
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntPWM0IntPWM1IntPWM2reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:17
Fault Interrupt Asserted
Indicates that the fault input is asserting.
0ROIntFault16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:3
PWM2 Interrupt Asserted
Indicates that the PWM generator 2 block is asserting its interrupt.
0ROIntPWM22
PWM1 Interrupt Asserted
Indicates that the PWM generator 1 block is asserting its interrupt.
0ROIntPWM11
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
0ROIntPWM00
June 18, 2012588
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. A
bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual
interrupt status registers in each block must be consulted to determine the reason for the interrupt,
and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched
interrupt status.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
IntFault
reserved
R/W1CROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntPWM0IntPWM1IntPWM2reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:17
Fault Interrupt Asserted
Indicates that the fault input is asserting an interrupt.
0R/W1CIntFault16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:3
PWM2 Interrupt Status
Indicates if the PWM generator 2 block is asserting an interrupt.
0ROIntPWM22
PWM1 Interrupt Status
Indicates if the PWM generator 1 block is asserting an interrupt.
0ROIntPWM11
PWM0 Interrupt Status
Indicates if the PWM generator 0 block is asserting an interrupt.
0ROIntPWM00
589June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the status of the FAULT input signal.
PWM Status (PWMSTATUS)
Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Faultreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Fault Interrupt Status
When set, indicates the fault input is asserted.
0ROFault0
June 18, 2012590
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 10: PWM0 Control (PWM0CTL), offset 0x040
Register 11: PWM1 Control (PWM1CTL), offset 0x080
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and
PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EnableModeDebugLoadUpdCmpAUpdCmpBUpdreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
0R/WCmpBUpd5
Comparator A Update Mode
The Update mode for the comparator A register. When not set, updates
to the register are reflected to the comparator the next time the counter
is 0. When set, updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been requested through
the PWM Master Control (PWMCTL) register (see page 582).
0R/WCmpAUpd4
Load Register Update Mode
The Update mode for the load register. When not set, updates to the
register are reflected to the counter the next time the counter is 0. When
set, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
0R/WLoadUpd3
Debug Mode
The behavior of the counter in Debug mode. When not set, the counter
stops running when it next reaches 0, and continues running again when
no longer in Debug mode. When set, the counter always runs.
0R/WDebug2
591June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Counter Mode
The mode for the counter. When not set, the counter counts down from
the load value to 0 and then wraps back to the load value (Count-Down
mode). When set, the counter counts up from 0 to the load value, back
down to 0, and then repeats (Count-Up/Down mode).
0R/WMode1
PWM Block Enable
Master enable for the PWM generation block. When not set, the entire
block is disabled and not clocked. When set, the block is enabled and
produces PWM signals.
0R/WEnable0
June 18, 2012592
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4
These registers control the interrupt generation capabilities of the PWM generators (PWM0INTEN
controls the PWM generator 0 block, and so on). The events that can cause an interrupt are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt.
PWM0 Interrupt Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
reserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Interrupt for Counter=Comparator B Down
DescriptionValue
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
1
No interrupt.0
0R/WIntCmpBD5
Interrupt for Counter=Comparator B Up
DescriptionValue
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting up.
1
No interrupt.0
0R/WIntCmpBU4
593June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Interrupt for Counter=Comparator A Down
DescriptionValue
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting down.
1
No interrupt.0
0R/WIntCmpAD3
Interrupt for Counter=Comparator A Up
DescriptionValue
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting up.
1
No interrupt.0
0R/WIntCmpAU2
Interrupt for Counter=Load
DescriptionValue
A raw interrupt occurs when the counter matches the value in
the PWMnLOAD register value.
1
No interrupt.0
0R/WIntCntLoad1
Interrupt for Counter=0
DescriptionValue
A raw interrupt occurs when the counter is zero.1
No interrupt.0
0R/WIntCntZero0
June 18, 2012594
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). Bits set to 1 indicate the latched events that have occurred; bits set to 0 indicate
that the event in question has not occurred.
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Comparator B Down Interrupt Status
Indicates that the counter has matched the comparator B value while
counting down.
0ROIntCmpBD5
Comparator B Up Interrupt Status
Indicates that the counter has matched the comparator B value while
counting up.
0ROIntCmpBU4
Comparator A Down Interrupt Status
Indicates that the counter has matched the comparator A value while
counting down.
0ROIntCmpAD3
Comparator A Up Interrupt Status
Indicates that the counter has matched the comparator A value while
counting up.
0ROIntCmpAU2
Counter=Load Interrupt Status
Indicates that the counter has matched the PWMnLOAD register.
0ROIntCntLoad1
Counter=0 Interrupt Status
Indicates that the counter has matched 0.
0ROIntCntZero0
595June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; bits set to 0 indicate that the event in question has not occurred. These are
R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
reserved
R/W1CR/W1CR/W1CR/W1CR/W1CR/W1CROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Comparator B Down Interrupt
Indicates that the counter has matched the comparator B value while
counting down.
0R/W1CIntCmpBD5
Comparator B Up Interrupt
Indicates that the counter has matched the comparator B value while
counting up.
0R/W1CIntCmpBU4
Comparator A Down Interrupt
Indicates that the counter has matched the comparator A value while
counting down.
0R/W1CIntCmpAD3
Comparator A Up Interrupt
Indicates that the counter has matched the comparator A value while
counting up.
0R/W1CIntCmpAU2
Counter=Load Interrupt
Indicates that the counter has matched the PWMnLOAD register.
0R/W1CIntCntLoad1
Counter=0 Interrupt
Indicates that the counter has matched 0.
0R/W1CIntCntZero0
June 18, 2012596
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 22: PWM0 Load (PWM0LOAD), offset 0x050
Register 23: PWM1 Load (PWM1LOAD), offset 0x090
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter
after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero.
If the Load Value Update mode is immediate, this value is used the next time the counter reaches
zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 582).
If this register is re-written before the actual update occurs, the previous value is never used and is
lost.
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Load
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
Counter Load Value
The counter load value.
0R/WLoad15:0
597June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches the load register, a pulse is output;
this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see
page 601 and page 604) or drive an interrupt (via the PWMnINTEN register, see page 593). A pulse
with the same capabilities is generated when this value is zero.
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Count
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
Counter Value
The current value of the counter.
0x00ROCount15:0
June 18, 2012598
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD
register (see page 597), then no pulse is ever output.
If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),
this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 582). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare A (PWM0CMPA)
Base 0x4002.8000
Offset 0x058
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CompA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
Comparator A Value
The value to be compared against the counter.
0x00R/WCompA15:0
599June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD
register, no pulse is ever output.
If the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL register),
this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 582). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CompB
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
Comparator B Value
The value to be compared against the counter.
0x00R/WCompB15:0
June 18, 2012600
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
These registers control the generation of the PWMnA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that
is produced.
The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal;
and PWM2GENA, the PWM2A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
PWM0 Generator A Control (PWM0GENA)
Base 0x4002.8000
Offset 0x060
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBDreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:12
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpBD11:10
601June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 591) is set to 1.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpBU9:8
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpAD7:6
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpAU5:4
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActLoad3:2
June 18, 2012602
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
DescriptionResetTypeNameBit/Field
Action for Counter=0
The action to be taken when the counter is zero.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActZero1:0
603June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
These registers control the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These
events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal;
and PWM2GENB, the PWM2B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBDreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:12
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpBD11:10
June 18, 2012604
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
DescriptionResetTypeNameBit/Field
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpBU9:8
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpAD7:6
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActCmpAU5:4
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActLoad3:2
605June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
DescriptionResetTypeNameBit/Field
Action for Counter=0
The action to be taken when the counter is 0.
The table below defines the effect of the event on the output signal.
DescriptionValue
Do nothing.0x0
Invert the output signal.0x1
Set the output signal to 0.0x2
Set the output signal to 1.0x3
0x0R/WActZero1:0
June 18, 2012606
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1
signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through
to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and
inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by
delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see
page 608), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by
the value in the PWM0DBFALL register (see page 609). In a similar manner, PWM2 and PWM3 are
produced from the PWM1A and PWM1B signals, and PWM4 and PWM5 are produced from the PWM2A
and PWM2B signals.
PWM0 Dead-Band Control (PWM0DBCTL)
Base 0x4002.8000
Offset 0x068
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Enablereserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Dead-Band Generator Enable
When set, the dead-band generator inserts dead bands into the output
signals; when clear, it simply passes the PWM signals through.
0R/WEnable0
607June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge
delayed.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RiseDelayreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:12
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
0R/WRiseDelay11:0
June 18, 2012608
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed and PWM5
is produced from PWM2A with its falling edge delayed.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FallDelayreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:12
Dead-Band Fall Delay
The number of clock ticks to delay the falling edge.
0x00R/WFallDelay11:0
609June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
17 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris®quadrature encoder interface (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
The Stellaris quadrature encoder has the following features:
■ Position integrator that tracks the encoder position
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
17.1 Block Diagram
Figure 17-1 on page 611 provides a block diagram of a Stellaris QEI module.
June 18, 2012610
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Figure 17-1. QEI Block Diagram
Quadrature
Encoder
Velocity
Predivider
Interrupt Control
QEIINTEN
QEIRIS
QEIISC
Position Integrator
QEIMAXPOS
QEIPOS
Velocity Accumulator
QEICOUNT
QEISPEED
Velocity Timer
QEILOAD
QEITIME
PhA
PhB
IDX
clk
dir
Interrupt
Control & Status
QEICTL
QEISTAT
17.2 Signal Description
Table 17-1 on page 611 and Table 17-2 on page 611 list the external signals of the QEI module and
describe the function of each. The QEI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the
possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 306) should be set to choose the QEI function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 284.
Table 17-1. QEI Signals (100LQFP)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
QEI module 0 index.TTLI100IDX0
QEI module 0 phase A.TTLI11PhA0
QEI module 0 phase B.TTLI47PhB0
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-2. QEI Signals (108BGA)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
QEI module 0 index.TTLIF1IDX0
QEI module 0 phase A.TTLIG2PhA0
QEI module 0 phase B.TTLIM9PhB0
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
611June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
17.3 Functional Description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA
and PhB, can be swapped before being interpreted by the QEI module to change the meaning of
forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see
page 616).
When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the
capture mode for the position integrator can be set to update the position counter on every edge of
the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on
every PhA and PhB provides more positional resolution at the cost of less range in the positional
counter.
When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB
lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is
seen on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI
Control (QEICTL) register.
When ResMode is 1, the positional counter is reset when the index pulse is sensed. This limits the
positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution
of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse
direction from position 0 can move the position counter to N-1. In this mode, the position register
contains the absolute position of the encoder relative to the index (or home) position once an index
pulse has been seen.
When ResMode is 0, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
The velocity capture has a configurable timer and a count register. It counts the number of phase
edges (using the same configuration as for the position integrator) in a given time period. The edge
count from the previous time period is available to the controller via the QEISPEED register, while
the edge count for the current time period is being accumulated in the QEICOUNT register. As soon
as the current time period is complete, the total number of edges counted in that time period is made
available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and
counting commences on a new time period. The number of edges counted in a given time period
is directly proportional to the velocity of the encoder.
Figure 17-2 on page 613 shows how the Stellaris quadrature encoder converts the phase input signals
into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode).
June 18, 2012612
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation
-1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1 +1 +1 +1 +1 +1 +1 +1
PhA
PhB
clk
clkdiv
dir
pos
rel
The period of the timer is configurable by specifying the load value for the timer in the QEILOAD
register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the
timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer
timer period is needed to be able to capture enough edges to have a meaningful result. At higher
encoder speeds, both a shorter timer period and/or the velocity predivider can be used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and
4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
÷1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation since intermediate values may exceed the capacity
of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could
be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if
they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled
by the ÷4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation, as well as reducing the processing requirement of computing
this equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a
load value must be selected such that the product is very close to a power of two. For example, a
613June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor,
which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the
divide in most cases. If absolute accuracy were required, the controller’s divide instruction could be
used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
17.4 Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there
are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the
count is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
5. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
6. Delay for some time.
7. Read the encoder position by reading the QEIPOS register value.
17.5 Register Map
Table 17-3 on page 614 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 218). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.
Table 17-3. QEI Register Map
See
page
DescriptionResetTypeNameOffset
616QEI Control0x0000.0000R/WQEICTL0x000
June 18, 2012614
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Table 17-3. QEI Register Map (continued)
See
page
DescriptionResetTypeNameOffset
618QEI Status0x0000.0000ROQEISTAT0x004
619QEI Position0x0000.0000R/WQEIPOS0x008
620QEI Maximum Position0x0000.0000R/WQEIMAXPOS0x00C
621QEI Timer Load0x0000.0000R/WQEILOAD0x010
622QEI Timer0x0000.0000ROQEITIME0x014
623QEI Velocity Counter0x0000.0000ROQEICOUNT0x018
624QEI Velocity0x0000.0000ROQEISPEED0x01C
625QEI Interrupt Enable0x0000.0000R/WQEIINTEN0x020
626QEI Raw Interrupt Status0x0000.0000ROQEIRIS0x024
627QEI Interrupt Status and Clear0x0000.0000R/W1CQEIISC0x028
17.6 Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
615June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EnableSwapSigModeCapModeResModeVelEnVelDivINVAINVBINVISTALLENreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:13
Stall QEI
When set, the QEI stalls when the microcontroller asserts Halt.
0R/WSTALLEN12
Invert Index Pulse
When set , the input Index Pulse is inverted.
0R/WINVI11
Invert PhB
When set, the PhB input is inverted.
0R/WINVB10
Invert PhA
When set, the PhA input is inverted.
0R/WINVA9
Predivide Velocity
A predivider of the input quadrature pulses before being applied to the
QEICOUNT accumulator. This field can be set to the following values:
PredividerValue
÷10x0
÷20x1
÷40x2
÷80x3
÷160x4
÷320x5
÷640x6
÷1280x7
0x0R/WVelDiv8:6
June 18, 2012616
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
DescriptionResetTypeNameBit/Field
Capture Velocity
When set, enables capture of the velocity of the quadrature encoder.
0R/WVelEn5
Reset Mode
The Reset mode for the position counter. When 0, the position counter
is reset when it reaches the maximum; when 1, the position counter is
reset when the index pulse is captured.
0R/WResMode4
Capture Mode
The Capture mode defines the phase edges that are counted in the
position. When 0, only the PhA edges are counted; when 1, the PhA
and PhB edges are counted, providing twice the positional resolution
but half the range.
0R/WCapMode3
Signal Mode
When 1, the PhA and PhB signals are clock and direction; when 0, they
are quadrature phase signals.
0R/WSigMode2
Swap Signals
Swaps the PhA and PhB signals.
0R/WSwap1
Enable QEI
Enables the quadrature encoder module.
0R/WEnable0
617June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
QEI0 base: 0x4002.C000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Error
Direction
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Direction of Rotation
Indicates the direction the encoder is rotating.
The Direction values are defined as follows:
DescriptionValue
Forward rotation0
Reverse rotation1
0RODirection1
Error Detected
Indicates that an error was detected in the gray code sequence (that is,
both signals changing at the same time).
0ROError0
June 18, 2012618
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. Its value is updated by inputs on
the QEI phase inputs, and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
QEI0 base: 0x4002.C000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
Position
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
Position
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Current Position Integrator Value
The current value of the position integrator.
0x00R/WPosition31:0
619June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving backward, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
QEI0 base: 0x4002.C000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
MaxPos
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
MaxPos
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Maximum Position Integrator Value
The maximum value of the position integrator.
0x00R/WMaxPos31:0
June 18, 2012620
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Since this value is loaded into the timer
the clock cycle after the timer is zero, this value should be one less than the number of clocks in
the desired period. So, for example, to have 2000 clocks per timer period, this register should contain
1999.
QEI Timer Load (QEILOAD)
QEI0 base: 0x4002.C000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
Load
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
Load
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Velocity Timer Load Value
The load value for the velocity timer.
0x00R/WLoad31:0
621June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
VelEn in QEICTL is 0.
QEI Timer (QEITIME)
QEI0 base: 0x4002.C000
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
Time
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Time
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Velocity Timer Current Value
The current value of the velocity timer.
0x00ROTime31:0
June 18, 2012622
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Since this is
a running total, the time period to which it applies cannot be known with precision (that is, a read of
this register does not necessarily correspond to the time returned by the QEITIME register since
there is a small window of time between the two reads, during which time either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when VelEn in
QEICTL is 0.
QEI Velocity Counter (QEICOUNT)
QEI0 base: 0x4002.C000
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
Count
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Count
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
0x00ROCount31:0
623June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when VelEn in QEICTL is 0.
QEI Velocity (QEISPEED)
QEI0 base: 0x4002.C000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
Speed
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Speed
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Velocity
The measured speed of the quadrature encoder in pulses per period.
0x00ROSpeed31:0
June 18, 2012624
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntIndexIntTimer
IntDir
IntError
reserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
0R/WIntError3
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
0R/WIntDir2
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
0R/WIntTimer1
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
0R/WIntIndex0
625June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
Offset 0x024
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntIndexIntTimer
IntDir
IntError
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
Phase Error Detected
Indicates that a phase error was detected.
0ROIntError3
Direction Change Detected
Indicates that the direction has changed.
0ROIntDir2
Velocity Timer Expired
Indicates that the velocity timer has expired.
0ROIntTimer1
Index Pulse Asserted
Indicates that the index pulse has occurred.
0ROIntIndex0
June 18, 2012626
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
Offset 0x028
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntIndexIntTimer
IntDir
IntError
reserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
Phase Error Interrupt
Indicates that a phase error was detected.
0R/W1CIntError3
Direction Change Interrupt
Indicates that the direction has changed.
0R/W1CIntDir2
Velocity Timer Expired Interrupt
Indicates that the velocity timer has expired.
0R/W1CIntTimer1
Index Pulse Interrupt
Indicates that the index pulse has occurred.
0R/W1CIntIndex0
627June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
18 Pin Diagram
The LM3S6950 microcontroller pin diagrams are shown below.
Figure 18-1. 100-Pin LQFP Package Pin Diagram
June 18, 2012628
Texas Instruments-Production Data
Pin Diagram
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View)
629June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
19 Signal Tables
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.
■ Signals by Pin Number
■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals
19.1 100-Pin LQFP Package Pin Tables
19.1.1 Signals by Pin Number
Table 19-1. Signals by Pin Number
DescriptionBuffer Typea
Pin TypePin NamePin Number
GPIO port E bit 7.TTLI/OPE7
1PWM 5. This signal is controlled by PWM Generator 2.TTLOPWM5
GPIO port E bit 6.TTLI/OPE6
2PWM 4. This signal is controlled by PWM Generator 2.TTLOPWM4
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 661, regardless of system implementation.
Power-VDDA
3
The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
Power-GNDA
4
GPIO port E bit 5.TTLI/OPE5
5
GPIO port E bit 4.TTLI/OPE4
6Capture/Compare/PWM 3.TTLI/OCCP3
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
Power-LDO
7
Positive supply for I/O and some logic.Power-VDD
8
Ground reference for logic and I/O pins.Power-GND
9
GPIO port D bit 0.TTLI/OPD0
10 PWM 0. This signal is controlled by PWM Generator 0.TTLOPWM0
GPIO port D bit 1.TTLI/OPD1
11 QEI module 0 phase A.TTLIPhA0
GPIO port D bit 2.TTLI/OPD2
12 UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
TTLIU1Rx
June 18, 2012630
Texas Instruments-Production Data
Signal Tables
Table 19-1. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
GPIO port D bit 3.TTLI/OPD3
13 UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
TTLOU1Tx
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
14
Ground reference for logic and I/O pins.Power-GND
15
Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
TTLIXTALPPHY
16
Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect
this pin to ground when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
TTLOXTALNPHY
17
GPIO port G bit 1.TTLI/OPG1
18 UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
TTLOU2Tx
GPIO port G bit 0.TTLI/OPG0
19 UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
TTLIU2Rx
Positive supply for I/O and some logic.Power-VDD
20
Ground reference for logic and I/O pins.Power-GND
21
GPIO port C bit 7.TTLI/OPC7
22 Analog comparator 2 negative input.AnalogIC2-
GPIO port C bit 6.TTLI/OPC6
23 Analog comparator 2 positive input.AnalogIC2+
Analog comparator 2 output.TTLOC2o
GPIO port C bit 5.TTLI/OPC5
24 Analog comparator 1 positive input.AnalogIC1+
Analog comparator 1 output.TTLOC1o
GPIO port C bit 4.TTLI/OPC4
25 Capture/Compare/PWM 5.TTLI/OCCP5
GPIO port A bit 0.TTLI/OPA0
26 UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
TTLIU0Rx
GPIO port A bit 1.TTLI/OPA1
27 UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
TTLOU0Tx
GPIO port A bit 2.TTLI/OPA2
28 SSI module 0 clockTTLI/OSSI0Clk
GPIO port A bit 3.TTLI/OPA3
29 SSI module 0 frame signalTTLI/OSSI0Fss
GPIO port A bit 4.TTLI/OPA4
30 SSI module 0 receiveTTLISSI0Rx
GPIO port A bit 5.TTLI/OPA5
31 SSI module 0 transmitTTLOSSI0Tx
Positive supply for I/O and some logic.Power-VDD
32
631June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-1. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
Ground reference for logic and I/O pins.Power-GND
33
GPIO port A bit 6.TTLI/OPA6
34 Capture/Compare/PWM 1.TTLI/OCCP1
GPIO port A bit 7.TTLI/OPA7
35 Capture/Compare/PWM 4.TTLI/OCCP4
VCC of the Ethernet PHY.Power-VCCPHY
36
RXIN of the Ethernet PHY.AnalogIRXIN
37
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
38
Ground reference for logic and I/O pins.Power-GND
39
RXIP of the Ethernet PHY.AnalogIRXIP
40
12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.AnalogIERBIAS
41
GND of the Ethernet PHY.Power-GNDPHY
42
TXOP of the Ethernet PHY.AnalogOTXOP
43
Positive supply for I/O and some logic.Power-VDD
44
Ground reference for logic and I/O pins.Power-GND
45
TXON of the Ethernet PHY.AnalogOTXON
46
GPIO port F bit 0.TTLI/OPF0
47 QEI module 0 phase B.TTLIPhB0
Main oscillator crystal input or an external clock reference input.AnalogIOSC0
48
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
AnalogOOSC1
49
An external input that brings the processor out of Hibernate mode
when asserted.
TTLIWAKE
50
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODOHIB
51
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
AnalogIXOSC0
52
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
AnalogOXOSC1
53
Ground reference for logic and I/O pins.Power-GND
54
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
Power-VBAT
55
Positive supply for I/O and some logic.Power-VDD
56
Ground reference for logic and I/O pins.Power-GND
57
MDIO of the Ethernet PHY.TTLI/OMDIO
58
GPIO port F bit 3.TTLI/OPF3
59 Ethernet LED 0.TTLOLED0
GPIO port F bit 2.TTLI/OPF2
60 Ethernet LED 1.TTLOLED1
GPIO port F bit 1.TTLI/OPF1
61 PWM 1. This signal is controlled by PWM Generator 0.TTLOPWM1
June 18, 2012632
Texas Instruments-Production Data
Signal Tables
Table 19-1. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
62
Ground reference for logic and I/O pins.Power-GND
63
System reset input.TTLIRST
64
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD0
65
GPIO port B bit 0.TTLI/OPB0
66 PWM 2. This signal is controlled by PWM Generator 1.TTLOPWM2
GPIO port B bit 1.TTLI/OPB1
67 PWM 3. This signal is controlled by PWM Generator 1.TTLOPWM3
Positive supply for I/O and some logic.Power-VDD
68
Ground reference for logic and I/O pins.Power-GND
69
GPIO port B bit 2.TTLI/OPB2
70 I2C module 0 clock.ODI/OI2C0SCL
GPIO port B bit 3.TTLI/OPB3
71 I2C module 0 data.ODI/OI2C0SDA
GPIO port E bit 0.TTLI/OPE0
72 SSI module 1 clockTTLI/OSSI1Clk
GPIO port E bit 1.TTLI/OPE1
73 SSI module 1 frame signalTTLI/OSSI1Fss
GPIO port E bit 2.TTLI/OPE2
74 SSI module 1 receiveTTLISSI1Rx
GPIO port E bit 3.TTLI/OPE3
75 SSI module 1 transmitTTLOSSI1Tx
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD1
76
GPIO port C bit 3.TTLI/OPC3
77 JTAG TDO and SWO.TTLOSWO
JTAG TDO and SWO.TTLOTDO
GPIO port C bit 2.TTLI/OPC2
78 JTAG TDI.TTLITDI
GPIO port C bit 1.TTLI/OPC1
79 JTAG TMS and SWDIO.TTLI/OSWDIO
JTAG TMS and SWDIO.TTLI/OTMS
GPIO port C bit 0.TTLI/OPC0
80 JTAG/SWD CLK.TTLISWCLK
JTAG/SWD CLK.TTLITCK
Positive supply for I/O and some logic.Power-VDD
81
Ground reference for logic and I/O pins.Power-GND
82
VCC of the Ethernet PHY.Power-VCCPHY
83
VCC of the Ethernet PHY.Power-VCCPHY
84
GND of the Ethernet PHY.Power-GNDPHY
85
633June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-1. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
GND of the Ethernet PHY.Power-GNDPHY
86
Ground reference for logic and I/O pins.Power-GND
87
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
88
GPIO port B bit 7.TTLI/OPB7
89 JTAG TRST.TTLITRST
GPIO port B bit 6.TTLI/OPB6
90 Analog comparator 0 positive input.AnalogIC0+
Analog comparator 0 output.TTLOC0o
GPIO port B bit 5.TTLI/OPB5
91 Analog comparator 1 negative input.AnalogIC1-
GPIO port B bit 4.TTLI/OPB4
92 Analog comparator 0 negative input.AnalogIC0-
Positive supply for I/O and some logic.Power-VDD
93
Ground reference for logic and I/O pins.Power-GND
94
GPIO port D bit 4.TTLI/OPD4
95 Capture/Compare/PWM 0.TTLI/OCCP0
GPIO port D bit 5.TTLI/OPD5
96 Capture/Compare/PWM 2.TTLI/OCCP2
The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
Power-GNDA
97
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 661, regardless of system implementation.
Power-VDDA
98
GPIO port D bit 6.TTLI/OPD6
99 PWM Fault.TTLIFault
GPIO port D bit 7.TTLI/OPD7
100 QEI module 0 index.TTLIIDX0
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.1.2 Signals by Signal Name
Table 19-2. Signals by Signal Name
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Analog comparator 0 positive input.AnalogI90C0+
Analog comparator 0 negative input.AnalogI92C0-
Analog comparator 0 output.TTLO90C0o
Analog comparator 1 positive input.AnalogI24C1+
Analog comparator 1 negative input.AnalogI91C1-
Analog comparator 1 output.TTLO24C1o
June 18, 2012634
Texas Instruments-Production Data
Signal Tables
Table 19-2. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Analog comparator 2 positive input.AnalogI23C2+
Analog comparator 2 negative input.AnalogI22C2-
Analog comparator 2 output.TTLO23C2o
Capture/Compare/PWM 0.TTLI/O95CCP0
Capture/Compare/PWM 1.TTLI/O34CCP1
Capture/Compare/PWM 2.TTLI/O96CCP2
Capture/Compare/PWM 3.TTLI/O6CCP3
Capture/Compare/PWM 4.TTLI/O35CCP4
Capture/Compare/PWM 5.TTLI/O25CCP5
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLI65CMOD0
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLI76CMOD1
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
AnalogI41ERBIAS
PWM Fault.TTLI99Fault
Ground reference for logic and I/O pins.Power-9
15
21
33
39
45
54
57
63
69
82
87
94
GND
The ground reference for the analog circuits ( Analog
Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
Power-4
97
GNDA
GND of the Ethernet PHY.Power-42
85
86
GNDPHY
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODO51HIB
I2C module 0 clock.ODI/O70I2C0SCL
I2C module 0 data.ODI/O71I2C0SDA
QEI module 0 index.TTLI100IDX0
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. The LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
Power-7LDO
Ethernet LED 0.TTLO59LED0
Ethernet LED 1.TTLO60LED1
MDIO of the Ethernet PHY.TTLI/O58MDIO
635June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-2. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Main oscillator crystal input or an external clock reference
input.
AnalogI48OSC0
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
AnalogO49OSC1
GPIO port A bit 0.TTLI/O26PA0
GPIO port A bit 1.TTLI/O27PA1
GPIO port A bit 2.TTLI/O28PA2
GPIO port A bit 3.TTLI/O29PA3
GPIO port A bit 4.TTLI/O30PA4
GPIO port A bit 5.TTLI/O31PA5
GPIO port A bit 6.TTLI/O34PA6
GPIO port A bit 7.TTLI/O35PA7
GPIO port B bit 0.TTLI/O66PB0
GPIO port B bit 1.TTLI/O67PB1
GPIO port B bit 2.TTLI/O70PB2
GPIO port B bit 3.TTLI/O71PB3
GPIO port B bit 4.TTLI/O92PB4
GPIO port B bit 5.TTLI/O91PB5
GPIO port B bit 6.TTLI/O90PB6
GPIO port B bit 7.TTLI/O89PB7
GPIO port C bit 0.TTLI/O80PC0
GPIO port C bit 1.TTLI/O79PC1
GPIO port C bit 2.TTLI/O78PC2
GPIO port C bit 3.TTLI/O77PC3
GPIO port C bit 4.TTLI/O25PC4
GPIO port C bit 5.TTLI/O24PC5
GPIO port C bit 6.TTLI/O23PC6
GPIO port C bit 7.TTLI/O22PC7
GPIO port D bit 0.TTLI/O10PD0
GPIO port D bit 1.TTLI/O11PD1
GPIO port D bit 2.TTLI/O12PD2
GPIO port D bit 3.TTLI/O13PD3
GPIO port D bit 4.TTLI/O95PD4
GPIO port D bit 5.TTLI/O96PD5
GPIO port D bit 6.TTLI/O99PD6
GPIO port D bit 7.TTLI/O100PD7
GPIO port E bit 0.TTLI/O72PE0
GPIO port E bit 1.TTLI/O73PE1
GPIO port E bit 2.TTLI/O74PE2
GPIO port E bit 3.TTLI/O75PE3
GPIO port E bit 4.TTLI/O6PE4
GPIO port E bit 5.TTLI/O5PE5
June 18, 2012636
Texas Instruments-Production Data
Signal Tables
Table 19-2. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
GPIO port E bit 6.TTLI/O2PE6
GPIO port E bit 7.TTLI/O1PE7
GPIO port F bit 0.TTLI/O47PF0
GPIO port F bit 1.TTLI/O61PF1
GPIO port F bit 2.TTLI/O60PF2
GPIO port F bit 3.TTLI/O59PF3
GPIO port G bit 0.TTLI/O19PG0
GPIO port G bit 1.TTLI/O18PG1
QEI module 0 phase A.TTLI11PhA0
QEI module 0 phase B.TTLI47PhB0
PWM 0. This signal is controlled by PWM Generator 0.TTLO10PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLO61PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLO66PWM2
PWM 3. This signal is controlled by PWM Generator 1.TTLO67PWM3
PWM 4. This signal is controlled by PWM Generator 2.TTLO2PWM4
PWM 5. This signal is controlled by PWM Generator 2.TTLO1PWM5
System reset input.TTLI64RST
RXIN of the Ethernet PHY.AnalogI37RXIN
RXIP of the Ethernet PHY.AnalogI40RXIP
SSI module 0 clockTTLI/O28SSI0Clk
SSI module 0 frame signalTTLI/O29SSI0Fss
SSI module 0 receiveTTLI30SSI0Rx
SSI module 0 transmitTTLO31SSI0Tx
SSI module 1 clockTTLI/O72SSI1Clk
SSI module 1 frame signalTTLI/O73SSI1Fss
SSI module 1 receiveTTLI74SSI1Rx
SSI module 1 transmitTTLO75SSI1Tx
JTAG/SWD CLK.TTLI80SWCLK
JTAG TMS and SWDIO.TTLI/O79SWDIO
JTAG TDO and SWO.TTLO77SWO
JTAG/SWD CLK.TTLI80TCK
JTAG TDI.TTLI78TDI
JTAG TDO and SWO.TTLO77TDO
JTAG TMS and SWDIO.TTLI/O79TMS
JTAG TRST.TTLI89TRST
TXON of the Ethernet PHY.AnalogO46TXON
TXOP of the Ethernet PHY.AnalogO43TXOP
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLI26U0Rx
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO27U0Tx
637June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-2. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLI12U1Rx
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO13U1Tx
UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLI19U2Rx
UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO18U2Tx
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
Power-55VBAT
VCC of the Ethernet PHY.Power-36
83
84
VCCPHY
Positive supply for I/O and some logic.Power-8
20
32
44
56
68
81
93
VDD
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-14
38
62
88
VDD25
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to
minimize the electrical noise contained on VDD from affecting
the analog functions. VDDA pins must be supplied with a
voltage that meets the specification in “Recommended DC
Operating Conditions” on page 661, regardless of system
implementation.
Power-3
98
VDDA
An external input that brings the processor out of Hibernate
mode when asserted.
TTLI50WAKE
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
AnalogI52XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
AnalogO53XOSC1
Ethernet PHY XTALN 25-MHz oscillator crystal output.
Connect this pin to ground when using a single-ended 25-MHz
clock input connected to the XTALPPHY pin.
TTLO17XTALNPHY
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
TTLI16XTALPPHY
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 18, 2012638
Texas Instruments-Production Data
Signal Tables
19.1.3 Signals by Function, Except for GPIO
Table 19-3. Signals by Function, Except for GPIO
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
Analog comparator 0 positive input.AnalogI90C0+
Analog Comparators
Analog comparator 0 negative input.AnalogI92C0-
Analog comparator 0 output.TTLO90C0o
Analog comparator 1 positive input.AnalogI24C1+
Analog comparator 1 negative input.AnalogI91C1-
Analog comparator 1 output.TTLO24C1o
Analog comparator 2 positive input.AnalogI23C2+
Analog comparator 2 negative input.AnalogI22C2-
Analog comparator 2 output.TTLO23C2o
12.4-kΩ resistor (1% precision) used internally for
Ethernet PHY.
AnalogI41ERBIAS
Ethernet
GND of the Ethernet PHY.Power-42
85
86
GNDPHY
Ethernet LED 0.TTLO59LED0
Ethernet LED 1.TTLO60LED1
MDIO of the Ethernet PHY.TTLI/O58MDIO
RXIN of the Ethernet PHY.AnalogI37RXIN
RXIP of the Ethernet PHY.AnalogI40RXIP
TXON of the Ethernet PHY.AnalogO46TXON
TXOP of the Ethernet PHY.AnalogO43TXOP
VCC of the Ethernet PHY.Power-36
83
84
VCCPHY
Ethernet PHY XTALN 25-MHz oscillator crystal
output. Connect this pin to ground when using a
single-ended 25-MHz clock input connected to the
XTALPPHY pin.
TTLO17XTALNPHY
Ethernet PHY XTALP 25-MHz oscillator crystal
input or external clock reference input.
TTLI16XTALPPHY
Capture/Compare/PWM 0.TTLI/O95CCP0
General-Purpose
Timers
Capture/Compare/PWM 1.TTLI/O34CCP1
Capture/Compare/PWM 2.TTLI/O96CCP2
Capture/Compare/PWM 3.TTLI/O6CCP3
Capture/Compare/PWM 4.TTLI/O35CCP4
Capture/Compare/PWM 5.TTLI/O25CCP5
639June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-3. Signals by Function, Except for GPIO (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
An open-drain output with internal pull-up that
indicates the processor is in Hibernate mode.
ODO51HIB
Hibernate
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
Power-55VBAT
An external input that brings the processor out of
Hibernate mode when asserted.
TTLI50WAKE
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
AnalogI52XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
AnalogO53XOSC1
I2C module 0 clock.ODI/O70I2C0SCL
I2C I2C module 0 data.ODI/O71I2C0SDA
JTAG/SWD CLK.TTLI80SWCLK
JTAG/SWD/SWO
JTAG TMS and SWDIO.TTLI/O79SWDIO
JTAG TDO and SWO.TTLO77SWO
JTAG/SWD CLK.TTLI80TCK
JTAG TDI.TTLI78TDI
JTAG TDO and SWO.TTLO77TDO
JTAG TMS and SWDIO.TTLI/O79TMS
JTAG TRST.TTLI89TRST
PWM Fault.TTLI99Fault
PWM
PWM 0. This signal is controlled by PWM Generator
0.
TTLO10PWM0
PWM 1. This signal is controlled by PWM Generator
0.
TTLO61PWM1
PWM 2. This signal is controlled by PWM Generator
1.
TTLO66PWM2
PWM 3. This signal is controlled by PWM Generator
1.
TTLO67PWM3
PWM 4. This signal is controlled by PWM Generator
2.
TTLO2PWM4
PWM 5. This signal is controlled by PWM Generator
2.
TTLO1PWM5
June 18, 2012640
Texas Instruments-Production Data
Signal Tables
Table 19-3. Signals by Function, Except for GPIO (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
Ground reference for logic and I/O pins.Power-9
15
21
33
39
45
54
57
63
69
82
87
94
GND
Power
The ground reference for the analog circuits (
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
Power-4
97
GNDA
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
Power-7LDO
Positive supply for I/O and some logic.Power-8
20
32
44
56
68
81
93
VDD
Positive supply for most of the logic function,
including the processor core and most peripherals.
Power-14
38
62
88
VDD25
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in “Recommended DC Operating
Conditions” on page 661, regardless of system
implementation.
Power-3
98
VDDA
QEI module 0 index.TTLI100IDX0
QEI QEI module 0 phase A.TTLI11PhA0
QEI module 0 phase B.TTLI47PhB0
641June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-3. Signals by Function, Except for GPIO (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
SSI module 0 clockTTLI/O28SSI0Clk
SSI
SSI module 0 frame signalTTLI/O29SSI0Fss
SSI module 0 receiveTTLI30SSI0Rx
SSI module 0 transmitTTLO31SSI0Tx
SSI module 1 clockTTLI/O72SSI1Clk
SSI module 1 frame signalTTLI/O73SSI1Fss
SSI module 1 receiveTTLI74SSI1Rx
SSI module 1 transmitTTLO75SSI1Tx
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI65CMOD0
System Control &
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI76CMOD1
Main oscillator crystal input or an external clock
reference input.
AnalogI48OSC0
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
AnalogO49OSC1
System reset input.TTLI64RST
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLI26U0Rx
UART
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLO27U0Tx
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLI12U1Rx
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLO13U1Tx
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLI19U2Rx
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLO18U2Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.1.4 GPIO Pins and Alternate Functions
Table 19-4. GPIO Pins and Alternate Functions
Multiplexed FunctionMultiplexed FunctionPin NumberIO
U0Rx26PA0
U0Tx27PA1
SSI0Clk28PA2
SSI0Fss29PA3
SSI0Rx30PA4
SSI0Tx31PA5
CCP134PA6
CCP435PA7
PWM266PB0
PWM367PB1
June 18, 2012642
Texas Instruments-Production Data
Signal Tables
Table 19-4. GPIO Pins and Alternate Functions (continued)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
I2C0SCL70PB2
I2C0SDA71PB3
C0-92PB4
C1-91PB5
C0oC0+90PB6
TRST89PB7
SWCLKTCK80PC0
SWDIOTMS79PC1
TDI78PC2
SWOTDO77PC3
CCP525PC4
C1oC1+24PC5
C2oC2+23PC6
C2-22PC7
PWM010PD0
PhA011PD1
U1Rx12PD2
U1Tx13PD3
CCP095PD4
CCP296PD5
Fault99PD6
IDX0100PD7
SSI1Clk72PE0
SSI1Fss73PE1
SSI1Rx74PE2
SSI1Tx75PE3
CCP36PE4
5PE5
PWM42PE6
PWM51PE7
PhB047PF0
PWM161PF1
LED160PF2
LED059PF3
U2Rx19PG0
U2Tx18PG1
643June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
19.2 108-Ball BGA Package Pin Tables
19.2.1 Signals by Pin Number
Table 19-5. Signals by Pin Number
DescriptionBuffer Typea
Pin TypePin NamePin Number
No connect. Leave the pin electrically unconnected/isolated.--NCA1
No connect. Leave the pin electrically unconnected/isolated.--NCA2
No connect. Leave the pin electrically unconnected/isolated.--NCA3
No connect. Leave the pin electrically unconnected/isolated.--NCA4
The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
Power-GNDA
A5
GPIO port B bit 4.TTLI/OPB4
A6 Analog comparator 0 negative input.AnalogIC0-
GPIO port B bit 6.TTLI/OPB6
A7 Analog comparator 0 positive input.AnalogIC0+
Analog comparator 0 output.TTLOC0o
GPIO port B bit 7.TTLI/OPB7
A8 JTAG TRST.TTLITRST
GPIO port C bit 0.TTLI/OPC0
A9 JTAG/SWD CLK.TTLISWCLK
JTAG/SWD CLK.TTLITCK
GPIO port C bit 3.TTLI/OPC3
A10 JTAG TDO and SWO.TTLOSWO
JTAG TDO and SWO.TTLOTDO
GPIO port E bit 0.TTLI/OPE0
A11 SSI module 1 clockTTLI/OSSI1Clk
GPIO port E bit 3.TTLI/OPE3
A12 SSI module 1 transmitTTLOSSI1Tx
No connect. Leave the pin electrically unconnected/isolated.--NCB1
No connect. Leave the pin electrically unconnected/isolated.--NCB2
No connect. Leave the pin electrically unconnected/isolated.--NCB3
No connect. Leave the pin electrically unconnected/isolated.--NCB4
The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
Power-GNDA
B5
Ground reference for logic and I/O pins.Power-GND
B6
GPIO port B bit 5.TTLI/OPB5
B7 Analog comparator 1 negative input.AnalogIC1-
GPIO port C bit 2.TTLI/OPC2
B8 JTAG TDI.TTLITDI
GPIO port C bit 1.TTLI/OPC1
B9 JTAG TMS and SWDIO.TTLI/OSWDIO
JTAG TMS and SWDIO.TTLI/OTMS
June 18, 2012644
Texas Instruments-Production Data
Signal Tables
Table 19-5. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD1
B10
GPIO port E bit 2.TTLI/OPE2
B11 SSI module 1 receiveTTLISSI1Rx
GPIO port E bit 1.TTLI/OPE1
B12 SSI module 1 frame signalTTLI/OSSI1Fss
GPIO port E bit 7.TTLI/OPE7
C1 PWM 5. This signal is controlled by PWM Generator 2.TTLOPWM5
GPIO port E bit 6.TTLI/OPE6
C2 PWM 4. This signal is controlled by PWM Generator 2.TTLOPWM4
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
C3
Ground reference for logic and I/O pins.Power-GND
C4
Ground reference for logic and I/O pins.Power-GND
C5
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 661, regardless of system implementation.
Power-VDDA
C6
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 661, regardless of system implementation.
Power-VDDA
C7
GND of the Ethernet PHY.Power-GNDPHY
C8
GND of the Ethernet PHY.Power-GNDPHY
C9
VCC of the Ethernet PHY.Power-VCCPHY
C10
GPIO port B bit 2.TTLI/OPB2
C11 I2C module 0 clock.ODI/OI2C0SCL
GPIO port B bit 3.TTLI/OPB3
C12 I2C module 0 data.ODI/OI2C0SDA
GPIO port E bit 4.TTLI/OPE4
D1 Capture/Compare/PWM 3.TTLI/OCCP3
GPIO port E bit 5.TTLI/OPE5
D2
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
D3
VCC of the Ethernet PHY.Power-VCCPHY
D10
VCC of the Ethernet PHY.Power-VCCPHY
D11
GPIO port B bit 1.TTLI/OPB1
D12 PWM 3. This signal is controlled by PWM Generator 1.TTLOPWM3
GPIO port D bit 4.TTLI/OPD4
E1 Capture/Compare/PWM 0.TTLI/OCCP0
645June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-5. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
GPIO port D bit 5.TTLI/OPD5
E2 Capture/Compare/PWM 2.TTLI/OCCP2
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
Power-LDO
E3
Positive supply for I/O and some logic.Power-VDD33
E10
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD0
E11
GPIO port B bit 0.TTLI/OPB0
E12 PWM 2. This signal is controlled by PWM Generator 1.TTLOPWM2
GPIO port D bit 7.TTLI/OPD7
F1 QEI module 0 index.TTLIIDX0
GPIO port D bit 6.TTLI/OPD6
F2 PWM Fault.TTLIFault
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
F3
Ground reference for logic and I/O pins.Power-GND
F10
Ground reference for logic and I/O pins.Power-GND
F11
Ground reference for logic and I/O pins.Power-GND
F12
GPIO port D bit 0.TTLI/OPD0
G1 PWM 0. This signal is controlled by PWM Generator 0.TTLOPWM0
GPIO port D bit 1.TTLI/OPD1
G2 QEI module 0 phase A.TTLIPhA0
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
G3
Positive supply for I/O and some logic.Power-VDD33
G10
Positive supply for I/O and some logic.Power-VDD33
G11
Positive supply for I/O and some logic.Power-VDD33
G12
GPIO port D bit 3.TTLI/OPD3
H1 UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
TTLOU1Tx
GPIO port D bit 2.TTLI/OPD2
H2 UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
TTLIU1Rx
Ground reference for logic and I/O pins.Power-GND
H3
Positive supply for I/O and some logic.Power-VDD33
H10
System reset input.TTLIRST
H11
GPIO port F bit 1.TTLI/OPF1
H12 PWM 1. This signal is controlled by PWM Generator 0.TTLOPWM1
Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect
this pin to ground when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
TTLOXTALNPHY
J1
Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
TTLIXTALPPHY
J2
June 18, 2012646
Texas Instruments-Production Data
Signal Tables
Table 19-5. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
Ground reference for logic and I/O pins.Power-GND
J3
Ground reference for logic and I/O pins.Power-GND
J10
GPIO port F bit 2.TTLI/OPF2
J11 Ethernet LED 1.TTLOLED1
GPIO port F bit 3.TTLI/OPF3
J12 Ethernet LED 0.TTLOLED0
GPIO port G bit 0.TTLI/OPG0
K1 UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
TTLIU2Rx
GPIO port G bit 1.TTLI/OPG1
K2 UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
TTLOU2Tx
12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.AnalogIERBIAS
K3
GND of the Ethernet PHY.Power-GNDPHY
K4
Ground reference for logic and I/O pins.Power-GND
K5
Ground reference for logic and I/O pins.Power-GND
K6
Positive supply for I/O and some logic.Power-VDD33
K7
Positive supply for I/O and some logic.Power-VDD33
K8
Positive supply for I/O and some logic.Power-VDD33
K9
Ground reference for logic and I/O pins.Power-GND
K10
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
AnalogIXOSC0
K11
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
AnalogOXOSC1
K12
GPIO port C bit 4.TTLI/OPC4
L1 Capture/Compare/PWM 5.TTLI/OCCP5
GPIO port C bit 7.TTLI/OPC7
L2 Analog comparator 2 negative input.AnalogIC2-
GPIO port A bit 0.TTLI/OPA0
L3 UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
TTLIU0Rx
GPIO port A bit 3.TTLI/OPA3
L4 SSI module 0 frame signalTTLI/OSSI0Fss
GPIO port A bit 4.TTLI/OPA4
L5 SSI module 0 receiveTTLISSI0Rx
GPIO port A bit 6.TTLI/OPA6
L6 Capture/Compare/PWM 1.TTLI/OCCP1
RXIN of the Ethernet PHY.AnalogIRXIN
L7
TXON of the Ethernet PHY.AnalogOTXON
L8
MDIO of the Ethernet PHY.TTLI/OMDIO
L9
Ground reference for logic and I/O pins.Power-GND
L10
Main oscillator crystal input or an external clock reference input.AnalogIOSC0
L11
647June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-5. Signals by Pin Number (continued)
DescriptionBuffer Typea
Pin TypePin NamePin Number
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
Power-VBAT
L12
GPIO port C bit 5.TTLI/OPC5
M1 Analog comparator 1 positive input.AnalogIC1+
Analog comparator 1 output.TTLOC1o
GPIO port C bit 6.TTLI/OPC6
M2 Analog comparator 2 positive input.AnalogIC2+
Analog comparator 2 output.TTLOC2o
GPIO port A bit 1.TTLI/OPA1
M3 UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
TTLOU0Tx
GPIO port A bit 2.TTLI/OPA2
M4 SSI module 0 clockTTLI/OSSI0Clk
GPIO port A bit 5.TTLI/OPA5
M5 SSI module 0 transmitTTLOSSI0Tx
GPIO port A bit 7.TTLI/OPA7
M6 Capture/Compare/PWM 4.TTLI/OCCP4
RXIP of the Ethernet PHY.AnalogIRXIP
M7
TXOP of the Ethernet PHY.AnalogOTXOP
M8
GPIO port F bit 0.TTLI/OPF0
M9 QEI module 0 phase B.TTLIPhB0
An external input that brings the processor out of Hibernate mode
when asserted.
TTLIWAKE
M10
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
AnalogOOSC1
M11
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODOHIB
M12
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.2.2 Signals by Signal Name
Table 19-6. Signals by Signal Name
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Analog comparator 0 positive input.AnalogIA7C0+
Analog comparator 0 negative input.AnalogIA6C0-
Analog comparator 0 output.TTLOA7C0o
Analog comparator 1 positive input.AnalogIM1C1+
Analog comparator 1 negative input.AnalogIB7C1-
Analog comparator 1 output.TTLOM1C1o
Analog comparator 2 positive input.AnalogIM2C2+
Analog comparator 2 negative input.AnalogIL2C2-
Analog comparator 2 output.TTLOM2C2o
Capture/Compare/PWM 0.TTLI/OE1CCP0
June 18, 2012648
Texas Instruments-Production Data
Signal Tables
Table 19-6. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
Capture/Compare/PWM 1.TTLI/OL6CCP1
Capture/Compare/PWM 2.TTLI/OE2CCP2
Capture/Compare/PWM 3.TTLI/OD1CCP3
Capture/Compare/PWM 4.TTLI/OM6CCP4
Capture/Compare/PWM 5.TTLI/OL1CCP5
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLIE11CMOD0
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLIB10CMOD1
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
AnalogIK3ERBIAS
PWM Fault.TTLIF2Fault
Ground reference for logic and I/O pins.Power-B6
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
GND
The ground reference for the analog circuits ( Analog
Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
Power-A5
B5
GNDA
GND of the Ethernet PHY.Power-C8
C9
K4
GNDPHY
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODOM12HIB
I2C module 0 clock.ODI/OC11I2C0SCL
I2C module 0 data.ODI/OC12I2C0SDA
QEI module 0 index.TTLIF1IDX0
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. The LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
Power-E3LDO
Ethernet LED 0.TTLOJ12LED0
Ethernet LED 1.TTLOJ11LED1
MDIO of the Ethernet PHY.TTLI/OL9MDIO
649June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-6. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
No connect. Leave the pin electrically unconnected/isolated.--A1
A2
A3
A4
B1
B2
B3
B4
NC
Main oscillator crystal input or an external clock reference
input.
AnalogIL11OSC0
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
AnalogOM11OSC1
GPIO port A bit 0.TTLI/OL3PA0
GPIO port A bit 1.TTLI/OM3PA1
GPIO port A bit 2.TTLI/OM4PA2
GPIO port A bit 3.TTLI/OL4PA3
GPIO port A bit 4.TTLI/OL5PA4
GPIO port A bit 5.TTLI/OM5PA5
GPIO port A bit 6.TTLI/OL6PA6
GPIO port A bit 7.TTLI/OM6PA7
GPIO port B bit 0.TTLI/OE12PB0
GPIO port B bit 1.TTLI/OD12PB1
GPIO port B bit 2.TTLI/OC11PB2
GPIO port B bit 3.TTLI/OC12PB3
GPIO port B bit 4.TTLI/OA6PB4
GPIO port B bit 5.TTLI/OB7PB5
GPIO port B bit 6.TTLI/OA7PB6
GPIO port B bit 7.TTLI/OA8PB7
GPIO port C bit 0.TTLI/OA9PC0
GPIO port C bit 1.TTLI/OB9PC1
GPIO port C bit 2.TTLI/OB8PC2
GPIO port C bit 3.TTLI/OA10PC3
GPIO port C bit 4.TTLI/OL1PC4
GPIO port C bit 5.TTLI/OM1PC5
GPIO port C bit 6.TTLI/OM2PC6
GPIO port C bit 7.TTLI/OL2PC7
GPIO port D bit 0.TTLI/OG1PD0
GPIO port D bit 1.TTLI/OG2PD1
GPIO port D bit 2.TTLI/OH2PD2
GPIO port D bit 3.TTLI/OH1PD3
GPIO port D bit 4.TTLI/OE1PD4
GPIO port D bit 5.TTLI/OE2PD5
GPIO port D bit 6.TTLI/OF2PD6
GPIO port D bit 7.TTLI/OF1PD7
June 18, 2012650
Texas Instruments-Production Data
Signal Tables
Table 19-6. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
GPIO port E bit 0.TTLI/OA11PE0
GPIO port E bit 1.TTLI/OB12PE1
GPIO port E bit 2.TTLI/OB11PE2
GPIO port E bit 3.TTLI/OA12PE3
GPIO port E bit 4.TTLI/OD1PE4
GPIO port E bit 5.TTLI/OD2PE5
GPIO port E bit 6.TTLI/OC2PE6
GPIO port E bit 7.TTLI/OC1PE7
GPIO port F bit 0.TTLI/OM9PF0
GPIO port F bit 1.TTLI/OH12PF1
GPIO port F bit 2.TTLI/OJ11PF2
GPIO port F bit 3.TTLI/OJ12PF3
GPIO port G bit 0.TTLI/OK1PG0
GPIO port G bit 1.TTLI/OK2PG1
QEI module 0 phase A.TTLIG2PhA0
QEI module 0 phase B.TTLIM9PhB0
PWM 0. This signal is controlled by PWM Generator 0.TTLOG1PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLOH12PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLOE12PWM2
PWM 3. This signal is controlled by PWM Generator 1.TTLOD12PWM3
PWM 4. This signal is controlled by PWM Generator 2.TTLOC2PWM4
PWM 5. This signal is controlled by PWM Generator 2.TTLOC1PWM5
System reset input.TTLIH11RST
RXIN of the Ethernet PHY.AnalogIL7RXIN
RXIP of the Ethernet PHY.AnalogIM7RXIP
SSI module 0 clockTTLI/OM4SSI0Clk
SSI module 0 frame signalTTLI/OL4SSI0Fss
SSI module 0 receiveTTLIL5SSI0Rx
SSI module 0 transmitTTLOM5SSI0Tx
SSI module 1 clockTTLI/OA11SSI1Clk
SSI module 1 frame signalTTLI/OB12SSI1Fss
SSI module 1 receiveTTLIB11SSI1Rx
SSI module 1 transmitTTLOA12SSI1Tx
JTAG/SWD CLK.TTLIA9SWCLK
JTAG TMS and SWDIO.TTLI/OB9SWDIO
JTAG TDO and SWO.TTLOA10SWO
JTAG/SWD CLK.TTLIA9TCK
JTAG TDI.TTLIB8TDI
JTAG TDO and SWO.TTLOA10TDO
JTAG TMS and SWDIO.TTLI/OB9TMS
JTAG TRST.TTLIA8TRST
651June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-6. Signals by Signal Name (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin Name
TXON of the Ethernet PHY.AnalogOL8TXON
TXOP of the Ethernet PHY.AnalogOM8TXOP
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIL3U0Rx
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOM3U0Tx
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIH2U1Rx
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOH1U1Tx
UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIK1U2Rx
UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOK2U2Tx
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
Power-L12VBAT
VCC of the Ethernet PHY.Power-C10
D10
D11
VCCPHY
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-C3
D3
F3
G3
VDD25
Positive supply for I/O and some logic.Power-E10
G10
G11
G12
H10
K7
K8
K9
VDD33
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to
minimize the electrical noise contained on VDD from affecting
the analog functions. VDDA pins must be supplied with a
voltage that meets the specification in “Recommended DC
Operating Conditions” on page 661, regardless of system
implementation.
Power-C6
C7
VDDA
An external input that brings the processor out of Hibernate
mode when asserted.
TTLIM10WAKE
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
AnalogIK11XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
AnalogOK12XOSC1
Ethernet PHY XTALN 25-MHz oscillator crystal output.
Connect this pin to ground when using a single-ended 25-MHz
clock input connected to the XTALPPHY pin.
TTLOJ1XTALNPHY
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
TTLIJ2XTALPPHY
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 18, 2012652
Texas Instruments-Production Data
Signal Tables
19.2.3 Signals by Function, Except for GPIO
Table 19-7. Signals by Function, Except for GPIO
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
Analog comparator 0 positive input.AnalogIA7C0+
Analog Comparators
Analog comparator 0 negative input.AnalogIA6C0-
Analog comparator 0 output.TTLOA7C0o
Analog comparator 1 positive input.AnalogIM1C1+
Analog comparator 1 negative input.AnalogIB7C1-
Analog comparator 1 output.TTLOM1C1o
Analog comparator 2 positive input.AnalogIM2C2+
Analog comparator 2 negative input.AnalogIL2C2-
Analog comparator 2 output.TTLOM2C2o
12.4-kΩ resistor (1% precision) used internally for
Ethernet PHY.
AnalogIK3ERBIAS
Ethernet
GND of the Ethernet PHY.Power-C8
C9
K4
GNDPHY
Ethernet LED 0.TTLOJ12LED0
Ethernet LED 1.TTLOJ11LED1
MDIO of the Ethernet PHY.TTLI/OL9MDIO
RXIN of the Ethernet PHY.AnalogIL7RXIN
RXIP of the Ethernet PHY.AnalogIM7RXIP
TXON of the Ethernet PHY.AnalogOL8TXON
TXOP of the Ethernet PHY.AnalogOM8TXOP
VCC of the Ethernet PHY.Power-C10
D10
D11
VCCPHY
Ethernet PHY XTALN 25-MHz oscillator crystal
output. Connect this pin to ground when using a
single-ended 25-MHz clock input connected to the
XTALPPHY pin.
TTLOJ1XTALNPHY
Ethernet PHY XTALP 25-MHz oscillator crystal
input or external clock reference input.
TTLIJ2XTALPPHY
Capture/Compare/PWM 0.TTLI/OE1CCP0
General-Purpose
Timers
Capture/Compare/PWM 1.TTLI/OL6CCP1
Capture/Compare/PWM 2.TTLI/OE2CCP2
Capture/Compare/PWM 3.TTLI/OD1CCP3
Capture/Compare/PWM 4.TTLI/OM6CCP4
Capture/Compare/PWM 5.TTLI/OL1CCP5
653June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-7. Signals by Function, Except for GPIO (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
An open-drain output with internal pull-up that
indicates the processor is in Hibernate mode.
ODOM12HIB
Hibernate
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
Power-L12VBAT
An external input that brings the processor out of
Hibernate mode when asserted.
TTLIM10WAKE
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
AnalogIK11XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
AnalogOK12XOSC1
I2C module 0 clock.ODI/OC11I2C0SCL
I2C I2C module 0 data.ODI/OC12I2C0SDA
JTAG/SWD CLK.TTLIA9SWCLK
JTAG/SWD/SWO
JTAG TMS and SWDIO.TTLI/OB9SWDIO
JTAG TDO and SWO.TTLOA10SWO
JTAG/SWD CLK.TTLIA9TCK
JTAG TDI.TTLIB8TDI
JTAG TDO and SWO.TTLOA10TDO
JTAG TMS and SWDIO.TTLI/OB9TMS
JTAG TRST.TTLIA8TRST
PWM Fault.TTLIF2Fault
PWM
PWM 0. This signal is controlled by PWM Generator
0.
TTLOG1PWM0
PWM 1. This signal is controlled by PWM Generator
0.
TTLOH12PWM1
PWM 2. This signal is controlled by PWM Generator
1.
TTLOE12PWM2
PWM 3. This signal is controlled by PWM Generator
1.
TTLOD12PWM3
PWM 4. This signal is controlled by PWM Generator
2.
TTLOC2PWM4
PWM 5. This signal is controlled by PWM Generator
2.
TTLOC1PWM5
June 18, 2012654
Texas Instruments-Production Data
Signal Tables
Table 19-7. Signals by Function, Except for GPIO (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
Ground reference for logic and I/O pins.Power-B6
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
GND
Power
The ground reference for the analog circuits (
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
Power-A5
B5
GNDA
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
Power-E3LDO
Positive supply for most of the logic function,
including the processor core and most peripherals.
Power-C3
D3
F3
G3
VDD25
Positive supply for I/O and some logic.Power-E10
G10
G11
G12
H10
K7
K8
K9
VDD33
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in “Recommended DC Operating
Conditions” on page 661, regardless of system
implementation.
Power-C6
C7
VDDA
QEI module 0 index.TTLIF1IDX0
QEI QEI module 0 phase A.TTLIG2PhA0
QEI module 0 phase B.TTLIM9PhB0
655June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 19-7. Signals by Function, Except for GPIO (continued)
DescriptionBuffer Typea
Pin TypePin NumberPin NameFunction
SSI module 0 clockTTLI/OM4SSI0Clk
SSI
SSI module 0 frame signalTTLI/OL4SSI0Fss
SSI module 0 receiveTTLIL5SSI0Rx
SSI module 0 transmitTTLOM5SSI0Tx
SSI module 1 clockTTLI/OA11SSI1Clk
SSI module 1 frame signalTTLI/OB12SSI1Fss
SSI module 1 receiveTTLIB11SSI1Rx
SSI module 1 transmitTTLOA12SSI1Tx
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTLIE11CMOD0
System Control &
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTLIB10CMOD1
Main oscillator crystal input or an external clock
reference input.
AnalogIL11OSC0
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
AnalogOM11OSC1
System reset input.TTLIH11RST
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLIL3U0Rx
UART
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLOM3U0Tx
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLIH2U1Rx
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLOH1U1Tx
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLIK1U2Rx
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLOK2U2Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.2.4 GPIO Pins and Alternate Functions
Table 19-8. GPIO Pins and Alternate Functions
Multiplexed FunctionMultiplexed FunctionPin NumberIO
U0RxL3PA0
U0TxM3PA1
SSI0ClkM4PA2
SSI0FssL4PA3
SSI0RxL5PA4
SSI0TxM5PA5
CCP1L6PA6
CCP4M6PA7
PWM2E12PB0
PWM3D12PB1
June 18, 2012656
Texas Instruments-Production Data
Signal Tables
Table 19-8. GPIO Pins and Alternate Functions (continued)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
I2C0SCLC11PB2
I2C0SDAC12PB3
C0-A6PB4
C1-B7PB5
C0oC0+A7PB6
TRSTA8PB7
SWCLKTCKA9PC0
SWDIOTMSB9PC1
TDIB8PC2
SWOTDOA10PC3
CCP5L1PC4
C1oC1+M1PC5
C2oC2+M2PC6
C2-L2PC7
PWM0G1PD0
PhA0G2PD1
U1RxH2PD2
U1TxH1PD3
CCP0E1PD4
CCP2E2PD5
FaultF2PD6
IDX0F1PD7
SSI1ClkA11PE0
SSI1FssB12PE1
SSI1RxB11PE2
SSI1TxA12PE3
CCP3D1PE4
D2PE5
PWM4C2PE6
PWM5C1PE7
PhB0M9PF0
PWM1H12PF1
LED1J11PF2
LED0J12PF3
U2RxK1PG0
U2TxK2PG1
19.3 Connections for Unused Signals
Table 19-9 on page 658 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 100-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
657June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
Table 19-9. Connections for Unused Signals (100-pin LQFP)
Preferred PracticeAcceptable PracticePin NumberSignal NameFunction
Connect to GND through
12.4-kΩ resistor.
Connect to GND through
12.4-kΩ resistor.
41ERBIAS
Ethernet
GNDGND42
85
86
GNDPHY
NCNC58MDIOa
GNDNC37RXIN
GNDNC40RXIP
GNDNC46TXON
GNDNC43TXOP
VDDVDD36
83
84
VCCPHY
NCNC17XTALNPHYa
GNDNC16XTALPPHYa
GNDNC-All unused GPIOsGPIO
NCNC51HIB
Hibernate
GNDNC55VBAT
GNDNC50WAKE
GNDNC52XOSC0
NCNC53XOSC1
NCNC-NCNo Connects
GNDNC48OSC0
System
Control
NCNC49OSC1
Connect through a capacitor to
GND as close to pin as possible
Pull up as shown in Figure
5-1 on page 172
64RST
a. Note that the Ethernet PHY is powered up by default. The PHY cannot be powered down unless a clock source is provided
and the MDIO pin is pulled up through a 10-kΏ resistor.
Table 19-10 on page 659 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 108-pin BGA package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
June 18, 2012658
Texas Instruments-Production Data
Signal Tables
Table 19-10. Connections for Unused Signals, 108-pin BGA
Preferred PracticeAcceptable PracticePin NumberSignal NameFunction
Connect to GND through
12.4-kΩ resistor.
Connect to GND through
12.4-kΩ resistor.
K3ERBIAS
Ethernet
GNDGNDC8
C9
K4
GNDPHY
NCNCL9MDIOa
GNDNCL7RXIN
GNDNCM7RXIP
GNDNCL8TXON
GNDNCM8TXOP
VDDVDDC10
D10
D11
VCCPHY
NCNCJ1XTALNPHYa
GNDNCJ2XTALPPHYa
GNDNC-All unused GPIOsGPIO
NCNCM12HIB
Hibernate
GNDNCL12VBAT
GNDNCM10WAKE
GNDNCK11XOSC0
NCNCK12XOSC1
NCNC-NCNo
Connects
GNDNCL11OSC0
System
Control
NCNCM11OSC1
Connect through a capacitor to
GND as close to pin as possible
Pull up as shown in Figure
5-1 on page 172
H11RST
a. Note that the Ethernet PHY is powered up by default. The PHY cannot be powered down unless a clock source is provided
and the MDIO pin is pulled up through a 10-kΏ resistor.
659June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
20 Operating Characteristics
Table 20-1. Temperature Characteristics
UnitValueSymbolCharacteristic
°C-40 to +85TA
Industrial operating temperature range
°C-65 to +150TS
Unpowered storage temperature range
Table 20-2. Thermal Characteristics
UnitValueSymbolCharacteristic
°C/W32ΘJA
Thermal resistance (junction to ambient)a
°CTA+ (P • ΘJA)TJ
Junction temperatureb
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
Table 20-3. ESD Absolute Maximum Ratingsa
UnitMaxNomMinParameter Name
kV2.0--VESDHBM
kV1.0--VESDCDM
V100--VESDMM
a. All Stellaris parts are ESD tested following the JEDEC standard.
June 18, 2012660
Texas Instruments-Production Data
Operating Characteristics
21 Electrical Characteristics
21.1 DC Characteristics
21.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 21-1. Maximum Ratings
Unit
Value
Symbol
Characteristica
MaxMin
V40VDD
I/O supply voltage (VDD)
V30VDD25
Core supply voltage (VDD25)
V40VDDA
Analog supply voltage (VDDA)
V40VBAT
Battery supply voltage (VBAT)
V40VCCPHY
Ethernet PHY supply voltage (VCCPHY)
V5.5-0.3
VIN
Input voltage
VVDD + 0.3-0.3Input voltage for a GPIO configured as an analog input
mA25-IMaximum current per output pins
mV300-VNON
Maximum input voltage on a non-power pin when the
microcontroller is unpowered
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
21.1.2 Recommended DC Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
Table 21-2. Recommended DC Operating Conditions
UnitMaxNomMinParameter NameParameter
V3.63.33.0I/O supply voltageVDD
V2.752.52.25Core supply voltageVDD25
V3.63.33.0Analog supply voltageVDDA
V3.63.02.3Battery supply voltageVBAT
V3.63.33.0Ethernet PHY supply voltageVCCPHY
661June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 21-2. Recommended DC Operating Conditions (continued)
UnitMaxNomMinParameter NameParameter
V5.0-2.0High-level input voltageVIH
V1.3--0.3Low-level input voltageVIL
V--2.4High-level output voltageVOH
a
V0.4--Low-level output voltageVOLa
High-level source current, VOH=2.4 V
IOH
mA--2.02-mA Drive
mA--4.04-mA Drive
mA--8.08-mA Drive
Low-level sink current, VOL=0.4 V
IOL
mA--2.02-mA Drive
mA--4.04-mA Drive
mA--8.08-mA Drive
a. VOL and VOH shift to 1.2 V when using high-current GPIOs.
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 21-3. LDO Regulator Characteristics
UnitMaxNomMinParameter NameParameter
V2.752.52.25Programmable internal (logic) power supply
output value
VLDOOUT
%-2%-Output voltage accuracy
µs100--Power-on timetPON
µs200--Time ontON
µs100--Time offtOFF
mV-50-Step programming incremental voltageVSTEP
µF3.0-1.0External filter capacitor size for internal power
supply
CLDO
21.1.4 GPIO Module Characteristics
Table 21-4. GPIO Module DC Characteristics
UnitMaxNomMinParameter NameParameter
kΩ110-50GPIO internal pull-up resistorRGPIOPU
kΩ180-55GPIO internal pull-down resistorRGPIOPD
µA2--GPIO input leakage currenta
ILKG
a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is
measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.
21.1.5 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
June 18, 2012662
Texas Instruments-Production Data
Electrical Characteristics
■ VDD25 = 2.50 V
■ VBAT = 3.0 V
■ VDDA = 3.3 V
■ VDDPHY = 3.3 V
■ Temperature = 25°C
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
Table 21-5. Detailed Power Specifications
Unit
3.0 V VBAT
2.5 V VDD25
3.3 V VDD,
VDDA, VDDPHY
Conditions
Parameter
Name
Parameter
MaxNomMaxNomMaxNom
mApendinga
0pendinga
108pendinga
48VDD25 = 2.50 V
Code= while(1){} executed out of
Flash
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(Flash loop)
IDD_RUN
mApendinga
0pendinga
52pendinga
5VDD25 = 2.50 V
Code= while(1){} executed out of
Flash
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(Flash loop)
mApendinga
0pendinga
100pendinga
48VDD25 = 2.50 V
Code= while(1){} executed in
SRAM
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(SRAM loop)
mApendinga
0pendinga
45pendinga
5VDD25 = 2.50 V
Code= while(1){} executed in
SRAM
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(SRAM loop)
mApendinga
0pendinga
16pendinga
5VDD25 = 2.50 V
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Sleep modeIDD_SLEEP
mApendinga
0pendinga
0.21pendinga
4.6LDO = 2.25 V
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Deep-Sleep
mode
IDD_DEEPSLEEP
663June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 21-5. Detailed Power Specifications (continued)
Unit
3.0 V VBAT
2.5 V VDD25
3.3 V VDD,
VDDA, VDDPHY
Conditions
Parameter
Name
Parameter
MaxNomMaxNomMaxNom
µApendinga
160000VBAT = 3.0 V
VDD = 0 V
VDD25 = 0 V
VDDA = 0 V
VDDPHY = 0 V
Peripherals = All OFF
System Clock = OFF
Hibernate Module = 32 kHz
Hibernate
mode
IDD_HIBERNATE
a. Pending characterization completion.
21.1.6 Flash Memory Characteristics
Table 21-6. Flash Memory Characteristics
UnitMaxNomMinParameter NameParameter
cycles-100,00010,000Number of guaranteed program/erase cycles
before failurea
PECYC
years--10Data retention at average operating
temperature of 85˚C
TRET
µs--20Word program timeTPROG
ms--20Page erase timeTERASE
ms250--Mass erase timeTME
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
21.1.7 Hibernation
Table 21-7. Hibernation Module DC Characteristics
UnitValueParameter NameParameter
V2.35Low battery detect voltageVLOWBAT
kΩ200WAKE internal pull-up resistorRWAKEPU
21.1.8 Ethernet Controller
Table 21-8. Ethernet Controller DC Characteristics
UnitValueParameter NameParameter
Ω12.4K ± 1 %Value of the pull-down resistor on the ERBIAS pinREBIAS
21.2 AC Characteristics
21.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
June 18, 2012664
Texas Instruments-Production Data
Electrical Characteristics
Figure 21-1. Load Conditions
CL= 50 pF
GND
pin
21.2.2 Clocks
Table 21-9. Phase Locked Loop (PLL) Characteristics
UnitMaxNomMinParameter NameParameter
MHz8.192-3.579545Crystal referencea
fref_crystal
MHz8.192-3.579545External clock referencea
fref_ext
MHz-400-PLL frequencyb
fpll
ms0.5--PLL lock timeTREADY
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 21-10 on page 665 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 21-10. Actual PLL Frequency
ErrorPLL Frequency (MHz)Crystal Frequency (MHz)XTAL
0.0023%400.9043.57950x4
0.0047%398.13123.68640x5
-4004.00x6
0.0035%401.4084.0960x7
0.0047%398.13124.91520x8
-4005.00x9
0.0016%399.365.120xA
-4006.00xB
0.0016%399.366.1440xC
0.0047%398.13127.37280xD
0.0047%4008.00xE
0.0033%398.67733338.1920xF
Table 21-11. Clock Characteristics
UnitMaxNomMinParameter NameParameter
MHz15.6128.4Internal 12 MHz oscillator frequencyfIOSC
KHz453015Internal 30 KHz oscillator frequencyfIOSC30KHZ
MHz-4.194304-Hibernation module oscillator frequencyfXOSC
MHz-4.194304-Crystal reference for hibernation oscillatorfXOSC_XTAL
665June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 21-11. Clock Characteristics (continued)
UnitMaxNomMinParameter NameParameter
KHz-32.768-External clock reference for hibernation
module
fXOSC_EXT
MHz8.192-1Main oscillator frequencyfMOSC
ns1000-125Main oscillator periodtMOSC_per
MHz8.192-1Crystal reference using the main oscillator
(PLL in BYPASS mode)
fref_crystal_bypass
MHz50-0External clock reference (PLL in BYPASS
mode)
fref_ext_bypass
MHz50-0System clockfsystem_clock
Table 21-12. Crystal Characteristics
UnitsValueParameter Name
MHz3.5468Frequency
ppm±50±50±50±50Frequency tolerance
ppm/yr±5±5±5±5Aging
-ParallelParallelParallelParallelOscillation mode
ppm±25±25±25±25Temperature stability (-40°C to 85°C)
pF63.555.637.027.8Motional capacitance (typ)
mH32.728.619.114.3Motional inductance (typ)
Ω220200160120Equivalent series resistance (max)
pF10101010Shunt capacitance (max)
pF16161616Load capacitance (typ)
µW100100100100Drive level (typ)
21.2.3 JTAG and Boundary Scan
Table 21-13. JTAG Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
MHz10-0TCK operational clock frequencyfTCK
J1
ns--100TCK operational clock periodtTCK
J2
ns-tTCK/2-TCK clock Low timetTCK_LOW
J3
ns-tTCK/2-TCK clock High timetTCK_HIGH
J4
ns10-0TCK rise timetTCK_R
J5
ns10-0TCK fall timetTCK_F
J6
ns--20TMS setup time to TCK risetTMS_SU
J7
ns--20TMS hold time from TCK risetTMS_HLD
J8
ns--25TDI setup time to TCK risetTDI_SU
J9
ns--25TDI hold time from TCK risetTDI_HLD
J10
ns3523
-
2-mA drive
TCK fall to Data
Valid from High-Z
J11
tTDO_ZDV
ns26154-mA drive
ns25148-mA drive
ns29188-mA drive with slew rate control
June 18, 2012666
Texas Instruments-Production Data
Electrical Characteristics
Table 21-13. JTAG Characteristics (continued)
UnitMaxNomMinParameter NameParameterParameter
No.
ns3521
-
2-mA drive
TCK fall to Data
Valid from Data
Valid
J12
tTDO_DV
ns25144-mA drive
ns24138-mA drive
ns28188-mA drive with slew rate control
ns119
-
2-mA drive
TCK fall to High-Z
from Data Valid
J13
tTDO_DVZ
ns974-mA drive
ns868-mA drive
ns978-mA drive with slew rate control
ns--100TRST assertion timetTRST
J14
ns--10TRST setup time to TCK risetTRST_SU
J15
Figure 21-2. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 21-3. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8J8J7
667June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 21-4. JTAG TRST Timing
TCK
J14 J15
TRST
21.2.4 Reset
Table 21-14. Reset Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
V-2.0-Reset thresholdVTH
R1
V2.952.92.85Brown-Out thresholdVBTH
R2
ms-10-Power-On Reset timeoutTPOR
R3
µs-500-Brown-Out timeoutTBOR
R4
ms11-6Internal reset timeout after PORTIRPOR
R5
µs1-0Internal reset timeout after BORa
TIRBOR
R6
ms1-0Internal reset timeout after hardware reset
(RST pin)
TIRHWR
R7
µs20-2.5Internal reset timeout after software-initiated
system reset a
TIRSWR
R8
µs20-2.5Internal reset timeout after watchdog reseta
TIRWDR
R9
ms100--Supply voltage (VDD) rise time (0V-3.3V),
power on reset
TVDDRISE
R10 µs250--Supply voltage (VDD) rise time (0V-3.3V),
waking from hibernation
µs--2Minimum RST pulse widthTMIN
R11
a. 20 * t MOSC_per
Figure 21-5. External Reset Timing (RST)
RST
/Reset
(Internal)
R7
R11
June 18, 2012668
Texas Instruments-Production Data
Electrical Characteristics
Figure 21-6. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 21-7. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
Figure 21-8. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 21-9. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
669June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
21.2.5 Sleep Modes
Table 21-15. Sleep Modes AC Characteristicsa
UnitMaxNomMinParameter NameParameterParameter No
system clocks7--Time to wake from interrupt in sleep or
deep-sleep mode, not using the PLL
tWAKE_S
D1
msTREADY
--Time to wake from interrupt in sleep or
deep-sleep mode when using the PLL
tWAKE_PLL_S
D2
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
21.2.6 Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 VDC or powered down with the same external voltage
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.
Table 21-16. Hibernation Module AC Characteristics
UnitMaxNomMinParameter NameParameterParameter
No
μs-200-Internal 32.768 KHz clock reference rising
edge to /HIB asserted
tHIB_LOW
H1
μs-30-Internal 32.768 KHz clock reference rising
edge to /HIB deasserted
tHIB_HIGH
H2
μs--62/WAKE assertion timetWAKE_ASSERT
H3
μs124-62/WAKE assert to /HIB desasserttWAKETOHIB
H4
ms--20XOSC settling timea
tXOSC_SETTLE
H5
μs--92Access time to or from a non-volatile register
in HIB module to complete
tHIB_REG_ACCESS
H6
μs250--HIB deassert to VDD and VDD25 at minimum
operational level
tHIB_TO_VDD
H7
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 21-10. Hibernation Module Timing
32.768 KHz
(internal)
HIB
H4
H1
WAKE
H2
H3
21.2.7 General-Purpose I/O (GPIO)
Note: All GPIOs are 5 V-tolerant.
June 18, 2012670
Texas Instruments-Production Data
Electrical Characteristics
Table 21-17. GPIO Characteristics
UnitMaxNomMinConditionParameter NameParameter
ns2617
-
2-mA drive
GPIO Rise Time
(from 20% to 80%
of VDD)
tGPIOR
ns1394-mA drive
ns968-mA drive
ns12108-mA drive with slew rate control
ns2517
-
2-mA drive
GPIO Fall Time
(from 80% to 20%
of VDD)
tGPIOF
ns1284-mA drive
ns1068-mA drive
ns13118-mA drive with slew rate control
21.2.8 Synchronous Serial Interface (SSI)
Table 21-18. SSI Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
system clocks65024-2SSIClk cycle timetclk_per
S1
t clk_per-0.5-SSIClk high timetclk_high
S2
t clk_per-0.5-SSIClk low timetclk_low
S3
ns106-SSIClk rise/fall timea
tclkrf
S4
system clocks1-0Data from master valid delay timetDMd
S5
system clocks--1Data from master setup timetDMs
S6
system clocks--2Data from master hold timetDMh
S7
system clocks--1Data from slave setup timetDSs
S8
system clocks--2Data from slave hold timetDSh
S9
a. Note that the delays shown are using 8-mA drive strength.
Figure 21-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
671June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
Figure 21-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S9S8
MSB
21.2.9 Inter-Integrated Circuit (I2C) Interface
Table 21-19. I2C Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
system clocks--36Start condition hold timetSCH
I1a
system clocks--36Clock Low periodtLP
I2a
ns(see note
b)
--I2CSCL/I2CSDA rise time (VIL =0.5 V
to V IH =2.4 V)
tSRT
I3b
June 18, 2012672
Texas Instruments-Production Data
Electrical Characteristics
Table 21-19. I2C Characteristics (continued)
UnitMaxNomMinParameter NameParameterParameter
No.
system clocks--2Data hold timetDH
I4a
ns109-I2CSCL/I2CSDA fall time (VIH =2.4 V
to V IL =0.5 V)
tSFT
I5c
system clocks--24Clock High timetHT
I6a
system clocks--18Data setup timetDS
I7a
system clocks--36Start condition setup time (for repeated
start condition only)
tSCSR
I8a
system clocks--24Stop condition setup timetSCS
I9a
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 21-14. I2C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
21.2.10 Ethernet Controller
Table 21-20. 100BASE-TX Transmitter Characteristicsa
UnitMaxNomMinParameter Name
mVpk1050-950Peak output amplitude
%102-98Output amplitude symmetry
%5--Output overshoot
ns5-3Rise/Fall time
ps500--Rise/Fall time imbalance
ps---Duty cycle distortion
ns1.4--Jitter
a. Measured at the line side of the transformer.
Table 21-21. 100BASE-TX Transmitter Characteristics (informative)a
UnitMaxNomMinParameter Name
dB--16Return loss
µH--350Open-circuit inductance
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
673June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 21-22. 100BASE-TX Receiver Characteristics
UnitMaxNomMinParameter Name
mVppd-700600Signal detect assertion threshold
mVppd-425350Signal detect de-assertion threshold
kΩ-20-Differential input resistance
ns--4Jitter tolerance (pk-pk)
%+75--75Baseline wander tracking
µs1000--Signal detect assertion time
µs4--Signal detect de-assertion time
Table 21-23. 10BASE-T Transmitter Characteristicsa
UnitMaxNomMinParameter Name
V2.8-2.2Peak differential output signal
dB--27Harmonic content
ns-100-Link pulse width
ns-300
350
-Start-of-idle pulse width
a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using
the procedures found in Clause 14 of IEEE 802.3.
Table 21-24. 10BASE-T Transmitter Characteristics (informative)a
UnitMaxNomMinParameter Name
dB--15Output return loss
dB--29-17log(f/10)Output impedance balance
mV50--Peak common-mode output voltage
mV100--Common-mode rejection
ns1--Common-mode rejection jitter
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 21-25. 10BASE-T Receiver Characteristics
UnitMaxNomMinParameter Name
ns--30Jitter tolerance (pk-pk)
mVppd700600500Input squelched threshold
kΩ-20-Differential input resistance
V--25Common-mode rejection
Table 21-26. Isolation Transformersa
ConditionValueName
+/- 5%1 CT : 1 CTTurns ratio
@ 10 mV, 10 kHz350 uH (min)Open-circuit inductance
@ 1 MHz (min)0.40 uH (max)Leakage inductance
25 pF (max)Inter-winding capacitance
0.9 Ohm (max)DC resistance
June 18, 2012674
Texas Instruments-Production Data
Electrical Characteristics
Table 21-26. Isolation Transformers (continued)
ConditionValueName
0-65 MHz0.4 dB (typ)Insertion loss
Vrms1500HIPOT
a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode
chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer
characteristics.
Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the
transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be
compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO)
bits in the MR19 register.
Table 21-27. Ethernet Reference Crystala
ConditionValueName
MHz25.00000Frequency
PPM±50Frequency tolerance
PPM/yr±2Aging
PPM±5Temperature stability (-40° to 85°)
Parallel resonance, fundamental modeOscillation mode
Parameters at 25° C ±2° C; Drive level = 0.5 mW
µW50-100Drive level (typ)
pF10Shunt capacitance (max)
fF10Motional capacitance (min)
Ω60Series resistance (max)
> 5 dB below main within 500 kHzSpurious response (max)
a. If the internal crystal oscillator is used, select a crystal that meets these specifications.
Figure 21-15. External XTLP Oscillator Characteristics
Tclkper
Tr
Tclkhi Tclklo
Tf
675June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Table 21-28. External XTLP Oscillator Characteristics
UnitMaxNomMinSymbolParameter Name
-0.8--XTLNILV
XTLN Input Low Voltage
--25.0-XTLPf
XTLP Frequencya
--40-Tclkper
XTLP Periodb
%60
60
-40
40
XTLPDC
XTLP Duty Cycle
ns4.0--Tr, Tf
Rise/Fall Time
ns0.1--TJITTER
Absolute Jitter
a. IEEE 802.3 frequency tolerance ±50 ppm.
b. IEEE 802.3 frequency tolerance ±50 ppm.
21.2.11 Analog Comparator
Table 21-29. Analog Comparator Characteristics
UnitMaxNomMinParameter NameParameter
mV±25±10-Input offset voltageVOS
VVDD-1.5-0Input common mode voltage rangeVCM
dB--50Common mode rejection ratioCMRR
µs1--Response timeTRT
µs10--Comparator mode change to Output ValidTMC
Table 21-30. Analog Comparator Voltage Reference Characteristics
UnitMaxNomMinParameter NameParameter
LSB-VDD/31-Resolution high rangeRHR
LSB-VDD/23-Resolution low rangeRLR
LSB±1/2--Absolute accuracy high rangeAHR
LSB±1/4--Absolute accuracy low rangeALR
June 18, 2012676
Texas Instruments-Production Data
Electrical Characteristics
A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris®serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 438 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
677June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 680).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
June 18, 2012678
Texas Instruments-Production Data
Serial Flash Loader
flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
679June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
June 18, 2012680
Texas Instruments-Production Data
Serial Flash Loader
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
681June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
B Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
The Cortex-M3 Processor
R0, type R/W, , reset - (see page 58)
DATA
DATA
R1, type R/W, , reset - (see page 58)
DATA
DATA
R2, type R/W, , reset - (see page 58)
DATA
DATA
R3, type R/W, , reset - (see page 58)
DATA
DATA
R4, type R/W, , reset - (see page 58)
DATA
DATA
R5, type R/W, , reset - (see page 58)
DATA
DATA
R6, type R/W, , reset - (see page 58)
DATA
DATA
R7, type R/W, , reset - (see page 58)
DATA
DATA
R8, type R/W, , reset - (see page 58)
DATA
DATA
R9, type R/W, , reset - (see page 58)
DATA
DATA
R10, type R/W, , reset - (see page 58)
DATA
DATA
R11, type R/W, , reset - (see page 58)
DATA
DATA
R12, type R/W, , reset - (see page 58)
DATA
DATA
SP, type R/W, , reset - (see page 59)
SP
SP
LR, type R/W, , reset 0xFFFF.FFFF (see page 60)
LINK
LINK
PC, type R/W, , reset - (see page 61)
PC
PC
June 18, 2012682
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
PSR, type R/W, , reset 0x0100.0000 (see page 62)
THUMBICI / ITQVCZN
ISRNUMICI / IT
PRIMASK, type R/W, , reset 0x0000.0000 (see page 66)
PRIMASK
FAULTMASK, type R/W, , reset 0x0000.0000 (see page 67)
FAULTMASK
BASEPRI, type R/W, , reset 0x0000.0000 (see page 68)
BASEPRI
CONTROL, type R/W, , reset 0x0000.0000 (see page 69)
TMPLASP
Cortex-M3 Peripherals
System Timer (SysTick) Registers
Base 0xE000.E000
STCTRL, type R/W, offset 0x010, reset 0x0000.0000
COUNT
ENABLEINTENCLK_SRC
STRELOAD, type R/W, offset 0x014, reset 0x0000.0000
RELOAD
RELOAD
STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000
CURRENT
CURRENT
Cortex-M3 Peripherals
Nested Vectored Interrupt Controller (NVIC) Registers
Base 0xE000.E000
EN0, type R/W, offset 0x100, reset 0x0000.0000
INT
INT
EN1, type R/W, offset 0x104, reset 0x0000.0000
INT
DIS0, type R/W, offset 0x180, reset 0x0000.0000
INT
INT
DIS1, type R/W, offset 0x184, reset 0x0000.0000
INT
PEND0, type R/W, offset 0x200, reset 0x0000.0000
INT
INT
PEND1, type R/W, offset 0x204, reset 0x0000.0000
INT
UNPEND0, type R/W, offset 0x280, reset 0x0000.0000
INT
INT
683June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
UNPEND1, type R/W, offset 0x284, reset 0x0000.0000
INT
ACTIVE0, type RO, offset 0x300, reset 0x0000.0000
INT
INT
ACTIVE1, type RO, offset 0x304, reset 0x0000.0000
INT
PRI0, type R/W, offset 0x400, reset 0x0000.0000
INTCINTD
INTAINTB
PRI1, type R/W, offset 0x404, reset 0x0000.0000
INTCINTD
INTAINTB
PRI2, type R/W, offset 0x408, reset 0x0000.0000
INTCINTD
INTAINTB
PRI3, type R/W, offset 0x40C, reset 0x0000.0000
INTCINTD
INTAINTB
PRI4, type R/W, offset 0x410, reset 0x0000.0000
INTCINTD
INTAINTB
PRI5, type R/W, offset 0x414, reset 0x0000.0000
INTCINTD
INTAINTB
PRI6, type R/W, offset 0x418, reset 0x0000.0000
INTCINTD
INTAINTB
PRI7, type R/W, offset 0x41C, reset 0x0000.0000
INTCINTD
INTAINTB
PRI8, type R/W, offset 0x420, reset 0x0000.0000
INTCINTD
INTAINTB
PRI9, type R/W, offset 0x424, reset 0x0000.0000
INTCINTD
INTAINTB
PRI10, type R/W, offset 0x428, reset 0x0000.0000
INTCINTD
INTAINTB
SWTRIG, type WO, offset 0xF00, reset 0x0000.0000
INTID
Cortex-M3 Peripherals
System Control Block (SCB) Registers
Base 0xE000.E000
CPUID, type RO, offset 0xD00, reset 0x411F.C231
CONVARIMP
REVPARTNO
June 18, 2012684
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000
VECPENDISRPENDISRPRE
PENDSTCLRPENDSTSETUNPENDSV
PENDSVNMISET
VECACTRETBASEVECPEND
VTABLE, type R/W, offset 0xD08, reset 0x0000.0000
OFFSETBASE
OFFSET
APINT, type R/W, offset 0xD0C, reset 0xFA05.0000
VECTKEY
VECTRESET
VECTCLRACT
SYSRESREQ
PRIGROUP
ENDIANESS
SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000
SLEEPEXITSLEEPDEEPSEVONPEND
CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000
BASETHR
MAINPENDUNALIGNED
DIV0
BFHFNMIGNSTKALIGN
SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000
USAGE
MEMBUS
SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000
SVC
SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000
PENDSVTICK
DEBUG
SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000
MEMBUSUSAGE
MEMABUSAUSGASVCAMONPNDSVTICKUSAGEPMEMPBUSPSVC
FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000
UNDEFINVSTATINVPCNOCPUNALIGNDIV0
IERRDERRMUSTKEMSTKEMMARVIBUSPRECISEIMPREBUSTKEBSTKEBFARV
HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000
FORCEDDBG
VECT
MMADDR, type R/W, offset 0xD34, reset -
ADDR
ADDR
FAULTADDR, type R/W, offset 0xD38, reset -
ADDR
ADDR
Cortex-M3 Peripherals
Memory Protection Unit (MPU) Registers
Base 0xE000.E000
MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800
IREGION
SEPARATE
DREGION
MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000
ENABLE
HFNMIENAPRIVDEFEN
MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000
NUMBER
685June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000
ADDR
REGIONVALIDADDR
MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000
ADDR
REGIONVALIDADDR
MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000
ADDR
REGIONVALIDADDR
MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000
ADDR
REGIONVALIDADDR
MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000
BCSTEXAPXN
ENABLESIZESRD
MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000
BCSTEXAPXN
ENABLESIZESRD
MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000
BCSTEXAPXN
ENABLESIZESRD
MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000
BCSTEXAPXN
ENABLESIZESRD
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset - (see page 185)
CLASSVER
MINORMAJOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 187)
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 (see page 188)
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 189)
BORRISPLLLRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 190)
BORIMPLLLIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 191)
BORMISPLLLMIS
RESC, type R/W, offset 0x05C, reset - (see page 192)
EXTPORBORWDTSW
RCC, type R/W, offset 0x060, reset 0x078E.3AD1 (see page 193)
PWMDIV
USEPWMDIVUSESYSDIV
SYSDIVACG
MOSCDISIOSCDISOSCSRCXTALBYPASSPWRDN
PLLCFG, type RO, offset 0x064, reset - (see page 197)
RF
June 18, 2012686
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
RCC2, type R/W, offset 0x070, reset 0x0780.2810 (see page 198)
SYSDIV2USERCC2
OSCSRC2BYPASS2PWRDN2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 200)
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset - (see page 201)
PARTNOFAMVER
QUALROHSPKGTEMPPINCOUNT
DC0, type RO, offset 0x008, reset 0x00FF.007F (see page 203)
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0010.30DF (see page 204)
PWM
JTAGSWDSWOWDTPLLHIBMPUMINSYSDIV
DC2, type RO, offset 0x014, reset 0x070F.1137 (see page 206)
TIMER0TIMER1TIMER2TIMER3COMP0COMP1COMP2
UART0UART1UART2SSI0SSI1QEI0I2C0
DC3, type RO, offset 0x018, reset 0xBF00.FFFF (see page 208)
CCP0CCP1CCP2CCP3CCP4CCP532KHZ
PWM0PWM1PWM2PWM3PWM4PWM5C0MINUSC0PLUSC0OC1MINUSC1PLUSC1OC2MINUSC2PLUSC2O
PWMFAULT
DC4, type RO, offset 0x01C, reset 0x5100.007F (see page 210)
E1588EMAC0EPHY0
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOG
RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 212)
PWM
WDTHIB
SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 214)
PWM
WDTHIB
DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 216)
PWM
WDTHIB
RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 218)
TIMER0TIMER1TIMER2TIMER3COMP0COMP1COMP2
UART0UART1UART2SSI0SSI1QEI0I2C0
SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 221)
TIMER0TIMER1TIMER2TIMER3COMP0COMP1COMP2
UART0UART1UART2SSI0SSI1QEI0I2C0
DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 224)
TIMER0TIMER1TIMER2TIMER3COMP0COMP1COMP2
UART0UART1UART2SSI0SSI1QEI0I2C0
RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 227)
EMAC0EPHY0
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOG
SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 229)
EMAC0EPHY0
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOG
DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 231)
EMAC0EPHY0
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOG
687June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 233)
PWM
WDTHIB
SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 234)
TIMER0TIMER1TIMER2TIMER3COMP0COMP1COMP2
UART0UART1UART2SSI0SSI1QEI0I2C0
SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 236)
EMAC0EPHY0
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOG
Hibernation Module
Base 0x400F.C000
HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 (see page 246)
RTCC
RTCC
HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF (see page 247)
RTCM0
RTCM0
HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF (see page 248)
RTCM1
RTCM1
HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF (see page 249)
RTCLD
RTCLD
HIBCTL, type R/W, offset 0x010, reset 0x8000.0000 (see page 250)
RTCENHIBREQCLKSELRTCWENPINWEN
LOWBATEN
CLK32ENVABORT
HIBIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 252)
RTCALT0RTCALT1LOWBATEXTW
HIBRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 253)
RTCALT0RTCALT1LOWBATEXTW
HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 254)
RTCALT0RTCALT1LOWBATEXTW
HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 (see page 255)
RTCALT0RTCALT1LOWBATEXTW
HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF (see page 256)
TRIM
HIBDATA, type R/W, offset 0x030-0x12C, reset - (see page 257)
RTD
RTD
Internal Memory
Flash Memory Control Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
June 18, 2012688
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
WRITEERASEMERASECOMT
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
ARISPRIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
AMASKPMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
AMISCPMISC
Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
DATANW
DBG0DBG1DATA
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
DATANW
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
DATANW
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
689June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 297)
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 298)
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 299)
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 300)
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 301)
IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 302)
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 303)
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 304)
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 305)
IC
GPIOAFSEL, type R/W, offset 0x420, reset - (see page 306)
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 308)
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 309)
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 310)
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 311)
ODE
June 18, 2012690
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
GPIOPUR, type R/W, offset 0x510, reset - (see page 312)
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 313)
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 314)
SRL
GPIODEN, type R/W, offset 0x51C, reset - (see page 315)
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 316)
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset - (see page 317)
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 319)
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 320)
PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 321)
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 322)
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 323)
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 324)
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 325)
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 326)
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 327)
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 328)
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 329)
CID2
691June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 330)
CID3
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 344)
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 345)
TAMRTACMRTAAMS
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 347)
TBMRTBCMRTBAMS
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 349)
TAENTASTALLTAEVENTRTCENTAPWMLTBENTBSTALLTBEVENTTBPWML
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 352)
TATOIMCAMIMCAEIMRTCIMTBTOIMCBMIMCBEIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 354)
TATORISCAMRISCAERISRTCRISTBTORISCBMRISCBERIS
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 355)
TATOMISCAMMISCAEMISRTCMISTBTOMISCBMMISCBEMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 356)
TATOCINT
CAMCINTCAECINTRTCCINT
TBTOCINT
CBMCINTCBECINT
GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 358)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 359)
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 360)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 361)
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 362)
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 363)
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 364)
TAPSMR
June 18, 2012692
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 365)
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 366)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 367)
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 372)
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 373)
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (see page 374)
INTENRESEN
WDTICR, type WO, offset 0x00C, reset - (see page 375)
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 376)
WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 377)
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 378)
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 379)
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 380)
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 381)
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 382)
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 383)
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 384)
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 385)
PID1
693June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 386)
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 387)
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 388)
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 389)
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 390)
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 391)
CID3
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 402)
DATAFEPEBEOE
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) (see page 404)
FEPEBEOE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) (see page 404)
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 406)
BUSYRXFETXFFRXFFTXFE
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 408)
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 409)
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 410)
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 411)
BRKPENEPSSTP2FENWLENSPS
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 413)
UARTENSIRENSIRLPLBETXERXE
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 415)
TXIFLSELRXIFLSEL
June 18, 2012694
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 417)
RXIMTXIMRTIMFEIMPEIMBEIMOEIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F (see page 419)
RXRISTXRISRTRISFERISPERISBERISOERIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 420)
RXMISTXMISRTMISFEMISPEMISBEMISOEMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 421)
RXICTXICRTICFEICPEICBEICOEIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 423)
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 424)
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 425)
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 426)
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 427)
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 428)
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 429)
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 430)
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 431)
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 432)
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 433)
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 434)
CID3
695June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 448)
DSSFRFSPOSPHSCR
SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 450)
LBMSSEMSSOD
SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 452)
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 453)
TFETNFRNERFFBSY
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 455)
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 456)
RORIMRTIMRXIMTXIM
SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 458)
RORRISRTRISRXRISTXRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 459)
RORMISRTMISRXMISTXMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 460)
RORICRTIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 461)
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 462)
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 463)
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 464)
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 465)
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 466)
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 467)
PID2
June 18, 2012696
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 468)
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 469)
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 470)
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 471)
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 472)
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
R/SSA
I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads)
BUSYERRORADRACKDATACKARBLSTIDLEBUSBSY
I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes)
RUNSTARTSTOPACK
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
LPBKMFESFE
697June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
Inter-Integrated Circuit (I2C) Interface
I2C Slave
I2C 0 base: 0x4002.0000
I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Reads)
RREQTREQFBR
I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Writes)
DA
I2CSDR, type R/W, offset 0x808, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000
DATAIM
I2CSRIS, type RO, offset 0x810, reset 0x0000.0000
DATARIS
I2CSMIS, type RO, offset 0x814, reset 0x0000.0000
DATAMIS
I2CSICR, type WO, offset 0x818, reset 0x0000.0000
DATAIC
Ethernet Controller
Ethernet MAC
Base 0x4004.8000
MACRIS/MACIACK, type RO, offset 0x000, reset 0x0000.0000 (Reads)
RXINTTXERTXEMPFOVRXERMDINTPHYINT
MACRIS/MACIACK, type WO, offset 0x000, reset 0x0000.0000 (Writes)
RXINTTXERTXEMPFOVRXERMDINTPHYINT
MACIM, type R/W, offset 0x004, reset 0x0000.007F
RXINTMTXERMTXEMPMFOVMRXERMMDINTMPHYINTM
MACRCTL, type R/W, offset 0x008, reset 0x0000.0008
RXENAMULPRMSBADCRCRSTFIFO
MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000
TXENPADENCRCDUPLEX
MACDATA, type RO, offset 0x010, reset 0x0000.0000 (Reads)
RXDATA
RXDATA
MACDATA, type WO, offset 0x010, reset 0x0000.0000 (Writes)
TXDATA
TXDATA
June 18, 2012698
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
MACIA0, type R/W, offset 0x014, reset 0x0000.0000
MACOCT3MACOCT4
MACOCT1MACOCT2
MACIA1, type R/W, offset 0x018, reset 0x0000.0000
MACOCT5MACOCT6
MACTHR, type R/W, offset 0x01C, reset 0x0000.003F
THRESH
MACMCTL, type R/W, offset 0x020, reset 0x0000.0000
STARTWRITEREGADR
MACMDV, type R/W, offset 0x024, reset 0x0000.0080
DIV
MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000
MDTX
MACMRXD, type R/W, offset 0x030, reset 0x0000.0000
MDRX
MACNP, type RO, offset 0x034, reset 0x0000.0000
NPR
MACTR, type R/W, offset 0x038, reset 0x0000.0000
NEWTX
MACTS, type R/W, offset 0x03C, reset 0x0000.0000
TSEN
Ethernet Controller
MII Management
MR0, type R/W, address 0x00, reset 0x3100
COLTDUPLEXRANEGISOPWRDNANEGENSPEEDSLLOOPBKRESET
MR1, type RO, address 0x01, reset 0x7849
EXTDJABLINKANEGARFAULTANEGCMFPS10T_H10T_F100X_H100X_F
MR2, type RO, address 0x02, reset 0x000E
OUI[21:6]
MR3, type RO, address 0x03, reset 0x7237
RNMNOUI[5:0]
MR4, type R/W, address 0x04, reset 0x01E1
SA0A1A2A3RFNP
MR5, type RO, address 0x05, reset 0x0000
SA[7:0]RFACKNP
MR6, type RO, address 0x06, reset 0x0000
LPANEGAPRXLPNPAPDF
MR16, type R/W, address 0x10, reset 0x0140
RXCCPCSBPRVSPOLAPOLNL10SQEITXHIMINPOLRPTR
MR17, type R/W, address 0x11, reset 0x0000
ANEGCOMP_INTRFAULT_INT
LSCHG_INTLPACK_INT
PDF_INTPRX_INT
RXER_INT
JABBER_INTANEGCOMP_IE
RFAULT_IELSCHG_IELPACK_IE
PDF_IEPRX_IERXER_IE
JABBER_IE
MR18, type RO, address 0x12, reset 0x0000
RX_LOCKRXSDRATEDPLXANEGF
699June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
MR19, type R/W, address 0x13, reset 0x4000
TXO
MR23, type R/W, address 0x17, reset 0x0010
LED0[3:0]LED1[3:0]
MR24, type R/W, address 0x18, reset 0x00C0
MDIX_SDMDIX_CMMDIXAUTO_SWPD_MODE
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 565)
IN0IN1IN2
ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 566)
IN0IN1IN2
ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 567)
IN0IN1IN2
ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 568)
VREFRNGEN
ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 569)
OVAL
ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 (see page 569)
OVAL
ACSTAT2, type RO, offset 0x060, reset 0x0000.0000 (see page 569)
OVAL
ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 570)
CINVISENISLVALASRCP
ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 570)
CINVISENISLVALASRCP
ACCTL2, type R/W, offset 0x064, reset 0x0000.0000 (see page 570)
CINVISENISLVALASRCP
Pulse Width Modulator (PWM)
Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 582)
GlobalSync0GlobalSync1GlobalSync2
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 (see page 583)
Sync0Sync1Sync2
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 (see page 584)
PWM0EnPWM1EnPWM2EnPWM3EnPWM4EnPWM5En
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 585)
PWM0InvPWM1InvPWM2InvPWM3InvPWM4InvPWM5Inv
June 18, 2012700
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 (see page 586)
Fault0Fault1Fault2Fault3Fault4Fault5
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 (see page 587)
IntFault
IntPWM0IntPWM1IntPWM2
PWMRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 588)
IntFault
IntPWM0IntPWM1IntPWM2
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 589)
IntFault
IntPWM0IntPWM1IntPWM2
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 590)
Fault
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 591)
EnableModeDebugLoadUpdCmpAUpdCmpBUpd
PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 591)
EnableModeDebugLoadUpdCmpAUpdCmpBUpd
PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 591)
EnableModeDebugLoadUpdCmpAUpdCmpBUpd
PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 (see page 593)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 (see page 593)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 (see page 593)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 (see page 595)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 (see page 595)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 (see page 595)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 (see page 596)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000 (see page 596)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000 (see page 596)
IntCntZeroIntCntLoad
IntCmpAUIntCmpADIntCmpBUIntCmpBD
701June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 (see page 597)
Load
PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000 (see page 597)
Load
PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000 (see page 597)
Load
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 (see page 598)
Count
PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000 (see page 598)
Count
PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000 (see page 598)
Count
PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 (see page 599)
CompA
PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000 (see page 599)
CompA
PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000 (see page 599)
CompA
PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 (see page 600)
CompB
PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 (see page 600)
CompB
PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 (see page 600)
CompB
PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 (see page 601)
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBD
PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 601)
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBD
PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000 (see page 601)
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBD
PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 (see page 604)
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBD
PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 604)
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBD
June 18, 2012702
Texas Instruments-Production Data
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000 (see page 604)
ActZeroActLoadActCmpAUActCmpADActCmpBUActCmpBD
PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 (see page 607)
Enable
PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 607)
Enable
PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000 (see page 607)
Enable
PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 (see page 608)
RiseDelay
PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000 (see page 608)
RiseDelay
PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000 (see page 608)
RiseDelay
PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 (see page 609)
FallDelay
PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 609)
FallDelay
PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 (see page 609)
FallDelay
Quadrature Encoder Interface (QEI)
QEI0 base: 0x4002.C000
QEICTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 616)
EnableSwapSigModeCapModeResModeVelEnVelDivINVAINVBINVISTALLEN
QEISTAT, type RO, offset 0x004, reset 0x0000.0000 (see page 618)
Error
Direction
QEIPOS, type R/W, offset 0x008, reset 0x0000.0000 (see page 619)
Position
Position
QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000 (see page 620)
MaxPos
MaxPos
QEILOAD, type R/W, offset 0x010, reset 0x0000.0000 (see page 621)
Load
Load
QEITIME, type RO, offset 0x014, reset 0x0000.0000 (see page 622)
Time
Time
QEICOUNT, type RO, offset 0x018, reset 0x0000.0000 (see page 623)
Count
Count
703June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
16171819202122232425262728293031
0123456789101112131415
QEISPEED, type RO, offset 0x01C, reset 0x0000.0000 (see page 624)
Speed
Speed
QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000 (see page 625)
IntIndexIntTimer
IntDir
IntError
QEIRIS, type RO, offset 0x024, reset 0x0000.0000 (see page 626)
IntIndexIntTimer
IntDir
IntError
QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000 (see page 627)
IntIndexIntTimer
IntDir
IntError
June 18, 2012704
Texas Instruments-Production Data
Register Quick Reference
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
Temperature
Package Speed
Revision
Shipping Medium
E = –40°C to +105°C
I = –40°C to +85°C
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
BZ = 108-ball BGA
QC = 100-pin LQFP
QN = 48-pin LQFP
QR = 64-pin LQFP
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
80 = 80 MHz
nnn = Sandstorm-class parts
nnnn = All other Stellaris® parts
Table C-1. Part Ordering Information
DescriptionOrderable Part Number
Stellaris®LM3S6950 Microcontroller Industrial Temperature 108-ball BGALM3S6950-IBZ50-A2
Stellaris LM3S6950 Microcontroller Industrial Temperature 108-ball BGA
Tape-and-reel
LM3S6950-IBZ50-A2T
Stellaris LM3S6950 Microcontroller Industrial Temperature 100-pin LQFPLM3S6950-IQC50-A2
Stellaris LM3S6950 Microcontroller Industrial Temperature 100-pin LQFP
Tape-and-reel
LM3S6950-IQC50-A2T
C.2 Part Markings
The Stellaris microcontrollers are marked with an identifying number. This code contains the following
information:
■ The first line indicates the part number, for example, LM3S9B90.
■ In the second line, the first eight characters indicate the temperature, package, speed, revision,
and product status. For example in the figure below, IQC80C0X indicates an Industrial temperature
(I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. The letter immediately
following the revision indicates product status. An X indicates experimental and requires a waiver;
an S indicates the part is fully qualified and released to production.
■ The remaining characters contain internal tracking numbers.
705June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
C.3 Kits
The Stellaris Family provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers
before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor.
C.4 Support Information
For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you:
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm.
June 18, 2012706
Texas Instruments-Production Data
Ordering and Contact Information
D Package Information
D.1 100-Pin LQFP Package
D.1.1 Package Dimensions
Figure D-1. Stellaris LM3S6950 100-Pin LQFP Package Dimensions
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
707June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Body +2.00 mm Footprint, 1.4 mm package thickness
100LLeadsSymbols
1.60Max.A
0.05 Min./0.15 Max.-A1
1.40±0.05A2
16.00±0.20D
14.00±0.05D1
16.00±0.20E
14.00±0.05E1
0.60+0.15/-0.10L
0.50Basice
0.22+0.05b
0˚-7˚-θ
0.08Max.ddd
0.08Max.ccc
MS-026JEDEC Reference Drawing
BEDVariation Designator
June 18, 2012708
Texas Instruments-Production Data
Package Information
D.1.2 Tray Dimensions
Figure D-2. 100-Pin LQFP Tray Dimensions
D.1.3 Tape and Reel Dimensions
Note: In the figure that follows, pin 1 is located in the top right corner of the device.
709June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions
PRINTED ON
MUST NOT BE REPRODUCED WITHOUT WRITTEN
PERMISSION FROM SUMICARRIER (S) PTE LTD
06.01.2003
THIS IS A COMPUTER GENERATED
UNCONTROLLED DOCUMENT
06.01.2003
06.01.2003
06.01.2003
06.01.2003
June 18, 2012710
Texas Instruments-Production Data
Package Information
D.2 108-Ball BGA Package
D.2.1 Package Dimensions
Figure D-4. Stellaris LM3S6950 108-Ball BGA Package Dimensions
711June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
Note: The following notes apply to the package drawing.
MAXNOMMINSymbols
1.501.361.22A
0.390.340.29A1
0.750.700.65A3
0.360.320.28c
10.1510.009.85D
8.80 BSCD1
10.1510.009.85E
8.80 BSCE1
0.530.480.43b
.20bbb
.12ddd
0.80 BSCe
-0.60-f
12M
108n
REF: JEDEC MO-219F
June 18, 2012712
Texas Instruments-Production Data
Package Information
D.2.2 Tray Dimensions
Figure D-5. 108-Ball BGA Tray Dimensions
713June 18, 2012
Texas Instruments-Production Data
Stellaris®LM3S6950 Microcontroller
D.2.3 Tape and Reel Dimensions
Figure D-6. 108-Ball BGA Tape and Reel Dimensions
C-PAK PTE LTD
June 18, 2012714
Texas Instruments-Production Data
Package Information
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2012, Texas Instruments Incorporated
