TE X AS I NS TRUM E NTS - P RO DUCTION D ATA (R) Stellaris LM3S6950 Microcontroller D ATA SHE E T D S -LM3S 6950 - 1 2 7 4 6 . 2 5 1 5 S P M S 142H C o p yri g h t (c) 2 0 07-2012 Te xa s In stru me n ts In co rporated Copyright Copyright (c) 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare(R) are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table of Contents Revision History ............................................................................................................................. 24 About This Document .................................................................................................................... 30 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 30 30 30 31 1 Architectural Overview .......................................................................................... 33 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 Product Features .......................................................................................................... Target Applications ........................................................................................................ High-Level Block Diagram ............................................................................................. Functional Overview ...................................................................................................... ARM CortexTM-M3 ......................................................................................................... Motor Control Peripherals .............................................................................................. Analog Peripherals ........................................................................................................ Serial Communications Peripherals ................................................................................ System Peripherals ....................................................................................................... Memory Peripherals ...................................................................................................... Additional Features ....................................................................................................... Hardware Details .......................................................................................................... 33 41 42 44 44 45 46 46 48 48 49 49 2 The Cortex-M3 Processor ...................................................................................... 51 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 Block Diagram .............................................................................................................. 52 Overview ...................................................................................................................... 53 System-Level Interface .................................................................................................. 53 Integrated Configurable Debug ...................................................................................... 53 Trace Port Interface Unit (TPIU) ..................................................................................... 54 Cortex-M3 System Component Details ........................................................................... 54 Programming Model ...................................................................................................... 55 Processor Mode and Privilege Levels for Software Execution ........................................... 55 Stacks .......................................................................................................................... 55 Register Map ................................................................................................................ 56 Register Descriptions .................................................................................................... 57 Exceptions and Interrupts .............................................................................................. 70 Data Types ................................................................................................................... 70 Memory Model .............................................................................................................. 70 Memory Regions, Types and Attributes ........................................................................... 72 Memory System Ordering of Memory Accesses .............................................................. 72 Behavior of Memory Accesses ....................................................................................... 72 Software Ordering of Memory Accesses ......................................................................... 73 Bit-Banding ................................................................................................................... 74 Data Storage ................................................................................................................ 76 Synchronization Primitives ............................................................................................. 77 Exception Model ........................................................................................................... 78 Exception States ........................................................................................................... 79 Exception Types ............................................................................................................ 79 Exception Handlers ....................................................................................................... 82 June 18, 2012 3 Texas Instruments-Production Data Table of Contents 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 Vector Table .................................................................................................................. 82 Exception Priorities ....................................................................................................... 83 Interrupt Priority Grouping .............................................................................................. 84 Exception Entry and Return ........................................................................................... 84 Fault Handling .............................................................................................................. 86 Fault Types ................................................................................................................... 87 Fault Escalation and Hard Faults .................................................................................... 87 Fault Status Registers and Fault Address Registers ........................................................ 88 Lockup ......................................................................................................................... 88 Power Management ...................................................................................................... 88 Entering Sleep Modes ................................................................................................... 89 Wake Up from Sleep Mode ............................................................................................ 89 Instruction Set Summary ............................................................................................... 90 3 Cortex-M3 Peripherals ........................................................................................... 93 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.3 3.4 3.5 3.6 Functional Description ................................................................................................... 93 System Timer (SysTick) ................................................................................................. 93 Nested Vectored Interrupt Controller (NVIC) .................................................................... 94 System Control Block (SCB) .......................................................................................... 96 Memory Protection Unit (MPU) ....................................................................................... 96 Register Map .............................................................................................................. 101 System Timer (SysTick) Register Descriptions .............................................................. 103 NVIC Register Descriptions .......................................................................................... 107 System Control Block (SCB) Register Descriptions ........................................................ 120 Memory Protection Unit (MPU) Register Descriptions .................................................... 147 4 JTAG Interface ...................................................................................................... 157 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. JTAG Interface Pins ..................................................................................................... JTAG TAP Controller ................................................................................................... Shift Registers ............................................................................................................ Operational Considerations .......................................................................................... Initialization and Configuration ..................................................................................... Register Descriptions .................................................................................................. Instruction Register (IR) ............................................................................................... Data Registers ............................................................................................................ 158 158 159 159 161 162 162 165 165 165 168 5 System Control ..................................................................................................... 170 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 5.4 5.5 Signal Description ....................................................................................................... Functional Description ................................................................................................. Device Identification .................................................................................................... Reset Control .............................................................................................................. Power Control ............................................................................................................. Clock Control .............................................................................................................. System Control ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 4 170 170 171 171 175 176 181 182 183 184 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 6 Hibernation Module .............................................................................................. 237 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Register Access Timing ............................................................................................... Clock Source .............................................................................................................. Battery Management ................................................................................................... Real-Time Clock .......................................................................................................... Battery-Backed Memory .............................................................................................. Power Control ............................................................................................................. Initiating Hibernate ...................................................................................................... Interrupts and Status ................................................................................................... Initialization and Configuration ..................................................................................... Initialization ................................................................................................................. RTC Match Functionality (No Hibernation) .................................................................... RTC Match/Wake-Up from Hibernation ......................................................................... External Wake-Up from Hibernation .............................................................................. RTC/External Wake-Up from Hibernation ...................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 238 238 239 239 240 241 241 242 242 242 243 243 243 243 244 244 244 244 245 7 Internal Memory ................................................................................................... 258 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.6 Block Diagram ............................................................................................................ 258 Functional Description ................................................................................................. 258 SRAM Memory ............................................................................................................ 258 Flash Memory ............................................................................................................. 259 Flash Memory Initialization and Configuration ............................................................... 260 Flash Programming ..................................................................................................... 260 Nonvolatile Register Programming ............................................................................... 261 Register Map .............................................................................................................. 262 Flash Register Descriptions (Flash Control Offset) ......................................................... 263 Flash Register Descriptions (System Control Offset) ...................................................... 271 8 General-Purpose Input/Outputs (GPIOs) ........................................................... 284 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.4 8.5 Signal Description ....................................................................................................... 284 Functional Description ................................................................................................. 290 Data Control ............................................................................................................... 291 Interrupt Control .......................................................................................................... 292 Mode Control .............................................................................................................. 292 Commit Control ........................................................................................................... 292 Pad Control ................................................................................................................. 292 Identification ............................................................................................................... 293 Initialization and Configuration ..................................................................................... 293 Register Map .............................................................................................................. 294 Register Descriptions .................................................................................................. 296 9 General-Purpose Timers ...................................................................................... 331 9.1 9.2 9.3 9.3.1 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. GPTM Reset Conditions .............................................................................................. June 18, 2012 332 332 333 333 5 Texas Instruments-Production Data Table of Contents 9.3.2 9.3.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.5 9.6 32-Bit Timer Operating Modes ...................................................................................... 16-Bit Timer Operating Modes ...................................................................................... Initialization and Configuration ..................................................................................... 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 16-Bit Input Edge Count Mode ..................................................................................... 16-Bit Input Edge Timing Mode .................................................................................... 16-Bit PWM Mode ....................................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 333 335 339 339 340 340 341 341 342 342 343 10 Watchdog Timer ................................................................................................... 368 10.1 10.2 10.3 10.4 10.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 369 369 370 370 371 11 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 392 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.4 11.5 11.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Transmit/Receive Logic ............................................................................................... Baud-Rate Generation ................................................................................................. Data Transmission ...................................................................................................... Serial IR (SIR) ............................................................................................................. FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... IrDA SIR block ............................................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 393 393 394 394 395 395 396 397 397 398 399 399 400 401 12 Synchronous Serial Interface (SSI) .................................................................... 435 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.4 12.5 12.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Frame Formats ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 13 Inter-Integrated Circuit (I2C) Interface ................................................................ 473 13.1 13.2 13.3 Block Diagram ............................................................................................................ 474 Signal Description ....................................................................................................... 474 Functional Description ................................................................................................. 474 6 435 436 436 436 437 437 438 445 446 447 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.4 13.5 13.6 13.7 I2C Bus Functional Overview ........................................................................................ Available Speed Modes ............................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... Command Sequence Flow Charts ................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions (I2C Master) ............................................................................... Register Descriptions (I2C Slave) ................................................................................. 475 477 478 478 478 486 487 488 501 14 Ethernet Controller .............................................................................................. 510 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.4 14.4.1 14.4.2 14.5 14.6 14.7 Block Diagram ............................................................................................................ 510 Signal Description ....................................................................................................... 511 Functional Description ................................................................................................. 513 MAC Operation ........................................................................................................... 513 Internal MII Operation .................................................................................................. 516 PHY Operation ............................................................................................................ 516 Interrupts .................................................................................................................... 518 Initialization and Configuration ..................................................................................... 518 Hardware Configuration ............................................................................................... 518 Software Configuration ................................................................................................ 519 Ethernet Register Map ................................................................................................. 520 Ethernet MAC Register Descriptions ............................................................................. 521 MII Management Register Descriptions ......................................................................... 540 15 Analog Comparators ............................................................................................ 559 15.1 15.2 15.3 15.3.1 15.4 15.5 15.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Internal Reference Programming .................................................................................. Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 560 560 561 562 563 563 564 16 Pulse Width Modulator (PWM) ............................................................................ 572 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.4 16.5 16.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. PWM Timer ................................................................................................................. PWM Comparators ...................................................................................................... PWM Signal Generator ................................................................................................ Dead-Band Generator ................................................................................................. Interrupt Selector ......................................................................................................... Synchronization Methods ............................................................................................ Fault Conditions .......................................................................................................... Output Control Block ................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. June 18, 2012 573 574 575 575 575 576 577 577 578 578 578 578 579 581 7 Texas Instruments-Production Data Table of Contents 17 Quadrature Encoder Interface (QEI) ................................................................... 610 17.1 17.2 17.3 17.4 17.5 17.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 18 Pin Diagram .......................................................................................................... 628 610 611 612 614 614 615 19 Signal Tables ........................................................................................................ 630 19.1 19.1.1 19.1.2 19.1.3 19.1.4 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.3 100-Pin LQFP Package Pin Tables ............................................................................... 630 Signals by Pin Number ................................................................................................ 630 Signals by Signal Name ............................................................................................... 634 Signals by Function, Except for GPIO ........................................................................... 639 GPIO Pins and Alternate Functions .............................................................................. 642 108-Ball BGA Package Pin Tables ................................................................................ 644 Signals by Pin Number ................................................................................................ 644 Signals by Signal Name ............................................................................................... 648 Signals by Function, Except for GPIO ........................................................................... 653 GPIO Pins and Alternate Functions .............................................................................. 656 Connections for Unused Signals ................................................................................... 657 20 Operating Characteristics ................................................................................... 660 21 Electrical Characteristics .................................................................................... 661 21.1 DC Characteristics ...................................................................................................... 661 21.1.1 Maximum Ratings ....................................................................................................... 661 21.1.2 Recommended DC Operating Conditions ...................................................................... 661 21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 662 21.1.4 GPIO Module Characteristics ....................................................................................... 662 21.1.5 Power Specifications ................................................................................................... 662 21.1.6 Flash Memory Characteristics ...................................................................................... 664 21.1.7 Hibernation ................................................................................................................. 664 21.1.8 Ethernet Controller ...................................................................................................... 664 21.2 AC Characteristics ....................................................................................................... 664 21.2.1 Load Conditions .......................................................................................................... 664 21.2.2 Clocks ........................................................................................................................ 665 21.2.3 JTAG and Boundary Scan ............................................................................................ 666 21.2.4 Reset ......................................................................................................................... 668 21.2.5 Sleep Modes ............................................................................................................... 670 21.2.6 Hibernation Module ..................................................................................................... 670 21.2.7 General-Purpose I/O (GPIO) ........................................................................................ 670 21.2.8 Synchronous Serial Interface (SSI) ............................................................................... 671 21.2.9 Inter-Integrated Circuit (I2C) Interface ........................................................................... 672 21.2.10 Ethernet Controller ...................................................................................................... 673 21.2.11 Analog Comparator ..................................................................................................... 676 A Serial Flash Loader .............................................................................................. 677 A.1 A.2 A.2.1 Serial Flash Loader ..................................................................................................... 677 Interfaces ................................................................................................................... 677 UART ......................................................................................................................... 677 8 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller A.2.2 A.3 A.3.1 A.3.2 A.3.3 A.4 A.4.1 A.4.2 A.4.3 A.4.4 A.4.5 A.4.6 SSI ............................................................................................................................. Packet Handling .......................................................................................................... Packet Format ............................................................................................................ Sending Packets ......................................................................................................... Receiving Packets ....................................................................................................... Commands ................................................................................................................. COMMAND_PING (0X20) ............................................................................................ COMMAND_GET_STATUS (0x23) ............................................................................... COMMAND_DOWNLOAD (0x21) ................................................................................. COMMAND_SEND_DATA (0x24) ................................................................................. COMMAND_RUN (0x22) ............................................................................................. COMMAND_RESET (0x25) ......................................................................................... 677 678 678 678 678 679 679 679 679 680 680 680 B Register Quick Reference ................................................................................... 682 C Ordering and Contact Information ..................................................................... 705 C.1 C.2 C.3 C.4 Ordering Information .................................................................................................... 705 Part Markings .............................................................................................................. 705 Kits ............................................................................................................................. 706 Support Information ..................................................................................................... 706 D Package Information ............................................................................................ 707 D.1 D.1.1 D.1.2 D.1.3 D.2 D.2.1 D.2.2 D.2.3 100-Pin LQFP Package ............................................................................................... Package Dimensions ................................................................................................... Tray Dimensions ......................................................................................................... Tape and Reel Dimensions .......................................................................................... 108-Ball BGA Package ................................................................................................ Package Dimensions ................................................................................................... Tray Dimensions ......................................................................................................... Tape and Reel Dimensions .......................................................................................... June 18, 2012 707 707 709 709 711 711 713 714 9 Texas Instruments-Production Data Table of Contents List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 6-3. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 11-3. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Stellaris LM3S6950 Microcontroller High-Level Block Diagram ............................... 43 CPU Block Diagram ............................................................................................. 53 TPIU Block Diagram ............................................................................................ 54 Cortex-M3 Register Set ........................................................................................ 56 Bit-Band Mapping ................................................................................................ 76 Data Storage ....................................................................................................... 77 Vector Table ........................................................................................................ 83 Exception Stack Frame ........................................................................................ 85 SRD Use Example ............................................................................................... 99 JTAG Module Block Diagram .............................................................................. 158 Test Access Port State Machine ......................................................................... 162 IDCODE Register Format ................................................................................... 168 BYPASS Register Format ................................................................................... 168 Boundary Scan Register Format ......................................................................... 169 Basic RST Configuration .................................................................................... 172 External Circuitry to Extend Power-On Reset ....................................................... 173 Reset Circuit Controlled by Switch ...................................................................... 173 Power Architecture ............................................................................................ 176 Main Clock Tree ................................................................................................ 178 Hibernation Module Block Diagram ..................................................................... 238 Clock Source Using Crystal ................................................................................ 240 Clock Source Using Dedicated Oscillator ............................................................. 241 Flash Block Diagram .......................................................................................... 258 GPIO Port Block Diagram ................................................................................... 290 GPIODATA Write Example ................................................................................. 291 GPIODATA Read Example ................................................................................. 291 GPTM Module Block Diagram ............................................................................ 332 16-Bit Input Edge Count Mode Example .............................................................. 337 16-Bit Input Edge Time Mode Example ............................................................... 338 16-Bit PWM Mode Example ................................................................................ 339 WDT Module Block Diagram .............................................................................. 369 UART Module Block Diagram ............................................................................. 393 UART Character Frame ..................................................................................... 395 IrDA Data Modulation ......................................................................................... 397 SSI Module Block Diagram ................................................................................. 435 TI Synchronous Serial Frame Format (Single Transfer) ........................................ 438 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 439 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 440 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 440 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 441 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 442 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 442 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 443 MICROWIRE Frame Format (Single Frame) ........................................................ 444 MICROWIRE Frame Format (Continuous Transfer) ............................................. 445 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 445 10 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 13-13. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 15-1. Figure 15-2. Figure 15-3. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 16-5. Figure 16-6. Figure 17-1. Figure 17-2. Figure 18-1. Figure 18-2. Figure 21-1. Figure 21-2. Figure 21-3. Figure 21-4. Figure 21-5. Figure 21-6. Figure 21-7. Figure 21-8. Figure 21-9. Figure 21-10. Figure 21-11. Figure 21-12. Figure 21-13. Figure 21-14. Figure 21-15. Figure D-1. Figure D-2. I2C Block Diagram ............................................................................................. 474 I2C Bus Configuration ........................................................................................ 475 START and STOP Conditions ............................................................................. 475 Complete Data Transfer with a 7-Bit Address ....................................................... 476 R/S Bit in First Byte ............................................................................................ 476 Data Validity During Bit Transfer on the I2C Bus ................................................... 476 Master Single SEND .......................................................................................... 480 Master Single RECEIVE ..................................................................................... 481 Master Burst SEND ........................................................................................... 482 Master Burst RECEIVE ...................................................................................... 483 Master Burst RECEIVE after Burst SEND ............................................................ 484 Master Burst SEND after Burst RECEIVE ............................................................ 485 Slave Command Sequence ................................................................................ 486 Ethernet Controller ............................................................................................. 511 Ethernet Controller Block Diagram ...................................................................... 511 Ethernet Frame ................................................................................................. 513 Interface to an Ethernet Jack .............................................................................. 519 Analog Comparator Module Block Diagram ......................................................... 560 Structure of Comparator Unit .............................................................................. 562 Comparator Internal Reference Structure ............................................................ 562 PWM Unit Diagram ............................................................................................ 573 PWM Module Block Diagram .............................................................................. 574 PWM Count-Down Mode .................................................................................... 576 PWM Count-Up/Down Mode .............................................................................. 576 PWM Generation Example In Count-Up/Down Mode ........................................... 577 PWM Dead-Band Generator ............................................................................... 577 QEI Block Diagram ............................................................................................ 611 Quadrature Encoder and Velocity Predivider Operation ........................................ 613 100-Pin LQFP Package Pin Diagram .................................................................. 628 108-Ball BGA Package Pin Diagram (Top View) ................................................... 629 Load Conditions ................................................................................................ 665 JTAG Test Clock Input Timing ............................................................................. 667 JTAG Test Access Port (TAP) Timing .................................................................. 667 JTAG TRST Timing ............................................................................................ 668 External Reset Timing (RST) .............................................................................. 668 Power-On Reset Timing ..................................................................................... 669 Brown-Out Reset Timing .................................................................................... 669 Software Reset Timing ....................................................................................... 669 Watchdog Reset Timing ..................................................................................... 669 Hibernation Module Timing ................................................................................. 670 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 671 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 672 SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 672 I2C Timing ......................................................................................................... 673 External XTLP Oscillator Characteristics ............................................................. 675 Stellaris LM3S6950 100-Pin LQFP Package Dimensions ..................................... 707 100-Pin LQFP Tray Dimensions .......................................................................... 709 June 18, 2012 11 Texas Instruments-Production Data Table of Contents Figure D-3. Figure D-4. Figure D-5. Figure D-6. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 710 Stellaris LM3S6950 108-Ball BGA Package Dimensions ...................................... 711 108-Ball BGA Tray Dimensions ........................................................................... 713 108-Ball BGA Tape and Reel Dimensions ............................................................ 714 12 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller List of Tables Table 1. Table 2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 6-1. Table 6-2. Table 6-3. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Revision History .................................................................................................. 24 Documentation Conventions ................................................................................ 31 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 56 Processor Register Map ....................................................................................... 57 PSR Register Combinations ................................................................................. 62 Memory Map ....................................................................................................... 70 Memory Access Behavior ..................................................................................... 72 SRAM Memory Bit-Banding Regions .................................................................... 74 Peripheral Memory Bit-Banding Regions ............................................................... 75 Exception Types .................................................................................................. 80 Interrupts ............................................................................................................ 81 Exception Return Behavior ................................................................................... 86 Faults ................................................................................................................. 87 Fault Status and Fault Address Registers .............................................................. 88 Cortex-M3 Instruction Summary ........................................................................... 90 Core Peripheral Register Regions ......................................................................... 93 Memory Attributes Summary ................................................................................ 96 TEX, S, C, and B Bit Field Encoding ..................................................................... 99 Cache Policy for Memory Attribute Encoding ....................................................... 100 AP Bit Field Encoding ........................................................................................ 100 Memory Region Attributes for Stellaris Microcontrollers ........................................ 100 Peripherals Register Map ................................................................................... 101 Interrupt Priority Levels ...................................................................................... 126 Example SIZE Field Values ................................................................................ 154 JTAG_SWD_SWO Signals (100LQFP) ................................................................ 158 JTAG_SWD_SWO Signals (108BGA) ................................................................. 159 JTAG Port Pins Reset State ............................................................................... 159 JTAG Instruction Register Commands ................................................................. 166 System Control & Clocks Signals (100LQFP) ...................................................... 170 System Control & Clocks Signals (108BGA) ........................................................ 170 Reset Sources ................................................................................................... 171 Clock Source Options ........................................................................................ 177 Possible System Clock Frequencies Using the SYSDIV Field ............................... 179 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 179 System Control Register Map ............................................................................. 183 RCC2 Fields that Override RCC fields ................................................................. 198 Hibernate Signals (100LQFP) ............................................................................. 238 Hibernate Signals (108BGA) .............................................................................. 239 Hibernation Module Register Map ....................................................................... 245 Flash Protection Policy Combinations ................................................................. 259 User-Programmable Flash Memory Resident Registers ....................................... 262 Flash Register Map ............................................................................................ 262 GPIO Pins With Non-Zero Reset Values .............................................................. 285 GPIO Pins and Alternate Functions (100LQFP) ................................................... 285 GPIO Pins and Alternate Functions (108BGA) ..................................................... 286 GPIO Signals (100LQFP) ................................................................................... 287 June 18, 2012 13 Texas Instruments-Production Data Table of Contents Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 10-1. Table 11-1. Table 11-2. Table 11-3. Table 12-1. Table 12-2. Table 12-3. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 13-5. Table 14-1. Table 14-2. Table 14-3. Table 14-4. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Table 16-1. Table 16-2. Table 16-3. Table 17-1. Table 17-2. Table 17-3. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 19-6. Table 19-7. Table 19-8. Table 19-9. Table 19-10. Table 20-1. Table 20-2. Table 20-3. GPIO Signals (108BGA) ..................................................................................... 288 GPIO Pad Configuration Examples ..................................................................... 293 GPIO Interrupt Configuration Example ................................................................ 294 GPIO Register Map ........................................................................................... 295 Available CCP Pins ............................................................................................ 332 General-Purpose Timers Signals (100LQFP) ....................................................... 333 General-Purpose Timers Signals (108BGA) ......................................................... 333 16-Bit Timer With Prescaler Configurations ......................................................... 335 Timers Register Map .......................................................................................... 342 Watchdog Timer Register Map ............................................................................ 370 UART Signals (100LQFP) .................................................................................. 393 UART Signals (108BGA) .................................................................................... 394 UART Register Map ........................................................................................... 400 SSI Signals (100LQFP) ...................................................................................... 436 SSI Signals (108BGA) ........................................................................................ 436 SSI Register Map .............................................................................................. 447 I2C Signals (100LQFP) ...................................................................................... 474 I2C Signals (108BGA) ........................................................................................ 474 Examples of I2C Master Timer Period versus Speed Mode ................................... 477 Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 487 Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 492 Ethernet Signals (100LQFP) ............................................................................... 512 Ethernet Signals (108BGA) ................................................................................ 512 TX & RX FIFO Organization ............................................................................... 515 Ethernet Register Map ....................................................................................... 520 Analog Comparators Signals (100LQFP) ............................................................. 560 Analog Comparators Signals (108BGA) .............................................................. 561 Internal Reference Voltage and ACREFCTL Field Values ..................................... 562 Analog Comparators Register Map ..................................................................... 564 PWM Signals (100LQFP) ................................................................................... 574 PWM Signals (108BGA) ..................................................................................... 574 PWM Register Map ............................................................................................ 580 QEI Signals (100LQFP) ...................................................................................... 611 QEI Signals (108BGA) ....................................................................................... 611 QEI Register Map .............................................................................................. 614 Signals by Pin Number ....................................................................................... 630 Signals by Signal Name ..................................................................................... 634 Signals by Function, Except for GPIO ................................................................. 639 GPIO Pins and Alternate Functions ..................................................................... 642 Signals by Pin Number ....................................................................................... 644 Signals by Signal Name ..................................................................................... 648 Signals by Function, Except for GPIO ................................................................. 653 GPIO Pins and Alternate Functions ..................................................................... 656 Connections for Unused Signals (100-pin LQFP) ................................................. 658 Connections for Unused Signals, 108-pin BGA .................................................... 659 Temperature Characteristics ............................................................................... 660 Thermal Characteristics ..................................................................................... 660 ESD Absolute Maximum Ratings ........................................................................ 660 14 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 21-1. Table 21-2. Table 21-3. Table 21-4. Table 21-5. Table 21-6. Table 21-7. Table 21-8. Table 21-9. Table 21-10. Table 21-11. Table 21-12. Table 21-13. Table 21-14. Table 21-15. Table 21-16. Table 21-17. Table 21-18. Table 21-19. Table 21-20. Table 21-21. Table 21-22. Table 21-23. Table 21-24. Table 21-25. Table 21-26. Table 21-27. Table 21-28. Table 21-29. Table 21-30. Table C-1. Maximum Ratings .............................................................................................. 661 Recommended DC Operating Conditions ............................................................ 661 LDO Regulator Characteristics ........................................................................... 662 GPIO Module DC Characteristics ........................................................................ 662 Detailed Power Specifications ............................................................................ 663 Flash Memory Characteristics ............................................................................ 664 Hibernation Module DC Characteristics ............................................................... 664 Ethernet Controller DC Characteristics ................................................................ 664 Phase Locked Loop (PLL) Characteristics ........................................................... 665 Actual PLL Frequency ........................................................................................ 665 Clock Characteristics ......................................................................................... 665 Crystal Characteristics ....................................................................................... 666 JTAG Characteristics ......................................................................................... 666 Reset Characteristics ......................................................................................... 668 Sleep Modes AC Characteristics ......................................................................... 670 Hibernation Module AC Characteristics ............................................................... 670 GPIO Characteristics ......................................................................................... 671 SSI Characteristics ............................................................................................ 671 I2C Characteristics ............................................................................................. 672 100BASE-TX Transmitter Characteristics ............................................................ 673 100BASE-TX Transmitter Characteristics (informative) ......................................... 673 100BASE-TX Receiver Characteristics ................................................................ 674 10BASE-T Transmitter Characteristics ................................................................ 674 10BASE-T Transmitter Characteristics (informative) ............................................. 674 10BASE-T Receiver Characteristics .................................................................... 674 Isolation Transformers ....................................................................................... 674 Ethernet Reference Crystal ................................................................................ 675 External XTLP Oscillator Characteristics ............................................................. 676 Analog Comparator Characteristics ..................................................................... 676 Analog Comparator Voltage Reference Characteristics ........................................ 676 Part Ordering Information ................................................................................... 705 June 18, 2012 15 Texas Instruments-Production Data Table of Contents List of Registers The Cortex-M3 Processor ............................................................................................................. 51 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Cortex General-Purpose Register 0 (R0) ........................................................................... 58 Cortex General-Purpose Register 1 (R1) ........................................................................... 58 Cortex General-Purpose Register 2 (R2) ........................................................................... 58 Cortex General-Purpose Register 3 (R3) ........................................................................... 58 Cortex General-Purpose Register 4 (R4) ........................................................................... 58 Cortex General-Purpose Register 5 (R5) ........................................................................... 58 Cortex General-Purpose Register 6 (R6) ........................................................................... 58 Cortex General-Purpose Register 7 (R7) ........................................................................... 58 Cortex General-Purpose Register 8 (R8) ........................................................................... 58 Cortex General-Purpose Register 9 (R9) ........................................................................... 58 Cortex General-Purpose Register 10 (R10) ....................................................................... 58 Cortex General-Purpose Register 11 (R11) ........................................................................ 58 Cortex General-Purpose Register 12 (R12) ....................................................................... 58 Stack Pointer (SP) ........................................................................................................... 59 Link Register (LR) ............................................................................................................ 60 Program Counter (PC) ..................................................................................................... 61 Program Status Register (PSR) ........................................................................................ 62 Priority Mask Register (PRIMASK) .................................................................................... 66 Fault Mask Register (FAULTMASK) .................................................................................. 67 Base Priority Mask Register (BASEPRI) ............................................................................ 68 Control Register (CONTROL) ........................................................................................... 69 Cortex-M3 Peripherals ................................................................................................................... 93 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 104 SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 106 SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 107 Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 108 Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................ 109 Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 110 Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................ 111 Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 112 Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 113 Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 114 Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 115 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 116 Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 117 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 118 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 118 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 118 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 118 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 118 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 118 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 118 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 118 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 118 16 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 118 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 118 Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 120 CPU ID Base (CPUID), offset 0xD00 ............................................................................... 121 Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 122 Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 125 Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 126 System Control (SYSCTRL), offset 0xD10 ....................................................................... 128 Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 130 System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 132 System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 133 System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 134 System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 135 Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 139 Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 145 Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 146 Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 147 MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 148 MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 149 MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 151 MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 152 MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 152 MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 152 MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 152 MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 154 MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 154 MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 154 MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 154 System Control ............................................................................................................................ 170 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Device Identification 0 (DID0), offset 0x000 ..................................................................... 185 Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 187 LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 188 Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 189 Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 190 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 191 Reset Cause (RESC), offset 0x05C ................................................................................ 192 Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 193 XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 197 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 198 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 200 Device Identification 1 (DID1), offset 0x004 ..................................................................... 201 Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 203 Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 204 Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 206 Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 208 Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 210 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 212 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 214 June 18, 2012 17 Texas Instruments-Production Data Table of Contents Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 216 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 218 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 221 Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 224 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 227 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 229 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 231 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 233 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 234 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 236 Hibernation Module ..................................................................................................................... 237 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... Hibernation Control (HIBCTL), offset 0x010 ..................................................................... Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 246 247 248 249 250 252 253 254 255 256 257 Internal Memory ........................................................................................................................... 258 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Flash Memory Address (FMA), offset 0x000 .................................................................... 264 Flash Memory Data (FMD), offset 0x004 ......................................................................... 265 Flash Memory Control (FMC), offset 0x008 ..................................................................... 266 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 268 Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 269 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 270 USec Reload (USECRL), offset 0x140 ............................................................................ 272 Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 273 Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 274 User Debug (USER_DBG), offset 0x1D0 ......................................................................... 275 User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 276 User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 277 Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 278 Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 279 Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 280 Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 281 Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 282 Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 283 General-Purpose Input/Outputs (GPIOs) ................................................................................... 284 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: GPIO Data (GPIODATA), offset 0x000 ............................................................................ GPIO Direction (GPIODIR), offset 0x400 ......................................................................... GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 18 297 298 299 300 301 302 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 303 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 304 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 305 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 306 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 308 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 309 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 310 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 311 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 312 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 313 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 314 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 315 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 316 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 317 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 319 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 320 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 321 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 322 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 323 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 324 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 325 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 326 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 327 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 328 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 329 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 330 General-Purpose Timers ............................................................................................................. 331 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 344 GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 345 GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 347 GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 349 GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 352 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 354 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 355 GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 356 GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 358 GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 359 GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 360 GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 361 GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 362 GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 363 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 364 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 365 GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 366 GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 367 Watchdog Timer ........................................................................................................................... 368 Register 1: Register 2: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 372 Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 373 June 18, 2012 19 Texas Instruments-Production Data Table of Contents Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 374 Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 375 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 376 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 377 Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 378 Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 379 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 380 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 381 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 382 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 383 Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 384 Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 385 Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 386 Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 387 Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 388 Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 389 Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 390 Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 391 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 392 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: UART Data (UARTDR), offset 0x000 ............................................................................... 402 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 404 UART Flag (UARTFR), offset 0x018 ................................................................................ 406 UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 408 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 409 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 410 UART Line Control (UARTLCRH), offset 0x02C ............................................................... 411 UART Control (UARTCTL), offset 0x030 ......................................................................... 413 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 415 UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 417 UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 419 UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 420 UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 421 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 423 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 424 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 425 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 426 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 427 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 428 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 429 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 430 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 431 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 432 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 433 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 434 Synchronous Serial Interface (SSI) ............................................................................................ 435 Register 1: Register 2: Register 3: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 448 SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 450 SSI Data (SSIDR), offset 0x008 ...................................................................................... 452 20 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: SSI Status (SSISR), offset 0x00C ................................................................................... 453 SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 455 SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 456 SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 458 SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 459 SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 460 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 461 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 462 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 463 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 464 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 465 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 466 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 467 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 468 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 469 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 470 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 471 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 472 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 473 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 489 I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 490 I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 494 I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 495 I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 496 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 497 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 498 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 499 I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 500 I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 502 I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 503 I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 505 I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 506 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 507 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 508 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 509 Ethernet Controller ...................................................................................................................... 510 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. June 18, 2012 522 525 526 527 528 530 531 532 534 535 536 21 Texas Instruments-Production Data Table of Contents Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 537 Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 538 Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 539 Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 540 Ethernet PHY Management Register 0 - Control (MR0), address 0x00 ............................. 541 Ethernet PHY Management Register 1 - Status (MR1), address 0x01 .............................. 543 Ethernet PHY Management Register 2 - PHY Identifier 1 (MR2), address 0x02 ................. 545 Ethernet PHY Management Register 3 - PHY Identifier 2 (MR3), address 0x03 ................. 546 Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement (MR4), address 0x04 ............................................................................................................................. 547 Ethernet PHY Management Register 5 - Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 ..................................................................................................... 549 Ethernet PHY Management Register 6 - Auto-Negotiation Expansion (MR6), address 0x06 ............................................................................................................................. 550 Ethernet PHY Management Register 16 - Vendor-Specific (MR16), address 0x10 ............. 551 Ethernet PHY Management Register 17 - Interrupt Control/Status (MR17), address 0x11 .............................................................................................................................. 553 Ethernet PHY Management Register 18 - Diagnostic (MR18), address 0x12 ..................... 555 Ethernet PHY Management Register 19 - Transceiver Control (MR19), address 0x13 ....... 556 Ethernet PHY Management Register 23 - LED Configuration (MR23), address 0x17 ......... 557 Ethernet PHY Management Register 24 -MDI/MDIX Control (MR24), address 0x18 .......... 558 Analog Comparators ................................................................................................................... 559 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 565 566 567 568 569 569 569 570 570 570 Pulse Width Modulator (PWM) .................................................................................................... 572 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 582 PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 583 PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 584 PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 585 PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 586 PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 587 PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 588 PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 589 PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 590 PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 591 PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 591 PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 591 PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 593 PWM1 Interrupt Enable (PWM1INTEN), offset 0x084 ...................................................... 593 PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4 ...................................................... 593 22 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 595 PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 595 PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 595 PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 596 PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 596 PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 596 PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 597 PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 597 PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 597 PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 598 PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 598 PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 598 PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 599 PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 599 PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 599 PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 600 PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 600 PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 600 PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 601 PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 601 PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 601 PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 604 PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 604 PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 604 PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 607 PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 607 PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 607 PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 608 PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 608 PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 608 PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 609 PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 609 PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 609 Quadrature Encoder Interface (QEI) .......................................................................................... 610 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: QEI Control (QEICTL), offset 0x000 ................................................................................ QEI Status (QEISTAT), offset 0x004 ................................................................................ QEI Position (QEIPOS), offset 0x008 .............................................................................. QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... QEI Timer (QEITIME), offset 0x014 ................................................................................. QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. QEI Velocity (QEISPEED), offset 0x01C .......................................................................... QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... June 18, 2012 616 618 619 620 621 622 623 624 625 626 627 23 Texas Instruments-Production Data Revision History Revision History The revision history table notes changes made between the indicated revisions of the LM3S6950 data sheet. Table 1. Revision History Date June 2012 November 2011 Revision Description 12746.2515 11108 Corrected missing interrupt 9 in "Interrupts" table. Removed extended temperature package. Minor data sheet clarifications and corrections. Added module-specific pin tables to each chapter in the new Signal Description sections. In Hibernation chapter: - Changed terminology from non-volatile memory to battery-backed memory. - Clarified Hibernation module register reset conditions. In Timer chapter, clarified that in 16-Bit Input Edge Time Mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. In UART chapter, clarified interrupt behavior. In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)". In Signal Tables chapter: - Corrected pin numbers in table "Connections for Unused Signals" (other pin tables were correct). - Corrected buffer type for PWMn signals in pin tables. In Electrical Characteristics chapter: - Added parameter "Input voltage for a GPIO configured as an analog input" to the "Maximum Ratings" table. - Corrected Nom values for parameters "TCK clock Low time" and "TCK clock High time" in "JTAG Characteristics" table. Additional minor data sheet clarifications and corrections. 24 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 1. Revision History (continued) Date Revision January 2011 9102 September 2010 7787 Description In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ to SYSRESREQ. Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register. Added "Reset Sources" table to System Control chapter. Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be four-bits wide, bits[7:4]. Removed mention of false-start bit detection in the UART chapter. This feature is not supported. Added note that specific module clocks must be enabled before that module's registers can be programmed. There must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed. Changed I2C slave register base addresses and offsets to be relative to the I2C module base address of 0x4002.0000 , so register bases and offsets were changed for all I2C slave registers. Note that (R) the hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x4002.0800 for the 2 I C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses the old slave base address for these offsets. Added GNDPHY and VCCPHY to Connections for Unused Signals tables. Added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (VNON parameter in Maximum Ratings table). Additional minor data sheet clarifications and corrections. Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was added, including all the Cortex-M3 registers. Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register. Added clarification of instruction execution during Flash operations. Modified Figure 8-1 on page 290 to clarify operation of the GPIO inputs when used as an alternate function. Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits wide, bits[7:0]. Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes the JTAG controller to be reset, resulting in a loss of JTAG communication. In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode. In Electrical Characteristics chapter: - Added ILKG parameter (GPIO input leakage current) to Table 21-4 on page 662. - Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 21-18 on page 671. - Added "Ethernet Controller DC Characteristics" table (see Table 21-8 on page 664). Added dimensions for Tray and Tape and Reel shipping mediums. June 18, 2012 25 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision June 2010 7393 April 2010 January 2010 7007 6712 Description Corrected base address for SRAM in architectural overview chapter. Clarified system clock operation, adding content to "Clock Control" on page 176. In Signal Tables chapter, added table "Connections for Unused Signals." In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32. In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time. Additional minor data sheet clarifications and corrections. Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed field width to 7 bits. Removed erroneous text about restoring the Flash Protection registers. Added note about RST signal routing. Clarified the function of the TnSTALL bit in the GPTMCTL register. Corrected XTALNPHY pin description. Additional minor data sheet clarifications and corrections. In "System Control" section, clarified Debug Access Port operation after Sleep modes. Clarified wording on Flash memory access errors. Added section on Flash interrupts. Clarified operation of SSI transmit FIFO. Made these changes to the Operating Characteristics chapter: October 2009 July 2009 6462 5920 - Added storage temperature ratings to "Temperature Characteristics" table - Added "ESD Absolute Maximum Ratings" table Made these changes to the Electrical Characteristics chapter: - In "Flash Memory Characteristics" table, corrected Mass erase time - Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) - In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time Removed erroneous reference to the WRC bit in the Hibernation chapter. Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers because the module resets in 32-bit mode. Made these changes to the Electrical Characteristics chapter: - Removed VSIH and VSIL parameters from Operating Conditions table. - Added table showing actual PLL frequency depending on input crystal. - Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS. - Changed SSI set up and hold times to be expressed in system clocks, not ns. Corrected ordering numbers. 26 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 1. Revision History (continued) Date Revision July 2009 5902 April 2009 January 2009 November 2008 October 2008 August 2008 5367 4660 4283 4149 3447 Description Clarified Power-on reset and RST pin operation; added new diagrams. Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL) registers. Clarified explanation of nonvolatile register programming in Internal Memory chapter. Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1 registers. Added description for Ethernet PHY power-saving modes. Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register. Changed buffer type for WAKE pin to TTL and HIB pin to OD. In ADC characteristics table, changed Max value for GAIN parameter from 1 to 3 and added EIR (Internal voltage reference error) parameter. Additional minor data sheet clarifications and corrections. Added JTAG/SWD clarification (see "Communication with JTAG/SWD" on page 164). Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. Added "GPIO Module DC Characteristics" table (see Table 21-4 on page 662). Additional minor data sheet clarifications and corrections. Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W. Clarification added as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO. Added "Hardware Configuration" section to Ethernet Controller chapter. Additional minor data sheet clarifications and corrections. Revised High-Level Block Diagram. Additional minor data sheet clarifications and corrections were made. Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG) register. The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the Internal Memory chapter. The correct value is 0x0000.0006. In the Ethernet chapter, major improvements were made including a rewrite of the conceptual information and the addition of new figures to clarify how to use the Ethernet Controller interface. Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter. Added note on clearing interrupts to Interrupts chapter. Added Power Architecture diagram to System Control chapter. Additional minor data sheet clarifications and corrections. June 18, 2012 27 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision July 2008 3108 May 2008 April 2008 2972 2881 Description Corrected resistor value in ERBIAS signal description. Additional minor data sheet clarifications and corrections. As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported: TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit fields in the MR23 register are now marked as reserved. As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use the LDO output as the source of VDD25 input. As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS. A 12.4-k resistor should be connected between ERBIAS and ground to accommodate future device revisions (see "Functional Description" on page 513). Additional minor data sheet clarifications and corrections. The JA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating Characteristics chapter. Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock. Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter. The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter. The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter was changed from a max of 100 to 250. The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical Characteristics" chapter was changed from 4 to 3. The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz 50% (prior data sheets incorrectly noted it as 30 kHz 30%). A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value. The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC). Two figures on clock source were added to the "Hibernation Module": - Clock Source Using Crystal - Clock Source Using Dedicated Oscillator The following notes on battery management were added to the "Hibernation Module" chapter: - Battery voltage is not measured while in Hibernate mode. - System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. A note on high-current applications was added to the GPIO chapter: For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only 28 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 1. Revision History (continued) Date Revision Description a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. A note on Schmitt inputs was added to the GPIO chapter: Pins configured as digital inputs are Schmitt-triggered. The Buffer type on the WAKE pin changed from OD to - in the Signal Tables. The "Differential Sampling Range" figures in the ADC chapter were clarified. The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected: March 2008 2550 - The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins. - The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams. Additional minor data sheet clarifications and corrections. Started tracking revision history. June 18, 2012 29 Texas Instruments-Production Data About This Document About This Document This data sheet provides reference information for the LM3S6950 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM(R) CortexTM-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents (R) The following related documents are available on the Stellaris web site at www.ti.com/stellaris: Stellaris(R) Errata ARM(R) CortexTM-M3 Errata CortexTM-M3/M4 Instruction Set Technical User's Manual Stellaris(R) Graphics Library User's Guide Stellaris(R) Peripheral Driver Library User's Guide The following related documents are also referenced: ARM(R) Debug Interface V5 Architecture Specification ARM(R) Embedded Trace Macrocell Architecture Specification IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. 30 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Documentation Conventions This document uses the conventions shown in Table 2 on page 31. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 70. Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/WC Software can read or write this field. Writing to it with any value clears the register. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1S Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. June 18, 2012 31 Texas Instruments-Production Data About This Document Table 2. Documentation Conventions (continued) Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 32 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 1 Architectural Overview (R) The Stellaris family of microcontrollers--the first ARM(R) CortexTM-M3 based controllers--brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an ARM architecture MCU. The LM3S6950 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S6950 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S6950 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S6950 microcontroller perfectly for battery applications. In addition, the LM3S6950 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb(R)-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S6950 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See "Ordering and Contact Information" on page 705 for ordering information for Stellaris family devices. 1.1 Product Features The LM3S6950 microcontroller includes the following product features: 32-Bit RISC Performance - 32-bit ARM(R) CortexTM-M3 v7M architecture optimized for small-footprint embedded applications - System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism - Thumb(R)-compatible Thumb-2-only instruction set processor core for high code density - 50-MHz operation - Hardware-division and single-cycle-multiplication June 18, 2012 33 Texas Instruments-Production Data Architectural Overview - Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling - 34 interrupts with eight priority levels - Memory protection unit (MPU), providing a privileged mode for protected operating system functionality - Unaligned data access, enabling data to be efficiently packed into memory - Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ARM(R) CortexTM-M3 Processor Core - Compact core. - Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. - Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. - Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. - Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining - Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. - Migration from the ARM7TM processor family for better performance and power efficiency. - Full-featured debug solution * Serial Wire JTAG Debug Port (SWJ-DP) * Flash Patch and Breakpoint (FPB) unit for implementing breakpoints * Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling * Instrumentation Trace Macrocell (ITM) for support of printf style debugging * Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer - Optimized for single-cycle flash usage - Three sleep modes with clock gating for low power - Single-cycle multiply instruction and hardware divide - Atomic operations - ARM Thumb2 mixed 16-/32-bit instruction set 34 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller - 1.25 DMIPS/MHz JTAG - IEEE 1149.1-1990 compatible Test Access Port (TAP) controller - Four-bit Instruction Register (IR) chain for storing JTAG instructions - IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST - ARM additional instructions: APACC, DPACC and ABORT - Integrated ARM Serial Wire Debug (SWD) Hibernation - System power control using discrete external regulator - Dedicated pin for waking from an external signal - Low-battery detection, signaling, and interrupt generation - 32-bit real-time clock (RTC) - Two 32-bit RTC match registers for timed wake-up and interrupt generation - Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal - RTC predivider trim for making fine adjustments to the clock rate - 64 32-bit words of non-volatile memory - Programmable interrupts for RTC match, external wake, and low battery events Internal Memory - 256 KB single-cycle flash * User-managed flash block protection on a 2-KB block basis * User-managed flash data programming * User-defined and managed flash-protection block - 64 KB single-cycle SRAM GPIOs - 1-46 GPIOs, depending on configuration - 5-V-tolerant in input configuration - Fast toggle capable of a change every two clock cycles - Programmable control for GPIO interrupts * Interrupt generation masking June 18, 2012 35 Texas Instruments-Production Data Architectural Overview * Edge-triggered on rising, falling, or both * Level-sensitive on High or Low values - Bit masking in both read and write operations through address lines - Pins configured as digital inputs are Schmitt-triggered. - Programmable control for GPIO pad configuration * Weak pull-up or pull-down resistors * 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications * Slew rate control for the 8-mA drive * Open drain enables * Digital input enables General-Purpose Timers - Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: * As a single 32-bit timer * As one 32-bit Real-Time Clock (RTC) to event capture * For Pulse Width Modulation (PWM) - 32-bit Timer modes * Programmable one-shot timer * Programmable periodic timer * Real-Time Clock when using an external 32.768-KHz clock as the input * User-enabled stalling when the controller asserts CPU Halt flag during debug - 16-bit Timer modes * General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) * Programmable one-shot timer * Programmable periodic timer * User-enabled stalling when the controller asserts CPU Halt flag during debug - 16-bit Input Capture modes * Input edge count capture 36 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller * Input edge time capture - 16-bit PWM mode * Simple PWM mode with software-programmable output inversion of the PWM signal ARM FiRM-compliant Watchdog Timer - 32-bit down counter with a programmable load register - Separate watchdog clock with an enable - Programmable interrupt generation logic with interrupt masking - Lock register protection from runaway software - Reset generation logic with an enable/disable - User-enabled stalling when the controller asserts the CPU Halt flag during debug UART - Three fully programmable 16C550-type UARTs with IrDA support - Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading - Programmable baud-rate generator allowing speeds up to 3.125 Mbps - Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface - FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 - Standard asynchronous communication bits for start, stop, and parity - Line-break generation and detection - Fully programmable serial interface characteristics * 5, 6, 7, or 8 data bits * Even, odd, stick, or no-parity bit generation/detection * 1 or 2 stop bit generation - IrDA serial-IR (SIR) encoder/decoder providing * Programmable use of IrDA Serial Infrared (SIR) or UART input/output * Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex * Support of normal 3/16 and low-power (1.41-2.23 s) bit durations * Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration Synchronous Serial Interface (SSI) June 18, 2012 37 Texas Instruments-Production Data Architectural Overview - Two SSI modules, each with the following features: - Master or slave operation - Programmable clock bit rate and prescale - Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep - Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces - Programmable data frame size from 4 to 16 bits - Internal loopback test mode for diagnostic/debug testing I2C - Devices on the I2C bus can be designated as either a master or a slave * Supports both sending and receiving data as either a master or a slave * Supports simultaneous master and slave operation - Four I2C modes * Master transmit * Master receive * Slave transmit * Slave receive - Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) - Master and slave interrupt generation * Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) * Slave generates interrupts when data has been sent or requested by a master - Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 10/100 Ethernet Controller - Conforms to the IEEE 802.3-2002 specification * 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line * 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler * Full-featured auto-negotiation 38 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller - Multiple operational modes * Full- and half-duplex 100 Mbps * Full- and half-duplex 10 Mbps * Power-saving and power-down modes - Highly configurable * Programmable MAC address * LED activity selection * Promiscuous mode support * CRC error-rejection control * User-configurable interrupts - Physical media manipulation * Automatic MDI/MDI-X cross-over correction * Register-programmable transmit amplitude * Automatic polarity correction and 10BASE-T signal reception - IEEE 1588 Precision Time Protocol - provides highly accurate time stamps for individual packets Analog Comparators - Three independent integrated analog comparators - Configurable for output to drive an output pin or generate an interrupt - Compare external pin input to external pin input or to internal programmable voltage reference - Compare a test voltage against any one of these voltages * An individual external reference voltage * A shared single external reference voltage * A shared internal reference voltage PWM - Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt selector - One fault input in hardware to promote low-latency shutdown - One 16-bit counter * Runs in Down or Up/Down mode June 18, 2012 39 Texas Instruments-Production Data Architectural Overview * Output frequency controlled by a 16-bit load value * Load value updates can be synchronized * Produces output signals at zero and load value - Two PWM comparators * Comparator value updates can be synchronized * Produces output signals on match - PWM generator * Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals * Produces two independent PWM signals - Dead-band generator * Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge * Can be bypassed, leaving input PWM signals unmodified - Flexible output control block with PWM output enable of each PWM signal * PWM output enable of each PWM signal * Optional output inversion of each PWM signal (polarity control) * Optional fault handling for each PWM signal * Synchronization of timers in the PWM generator blocks * Interrupt status summary of the PWM generator blocks QEI - Position integrator that tracks the encoder position - Velocity capture using built-in timer - The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) - Interrupt generation on: * Index pulse * Velocity-timer expiration * Direction change * Quadrature error detection 40 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Power - On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V - Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits - Low-power options on controller: Sleep and Deep-sleep modes - Low-power options for peripherals: software controls shutdown of individual peripherals - 3.3-V supply brown-out detection and reporting via interrupt or reset Flexible Reset Sources - Power-on reset (POR) - Reset pin assertion - Brown-out (BOR) detector alerts to system power drops - Software reset - Watchdog timer reset - Internal low drop-out (LDO) regulator output goes unregulated Industrial temperature 100-pin RoHS-compliant LQFP package Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications Remote monitoring Electronic point-of-sale (POS) machines Test and measurement equipment Network appliances and switches Factory automation HVAC and building control Gaming equipment Motion control Medical instrumentation Fire and security Power and energy June 18, 2012 41 Texas Instruments-Production Data Architectural Overview Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 43 depicts the features on the Stellaris LM3S6950 microcontroller. 42 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 1-1. Stellaris LM3S6950 Microcontroller High-Level Block Diagram JTAG/SWD ARM(R) CortexTM-M3 (50MHz) System Control and Clocks (w/ Precis. Osc.) Flash (256KB) DCode bus NVIC MPU ICode bus System Bus LM3S6950 Bus Matrix SRAM (64KB) SYSTEM PERIPHERALS Watchdog Timer (1) GPIOs (1-46) GeneralPurpose Timer (4) I2C (1) Ethernet MAC/PHY Advanced Peripheral Bus (APB) Hibernation Module SERIAL PERIPHERALS UART (3) SSI (2) ANALOG PERIPHERALS Analog Comparator (3) MOTION CONTROL PERIPHERALS PWM (6) QEI (1) June 18, 2012 43 Texas Instruments-Production Data Architectural Overview 1.4 Functional Overview The following sections provide an overview of the features of the LM3S6950 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in "Ordering and Contact Information" on page 705. 1.4.1 ARM CortexTM-M3 1.4.1.1 Processor Core (see page 51) All members of the Stellaris product family, including the LM3S6950 microcontroller, are designed around an ARM CortexTM-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. 1.4.1.2 Memory Map (see page 70) A memory map lists the location of instructions and data in memory. The memory map for the LM3S6950 controller can be found in Table 2-4 on page 70. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. 1.4.1.3 System Timer (SysTick) (see page 93) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. A high-speed alarm timer using the system clock. A variable rate alarm or signal timer--the duration is range-dependent on the reference clock used and the dynamic range of the counter. A simple counter. Software can use this to measure time to completion and time used. An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 94) The LM3S6950 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM(R) CortexTM-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 34 interrupts. 44 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 1.4.1.5 System Control Block (SCB) (see page 96) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.4.1.6 Memory Protection Unit (MPU) (see page 96) The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S6950 controller features Pulse Width Modulation (PWM) outputs and the Quadrature Encoder Interface (QEI). 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S6950, PWM motion control functionality can be achieved through: Dedicated, flexible motion control hardware using the PWM pins The motion control features of the general-purpose timers using the CCP pins PWM Pins (see page 572) The LM3S6950 PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. CCP Pins (see page 338) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. Fault Pin (see page 578) The LM3S6950 PWM module includes one fault-condition handling input to quickly provide low-latency shutdown and prevent damage to the motor being controlled. 1.4.2.2 QEI (see page 610) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. June 18, 2012 45 Texas Instruments-Production Data Architectural Overview The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. 1.4.3 Analog Peripherals For support of analog signals, the LM3S6950 microcontroller offers three analog comparators. 1.4.3.1 Analog Comparators (see page 559) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6950 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt . A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. 1.4.4 Serial Communications Peripherals The LM3S6950 controller supports both asynchronous and synchronous serial communications with: Three fully programmable 16C550-type UARTs Two SSI modules One I2C module Ethernet controller 1.4.4.1 UART (see page 392) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S6950 controller includes three fully programmable 16C550-type UARTs that support data transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 46 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 1.4.4.2 SSI (see page 435) Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications interface. The LM3S6950 controller includes two SSI modules that provide the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. Each SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. Each SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 473) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S6950 controller includes one I2C module that provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.4.4 Ethernet Controller (see page 510) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris(R) Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. June 18, 2012 47 Texas Instruments-Production Data Architectural Overview 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 284) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is comprised of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 1-46 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see "Signal Tables" on page 630 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. Pins configured as digital inputs are Schmitt-triggered. 1.4.5.2 Four Programmable Timers (see page 331) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 368) A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S6950 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 258) The LM3S6950 static random access memory (SRAM) controller supports 64 KB SRAM. The internal SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 48 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 1.4.6.2 Flash (see page 259) The LM3S6950 Flash controller supports 256 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 Additional Features 1.4.7.1 JTAG TAP Controller (see page 157) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. 1.4.7.2 System Control and Clocks (see page 170) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.7.3 Hibernation Module (see page 237) The Hibernation module provides logic to switch power off to the main processor and peripherals, and to wake on external or time-based events. The Hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: "Pin Diagram" on page 628 "Signal Tables" on page 630 June 18, 2012 49 Texas Instruments-Production Data Architectural Overview "Operating Characteristics" on page 660 "Electrical Characteristics" on page 661 "Package Information" on page 707 50 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 2 The Cortex-M3 Processor The ARM(R) CortexTM-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: Compact core. Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. Migration from the ARM7TM processor family for better performance and power efficiency. Full-featured debug solution - Serial Wire JTAG Debug Port (SWJ-DP) - Flash Patch and Breakpoint (FPB) unit for implementing breakpoints - Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling - Instrumentation Trace Macrocell (ITM) for support of printf style debugging - Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer Optimized for single-cycle flash usage Three sleep modes with clock gating for low power Single-cycle multiply instruction and hardware divide Atomic operations ARM Thumb2 mixed 16-/32-bit instruction set 1.25 DMIPS/MHz (R) The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. June 18, 2012 51 Texas Instruments-Production Data The Cortex-M3 Processor This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the CortexTM-M3/M4 Instruction Set Technical User's Manual. 2.1 Block Diagram The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb(R) instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 52 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep ARM Cortex-M3 CM3 Core Debug Instructions Data Trace Port Interface Unit Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace ROM Table Private Peripheral Bus (internal) Adv. Peripheral Bus Bus Matrix Serial Wire JTAG Debug Port Debug Access Port 2.2 Overview 2.2.1 System-Level Interface Serial Wire Output Trace Port (SWO) I-code bus D-code bus System bus The Cortex-M3 processor provides multiple interfaces using AMBA(R) technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 Integrated Configurable Debug The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSightTM-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM(R) Debug Interface V5 Architecture Specification for details on SWJ-DP. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. June 18, 2012 53 Texas Instruments-Production Data The Cortex-M3 Processor The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M3 debug capabilities, see theARM(R) Debug Interface V5 Architecture Specification. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 54. Figure 2-2. TPIU Block Diagram 2.2.4 Debug ATB Slave Port ATB Interface APB Slave Port APB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) Cortex-M3 System Component Details The Cortex-M3 includes the following system components: SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see "System Timer (SysTick)" on page 93). Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see "Nested Vectored Interrupt Controller (NVIC)" on page 94). System Control Block (SCB) 54 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see "System Control Block (SCB)" on page 96). Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see "Memory Protection Unit (MPU)" on page 96). 2.3 Programming Model This section describes the Cortex-M3 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M3 has two modes of operation: Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M3 has two privilege levels: Unprivileged In this mode, software has the following restrictions: - Limited access to the MSR and MRS instructions and no use of the CPS instruction - No access to the system timer, NVIC, or system control block - Possibly restricted access to memory or peripherals Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 69) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.3.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks: June 18, 2012 55 Texas Instruments-Production Data The Cortex-M3 Processor the main stack and the process stack, with a pointer for each held in independent registers (see the SP register on page 59). In Thread mode, the CONTROL register (see page 69) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 56. Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use Processor Mode Use Privilege Level Thread Applications Privileged or unprivileged Stack Used Handler Exception handlers Always privileged a Main stack or process stack a Main stack a. See CONTROL (page 69). 2.3.3 Register Map Figure 2-3 on page 56 shows the Cortex-M3 register set. Table 2-2 on page 57 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. Figure 2-3. Cortex-M3 Register Set R0 R1 R2 Low registers R3 R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP MSP Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register 56 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 2-2. Processor Register Map Offset Type Reset - R0 R/W - Cortex General-Purpose Register 0 58 - R1 R/W - Cortex General-Purpose Register 1 58 - R2 R/W - Cortex General-Purpose Register 2 58 - R3 R/W - Cortex General-Purpose Register 3 58 - R4 R/W - Cortex General-Purpose Register 4 58 - R5 R/W - Cortex General-Purpose Register 5 58 - R6 R/W - Cortex General-Purpose Register 6 58 - R7 R/W - Cortex General-Purpose Register 7 58 - R8 R/W - Cortex General-Purpose Register 8 58 - R9 R/W - Cortex General-Purpose Register 9 58 - R10 R/W - Cortex General-Purpose Register 10 58 - R11 R/W - Cortex General-Purpose Register 11 58 - R12 R/W - Cortex General-Purpose Register 12 58 - SP R/W - Stack Pointer 59 - LR R/W 0xFFFF.FFFF Link Register 60 - PC R/W - Program Counter 61 - PSR R/W 0x0100.0000 Program Status Register 62 - PRIMASK R/W 0x0000.0000 Priority Mask Register 66 - FAULTMASK R/W 0x0000.0000 Fault Mask Register 67 - BASEPRI R/W 0x0000.0000 Base Priority Mask Register 68 - CONTROL R/W 0x0000.0000 Control Register 69 2.3.4 Description See page Name Register Descriptions This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 56. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. June 18, 2012 57 Texas Instruments-Production Data The Cortex-M3 Processor Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General-Purpose Register 9 (R9) Register 11: Cortex General-Purpose Register 10 (R10) Register 12: Cortex General-Purpose Register 11 (R11) Register 13: Cortex General-Purpose Register 12 (R12) The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - DATA Type Reset DATA Type Reset Bit/Field Name Type Reset 31:0 DATA R/W - Description Register data. 58 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - SP Type Reset SP Type Reset Bit/Field Name Type Reset 31:0 SP R/W - Description This field is the address of the stack pointer. June 18, 2012 59 Texas Instruments-Production Data The Cortex-M3 Processor Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 86 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 LINK R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF This field is the return address. 60 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - PC Type Reset PC Type Reset Bit/Field Name Type Reset 31:0 PC R/W - Description This field is the current program address. June 18, 2012 61 Texas Instruments-Production Data The Cortex-M3 Processor Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: Application Program Status Register (APSR), bits 31:27, Execution Program Status Register (EPSR), bits 26:24, 15:10 Interrupt Program Status Register (IPSR), bits 5:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see "Exception Entry and Return" on page 84). IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. page 62 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register Type PSR R/W Combination APSR, EPSR, and IPSR IEPSR RO EPSR and IPSR a, b a APSR and IPSR b APSR and EPSR IAPSR R/W EAPSR R/W a. The processor ignores writes to the IPSR bits. b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type R/W, reset 0x0100.0000 Type Reset 31 30 29 28 27 N Z C V Q 26 25 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 ICI / IT ICI / IT Type Reset RO 0 RO 0 RO 0 24 23 22 21 20 THUMB reserved RO 0 RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 reserved RO 0 ISRNUM RO 0 62 RO 0 RO 0 RO 0 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 31 N R/W 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z R/W 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero. The value of this bit is only meaningful when accessing PSR or APSR. 29 C R/W 0 APSR Carry or Borrow Flag Value Description 1 The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 0 The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessing PSR or APSR. 28 V R/W 0 APSR Overflow Flag Value Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. The value of this bit is only meaningful when accessing PSR or APSR. 27 Q R/W 0 APSR DSP Overflow and Saturation Flag Value Description 1 DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. June 18, 2012 63 Texas Instruments-Production Data The Cortex-M3 Processor Bit/Field Name Type Reset 26:25 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 24 THUMB RO 1 EPSR Thumb State This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit: The BLX, BX and POP{PC} instructions Restoration from the stacked xPSR value on an exception return Bit 0 of the vector value on an exception entry or reset Attempting to execute instructions when this bit is clear results in a fault or lockup. See "Lockup" on page 88 for more information. The value of this bit is only meaningful when accessing PSR or EPSR. 23:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 ICI / IT RO 0x0 EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 9:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 64 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 5:0 ISRNUM RO 0x00 IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). Value Description 0x00 Thread mode 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3B Interrupt Vector 43 0x3C-0x3F Reserved See "Exception Types" on page 79 for more information. The value of this field is only meaningful when accessing PSR or IPSR. June 18, 2012 65 Texas Instruments-Production Data The Cortex-M3 Processor Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see "Exception Types" on page 79. Priority Mask Register (PRIMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PRIMASK R/W 0 RO 0 PRIMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority. 0 No effect. 66 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see "Exception Types" on page 79. Fault Mask Register (FAULTMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 FAULTMASK R/W 0 RO 0 FAULTMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI. 0 No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. June 18, 2012 67 Texas Instruments-Production Data The Cortex-M3 Processor Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see "Exception Types" on page 79. Base Priority Mask Register (BASEPRI) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset BASEPRI RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:5 BASEPRI R/W 0x0 R/W 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. Value Description 4:0 reserved RO 0x0 0x0 All exceptions are unmasked. 0x1 All exceptions with priority level 1-7 are masked. 0x2 All exceptions with priority level 2-7 are masked. 0x3 All exceptions with priority level 3-7 are masked. 0x4 All exceptions with priority level 4-7 are masked. 0x5 All exceptions with priority level 5-7 are masked. 0x6 All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 68 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 86). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as detailed in the CortexTM-M3/M4 Instruction Set Technical User's Manual, or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 86. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the CortexTM-M3/M4 Instruction Set Technical User's Manual. Control Register (CONTROL) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASP TMPL RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 ASP R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Active Stack Pointer Value Description 1 PSP is the current stack pointer. 0 MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 0 TMPL R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. June 18, 2012 69 Texas Instruments-Production Data The Cortex-M3 Processor 2.3.5 Exceptions and Interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See "Exception Entry and Return" on page 84 for more information. The NVIC registers control interrupt handling. See "Nested Vectored Interrupt Controller (NVIC)" on page 94 for more information. 2.3.6 Data Types The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See "Memory Regions, Types and Attributes" on page 72 for more information. 2.4 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the LM3S6950 controller is provided in Table 2-4 on page 70. In this manual, register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see "Bit-Banding" on page 74). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see "Cortex-M3 Peripherals" on page 93). Note: Within the memory map, all reserved space returns a bus fault when read or written. Table 2-4. Memory Map Start End Description For details, see page ... 0x0000.0000 0x0003.FFFF On-chip Flash 263 0x0004.0000 0x1FFF.FFFF Reserved - 0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAM 258 0x2001.0000 0x21FF.FFFF Reserved - 0x2200.0000 0x221F.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 0x2000.0000 258 0x2220.0000 0x3FFF.FFFF Reserved - 0x4000.0000 0x4000.0FFF Watchdog timer 0 371 0x4000.1000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 296 0x4000.5000 0x4000.5FFF GPIO Port B 296 0x4000.6000 0x4000.6FFF GPIO Port C 296 0x4000.7000 0x4000.7FFF GPIO Port D 296 0x4000.8000 0x4000.8FFF SSI0 447 Memory FiRM Peripherals 70 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4000.9000 0x4000.9FFF SSI1 447 0x4000.A000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 401 0x4000.D000 0x4000.DFFF UART1 401 0x4000.E000 0x4000.EFFF UART2 401 0x4000.F000 0x4001.FFFF Reserved - 0x4002.0000 0x4002.0FFF I2C 0 488 0x4002.1000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 296 0x4002.5000 0x4002.5FFF GPIO Port F 296 0x4002.6000 0x4002.6FFF GPIO Port G 296 0x4002.7000 0x4002.7FFF Reserved - 0x4002.8000 0x4002.8FFF PWM 581 0x4002.9000 0x4002.BFFF Reserved - 0x4002.C000 0x4002.CFFF QEI0 615 0x4002.D000 0x4002.FFFF Reserved - 0x4003.0000 0x4003.0FFF Timer 0 343 0x4003.1000 0x4003.1FFF Timer 1 343 0x4003.2000 0x4003.2FFF Timer 2 343 0x4003.3000 0x4003.3FFF Timer 3 343 0x4003.4000 0x4003.BFFF Reserved - 0x4003.C000 0x4003.CFFF Analog Comparators 559 0x4003.D000 0x400F.BFFF Reserved - 0x400F.C000 0x400F.CFFF Hibernation Module 245 0x400F.D000 0x400F.DFFF Flash memory control 263 0x400F.E000 0x400F.EFFF System control 184 0x400F.F000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0xDFFF.FFFF Reserved - 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 53 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 53 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 53 0xE000.3000 0xE000.DFFF Reserved - 0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB) 101 0xE000.F000 0xE003.FFFF Reserved - 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 54 0xE004.1000 0xFFFF.FFFF Reserved - Peripherals Private Peripheral Bus June 18, 2012 71 Texas Instruments-Production Data The Cortex-M3 Processor 2.4.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: Normal: The processor can re-order transactions for efficiency and perform speculative reads. Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 2.4.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see "Software Ordering of Memory Accesses" on page 73). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2. 2.4.3 Behavior of Memory Accesses Table 2-5 on page 72 shows the behavior of accesses to each region in the memory map. See "Memory Regions, Types and Attributes" on page 72 for more information on memory types and the XN attribute. Stellaris devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 70 for more information). Table 2-5. Memory Access Behavior Address Range Memory Region Memory Type Execute Never (XN) Description 0x0000.0000 - 0x1FFF.FFFF Code Normal - This executable region is for program code. Data can also be stored here. 0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 74). 0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band alias areas (see Table 2-7 on page 75). 0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data. 72 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 2-5. Memory Access Behavior (continued) Address Range Memory Region Memory Type Execute Never (XN) Description 0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory. 0xE000.0000- 0xE00F.FFFF Private peripheral bus Strongly Ordered XN This region includes the NVIC, system timer, and system control block. 0xE010.0000- 0xFFFF.FFFF Reserved - - - The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M3 has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see "Memory Protection Unit (MPU)" on page 96. The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 2.4.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. The processor has multiple bus interfaces. Memory or devices in the memory map have different wait states. Some memory accesses are buffered or speculative. "Memory System Ordering of Memory Accesses" on page 72 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M3 has the following memory barrier instructions: The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: MPU programming - If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. June 18, 2012 73 Texas Instruments-Production Data The Cortex-M3 Processor - Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. Memory map switching If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use of DMB instructions. For more information on the memory barrier instructions, see the CortexTM-M3/M4 Instruction Set Technical User's Manual. 2.4.5 Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 74. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 75. For the specific address range of the bit-band regions, see Table 2-4 on page 70. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Table 2-6. SRAM Memory Bit-Banding Regions Address Range Memory Region Start End 0x2000.0000 0x2000.FFFF Instruction and Data Accesses SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 74 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 2-6. SRAM Memory Bit-Banding Regions (continued) Address Range Start End 0x2200.0000 0x221F.FFFF Memory Region Instruction and Data Accesses SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 2-7. Peripheral Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses 0x400F.FFFF Peripheral bit-band region Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x43FF.FFFF Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Start End 0x4000.0000 0x4200.0000 The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 76 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: June 18, 2012 75 Texas Instruments-Production Data The Cortex-M3 Processor 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 7 3 1-MB SRAM Bit-Band Region 7 6 5 4 3 2 1 0 7 6 0x200F.FFFF 7 6 5 4 3 2 0x2000.0003 2.4.5.1 5 4 3 2 1 0 7 6 0x200F.FFFE 1 0 7 6 5 4 3 2 5 4 3 2 1 0 6 0x200F.FFFD 1 0 0x2000.0002 7 6 5 4 3 2 0x2000.0001 5 4 2 1 0 1 0 0x200F.FFFC 1 0 7 6 5 4 3 2 0x2000.0000 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 Directly Accessing a Bit-Band Region "Behavior of Memory Accesses" on page 72 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 77 illustrates how data is stored. 76 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 2-5. Data Storage Memory 7 Register 0 31 2.4.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: The word instructions LDREX and STREX The halfword instructions LDREXH and STREXH The byte instructions LDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Modify the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location. 4. Test the returned status bit. If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: June 18, 2012 77 Texas Instruments-Production Data The Cortex-M3 Processor 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: It executes a CLREX instruction. It executes a Store-Exclusive instruction, regardless of whether the write succeeds. An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the CortexTM-M3/M4 Instruction Set Technical User's Manual. 2.5 Exception Model The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 80 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 34 interrupts (listed in Table 2-9 on page 81). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in "Nested Vectored Interrupt Controller (NVIC)" on page 94. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See "Nested Vectored Interrupt Controller (NVIC)" on page 94 for more information on exceptions and interrupts. 78 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 2.5.1 Exception States Each exception is in one of the following states: Inactive. The exception is not active and not pending. Pending. The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active. An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. Active and Pending. The exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 Exception Types The exception types are: Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. Hard Fault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. Memory Management Fault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: - An undefined instruction - An illegal unaligned access - Invalid state on instruction execution June 18, 2012 79 Texas Instruments-Production Data The Cortex-M3 Processor - An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. SysTick. A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 81 lists the interrupts on the LM3S6950 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 80 shows as having configurable priority (see the SYSHNDCTRL register on page 135 and the DIS0 register on page 110). For more information about hard faults, memory management faults, bus faults, and usage faults, see "Fault Handling" on page 86. Table 2-8. Exception Types Exception Type a Vector Number Priority Vector Address or b Offset - 0 - 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset. Reset 1 -3 (highest) 0x0000.0004 Asynchronous Non-Maskable Interrupt (NMI) 2 -2 0x0000.0008 Asynchronous Hard Fault 3 -1 0x0000.000C - c 0x0000.0010 Synchronous c 0x0000.0014 Synchronous when precise and asynchronous when imprecise c Synchronous Memory Management 4 programmable Bus Fault 5 programmable Usage Fault 6 programmable 0x0000.0018 7-10 - - - Activation c c Reserved SVCall 11 programmable 0x0000.002C Synchronous Debug Monitor 12 programmable 0x0000.0030 Synchronous - 13 - - 80 Reserved June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 2-8. Exception Types (continued) Exception Type PendSV SysTick a Vector Number Priority 14 programmable 15 Interrupts Vector Address or b Offset c 0x0000.0038 Asynchronous c 0x0000.003C Asynchronous programmable 16 and above Activation d programmable 0x0000.0040 and above Asynchronous a. 0 is the default priority for all the programmable priorities. b. See "Vector Table" on page 82. c. See SYSPRI1 on page 132. d. See PRIn registers on page 118. Table 2-9. Interrupts Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 0-15 - 0x0000.0000 0x0000.003C 16 0 0x0000.0040 GPIO Port A 17 1 0x0000.0044 GPIO Port B 18 2 0x0000.0048 GPIO Port C 19 3 0x0000.004C GPIO Port D 20 4 0x0000.0050 GPIO Port E 21 5 0x0000.0054 UART0 22 6 0x0000.0058 UART1 23 7 0x0000.005C SSI0 24 8 0x0000.0060 I2C0 25 9 0x0000.0064 PWM Fault 26 10 0x0000.0068 PWM Generator 0 27 11 0x0000.006C PWM Generator 1 28 12 0x0000.0070 PWM Generator 2 29 13 0x0000.0074 QEI0 30-33 14-17 - 34 18 0x0000.0088 Watchdog Timer 0 35 19 0x0000.008C Timer 0A 36 20 0x0000.0090 Timer 0B 37 21 0x0000.0094 Timer 1A 38 22 0x0000.0098 Timer 1B 39 23 0x0000.009C Timer 2A 40 24 0x0000.00A0 Timer 2B 41 25 0x0000.00A4 Analog Comparator 0 42 26 0x0000.00A8 Analog Comparator 1 43 27 0x0000.00AC Analog Comparator 2 44 28 0x0000.00B0 System Control 45 29 0x0000.00B4 Flash Memory Control 46 30 0x0000.00B8 GPIO Port F 47 31 0x0000.00BC GPIO Port G Processor exceptions Reserved June 18, 2012 81 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-9. Interrupts (continued) 2.5.3 Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 48 32 - 49 33 0x0000.00C4 UART2 50 34 0x0000.00C8 SSI1 51 35 0x0000.00CC Timer 3A 52 36 0x0000.00D0 Timer 3B 53-57 37-41 - Reserved 58 42 0x0000.00E8 Ethernet Controller 59 43 0x0000.00EC Hibernation Module Reserved Exception Handlers The processor handles exceptions using: Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 80. Figure 2-6 on page 83 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code 82 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 2-6. Vector Table Exception number IRQ number 59 43 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x00EC . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 12 11 Vector IRQ43 . . . IRQ2 IRQ1 IRQ0 Systick PendSV Reserved Reserved for Debug -5 10 0x002C 9 SVCall Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault NMI Reset Initial SP value On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see "Vector Table" on page 82). Note that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary. 2.5.5 Exception Priorities As Table 2-8 on page 80 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 132 and page 118. Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. June 18, 2012 83 Texas Instruments-Production Data The Cortex-M3 Processor If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.5.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: An upper field that defines the group priority A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 126. 2.5.7 Exception Entry and Return Descriptions of exception handling use the following terms: Preemption. When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See "Interrupt Priority Grouping" on page 84 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See "Exception Entry" on page 85 more information. Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See "Exception Return" on page 86 for more information. Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On 84 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK on page 66, FAULTMASK on page 67, and BASEPRI on page 68). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Figure 2-7. Exception Stack Frame ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during stacking. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. June 18, 2012 85 Texas Instruments-Production Data The Cortex-M3 Processor 2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: An LDM or POP instruction that loads the PC A BX instruction using any register An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 2-10 on page 86 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 2-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFF.FFF0 Reserved 0xFFFF.FFF1 Return to Handler mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved 0xFFFF.FFF9 Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFFA - 0xFFFF.FFFC Reserved 0xFFFF.FFFD Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. 0xFFFF.FFFE - 0xFFFF.FFFF 2.6 Reserved Fault Handling Faults are a subset of the exceptions (see "Exception Model" on page 78). The following conditions generate a fault: A bus error on an instruction fetch or vector table load or a data access. An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. Attempting to execute an instruction from a memory region marked as Non-Executable (XN). An MPU fault because of a privilege violation or an attempt to access an unmanaged region. 86 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 2.6.1 Fault Types Table 2-11 on page 87 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 139 for more information about the fault status registers. Table 2-11. Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED MPU or default memory mismatch on Memory management instruction access fault Memory Management Fault Status (MFAULTSTAT) IERR MPU or default memory mismatch on Memory management data access fault Memory Management Fault Status (MFAULTSTAT) DERR MPU or default memory mismatch on Memory management exception stacking fault Memory Management Fault Status (MFAULTSTAT) MSTKE MPU or default memory mismatch on Memory management exception unstacking fault Memory Management Fault Status (MFAULTSTAT) MUSTKE Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction Usage fault b set state Usage Fault Status (UFAULTSTAT) INVSTAT a Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. 2.6.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 132). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 135). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in "Exception Model" on page 78. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. June 18, 2012 87 Texas Instruments-Production Data The Cortex-M3 Processor A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: 2.6.3 Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 88. Table 2-12. Fault Status and Fault Address Registers 2.6.4 Handler Status Register Name Address Register Name Register Description Hard fault Hard Fault Status (HFAULTSTAT) - page 145 Memory management Memory Management Fault Status fault (MFAULTSTAT) Memory Management Fault Address (MMADDR) page 139 Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address (FAULTADDR) page 139 Usage fault Usage Fault Status (UFAULTSTAT) - page 139 page 146 page 147 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger. Note: 2.7 If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. Power Management The Cortex-M3 processor sleep modes reduce power consumption: Sleep mode stops the processor clock. Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 128). For more information about the behavior of the sleep modes, see "System Control" on page 181. 88 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. 2.7.1 Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see "Wake Up from WFI or Sleep-on-Exit" on page 89). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information. 2.7.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation occurs if an SEV instruction has been executed. Software cannot access this register directly. See the CortexTM-M3/M4 Instruction Set Technical User's Manual for more information. 2.7.1.3 Sleep-on-Exit If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears PRIMASK. For more information about PRIMASK and FAULTMASK, see page 66 and page 67. 2.7.2.2 Wake Up from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry. June 18, 2012 89 Texas Instruments-Production Data The Cortex-M3 Processor In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 128. 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 90 lists the supported instructions. Note: In Table 2-13 on page 90: Angle brackets, <>, enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the CortexTM-M3/M4 Instruction Set Technical User's Manual. Table 2-13. Cortex-M3 Instruction Summary Mnemonic Operands Brief Description Flags ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V ADR Rd, label Load PC-relative address - AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N,Z,C B label Branch - BFC Rd, #lsb, #width Bit field clear - BFI Rd, Rn, #lsb, #width Bit field insert - BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C BKPT #imm Breakpoint - BL label Branch with link - BLX Rm Branch indirect with link - BX Rm Branch indirect - CBNZ Rn, label Compare and branch if non-zero - CBZ Rn, label Compare and branch if zero - CLREX - Clear exclusive - CLZ Rd, Rm Count leading zeros - CMN Rn, Op2 Compare negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change processor state, disable interrupts - CPSIE i Change processor state, enable interrupts - DMB - Data memory barrier - DSB - Data synchronization barrier - 90 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB - Instruction synchronization barrier - IT - If-Then condition block - LDM Rn{!}, reglist Load multiple registers, increment after - LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement before LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after - LDR Rt, [Rn, #offset] Load register with word - LDRB, LDRBT Rt, [Rn, #offset] Load register with byte - LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes - LDREX Rt, [Rn, #offset] Load register exclusive - LDREXB Rt, [Rn] Load register exclusive with byte - LDREXH Rt, [Rn] Load register exclusive with halfword - LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword - LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte - LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword - LDRT Rt, [Rn, #offset] Load register with word - LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N,Z,C LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result - MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result - MOV, MOVS Rd, Op2 Move N,Z,C MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C MOVT Rd, #imm16 Move top - MRS Rd, spec_reg Move from special register to general register - MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP - No operation - ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - RBIT Rd, Rn Reverse bits - REV Rd, Rn Reverse byte order in a word - REV16 Rd, Rn Reverse byte order in each halfword - REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - ROR, RORS Rd, Rm, <Rs|#n> Rotate right N,Z,C RRX, RRXS Rd, Rm Rotate right with extend N,Z,C June 18, 2012 - 91 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed bit field extract - SDIV {Rd,} Rn, Rm Signed divide - SEV - Send event - SMLAL RdLo, RdHi, Rn, Rm Signed multiply with accumulate (32x32+64), 64-bit result - SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result - SSAT Rd, #n, Rm {,shift #s} Signed saturate Q STM Rn{!}, reglist Store multiple registers, increment after - STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement before STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after - STR Rt, [Rn {, #offset}] Store register word - STRB, STRBT Rt, [Rn {, #offset}] Store register byte - STRD Rt, Rt2, [Rn {, #offset}] Store register two words - STREX Rt, Rt, [Rn {, #offset}] Store register exclusive - STREXB Rd, Rt, [Rn] Store register exclusive byte - STREXH Rd, Rt, [Rn] Store register exclusive halfword - STRH, STRHT Rt, [Rn {, #offset}] Store register halfword - STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte - STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword - STRT Rt, [Rn {, #offset}] Store register word - SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V SVC #imm Supervisor call - SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - TBB [Rn, Rm] Table branch byte - TBH [Rn, Rm, LSL #1] Table branch halfword - TEQ Rn, Op2 Test equivalence N,Z,C TST Rn, Op2 Test N,Z,C UBFX Rd, Rn, #lsb, #width Unsigned bit field extract - UDIV {Rd,} Rn, Rm Unsigned divide - UMLAL RdLo, RdHi, Rn, Rm Unsigned multiply with accumulate (32x32+32+32), 64-bit result - UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result - USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q UXTB {Rd,} Rm, {,ROR #n} Zero extend a Byte - UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword - WFE - Wait for event - WFI - Wait for interrupt - 92 - June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 3 Cortex-M3 Peripherals (R) This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals, including: SysTick (see page 93) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. Nested Vectored Interrupt Controller (NVIC) (see page 94) - Facilitates low-latency exception and interrupt handling - Controls power management - Implements system control registers System Control Block (SCB) (see page 96) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. Memory Protection Unit (MPU) (see page 96) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. Table 3-1 on page 93 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table 3-1. Core Peripheral Register Regions Address Core Peripheral Description (see page ...) 0xE000.E010-0xE000.E01F System Timer 93 0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 94 0xE000.ED00-0xE000.ED3F System Control Block 96 0xE000.ED90-0xE000.EDB8 Memory Protection Unit 96 0xE000.EF00-0xE000.EF03 3.1 Functional Description This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals: SysTick, NVIC, SCB and MPU. 3.1.1 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. A high-speed alarm timer using the system clock. June 18, 2012 93 Texas Instruments-Production Data Cortex-M3 Peripherals A variable rate alarm or signal timer--the duration is range-dependent on the reference clock used and the dynamic range of the counter. A simple counter used to measure time to completion and time used. An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value. SysTick Current Value (STCURRENT): The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. Note: 3.1.2 When the processor is halted for debugging, the counter does not decrement. Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: 34 interrupts. A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Low-latency exception and interrupt handling. Level and pulse detection of interrupt signals. Dynamic reprioritization of interrupts. Grouping of priority values into group priority and subpriority fields. Interrupt tail-chaining. An external Non-maskable interrupt (NMI). 94 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see "Hardware and Software Control of Interrupts" on page 95 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 Hardware and Software Control of Interrupts The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: The NVIC detects that the interrupt signal is High and the interrupt is not active. The NVIC detects a rising edge on the interrupt signal. Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 112 or SWTRIG on page 120. A pending interrupt remains pending until one of the following: The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: - For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. - For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. Software writes to the corresponding interrupt clear-pending register bit - For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. June 18, 2012 95 Texas Instruments-Production Data Cortex-M3 Peripherals - For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 Memory Protection Unit (MPU) This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see "Memory Regions, Types and Attributes" on page 72 for more information). Table 3-2 on page 96 shows the possible MPU region attributes. See the section called "MPU Configuration for a Stellaris Microcontroller" on page 100 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Description Strongly Ordered All accesses to Strongly Ordered memory occur in program order. Device Memory-mapped peripherals Normal Normal memory To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. The MPUATTR register can be accessed with byte or aligned halfword or word accesses. 96 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 3.1.4.1 Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] BIC R2, R2, #1 STRH R2, [R0, #0x8] STR R4, [R0, #0x4] STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; ; ; ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Disable Region Size and Enable Region Base Address Region Attribute Enable Region Size and Enable Software must use memory barrier instructions: Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. June 18, 2012 97 Texas Instruments-Production Data Cortex-M3 Peripherals For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that the MPU Region Base Address (MPUBASE) register (see page 152) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 154) to disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. 98 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 99 shows. Figure 3-1. SRD Use Example Region 2, with subregions Region 1 Base address of both regions 3.1.4.2 Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Access Permission Attributes The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 99 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called "MPU Configuration for a Stellaris Microcontroller" on page 100 for information on programming the MPU for Stellaris implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding TEX S 000b x C B Memory Type Shareability Other Attributes a 0 0 Strongly Ordered Shareable - a - 000 x 0 1 Device Shareable 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable 001 0 0 0 Normal Not shareable 001 1 0 0 Normal Shareable Outer and inner noncacheable. 001 x a 0 1 Reserved encoding - - a Outer and inner write-through. No write allocate. 001 x 1 0 Reserved encoding - - 001 0 1 1 Normal Not shareable 001 1 1 1 Normal Shareable Outer and inner write-back. Write and read allocate. 010 x a 0 0 Device Not shareable Nonshared Device. a 0 1 Reserved encoding - - a 1 x Reserved encoding - - 010 x 010 x a June 18, 2012 99 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S C B Memory Type Shareability Other Attributes 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. a. The MPU ignores the value of this bit. Table 3-4 on page 100 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-0x7. Table 3-4. Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 3-5 on page 100 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software. Table 3-5. AP Bit Field Encoding AP Bit Field Privileged Permissions Unprivileged Permissions Description 000 No access No access All accesses generate a permission fault. 001 R/W No access Access from privileged software only. 010 R/W RO Writes by unprivileged software generate a permission fault. 011 R/W R/W Full access. 100 Unpredictable Unpredictable Reserved. 101 RO No access Reads by privileged software only. 110 RO RO Read-only, by privileged or unprivileged software. 111 RO RO Read-only, by privileged or unprivileged software. MPU Configuration for a Stellaris Microcontroller Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 100. Table 3-6. Memory Region Attributes for Stellaris Microcontrollers Memory Region TEX S C B Memory Type and Attributes Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through External SRAM 000b 1 1 1 Normal memory, shareable, write-back, write-allocate Peripherals 000b 1 0 1 Device memory, shareable 100 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. 3.1.4.3 MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault (see "Exceptions and Interrupts" on page 70 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 139 for more information. 3.2 Register Map Table 3-7 on page 101 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU and SCB registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 3-7. Peripherals Register Map Offset Name Type Reset Description See page System Timer (SysTick) Registers 0x010 STCTRL R/W 0x0000.0000 SysTick Control and Status Register 104 0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 106 0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 107 Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 108 0x104 EN1 R/W 0x0000.0000 Interrupt 32-43 Set Enable 109 0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 110 0x184 DIS1 R/W 0x0000.0000 Interrupt 32-43 Clear Enable 111 0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 112 0x204 PEND1 R/W 0x0000.0000 Interrupt 32-43 Set Pending 113 0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 114 0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-43 Clear Pending 115 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 116 0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-43 Active Bit 117 0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 118 0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 118 0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 118 0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 118 0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 118 June 18, 2012 101 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-7. Peripherals Register Map (continued) Description See page Offset Name Type Reset 0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 118 0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 118 0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 118 0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 118 0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 118 0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 118 0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 120 System Control Block (SCB) Registers 0xD00 CPUID RO 0x411F.C231 CPU ID Base 121 0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 122 0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 125 0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 126 0xD10 SYSCTRL R/W 0x0000.0000 System Control 128 0xD14 CFGCTRL R/W 0x0000.0000 Configuration and Control 130 0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 132 0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 133 0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 134 0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 135 0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 139 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 145 0xD34 MMADDR R/W - Memory Management Fault Address 146 0xD38 FAULTADDR R/W - Bus Fault Address 147 Memory Protection Unit (MPU) Registers 0xD90 MPUTYPE RO 0x0000.0800 MPU Type 148 0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 149 0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 151 0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 152 0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 154 0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 152 0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 154 0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 152 0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 154 102 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 3-7. Peripherals Register Map (continued) Name Type Reset 0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 152 0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 154 3.3 Description See page Offset System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. June 18, 2012 103 Texas Instruments-Production Data Cortex-M3 Peripherals Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 16 COUNT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 CLK_SRC INTEN ENABLE R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 COUNT RO 0 Count Flag Value Description 0 The SysTick timer has not counted to 0 since the last time this bit was read. 1 The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM(R) Debug Interface V5 Architecture Specification for more information on MasterType. 15:3 reserved RO 0x000 2 CLK_SRC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source Value Description 0 External reference clock. (Not implemented for most Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. 104 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1 INTEN R/W 0 0 ENABLE R/W 0 Description Interrupt Enable Value Description 0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1 An interrupt is generated to the NVIC when SysTick counts to 0. Enable Value Description 0 The counter is disabled. 1 Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. June 18, 2012 105 Texas Instruments-Production Data Cortex-M3 Peripherals Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 18 17 16 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 19 RELOAD RELOAD Type Reset Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 RELOAD R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. 106 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset 20 19 18 17 16 CURRENT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 CURRENT Type Reset R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 CURRENT R/WC 0x00.0000 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. 3.4 NVIC Register Descriptions This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 125. June 18, 2012 107 Texas Instruments-Production Data Cortex-M3 Peripherals Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Note: This register can only be accessed from privileged mode. The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 81 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 INT R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. 108 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 Note: This register can only be accessed from privileged mode. The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 32-43 Set Enable (EN1) Base 0xE000.E000 Offset 0x104 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset INT RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 INT R/W 0x000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. June 18, 2012 109 Texas Instruments-Production Data Cortex-M3 Peripherals Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Note: This register can only be accessed from privileged mode. The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 81 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. 110 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 Note: This register can only be accessed from privileged mode. The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments. Interrupt 32-43 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 INT RO 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 INT R/W 0x000 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. June 18, 2012 111 Texas Instruments-Production Data Cortex-M3 Peripherals Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Note: This register can only be accessed from privileged mode. The PEND0 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 81 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. 112 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 Note: This register can only be accessed from privileged mode. The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments. Interrupt 32-43 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 INT RO 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 INT R/W 0x000 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. June 18, 2012 113 Texas Instruments-Production Data Cortex-M3 Peripherals Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Note: This register can only be accessed from privileged mode. The UNPEND0 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 81 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 114 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 Note: This register can only be accessed from privileged mode. The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments. Interrupt 32-43 Clear Pending (UNPEND1) Base 0xE000.E000 Offset 0x284 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 INT RO 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 INT R/W 0x000 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. June 18, 2012 115 Texas Instruments-Production Data Cortex-M3 Peripherals Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Note: This register can only be accessed from privileged mode. The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 81 for interrupt assignments. Caution - Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT RO Reset Description 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 116 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 81 for interrupt assignments. Caution - Do not manually set or clear the bits in this register. Interrupt 32-43 Active Bit (ACTIVE1) Base 0xE000.E000 Offset 0x304 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 INT RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 INT RO 0x000 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. June 18, 2012 117 Texas Instruments-Production Data Cortex-M3 Peripherals Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 Note: This register can only be accessed from privileged mode. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Interrupt Bits 31:29 Interrupt [4n+3] Bits 23:21 Interrupt [4n+2] Bits 15:13 Interrupt [4n+1] Bits 7:5 Interrupt [4n] See Table 2-9 on page 81 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 126) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 INTD Type Reset R/W 0 15 R/W 0 R/W 0 RO 0 RO 0 14 13 12 11 INTB Type Reset R/W 0 R/W 0 26 25 24 23 reserved RO 0 RO 0 RO 0 R/W 0 10 9 8 7 reserved R/W 0 RO 0 RO 0 RO 0 22 21 20 19 INTC R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 INTA RO 0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 118 RO 0 RO 0 RO 0 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 31:29 INTD R/W 0x0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 INTC R/W 0x0 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 INTB R/W 0x0 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 INTA R/W 0x0 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 119 Texas Instruments-Production Data Cortex-M3 Peripherals Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 81 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 130) is set, unprivileged software can access the SWTRIG register. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 INTID Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 INTID WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 3.5 System Control Block (SCB) Register Descriptions This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. 120 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 26: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM(R) CortexTM-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x411F.C231 31 30 29 28 27 26 25 24 23 22 IMP Type Reset 21 20 19 18 VAR RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PARTNO Type Reset RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 17 16 RO 1 RO 1 1 0 RO 0 RO 1 CON REV RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 IMP RO 0x41 Implementer Code RO 1 RO 1 RO 0 RO 0 Value Description 0x41 ARM 23:20 VAR RO 0x1 Variant Number Value Description 0x1 19:16 CON RO 0xF The rn value in the rnpn product revision identifier, for example, the 1 in r1p1. Constant Value Description 0xF 15:4 PARTNO RO 0xC23 Always reads as 0xF. Part Number Value Description 0xC23 Cortex-M3 processor. 3:0 REV RO 0x1 Revision Number Value Description 0x1 The pn value in the rnpn product revision identifier, for example, the 1 in r1p1. June 18, 2012 121 Texas Instruments-Production Data Cortex-M3 Peripherals Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type R/W, reset 0x0000.0000 31 NMISET Type Reset 30 29 reserved 28 26 25 24 PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved 23 22 21 20 ISRPRE ISRPEND 19 18 17 reserved 16 VECPEND R/W 0 RO 0 RO 0 R/W 0 WO 0 R/W 0 WO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 VECPEND Type Reset 27 RO 0 RETBASE RO 0 reserved RO 0 Bit/Field Name Type Reset 31 NMISET R/W 0 RO 0 VECACT Description NMI Set Pending Value Description 0 On a read, indicates an NMI exception is not pending. On a write, no effect. 1 On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 30:29 reserved RO 0x0 28 PENDSV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PendSV Set Pending Value Description 0 On a read, indicates a PendSV exception is not pending. On a write, no effect. 1 On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. 122 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 27 UNPENDSV WO 0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 26 PENDSTSET R/W 0 SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect. 1 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to the PENDSTCLR bit. 25 PENDSTCLR WO 0 SysTick Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. 24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 ISRPRE RO 0 Debug Interrupt Handling Value Description 0 The release from halt does not take an interrupt. 1 The release from halt takes an interrupt. This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 22 ISRPEND RO 0 Interrupt Pending Value Description 0 No interrupt is pending. 1 An interrupt is pending. This bit provides status for all interrupts excluding NMI and Faults. 21:18 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 123 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description 17:12 VECPEND RO 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Value Description 0x00 No exceptions are pending 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3B Interrupt Vector 43 0x3C-0x3F Reserved 11 RETBASE RO 0 Return to Base Value Description 0 There are preempted active exceptions to execute. 1 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). 10:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 VECACT RO 0x00 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 62). 124 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 28: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.0000 31 30 reserved Type Reset 29 28 27 26 25 24 23 BASE 22 21 20 19 18 17 16 OFFSET RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 OFFSET Type Reset R/W 0 R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:30 reserved RO 0x0 29 BASE R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Base Value Description 28:8 OFFSET R/W 0x000.00 0 The vector table is in the code memory region. 1 The vector table is in the SRAM memory region. Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 43 interrupts, the offset must be aligned on a 256-byte boundary. 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 125 Texas Instruments-Production Data Cortex-M3 Peripherals Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table 3-8 on page 126 shows how the PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table 3-8. Interrupt Priority Levels a PRIGROUP Bit Field Binary Point Group Priority Field Subpriority Field Group Priorities Subpriorities 0x0 - 0x4 bxxx. [7:5] None 8 1 0x5 bxx.y [7:6] [5] 4 2 0x6 bx.yy [7] [6:5] 2 4 0x7 b.yyy None [7:5] 1 8 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type R/W, reset 0xFA05.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 5 4 3 2 1 0 VECTKEY Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 15 14 13 12 11 10 reserved ENDIANESS Type Reset RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 9 8 7 6 PRIGROUP RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 VECTKEY R/W 0xFA05 reserved R/W 0 RO 0 RO 0 RO 0 SYSRESREQ VECTCLRACT VECTRESET RO 0 RO 0 WO 0 WO 0 WO 0 Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 15 ENDIANESS RO 0 Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared to 0. 14:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 126 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 10:8 PRIGROUP R/W 0x0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 126 for more information). 7:3 reserved RO 0x0 2 SYSRESREQ WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Reset Request Value Description 0 No effect. 1 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. 1 VECTCLRACT WO 0 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0 VECTRESET WO 0 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. June 18, 2012 127 Texas Instruments-Production Data Cortex-M3 Peripherals Register 30: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4 SEVONPEND R/W 0 RO 0 RO 0 RO 0 RO 0 4 3 SEVONPEND reserved R/W 0 RO 0 SLEEPDEEP SLEEPEXIT R/W 0 R/W 0 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Wake Up on Pending Value Description 0 Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SLEEPDEEP R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. 128 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1 SLEEPEXIT R/W 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 129 Texas Instruments-Production Data Cortex-M3 Peripherals Register 31: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 120). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 reserved STKALIGN BFHFNMIGN RO 0 RO 0 R/W 0 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.00 9 STKALIGN R/W 0 R/W 0 RO 0 RO 0 RO 0 4 3 2 1 0 DIV0 UNALIGNED reserved MAINPEND BASETHR R/W 0 R/W 0 RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Stack Alignment on Exception Entry Value Description 0 The stack is 4-byte aligned. 1 The stack is 8-byte aligned. On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 8 BFHFNMIGN R/W 0 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Value Description 0 Data bus faults caused by load and store instructions cause a lock-up. 1 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 130 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 4 DIV0 R/W 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 3 UNALIGNED R/W 0 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses. 1 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 MAINPEND R/W 0 Allow Main Interrupt Trigger Value Description 0 BASETHR R/W 0 0 Disables unprivileged software access to the SWTRIG register. 1 Enables unprivileged software access to the SWTRIG register (see page 120). Thread State Control Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see "Exception Return" on page 86 for more information). June 18, 2012 131 Texas Instruments-Production Data Cortex-M3 Peripherals Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 reserved Type Reset RO 0 15 RO 0 RO 0 RO 0 RO 0 14 13 12 11 BUS Type Reset R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 10 9 8 7 reserved R/W 0 RO 0 22 21 20 19 USAGE RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 MEM RO 0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 USAGE R/W 0x0 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 BUS R/W 0x0 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 MEM R/W 0x0 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 132 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 SVC Type Reset 22 21 20 19 18 17 16 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 SVC R/W 0x0 RO 0 Description SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:0 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 133 Texas Instruments-Production Data Cortex-M3 Peripherals Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.0000 31 30 29 28 27 TICK Type Reset 26 25 24 23 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 22 21 20 19 PENDSV R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 DEBUG RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 TICK R/W 0x0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Description SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 PENDSV R/W 0x0 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:8 reserved RO 0x000 7:5 DEBUG R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 134 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution - Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 SVC BUSP MEMP USAGEP R/W 0 R/W 0 R/W 0 R/W 0 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 USAGE BUS MEM R/W 0 R/W 0 R/W 0 10 9 8 7 6 5 4 3 2 1 0 TICK PNDSV reserved MON SVCA R/W 0 R/W 0 RO 0 R/W 0 R/W 0 USGA reserved BUSA MEMA R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset Type Reset reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 USAGE R/W 0 Usage Fault Enable Value Description 17 BUS R/W 0 0 Disables the usage fault exception. 1 Enables the usage fault exception. Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. June 18, 2012 135 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 16 MEM R/W 0 Description Memory Management Fault Enable Value Description 15 SVC R/W 0 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception. 14 BUSP R/W 0 Bus Fault Pending Value Description 0 A bus fault exception is not pending. 1 A bus fault exception is pending. This bit can be modified to change the pending status of the bus fault exception. 13 MEMP R/W 0 Memory Management Fault Pending Value Description 0 A memory management fault exception is not pending. 1 A memory management fault exception is pending. This bit can be modified to change the pending status of the memory management fault exception. 12 USAGEP R/W 0 Usage Fault Pending Value Description 0 A usage fault exception is not pending. 1 A usage fault exception is pending. This bit can be modified to change the pending status of the usage fault exception. 11 TICK R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active. 1 A SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 136 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 10 PNDSV R/W 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MON R/W 0 Debug Monitor Active Value Description 7 SVCA R/W 0 0 The Debug monitor is not active. 1 The Debug monitor is active. SVC Call Active Value Description 0 SVC call is not active. 1 SVC call is active. This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 6:4 reserved RO 0x0 3 USGA R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Usage Fault Active Value Description 0 Usage fault is not active. 1 Usage fault is active. This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BUSA R/W 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. June 18, 2012 137 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 0 MEMA R/W 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 138 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: Usage Fault Status (UFAULTSTAT), bits 31:16 Bus Fault Status (BFAULTSTAT), bits 15:8 Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: The complete FAULTSTAT register, with a word access to offset 0xD28 The MFAULTSTAT, with a byte access to offset 0xD28 The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 The BFAULTSTAT, with a byte access to offset 0xD29 The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 reserved Type Reset RO 0 RO 0 RO 0 15 14 13 BFARV Type Reset R/W1C 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 25 24 DIV0 UNALIGN R/W1C 0 R/W1C 0 23 22 21 20 reserved RO 0 RO 0 RO 0 6 5 12 11 10 9 8 7 BSTKE BUSTKE IMPRE PRECISE IBUS MMARV R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved RO 0 RO 0 RO 0 19 18 17 16 NOCP INVPC INVSTAT UNDEF R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 4 3 2 1 0 MSTKE MUSTKE reserved DERR IERR R/W1C 0 R/W1C 0 RO 0 R/W1C 0 R/W1C 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 139 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 25 DIV0 R/W1C 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see page 130). This bit is cleared by writing a 1 to it. 24 UNALIGN R/W1C 0 Unaligned Access Usage Fault Value Description 0 No unaligned access fault has occurred, or unaligned access trapping is not enabled. 1 The processor has made an unaligned memory access. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see page 130). This bit is cleared by writing a 1 to it. 23:20 reserved RO 0x00 19 NOCP R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. No Coprocessor Usage Fault Value Description 0 A usage fault has not been caused by attempting to access a coprocessor. 1 The processor has attempted to access a coprocessor. This bit is cleared by writing a 1 to it. 18 INVPC R/W1C 0 Invalid PC Load Usage Fault Value Description 0 A usage fault has not been caused by attempting to load an invalid PC value. 1 The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. 140 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 17 INVSTAT R/W1C 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register. When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. 16 UNDEF R/W1C 0 Undefined Instruction Usage Fault Value Description 0 A usage fault has not been caused by an undefined instruction. 1 The processor has attempted to execute an undefined instruction. When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 15 BFARV R/W1C 0 Bus Fault Address Register Valid Value Description 0 The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 1 The FAULTADDR register is holding a valid fault address. This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 14:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 141 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 12 BSTKE R/W1C 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 11 BUSTKE R/W1C 0 Unstack Bus Fault Value Description 0 No bus fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 10 IMPRE R/W1C 0 Imprecise Data Bus Error Value Description 0 An imprecise data bus error has not occurred. 1 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 9 PRECISE R/W1C 0 Precise Data Bus Error Value Description 0 A precise data bus error has not occurred. 1 A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 142 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 8 IBUS R/W1C 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 7 MMARV R/W1C 0 Memory Management Fault Address Register Valid Value Description 0 The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 1 The MMADDR register is holding a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 MSTKE R/W1C 0 Stack Access Violation Value Description 0 No memory management fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more access violations. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. June 18, 2012 143 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 3 MUSTKE R/W1C 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 DERR R/W1C 0 Data Access Violation Value Description 0 A data access violation has not occurred. 1 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. 0 IERR R/W1C 0 Instruction Access Violation Value Description 0 An instruction access violation has not occurred. 1 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 144 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.0000 Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG FORCED R/W1C 0 R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECT reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset Bit/Field Name Type Reset 31 DBG R/W1C 0 Description Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 30 FORCED R/W1C 0 Forced Hard Fault Value Description 0 No forced hard fault has occurred. 1 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 29:2 reserved RO 0x00 1 VECT R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Read Fault Value Description 0 No bus fault has occurred on a vector table read. 1 A bus fault occurred on a vector table read. This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 145 Texas Instruments-Production Data Cortex-M3 Peripherals Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether the value in the MMADDR register is valid (see page 139). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. 146 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid (see page 139). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 3.6 Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. June 18, 2012 147 Texas Instruments-Production Data Cortex-M3 Peripherals Register 40: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 DREGION Type Reset RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 IREGION RO 0 RO 0 RO 0 RO 0 4 3 2 1 reserved RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 0 SEPARATE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 IREGION RO 0x00 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by the DREGION field. 15:8 DREGION RO 0x08 Number of D Regions Value Description 0x08 Indicates there are eight supported MPU data regions. 7:1 reserved RO 0x00 0 SEPARATE RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Separate or Unified MPU Value Description 0 Indicates the MPU is unified. 148 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 41: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers. When the ENABLE and PRIVDEFEN bits are both set: For privileged accesses, the default memory map is as described in "Memory Model" on page 70. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When the ENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 72 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority -1 or -2. These priorities are only possible when handling a hard fault or NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 PRIVDEFEN HFNMIENA R/W 0 R/W 0 ENABLE R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 149 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 2 PRIVDEFEN R/W 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 1 HFNMIENA R/W 0 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASK handlers. Value Description 0 The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 0 ENABLE R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. 150 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register with the VALID bit set (see page 152). This write updates the value of the REGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 NUMBER R/W 0x0 NUMBER RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. June 18, 2012 151 Texas Instruments-Production Data Cortex-M3 Peripherals Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set. The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALID reserved WO 0 RO 0 ADDR Type Reset ADDR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:5 ADDR R/W 0x0000.000 R/W 0 R/W 0 R/W 0 R/W 0 REGION R/W 0 R/W 0 R/W 0 Description Base Address Mask Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 152 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 4 VALID WO 0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. This bit is always read as 0. 3 reserved RO 0 2:0 REGION R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. June 18, 2012 153 Texas Instruments-Production Data Cortex-M3 Peripherals Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions. The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 3-9 on page 154 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register. Table 3-9. Example SIZE Field Values a SIZE Encoding Region Size Value of N Note 00100b (0x4) 32 B 5 Minimum permitted size 01001b (0x9) 1 KB 10 - 10011b (0x13) 1 MB 20 - 11101b (0x1D) 1 GB 30 - 11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size region occupies the complete memory map. a. Refers to the N parameter in the MPUBASE register (see page 152). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type R/W, reset 0x0000.0000 31 30 29 28 27 reserved Type Reset 26 25 24 23 AP 21 reserved 20 19 18 TEX 17 16 XN reserved S C B RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 SRD Type Reset 22 reserved SIZE 154 R/W 0 ENABLE R/W 0 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 XN R/W 0 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26:24 AP R/W 0 Access Privilege For information on using this bit field, see Table 3-5 on page 100. 23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21:19 TEX R/W 0x0 Type Extension Mask For information on using this bit field, see Table 3-3 on page 99. 18 S R/W 0 Shareable For information on using this bit, see Table 3-3 on page 99. 17 C R/W 0 Cacheable For information on using this bit, see Table 3-3 on page 99. 16 B R/W 0 Bufferable For information on using this bit, see Table 3-3 on page 99. 15:8 SRD R/W 0x00 Subregion Disable Bits Value Description 0 The corresponding subregion is enabled. 1 The corresponding subregion is disabled. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See the section called "Subregions" on page 98 for more information. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:1 SIZE R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 154 for more information. June 18, 2012 155 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 0 ENABLE R/W 0 Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled. 156 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. (R) The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. The Stellaris JTAG module has the following features: IEEE 1149.1-1990 compatible Test Access Port (TAP) controller Four-bit Instruction Register (IR) chain for storing JTAG instructions IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ARM additional instructions: APACC, DPACC and ABORT Integrated ARM Serial Wire Debug (SWD) See the ARM(R) Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. June 18, 2012 157 Texas Instruments-Production Data JTAG Interface 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TRST TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M3 Debug Port 4.2 Signal Description Table 4-1 on page 158 and Table 4-2 on page 159 list the external signals of the JTAG/SWD controller and describe the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see "Commit Control" on page 292. The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) is set to choose the JTAG/SWD function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 4-1. JTAG_SWD_SWO Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type SWCLK 80 I TTL Description JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I/O TTL JTAG TMS and SWDIO. TRST 89 I TTL JTAG TRST. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 158 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 4-2. JTAG_SWD_SWO Signals (108BGA) Pin Name Pin Number SWCLK SWDIO a Pin Type Buffer Type Description A9 I TTL JTAG/SWD CLK. B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I/O TTL JTAG TMS and SWDIO. TRST A8 I TTL JTAG TRST. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 4.3 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 158. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 4-4 on page 166 for a list of implemented instructions). See "JTAG and Boundary Scan" on page 666 for JTAG timing diagrams. 4.3.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 4-3 on page 159. Detailed information on each pin follows. Table 4-3. JTAG Port Pins Reset State Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TRST Input Enabled Disabled N/A N/A TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z June 18, 2012 159 Texas Instruments-Production Data JTAG Interface 4.3.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 4.3.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 4.3.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 162. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 4.3.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 160 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 4.3.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 4.3.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 4-2 on page 162. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. June 18, 2012 161 Texas Instruments-Production Data JTAG Interface Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 4.3.3 1 0 Pause DR 1 0 1 0 0 1 0 0 Update IR 1 0 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller's CAPTURE states and allows this information to be shifted out of TDO during the TAP controller's SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE states. Each of the shift registers is discussed in detail in "Register Descriptions" on page 165. 4.3.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 162 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 4.3.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution - It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 306) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 316) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 317) have been set to 1. Recovering a "Locked" Device Note: The mass erase of the flash memory caused by the below sequence erases the entire flash memory, regardless of the settings in the Flash Memory Protection Program Enable n (FMPPEn) registers. Performing the sequence below does not affect the nonvolatile registers discussed in "Nonvolatile Register Programming" on page 261. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Apply power to the device. 3. Perform the JTAG-to-SWD switch sequence. 4. Perform the SWD-to-JTAG switch sequence. 5. Perform the JTAG-to-SWD switch sequence. 6. Perform the SWD-to-JTAG switch sequence. 7. Perform the JTAG-to-SWD switch sequence. 8. Perform the SWD-to-JTAG switch sequence. 9. Perform the JTAG-to-SWD switch sequence. 10. Perform the SWD-to-JTAG switch sequence. June 18, 2012 163 Texas Instruments-Production Data JTAG Interface 11. Perform the JTAG-to-SWD switch sequence. 12. Perform the SWD-to-JTAG switch sequence. 13. Release the RST signal. 14. Wait 400 ms. 15. Power-cycle the device. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in "ARM Serial Wire Debug (SWD)" on page 164. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence in the section called "JTAG-to-SWD Switching" on page 164 must be performed. 4.3.4.2 Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. 4.3.4.3 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM(R) Debug Interface V5 Architecture Specification. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 164 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 4.4 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG pins (PB7 andPC[3:0]) should be reverted to their default settings. 4.5 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 4.5.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 4-4 on page 166. A detailed explanation of each instruction, along with its associated Data Register, follows. June 18, 2012 165 Texas Instruments-Production Data JTAG Interface Table 4-4. JTAG Instruction Register Commands 4.5.1.1 IR[3:0] Instruction Description 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0001 INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0010 SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. 1110 IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.2 INTEST Instruction The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. 166 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see "Boundary Scan Data Register" on page 168 for more information. 4.5.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the "ABORT Data Register" on page 169 for more information. 4.5.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see "DPACC Data Register" on page 169 for more information. 4.5.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see "APACC Data Register" on page 169 for more information. 4.5.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see "IDCODE Data Register" on page 168 for more information. 4.5.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see "BYPASS Data Register" on page 168 for more information. June 18, 2012 167 Texas Instruments-Production Data JTAG Interface 4.5.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 4.5.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3 on page 168. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 4-3. IDCODE Register Format 31 TDI 4.5.2.2 28 27 12 11 Version Part Number 1 0 Manufacturer ID 1 TDO BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-4 on page 168. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. Figure 4-4. BYPASS Register Format 0 TDI 4.5.2.3 0 TDO Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 169. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with 168 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 4-5. Boundary Scan Register Format TDI I N O U T O E ... GPIO PB6 4.5.2.4 I N O U T GPIO m O E I N RST I N O U T GPIO m+1 O E ... I N O U T O TDO E GPIO n APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM(R) Debug Interface V5 Architecture Specification. 4.5.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM(R) Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM(R) Debug Interface V5 Architecture Specification. June 18, 2012 169 Texas Instruments-Production Data System Control 5 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 5.1 Signal Description Table 5-1 on page 170 and Table 5-2 on page 170 list the external signals of the System Control module and describe the function of each. The NMI signal is the alternate function for and functions as a GPIO after reset. under commit protection and require a special process to be configured as any alternate function or to subsequently return to the GPIO function, see "Commit Control" on page 292. The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the NMI function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. The remaining signals (with the word "fixed" in the Pin Assignment column) have a fixed pin assignment and function. Table 5-1. System Control & Clocks Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 48 I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 5-2. System Control & Clocks Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type CMOD0 E11 I TTL Description CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST H11 I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 5.2 Functional Description The System Control module provides the following capabilities: Device identification (see "Device Identification" on page 171) 170 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Local control, such as reset (see "Reset Control" on page 171), power (see "Power Control" on page 175) and clock control (see "Clock Control" on page 176) System control (Run, Sleep, and Deep-Sleep modes); see "System Control" on page 181 5.2.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 5.2.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 5.2.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion; see "External RST Pin" on page 172. 2. Power-on reset (POR); see "Power-On Reset (POR)" on page 172. 3. Internal brown-out (BOR) detector; see "Brown-Out Reset (BOR)" on page 173. 4. Software-initiated reset (with the software reset registers); see "Software Reset" on page 174. 5. A watchdog timer reset condition violation; see "Watchdog Timer Reset" on page 174. Table 5-3 provides a summary of results of the various reset operations. Table 5-3. Reset Sources Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset? Power-On Reset Yes Yes Yes RST Yes Pin Config Only Yes Brown-Out Reset Yes No Yes Software System Request a Reset Yes No Yes Software Peripheral Reset No No Yes Watchdog Reset Yes No Yes b a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register b. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. June 18, 2012 171 Texas Instruments-Production Data System Control 5.2.2.3 Power-On Reset (POR) Note: The power-on reset also resets the JTAG controller. An external reset does not. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in "External RST Pin" on page 172. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 21-6 on page 669. 5.2.2.4 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K ) as shown in Figure 5-1 on page 172. Figure 5-1. Basic RST Configuration VDD Stellaris(R) RPU RST RPU = 0 to 100 k The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see "JTAG Interface" on page 157). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see "Reset" on page 668). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. 172 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 173. Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris(R) RPU RST C1 RPU = 1 k to 100 k C1 = 1 nF to 10 F If the application requires the use of an external reset switch, Figure 5-3 on page 173 shows the proper circuitry to use. Figure 5-3. Reset Circuit Controlled by Switch VDD Stellaris(R) RPU RST C1 RS Typical RPU = 10 k Typical RS = 470 C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 21-5 on page 668. 5.2.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. June 18, 2012 173 Texas Instruments-Production Data System Control The brown-out reset is equivalent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 21-7 on page 669. 5.2.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see "System Control" on page 181). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 21-8 on page 669. 5.2.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The watchdog reset timing is shown in Figure 21-9 on page 669. 174 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 5.2.3 Power Control (R) The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)--or 2.5 V 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Figure 5-4 on page 176 shows the power architecture. Note: On the printed circuit board, use the LDO output as the source of VDD25 input. Do not use an external regulator to supply the voltage to VDD25. In addition, the LDO requires decoupling capacitors. See "On-Chip Low Drop-Out (LDO) Regulator Characteristics" on page 662. VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the LDO and the clock circuitry. June 18, 2012 175 Texas Instruments-Production Data System Control Figure 5-4. Power Architecture VDD VCCPHY GNDPHY VCCPHY Ethernet PHY VCCPHY VCCPHY VDD25 GNDPHY GNDPHY VDD25 VDD25 GNDPHY GND Internal Logic and PLL VDD25 GND GND GND LDO Low-noise LDO +3.3V VDDA VDDA GNDA Analog circuits VDD GND VDD GND VDD I/O Buffers VDD 5.2.4 GNDA GND GND Clock Control System control determines the control of clocks in this part. 5.2.4.1 Fundamental Clock Sources There are multiple clock sources for use in the device: Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz 30%. 176 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit field in the RCC register (see page 193). Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. External Real-Time Oscillator. The external real-time oscillator provides a low-frequency, accurate clock reference. It is intended to provide the system with a real-time clock source. The real-time oscillator is part of the Hibernation Module (see "Hibernation Module" on page 237) and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL, and the internal oscillator divided by four (3 MHz 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). Table 5-4 on page 177 shows how the various clock sources can be used in a system. Table 5-4. Clock Source Options 5.2.4.2 Clock Source Drive PLL? Used as SysClk? Internal Oscillator (12 MHz) No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x1 Internal Oscillator divide by 4 (3 MHz) No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x2 Main Oscillator Yes BYPASS = 0, OSCSRC = Yes 0x0 BYPASS = 1, OSCSRC = 0x0 Internal 30-kHz Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x3 External Real-Time Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC2 = 0x7 Clock Configuration The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality: Source of clocks in sleep and deep-sleep modes System clock derived from PLL or other clock source Enabling/disabling of oscillators and PLL June 18, 2012 177 Texas Instruments-Production Data System Control Clock divisors Crystal input selection Figure 5-5 on page 178 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV in RCC). Figure 5-5. Main Clock Tree USEPWMDIV a PWMDW a PWM Clock XTALa PWRDN b MOSCDIS a PLL (400 MHz) Main OSC USESYSDIV a,d /2 IOSCDIS a System Clock Internal OSC (12 MHz) SYSDIV b,d /4 BYPASS Internal OSC (30 kHz) Hibernation Module (32.768 kHz) b,d OSCSRC b,d PWRDN ADC Clock / 25 / 50 CAN Clock a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. Note: The figure above shows all features available on all Stellaris(R) Fury-class devices. Not all peripherals may be available on this device. In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register 178 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-4 on page 177. Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field SYSDIV Divisor a Frequency (BYPASS=0) Frequency (BYPASS=1) StellarisWare Parameter b 0x0 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x2 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3 0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11 0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12 0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13 0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14 0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15 0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-4 on page 177. Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field SYSDIV2 Divisor a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter b 0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x02 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3 0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x05 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x06 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 June 18, 2012 179 Texas Instruments-Production Data System Control Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) Frequency (BYPASS2=1) StellarisWare Parameter /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x08 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 ... ... ... ... ... 0x3F /64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64 0x07 Divisor a Frequency (BYPASS2=0) SYSDIV2 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. 5.2.4.3 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 193) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 5.2.4.4 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency, and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 197). The internal translation provides a translation within 1% of the targeted PLL VCO frequency. Table 21-10 on page 665 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 193) describes the available crystal choices and default programming of the PLLCFG register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7. 5.2.4.5 PLL Modes The PLL has two modes of operation: Normal and Power-Down Normal: The PLL multiplies the input clock reference and drives the output. Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 193 and page 198). 180 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 5.2.4.6 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 21-9 on page 665). During the relock time, the affected PLL is not usable as a clock reference. PLL is changed by one of the following: Change to the XTAL value in the RCC register--writes of the same value do not cause a relock. Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 s at an 8.192 MHz external oscillator clock). Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. 5.2.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. There are four levels of operation for the device defined as: Run Mode. In Run mode, the controller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See "Power Management" on page 88 for more details. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See "Power Management" on page 88 for more details. June 18, 2012 181 Texas Instruments-Production Data System Control The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. It can determine that it has been restarted from Hibernate mode by inspecting the Hibernation module registers. Caution - If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 5.3 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a "raw" clock source and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 182 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 5.4 Register Map Table 5-7 on page 183 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 5-7. System Control Register Map Description See page Offset Name Type Reset 0x000 DID0 RO - Device Identification 0 185 0x004 DID1 RO - Device Identification 1 201 0x008 DC0 RO 0x00FF.007F Device Capabilities 0 203 0x010 DC1 RO 0x0010.30DF Device Capabilities 1 204 0x014 DC2 RO 0x070F.1137 Device Capabilities 2 206 0x018 DC3 RO 0xBF00.FFFF Device Capabilities 3 208 0x01C DC4 RO 0x5100.007F Device Capabilities 4 210 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 187 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 188 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 233 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 234 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 236 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 189 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 190 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 191 0x05C RESC R/W - Reset Cause 192 0x060 RCC R/W 0x078E.3AD1 Run-Mode Clock Configuration 193 0x064 PLLCFG RO - XTAL to PLL Translation 197 0x070 RCC2 R/W 0x0780.2810 Run-Mode Clock Configuration 2 198 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 212 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 218 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 227 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 214 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 221 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 229 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 216 June 18, 2012 183 Texas Instruments-Production Data System Control Table 5-7. System Control Register Map (continued) See page Offset Name Type Reset 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 224 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 231 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 200 5.5 Description Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. 184 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 30 28 27 26 VER reserved Type Reset 29 25 24 23 22 21 20 reserved 18 17 16 CLASS RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - MAJOR Type Reset 19 MINOR Bit/Field Name Type Reset 31 reserved RO 0 30:28 VER RO 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 Second version of the DID0 register format. 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 CLASS RO 0x1 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris(R) Fury-class devices. June 18, 2012 185 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 7:0 MINOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. 186 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORIOR reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 BORIOR R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 187 Texas Instruments-Production Data System Control Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 VADJ Bit/Field Name Type Reset 31:6 reserved RO 0 5:0 VADJ R/W 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 188 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORRIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PLLLRIS RO 0 RO 0 reserved Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 189 Texas Instruments-Production Data System Control Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORIM reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset PLLLIM RO 0 R/W 0 reserved Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLIM R/W 0 PLL Lock Interrupt Mask This bit specifies whether a PLL Lock interrupt is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORIM R/W 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 190 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 189). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORMIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset reserved Type Reset PLLLMIS RO 0 R/W1C 0 reserved Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORMIS R/W1C 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 191 Texas Instruments-Production Data System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SW WDT BOR POR EXT RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SW R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 3 WDT R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 2 BOR R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 1 POR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 0 EXT R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. 192 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x078E.3AD1 31 30 29 28 26 25 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 15 14 13 12 11 10 PWRDN reserved BYPASS reserved R/W 1 RO 1 R/W 1 RO 0 reserved Type Reset reserved Type Reset RO 0 RO 0 27 24 23 R/W 1 R/W 1 R/W 1 9 8 R/W 1 R/W 0 ACG 22 21 20 USESYSDIV reserved USEPWMDIV R/W 0 RO 0 R/W 0 R/W 1 R/W 1 R/W 1 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 0 R/W 1 RO 0 SYSDIV XTAL Bit/Field Name Type Reset 31:28 reserved RO 0x0 27 ACG R/W 0 OSCSRC 19 18 17 PWMDIV reserved RO 0 16 reserved IOSCDIS MOSCDIS R/W 0 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 26:23 SYSDIV R/W 0xF System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). See Table 5-5 on page 179 for bit encodings. If the SYSDIV value is less than MINSYSDIV (see page 204), and the PLL is being used, then the MINSYSDIV value is used as the divisor. If the PLL is not being used, the SYSDIV value can be less than MINSYSDIV. 22 USESYSDIV R/W 0 Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field in the RCC2 register is used as the system clock divider rather than the SYSDIV field in this register. June 18, 2012 193 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 USEPWMDIV R/W 0 Enable PWM Clock Divisor Use the PWM clock divider as the source for the PWM clock. 19:17 PWMDIV R/W 0x7 PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. This clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. Value Divisor 0x0 /2 0x1 /4 0x2 /8 0x3 /16 0x4 /32 0x5 /64 0x6 /64 0x7 /64 (default) 16:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 PWRDN R/W 1 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS R/W 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. See Table 5-5 on page 179 for programming guidelines. 10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 194 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 9:6 XTAL R/W 0xB Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz (see Table 21-10 on page 665 for more information). Value Crystal Frequency (MHz) Not Using the PLL 5:4 OSCSRC R/W 0x1 Crystal Frequency (MHz) Using the PLL 0x0 1.000 reserved 0x1 1.8432 reserved 0x2 2.000 reserved 0x3 2.4576 reserved 0x4 3.579545 MHz 0x5 3.6864 MHz 0x6 4 MHz 0x7 4.096 MHz 0x8 4.9152 MHz 0x9 5 MHz 0xA 5.12 MHz 0xB 6 MHz (reset value) 0xC 6.144 MHz 0xD 7.3728 MHz 0xE 8 MHz 0xF 8.192 MHz Oscillator Source Selects the input source for the OSC. The values are: Value Input Source 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator (default) 0x2 IOSC/4 Internal oscillator / 4 0x3 30 kHz 30-KHz internal oscillator For additional oscillator sources, see the RCC2 register. 3:2 reserved RO 0x0 1 IOSCDIS R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. June 18, 2012 195 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 0 MOSCDIS R/W 1 Description Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). 196 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 193). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO - RO - RO - RO - RO - 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - reserved Type Reset reserved Type Reset RO 0 RO 0 F Bit/Field Name Type Reset 31:14 reserved RO 0x0 13:5 F RO - R Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL's F input. 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL's R input. June 18, 2012 197 Texas Instruments-Production Data System Control Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-8, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. Table 5-8. RCC2 Fields that Override RCC fields RCC2 Field... Overrides RCC Field SYSDIV2, bits[28:23] SYSDIV, bits[26:23] PWRDN2, bit[13] PWRDN, bit[13] BYPASS2, bit[11] BYPASS, bit[11] OSCSRC2, bits[6:4] OSCSRC, bits[5:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2810 31 30 USERCC2 Type Reset R/W 0 RO 0 15 14 reserved Type Reset RO 0 29 28 27 26 reserved RO 0 25 24 23 22 21 20 SYSDIV2 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 10 9 8 7 6 13 12 11 PWRDN2 reserved BYPASS2 R/W 1 RO 0 R/W 1 reserved RO 0 19 18 17 16 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO 0 RO 0 OSCSRC2 RO 0 RO 0 Bit/Field Name Type Reset Description 31 USERCC2 R/W 0 Use RCC2 R/W 0 R/W 0 reserved R/W 1 RO 0 RO 0 When set, overrides the RCC register fields. 30:29 reserved RO 0x0 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-6 on page 179 for programming guidelines. 22:14 reserved RO 0x0 13 PWRDN2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down PLL When set, powers down the PLL. 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 198 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 11 BYPASS2 R/W 1 Bypass PLL When set, bypasses the PLL for the clock source. See Table 5-6 on page 179 for programming guidelines. 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 OSCSRC2 R/W 0x1 Oscillator Source Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator 0x2 IOSC/4 Internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 32 kHz 32.768-kHz external oscillator 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 199 Texas Instruments-Production Data System Control Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 reserved Type Reset 25 24 23 22 21 20 DSDIVORIDE 18 17 16 reserved RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 DSOSCSRC RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28:23 DSDIVORIDE R/W 0x0F R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 22:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 DSOSCSRC R/W 0x0 Clock Source Specifies the clock source during Deep-Sleep mode. Value Description 0x0 MOSC Use main oscillator as source. 0x1 IOSC Use internal 12-MHz oscillator as source. 0x2 Reserved 0x3 30 kHz Use 30-kHz internal oscillator as source. 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 32 kHz Use 32.768-kHz external oscillator as source. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 200 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 29 28 27 26 RO 0 15 25 24 23 22 21 20 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 14 13 12 11 10 9 8 7 6 5 4 RO 0 RO 0 RO 0 RO 0 RO 0 RO - RO - RO - VER Type Reset FAM PINCOUNT Type Reset RO 0 RO 1 18 17 16 RO 0 RO 0 RO 1 RO 0 3 2 1 0 PARTNO reserved RO 0 19 TEMP Bit/Field Name Type Reset 31:28 VER RO 0x1 RO - PKG ROHS RO - RO 1 QUAL RO - RO - Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 27:24 FAM RO 0x0 Second version of the DID1 register format. Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 23:16 PARTNO RO 0x72 Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x72 LM3S6950 15:13 PINCOUNT RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin or 108-ball package June 18, 2012 201 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 TEMP RO - Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 4:3 PKG RO - 0x0 Commercial temperature range (0C to 70C) 0x1 Industrial temperature range (-40C to 85C) 0x2 Extended temperature range (-40C to 105C) Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 2 ROHS RO 1 0x0 SOIC package 0x1 LQFP package 0x2 BGA package RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 202 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.007F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 SRAMSZ Type Reset FLASHSZ Type Reset RO 0 Bit/Field Name Type Reset Description 31:16 SRAMSZ RO 0x00FF SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 15:0 FLASHSZ RO 0x007F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x007F 256 KB of Flash June 18, 2012 203 Texas Instruments-Production Data System Control Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0010.30DF 31 30 29 28 27 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 1 26 25 24 23 22 21 19 18 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 6 5 4 3 2 1 0 MPU RO 0 RO 0 RO 0 RO 0 RO 1 HIB reserved PLL WDT SWO SWD JTAG RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset MINSYSDIV Type Reset PWM reserved RO 1 20 17 16 reserved Bit/Field Name Type Reset Description 31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM RO 1 PWM Module Present When set, indicates that the PWM module is present. 19:16 reserved RO 0 15:12 MINSYSDIV RO 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 11:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 MPU RO 1 MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter in the Stellaris Data Sheet for details on the MPU. 6 HIB RO 1 Hibernation Module Present When set, indicates that the Hibernation module is present. 204 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 PLL RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 3 WDT RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 2 SWO RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 0 JTAG RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. June 18, 2012 205 Texas Instruments-Production Data System Control Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x070F.1137 31 30 RO 0 RO 0 15 14 29 28 27 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset reserved Type Reset RO 0 RO 0 I2C0 RO 0 RO 1 26 25 24 COMP2 COMP1 COMP0 RO 1 RO 1 10 9 reserved RO 0 RO 0 23 22 RO 1 RO 0 RO 0 RO 0 RO 0 8 7 6 5 QEI0 RO 0 RO 1 21 20 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 RO 1 RO 1 RO 1 RO 1 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 RO 1 RO 1 RO 0 RO 1 RO 1 RO 1 reserved reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26 COMP2 RO 1 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 25 COMP1 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 24 COMP0 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 RO 1 Timer 3 Present When set, indicates that General-Purpose Timer module 3 is present. 18 TIMER2 RO 1 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 17 TIMER1 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 16 TIMER0 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 206 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 12 I2C0 RO 1 Description I2C Module 0 Present When set, indicates that I2C module 0 is present. 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 QEI0 RO 1 QEI0 Present When set, indicates that QEI module 0 is present. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 RO 1 SSI1 Present When set, indicates that SSI module 1 is present. 4 SSI0 RO 1 SSI0 Present When set, indicates that SSI module 0 is present. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 RO 1 UART2 Present When set, indicates that UART module 2 is present. 1 UART1 RO 1 UART1 Present When set, indicates that UART module 1 is present. 0 UART0 RO 1 UART0 Present When set, indicates that UART module 0 is present. June 18, 2012 207 Texas Instruments-Production Data System Control Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBF00.FFFF Type Reset Type Reset 31 30 29 28 27 26 25 24 32KHZ reserved CCP5 CCP4 CCP3 CCP2 CCP1 CCP0 RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 PWMFAULT C2O RO 1 RO 1 C2PLUS C2MINUS RO 1 RO 1 C1O C1PLUS C1MINUS RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 32KHZ RO 1 23 22 21 20 RO 1 RO 0 RO 0 RO 0 RO 0 8 7 6 5 C0O RO 1 19 18 17 16 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved C0PLUS C0MINUS RO 1 RO 1 Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 30 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 CCP5 RO 1 CCP5 Pin Present When set, indicates that Capture/Compare/PWM pin 5 is present. 28 CCP4 RO 1 CCP4 Pin Present When set, indicates that Capture/Compare/PWM pin 4 is present. 27 CCP3 RO 1 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 26 CCP2 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 23:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 PWMFAULT RO 1 PWM Fault Pin Present When set, indicates that the PWM Fault pin is present. 14 C2O RO 1 C2o Pin Present When set, indicates that the analog comparator 2 output pin is present. 208 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 13 C2PLUS RO 1 Description C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. 12 C2MINUS RO 1 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. 11 C1O RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 10 C1PLUS RO 1 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 9 C1MINUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 8 C0O RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 7 C0PLUS RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 6 C0MINUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 5 PWM5 RO 1 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 4 PWM4 RO 1 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 3 PWM3 RO 1 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 2 PWM2 RO 1 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 1 PWM1 RO 1 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 0 PWM0 RO 1 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. June 18, 2012 209 Texas Instruments-Production Data System Control Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5100.007F Type Reset 31 30 29 28 27 26 25 reserved EPHY0 reserved EMAC0 RO 0 RO 1 RO 0 RO 1 RO 0 23 22 21 20 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOG RO 0 RO 0 RO 0 RO 1 reserved 24 RO 0 17 16 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved reserved Type Reset 18 E1588 19 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 RO 1 Ethernet PHY0 Present When set, indicates that Ethernet PHY module 0 is present. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 RO 1 Ethernet MAC0 Present When set, indicates that Ethernet MAC module 0 is present. 27:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 E1588 RO 1 1588 Capable When set, indicates that that EMAC0 is 1588-capable. 23:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG RO 1 GPIO Port G Present When set, indicates that GPIO Port G is present. 5 GPIOF RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 4 GPIOE RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 210 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 3 GPIOD RO 1 Description GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 1 GPIOB RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. June 18, 2012 211 Texas Instruments-Production Data System Control Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 26 25 24 23 22 21 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 RO 0 RO 0 RO 0 RO 0 R/W 1 reserved Type Reset HIB RO 0 19 18 R/W 0 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 PWM reserved Type Reset 20 reserved RO 0 RO 0 17 16 reserved WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 19:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 212 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 2:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 213 Texas Instruments-Production Data System Control Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 6 5 4 HIB RO 0 RO 0 20 19 18 PWM RO 0 RO 0 RO 0 R/W 1 reserved RO 0 RO 0 17 16 reserved RO 0 RO 0 3 2 WDT R/W 0 RO 0 RO 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 19:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 214 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 2:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 215 Texas Instruments-Production Data System Control Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 6 5 4 HIB RO 0 RO 0 20 19 18 PWM RO 0 RO 0 RO 0 R/W 1 reserved RO 0 RO 0 17 16 reserved RO 0 RO 0 3 2 WDT R/W 0 RO 0 RO 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 19:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 216 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 2:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 217 Texas Instruments-Production Data System Control Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 RO 0 RO 0 15 14 29 28 27 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset reserved Type Reset RO 0 RO 0 I2C0 RO 0 R/W 0 26 25 24 COMP2 COMP1 COMP0 R/W 0 R/W 0 10 9 reserved RO 0 RO 0 23 22 R/W 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 QEI0 RO 0 R/W 0 21 20 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26 COMP2 R/W 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 218 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 19 TIMER3 R/W 0 Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 QEI0 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. June 18, 2012 219 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 220 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 reserved Type Reset RO 0 15 RO 0 RO 0 14 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 12 11 I2C0 RO 0 R/W 0 26 25 24 COMP2 COMP1 COMP0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 10 9 8 7 6 reserved RO 0 RO 0 QEI0 RO 0 R/W 0 23 22 21 20 reserved reserved RO 0 RO 0 RO 0 RO 0 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26 COMP2 R/W 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 221 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 19 TIMER3 R/W 0 Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 QEI0 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 222 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. June 18, 2012 223 Texas Instruments-Production Data System Control Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 reserved Type Reset RO 0 15 RO 0 RO 0 14 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 12 11 I2C0 RO 0 R/W 0 26 25 24 COMP2 COMP1 COMP0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 10 9 8 7 6 reserved RO 0 RO 0 QEI0 RO 0 R/W 0 23 22 21 20 reserved reserved RO 0 RO 0 RO 0 RO 0 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26 COMP2 R/W 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 224 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 19 TIMER3 R/W 0 Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 QEI0 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. June 18, 2012 225 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 226 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 27 26 25 24 23 22 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved reserved Type Reset 21 RO 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. June 18, 2012 227 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 228 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 15 14 13 12 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset 22 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. June 18, 2012 229 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 230 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 15 14 13 12 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset 22 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. June 18, 2012 231 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 232 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 26 25 24 23 22 21 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset HIB RO 0 19 18 R/W 0 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 PWM reserved Type Reset 20 reserved RO 0 RO 0 17 16 reserved WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Reset Control Reset control for PWM module. 19:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 0 HIB Reset Control Reset control for the Hibernation module. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Reset Control Reset control for Watchdog unit. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 233 Texas Instruments-Production Data System Control Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 RO 0 RO 0 15 14 29 28 27 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset reserved Type Reset RO 0 RO 0 I2C0 RO 0 R/W 0 26 25 24 COMP2 COMP1 COMP0 R/W 0 R/W 0 10 9 reserved RO 0 RO 0 23 22 R/W 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 QEI0 RO 0 R/W 0 21 20 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26 COMP2 R/W 0 Analog Comp 2 Reset Control Reset control for analog comparator 2. 25 COMP1 R/W 0 Analog Comp 1 Reset Control Reset control for analog comparator 1. 24 COMP0 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Reset Control Reset control for General-Purpose Timer module 3. 18 TIMER2 R/W 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 17 TIMER1 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 16 TIMER0 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Reset Control Reset control for I2C unit 0. 234 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 QEI0 R/W 0 QEI0 Reset Control Reset control for QEI unit 0. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Reset Control Reset control for SSI unit 1. 4 SSI0 R/W 0 SSI0 Reset Control Reset control for SSI unit 0. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Reset Control Reset control for UART unit 2. 1 UART1 R/W 0 UART1 Reset Control Reset control for UART unit 1. 0 UART0 R/W 0 UART0 Reset Control Reset control for UART unit 0. June 18, 2012 235 Texas Instruments-Production Data System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 27 26 25 24 23 22 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved reserved Type Reset 21 RO 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Reset Control Reset control for Ethernet PHY unit 0. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Reset Control Reset control for Ethernet MAC unit 0. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG R/W 0 Port G Reset Control Reset control for GPIO Port G. 5 GPIOF R/W 0 Port F Reset Control Reset control for GPIO Port F. 4 GPIOE R/W 0 Port E Reset Control Reset control for GPIO Port E. 3 GPIOD R/W 0 Port D Reset Control Reset control for GPIO Port D. 2 GPIOC R/W 0 Port C Reset Control Reset control for GPIO Port C. 1 GPIOB R/W 0 Port B Reset Control Reset control for GPIO Port B. 0 GPIOA R/W 0 Port A Reset Control Reset control for GPIO Port A. 236 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 6 Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: System power control using discrete external regulator Dedicated pin for waking from an external signal Low-battery detection, signaling, and interrupt generation 32-bit real-time clock (RTC) Two 32-bit RTC match registers for timed wake-up and interrupt generation Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal RTC predivider trim for making fine adjustments to the clock rate 64 32-bit words of non-volatile memory Programmable interrupts for RTC match, external wake, and low battery events June 18, 2012 237 Texas Instruments-Production Data Hibernation Module 6.1 Block Diagram Figure 6-1. Hibernation Module Block Diagram HIBCTL.CLK32EN 32.768 kHz XOSC0 Pre-Divider 4.194304 MHz XOSC1 Interrupts HIBIM HIBRIS HIBMIS HIBIC HIBRTCT /128 HIBCTL.CLKSEL Non-Volatile Memory 64 words HIBDATA RTC HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 MATCH0/1 WAKE LOWBAT VDD Low Battery Detect VBAT HIBCTL.LOWBATEN 6.2 Interrupts to CPU Power Sequence Logic HIB HIBCTL.PWRCUT HIBCTL.RTCWEN HIBCTL.EXTWEN HIBCTL.VABORT Signal Description Table 6-1 on page 238 and Table 6-2 on page 239 list the external signals of the Hibernation module and describe the function of each. These signals have dedicated functions and are not alternate functions for any GPIO signals. Table 6-1. Hibernate Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description HIB 51 O OD An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. VBAT 55 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE 50 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 52 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 238 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 6-2. Hibernate Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description HIB M12 O OD An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. VBAT L12 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE M10 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 K11 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 6.3 Functional Description The Hibernation module controls the power to the processor with an enable signal (HIB) that signals an external voltage regulator to turn off. The Hibernation module power source is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. The Hibernation module also has a separate clock source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low, and optionally prevent hibernation when this occurs. When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to be executed. The time from when the WAKE signal is asserted to when code begins execution is equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR). 6.3.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain Hibernation registers, or between a write followed by a read to those same registers. There is no restriction on timing for back-to-back reads from the Hibernation module. The following registers are subject to this timing restriction: Hibernation RTC Counter (HIBRTCC) Hibernation RTC Match 0 (HIBRTCM0) Hibernation RTC Match 1 (HIBRTCM1) Hibernation RTC Load (HIBRTCLD) Hibernation RTC Trim (HIBRTCT) Hibernation Data (HIBDATA) June 18, 2012 239 Texas Instruments-Production Data Hibernation Module 6.3.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature is not used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can be connected to the XOSC0 pin. See Figure 6-2 on page 240 and Figure 6-3 on page 241. Note that these diagrams only show the connection to the Hibernation pins and not to the full system. See "Hibernation Module" on page 670 for specific values. The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a 32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128, resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. Figure 6-2. Clock Source Using Crystal Stellaris Microcontroller Regulator or Switch Input Voltage IN OUT VDD EN XOSC0 X1 RL XOSC1 C1 C2 HIB WAKE RPU Note: Open drain external wake up circuit VBAT GND 3V Battery X1 = Crystal frequency is fXOSC_XTAL. C1,2 = Capacitor value derived from crystal vendor load capacitance specifications. RL = Load resistor is RXOSC_LOAD. RPU = Pull-up resistor (1 M1/2). See "Hibernation Module" on page 670 for specific parameter values. 240 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 6-3. Clock Source Using Dedicated Oscillator Stellaris Microcontroller Regulator or Switch Input Voltage IN OUT VDD EN Clock Source XOSC0 (fEXT_OSC) N.C. XOSC1 HIB WAKE RPU Open drain external wake up circuit Note: 6.3.3 VBAT GND 3V Battery RPU = Pull-up resistor (1 M1/2). Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage drops below VLOWBAT. When this happens, an interrupt can be generated. The module can also be configured so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery voltage is not measured while in Hibernate mode. Important: System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see "Interrupts and Status" on page 243). 6.3.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see "Clock Source" on page 240). The 32.768-kHz clock signal is fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate, and down from 0x7FFF in order to speed up the RTC rate. June 18, 2012 241 Texas Instruments-Production Data Hibernation Module The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see "Interrupts and Status" on page 243). As long as the RTC is enabled and a valid VBAT is present, the RTC continues counting, regardless of whether VDD is present or if the part is in hibernation. 6.3.5 Battery-Backed Memory The Hibernation module contains 64 32-bit words of memory which are retained during hibernation. This memory is powered from the battery or auxiliary power supply during hibernation. The processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. The battery-backed memory can be accessed through the HIBDATA registers. 6.3.6 Power Control Important: The Hibernation Module requires special system implementation considerations when using HIB to control power, as it is intended to power-down all other sections of its host device. All system signals and power supplies that connect to the chip must be driven to 0 VDC or powered down with the same regulator controlled by HIB. See "Hibernation Module" on page 670 for more details. The Hibernation module controls power to the microcontroller through the use of the HIB pin. This pin is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the system. The Hibernation module remains powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake event. Power to the device is restored by deasserting the HIB signal, which causes the external regulator to turn power back on to the chip. 6.3.7 Initiating Hibernate Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power supply as the logic 1 reference. When the Hibernation module wakes, the microcontroller will see a normal power-on reset. Software can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see "Interrupts and Status" on page 243) and by looking for state data in the battery-backed memory (see "Battery-Backed Memory" on page 242). When the HIB signal deasserts, enabling the external regulator, the external regulator must reach the operating voltage within tHIB_TO_VDD. 242 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 6.3.8 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: Assertion of WAKE pin RTC match Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register. 6.4 Initialization and Configuration The Hibernation module can be set in several different configurations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the system, software must allow a delay of tHIB_REG_WRITE after writes to certain registers (see "Register Access Timing" on page 239). The registers that require a delay are listed in a note in "Register Map" on page 244 as well as in each register description. 6.4.1 Initialization The Hibernation module clock source must be enabled first, even if the RTC feature is not used. If a 4.194304-MHz crystal is used, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any other operations with the Hibernation module. If a 32.678-kHz oscillator is used, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input. 2. No delay is necessary. The above is only necessary when the entire system is initialized for the first time. If the processor is powered due to a wake from hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. 6.4.2 RTC Match Functionality (No Hibernation) Use the following steps to implement the RTC match functionality of the Hibernation module: June 18, 2012 243 Texas Instruments-Production Data Hibernation Module 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 6.4.3 RTC Match/Wake-Up from Hibernation Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 6.4.4 External Wake-Up from Hibernation Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 6.4.5 RTC/External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 6.5 Register Map Table 6-3 on page 245 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled before the registers can be programmed (see page 212). There must be a delay of 3 system clocks after the Hibernation module clock is enabled before any Hibernation module registers are accessed. Important: The Hibernation module registers are reset under two conditions: 1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are both cleared. 244 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 2. A cold POR, when both the VDD and VBAT supplies are removed. Any other reset condition is ignored by the Hibernation module. Table 6-3. Hibernation Module Register Map Offset Name 0x000 Reset HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 246 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 247 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 248 0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 249 0x010 HIBCTL R/W 0x8000.0000 Hibernation Control 250 0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 252 0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 253 0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 254 0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 255 0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 256 0x0300x12C HIBDATA R/W - Hibernation Data 257 6.6 Description See page Type Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. June 18, 2012 245 Texas Instruments-Production Data Hibernation Module Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RTCC Type Reset RTCC Type Reset Bit/Field Name Type 31:0 RTCC RO Reset Description 0x0000.0000 RTC Counter A read returns the 32-bit counter value. This register is read-only. To change the value, use the HIBRTCLD register. 246 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCM0 Type Reset RTCM0 Type Reset Bit/Field Name Type 31:0 RTCM0 R/W Reset Description 0xFFFF.FFFF RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. June 18, 2012 247 Texas Instruments-Production Data Hibernation Module Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCM1 Type Reset RTCM1 Type Reset Bit/Field Name Type 31:0 RTCM1 R/W Reset Description 0xFFFF.FFFF RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. 248 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCLD Type Reset RTCLD Type Reset Bit/Field Name Type 31:0 RTCLD R/W Reset Description 0xFFFF.FFFF RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. June 18, 2012 249 Texas Instruments-Production Data Hibernation Module Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x8000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 HIBREQ RTCEN R/W 0 R/W 0 reserved Type Reset reserved Type Reset VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 VABORT R/W 0 Power Cut Abort Enable Value 6 CLK32EN R/W 0 Description 0 Power cut occurs during a low-battery alert. 1 Power cut is aborted. Clocking Enable Value Description 0 Disabled 1 Enabled This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 5 LOWBATEN R/W 0 Low Battery Monitoring Enable Value Description 0 Disabled 1 Enabled When set, low battery voltage detection is enabled (VBAT < VLOWBAT). 4 PINWEN R/W 0 External WAKE Pin Enable Value Description 0 Disabled 1 Enabled When set, an external event on the WAKE pin will re-power the device. 250 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 3 RTCWEN R/W 0 Description RTC Wake-up Enable Value Description 0 Disabled 1 Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. 2 CLKSEL R/W 0 Hibernation Module Clock Select Value 1 HIBREQ R/W 0 Description 0 Use Divide by 128 output. Use this value for a 4.194304-MHz crystal. 1 Use raw output. Use this value for a 32.768-kHz oscillator. Hibernation Request Value Description 0 Disabled 1 Hibernation initiated After a wake-up event, this bit is cleared by hardware. 0 RTCEN R/W 0 RTC Timer Enable Value Description 0 Disabled 1 Enabled June 18, 2012 251 Texas Instruments-Production Data Hibernation Module Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW R/W 0 LOWBAT R/W 0 RTCALT1 R/W 0 RTCALT0 R/W 0 R/W 0 R/W 0 External Wake-Up Interrupt Mask Description 0 Masked 1 Unmasked Low Battery Voltage Interrupt Mask Description 0 Masked 1 Unmasked RTC Alert1 Interrupt Mask Value 0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Value 1 LOWBAT RTCALT1 RTCALT0 Description Value 2 R/W 0 Description 0 Masked 1 Unmasked RTC Alert0 Interrupt Mask Value Description 0 Masked 1 Unmasked 252 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Raw Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 253 Texas Instruments-Production Data Hibernation Module Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Masked Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 254 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW R/W1C 0 LOWBAT RTCALT1 RTCALT0 R/W1C 0 R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Masked Interrupt Clear Reads return an indeterminate value. 2 LOWBAT R/W1C 0 Low Battery Voltage Masked Interrupt Clear Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert1 Masked Interrupt Clear Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 RTC Alert0 Masked Interrupt Clear Reads return an indeterminate value. June 18, 2012 255 Texas Instruments-Production Data Hibernation Module Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF N clock cycles. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset TRIM Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TRIM R/W 0x7FFF RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. The compensation is made by software by adjusting the default value of 0x7FFF up or down. 256 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store state information and does not lose power during a power-cut operation as long as a battery is present. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - RTD Type Reset RTD Type Reset Bit/Field Name Type Reset 31:0 RTD R/W - Description Hibernation Module NV Registers[63:0] June 18, 2012 257 Texas Instruments-Production Data Internal Memory 7 Internal Memory The LM3S6950 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1 on page 258 illustrates the Flash functions. The dashed boxes in the figure indicate registers residing in the System Control module rather than the Flash Control module. Figure 7-1. Flash Block Diagram Flash Control Icode Bus Cortex-M3 System Bus Dcode Bus FMA FMD FMC FCRIS FCIM FCMISC Flash Array Flash Protection Bridge FMPREn FMPPEn Flash Timing USECRL User Registers USER_DBG USER_REG0 USER_REG1 SRAM Array 7.2 Functional Description This section describes the functionality of the SRAM and Flash memories. 7.2.1 SRAM Memory (R) The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 258 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see "Bit-Banding" on page 74. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also "Serial Flash Loader" on page 677 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 7.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 7.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 7-1 on page 259. Table 7-1. Flash Protection Policy Combinations FMPPEn FMPREn 0 0 Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. June 18, 2012 259 Texas Instruments-Production Data Internal Memory Table 7-1. Flash Protection Policy Combinations (continued) FMPPEn FMPREn Protection 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. 0 1 Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 1 1 No protection. The block may be written, erased, executed or read. A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using the Flash Memory Control (FMC) register. Details on programming these bits are discussed in "Nonvolatile Register Programming" on page 261. 7.2.2.3 Interrupts The Flash memory controller can generate interrupts when the following conditions are observed: Programming Interrupt - signals when a program or erase action is complete. Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its corresponding FMPPEn bit. The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 269) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw Interrupt Status (FCRIS) register (see page 268). Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see page 270). 7.3 Flash Memory Initialization and Configuration 7.3.1 Flash Programming The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. 260 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 7.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. 7.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. Prior to being committed, the register contents are unaffected by any reset condition except power-on reset, which returns the register contents to the original value. By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the contents are permanent, and they cannot be restored to their factory default values. With the exception of the USER_DBG register, the settings in these registers can be tested before committing them to Flash memory. For the USER_DBG register, the data to be written is loaded into the FMD register before it is committed. The FMD register is read only and does not allow the USER_DBG operation to be tried before committing it to nonvolatile memory. Important: The Flash memory registers can only have bits changed from 1 to 0 by user programming and can only be committed once. After being committed, these registers cannot be restored to their factory default values. In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. These five registers can only be committed once whereas the Flash memory protection registers may be committed multiple times. Table 7-2 on page 262 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. June 18, 2012 261 Texas Instruments-Production Data Internal Memory Table 7-2. User-Programmable Flash Memory Resident Registers Register to be Committed 7.4 FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0006 FMPRE3 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_REG2 0x8000.0002 USER_REG2 USER_REG3 0x8000.0003 USER_REG3 USER_DBG 0x7510.0000 FMD Register Map Table 7-3 on page 262 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map Offset Name Type Reset See page Description Flash Memory Control Registers (Flash Control Offset) 0x000 FMA R/W 0x0000.0000 Flash Memory Address 264 0x004 FMD R/W 0x0000.0000 Flash Memory Data 265 0x008 FMC R/W 0x0000.0000 Flash Memory Control 266 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 268 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 269 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 270 Flash Memory Protection Registers (System Control Offset) 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 273 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 273 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 274 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 274 0x140 USECRL R/W 0x31 USec Reload 272 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 275 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 276 262 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 7-3. Flash Register Map (continued) Name Type Reset 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 277 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 278 0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 279 0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 280 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 281 0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 282 0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 283 7.5 Description See page Offset Flash Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. June 18, 2012 263 Texas Instruments-Production Data Internal Memory Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 16 OFFSET OFFSET Type Reset Bit/Field Name Type Reset Description 31:18 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 17:0 OFFSET R/W 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see "Nonvolatile Register Programming" on page 261 for details on values for this field). 264 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA R/W 0x0 Data Value Data value for write operation. June 18, 2012 265 Texas Instruments-Production Data Internal Memory Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 264). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 265) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COMT MERASE ERASE WRITE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 WRKEY Type Reset reserved Type Reset Bit/Field Name Type Reset 31:16 WRKEY WO 0x0 Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x0 3 COMT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 s. 2 MERASE R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 266 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1 ERASE R/W 0 Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 0 WRITE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 s. June 18, 2012 267 Texas Instruments-Production Data Internal Memory Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PRIS ARIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC register bits (see page 266). Value Description 1 The programming cycle has completed. 0 The programming cycle has not completed. This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 0 ARIS RO 0 Access Raw Interrupt Status Value Description 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. 0 No access has tried to improperly program or erase the Flash memory. This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. 268 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PMASK AMASK RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. Value Description 0 AMASK R/W 0 1 An interrupt is sent to the interrupt controller when the PRIS bit is set. 0 The PRIS interrupt is suppressed and not sent to the interrupt controller. Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description 1 An interrupt is sent to the interrupt controller when the ARIS bit is set. 0 The ARIS interrupt is suppressed and not sent to the interrupt controller. June 18, 2012 269 Texas Instruments-Production Data Internal Memory Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PMISC R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 PMISC AMISC R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 268). 0 When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see page 268). 0 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. 270 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 7.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. June 18, 2012 271 Texas Instruments-Production Data Internal Memory Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-s tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 USEC RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 USEC R/W 0x31 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. If the maximum system frequency is being used, USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 272 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed or read. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. June 18, 2012 273 Texas Instruments-Production Data Internal Memory Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 PROG_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 274 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, this register cannot be restored to the factory default value. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 31 NW R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 1 0 DBG1 DBG0 R/W 1 R/W 0 Description User Debug Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:2 DATA R/W 0x1FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 1 DBG1 R/W 1 Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. June 18, 2012 275 Texas Instruments-Production Data Internal Memory Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once committed, this register cannot be restored to the factory default value. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 276 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once committed, this register cannot be restored to the factory default value. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. June 18, 2012 277 Texas Instruments-Production Data Internal Memory Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed or read. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 278 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Enables 256 KB of flash. June 18, 2012 279 Texas Instruments-Production Data Internal Memory Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Enables 256 KB of flash. 280 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. June 18, 2012 281 Texas Instruments-Production Data Internal Memory Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Enables 256 KB of flash. 282 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table "Flash Protection Policy Combinations". Value Description 0xFFFFFFFF Enables 256 KB of flash. June 18, 2012 283 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports 1-46 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: 1-46 GPIOs, depending on configuration 5-V-tolerant in input configuration Fast toggle capable of a change every two clock cycles Programmable control for GPIO interrupts - Interrupt generation masking - Edge-triggered on rising, falling, or both - Level-sensitive on High or Low values Bit masking in both read and write operations through address lines Pins configured as digital inputs are Schmitt-triggered. Programmable control for GPIO pad configuration - Weak pull-up or pull-down resistors - 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications - Slew rate control for the 8-mA drive - Open drain enables - Digital input enables 8.1 Signal Description GPIO signals have alternate hardware functions. Table 8-4 on page 287 and Table 8-5 on page 288 list the GPIO pins and the digital alternate functions. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-, C1+, C2-, C2+). These signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. 284 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 8-1. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 1 1 0 0 GPIOPCTL 0x1 PA[5:2] SSI0 1 1 0 0 0x1 PB[3:2] I2C0 1 1 0 0 0x1 PC[3:0] JTAG/SWD 1 1 0 1 0x3 Table 8-2. GPIO Pins and Alternate Functions (100LQFP) IO Pin Number Multiplexed Function PA0 26 U0Rx PA1 27 U0Tx PA2 28 SSI0Clk PA3 29 SSI0Fss PA4 30 SSI0Rx PA5 31 SSI0Tx PA6 34 CCP1 PA7 35 CCP4 PB0 66 PWM2 PB1 67 PWM3 PB2 70 I2C0SCL PB3 71 I2C0SDA PB4 92 C0- PB5 91 C1- Multiplexed Function PB6 90 C0+ PB7 89 TRST PC0 80 TCK SWCLK PC1 79 TMS SWDIO PC2 78 TDI PC3 77 TDO PC4 25 CCP5 PC5 24 C1+ C1o PC6 23 C2+ C2o PC7 22 C2- PD0 10 PWM0 PD1 11 PhA0 PD2 12 U1Rx PD3 13 U1Tx PD4 95 CCP0 PD5 96 CCP2 PD6 99 Fault PD7 100 IDX0 PE0 72 SSI1Clk June 18, 2012 C0o SWO 285 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-2. GPIO Pins and Alternate Functions (100LQFP) (continued) IO Pin Number Multiplexed Function PE1 73 SSI1Fss PE2 74 SSI1Rx PE3 75 SSI1Tx PE4 6 CCP3 PE5 5 PE6 2 PWM4 PE7 1 PWM5 PF0 47 PhB0 PF1 61 PWM1 PF2 60 LED1 PF3 59 LED0 PG0 19 U2Rx PG1 18 U2Tx Multiplexed Function Table 8-3. GPIO Pins and Alternate Functions (108BGA) IO Pin Number Multiplexed Function PA0 L3 U0Rx PA1 M3 U0Tx PA2 M4 SSI0Clk PA3 L4 SSI0Fss Multiplexed Function PA4 L5 SSI0Rx PA5 M5 SSI0Tx PA6 L6 CCP1 PA7 M6 CCP4 PB0 E12 PWM2 PB1 D12 PWM3 PB2 C11 I2C0SCL PB3 C12 I2C0SDA PB4 A6 C0- PB5 B7 C1- PB6 A7 C0+ PB7 A8 TRST PC0 A9 TCK SWCLK PC1 B9 TMS SWDIO PC2 B8 TDI PC3 A10 TDO C0o SWO PC4 L1 CCP5 PC5 M1 C1+ C1o PC6 M2 C2+ C2o PC7 L2 C2- PD0 G1 PWM0 286 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 8-3. GPIO Pins and Alternate Functions (108BGA) (continued) IO Pin Number Multiplexed Function PD1 G2 PhA0 PD2 H2 U1Rx PD3 H1 U1Tx PD4 E1 CCP0 PD5 E2 CCP2 PD6 F2 Fault PD7 F1 IDX0 PE0 A11 SSI1Clk PE1 B12 SSI1Fss PE2 B11 SSI1Rx PE3 A12 SSI1Tx PE4 D1 CCP3 PE5 D2 PE6 C2 PWM4 PE7 C1 PWM5 PF0 M9 PhB0 PF1 H12 PWM1 PF2 J11 LED1 PF3 J12 LED0 PG0 K1 U2Rx PG1 K2 U2Tx Multiplexed Function Table 8-4. GPIO Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type PA0 26 I/O TTL Description GPIO port A bit 0. PA1 27 I/O TTL GPIO port A bit 1. PA2 28 I/O TTL GPIO port A bit 2. PA3 29 I/O TTL GPIO port A bit 3. PA4 30 I/O TTL GPIO port A bit 4. PA5 31 I/O TTL GPIO port A bit 5. PA6 34 I/O TTL GPIO port A bit 6. PA7 35 I/O TTL GPIO port A bit 7. PB0 66 I/O TTL GPIO port B bit 0. PB1 67 I/O TTL GPIO port B bit 1. PB2 70 I/O TTL GPIO port B bit 2. PB3 71 I/O TTL GPIO port B bit 3. PB4 92 I/O TTL GPIO port B bit 4. PB5 91 I/O TTL GPIO port B bit 5. PB6 90 I/O TTL GPIO port B bit 6. PB7 89 I/O TTL GPIO port B bit 7. PC0 80 I/O TTL GPIO port C bit 0. June 18, 2012 287 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-4. GPIO Signals (100LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type Description PC1 79 I/O TTL GPIO port C bit 1. PC2 78 I/O TTL GPIO port C bit 2. PC3 77 I/O TTL GPIO port C bit 3. PC4 25 I/O TTL GPIO port C bit 4. PC5 24 I/O TTL GPIO port C bit 5. PC6 23 I/O TTL GPIO port C bit 6. PC7 22 I/O TTL GPIO port C bit 7. PD0 10 I/O TTL GPIO port D bit 0. PD1 11 I/O TTL GPIO port D bit 1. PD2 12 I/O TTL GPIO port D bit 2. PD3 13 I/O TTL GPIO port D bit 3. PD4 95 I/O TTL GPIO port D bit 4. PD5 96 I/O TTL GPIO port D bit 5. PD6 99 I/O TTL GPIO port D bit 6. PD7 100 I/O TTL GPIO port D bit 7. PE0 72 I/O TTL GPIO port E bit 0. PE1 73 I/O TTL GPIO port E bit 1. PE2 74 I/O TTL GPIO port E bit 2. PE3 75 I/O TTL GPIO port E bit 3. PE4 6 I/O TTL GPIO port E bit 4. PE5 5 I/O TTL GPIO port E bit 5. PE6 2 I/O TTL GPIO port E bit 6. PE7 1 I/O TTL GPIO port E bit 7. PF0 47 I/O TTL GPIO port F bit 0. PF1 61 I/O TTL GPIO port F bit 1. PF2 60 I/O TTL GPIO port F bit 2. PF3 59 I/O TTL GPIO port F bit 3. PG0 19 I/O TTL GPIO port G bit 0. PG1 18 I/O TTL GPIO port G bit 1. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 8-5. GPIO Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type PA0 L3 I/O TTL Description GPIO port A bit 0. PA1 M3 I/O TTL GPIO port A bit 1. PA2 M4 I/O TTL GPIO port A bit 2. PA3 L4 I/O TTL GPIO port A bit 3. PA4 L5 I/O TTL GPIO port A bit 4. PA5 M5 I/O TTL GPIO port A bit 5. PA6 L6 I/O TTL GPIO port A bit 6. PA7 M6 I/O TTL GPIO port A bit 7. 288 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 8-5. GPIO Signals (108BGA) (continued) Pin Name a Pin Number Pin Type Buffer Type Description PB0 E12 I/O TTL GPIO port B bit 0. PB1 D12 I/O TTL GPIO port B bit 1. PB2 C11 I/O TTL GPIO port B bit 2. PB3 C12 I/O TTL GPIO port B bit 3. PB4 A6 I/O TTL GPIO port B bit 4. PB5 B7 I/O TTL GPIO port B bit 5. PB6 A7 I/O TTL GPIO port B bit 6. PB7 A8 I/O TTL GPIO port B bit 7. PC0 A9 I/O TTL GPIO port C bit 0. PC1 B9 I/O TTL GPIO port C bit 1. PC2 B8 I/O TTL GPIO port C bit 2. PC3 A10 I/O TTL GPIO port C bit 3. PC4 L1 I/O TTL GPIO port C bit 4. PC5 M1 I/O TTL GPIO port C bit 5. PC6 M2 I/O TTL GPIO port C bit 6. PC7 L2 I/O TTL GPIO port C bit 7. PD0 G1 I/O TTL GPIO port D bit 0. PD1 G2 I/O TTL GPIO port D bit 1. PD2 H2 I/O TTL GPIO port D bit 2. PD3 H1 I/O TTL GPIO port D bit 3. PD4 E1 I/O TTL GPIO port D bit 4. PD5 E2 I/O TTL GPIO port D bit 5. PD6 F2 I/O TTL GPIO port D bit 6. PD7 F1 I/O TTL GPIO port D bit 7. PE0 A11 I/O TTL GPIO port E bit 0. PE1 B12 I/O TTL GPIO port E bit 1. PE2 B11 I/O TTL GPIO port E bit 2. PE3 A12 I/O TTL GPIO port E bit 3. PE4 D1 I/O TTL GPIO port E bit 4. PE5 D2 I/O TTL GPIO port E bit 5. PE6 C2 I/O TTL GPIO port E bit 6. PE7 C1 I/O TTL GPIO port E bit 7. PF0 M9 I/O TTL GPIO port F bit 0. PF1 H12 I/O TTL GPIO port F bit 1. PF2 J11 I/O TTL GPIO port F bit 2. PF3 J12 I/O TTL GPIO port F bit 3. PG0 K1 I/O TTL GPIO port G bit 0. PG1 K2 I/O TTL GPIO port G bit 1. a. The TTL designation indicates the pin has TTL-compatible voltage levels. June 18, 2012 289 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) 8.2 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. While debugging systems where PB7 is being used as a GPIO, care must be taken to ensure that a low value is not applied to the pin when the part is reset. Because PB7 reverts to the TRST function after reset, a Low value on the pin causes the JTAG controller to be reset, resulting in a loss of JTAG communication. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 290). The LM3S6950 microcontroller contains seven ports and thus seven of these physical GPIO blocks. Figure 8-1. GPIO Port Block Diagram Commit Control Mode Control GPIOLOCK GPIOCR GPIOAFSEL DEMUX Alternate Input Alternate Output Pad Input Alternate Output Enable Pad Output MUX Pad Output Enable Digital I/O Pad Package I/O Pin GPIO Output GPIODATA GPIODIR Interrupt MUX GPIO Input Data Control GPIO Output Enable Interrupt Control Pad Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 290 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 8.2.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 8.2.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 298) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 8.2.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 297) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-2 on page 291, where u is data unchanged by the write. Figure 8-2. GPIODATA Write Example ADDR[9:2] 0x098 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 0 0 0xEB 1 1 1 0 1 0 1 1 GPIODATA u u 1 u u 0 1 u 7 6 5 4 3 2 1 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 291. Figure 8-3. GPIODATA Read Example ADDR[9:2] 0x0C4 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 0 0 GPIODATA 1 0 1 1 1 1 1 0 Returned Value 0 0 1 1 0 0 0 0 7 6 5 4 3 2 1 0 June 18, 2012 291 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) 8.2.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: GPIO Interrupt Sense (GPIOIS) register (see page 299) GPIO Interrupt Both Edges (GPIOIBE) register (see page 300) GPIO Interrupt Event (GPIOIEV) register (see page 301) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 302). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 303 and page 304). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 305). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 8.2.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 306), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 8.2.4 Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 306) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 316) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 317) have been set to 1. 8.2.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may 292 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. 8.2.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.3 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-6 on page 293 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-7 on page 294 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 8-6. GPIO Pad Configuration Examples a Configuration GPIO Register Bit Value AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR Digital Input (GPIO) 0 0 0 1 ? ? X X X X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Output (GPIO) 0 1 1 1 X X ? ? ? ? Open Drain Input/Output (I2C) 1 X 1 1 X X ? ? ? ? Digital Input (Timer CCP) 1 X 0 1 ? ? X X X X Digital Input (QEI) 1 X 0 1 ? ? X X X X Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ? Digital Output (Timer PWM) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (SSI) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (UART) 1 X 0 1 ? ? ? ? ? ? Analog Input (Comparator) 0 0 0 0 0 0 X X X X Digital Output (Comparator) 1 X 0 1 ? ? ? ? ? ? a. X=Ignored (don't care bit) ?=Can be either 0 or 1, depending on the configuration June 18, 2012 293 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-7. GPIO Interrupt Configuration Example Register GPIOIS a Desired Interrupt Event Trigger Pin 2 Bit Value 7 0=edge 6 5 4 3 2 1 0 X X X X X 0 X X X X X X X 0 X X X X X X X 1 X X 0 0 0 0 0 1 0 0 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don't care bit) 8.4 Register Map Table 8-8 on page 295 lists the GPIO registers. The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's base address: GPIO Port A: 0x4000.4000 GPIO Port B: 0x4000.5000 GPIO Port C: 0x4000.6000 GPIO Port D: 0x4000.7000 GPIO Port E: 0x4002.4000 GPIO Port F: 0x4002.5000 GPIO Port G: 0x4002.6000 Note that the GPIO module clock must be enabled before the registers can be programmed (see page 227). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. 294 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-8. GPIO Register Map Description See page Offset Name Type Reset 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 297 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 298 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 299 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 300 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 301 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 302 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 303 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 304 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 305 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 306 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 308 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 309 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 310 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 311 0x510 GPIOPUR R/W - GPIO Pull-Up Select 312 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 313 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 314 0x51C GPIODEN R/W - GPIO Digital Enable 315 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 316 0x524 GPIOCR - - GPIO Commit 317 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 319 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 320 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 321 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 322 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 323 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 324 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 325 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 326 June 18, 2012 295 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-8. GPIO Register Map (continued) Offset Name 0xFF0 Reset GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 327 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 328 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 329 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 330 8.5 Description See page Type Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. 296 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 298). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See "Data Register Operation" on page 291 for examples of reads and writes. June 18, 2012 297 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DIR R/W 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. 298 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IS RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IS R/W 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). June 18, 2012 299 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 299) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 301). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IBE RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IBE R/W 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description 0 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 301). 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 300 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 299). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IEV RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IEV R/W 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description 0 Falling edge or Low levels on corresponding pins trigger interrupts. 1 Rising edge or High levels on corresponding pins trigger interrupts. June 18, 2012 301 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IME RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IME R/W 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. 302 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 302). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 RIS RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. June 18, 2012 303 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset MIS RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 MIS RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. 304 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 W1C 0 W1C 0 W1C 0 W1C 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IC RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IC W1C 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. June 18, 2012 305 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 306) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 316) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 317) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. While debugging systems where PB7 is being used as a GPIO, care must be taken to ensure that a low value is not applied to the pin when the part is reset. Because PB7 reverts to the TRST function after reset, a Low value on the pin causes the JTAG controller to be reset, resulting in a loss of JTAG communication. Caution - It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris(R) microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 AFSEL RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 306 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 7:0 AFSEL R/W - Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). 1 Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. June 18, 2012 307 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV2 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV2 R/W 0xFF Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 308 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV4 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV4 R/W 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. June 18, 2012 309 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV8 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV8 R/W 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 310 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 315). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see examples in "Initialization and Configuration" on page 293). GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ODE RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 ODE R/W 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. June 18, 2012 311 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 313). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PUE RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PUE R/W - Pad Weak Pull-Up Enable Value Description 0 The corresponding pin's weak pull-up resistor is disabled. 1 The corresponding pin's weak pull-up resistor is enabled. A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 312 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 312). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PDE RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PDE R/W 0x00 Pad Weak Pull-Down Enable Value Description 0 The corresponding pin's weak pull-down resistor is disabled. 1 The corresponding pin's weak pull-down resistor is enabled. A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. June 18, 2012 313 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 310). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SRL RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 SRL R/W 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. 314 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset DEN RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DEN R/W - Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. June 18, 2012 315 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 317). Writing 0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 LOCK R/W R/W 0 Reset R/W 0 Description 0x0000.0001 GPIO Lock A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 316 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSELregister bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 - - - - - - - - reserved Type Reset reserved Type Reset CR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 317 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 7:0 CR - - Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. 318 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] June 18, 2012 319 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] 320 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] June 18, 2012 321 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] 322 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x61 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. June 18, 2012 323 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 324 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. June 18, 2012 325 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 326 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. June 18, 2012 327 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 328 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. June 18, 2012 329 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID3 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 330 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. (R) The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1, Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see 93) and the PWM timer in the PWM module (see "PWM Timer" on page 575). The General-Purpose Timers provide the following features: Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: - As a single 32-bit timer - As one 32-bit Real-Time Clock (RTC) to event capture - For Pulse Width Modulation (PWM) 32-bit Timer modes - Programmable one-shot timer - Programmable periodic timer - Real-Time Clock when using an external 32.768-KHz clock as the input - User-enabled stalling when the controller asserts CPU Halt flag during debug 16-bit Timer modes - General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) - Programmable one-shot timer - Programmable periodic timer - User-enabled stalling when the controller asserts CPU Halt flag during debug 16-bit Input Capture modes - Input edge count capture - Input edge time capture 16-bit PWM mode - Simple PWM mode with software-programmable output inversion of the PWM signal June 18, 2012 331 Texas Instruments-Production Data General-Purpose Timers 9.1 Block Diagram Note: In Figure 9-1 on page 332, the specific CCP pins available depend on the Stellaris device. See Table 9-1 on page 332 for the available CCPs. Figure 9-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) TimerA Control GPTMTAPMR TA Comparator GPTMTAPR Clock / Edge Detect GPTMTAMATCHR Interrupt / Config TimerA Interrupt GPTMCFG GPTMTAILR GPTMAR En GPTMTAMR GPTMCTL GPTMIMR TimerB Interrupt 32 KHz or Even CCP Pin RTC Divider GPTMRIS GPTMMIS TimerB Control GPTMICR GPTMTBPMR GPTMTBR En Clock / Edge Detect GPTMTBPR GPTMTBMATCHR GPTMTBILR Odd CCP Pin TB Comparator GPTMTBMR 0x0000 (Down Counter Modes) System Clock Table 9-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 TimerA CCP2 - TimerB - CCP3 TimerA CCP4 - TimerB - CCP5 TimerA - - TimerB - - Timer 1 Timer 2 Timer 3 9.2 Signal Description Table 9-2 on page 333 and Table 9-3 on page 333 list the external signals of the GP Timer module and describe the function of each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the GP Timer 332 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 9-2. General-Purpose Timers Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description CCP0 95 I/O TTL Capture/Compare/PWM 0. CCP1 34 I/O TTL Capture/Compare/PWM 1. CCP2 96 I/O TTL Capture/Compare/PWM 2. CCP3 6 I/O TTL Capture/Compare/PWM 3. CCP4 35 I/O TTL Capture/Compare/PWM 4. CCP5 25 I/O TTL Capture/Compare/PWM 5. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 9-3. General-Purpose Timers Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type CCP0 E1 I/O TTL Description Capture/Compare/PWM 0. CCP1 L6 I/O TTL Capture/Compare/PWM 1. CCP2 E2 I/O TTL Capture/Compare/PWM 2. CCP3 D1 I/O TTL Capture/Compare/PWM 3. CCP4 M6 I/O TTL Capture/Compare/PWM 4. CCP5 L1 I/O TTL Capture/Compare/PWM 5. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 9.3 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 344), the GPTM TimerA Mode (GPTMTAMR) register (see page 345), and the GPTM TimerB Mode (GPTMTBMR) register (see page 347). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 358) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 359). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 362) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 363). 9.3.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. June 18, 2012 333 Texas Instruments-Production Data General-Purpose Timers The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 358 GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 359 GPTM TimerA (GPTMTAR) register [15:0], see page 366 GPTM TimerB (GPTMTBR) register [15:0], see page 367 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 9.3.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 345), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 349), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 354), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 356). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register (see page 352), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 355). If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. 9.3.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 360) by the controller. The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. 334 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.3.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 344). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 9.3.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 9-4. 16-Bit Timer With Prescaler Configurations a Prescale #Clock (T c) Max Time Units 00000000 1 1.3107 mS 00000001 2 2.6214 mS 00000010 3 3.9322 mS ------------ -- -- -- 11111101 254 332.9229 mS 11111110 255 334.2336 mS June 18, 2012 335 Texas Instruments-Production Data General-Purpose Timers Table 9-4. 16-Bit Timer With Prescaler Configurations (continued) a Prescale #Clock (T c) Max Time Units 11111111 256 335.5443 mS a. Tc is the clock period. 9.3.3.2 16-Bit Input Edge Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Count mode. In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-2 on page 337 shows how input edge count mode works. In this case, the timer start value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. 336 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 9-2. 16-Bit Input Edge Count Mode Example Timer stops, flags asserted Count Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 9.3.3.3 16-Bit Input Edge Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMTnILR register. Figure 9-3 on page 338 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). June 18, 2012 337 Texas Instruments-Production Data General-Purpose Timers Figure 9-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 9.3.3.4 16-Bit PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 on page 339 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is GPTMTnMATCHR=0x411A. 338 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 9-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 9.4 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 9.4.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. June 18, 2012 339 Texas Instruments-Production Data General-Purpose Timers 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 340. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.4.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. 9.4.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 340 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller In One-Shot mode, the timer stops counting after step 8 on page 340. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.4.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 341 through step 9 on page 341. 9.4.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM June 18, 2012 341 Texas Instruments-Production Data General-Purpose Timers Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.4.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.5 Register Map Table 9-5 on page 342 lists the GPTM registers. The offset listed is a hexadecimal increment to the register's address, relative to that timer's base address: Timer0: 0x4003.0000 Timer1: 0x4003.1000 Timer2: 0x4003.2000 Timer3: 0x4003.3000 Note that the Timer module clock must be enabled before the registers can be programmed (see page 218). There must be a delay of 3 system clocks after the Timer module clock is enabled before any Timer module registers are accessed. Table 9-5. Timers Register Map Description See page Offset Name Type Reset 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 344 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 345 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 347 342 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 9-5. Timers Register Map (continued) Name Type Reset 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 349 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 352 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 354 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 355 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 356 0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM TimerA Interval Load 358 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 359 0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM TimerA Match 360 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 361 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 362 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 363 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 364 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 365 0x048 GPTMTAR RO 0xFFFF.FFFF GPTM TimerA 366 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 367 9.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. June 18, 2012 343 Texas Instruments-Production Data General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPTMCFG RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 GPTMCFG R/W 0x0 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved 0x3 Reserved 0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 344 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 TAAMS TACMR R/W 0 R/W 0 0 TAMR R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TAAMS R/W 0 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TACMR R/W 0 To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode June 18, 2012 345 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1:0 TAMR R/W 0x0 Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 346 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 TBAMS TBCMR R/W 0 R/W 0 0 TBMR R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TBAMS R/W 0 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TBCMR R/W 0 To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode June 18, 2012 347 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1:0 TBMR R/W 0x0 Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register's contents are ignored and GPTMTAMR is used. 348 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 reserved Type Reset Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 15 14 reserved TBPWML RO 0 R/W 0 reserved RO 0 RO 0 TBEVENT R/W 0 R/W 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 TBSTALL TBEN reserved TAPWML reserved RTCEN R/W 0 R/W 0 RO 0 R/W 0 RO 0 R/W 0 TAEVENT R/W 0 R/W 0 1 0 TASTALL TAEN R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:15 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 TBPWML R/W 0 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 13:12 reserved RO 0 11:10 TBEVENT R/W 0x0 0 Output is unaffected. 1 Output is inverted. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges June 18, 2012 349 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 9 TBSTALL R/W 0 Description GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description 0 Timer B continues counting while the processor is halted by the debugger. 1 Timer B freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TBSTALL bit is ignored. 8 TBEN R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. 1 TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 TAPWML R/W 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 RTCEN R/W 0 GPTM RTC Enable The RTCEN values are defined as follows: Value Description 3:2 TAEVENT R/W 0x0 0 RTC counting is disabled. 1 RTC counting is enabled. GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 350 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1 TASTALL R/W 0 Description GPTM Timer A Stall Enable The TASTALL values are defined as follows: Value Description 0 Timer A continues counting while the processor is halted by the debugger. 1 Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TASTALL bit is ignored. 0 TAEN R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. 1 TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. June 18, 2012 351 Texas Instruments-Production Data General-Purpose Timers Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 10 9 8 CBEIM CBMIM TBTOIM R/W 0 R/W 0 R/W 0 RO 0 reserved RO 0 RO 0 RO 0 3 2 1 0 RTCIM CAEIM CAMIM TATOIM R/W 0 R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBEIM R/W 0 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 9 CBMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 8 TBTOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 7:4 reserved RO 0 0 Interrupt is disabled. 1 Interrupt is enabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 352 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 3 RTCIM R/W 0 Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 2 CAEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 1 CAMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 TATOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. June 18, 2012 353 Texas Instruments-Production Data General-Purpose Timers Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 10 CBERIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 CBMRIS TBTORIS RO 0 RO 0 reserved RO 0 RO 0 RO 0 3 2 RTCRIS CAERIS RO 0 RO 0 RO 0 CAMRIS TATORIS RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBERIS RO 0 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 7:4 reserved RO 0x0 3 RTCRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 354 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 2 1 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 3 RTCMIS RO 0 RO 0 CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBEMIS RO 0 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 9 CBMMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 7:4 reserved RO 0x0 3 RTCMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 1 CAMMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. June 18, 2012 355 Texas Instruments-Production Data General-Purpose Timers Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 CBECINT CBMCINT TBTOCINT RO 0 RO 0 W1C 0 W1C 0 W1C 0 reserved RO 0 RO 0 RO 0 RTCCINT CAECINT CAMCINT TATOCINT RO 0 W1C 0 W1C 0 W1C 0 W1C 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBECINT W1C 0 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 9 CBMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 8 TBTOCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 7:4 reserved RO 0x0 0 The interrupt is unaffected. 1 The interrupt is cleared. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 356 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 3 RTCCINT W1C 0 Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 2 CAECINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 1 CAMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Match Interrupt Clear The CAMCINT values are defined as follows: Value Description 0 TATOCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM TimerA Time-Out Interrupt Clear The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. June 18, 2012 357 Texas Instruments-Production Data General-Purpose Timers Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAILRH Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 31:16 TAILRH R/W 0xFFFF R/W 1 Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 358 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TBILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBILRL R/W 0xFFFF GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. June 18, 2012 359 Texas Instruments-Production Data General-Purpose Timers Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAMRH Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAMRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 31:16 TAMRH R/W 0xFFFF R/W 1 Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 15:0 TAMRL R/W 0xFFFF GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 360 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TBMRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBMRL R/W 0xFFFF GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. June 18, 2012 361 Texas Instruments-Production Data General-Purpose Timers Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TAPSR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TAPSR R/W 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-4 on page 335 for more details and an example. 362 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBPSR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TBPSR R/W 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-4 on page 335 for more details and an example. June 18, 2012 363 Texas Instruments-Production Data General-Purpose Timers Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TAPSMR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TAPSMR R/W 0x00 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 364 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBPSMR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TBPSMR R/W 0x00 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. June 18, 2012 365 Texas Instruments-Production Data General-Purpose Timers Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TARH Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 TARL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31:16 TARH RO 0xFFFF RO 1 Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 15:0 TARL RO 0xFFFF GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge-Count mode, when it returns the number of edges that have occurred. 366 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TBRL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBRL RO 0xFFFF GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge-Count mode, when it returns the number of edges that have occurred. June 18, 2012 367 Texas Instruments-Production Data Watchdog Timer 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. (R) The Stellaris Watchdog Timer module has the following features: 32-bit down counter with a programmable load register Separate watchdog clock with an enable Programmable interrupt generation logic with interrupt masking Lock register protection from runaway software Reset generation logic with an enable/disable User-enabled stalling when the controller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 368 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS 32-Bit Down Counter WDTMIS 0x00000000 WDTLOCK System Clock WDTTEST Comparator WDTVALUE Identification Registers 10.2 WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. June 18, 2012 369 Texas Instruments-Production Data Watchdog Timer Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 10.4 Register Map Table 10-1 on page 370 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register's address, relative to the Watchdog Timer base address of 0x4000.0000. Table 10-1. Watchdog Timer Register Map Description See page Offset Name Type Reset 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 372 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 373 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 374 0x00C WDTICR WO - Watchdog Interrupt Clear 375 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 376 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 377 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 378 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 379 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 380 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 381 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 382 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 383 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 384 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 385 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 386 370 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 10-1. Watchdog Timer Register Map (continued) Offset Name 0xFEC Reset WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 387 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 388 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 389 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 390 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 391 10.5 Description See page Type Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. June 18, 2012 371 Texas Instruments-Production Data Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 WDTLoad Type Reset WDTLoad Type Reset Bit/Field Name Type 31:0 WDTLoad R/W Reset R/W 1 Description 0xFFFF.FFFF Watchdog Load Value 372 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 WDTValue Type Reset WDTValue Type Reset Bit/Field Name Type 31:0 WDTValue RO Reset RO 1 Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. June 18, 2012 373 Texas Instruments-Production Data Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 RESEN INTEN R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RESEN R/W 0 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 INTEN R/W 0 0 Disabled. 1 Enable the Watchdog module reset output. Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 1 Interrupt event enabled. Once enabled, all writes are ignored. 374 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WDTIntClr Type Reset WDTIntClr Type Reset Bit/Field Name Type Reset 31:0 WDTIntClr WO - WO - Description Watchdog Interrupt Clear June 18, 2012 375 Texas Instruments-Production Data Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 WDTRIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 WDTRIS RO 0 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 376 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 WDTMIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 WDTMIS RO 0 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. June 18, 2012 377 Texas Instruments-Production Data Watchdog Timer Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STALL R/W 0 reserved Bit/Field Name Type Reset Description 31:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 STALL R/W 0 Watchdog Stall Enable When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 378 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WDTLock Type Reset WDTLock Type Reset Bit/Field Name Type Reset 31:0 WDTLock R/W 0x0000 R/W 0 Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked June 18, 2012 379 Texas Instruments-Production Data Watchdog Timer Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] 380 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] June 18, 2012 381 Texas Instruments-Production Data Watchdog Timer Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] 382 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] June 18, 2012 383 Texas Instruments-Production Data Watchdog Timer Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] 384 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] June 18, 2012 385 Texas Instruments-Production Data Watchdog Timer Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] 386 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] June 18, 2012 387 Texas Instruments-Production Data Watchdog Timer Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] 388 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] June 18, 2012 389 Texas Instruments-Production Data Watchdog Timer Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] 390 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] June 18, 2012 391 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 11 Universal Asynchronous Receivers/Transmitters (UARTs) (R) Each Stellaris Universal Asynchronous Receiver/Transmitter (UART) has the following features: Three fully programmable 16C550-type UARTs with IrDA support Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading Programmable baud-rate generator allowing speeds up to 3.125 Mbps Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 Standard asynchronous communication bits for start, stop, and parity Line-break generation and detection Fully programmable serial interface characteristics - 5, 6, 7, or 8 data bits - Even, odd, stick, or no-parity bit generation/detection - 1 or 2 stop bit generation IrDA serial-IR (SIR) encoder/decoder providing - Programmable use of IrDA Serial Infrared (SIR) or UART input/output - Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex - Support of normal 3/16 and low-power (1.41-2.23 s) bit durations - Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration 392 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 11.1 Block Diagram Figure 11-1. UART Module Block Diagram System Clock Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 11.2 TxFIFO 16 x 8 . . . Baud Rate Generator UARTDR Transmitter (with SIR Transmit Encoder) UnTx UARTIBRD UARTFBRD Control/Status RxFIFO 16 x 8 UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR . . . Receiver (with SIR Receive Decoder) UnRx Signal Description Table 11-1 on page 393 and Table 11-2 on page 394 list the external signals of the UART module and describe the function of each. The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the UART function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 11-1. UART Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx 12 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. June 18, 2012 393 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Table 11-1. UART Signals (100LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type Description U1Tx 13 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 19 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 18 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 11-2. UART Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx H2 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx H1 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx K1 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx K2 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 11.3 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 413). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 11.3.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 11-2 on page 395 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. 394 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 11-2. UART Character Frame UnTX LSB 1 5-8 data bits 0 n Parity bit if enabled Start 11.3.2 1-2 stop bits MSB Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 409) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 410). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 411), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: UARTIBRD write, UARTFBRD write, and UARTLCRH write UARTFBRD write, UARTIBRD write, and UARTLCRH write UARTIBRD write and UARTLCRH write UARTFBRD write and UARTLCRH write 11.3.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 406) is asserted as soon as June 18, 2012 395 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in "Transmit/Receive Logic" on page 394). The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 11.3.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 s, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 408 for more information on IrDA low-power pulse-duration configuration. Figure 11-3 on page 397 shows the UART transmit and receive signals, with and without IrDA modulation. 396 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 11-3. IrDA Data Modulation Data bits Start bit UnTx 1 0 0 0 1 Stop bit 0 0 1 1 1 UnTx with IrDA 3 16 Bit period Bit period UnRx with IrDA UnRx 0 1 0 Start 1 0 0 1 1 Data bits 0 1 Stop In both normal and low-power IrDA modes: During transmission, the UART data bit is used as the base for encoding During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal as an alternate function must be configured as the UnRx signal and pulled High. 11.3.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 402). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 411). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 406) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 415). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, 1/4, 1/2, 3/4, and 7/8. For example, if the 1/4 option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the 1/2 mark. 11.3.6 Interrupts The UART can generate interrupts when the following conditions are observed: June 18, 2012 397 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Overrun Error Break Error Parity Error Framing Error Receive Timeout Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 420). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 417) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 419). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 421). The receive interrupt changes state when one of the following events occurs: If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit. If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit. The transmit interrupt changes state when one of the following events occurs: If the FIFOs are enabled and the transmit FIFO reaches the programmed trigger level, the TXRIS bit is set. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit. If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit. 11.3.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 413). In loopback mode, data transmitted on UnTx is received on the UnRx input. 398 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 11.3.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 11.4 Initialization and Configuration To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1 register. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz and the desired UART configuration is: 115200 baud rate Data length of 8 bits One stop bit No parity FIFOs disabled No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in "Baud-Rate Generation" on page 395, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 409) should be set to 10. The value to be loaded into the UARTFBRD register (see page 410) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. June 18, 2012 399 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 11.5 Register Map Table 11-3 on page 400 lists the UART registers. The offset listed is a hexadecimal increment to the register's address, relative to that UART's base address: UART0: 0x4000.C000 UART1: 0x4000.D000 UART2: 0x4000.E000 Note that the UART module clock must be enabled before the registers can be programmed (see page 218). There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed. Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 413) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 11-3. UART Register Map Offset Name Type Reset Description See page 0x000 UARTDR R/W 0x0000.0000 UART Data 402 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 404 0x018 UARTFR RO 0x0000.0090 UART Flag 406 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 408 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 409 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 410 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 411 0x030 UARTCTL R/W 0x0000.0300 UART Control 413 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 415 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 417 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 419 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 420 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 421 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 423 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 424 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 425 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 426 0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 427 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 428 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 429 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 430 400 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 11-3. UART Register Map (continued) Offset Name 0xFF0 Reset UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 431 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 432 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 433 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 434 11.6 Description See page Type Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. June 18, 2012 401 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 1: UART Data (UARTDR), offset 0x000 Important: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 OE BE PE FE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DATA Bit/Field Name Type Reset Description 31:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 OE RO 0 UART Overrun Error The OE values are defined as follows: Value Description 10 BE RO 0 0 There has been no data loss due to a FIFO overrun. 1 New data was received when the FIFO was full, resulting in data loss. UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 402 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 9 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 7:0 DATA R/W 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. June 18, 2012 403 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Reads UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 OE BE PE FE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 OE RO 0 UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 2 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 404 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Writes UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset DATA WO 0 Bit/Field Name Type Reset Description 31:8 reserved WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA WO 0 Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. June 18, 2012 405 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TXFE RXFF TXFF RXFE BUSY RO 1 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 TXFE RO 1 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 6 RXFF RO 0 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 5 TXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 4 RXFE RO 1 UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 406 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 407 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41-2.11 s (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 s are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ILPDVSR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 ILPDVSR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 408 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See "Baud-Rate Generation" on page 395 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DIVINT Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0 15:0 DIVINT R/W 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Integer Baud-Rate Divisor June 18, 2012 409 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See "Baud-Rate Generation" on page 395 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DIVFRAC R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor 410 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SPS RO 0 RO 0 RO 0 RO 0 R/W 0 5 WLEN R/W 0 R/W 0 4 3 2 1 0 FEN STP2 EPS PEN BRK R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 SPS R/W 0 UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 6:5 WLEN R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 4 FEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 3 STP2 R/W 0 UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. June 18, 2012 411 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2 EPS R/W 0 Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 BRK R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 412 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. Note: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE TXE LBE RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 0 SIRLP SIREN UARTEN RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 RXE R/W 1 UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. June 18, 2012 413 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 8 TXE R/W 1 Description UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: 7 LBE R/W 0 To enable transmission, the UARTEN bit must also be set. UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SIRLP R/W 0 UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 408 for more information. 1 SIREN R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 UARTEN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 414 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RXIFLSEL R/W 1 TXIFLSEL R/W 1 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:3 RXIFLSEL R/W 0x2 UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO full 0x1 RX FIFO 1/4 full 0x2 RX FIFO 1/2 full (default) 0x3 RX FIFO 3/4 full 0x4 RX FIFO full 0x5-0x7 Reserved June 18, 2012 415 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2:0 TXIFLSEL R/W 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO empty 0x1 TX FIFO 3/4 empty 0x2 TX FIFO 1/2 empty (default) 0x3 TX FIFO 1/4 empty 0x4 TX FIFO empty 0x5-0x7 Reserved 416 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEIM BEIM PEIM FEIM RTIM TXIM RXIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIM R/W 0 UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 9 BEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 5 TXIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. June 18, 2012 417 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 4 RXIM R/W 0 Description UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 418 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OERIS RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BERIS PERIS FERIS RTRIS TXRIS RXRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OERIS RO 0 UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 9 BERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved RO 0xF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 419 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OEMIS RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 420 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OEIC RO 0 RO 0 RO 0 RO 0 W1C 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEIC PEIC FEIC RTIC TXIC RXIC W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIC W1C 0 Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 9 BEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 8 PEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. June 18, 2012 421 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 7 FEIC W1C 0 Description Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 6 RTIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 5 TXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 4 RXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Receive Interrupt Clear The RXIC values are defined as follows: Value Description 3:0 reserved RO 0x00 0 No effect on the interrupt. 1 Clears interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 422 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x0000 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. June 18, 2012 423 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x0000 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 424 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x0000 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. June 18, 2012 425 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 PID7 RO 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 426 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x11 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. June 18, 2012 427 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 428 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. June 18, 2012 429 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 430 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. June 18, 2012 431 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 432 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. June 18, 2012 433 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 434 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 12 Synchronous Serial Interface (SSI) (R) The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. Each Stellaris SSI module has the following features: Two SSI modules, each with the following features: Master or slave operation Programmable clock bit rate and prescale Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces Programmable data frame size from 4 to 16 bits Internal loopback test mode for diagnostic/debug testing 12.1 Block Diagram Figure 12-1. SSI Module Block Diagram Interrupt Interrupt Control SSIIM SSIMIS Control/ Status SSICR0 SSIRIS SSIICR SSICR1 TxFIFO 8 x16 . . . SSITx SSISR SSIRx SSIDR RxFIFO 8 x16 System Clock SSIPCellID0 Identification Registers SSIPeriphID0 SSIPeriphID 4 SSIPCellID1 SSIPeriphID 1 SSIPeriphID 5 SSIPCellID2 SSIPeriphID 2 SSIPeriphID 6 SSIPCellID3 SSIPeriphID 3 SSIPeriphID7 Clock Prescaler Transmit / Receive Logic SSIClk SSIFss . . . SSICPSR June 18, 2012 435 Texas Instruments-Production Data Synchronous Serial Interface (SSI) 12.2 Signal Description Table 12-1 on page 436 and Table 12-2 on page 436 list the external signals of the SSI module and describe the function of each. The SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the SSI function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 12-1. SSI Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description SSI0Clk 28 I/O TTL SSI module 0 clock SSI0Fss 29 I/O TTL SSI module 0 frame signal SSI0Rx 30 I TTL SSI module 0 receive SSI0Tx 31 O TTL SSI module 0 transmit SSI1Clk 72 I/O TTL SSI module 1 clock SSI1Fss 73 I/O TTL SSI module 1 frame signal SSI1Rx 74 I TTL SSI module 1 receive SSI1Tx 75 O TTL SSI module 1 transmit a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 12-2. SSI Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description SSI0Clk M4 I/O TTL SSI module 0 clock SSI0Fss L4 I/O TTL SSI module 0 frame signal SSI0Rx L5 I TTL SSI module 0 receive SSI0Tx M5 O TTL SSI module 0 transmit SSI1Clk A11 I/O TTL SSI module 1 clock SSI1Fss B12 I/O TTL SSI module 1 frame signal SSI1Rx B11 I TTL SSI module 1 receive SSI1Tx A12 O TTL SSI module 1 transmit a. The TTL designation indicates the pin has TTL-compatible voltage levels. 12.3 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 12.3.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale 436 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller (SSICPSR) register (see page 455). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 448). The frequency of the output clock SSIClk is defined by: SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note: For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See "Synchronous Serial Interface (SSI)" on page 671 to view SSI timing parameters. 12.3.2 FIFO Operation 12.3.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 452), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or a DMA request when the FIFO is empty. 12.3.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 12.3.3 Interrupts The SSI can generate interrupts when the following conditions are observed: Transmit FIFO service Receive FIFO service Receive FIFO time-out Receive FIFO overrun All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 456). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and June 18, 2012 437 Texas Instruments-Production Data Synchronous Serial Interface (SSI) receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 458 and page 459, respectively). 12.3.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: Texas Instruments synchronous serial Freescale SPI MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 12.3.4.1 Texas Instruments Synchronous Serial Frame Format Figure 12-2 on page 438 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is 438 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 12-3 on page 439 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits 12.3.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 12.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 12-4 on page 440 and Figure 12-5 on page 440. June 18, 2012 439 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB Q 4 to 16 bits SSITx MSB Note: LSB Q is undefined. Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB LSB MSB MSB 4 to16 bits SSITx LSB MSB LSB MSB In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to 440 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 12-6 on page 441, which covers both single and continuous transfers. Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q Q MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 12-7 on page 442 and Figure 12-8 on page 442. June 18, 2012 441 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB LSB MSB 4 to 16 bits In this configuration, during idle periods: SSIClk is forced High SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 442 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 12.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 12-9 on page 443, which covers both single and continuous transfers. Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB LSB Q 4 to 16 bits MSB SSITx Note: LSB Q is undefined. In this configuration, during idle periods: SSIClk is forced High SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.3.4.7 MICROWIRE Frame Format Figure 12-10 on page 444 shows the MICROWIRE frame format, again for a single frame. Figure 12-11 on page 445 shows the same format when back-to-back frames are transmitted. June 18, 2012 443 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 12-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx LSB MSB 8-bit control 0 SSIRx MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. 444 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB MSB LSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 12-12 on page 445 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 12.4 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: June 18, 2012 445 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Serial clock rate (SCR) Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: Master operation Freescale SPI mode (SPO=1, SPH=1) 1 Mbps bit rate 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 12.5 Register Map Table 12-3 on page 447 lists the SSI registers. The offset listed is a hexadecimal increment to the register's address, relative to that SSI module's base address: SSI0: 0x4000.8000 SSI1: 0x4000.9000 Note that the SSI module clock must be enabled before the registers can be programmed (see page 218). There must be a delay of 3 system clocks after the SSI module clock is enabled before any SSI module registers are accessed. Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. 446 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 12-3. SSI Register Map Offset Name Type Reset Description See page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 448 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 450 0x008 SSIDR R/W 0x0000.0000 SSI Data 452 0x00C SSISR RO 0x0000.0003 SSI Status 453 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 455 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 456 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 458 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 459 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 460 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 461 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 462 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 463 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 464 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 465 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 466 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 467 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 468 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 469 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 470 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 471 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 472 12.6 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. June 18, 2012 447 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 SPH SPO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset SCR Type Reset FRF R/W 0 DSS Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 SCR R/W 0x0000 SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 6 SPO R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. 448 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 5:4 FRF R/W 0x0 Description SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Instruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 3:0 DSS R/W 0x00 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data June 18, 2012 449 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SOD MS SSE LBM RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SOD R/W 0 SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 2 MS R/W 0 0 SSI can drive SSITx output in Slave Output mode. 1 SSI must not drive the SSITx output in Slave mode. SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 Device configured as a master. 1 Device configured as a slave. 450 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1 SSE R/W 0 Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 SSI operation disabled. 1 SSI operation enabled. Note: 0 LBM R/W 0 This bit must be set to 0 before any control registers are reprogrammed. SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 Normal serial port operation enabled. 1 Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. June 18, 2012 451 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 3: SSI Data (SSIDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. 452 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BSY RFF RNE TNF TFE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 R0 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:5 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 BSY RO 0 SSI Busy Bit The BSY values are defined as follows: Value Description 3 RFF RO 0 0 SSI is idle. 1 SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. SSI Receive FIFO Full The RFF values are defined as follows: Value Description 2 RNE RO 0 0 Receive FIFO is not full. 1 Receive FIFO is full. SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 1 TNF RO 1 0 Receive FIFO is empty. 1 Receive FIFO is not empty. SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 Transmit FIFO is full. 1 Transmit FIFO is not full. June 18, 2012 453 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 0 TFE R0 1 Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. 454 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CPSDVSR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CPSDVSR R/W 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. June 18, 2012 455 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 TXIM RXIM RTIM RORIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 2 RXIM R/W 0 0 TX FIFO half-empty or less condition interrupt is masked. 1 TX FIFO half-empty or less condition interrupt is not masked. SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 1 RTIM R/W 0 0 RX FIFO half-full or more condition interrupt is masked. 1 RX FIFO half-full or more condition interrupt is not masked. SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 RX FIFO time-out interrupt is masked. 1 RX FIFO time-out interrupt is not masked. 456 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 0 RORIM R/W 0 Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 RX FIFO overrun interrupt is masked. 1 RX FIFO overrun interrupt is not masked. June 18, 2012 457 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXRIS RXRIS RTRIS RORRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half empty or less, when set. 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. 458 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXMIS RXMIS RTMIS RORMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half empty or less, when set. 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. June 18, 2012 459 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RTIC RORIC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 RORIC W1C 0 0 No effect on interrupt. 1 Clears interrupt. SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. 460 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. June 18, 2012 461 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 462 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. June 18, 2012 463 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 464 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 PID0 RO 0x22 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. June 18, 2012 465 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 466 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. June 18, 2012 467 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 468 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. June 18, 2012 469 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 470 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. June 18, 2012 471 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 472 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 13 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S6950 microcontroller includes one I2C module, providing the ability to interact (both send and receive) with other I2C devices on the bus. (R) The Stellaris I2C interface has the following features: Devices on the I2C bus can be designated as either a master or a slave - Supports both sending and receiving data as either a master or a slave - Supports simultaneous master and slave operation Four I2C modes - Master transmit - Master receive - Slave transmit - Slave receive Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) Master and slave interrupt generation - Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) - Slave generates interrupts when data has been sent or requested by a master Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode June 18, 2012 473 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 13.1 Block Diagram Figure 13-1. I2C Block Diagram I2CSCL I2C Control Interrupt I2CMSA I2CSOAR I2CMCS I2CSCSR I2CMDR I2CSDR I2CMTPR I2CSIM I2CMIMR I2CSRIS I2CMRIS I2CSMIS I2CMMIS I2CSICR I2C Master Core I2CSCL I2C I/O Select I2CSDA I2CSCL I2C Slave Core I2CMICR I2CSDA I2CMCR 13.2 I2CSDA Signal Description Table 13-1 on page 474 and Table 13-2 on page 474 list the external signals of the I2C interface and describe the function of each. The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the I2C function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the I2C function. Note that the I2C pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 13-1. I2C Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description I2C0SCL 70 I/O OD I2C module 0 clock. I2C0SDA 71 I/O OD I2C module 0 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 13-2. I2C Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description I2C0SCL C11 I/O OD I2C module 0 clock. I2C0SDA C12 I/O OD I2C module 0 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 13.3 Functional Description The I2C module is comprised of both master and slave functions which are implemented as separate peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional open-drain pads. A typical I2C bus configuration is shown in Figure 13-2 on page 475. See "Inter-Integrated Circuit (I2C) Interface" on page 672 for I2C timing diagrams. 474 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 13-2. I2C Bus Configuration RPUP SCL SDA I2C Bus I2CSCL I2CSDA StellarisTM 13.3.1 RPUP SCL SDA 3rd Party Device with I2C Interface SCL SDA 3rd Party Device with I2C Interface I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are High. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in "START and STOP Conditions" on page 475) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 13.3.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 13-3 on page 475. Figure 13-3. START and STOP Conditions SDA SDA SCL SCL START condition 13.3.1.2 STOP condition Data Format with 7-Bit Address Data transfers follow the format shown in Figure 13-4 on page 476. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within a single transfer. June 18, 2012 475 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 13-4. Complete Data Transfer with a 7-Bit Address SDA MSB SCL 1 2 LSB R/S ACK 7 8 9 MSB 1 2 Slave address 7 LSB ACK 8 9 Data The first seven bits of the first byte make up the slave address (see Figure 13-5 on page 476). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. Figure 13-5. R/S Bit in First Byte MSB LSB R/S Slave address 13.3.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 13-6 on page 476). Figure 13-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL Data line Change stable of data allowed 13.3.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in "Data Validity" on page 476. When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Since the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. 13.3.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an 476 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of the competing master devices to place a '1' (High) on SDA while another master transmits a '0' (Low) will switch off its data output stage and retire until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 13.3.2 Available Speed Modes The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP. where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see page 495). The I2C clock period is calculated as follows: SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/T = 333 Khz Table 13-3 on page 477 gives examples of timer period, system clock, and speed mode (Standard or Fast). Table 13-3. Examples of I2C Master Timer Period versus Speed Mode System Clock Timer Period Standard Mode Timer Period Fast Mode 4 MHz 0x01 100 Kbps - - 6 MHz 0x02 100 Kbps - - 12.5 MHz 0x06 89 Kbps 0x01 312 Kbps 16.7 MHz 0x08 93 Kbps 0x02 278 Kbps 20 MHz 0x09 100 Kbps 0x02 333 Kbps 25 MHz 0x0C 96.2 Kbps 0x03 312 Kbps 33 MHz 0x10 97.1 Kbps 0x04 330 Kbps 40 MHz 0x13 100 Kbps 0x04 400 Kbps 50 MHz 0x18 100 Kbps 0x06 357 Kbps June 18, 2012 477 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 13.3.3 Interrupts The I2C can generate interrupts when the following conditions are observed: Master transaction completed Master arbitration lost Master transaction error Slave transaction received Slave transaction requested There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 13.3.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 13.3.3.2 I2C Slave Interrupts The slave module can generate an interrupt when data has been received or requested. This interrupt is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit in the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 13.3.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. 13.3.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 478 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 13.3.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. June 18, 2012 479 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 13-7. Master Single SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Write data to I2CMDR Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 480 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 13-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle June 18, 2012 481 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 13-9. Master Burst SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Write data to I2CMDR BUSY bit=0? YES Read I2CMCS ERROR bit=0? NO NO NO BUSBSY bit=0? YES Write data to I2CMDR YES Write ---0-011 to I2CMCS NO ARBLST bit=1? YES Write ---0-001 to I2CMCS NO Index=n? YES Write ---0-101 to I2CMCS Write ---0-100 to I2CMCS Error Service Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 482 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 13-10. Master Burst RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS BUSY bit=0? Read I2CMCS NO YES NO BUSBSY bit=0? ERROR bit=0? NO YES Write ---01011 to I2CMCS NO Read data from I2CMDR ARBLST bit=1? YES Write ---01001 to I2CMCS NO Write ---0-100 to I2CMCS Index=m-1? Error Service YES Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? YES Error Service Read data from I2CMDR Idle June 18, 2012 483 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 13-11. Master Burst RECEIVE after Burst SEND Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Master operates in Master Receive mode Repeated START condition is generated with changing data direction Idle 484 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 13-12. Master Burst SEND after Burst RECEIVE Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Repeated START condition is generated with changing data direction Idle 13.3.5.2 I2C Slave Command Sequences Figure 13-13 on page 486 presents the command sequence available for the I2C slave. June 18, 2012 485 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 13-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR 13.4 NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR Initialization and Configuration The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation. 4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020. 5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: 486 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 6. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data. 8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 9. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has been cleared. 13.5 Register Map Table 13-4 on page 487 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave: I2C 0: 0x4002.0000 Note that the I2C module clock must be enabled before the registers can be programmed (see page 218). There must be a delay of 3 system clocks after the I2C module clock is enabled before any I2C module registers are accessed. (R) The hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x800 for the I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses an offset between 0x000 and 0x018 with the slave base address. Table 13-4. Inter-Integrated Circuit (I2C) Interface Register Map Offset Description See page Name Type Reset 0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 489 0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 490 0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 494 0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 495 0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 496 0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 497 0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 498 0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 499 0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 500 I2C Master June 18, 2012 487 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Table 13-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued) Offset Description See page Name Type Reset 0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 502 0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 503 0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 505 0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 506 0x810 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 507 0x814 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 508 0x818 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 509 I2C Slave 13.6 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also "Register Descriptions (I2C Slave)" on page 501. 488 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low). I2C Master Slave Address (I2CMSA) I2C 0 base: 0x4002.0000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset SA RO 0 R/S Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:1 SA R/W 0 I2C Slave Address This field specifies bits A6 through A0 of the slave address. 0 R/S R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Send (Low). Value Description 0 Send. 1 Receive. June 18, 2012 489 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after each byte. This bit must be reset when the I2C bus controller requires no further data to be sent from the slave transmitter. Reads I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BUSBSY IDLE ARBLST ERROR BUSY RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATACK ADRACK RO 0 RO 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 BUSBSY RO 0 Bus Busy This bit specifies the state of the I2C bus. If set, the bus is busy; otherwise, the bus is idle. The bit changes based on the START and STOP conditions. 5 IDLE RO 0 I2C Idle This bit specifies the I2C controller state. If set, the controller is idle; otherwise the controller is not idle. 4 ARBLST RO 0 Arbitration Lost This bit specifies the result of bus arbitration. If set, the controller lost arbitration; otherwise, the controller won arbitration. 490 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 3 DATACK RO 0 Description Acknowledge Data This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 2 ADRACK RO 0 Acknowledge Address This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 1 ERROR RO 0 Error This bit specifies the result of the last bus operation. If set, an error occurred on the last operation; otherwise, no error was detected. The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 BUSY RO 0 I2C Busy This bit specifies the state of the controller. If set, the controller is busy; otherwise, the controller is idle. When the BUSY bit is set, the other status bits are not valid. Writes I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 ACK STOP START RUN WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved WO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 ACK WO 0 Data Acknowledge Enable When set, causes received data byte to be acknowledged automatically by the master. See field decoding in Table 13-5 on page 492. 2 STOP WO 0 Generate STOP When set, causes the generation of the STOP condition. See field decoding in Table 13-5 on page 492. 1 START WO 0 Generate START When set, causes the generation of a START or repeated START condition. See field decoding in Table 13-5 on page 492. June 18, 2012 491 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 0 RUN WO 0 Description I2C Master Enable When set, allows the master to send or receive data. See field decoding in Table 13-5 on page 492. Table 13-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) Current I2CMSA[0] State R/S Idle I2CMCS[3:0] ACK STOP START RUN 1 0 X a 0 1 0 X 1 1 1 START condition followed by a SEND and STOP condition (master remains in Idle state). 1 0 0 1 1 START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). 1 0 1 1 1 START condition followed by RECEIVE and STOP condition (master remains in Idle state). 1 1 0 1 1 START condition followed by RECEIVE (master goes to the Master Receive state). 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. Master Transmit Description START condition followed by SEND (master goes to the Master Transmit state). NOP. X X 0 0 1 SEND operation (master remains in Master Transmit state). X X 1 0 0 STOP condition (master goes to Idle state). X X 1 0 1 SEND followed by STOP condition (master goes to Idle state). 0 X 0 1 1 Repeated START condition followed by a SEND (master remains in Master Transmit state). 0 X 1 1 1 Repeated START condition followed by SEND and STOP condition (master goes to Idle state). 1 0 0 1 1 Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). 1 0 1 1 1 Repeated START condition followed by a SEND and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master goes to Master Receive state). 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. NOP. 492 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 13-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued) Current I2CMSA[0] State R/S I2CMCS[3:0] Description ACK STOP START RUN X 0 0 0 1 RECEIVE operation with negative ACK (master remains in Master Receive state). X X 1 0 0 STOP condition (master goes to Idle state). X 0 1 0 1 RECEIVE followed by STOP condition (master goes to Idle state). X 1 0 0 1 RECEIVE operation (master remains in Master Receive state). X 1 1 0 1 Illegal. 1 0 0 1 1 Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). 1 0 1 1 1 Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master remains in Master Receive state). 0 X 0 1 1 Repeated START condition followed by SEND (master goes to Master Transmit state). 0 X 1 1 1 Repeated START condition followed by SEND and STOP condition (master goes to Idle state). Master Receive All other combinations not listed are non-operations. b NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. June 18, 2012 493 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 3: I2C Master Data (I2CMDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C 0 base: 0x4002.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DATA RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x00 Data Transferred Data transferred during transaction. 494 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. Caution - Take care not to set bit 7 when accessing this register as unpredictable behavior can occur. I2C Master Timer Period (I2CMTPR) I2C 0 base: 0x4002.0000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TPR RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 TPR R/W 0x1 SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). June 18, 2012 495 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C 0 base: 0x4002.0000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 IM Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IM R/W 0 Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 496 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C 0 base: 0x4002.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RIS RO 0 Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C master block. If set, an interrupt is pending; otherwise, an interrupt is not pending. June 18, 2012 497 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C 0 base: 0x4002.0000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MIS RO 0 Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C master block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 498 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt. I2C Master Interrupt Clear (I2CMICR) I2C 0 base: 0x4002.0000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 IC Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IC WO 0 Interrupt Clear This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise, a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. June 18, 2012 499 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C 0 base: 0x4002.0000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SFE MFE RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved RO 0 RO 0 LPBK RO 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SFE R/W 0 I2C Slave Function Enable This bit specifies whether the interface may operate in Slave mode. If set, Slave mode is enabled; otherwise, Slave mode is disabled. 4 MFE R/W 0 I2C Master Function Enable This bit specifies whether the interface may operate in Master mode. If set, Master mode is enabled; otherwise, Master mode is disabled and the interface clock is disabled. 3:1 reserved RO 0x00 0 LPBK R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Loopback This bit specifies whether the interface is operating normally or in Loopback mode. If set, the device is put in a test mode loopback configuration; otherwise, the device operates normally. 500 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 13.7 Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also "Register Descriptions (I2C Master)" on page 488. June 18, 2012 501 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C 0 base: 0x4002.0000 Offset 0x800 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 OAR RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 OAR R/W 0x00 I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. 502 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 This register accesses one control bit when written, and three status bits when read. The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into the I2C Slave Data (I2CSDR) register to clear the TREQ bit. The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the Stellaris I2C slave operation. Reads I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 Offset 0x804 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 FBR TREQ RREQ RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 FBR RO 0 First Byte Received Indicates that the first byte following the slave's own address is received. This bit is only valid when the RREQ bit is set, and is automatically cleared when data has been read from the I2CSDR register. Note: 1 TREQ RO 0 This bit is not used for slave transmit operations. Transmit Request This bit specifies the state of the I2C slave with regards to outstanding transmit requests. If set, the I2C unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the I2CSDR register. Otherwise, there is no outstanding transmit request. 0 RREQ RO 0 Receive Request This bit specifies the status of the I2C slave with regards to outstanding receive requests. If set, the I2C unit has outstanding receive data from the I2C master and uses clock stretching to delay the master until the data has been read from the I2CSDR register. Otherwise, no receive data is outstanding. June 18, 2012 503 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Writes I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 Offset 0x804 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 DA Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DA WO 0 Device Active Value Description 0 Disables the I2C slave operation. 1 Enables the I2C slave operation. Once this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 504 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: I2C Slave Data (I2CSDR), offset 0x808 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C 0 base: 0x4002.0000 Offset 0x808 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DATA RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x0 Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. June 18, 2012 505 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C 0 base: 0x4002.0000 Offset 0x80C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATAIM R/W 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATAIM R/W 0 Data Interrupt Mask This bit controls whether the raw interrupt for data received and data requested is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 506 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C 0 base: 0x4002.0000 Offset 0x810 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATARIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATARIS RO 0 Data Raw Interrupt Status This bit specifies the raw interrupt state for data received and data requested (prior to masking) of the I2C slave block. If set, an interrupt is pending; otherwise, an interrupt is not pending. June 18, 2012 507 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C 0 base: 0x4002.0000 Offset 0x814 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATAMIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATAMIS RO 0 Data Masked Interrupt Status This bit specifies the interrupt state for data received and data requested (after masking) of the I2C slave block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 508 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 This register clears the raw interrupt. A read of this register returns no meaningful data. I2C Slave Interrupt Clear (I2CSICR) I2C 0 base: 0x4002.0000 Offset 0x818 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATAIC WO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATAIC WO 0 Data Interrupt Clear This bit controls the clearing of the raw interrupt for data received and data requested. When set, it clears the DATARIS interrupt bit; otherwise, it has no effect on the DATARIS bit value. June 18, 2012 509 Texas Instruments-Production Data Ethernet Controller 14 Ethernet Controller (R) The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Stellaris Ethernet Controller module has the following features: Conforms to the IEEE 802.3-2002 specification - 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line - 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler - Full-featured auto-negotiation Multiple operational modes - Full- and half-duplex 100 Mbps - Full- and half-duplex 10 Mbps - Power-saving and power-down modes Highly configurable - Programmable MAC address - LED activity selection - Promiscuous mode support - CRC error-rejection control - User-configurable interrupts Physical media manipulation - Automatic MDI/MDI-X cross-over correction - Register-programmable transmit amplitude - Automatic polarity correction and 10BASE-T signal reception IEEE 1588 Precision Time Protocol - provides highly accurate time stamps for individual packets 14.1 Block Diagram As shown in Figure 14-1 on page 511, the Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers correspond to the OSI model layers 2 and 1. The CPU accesses the Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the PHY layer via an internal Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus. 510 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 14-1. Ethernet Controller Ethernet Media Controller Physical Access Layer Entity Controller ARM Cortex M3 MAC (Layer 2) Magnetics RJ45 PHY (Layer 1) Figure 14-2 on page 511 shows more detail of the internal structure of the Ethernet Controller and how the register set relates to various functions. Figure 14-2. Ethernet Controller Block Diagram Interrupt Interrupt Control Receive Control MACRIS MACIACK MACIM MACRCTL MACNP TXOP Transmit FIFO Data Access Transmit Encoding Pulse Shaping Collision Detect Carrier Sense Receive Decoding Clock Recovery TXON MDIX MACDDATA RXIP Timer Support Transmit Control MACTS MACTCTL MACTHR MACTR Receive FIFO MII Control Individual Address MACIA0 Media Independent Interface Management Register Set MR0 MR1 MR2 MR3 MACMCTL MACMDV MACMTXD MACMRXD MACIA1 MR4 MR5 MR6 MR16 MR17 MR18 MR19 MR23 MR24 RXIN Auto Negotiation XTALPPHY Clock Reference XTALNPHY LED0 LED1 14.2 Signal Description Table 14-1 on page 512 and Table 14-2 on page 512 list the external signals of the Ethernet Controller and describe the function of each. The Ethernet LED signals are alternate functions for GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the LED signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the LED function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. June 18, 2012 511 Texas Instruments-Production Data Ethernet Controller Table 14-1. Ethernet Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description ERBIAS 41 I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY. RXIN 37 I Analog RXIN of the Ethernet PHY. RXIP 40 I Analog RXIP of the Ethernet PHY. TXON 46 O Analog TXON of the Ethernet PHY. TXOP 43 O Analog TXOP of the Ethernet PHY. VCCPHY 36 83 84 - Power VCC of the Ethernet PHY. XTALNPHY 17 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY 16 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 14-2. Ethernet Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description ERBIAS K3 I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. GNDPHY C8 C9 K4 - Power GND of the Ethernet PHY. LED0 J12 O TTL Ethernet LED 0. LED1 J11 O TTL Ethernet LED 1. MDIO L9 I/O TTL MDIO of the Ethernet PHY. RXIN L7 I Analog RXIN of the Ethernet PHY. RXIP M7 I Analog RXIP of the Ethernet PHY. TXON L8 O Analog TXON of the Ethernet PHY. TXOP M8 O Analog TXOP of the Ethernet PHY. VCCPHY C10 D10 D11 - Power VCC of the Ethernet PHY. XTALNPHY J1 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY J2 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 512 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 14.3 Functional Description Note: A 12.4-k resistor should be connected between the ERBIAS and ground. The 12.4-k resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used. The functional description of the Ethernet Controller is discussed in the following sections. 14.3.1 MAC Operation The following sections decribe the operation of the MAC unit, including an overview of the Ethernet frame format, the MAC layer FIFOs, Ethernet transmission and reception options, packet timestamps, and LED indicators. 14.3.1.1 Ethernet Frame Format Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure 14-3 on page 513. Figure 14-3. Ethernet Frame Preamble 7 Bytes SFD Destination Address 1 Byte 6 Bytes Source Address Length/ Type Data FCS 6 Bytes 2 Bytes 46 - 1500 Bytes 4 Bytes The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. Preamble The Preamble field is used to synchronize with the received frame's timing. The preamble is 7 octets long. Start Frame Delimiter (SFD) The SFD field follows the preamble pattern and indicates the start of the frame. Its value is 1010.1011. Destination Address (DA) This field specifies destination addresses for which the frame is intended. The LSB (bit 16 of DA oct 1 in the frame, see Table 14-3 on page 515) of the DA determines whether the address is an individual (0), or group/multicast (1) address. Source Address (SA) The source address field identifies the station from which the frame was initiated. Length/Type Field The meaning of this field depends on its numeric value. This field can be interpreted as length or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified by the IEEE 802.3 standard. However, the Ethernet Controller assumes type interpretation if the June 18, 2012 513 Texas Instruments-Production Data Ethernet Controller value of the Length/Type field is greater than 1500 decimal. The definition of the Type field is specified in the IEEE 802.3 standard. The first of the two octets in this field is most significant. Data The data field is a sequence of octets that is at least 46 in length, up to 1500 in length. Full data transparency is provided so any values can appear in this field. A minimum frame size of 46 octets is required to meet the IEEE standard. If the frame size is too small, the Ethernet Controller automatically appends extra bits (a pad), thus the pad can have a size of 0 to 46 octets. Data padding can be disabled by clearing the PADEN bit in the Ethernet MAC Transmit Control (MACTCTL) register. For the Ethernet Controller, data sent/received can be larger than 1500 bytes without causing a Frame Too Long error. Instead, a FIFO overrun error is reported using the FOV bit in the Ethernet MAC Raw Interrupt Status(MACRIS) register when the frame received is too large to fit into the Ethernet Controller's 2K RAM. Frame Check Sequence (FCS) The frame check sequence carries the cyclic redundancy check (CRC) value. The CRC is computed over the destination address, source address, length/type, and data (including pad) fields using the CRC-32 algorithm. The Ethernet Controller computes the FCS value one nibble at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by clearing the CRC bit in the MACTCTL register. For received frames, this field is automatically checked. If the FCS does not pass, the frame is not placed in the RX FIFO, unless the FCS check is disabled by clearing the BADCRC bit in the MACRCTL register. 14.3.1.2 MAC Layer FIFOs The Ethernet Controller is capable of simultaneous transmission and reception. This feature is enabled by setting the DUPLEX bit in the MACTCTL register. For Ethernet frame transmission, a 2 KB transmit FIFO is provided that can be used to store a single frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to 1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload of up to 2032 bytes (as the first 16 bytes in the FIFO are reserved for destination address, source address and length/type information). For Ethernet frame reception, a 2-KB receive FIFO is provided that can be used to store multiple frames, up to a maximum of 31 frames. If a frame is received, and there is insufficient space in the RX FIFO, an overflow error is indicated using the FOV bit in the MACRIS register. For details regarding the TX and RX FIFO layout, refer to Table 14-3 on page 515. Please note the following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions. For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including the Length/Type bytes and the FCS bits. If FCS generation is disabled by clearing the CRC bit in the MACTCTL register, the last word in the TX FIFO must contain the FCS bytes for the frame that has been written to the FIFO. Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not be aligned on a word boundary in the FIFO. However, for the RX FIFO the beginning of the next frame is always on a word boundary. 514 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 14-3. TX & RX FIFO Organization FIFO Word Read/Write Sequence Word Bit Fields TX FIFO (Write) 1st 7:0 Data Length Least Significant Frame Length Least Byte Significant Byte 15:8 Data Length Most Significant Frame Length Most Significant Byte Byte 23:16 DA oct 1 31:24 DA oct 2 7:0 DA oct 3 15:8 DA oct 4 23:16 DA oct 5 31:24 DA oct 6 7:0 SA oct 1 15:8 SA oct 2 23:16 SA oct 3 31:24 SA oct 4 7:0 SA oct 5 15:8 SA oct 6 23:16 Len/Type Most Significant Byte 31:24 Len/Type Least Significant Byte 2nd 3rd 4th 5th to nth last Note: 14.3.1.3 RX FIFO (Read) 7:0 data oct n 15:8 data oct n+1 23:16 data oct n+2 31:24 data oct n+3 7:0 FCS 1 15:8 FCS 2 23:16 FCS 3 31:24 FCS 4 If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the correct CRC. If the CRC bit is set, the Ethernet Controller automatically writes the FCS bytes. Ethernet Transmission Options At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the DUPLEX bit in the MACTCTL register. The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing the CRC bit. The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is set. This feature can be disabled by clearing the PADEN bit. The transmitter must be enabled by setting the TXEN bit in the TCTL register. June 18, 2012 515 Texas Instruments-Production Data Ethernet Controller 14.3.1.4 Ethernet Reception Options The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL) register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register. The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case, a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the BADCRC bit in the MACRCTL register. In normal operating mode, the receiver accepts only those frames that have a destination address that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0) and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the MACRCTL register. 14.3.1.5 Packet Timestamps For applications requiring very high-precision synchronization packets, the Ethernet Controller provides a means of generating precision timestamps in support of the IEEE Precision Time Protocol (IEEE-1588). This feature is enabled by setting the TSEN bit in the Ethernet MAC Timer Support (MATCS) register. Note that when this feature is enabled, General-Purpose Timer 3 (GPT3) must be dedicated to the Ethernet Controller. GPT3 must be configured to 16-bit edge capture mode, see page 345. Timer A of GPT3 stores the transmit time, and Timer B stores the receive time. One other General-Purpose Timer can be set up as a 16-bit free-running timer to synchronize the receiver and transmitter timers and provide a timestamp with which to compare the timestamps stored in GPT3. 14.3.2 Internal MII Operation For the MII management interface to function properly, the MDIO signal must be connected through a 10k pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents management transactions on this internal MII to function. Note that it is possible for data transmission across the MII to still function since the PHY layer auto-negotiates the link parameters by default. For the MII management interface to function properly, the internal clock must be divided down from the system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider (MACMDV) register contains the divider used for scaling down the system clock. See page 535 for more details about the use of this register. 14.3.3 PHY Operation The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external filter is required. 14.3.3.1 Clock Selection The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY 516 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground. 14.3.3.2 Auto-Negotiation The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function is controlled via register settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller's link partner during auto-negotiation via fast-link pulse coding. Once auto-negotiation is complete, the DPLX and RATE bits in the Ethernet PHY Management Register 18 - Diagnostic (MR18) register reflect the actual speed and duplex condition. If auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Setting the RANEG bit in the MR0 register also causes auto-negotiation to restart. 14.3.3.3 Polarity Correction The Ethernet Controller is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the Ethernet PHY Management Register 16 - Vendor-Specific (MR16) control this feature. The default is automatic mode, where APOL is clear and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter manual mode, APOL should be set. In manual mode RVSPOL controls the signal polarity. 14.3.3.4 MDI/MDI-X Configuration The Ethernet Controller supports the MDI/MDI-X configuration as defined in IEEE 802.3-2002 specification. The MDI/MDI-X configuration eliminates the need for cross-over cables when connecting to another device, such as a hub. The algorithm is controlled via settings in the Ethernet PHY Management Register 24 - MDI/MIDIX Control (MR24). Refer to page 558 for additional details about these settings. 14.3.3.5 Power Management The PHY has two power-saving modes: Power-Down Receive Power Management Power-down mode is activated by setting the PWRDN bit in the MR0 register. When the PHY is in power-down mode, it consumes minimum power. While in the power-down state, the Ethernet Controller still responds to management transactions. Receive power management (RXCC mode) is activated by setting the RXCC bit in the MR16 register. In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all other receive circuitry are powered down. As soon as a valid signal is detected, all circuits are automatically powered up to resume normal operation. Note that the RXCC mode is not supported during 10BASE-T operation. June 18, 2012 517 Texas Instruments-Production Data Ethernet Controller 14.3.3.6 LED Indicators The Ethernet Controller supports two LED signals that can be used to indicate various states of operation. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfigured to their alternate function. See "General-Purpose Input/Outputs (GPIOs)" on page 284 for additional details. The function of these pins is programmable via the PHY layer Ethernet PHY Management Register 23 - LED Configuration (MR23). Refer to page 557 for additional details on how to program these LED functions. 14.3.4 Interrupts The Ethernet Controller can generate an interrupt for one or more of the following conditions: A frame has been received into an empty RX FIFO A frame transmission error has occurred A frame has been transmitted successfully A frame has been received with inadequate room in the RX FIFO (overrun) A frame has been received with one or more error conditions (for example, FCS failed) An MII management transaction between the MAC and PHY layers has completed One or more of the following PHY layer conditions occurs: - Auto-Negotiate Complete - Remote Fault - Link Status Change - Link Partner Acknowledge - Parallel Detect Fault - Page Received - Receive Error - Jabber Event Detected 14.4 Initialization and Configuration The following sections describe the hardware and software configuration required to set up the Ethernet Controller. 14.4.1 Hardware Configuration Figure 14-4 on page 519 shows the proper method for interfacing the Ethernet Controller to a 10/100BASE-T Ethernet jack. 518 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 14-4. Interface to an Ethernet Jack Stellaris Microcontroller PF2/LED1 PF3/LED0 MDIO TXOP 60 59 PF2/LED1 PF3/LED0 +3.3V 10/100BASE-T Ethernet Jack P2 58 R3 +3.3V +3.3V R4 49.9 10K R5 49.9 C2 10pF C3 10pF 43 12 11 R6 330 C4 3 G+ G- 1CT: 1 +3.3V TX+ 1 TX- 2 5 TXON RXIP 0.1UF 46 RX+ 3 4 4 7 40 C5 5 RX- 6 1CT: 1 +3.3V 7 6 8 RXIN 0.1UF 37 +3.3V R8 49.9 R9 49.9 C6 10pF C7 10pF R7 8 +3.3V 2 1 Y- 9 10 NC 330 Y+ GND J3011G21DNL GL GR C13 0.01UF The following isolation transformers have been tested and are known to successfully interface to the Ethernet PHY layer. Isolation Transformers - TDK TLA-6T103 - Bel-Fuse S558-5999-46 - Halo TG22-3506ND - Pulse PE-68515 - Valor ST6118 - YCL 20PMT04 Isolation transformers in low profile packages (0.100 in/2.5 mm or less) - TDK TLA-6T118 - Halo TG110-S050 - PCA EPF8023G Isolation transformers with integrated RJ45 connector - TDK TLA-6T704 - Delta RJS-1A08T089A Isolation transformers with integrated RJ45 connector, LEDs and termination resistors - Pulse J0011D21B/E - Pulse J3011G21DNL 14.4.2 Software Configuration To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the RCGC2 register (see page 227). The following steps can then be used to configure the Ethernet Controller for basic operation. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a 20-MHz system clock, the MACDIV value should be 0x03 or greater. 2. Program the MACIA0 and MACIA1 register for address filtering. 3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16. June 18, 2012 519 Texas Instruments-Production Data Ethernet Controller 4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using a value of 0x18. 5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA) register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available for the next transmit frame. 7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP) register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare the number of bytes received to the Length field from the frame to determine when the packet has been completely read. 14.5 Ethernet Register Map Table 14-4 on page 520 lists the Ethernet MAC registers. All addresses given are relative to the Ethernet MAC base address of 0x4004.8000. Note that the Ethernet module clock must be enabled before the registers can be programmed (see page 227). There must be a delay of 3 system clocks after the Ethernet module clock is enabled before any Ethernet module registers are accessed. The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. Table 14-4 on page 520 also lists these MII Management registers. All addresses given are absolute and are written directly to the REGADR field of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY layer implementations. The only variance allowed is for features that may or may not be supported by a specific PHY implementation. Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendor's PHY implementation. Vendor-specific registers not listed are reserved. Table 14-4. Ethernet Register Map Offset Name Description See page Type Reset R/W1C 0x0000.0000 Ethernet MAC Raw Interrupt Status/Acknowledge 522 Ethernet MAC 0x000 MACRIS/MACIACK 0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 525 0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 526 0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 527 0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 528 0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 530 0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 531 0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 532 0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 534 520 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 14-4. Ethernet Register Map (continued) Description See page Offset Name Type Reset 0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 535 0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 536 0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 537 0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 538 0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 539 0x03C MACTS R/W 0x0000.0000 Ethernet MAC Timer Support 540 MII Management - MR0 R/W 0x3100 Ethernet PHY Management Register 0 - Control 541 - MR1 RO 0x7849 Ethernet PHY Management Register 1 - Status 543 - MR2 RO 0x000E Ethernet PHY Management Register 2 - PHY Identifier 1 545 - MR3 RO 0x7237 Ethernet PHY Management Register 3 - PHY Identifier 2 546 - MR4 R/W 0x01E1 Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement 547 - MR5 RO 0x0000 Ethernet PHY Management Register 5 - Auto-Negotiation Link Partner Base Page Ability 549 - MR6 RO 0x0000 Ethernet PHY Management Register 6 - Auto-Negotiation Expansion 550 - MR16 R/W 0x0140 Ethernet PHY Management Register 16 - Vendor-Specific 551 - MR17 R/W 0x0000 Ethernet PHY Management Register 17 - Interrupt Control/Status 553 - MR18 RO 0x0000 Ethernet PHY Management Register 18 - Diagnostic 555 - MR19 R/W 0x4000 Ethernet PHY Management Register 19 - Transceiver Control 556 - MR23 R/W 0x0010 Ethernet PHY Management Register 23 - LED Configuration 557 - MR24 R/W 0x00C0 Ethernet PHY Management Register 24 -MDI/MDIX Control 558 14.6 Ethernet MAC Register Descriptions The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. Also see "MII Management Register Descriptions" on page 540. June 18, 2012 521 Texas Instruments-Production Data Ethernet Controller Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. On a write, setting any bit clears the corresponding interrupt status bit. Reads Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Base 0x4004.8000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 PHYINT RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY Interrupt When set, indicates that an enabled interrupt in the PHY layer has occurred. MR17 in the PHY must be read to determine the specific PHY event that triggered this interrupt. 5 MDINT RO 0 MII Transaction Complete When set, indicates that a transaction (read or write) on the MII interface has completed successfully. 4 RXER RO 0 Receive Error This bit indicates that an error was encountered on the receiver. The possible errors that can cause this interrupt bit to be set are: 3 FOV RO 0 A receive error occurs during the reception of a frame (100 Mb/s only). The frame is not an integer number of bytes (dribble bits) due to an alignment error. The CRC of the frame does not pass the FCS check. The length/type field is inconsistent with the frame data size when interpreted as a length field. FIFO Overrun When set, indicates that an overrun was encountered on the receive FIFO. 522 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 2 TXEMP RO 0 Description Transmit FIFO Empty When set, indicates that the packet was transmitted and that the TX FIFO is empty. 1 TXER RO 0 Transmit Error When set, indicates that an error was encountered on the transmitter. The possible errors that can cause this interrupt bit to be set are: 0 RXINT RO 0 The data length field stored in the TX FIFO exceeds 2032 decimal (buffer length - 16 bytes of header data). The frame is not sent when this error occurs. The retransmission attempts during the backoff process have exceeded the maximum limit of 16 decimal. Packet Received When set, indicates that at least one packet has been received and is stored in the receiver FIFO. Writes Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Base 0x4004.8000 Offset 0x000 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 PHYINT W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear PHY Interrupt Setting this bit clears the PHYINT interrupt in the MACRIS register. 5 MDINT W1C 0 Clear MII Transaction Complete Setting this bit clears the MDINT interrupt in the MACRIS register. 4 RXER W1C 0 Clear Receive Error Setting this bit clears the RXER interrupt in the MACRIS register. 3 FOV W1C 0 Clear FIFO Overrun Setting this bit clears the FOV interrupt in the MACRIS register. June 18, 2012 523 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 2 TXEMP W1C 0 Description Clear Transmit FIFO Empty Setting this bit clears the TXEMP interrupt in the MACRIS register. 1 TXER W1C 0 Clear Transmit Error Setting this bit clears the TXER interrupt in the MACRIS register and resets the TX FIFO write pointer. 0 RXINT W1C 0 Clear Packet Received Setting this bit clears the RXINT interrupt in the MACRIS register. 524 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the interrupt, while setting the bit enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.007F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RXERM FOVM TXEMPM TXERM RXINTM RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset reserved Type Reset PHYINTM MDINTM RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 PHYINTM R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Mask PHY Interrupt Clearing this bit masks the PHYINT bit in the MACRIS register from being set. 5 MDINTM R/W 1 Mask MII Transaction Complete Clearing this bit masks the MDINT bit in the MACRIS register from being set. 4 RXERM R/W 1 Mask Receive Error Clearing this bit masks the RXER bit in the MACRIS register from being set. 3 FOVM R/W 1 Mask FIFO Overrun Clearing this bit masks the FOV bit in the MACRIS register from being set. 2 TXEMPM R/W 1 Mask Transmit FIFO Empty Clearing this bit masks the TXEMP bit in the MACRIS register from being set. 1 TXERM R/W 1 Mask Transmit Error Clearing this bit masks the TXER bit in the MACRIS register from being set. 0 RXINTM R/W 1 Mask Packet Received Clearing this bit masks the RXINT bit in the MACRIS register from being set. June 18, 2012 525 Texas Instruments-Production Data Ethernet Controller Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register configures the receiver and controls the types of frames that are received. It is important to note that when the receiver is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.8000 Offset 0x008 Type R/W, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RSTFIFO BADCRC RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 RSTFIFO R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 2 1 0 PRMS AMUL RXEN R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear Receive FIFO When set, this bit clears the receive FIFO. This should be done when software initialization is performed. It is recommended that the receiver be disabled (RXEN = 0), before a reset is initiated (RSTFIFO = 1). This sequence flushes and resets the RX FIFO. This bit is automatically cleared when read. 3 BADCRC R/W 1 Enable Reject Bad CRC When set, the BADCRC bit enables the rejection of frames with an incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit in the MACRIS register is set and the receiver FIFO is reset. 2 PRMS R/W 0 Enable Promiscuous Mode When set, the PRMS bit enables Promiscuous mode, which accepts all valid frames, regardless of the specified Destination Address. 1 AMUL R/W 0 Enable Multicast Frames When set, the AMUL bit enables the reception of multicast frames. 0 RXEN R/W 0 Enable Receiver When set the RXEN bit enables the Ethernet receiver. When this bit is clear, the receiver is disabled and all frames are ignored. 526 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register configures the transmitter and controls the frames that are transmitted. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 DUPLEX reserved CRC PADEN TXEN RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 DUPLEX R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Duplex Mode When set, this bit enables Duplex mode, allowing simultaneous transmission and reception. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 CRC R/W 0 Enable CRC Generation When set this bit enables the automatic generation of the CRC and its placement at the end of the packet. If this bit is clear, the frames placed in the TX FIFO are sent exactly as they are written into the FIFO. Note that this bit should generally be set. 1 PADEN R/W 0 Enable Packet Padding When set, this bit enables the automatic padding of packets that do not meet the minimum frame size. Note that this bit should generally be set. 0 TXEN R/W 0 Enable Transmitter When set, this bit enables the transmitter. When this bit is clear, the transmitter is disabled. June 18, 2012 527 Texas Instruments-Production Data Ethernet Controller Register 5: Ethernet MAC Data (MACDATA), offset 0x010 Important: This register is read-sensitive. See the register description for details. This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. The read pointer is then auto incremented to the next RX FIFO location. Reading from the RX FIFO when a frame has not been received or is in the process of being received will return indeterminate data and not increment the read pointer. Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is the auto incremented to the next TX FIFO location. Writing more data into the TX FIFO than indicated in the length field will result in the data being lost. Writing less data into the TX FIFO than indicated in the length field will result in indeterminate data being appended to the end of the frame to achieve the indicated length. Attempting to write the next frame into the TX FIFO before transmission of the first has completed will result in the data being lost. There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written. Reads Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RXDATA Type Reset RXDATA Type Reset Bit/Field Name Type 31:0 RXDATA RO Reset Description 0x0000.0000 Receive FIFO Data The RXDATA bits represent the next word of data stored in the RX FIFO. 528 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Writes Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 TXDATA Type Reset TXDATA Type Reset Bit/Field Name Type 31:0 TXDATA WO Reset Description 0x0000.0000 Transmit FIFO Data The TXDATA bits represent the next word of data to place in the TX FIFO for transmission. June 18, 2012 529 Texas Instruments-Production Data Ethernet Controller Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte Individual Address is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 R/W 0 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MACOCT4 Type Reset 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 MACOCT3 MACOCT2 Type Reset 19 MACOCT1 R/W 0 Bit/Field Name Type Reset Description 31:24 MACOCT4 R/W 0x00 MAC Address Octet 4 R/W 0 The MACOCT4 bits represent the fourth octet of the MAC address used to uniquely identify the Ethernet Controller. 23:16 MACOCT3 R/W 0x00 MAC Address Octet 3 The MACOCT3 bits represent the third octet of the MAC address used to uniquely identify the Ethernet Controller. 15:8 MACOCT2 R/W 0x00 MAC Address Octet 2 The MACOCT2 bits represent the second octet of the MAC address used to uniquely identify the Ethernet Controller. 7:0 MACOCT1 R/W 0x00 MAC Address Octet 1 The MACOCT1 bits represent the first octet of the MAC address used to uniquely identify the Ethernet Controller. 530 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.8000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset MACOCT6 Type Reset MACOCT5 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:8 MACOCT6 R/W 0x00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address Octet 6 The MACOCT6 bits represent the sixth octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT5 R/W 0x00 MAC Address Octet 5 The MACOCT5 bits represent the fifth octet of the MAC address used to uniquely identify the Ethernet Controller. June 18, 2012 531 Texas Instruments-Production Data Ethernet Controller Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C In order to increase the transmission rate, it is possible to program the Ethernet Controller to begin transmission of the next frame prior to the completion of the transmission of the current frame. Note: Extreme care must be used when implementing this function. Software must be able to guarantee that the complete frame is able to be stored in the transmission FIFO prior to the completion of the transmission frame. This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature is disabled, and transmission does not start until the NEWTX bit is set in the MACTR register. Writing the THRESH bits to any value besides 0x3F enables the early transmission feature. Once the byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown below, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02 makes the wait equal to 68 bytes of written data. In general, early transmission starts when: Number of Bytes >= 4 (THRESH x 8 + 1) Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins and then the number of bytes indicated by the Data Length field is transmitted. Because under-run checking is not performed, if any event, such as an interrupt, delays the filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO. In this event, indeterminate values are transmitted rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software. If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must be set with an explicit write. This initiates the transmission of the frame even though the threshold limit has not been reached. If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the MACRIS is not set meaning that the CPU receives no indication that a transmit error happened. Ethernet MAC Threshold (MACTHR) Base 0x4004.8000 Offset 0x01C Type R/W, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 THRESH RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 532 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset Description 5:0 THRESH R/W 0x3F Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds the value represented by the above equation, transmission of the packet begins. June 18, 2012 533 Texas Instruments-Production Data Ethernet Controller Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional description of each of these registers can be found in Table 14-4 on page 520 and in "MII Management Register Descriptions" on page 540. In order to initiate a read transaction from the MII Management registers, the WRITE bit must be cleared during the same cycle that the START bit is set. In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set during the same cycle that the START bit is set. Ethernet MAC Management Control (MACMCTL) Base 0x4004.8000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 reserved WRITE START RO 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset REGADR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:3 REGADR R/W 0x0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Address The REGADR bit field represents the MII Management register address for the next MII management interface transaction. Refer to Table 14-4 on page 520 for the PHY register offsets. Note that any address that is not valid in the register map should not be written to and any data read should be ignored. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 WRITE R/W 0 MII Register Transaction Type The WRITE bit represents the operation of the next MII management interface transaction. If WRITE is set, the next operation is a write; if WRITE is clear, the next transaction is a read. 0 START R/W 0 MII Register Transaction Enable The START bit represents the initiation of the next MII management interface transaction. When this bit is set, the MII register located at REGADR is read (WRITE=0) or written (WRITE=1). 534 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions between the system and the MII Management registers. The frequency of the MDC clock can be calculated from the following formula: The clock divider must be written with a value that ensures that the MDC clock does not exceed a frequency of 2.5 MHz. Ethernet MAC Management Divider (MACMDV) Base 0x4004.8000 Offset 0x024 Type R/W, reset 0x0000.0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIV RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DIV R/W 0x80 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Divider The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the MAC and PHY layers over the serial MII interface. June 18, 2012 535 Texas Instruments-Production Data Ethernet Controller Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 MDTX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MDTX R/W 0x0000 MII Register Transmit Data The MDTX bits represent the data that will be written in the next MII management transaction. 536 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 MDRX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MDRX R/W 0x0000 MII Register Receive Data The MDRX bits represent the data that was read in the previous MII management transaction. June 18, 2012 537 Texas Instruments-Production Data Ethernet Controller Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO, and the RXINT bit is clear. When NPR is any other value, at least one frame is in the RX FIFO, and the RXINT bit in the MACRIS register is set. Note: The FCS bytes are not included in the NPR value. As a result, the NPR value could be zero before the FCS bytes are read from the FIFO. In addition, a new packet could be received before the NPR value reaches zero. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare the number of bytes received to the Length field from the frame to determine when the packet has been completely read. Ethernet MAC Number of Packets (MACNP) Base 0x4004.8000 Offset 0x034 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 NPR RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 NPR RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of Packets in Receive FIFO The NPR bits represent the number of packets stored in the RX FIFO. While the NPR field is greater than 0, the RXINT interrupt in the MACRIS register is set. 538 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been encountered, the NEWTX bit is automatically cleared. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 NEWTX R/W 0 RO 0 NEWTX R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Transmission When set, the NEWTX bit initiates an Ethernet transmission once the packet has been placed in the TX FIFO. This bit is cleared once the transmission has been completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set. June 18, 2012 539 Texas Instruments-Production Data Ethernet Controller Register 15: Ethernet MAC Timer Support (MACTS), offset 0x03C This register enables software to enable highly precise timing on the transmission and reception of frames. To enable this function, set the TSEN bit. Ethernet MAC Timer Support (MACTS) Base 0x4004.8000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 TSEN R/W 0 RO 0 TSEN R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Time Stamp Enable When set, the TSEN bit multiplexes the TX and RX interrupts to the CCP inputs of General-Purpose Timer 3. 14.7 MII Management Register Descriptions The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers. All addresses given are absolute. Addresses not listed are reserved; these addresses should not be written to and any data read should be ignored. Also see "Ethernet MAC Register Descriptions" on page 521. 540 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: Ethernet PHY Management Register 0 - Control (MR0), address 0x00 This register enables software to configure the operation of the PHY layer. The default settings of these registers are designed to initialize the Ethernet Controller to a normal operational mode without configuration. Ethernet PHY Management Register 0 - Control (MR0) Base 0x4004.8000 Address 0x00 Type R/W, reset 0x3100 15 RESET Type Reset R/W 0 14 13 12 11 LOOPBK SPEEDSL ANEGEN PWRDN R/W 0 R/W 1 R/W 1 R/W 0 10 9 8 7 ISO RANEG DUPLEX COLT R/W 0 R/W 0 R/W 1 R/W 0 Bit/Field Name Type Reset 15 RESET R/W 0 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 R/W 0 Description Reset Registers When set, this bit resets the PHY layer registers to their default state and reinitializes internal state machines. Once the reset operation has completed, this bit is cleared by hardware. 14 LOOPBK R/W 0 Loopback Mode When set, this bit enables the Loopback mode of operation. The receiver ignores external inputs and receives the data that is transmitted by the transmitter. 13 SPEEDSL R/W 1 Speed Select Value Description 12 ANEGEN R/W 1 1 Enables the 100 Mb/s mode of operation (100BASE-TX). 0 Enables the 10 Mb/s mode of operation (10BASE-T). Auto-Negotiation Enable When set, this bit enables the auto-negotiation process. 11 PWRDN R/W 0 Power Down When set, this bit places the PHY layer into a low-power consuming state. All data on the data inputs is ignored. 10 ISO R/W 0 Isolate When set, this bit isolates the transmit and receive data paths and ignores all data being transmitted and received. 9 RANEG R/W 0 Restart Auto-Negotiation When set, this bit restarts the auto-negotiation process. Once the restart has initiated, this bit is cleared by hardware. June 18, 2012 541 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 8 DUPLEX R/W 1 Description Set Duplex Mode Value Description 7 COLT R/W 0 1 Enables the Full-Duplex mode of operation. This bit can be set by software in a manual configuration process or by the auto-negotiation process. 0 Enables the Half-Duplex mode of operation. Collision Test When set, this bit enables the Collision Test mode of operation. The COLT bit is set after the initiation of a transmission and is cleared once the transmission is halted. 6:0 reserved R/W 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. These bits should always be written as zero. 542 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 17: Ethernet PHY Management Register 1 - Status (MR1), address 0x01 This register enables software to determine the capabilities of the PHY layer and perform its initialization and operation appropriately. Ethernet PHY Management Register 1 - Status (MR1) Base 0x4004.8000 Address 0x01 Type RO, reset 0x7849 Type Reset 15 14 13 12 11 reserved 100X_F 100X_H 10T_F 10T_H 10 RO 0 RO 1 RO 1 RO 1 RO 1 9 8 7 reserved RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 MFPS ANEGC RFAULT ANEGA LINK JAB EXTD RO 1 RO 0 RC 0 RO 1 RO 0 RC 0 RO 1 Bit/Field Name Type Reset Description 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 100X_F RO 1 100BASE-TX Full-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of supporting 100BASE-TX Full-Duplex mode. 13 100X_H RO 1 100BASE-TX Half-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of supporting 100BASE-TX Half-Duplex mode. 12 10T_F RO 1 10BASE-T Full-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of 10BASE-T Full-Duplex mode. 11 10T_H RO 1 10BASE-T Half-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of supporting 10BASE-T Half-Duplex mode. 10:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 MFPS RO 1 Management Frames with Preamble Suppressed When set, this bit indicates that the Management Interface is capable of receiving management frames with the preamble suppressed. 5 ANEGC RO 0 Auto-Negotiation Complete When set, this bit indicates that the auto-negotiation process has been completed and that the extended registers defined by the auto-negotiation protocol are valid. 4 RFAULT RC 0 Remote Fault When set, this bit indicates that a remote fault condition has been detected. This bit remains set until it is read, even if the condition no longer exists. 3 ANEGA RO 1 Auto-Negotiation When set, this bit indicates that the Ethernet Controller has the ability to perform auto-negotiation. June 18, 2012 543 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset Description 2 LINK RO 0 Link Made When set, this bit indicates that a valid link has been established by the Ethernet Controller. 1 JAB RC 0 Jabber Condition When set, this bit indicates that a jabber condition has been detected by the Ethernet Controller. This bit remains set until it is read, even if the jabber condition no longer exists. 0 EXTD RO 1 Extended Capabilities When set, this bit indicates that the Ethernet Controller provides an extended set of capabilities that can be accessed through the extended register set. 544 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 18: Ethernet PHY Management Register 2 - PHY Identifier 1 (MR2), address 0x02 This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 2 - PHY Identifier 1 (MR2) Base 0x4004.8000 Address 0x02 Type RO, reset 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 0 OUI[21:6] Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15:0 OUI[21:6] RO 0x000E RO 0 Description Organizationally Unique Identifier[21:6] This field, along with the OUI[5:0] field in MR3, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. June 18, 2012 545 Texas Instruments-Production Data Ethernet Controller Register 19: Ethernet PHY Management Register 3 - PHY Identifier 2 (MR3), address 0x03 This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 3 - PHY Identifier 2 (MR3) Base 0x4004.8000 Address 0x03 Type RO, reset 0x7237 15 14 13 12 11 10 9 8 7 OUI[5:0] Type Reset RO 0 RO 1 RO 1 RO 1 6 5 4 3 2 MN RO 0 RO 0 RO 1 RO 0 RO 0 1 0 RO 1 RO 1 RN RO 0 RO 1 RO 1 Bit/Field Name Type Reset Description 15:10 OUI[5:0] RO 0x1C Organizationally Unique Identifier[5:0] RO 0 RO 1 This field, along with the OUI[21:6] field in MR2, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 9:4 MN RO 0x23 Model Number The MN field represents the Model Number of the PHY. 3:0 RN RO 0x7 Revision Number The RN field represents the Revision Number of the PHY implementation. 546 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 20: Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement (MR4), address 0x04 This register provides the advertised abilities of the Ethernet Controller used during auto-negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to auto-negotiate to an alternate common technology. Writing to this register has no effect until auto-negotiation is re-initiated by setting the RANEG bit in the MR0 register. Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement (MR4) Base 0x4004.8000 Address 0x04 Type R/W, reset 0x01E1 Type Reset 15 14 13 NP reserved RF 12 RO 0 RO 0 R/W 0 11 10 9 reserved RO 0 RO 0 RO 0 RO 0 8 7 6 5 A3 A2 A1 A0 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 15 NP RO 0 Next Page 4 3 2 1 0 RO 0 RO 1 S RO 0 RO 0 RO 0 When set, this bit indicates the Ethernet Controller is capable of Next Page exchanges to provide more detailed information on the PHY layer's capabilities. 14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 RF R/W 0 Remote Fault When set, this bit indicates to the link partner that a Remote Fault condition has been encountered. 12:9 reserved RO 0x0 8 A3 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Technology Ability Field[3] When set, this bit indicates that the Ethernet Controller supports the 100Base-TX full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register. 7 A2 R/W 1 Technology Ability Field[2] When set, this bit indicates that the Ethernet Controller supports the 100Base-TX half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register. 6 A1 R/W 1 Technology Ability Field[1] When set, this bit indicates that the Ethernet Controller supports the 10BASE-T full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register.. June 18, 2012 547 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 5 A0 R/W 1 Description Technology Ability Field[0] When set, this bit indicates that the Ethernet Controller supports the 10BASE-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register.. 4:0 S RO 0x1 Selector Field The S field encodes 32 possible messages for communicating between Ethernet Controllers. This field is hard-coded to 0x01, indicating that the Stellaris Ethernet Controller is IEEE 802.3 compliant. 548 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 21: Ethernet PHY Management Register 5 - Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 This register provides the advertised abilities of the link partner's Ethernet Controller that are received and stored during auto-negotiation. Ethernet PHY Management Register 5 - Auto-Negotiation Link Partner Base Page Ability (MR5) Base 0x4004.8000 Address 0x05 Type RO, reset 0x0000 Type Reset 15 14 13 NP ACK RF RO 0 RO 0 RO 0 12 11 10 9 8 7 6 5 4 3 A[7:0] RO 0 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 S RO 0 RO 0 Bit/Field Name Type Reset Description 15 NP RO 0 Next Page RO 0 RO 0 RO 0 RO 0 RO 0 When set, this bit indicates that the link partner's Ethernet Controller is capable of Next page exchanges to provide more detailed information on the Ethernet Controller's capabilities. 14 ACK RO 0 Acknowledge When set, this bit indicates that the Ethernet Controller has successfully received the link partner's advertised abilities during auto-negotiation. 13 RF RO 0 Remote Fault Used as a standard transport mechanism for transmitting simple fault information from the link partner. 12:5 A[7:0] RO 0x00 Technology Ability Field The A[7:0] field encodes individual technologies that are supported by the Ethernet Controller. See the MR4 register for definitions. Note that bits 12:9 describe functions that are not implemented on the Stellaris Ethernet Controller. Refer to the IEEE 802.3 standard for definitions. 4:0 S RO 0x00 Selector Field The S field encodes possible messages for communicating between Ethernet Controllers. Value Description 0x00 Reserved 0x01 IEEE Std 802.3 0x02 IEEE Std 802.9 ISLAN-16T 0x03 IEEE Std 802.5 0x04 IEEE Std 1394 0x05-0x1F Reserved June 18, 2012 549 Texas Instruments-Production Data Ethernet Controller Register 22: Ethernet PHY Management Register 6 - Auto-Negotiation Expansion (MR6), address 0x06 This register enables software to determine the auto-negotiation and next page capabilities of the Ethernet Controller and the link partner after auto-negotiation. Ethernet PHY Management Register 6 - Auto-Negotiation Expansion (MR6) Base 0x4004.8000 Address 0x06 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 PDF LPNPA reserved PRX LPANEGA RC 0 RO 0 RO 0 RC 0 RO 0 Bit/Field Name Type Reset Description 15:5 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 PDF RC 0 Parallel Detection Fault When set, this bit indicates that more than one technology has been detected at link up. This bit is cleared when read. 3 LPNPA RO 0 Link Partner is Next Page Able When set, this bit indicates that the link partner is enabled to support next page. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 PRX RC 0 New Page Received When set, this bit indicates that a new page has been received from the link partner and stored. This bit remains set until the register is read. 0 LPANEGA RO 0 Link Partner is Auto-Negotiation Able When set, this bit indicates that the link partner is enabled to support auto-negotiation. 550 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 23: Ethernet PHY Management Register 16 - Vendor-Specific (MR16), address 0x10 This register enables software to configure the operation of vendor-specific modes of the Ethernet Controller. Ethernet PHY Management Register 16 - Vendor-Specific (MR16) Base 0x4004.8000 Address 0x10 Type R/W, reset 0x0140 Type Reset 15 14 13 12 11 10 RPTR INPOL reserved TXHIM SQEI NL10 R/W 0 R/W0 0 RO 0 R/W 0 R/W 0 R/W 0 9 8 7 6 reserved RO 0 Bit/Field Name Type Reset 15 RPTR R/W 0 RO 1 RO 0 RO 1 5 4 APOL RVSPOL R/W 0 R/W 0 3 2 reserved RO 0 RO 0 1 0 PCSBP RXCC R/W 0 R/W 0 Description Repeater Mode When set, this bit enables the repeater mode of operation. In this mode, full-duplex is not allowed and the Carrier Sense signal only responds to receive activity. 14 INPOL R/W0 0 Interrupt Polarity Value Description 1 Sets the polarity of the PHY interrupt to be active High. 0 Sets the polarity of the PHY interrupt to active Low. Important: Because the Media Access Controller expects active Low interrupts from the PHY, this bit must always be written with a 0 to ensure proper operation. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 TXHIM R/W 0 Transmit High Impedance Mode When set, this bit enables the transmitter High Impedance mode. In this mode, the TXOP and TXON transmitter pins are put into a high impedance state. The RXIP and RXIN pins remain fully functional. 11 SQEI R/W 0 SQE Inhibit Testing When set, this bit prohibits 10BASE-T SQE testing. When clear, the SQE testing is performed by generating a collision pulse following the completion of the transmission of a frame. 10 NL10 R/W 0 Natural Loopback Mode When set, this bit enables the 10BASE-T Natural Loopback mode. In this mode, the transmission data received by the Ethernet Controller is looped back onto the receive data path when 10BASE-T mode is enabled. 9:6 reserved RO 0x5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 551 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 5 APOL R/W 0 Description Auto-Polarity Disable When set, this bit disables the Ethernet Controller's auto-polarity function. If this bit is clear, the Ethernet Controller automatically inverts the received signal due to a wrong polarity connection during auto-negotiation when in 10BASE-T mode. 4 RVSPOL R/W 0 Receive Data Polarity This bit indicates whether the receive data pulses are being inverted. If the APOL bit is 0, then the RVSPOL bit is read-only and indicates whether the auto-polarity circuitry is reversing the polarity. In this case, if RVSPOL is set, it indicates that the receive data is inverted; if RVSPOL is clear, it indicates that the receive data is not inverted. If the APOL bit is 1, then the RVSPOL bit is writable and software can force the receive data to be inverted. Setting RVSPOL to 1 forces the receive data to be inverted; clearing RVSPOL does not invert the receive data. 3:2 reserved RO 0x0 1 PCSBP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PCS Bypass When set, this bit enables the bypass of the PCS and scrambling/descrambling functions in 100BASE-TX mode. This mode is only valid when auto-negotiation is disabled and 100BASE-TX mode is enabled. 0 RXCC R/W 0 Receive Clock Control When set, this bit enables the Receive Clock Control power saving mode if the Ethernet Controller is configured in 100BASE-TX mode. This mode shuts down the receive clock when no data is being received to save power. This mode should not be used when PCSBP is enabled and is automatically disabled when the LOOPBK bit in the MR0 register is set. 552 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 24: Ethernet PHY Management Register 17 - Interrupt Control/Status (MR17), address 0x11 This register provides the means for controlling and observing the events which trigger a PHY layer interrupt in the MACRIS register. This register can also be used in a polling mode via the Media Independent Interface as a means to observe key events within the PHY layer via one register address. Bits 0 through 7 are status bits which are each set based on an event. These bits are cleared after the register is read. Bits 8 through 15 of this register, when set, enable the corresponding bit in the lower byte to signal a PHY layer interrupt in the MACRIS register. Ethernet PHY Management Register 17 - Interrupt Control/Status (MR17) Base 0x4004.8000 Address 0x11 Type R/W, reset 0x0000 15 JABBER_IE Type Reset R/W 0 14 13 RXER_IE PRX_IE R/W 0 12 11 PDF_IE LPACK_IE R/W 0 R/W 0 R/W 0 10 9 8 7 6 LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT R/W 0 R/W 0 Bit/Field Name Type Reset 15 JABBER_IE R/W 0 R/W 0 RC 0 5 4 3 2 PRX_INT PDF_INT LPACK_INT LSCHG_INT RC 0 RC 0 RC 0 RC 0 RC 0 1 0 RFAULT_INT ANEGCOMP_INT RC 0 RC 0 Description Jabber Interrupt Enable When set, this bit enables system interrupts when a Jabber condition is detected by the Ethernet Controller. 14 RXER_IE R/W 0 Receive Error Interrupt Enable When set, this bit enables system interrupts when a receive error is detected by the Ethernet Controller. 13 PRX_IE R/W 0 Page Received Interrupt Enable When set, this bit enables system interrupts when a new page is received by the Ethernet Controller. 12 PDF_IE R/W 0 Parallel Detection Fault Interrupt Enable When set, this bit enables system interrupts when a Parallel Detection Fault is detected by the Ethernet Controller. 11 LPACK_IE R/W 0 LP Acknowledge Interrupt Enable When set, this bit enables system interrupts when FLP bursts are received with the ACK bit in the MR5 register during auto-negotiation. 10 LSCHG_IE R/W 0 Link Status Change Interrupt Enable When set, this bit enables system interrupts when the link status changes from OK to FAIL. 9 RFAULT_IE R/W 0 Remote Fault Interrupt Enable When set, this bit enables system interrupts when a remote fault condition is signaled by the link partner. 8 ANEGCOMP_IE R/W 0 Auto-Negotiation Complete Interrupt Enable When set, this bit enables system interrupts when the auto-negotiation sequence has completed successfully. 7 JABBER_INT RC 0 Jabber Event Interrupt When set, this bit indicates that a Jabber event has been detected by the 10BASE-T circuitry. June 18, 2012 553 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 6 RXER_INT RC 0 Description Receive Error Interrupt When set, this bit indicates that a receive error has been detected by the Ethernet Controller. 5 PRX_INT RC 0 Page Receive Interrupt When set, this bit indicates that a new page has been received from the link partner during auto-negotiation. 4 PDF_INT RC 0 Parallel Detection Fault Interrupt When set, this bit indicates that a parallel detection fault has been detected by the Ethernet Controller during the auto-negotiation process. 3 LPACK_INT RC 0 LP Acknowledge Interrupt When set, this bit indicates that an FLP burst has been received with the ACK bit set in the MR5 register during auto-negotiation. 2 LSCHG_INT RC 0 Link Status Change Interrupt When set, this bit indicates that the link status has changed from OK to FAIL. 1 RFAULT_INT RC 0 Remote Fault Interrupt When set, this bit indicates that a remote fault condition has been signaled by the link partner. 0 ANEGCOMP_INT RC 0 Auto-Negotiation Complete Interrupt When set, this bit indicates that the auto-negotiation sequence has completed successfully. 554 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 25: Ethernet PHY Management Register 18 - Diagnostic (MR18), address 0x12 This register enables software to diagnose the results of the previous auto-negotiation. Ethernet PHY Management Register 18 - Diagnostic (MR18) Base 0x4004.8000 Address 0x12 Type RO, reset 0x0000 15 14 13 reserved Type Reset RO 0 RO 0 12 11 10 9 8 ANEGF DPLX RATE RXSD RX_LOCK RC 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15:13 reserved RO 0x0 12 ANEGF RC 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto-Negotiation Failure When set, this bit indicates that no common technology was found during auto-negotiation and auto-negotiation has failed. This bit remains set until read. 11 DPLX RO 0 Duplex Mode When set, this bit indicates that Full-Duplex was the highest common denominator found during the auto-negotiation process. Otherwise, Half-Duplex was the highest common denominator found. 10 RATE RO 0 Rate When set, this bit indicates that 100BASE-TX was the highest common denominator found during the auto-negotiation process. Otherwise, 10BASE-T was the highest common denominator found. 9 RXSD RO 0 Receive Detection When set, this bit indicates that receive signal detection has occurred (in 100BASE-TX mode) or that Manchester-encoded data has been detected (in 10BASE-T mode). 8 RX_LOCK RO 0 Receive PLL Lock When set, this bit indicates that the Receive PLL has locked onto the receive signal for the selected speed of operation (10BASE-T or 100BASE-TX). 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 555 Texas Instruments-Production Data Ethernet Controller Register 26: Ethernet PHY Management Register 19 - Transceiver Control (MR19), address 0x13 This register enables software to set the gain of the transmit output to compensate for transformer loss. Ethernet PHY Management Register 19 - Transceiver Control (MR19) Base 0x4004.8000 Address 0x13 Type R/W, reset 0x4000 15 14 13 12 11 10 9 8 7 TXO Type Reset R/W 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15:14 TXO R/W 0x1 RO 0 RO 0 Description Transmit Amplitude Selection The TXO field sets the transmit output amplitude to account for transmit transformer insertion loss. Value Description 13:0 reserved RO 0x000 0x0 Gain set for 0.0dB of insertion loss 0x1 Gain set for 0.4dB of insertion loss 0x2 Gain set for 0.8dB of insertion loss 0x3 Gain set for 1.2dB of insertion loss Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 556 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 27: Ethernet PHY Management Register 23 - LED Configuration (MR23), address 0x17 This register enables software to select the source that causes the LED1 and LED0 signals to toggle. Ethernet PHY Management Register 23 - LED Configuration (MR23) Base 0x4004.8000 Address 0x17 Type R/W, reset 0x0010 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 5 4 3 LED1[3:0] RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 2 1 0 LED0[3:0] R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 LED1[3:0] R/W 0x1 LED1 Source The LED1 field selects the source that toggles the LED1 signal. Value Description 3:0 LED0[3:0] R/W 0x0 0x0 Link OK 0x1 RX or TX Activity (Default LED1) 0x2 Reserved 0x3 Reserved 0x4 Reserved 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity LED0 Source The LED0 field selects the source that toggles the LED0 signal. Value Description 0x0 Link OK (Default LED0) 0x1 RX or TX Activity 0x2 Reserved 0x3 Reserved 0x4 Reserved 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity June 18, 2012 557 Texas Instruments-Production Data Ethernet Controller Register 28: Ethernet PHY Management Register 24 -MDI/MDIX Control (MR24), address 0x18 This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities. Ethernet PHY Management Register 24 -MDI/MDIX Control (MR24) Base 0x4004.8000 Address 0x18 Type R/W, reset 0x00C0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 7 6 PD_MODE AUTO_SW RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 5 4 MDIX MDIX_CM R/W 0 RO 0 3 2 1 0 MDIX_SD R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 PD_MODE R/W 1 Parallel Detection Mode When set, enables the Parallel Detection mode and allows auto-switching to work when auto-negotiation is not enabled. 6 AUTO_SW R/W 1 Auto-Switching Enable When set, enables Auto-Switching of the MDI/MDIX mux. 5 MDIX R/W 0 Auto-Switching Configuration When set, indicates that the MDI/MDIX mux is in the crossover (MDIX) configuration. When 0, it indicates that the mux is in the pass-through (MDI) configuration. When the AUTO_SW bit is 1, the MDIX bit is read-only. When the AUTO_SW bit is 0, the MDIX bit is read/write and can be configured manually. 4 MDIX_CM RO 0 Auto-Switching Complete When set, indicates that the auto-switching sequence has completed. If 0, it indicates that the sequence has not completed or that auto-switching is disabled. 3:0 MDIX_SD R/W 0x0 Auto-Switching Seed This field provides the initial seed for the switching algorithm. This seed directly affects the number of attempts [5,4] respectively to write bits [3:0]. A 0 sets the seed to 0x5. 558 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 15 Analog Comparators An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. Note: Not all comparators have the option to drive an output pin. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. (R) The Stellaris Analog Comparators module has the following features: Three independent integrated analog comparators Configurable for output to drive an output pin or generate an interrupt Compare external pin input to external pin input or to internal programmable voltage reference Compare a test voltage against any one of these voltages - An individual external reference voltage - A shared single external reference voltage - A shared internal reference voltage June 18, 2012 559 Texas Instruments-Production Data Analog Comparators 15.1 Block Diagram Figure 15-1. Analog Comparator Module Block Diagram C2- -ve input C2+ +ve input Comparator 2 output C2o +ve input (alternate) ACCTL2 ACSTAT2 interrupt reference input C1- -ve input C1+ +ve input Comparator 1 output C1o +ve input (alternate) ACCTL1 ACSTAT1 interrupt reference input C0- -ve input C0+ +ve input Comparator 0 output C0o +ve input (alternate) ACCTL0 ACSTAT0 interrupt reference input Voltage Ref Interrupt Control ACRIS ACREFCTL internal bus ACMIS ACINTEN interrupt 15.2 Signal Description Table 15-1 on page 560 and Table 15-2 on page 561 list the external signals of the Analog Comparators and describe the function of each. The Analog Comparator output signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the Analog Comparator function. The positive and negative input signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 15-1. Analog Comparators Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description C0+ 90 I Analog Analog comparator 0 positive input. C0- 92 I Analog Analog comparator 0 negative input. C0o 90 O TTL Analog comparator 0 output. 560 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 15-1. Analog Comparators Signals (100LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type Description C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 24 O TTL C2+ 23 I Analog Analog comparator 2 positive input. C2- 22 I Analog Analog comparator 2 negative input. C2o 23 O TTL Analog comparator 1 output. Analog comparator 2 output. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 15-2. Analog Comparators Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type C0+ A7 I Analog Description Analog comparator 0 positive input. C0- A6 I Analog Analog comparator 0 negative input. C0o A7 O TTL C1+ M1 I Analog Analog comparator 1 positive input. Analog comparator 1 negative input. Analog comparator 0 output. C1- B7 I Analog C1o M1 O TTL C2+ M2 I Analog Analog comparator 2 positive input. Analog comparator 2 negative input. C2- L2 I Analog C2o M2 O TTL Analog comparator 1 output. Analog comparator 2 output. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 15.3 Functional Description Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module) for the analog input pin be disabled to prevent excessive current draw from the I/O pads. The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. VIN- < VIN+, VOUT = 1 VIN- > VIN+, VOUT = 0 As shown in Figure 15-2 on page 562, the input source for VIN- is an external input. In addition to an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference. June 18, 2012 561 Texas Instruments-Production Data Analog Comparators Figure 15-2. Structure of Comparator Unit -ve input +ve input 0 output CINV 1 IntGen +ve input (alternate) reference input 2 ACSTAT interrupt internal bus ACCTL A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). Typically, the comparator output is used internally to generate controller interrupts. It may also be used to drive an external pin. Important: The ASRCP bits in the ACCTLn register must be set before using the analog comparators. 15.3.1 Internal Reference Programming The structure of the internal reference is shown in Figure 15-3 on page 562. This is controlled by a single configuration register (ACREFCTL). Table 15-3 on page 562 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. Figure 15-3. Comparator Internal Reference Structure 8R AVDD 8R R R R *** EN 15 14 *** 1 0 Decoder VREF internal reference RNG Table 15-3. Internal Reference Voltage and ACREFCTL Field Values ACREFCTL Register EN Bit Value EN=0 RNG Bit Value RNG=X Output Reference Voltage Based on VREF Field Value 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. 562 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 15-3. Internal Reference Voltage and ACREFCTL Field Values (continued) ACREFCTL Register EN Bit Value RNG Bit Value RNG=0 EN=1 Output Reference Voltage Based on VREF Field Value Total resistance in ladder is 31 R. The range of internal reference in this mode is 0.85-2.448 V. RNG=1 Total resistance in ladder is 23 R. The range of internal reference for this mode is 0-2.152 V. 15.4 Initialization and Configuration The following example shows how to configure an analog comparator to read back its output value from an internal register. 1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register in the System Control module. 2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input. 3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000.030C. 4. Configure comparator 0 to use the internal voltage reference and to not invert the output by writing the ACCTL0 register with the value of 0x0000.040C. 5. Delay for some time. 6. Read the comparator output value by reading the ACSTAT0 register's OVAL value. Change the level of the signal input on C0- to see the OVAL value change. 15.5 Register Map Table 15-4 on page 564 lists the comparator registers. The offset listed is a hexadecimal increment to the register's address, relative to the Analog Comparator base address of 0x4003.C000. Note that the analog comparator module clock must be enabled before the registers can be programmed (see page 218). There must be a delay of 3 system clocks after the ADC module clock is enabled before any ADC module registers are accessed. June 18, 2012 563 Texas Instruments-Production Data Analog Comparators Table 15-4. Analog Comparators Register Map Name Type Reset 0x000 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 565 0x004 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 566 0x008 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 567 0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 568 0x020 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 569 0x024 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 570 0x040 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 569 0x044 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 570 0x060 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 569 0x064 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 570 15.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. 564 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 This register provides a summary of the interrupt status (masked) of the comparator. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x000 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN2 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 IN2 R/W1C 0 Comparator 2 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 1 IN1 R/W1C 0 Comparator 1 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 0 IN0 R/W1C 0 Comparator 0 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. June 18, 2012 565 Texas Instruments-Production Data Analog Comparators Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 This register provides a summary of the interrupt status (raw) of the comparator. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN2 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 IN2 RO 0 Comparator 2 Interrupt Status When set, indicates that an interrupt has been generated by comparator 2. 1 IN1 RO 0 Comparator 1 Interrupt Status When set, indicates that an interrupt has been generated by comparator 1. 0 IN0 RO 0 Comparator 0 Interrupt Status When set, indicates that an interrupt has been generated by comparator 0. 566 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 This register provides the interrupt enable for the comparator. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN2 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 IN2 R/W 0 Comparator 2 Interrupt Enable When set, enables the controller interrupt from the comparator 2 output 1 IN1 R/W 0 Comparator 1 Interrupt Enable When set, enables the controller interrupt from the comparator 1 output. 0 IN0 R/W 0 Comparator 0 Interrupt Enable When set, enables the controller interrupt from the comparator 0 output. June 18, 2012 567 Texas Instruments-Production Data Analog Comparators Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 9 8 EN RNG R/W 0 R/W 0 reserved RO 0 RO 0 RO 0 VREF RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:10 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 EN R/W 0 Resistor Ladder Enable The EN bit specifies whether the resistor ladder is powered on. If 0, the resistor ladder is unpowered. If 1, the resistor ladder is connected to the analog VDD. This bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 8 RNG R/W 0 Resistor Ladder Range The RNG bit specifies the range of the resistor ladder. If 0, the resistor ladder has a total resistance of 31 R. If 1, the resistor ladder has a total resistance of 23 R. 7:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 VREF R/W 0x00 Resistor Ladder Voltage Ref The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 15-3 on page 562 for some output reference voltage examples. 568 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 These registers specify the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OVAL reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 OVAL RO 0 Comparator Output Value The OVAL bit specifies the current output value of the comparator. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 569 Texas Instruments-Production Data Analog Comparators Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 These registers configure the comparator's input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 CINV reserved RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 ASRCP reserved ISLVAL R/W 0 ISEN R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:9 ASRCP R/W 0x00 Analog Source Positive The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: Value Function 0x0 Pin value 0x1 Pin value of C0+ 0x2 Internal voltage reference 0x3 Reserved 8:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 ISLVAL R/W 0 Interrupt Sense Level Value The ISLVAL bit specifies the sense value of the input that generates an interrupt if in Level Sense mode. If 0, an interrupt is generated if the comparator output is Low. Otherwise, an interrupt is generated if the comparator output is High. 570 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 3:2 ISEN R/W 0x0 Description Interrupt Sense The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: Value Function 1 CINV R/W 0 0x0 Level sense, see ISLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Comparator Output Invert The CINV bit conditionally inverts the output of the comparator. If 0, the output of the comparator is unchanged. If 1, the output of the comparator is inverted prior to being processed by hardware. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2012 571 Texas Instruments-Production Data Pulse Width Modulator (PWM) 16 Pulse Width Modulator (PWM) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. (R) The Stellaris PWM module consists of three PWM generator blocks and a control block. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals (other than being based on the same timer and therefore having the same frequency) or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The Stellaris PWM module provides a great deal of flexibility. It can generate simple PWM signals, such as those required by a simple charge pump. It can also generate paired PWM signals with dead-band delays, such as those required by a half-H bridge driver. Three generator blocks can also generate the full six channels of gate controls required by a 3-phase inverter bridge. Each Stellaris PWM module has the following features: Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt selector One fault input in hardware to promote low-latency shutdown One 16-bit counter - Runs in Down or Up/Down mode - Output frequency controlled by a 16-bit load value - Load value updates can be synchronized - Produces output signals at zero and load value Two PWM comparators - Comparator value updates can be synchronized - Produces output signals on match PWM generator - Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals - Produces two independent PWM signals Dead-band generator - Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge - Can be bypassed, leaving input PWM signals unmodified 572 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Flexible output control block with PWM output enable of each PWM signal - PWM output enable of each PWM signal - Optional output inversion of each PWM signal (polarity control) - Optional fault handling for each PWM signal - Synchronization of timers in the PWM generator blocks - Interrupt status summary of the PWM generator blocks 16.1 Block Diagram Figure 16-1 on page 573 provides the Stellaris PWM module unit diagram and Figure 16-2 on page 574 provides a more detailed diagram of a Stellaris PWM generator. The LM3S6950 controller contains three generator blocks (PWM0, PWM1, and PWM2) and generates six independent PWM signals or three paired PWM signals with dead-band delays inserted. Figure 16-1. PWM Unit Diagram PWM Clock Fault System Clock PWM0_A Control and Status PWMCTL PWMSYNC PWMSTATUS PWM Generator 0 PWM 1 PWM0_Fault PWM PWM1_A PWM Generator 1 Output PWM 2 PWM1_B PWM1_Fault Control PWM 3 Logic Interrupt PWM2_A Interrupts PWM 0 PWM0_B PWMINTEN PWMRIS PWMISC PWM Generator 2 PWM 4 PWM2_B PWM 5 PWM2_Fault Triggers Output PWMENABLE PWMINVERT PWMFAULT June 18, 2012 573 Texas Instruments-Production Data Pulse Width Modulator (PWM) Figure 16-2. PWM Module Block Diagram PWM Generator Block Interrupts / Triggers Interrupt and Trigger Generator Control PWMnINTEN PWMnRIS PWMnISC PWMnCTL PWMn_Fault load dir PWMnLOAD PWMnCOUNT Signal Generator Comparators 16.2 Fault(s) PWMnFLTSRC0 PWMnMINFLTPER PWMnFLTSEN PWMnFLTSTAT0 zero Timer cmp A PWMnCMPA PWMnCMPB PWM Clock Fault Condition PWMnGENA PWMnGENB cmp B Dead-Band Generator PWMnDBCTL PWMnDBRISE PWMnDBFALL PWMn_A PWMn_B Signal Description Table 16-1 on page 574 and Table 16-2 on page 574 list the external signals of the PWM module and describe the function of each. The PWM controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these PWM signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the PWM function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 16-1. PWM Signals (100LQFP) Pin Name Pin Number Fault PWM0 a Pin Type Buffer Type Description 99 I TTL PWM Fault. 10 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 61 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 66 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 67 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 2 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 1 O TTL PWM 5. This signal is controlled by PWM Generator 2. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-2. PWM Signals (108BGA) Pin Name Pin Number a Pin Type Buffer Type Description Fault F2 I TTL PWM Fault. PWM0 G1 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 H12 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 E12 O TTL PWM 2. This signal is controlled by PWM Generator 1. 574 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 16-2. PWM Signals (108BGA) (continued) a Pin Name Pin Number Pin Type Buffer Type Description PWM3 D12 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 C2 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 C1 O TTL PWM 5. This signal is controlled by PWM Generator 2. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 16.3 Functional Description 16.3.1 PWM Timer The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals. The timers output three signals that are used in the PWM generation process: the direction signal (this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero pulse is immediately followed by the load pulse. 16.3.2 PWM Comparators There are two comparators in each PWM generator that monitor the value of the counter; when either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down mode, these comparators match both when counting up and when counting down; they are therefore qualified by the counter direction signal. These qualified pulses are used in the PWM generation process. If either comparator match value is greater than the counter load value, then that comparator never outputs a High pulse. Figure 16-3 on page 576 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Down mode. Figure 16-4 on page 576 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Up/Down mode. June 18, 2012 575 Texas Instruments-Production Data Pulse Width Modulator (PWM) Figure 16-3. PWM Count-Down Mode Load CompA CompB Zero Load Zero A B Dir BDown ADown Figure 16-4. PWM Count-Up/Down Mode Load CompA CompB Zero Load Zero A B Dir BUp AUp 16.3.3 BDown ADown PWM Signal Generator The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load, match A down, and match B down. In Count-Up/Down mode, there are six events that can affect the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match A or match B events are ignored when they coincide with the zero or load events. If the match A and match B events coincide, the first signal, PWMA, is generated based only on the match A event, and the second signal, PWMB, is generated based only on the match B event. For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be used to generate a pair of PWM signals of various positions and duty cycles, which do or do not overlap. Figure 16-5 on page 577 shows the use of Count-Up/Down mode to generate a pair of center-aligned, overlapped PWM signals that have different duty cycles. 576 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 16-5. PWM Generation Example In Count-Up/Down Mode Load CompA CompB Zero PWMA PWMB In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events. Changing the value of comparator A changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the duty cycle of the PWMB signal. 16.3.4 Dead-Band Generator The two PWM signals produced by the PWM generator are passed to the dead-band generator. If disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal is the input signal with the rising edge delayed by a programmable amount. The second output PWM signal is the inversion of the input signal with a programmable delay added between the falling edge of the input signal and the rising edge of this new signal. This is therefore a pair of active High signals where one is always High, except for a programmable amount of time at transitions where both are Low. These signals are therefore suitable for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. Figure 16-6 on page 577 shows the effect of the dead-band generator on an input PWM signal. Figure 16-6. PWM Dead-Band Generator Input PWMA PWMB Rising Edge Delay 16.3.5 Falling Edge Delay Interrupt Selector The PWM generator also takes the same four (or six) counter events and uses them to generate an interrupt. Any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. The selection of events allows the interrupt to occur at a specific position within the PWM signal. Note that interrupts are based on the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken into account. June 18, 2012 577 Texas Instruments-Production Data Pulse Width Modulator (PWM) 16.3.6 Synchronization Methods There is a global reset capability that can synchronously reset any or all of the counters in the PWM generators. If multiple PWM generators are configured with the same counter load value, this can be used to guarantee that they also have the same count value (this does imply that the PWM generators must be configured before they are synchronized). With this, more than two PWM signals can be produced with a known relationship between the edges of those signals since the counters always have the same values. The counter load values and comparator match values of the PWM generator can be updated in two ways. The first is immediate update mode, where a new value is used as soon as the counter reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly short or overly long output PWM pulses are prevented. The other update method is synchronous, where the new value is not used until a global synchronized update signal is asserted, at which point the new value is used as soon as the counter reaches zero. This second mode allows multiple items in multiple PWM generators to be updated simultaneously without odd effects during the update; everything runs from the old values until a point at which they all run from the new values. The Update mode of the load and comparator match values can be individually configured in each PWM generator block. It typically makes sense to use the synchronous update mechanism across PWM generator blocks when the timers in those blocks are synchronized, though this is not required in order for this mechanism to function properly. 16.3.7 Fault Conditions There are two external conditions that affect the PWM block; the signal input on the Fault pin and the stalling of the controller by a debugger. There are two mechanisms available to handle such conditions: the output signals can be forced into an inactive state and/or the PWM timers can be stopped. Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an extended period of time, this keeps the output signal from driving the outside world in a dangerous manner during the fault condition. A fault condition can also generate a controller interrupt. Each PWM generator can also be configured to stop counting during a stall condition. The user can select for the counters to run until they reach zero then stop, or to continue counting and reloading. A stall condition does not generate a controller interrupt. 16.3.8 Output Control Block With each PWM generator block producing two raw PWM signals, the output control block takes care of the final conditioning of the PWM signals before they go to the pins. Via a single register, the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for example, to perform commutation of a brushless DC motor with a single register write (and without modifying the individual PWM generators, which are modified by the feedback control loop). Similarly, fault control can disable any of the PWM signals as well. A final inversion can be applied to any of the PWM signals, making them active Low instead of the default active High. 16.4 Initialization and Configuration The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes the system clock is 20 MHz. 578 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. 4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000). 5. Configure the PWM generator for countdown mode with immediate updates to the parameters. Write the PWM0CTL register with a value of 0x0000.0000. Write the PWM0GENA register with a value of 0x0000.008C. Write the PWM0GENB register with a value of 0x0000.080C. 6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field in the PWM0LOAD register to the requested period minus one. Write the PWM0LOAD register with a value of 0x0000.018F. 7. Set the pulse width of the PWM0 pin for a 25% duty cycle. Write the PWM0CMPA register with a value of 0x0000.012B. 8. Set the pulse width of the PWM1 pin for a 75% duty cycle. Write the PWM0CMPB register with a value of 0x0000.0063. 9. Start the timers in PWM generator 0. Write the PWM0CTL register with a value of 0x0000.0001. 10. Enable PWM outputs. Write the PWMENABLE register with a value of 0x0000.0003. 16.5 Register Map Table 16-3 on page 580 lists the PWM registers. The offset listed is a hexadecimal increment to the register's address, relative to the PWM base address of 0x4002.8000. Note that the PWM module clock must be enabled before the registers can be programmed (see page 212). There must be a delay of 3 system clocks after the PWM module clock is enabled before any PWM module registers are accessed. June 18, 2012 579 Texas Instruments-Production Data Pulse Width Modulator (PWM) Table 16-3. PWM Register Map Description See page Offset Name Type Reset 0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 582 0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 583 0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 584 0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 585 0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 586 0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 587 0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 588 0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 589 0x020 PWMSTATUS RO 0x0000.0000 PWM Status 590 0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 591 0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt Enable 593 0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 595 0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 596 0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 597 0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 598 0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 599 0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 600 0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 601 0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 604 0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 607 0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 608 0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 609 0x080 PWM1CTL R/W 0x0000.0000 PWM1 Control 591 0x084 PWM1INTEN R/W 0x0000.0000 PWM1 Interrupt Enable 593 0x088 PWM1RIS RO 0x0000.0000 PWM1 Raw Interrupt Status 595 0x08C PWM1ISC R/W1C 0x0000.0000 PWM1 Interrupt Status and Clear 596 0x090 PWM1LOAD R/W 0x0000.0000 PWM1 Load 597 0x094 PWM1COUNT RO 0x0000.0000 PWM1 Counter 598 0x098 PWM1CMPA R/W 0x0000.0000 PWM1 Compare A 599 0x09C PWM1CMPB R/W 0x0000.0000 PWM1 Compare B 600 0x0A0 PWM1GENA R/W 0x0000.0000 PWM1 Generator A Control 601 0x0A4 PWM1GENB R/W 0x0000.0000 PWM1 Generator B Control 604 580 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 16-3. PWM Register Map (continued) Name Type Reset 0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 607 0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 608 0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 609 0x0C0 PWM2CTL R/W 0x0000.0000 PWM2 Control 591 0x0C4 PWM2INTEN R/W 0x0000.0000 PWM2 InterruptEnable 593 0x0C8 PWM2RIS RO 0x0000.0000 PWM2 Raw Interrupt Status 595 0x0CC PWM2ISC R/W1C 0x0000.0000 PWM2 Interrupt Status and Clear 596 0x0D0 PWM2LOAD R/W 0x0000.0000 PWM2 Load 597 0x0D4 PWM2COUNT RO 0x0000.0000 PWM2 Counter 598 0x0D8 PWM2CMPA R/W 0x0000.0000 PWM2 Compare A 599 0x0DC PWM2CMPB R/W 0x0000.0000 PWM2 Compare B 600 0x0E0 PWM2GENA R/W 0x0000.0000 PWM2 Generator A Control 601 0x0E4 PWM2GENB R/W 0x0000.0000 PWM2 Generator B Control 604 0x0E8 PWM2DBCTL R/W 0x0000.0000 PWM2 Dead-Band Control 607 0x0EC PWM2DBRISE R/W 0x0000.0000 PWM2 Dead-Band Rising-Edge Delay 608 0x0F0 PWM2DBFALL R/W 0x0000.0000 PWM2 Dead-Band Falling-Edge-Delay 609 16.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the PWM registers, in numerical order by address offset. June 18, 2012 581 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 1: PWM Master Control (PWMCTL), offset 0x000 This register provides master control over the PWM generation blocks. PWM Master Control (PWMCTL) Base 0x4002.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 GlobalSync2 GlobalSync1 GlobalSync0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 GlobalSync2 R/W 0 Update PWM Generator 2 Same as GlobalSync0 but for PWM generator 2. 1 GlobalSync1 R/W 0 Update PWM Generator 1 Same as GlobalSync0 but for PWM generator 1. 0 GlobalSync0 R/W 0 Update PWM Generator 0 Setting this bit causes any queued update to a load or comparator register in PWM generator 0 to be applied the next time the corresponding counter becomes zero. This bit automatically clears when the updates have completed; it cannot be cleared by software. 582 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 This register provides a method to perform synchronization of the counters in the PWM generation blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. PWM Time Base Sync (PWMSYNC) Base 0x4002.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 Sync2 Sync1 Sync0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 Sync2 R/W 0 Reset Generator 2 Counter Performs a reset of the PWM generator 2 counter. 1 Sync1 R/W 0 Reset Generator 1 Counter Performs a reset of the PWM generator 1 counter. 0 Sync0 R/W 0 Reset Generator 0 Counter Performs a reset of the PWM generator 0 counter. June 18, 2012 583 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 3: PWM Output Enable (PWMENABLE), offset 0x008 This register provides a master control of which generated PWM signals are output to device pins. By disabling a PWM output, the generation process can continue (for example, when the time bases are synchronized) without driving PWM signals to the pins. When bits in this register are set, the corresponding PWM signal is passed through to the output stage, which is controlled by the PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is also passed to the output stage. PWM Output Enable (PWMENABLE) Base 0x4002.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 PWM5En R/W 0 PWM5 Output Enable When set, allows the generated PWM5 signal to be passed to the device pin. 4 PWM4En R/W 0 PWM4 Output Enable When set, allows the generated PWM4 signal to be passed to the device pin. 3 PWM3En R/W 0 PWM3 Output Enable When set, allows the generated PWM3 signal to be passed to the device pin. 2 PWM2En R/W 0 PWM2 Output Enable When set, allows the generated PWM2 signal to be passed to the device pin. 1 PWM1En R/W 0 PWM1 Output Enable When set, allows the generated PWM1 signal to be passed to the device pin. 0 PWM0En R/W 0 PWM0 Output Enable When set, allows the generated PWM0 signal to be passed to the device pin. 584 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C This register provides a master control of the polarity of the PWM signals on the device pins. The PWM signals generated by the PWM generator are active High; they can optionally be made active Low via this register. Disabled PWM channels are also passed through the output inverter (if so configured) so that inactive channels maintain the correct polarity. PWM Output Inversion (PWMINVERT) Base 0x4002.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 PWM5Inv R/W 0 Invert PWM5 Signal When set, the generated PWM5 signal is inverted. 4 PWM4Inv R/W 0 Invert PWM4 Signal When set, the generated PWM4 signal is inverted. 3 PWM3Inv R/W 0 Invert PWM3 Signal When set, the generated PWM3 signal is inverted. 2 PWM2Inv R/W 0 Invert PWM2 Signal When set, the generated PWM2 signal is inverted. 1 PWM1Inv R/W 0 Invert PWM1 Signal When set, the generated PWM1 signal is inverted. 0 PWM0Inv R/W 0 Invert PWM0 Signal When set, the generated PWM0 signal is inverted. June 18, 2012 585 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 5: PWM Output Fault (PWMFAULT), offset 0x010 This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the fault inputs and debug events are considered fault conditions. On a fault condition, each PWM signal can be passed through unmodified or driven Low. For outputs that are configured for pass-through, the debug event handling on the corresponding PWM generator also determines if the PWM signal continues to be generated. Fault condition control occurs before the output inverter, so PWM signals driven Low on fault are inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition). PWM Output Fault (PWMFAULT) Base 0x4002.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 Fault5 Fault4 Fault3 Fault2 Fault1 Fault0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 Fault5 R/W 0 PWM5 Fault When set, the PWM5 output signal is driven Low on a fault condition. 4 Fault4 R/W 0 PWM4 Fault When set, the PWM4 output signal is driven Low on a fault condition. 3 Fault3 R/W 0 PWM3 Fault When set, the PWM3 output signal is driven Low on a fault condition. 2 Fault2 R/W 0 PWM2 Fault When set, the PWM2 output signal is driven Low on a fault condition. 1 Fault1 R/W 0 PWM1 Fault When set, the PWM1 output signal is driven Low on a fault condition. 0 Fault0 R/W 0 PWM0 Fault When set, the PWM0 output signal is driven Low on a fault condition. 586 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 This register controls the global interrupt generation capabilities of the PWM module. The events that can cause an interrupt are the fault input and the individual interrupts from the PWM generators. PWM Interrupt Enable (PWMINTEN) Base 0x4002.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset IntFault reserved Type Reset RO 0 16 IntPWM2 IntPWM1 IntPWM0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 IntFault R/W 0 Fault Interrupt Enable When set, an interrupt occurs when the fault input is asserted. 15:3 reserved RO 0x00 2 IntPWM2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Enable When set, an interrupt occurs when the PWM generator 2 block asserts an interrupt. 1 IntPWM1 R/W 0 PWM1 Interrupt Enable When set, an interrupt occurs when the PWM generator 1 block asserts an interrupt. 0 IntPWM0 R/W 0 PWM0 Interrupt Enable When set, an interrupt occurs when the PWM generator 0 block asserts an interrupt. June 18, 2012 587 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection; it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 589). The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that are active; zero bits indicate that the event in question is not active. PWM Raw Interrupt Status (PWMRIS) Base 0x4002.8000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset IntFault reserved Type Reset RO 0 16 IntPWM2 IntPWM1 IntPWM0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 IntFault RO 0 Fault Interrupt Asserted Indicates that the fault input is asserting. 15:3 reserved RO 0x00 2 IntPWM2 RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Asserted Indicates that the PWM generator 2 block is asserting its interrupt. 1 IntPWM1 RO 0 PWM1 Interrupt Asserted Indicates that the PWM generator 1 block is asserting its interrupt. 0 IntPWM0 RO 0 PWM0 Interrupt Asserted Indicates that the PWM generator 0 block is asserting its interrupt. 588 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C This register provides a summary of the interrupt status of the individual PWM generator blocks. A bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual interrupt status registers in each block must be consulted to determine the reason for the interrupt, and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. PWM Interrupt Status and Clear (PWMISC) Base 0x4002.8000 Offset 0x01C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset IntFault reserved Type Reset RO 0 IntPWM2 IntPWM1 IntPWM0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 IntFault R/W1C 0 Fault Interrupt Asserted Indicates that the fault input is asserting an interrupt. 15:3 reserved RO 0x00 2 IntPWM2 RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Status Indicates if the PWM generator 2 block is asserting an interrupt. 1 IntPWM1 RO 0 PWM1 Interrupt Status Indicates if the PWM generator 1 block is asserting an interrupt. 0 IntPWM0 RO 0 PWM0 Interrupt Status Indicates if the PWM generator 0 block is asserting an interrupt. June 18, 2012 589 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 9: PWM Status (PWMSTATUS), offset 0x020 This register provides the status of the FAULT input signal. PWM Status (PWMSTATUS) Base 0x4002.8000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Fault RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Fault RO 0 Fault Interrupt Status When set, indicates the fault input is asserted. 590 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 10: PWM0 Control (PWM0CTL), offset 0x040 Register 11: PWM1 Control (PWM1CTL), offset 0x080 Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers. The blocks produce the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added. The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs. PWM0 Control (PWM0CTL) Base 0x4002.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CmpBUpd CmpAUpd LoadUpd RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 2 1 0 Debug Mode Enable R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 CmpBUpd R/W 0 Comparator B Update Mode Same as CmpAUpd but for the comparator B register. 4 CmpAUpd R/W 0 Comparator A Update Mode The Update mode for the comparator A register. When not set, updates to the register are reflected to the comparator the next time the counter is 0. When set, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 582). 3 LoadUpd R/W 0 Load Register Update Mode The Update mode for the load register. When not set, updates to the register are reflected to the counter the next time the counter is 0. When set, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 2 Debug R/W 0 Debug Mode The behavior of the counter in Debug mode. When not set, the counter stops running when it next reaches 0, and continues running again when no longer in Debug mode. When set, the counter always runs. June 18, 2012 591 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 1 Mode R/W 0 Description Counter Mode The mode for the counter. When not set, the counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode). When set, the counter counts up from 0 to the load value, back down to 0, and then repeats (Count-Up/Down mode). 0 Enable R/W 0 PWM Block Enable Master enable for the PWM generation block. When not set, the entire block is disabled and not clocked. When set, the block is enabled and produces PWM signals. 592 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084 Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4 These registers control the interrupt generation capabilities of the PWM generators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an interrupt are: The counter being equal to the load register The counter being equal to zero The counter being equal to the comparator A register while counting up The counter being equal to the comparator A register while counting down The counter being equal to the comparator B register while counting up The counter being equal to the comparator B register while counting down Any combination of these events can generate either an interrupt. PWM0 Interrupt Enable (PWM0INTEN) Base 0x4002.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 IntCmpBD R/W 0 Interrupt for Counter=Comparator B Down Value Description 4 IntCmpBU R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting down. 0 No interrupt. Interrupt for Counter=Comparator B Up Value Description 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting up. 0 No interrupt. June 18, 2012 593 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 3 IntCmpAD R/W 0 Description Interrupt for Counter=Comparator A Down Value Description 2 IntCmpAU R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting down. 0 No interrupt. Interrupt for Counter=Comparator A Up Value Description 1 IntCntLoad R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting up. 0 No interrupt. Interrupt for Counter=Load Value Description 0 IntCntZero R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnLOAD register value. 0 No interrupt. Interrupt for Counter=0 Value Description 1 A raw interrupt occurs when the counter is zero. 0 No interrupt. 594 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events that have occurred; bits set to 0 indicate that the event in question has not occurred. PWM0 Raw Interrupt Status (PWM0RIS) Base 0x4002.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 IntCmpBD RO 0 Comparator B Down Interrupt Status Indicates that the counter has matched the comparator B value while counting down. 4 IntCmpBU RO 0 Comparator B Up Interrupt Status Indicates that the counter has matched the comparator B value while counting up. 3 IntCmpAD RO 0 Comparator A Down Interrupt Status Indicates that the counter has matched the comparator A value while counting down. 2 IntCmpAU RO 0 Comparator A Up Interrupt Status Indicates that the counter has matched the comparator A value while counting up. 1 IntCntLoad RO 0 Counter=Load Interrupt Status Indicates that the counter has matched the PWMnLOAD register. 0 IntCntZero RO 0 Counter=0 Interrupt Status Indicates that the counter has matched 0. June 18, 2012 595 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC These registers provide the current set of interrupt sources that are asserted to the controller (PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events that have occurred; bits set to 0 indicate that the event in question has not occurred. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason. PWM0 Interrupt Status and Clear (PWM0ISC) Base 0x4002.8000 Offset 0x04C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 IntCmpBD R/W1C 0 Comparator B Down Interrupt Indicates that the counter has matched the comparator B value while counting down. 4 IntCmpBU R/W1C 0 Comparator B Up Interrupt Indicates that the counter has matched the comparator B value while counting up. 3 IntCmpAD R/W1C 0 Comparator A Down Interrupt Indicates that the counter has matched the comparator A value while counting down. 2 IntCmpAU R/W1C 0 Comparator A Up Interrupt Indicates that the counter has matched the comparator A value while counting up. 1 IntCntLoad R/W1C 0 Counter=Load Interrupt Indicates that the counter has matched the PWMnLOAD register. 0 IntCntZero R/W1C 0 Counter=0 Interrupt Indicates that the counter has matched 0. 596 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 22: PWM0 Load (PWM0LOAD), offset 0x050 Register 23: PWM1 Load (PWM1LOAD), offset 0x090 Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero. If the Load Value Update mode is immediate, this value is used the next time the counter reaches zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 582). If this register is re-written before the actual update occurs, the previous value is never used and is lost. PWM0 Load (PWM0LOAD) Base 0x4002.8000 Offset 0x050 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 Load Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 Load R/W 0 Counter Load Value The counter load value. June 18, 2012 597 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on). When this value matches the load register, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see page 601 and page 604) or drive an interrupt (via the PWMnINTEN register, see page 593). A pulse with the same capabilities is generated when this value is zero. PWM0 Counter (PWM0COUNT) Base 0x4002.8000 Offset 0x054 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset Count Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 Count RO 0x00 Counter Value The current value of the counter. 598 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 These registers contain a value to be compared against the counter (PWM0CMPA controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register (see page 597), then no pulse is ever output. If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register), this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 582). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare A (PWM0CMPA) Base 0x4002.8000 Offset 0x058 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 CompA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 CompA R/W 0x00 Comparator A Value The value to be compared against the counter. June 18, 2012 599 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register, no pulse is ever output. If the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL register), this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 582). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare B (PWM0CMPB) Base 0x4002.8000 Offset 0x05C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 CompB Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 CompB R/W 0x00 Comparator B Value The value to be compared against the counter. 600 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 These registers control the generation of the PWMnA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced. The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal; and PWM2GENA, the PWM2A signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare A action is taken and the compare B action is ignored. PWM0 Generator A Control (PWM0GENA) Base 0x4002.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ActCmpBD RO 0 R/W 0 ActCmpBU R/W 0 ActCmpAD R/W 0 R/W 0 R/W 0 ActCmpAU R/W 0 R/W 0 ActLoad R/W 0 ActZero R/W 0 Bit/Field Name Type Reset Description 31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 ActCmpBD R/W 0x0 Action for Comparator B Down The action to be taken when the counter matches comparator B while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. June 18, 2012 601 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 9:8 ActCmpBU R/W 0x0 Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register (see page 591) is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 7:6 ActCmpAD R/W 0x0 Action for Comparator A Down The action to be taken when the counter matches comparator A while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 5:4 ActCmpAU R/W 0x0 Action for Comparator A Up The action to be taken when the counter matches comparator A while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 3:2 ActLoad R/W 0x0 Action for Counter=Load The action to be taken when the counter matches the load value. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 602 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 1:0 ActZero R/W 0x0 Description Action for Counter=0 The action to be taken when the counter is zero. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. June 18, 2012 603 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 These registers control the generation of the PWMnB signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced. The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal; and PWM2GENB, the PWM2B signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare B action is taken and the compare A action is ignored. PWM0 Generator B Control (PWM0GENB) Base 0x4002.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ActCmpBD RO 0 R/W 0 ActCmpBU R/W 0 ActCmpAD R/W 0 R/W 0 R/W 0 ActCmpAU R/W 0 R/W 0 ActLoad R/W 0 ActZero R/W 0 Bit/Field Name Type Reset Description 31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 ActCmpBD R/W 0x0 Action for Comparator B Down The action to be taken when the counter matches comparator B while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 604 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 9:8 ActCmpBU R/W 0x0 Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 7:6 ActCmpAD R/W 0x0 Action for Comparator A Down The action to be taken when the counter matches comparator A while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 5:4 ActCmpAU R/W 0x0 Action for Comparator A Up The action to be taken when the counter matches comparator A while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 3:2 ActLoad R/W 0x0 Action for Counter=Load The action to be taken when the counter matches the load value. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. June 18, 2012 605 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 1:0 ActZero R/W 0x0 Description Action for Counter=0 The action to be taken when the counter is 0. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 606 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1 signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see page 608), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by the value in the PWM0DBFALL register (see page 609). In a similar manner, PWM2 and PWM3 are produced from the PWM1A and PWM1B signals, and PWM4 and PWM5 are produced from the PWM2A and PWM2B signals. PWM0 Dead-Band Control (PWM0DBCTL) Base 0x4002.8000 Offset 0x068 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 0 Enable RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Enable R/W 0 Dead-Band Generator Enable When set, the dead-band generator inserts dead bands into the output signals; when clear, it simply passes the PWM signals through. June 18, 2012 607 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A signal when generating the PWM0 signal. If the dead-band generator is disabled through the PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire High time of the signal, resulting in no High time on the output. Care must be taken to ensure that the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge delayed. PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE) Base 0x4002.8000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RiseDelay RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:0 RiseDelay R/W 0 Dead-Band Rise Delay The number of clock ticks to delay the rising edge. 608 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed and PWM5 is produced from PWM2A with its falling edge delayed. PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL) Base 0x4002.8000 Offset 0x070 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 FallDelay RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:0 FallDelay R/W 0x00 Dead-Band Fall Delay The number of clock ticks to delay the falling edge. June 18, 2012 609 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) 17 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. (R) The Stellaris quadrature encoder interface (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The Stellaris quadrature encoder has the following features: Position integrator that tracks the encoder position Velocity capture using built-in timer The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) Interrupt generation on: - Index pulse - Velocity-timer expiration - Direction change - Quadrature error detection 17.1 Block Diagram Figure 17-1 on page 611 provides a block diagram of a Stellaris QEI module. 610 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 17-1. QEI Block Diagram QEILOAD Control & Status Velocity Timer QEITIME QEICTL QEISTAT Velocity Accumulator Velocity Predivider clk PhA PhB QEICOUNT QEISPEED QEIMAXPOS Quadrature Encoder dir Position Integrator QEIPOS IDX QEIINTEN Interrupt Control Interrupt QEIRIS QEIISC 17.2 Signal Description Table 17-1 on page 611 and Table 17-2 on page 611 list the external signals of the QEI module and describe the function of each. The QEI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 306) should be set to choose the QEI function. For more information on configuring GPIOs, see "General-Purpose Input/Outputs (GPIOs)" on page 284. Table 17-1. QEI Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description IDX0 100 I TTL QEI module 0 index. PhA0 11 I TTL QEI module 0 phase A. PhB0 47 I TTL QEI module 0 phase B. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 17-2. QEI Signals (108BGA) Pin Name a Pin Number Pin Type Buffer Type Description IDX0 F1 I TTL QEI module 0 index. PhA0 G2 I TTL QEI module 0 phase A. PhB0 M9 I TTL QEI module 0 phase B. a. The TTL designation indicates the pin has TTL-compatible voltage levels. June 18, 2012 611 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) 17.3 Functional Description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The position integrator and velocity capture can be independently enabled, though the position integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA and PhB, can be swapped before being interpreted by the QEI module to change the meaning of forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see page 616). When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the capture mode for the position integrator can be set to update the position counter on every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA and PhB provides more positional resolution at the cost of less range in the positional counter. When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. The positional counter is automatically reset on one of two conditions: sensing the index pulse or reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI Control (QEICTL) register. When ResMode is 1, the positional counter is reset when the index pulse is sensed. This limits the positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse direction from position 0 can move the position counter to N-1. In this mode, the position register contains the absolute position of the encoder relative to the index (or home) position once an index pulse has been seen. When ResMode is 0, the positional counter is constrained to the range [0:M], where M is the programmable maximum value. The index pulse is ignored by the positional counter in this mode. The velocity capture has a configurable timer and a count register. It counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. The edge count from the previous time period is available to the controller via the QEISPEED register, while the edge count for the current time period is being accumulated in the QEICOUNT register. As soon as the current time period is complete, the total number of edges counted in that time period is made available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and counting commences on a new time period. The number of edges counted in a given time period is directly proportional to the velocity of the encoder. Figure 17-2 on page 613 shows how the Stellaris quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode). 612 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 17-2. Quadrature Encoder and Velocity Predivider Operation PhA PhB clk clkdiv dir pos rel -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 The period of the timer is configurable by specifying the load value for the timer in the QEILOAD register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer timer period is needed to be able to capture enough edges to have a meaningful result. At higher encoder speeds, both a shorter timer period and/or the velocity predivider can be used. The following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ VelDiv) * Speed * 60) / (Load * ppr * edges) where: clock is the controller clock rate ppr is the number of pulses per revolution of the physical encoder edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and 4 for CapMode set to 1) For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of /1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load value was 2,500 (1/4 of a second), it would count 20,480 pulses per update. Using the above equation: rpm = (10000 * 1 * 20480 * 60) / (2500 * 2048 * 4) = 600 rpm Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second, or 102,400 every 1/4 of a second. Again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) / (2500 * 2048 * 4) = 3000 rpm Care must be taken when evaluating this equation since intermediate values may exceed the capacity of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the /4 for the edge-count factor. Important: Reducing constant factors at compile time is the best way to control the intermediate values of this equation, as well as reducing the processing requirement of computing this equation. The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a load value must be selected such that the product is very close to a power of two. For example, a June 18, 2012 613 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) 100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute accuracy were required, the controller's divide instruction could be used. The QEI module can produce a controller interrupt on several events: phase error, direction change, reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt status, interrupt status, and interrupt clear capabilities are provided. 17.4 Initialization and Configuration The following example shows how to configure the Quadrature Encoder module to read back an absolute position: 1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. 4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the count is zero-based. Write the QEICTL register with the value of 0x0000.0018. Write the QEIMAXPOS register with the value of 0x0000.0F9F. 5. Enable the quadrature encoder by setting bit 0 of the QEICTL register. 6. Delay for some time. 7. Read the encoder position by reading the QEIPOS register value. 17.5 Register Map Table 17-3 on page 614 lists the QEI registers. The offset listed is a hexadecimal increment to the register's address, relative to the module's base address: QEI0: 0x4002.C000 Note that the QEI module clock must be enabled before the registers can be programmed (see page 218). There must be a delay of 3 system clocks after the QEI module clock is enabled before any QEI module registers are accessed. Table 17-3. QEI Register Map Offset Name Type Reset Description See page 0x000 QEICTL R/W 0x0000.0000 QEI Control 616 614 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 17-3. QEI Register Map (continued) Offset Name 0x004 Reset QEISTAT RO 0x0000.0000 QEI Status 618 0x008 QEIPOS R/W 0x0000.0000 QEI Position 619 0x00C QEIMAXPOS R/W 0x0000.0000 QEI Maximum Position 620 0x010 QEILOAD R/W 0x0000.0000 QEI Timer Load 621 0x014 QEITIME RO 0x0000.0000 QEI Timer 622 0x018 QEICOUNT RO 0x0000.0000 QEI Velocity Counter 623 0x01C QEISPEED RO 0x0000.0000 QEI Velocity 624 0x020 QEIINTEN R/W 0x0000.0000 QEI Interrupt Enable 625 0x024 QEIRIS RO 0x0000.0000 QEI Raw Interrupt Status 626 0x028 QEIISC R/W1C 0x0000.0000 QEI Interrupt Status and Clear 627 17.6 Description See page Type Register Descriptions The remainder of this section lists and describes the QEI registers, in numerical order by address offset. June 18, 2012 615 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 1: QEI Control (QEICTL), offset 0x000 This register contains the configuration of the QEI module. Separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset mode, and velocity predivider are all set via this register. QEI Control (QEICTL) QEI0 base: 0x4002.C000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 STALLEN INVI INVB INVA R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 Swap Enable R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 RO 0 VelDiv R/W 0 VelEn R/W 0 R/W 0 R/W 0 ResMode CapMode SigMode R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:13 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 STALLEN R/W 0 Stall QEI When set, the QEI stalls when the microcontroller asserts Halt. 11 INVI R/W 0 Invert Index Pulse When set , the input Index Pulse is inverted. 10 INVB R/W 0 Invert PhB When set, the PhB input is inverted. 9 INVA R/W 0 Invert PhA When set, the PhA input is inverted. 8:6 VelDiv R/W 0x0 Predivide Velocity A predivider of the input quadrature pulses before being applied to the QEICOUNT accumulator. This field can be set to the following values: Value Predivider 0x0 /1 0x1 /2 0x2 /4 0x3 /8 0x4 /16 0x5 /32 0x6 /64 0x7 /128 616 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Bit/Field Name Type Reset 5 VelEn R/W 0 Description Capture Velocity When set, enables capture of the velocity of the quadrature encoder. 4 ResMode R/W 0 Reset Mode The Reset mode for the position counter. When 0, the position counter is reset when it reaches the maximum; when 1, the position counter is reset when the index pulse is captured. 3 CapMode R/W 0 Capture Mode The Capture mode defines the phase edges that are counted in the position. When 0, only the PhA edges are counted; when 1, the PhA and PhB edges are counted, providing twice the positional resolution but half the range. 2 SigMode R/W 0 Signal Mode When 1, the PhA and PhB signals are clock and direction; when 0, they are quadrature phase signals. 1 Swap R/W 0 Swap Signals Swaps the PhA and PhB signals. 0 Enable R/W 0 Enable QEI Enables the quadrature encoder module. June 18, 2012 617 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 2: QEI Status (QEISTAT), offset 0x004 This register provides status about the operation of the QEI module. QEI Status (QEISTAT) QEI0 base: 0x4002.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 Direction Error RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 Direction RO 0 Direction of Rotation Indicates the direction the encoder is rotating. The Direction values are defined as follows: Value Description 0 Error RO 0 0 Forward rotation 1 Reverse rotation Error Detected Indicates that an error was detected in the gray code sequence (that is, both signals changing at the same time). 618 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 3: QEI Position (QEIPOS), offset 0x008 This register contains the current value of the position integrator. Its value is updated by inputs on the QEI phase inputs, and can be set to a specific value by writing to it. QEI Position (QEIPOS) QEI0 base: 0x4002.C000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Position Type Reset Position Type Reset Bit/Field Name Type Reset Description 31:0 Position R/W 0x00 Current Position Integrator Value The current value of the position integrator. June 18, 2012 619 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C This register contains the maximum value of the position integrator. When moving forward, the position register resets to zero when it increments past this value. When moving backward, the position register resets to this value when it decrements from zero. QEI Maximum Position (QEIMAXPOS) QEI0 base: 0x4002.C000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MaxPos Type Reset MaxPos Type Reset Bit/Field Name Type Reset Description 31:0 MaxPos R/W 0x00 Maximum Position Integrator Value The maximum value of the position integrator. 620 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 5: QEI Timer Load (QEILOAD), offset 0x010 This register contains the load value for the velocity timer. Since this value is loaded into the timer the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. So, for example, to have 2000 clocks per timer period, this register should contain 1999. QEI Timer Load (QEILOAD) QEI0 base: 0x4002.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Load Type Reset Load Type Reset Bit/Field Name Type Reset Description 31:0 Load R/W 0x00 Velocity Timer Load Value The load value for the velocity timer. June 18, 2012 621 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 6: QEI Timer (QEITIME), offset 0x014 This register contains the current value of the velocity timer. This counter does not increment when VelEn in QEICTL is 0. QEI Timer (QEITIME) QEI0 base: 0x4002.C000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Time Type Reset Time Type Reset Bit/Field Name Type Reset Description 31:0 Time RO 0x00 Velocity Timer Current Value The current value of the velocity timer. 622 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 This register contains the running count of velocity pulses for the current time period. Since this is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the QEITIME register since there is a small window of time between the two reads, during which time either value may have changed). The QEISPEED register should be used to determine the actual encoder velocity; this register is provided for information purposes only. This counter does not increment when VelEn in QEICTL is 0. QEI Velocity Counter (QEICOUNT) QEI0 base: 0x4002.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Count Type Reset Count Type Reset Bit/Field Name Type Reset Description 31:0 Count RO 0x00 Velocity Pulse Count The running total of encoder pulses during this velocity timer period. June 18, 2012 623 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 8: QEI Velocity (QEISPEED), offset 0x01C This register contains the most recently measured velocity of the quadrature encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period. This register does not update when VelEn in QEICTL is 0. QEI Velocity (QEISPEED) QEI0 base: 0x4002.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Speed Type Reset Speed Type Reset Bit/Field Name Type Reset Description 31:0 Speed RO 0x00 Velocity The measured speed of the quadrature encoder in pulses per period. 624 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 This register contains enables for each of the QEI module's interrupts. An interrupt is asserted to the controller if its corresponding bit in this register is set to 1. QEI Interrupt Enable (QEIINTEN) QEI0 base: 0x4002.C000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IntError IntDir IntTimer IntIndex RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 IntError R/W 0 Phase Error Interrupt Enable When 1, an interrupt occurs when a phase error is detected. 2 IntDir R/W 0 Direction Change Interrupt Enable When 1, an interrupt occurs when the direction changes. 1 IntTimer R/W 0 Timer Expires Interrupt Enable When 1, an interrupt occurs when the velocity timer expires. 0 IntIndex R/W 0 Index Pulse Detected Interrupt Enable When 1, an interrupt occurs when the index pulse is detected. June 18, 2012 625 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register). Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. QEI Raw Interrupt Status (QEIRIS) QEI0 base: 0x4002.C000 Offset 0x024 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IntError IntDir IntTimer IntIndex RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 IntError RO 0 Phase Error Detected Indicates that a phase error was detected. 2 IntDir RO 0 Direction Change Detected Indicates that the direction has changed. 1 IntTimer RO 0 Velocity Timer Expired Indicates that the velocity timer has expired. 0 IntIndex RO 0 Index Pulse Asserted Indicates that the index pulse has occurred. 626 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 This register provides the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding interrupt reason. QEI Interrupt Status and Clear (QEIISC) QEI0 base: 0x4002.C000 Offset 0x028 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IntError IntDir IntTimer IntIndex RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 IntError R/W1C 0 Phase Error Interrupt Indicates that a phase error was detected. 2 IntDir R/W1C 0 Direction Change Interrupt Indicates that the direction has changed. 1 IntTimer R/W1C 0 Velocity Timer Expired Interrupt Indicates that the velocity timer has expired. 0 IntIndex R/W1C 0 Index Pulse Interrupt Indicates that the index pulse has occurred. June 18, 2012 627 Texas Instruments-Production Data Pin Diagram 18 Pin Diagram The LM3S6950 microcontroller pin diagrams are shown below. Figure 18-1. 100-Pin LQFP Package Pin Diagram 628 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) June 18, 2012 629 Texas Instruments-Production Data Signal Tables 19 Signal Tables Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register. All digital inputs are Schmitt triggered. Signals by Pin Number Signals by Signal Name Signals by Function, Except for GPIO GPIO Pins and Alternate Functions Connections for Unused Signals 19.1 100-Pin LQFP Package Pin Tables 19.1.1 Signals by Pin Number Table 19-1. Signals by Pin Number Pin Number a Pin Name Pin Type Buffer Type PE7 I/O TTL GPIO port E bit 7. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. PE6 I/O TTL GPIO port E bit 6. PWM 4. This signal is controlled by PWM Generator 2. 1 2 PWM4 O TTL VDDA - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. GNDA - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. PE5 I/O TTL GPIO port E bit 5. 3 4 5 Description PE4 I/O TTL GPIO port E bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). 8 VDD - Power Positive supply for I/O and some logic. 9 GND - Power Ground reference for logic and I/O pins. PD0 I/O TTL GPIO port D bit 0. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PD1 I/O TTL GPIO port D bit 1. PhA0 I TTL QEI module 0 phase A. PD2 I/O TTL GPIO port D bit 2. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. 6 7 10 11 12 630 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-1. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PD3 I/O TTL GPIO port D bit 3. 13 U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. Ground reference for logic and I/O pins. 14 15 16 Description GND - Power XTALPPHY I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. XTALNPHY O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. 17 PG1 I/O TTL GPIO port G bit 1. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PG0 I/O TTL GPIO port G bit 0. 19 U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. 20 VDD - Power Positive supply for I/O and some logic. 21 GND - Power Ground reference for logic and I/O pins. PC7 I/O TTL C2- I Analog PC6 I/O TTL C2+ I Analog C2o O TTL Analog comparator 2 output. PC5 I/O TTL GPIO port C bit 5. C1+ I Analog C1o O TTL Analog comparator 1 output. PC4 I/O TTL GPIO port C bit 4. CCP5 I/O TTL Capture/Compare/PWM 5. PA0 I/O TTL GPIO port A bit 0. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. PA1 I/O TTL GPIO port A bit 1. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. 18 22 23 24 25 26 27 Analog comparator 2 negative input. GPIO port C bit 6. Analog comparator 2 positive input. Analog comparator 1 positive input. PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame signal PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive PA5 I/O TTL GPIO port A bit 5. SSI0Tx O TTL SSI module 0 transmit VDD - Power 28 29 30 31 32 GPIO port C bit 7. Positive supply for I/O and some logic. June 18, 2012 631 Texas Instruments-Production Data Signal Tables Table 19-1. Signals by Pin Number (continued) Pin Number Pin Name 33 a Pin Type Buffer Type GND - Power PA6 I/O TTL GPIO port A bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. 34 Description Ground reference for logic and I/O pins. PA7 I/O TTL GPIO port A bit 7. CCP4 I/O TTL Capture/Compare/PWM 4. 36 VCCPHY - Power VCC of the Ethernet PHY. 37 RXIN I Analog RXIN of the Ethernet PHY. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. GND - Power Ground reference for logic and I/O pins. 35 38 39 40 RXIP I Analog RXIP of the Ethernet PHY. 41 ERBIAS I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. 42 GNDPHY - Power GND of the Ethernet PHY. 43 TXOP O Analog TXOP of the Ethernet PHY. 44 VDD - Power Positive supply for I/O and some logic. 45 GND - Power Ground reference for logic and I/O pins. 46 TXON O Analog TXON of the Ethernet PHY. PF0 I/O TTL GPIO port F bit 0. PhB0 I TTL QEI module 0 phase B. OSC0 I Analog Main oscillator crystal input or an external clock reference input. OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. WAKE I TTL An external input that brings the processor out of Hibernate mode when asserted. HIB O OD An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. XOSC0 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. 47 48 49 50 51 52 53 GND - Power Ground reference for logic and I/O pins. VBAT - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. 56 VDD - Power Positive supply for I/O and some logic. 57 GND - Power Ground reference for logic and I/O pins. 58 MDIO I/O TTL MDIO of the Ethernet PHY. 54 55 PF3 I/O TTL GPIO port F bit 3. LED0 O TTL Ethernet LED 0. 59 PF2 I/O TTL GPIO port F bit 2. LED1 O TTL Ethernet LED 1. PF1 I/O TTL GPIO port F bit 1. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. 60 61 632 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-1. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 63 GND - Power Ground reference for logic and I/O pins. 64 RST I TTL System reset input. CMOD0 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. PB0 I/O TTL GPIO port B bit 0. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. PB1 I/O TTL GPIO port B bit 1. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. 68 VDD - Power Positive supply for I/O and some logic. 69 GND - Power Ground reference for logic and I/O pins. 62 65 66 67 Description PB2 I/O TTL GPIO port B bit 2. I2C0SCL I/O OD I2C module 0 clock. PB3 I/O TTL GPIO port B bit 3. I2C0SDA I/O OD I2C module 0 data. PE0 I/O TTL GPIO port E bit 0. SSI1Clk I/O TTL SSI module 1 clock 70 71 72 PE1 I/O TTL GPIO port E bit 1. SSI1Fss I/O TTL SSI module 1 frame signal 73 PE2 I/O TTL GPIO port E bit 2. SSI1Rx I TTL SSI module 1 receive PE3 I/O TTL GPIO port E bit 3. SSI1Tx O TTL SSI module 1 transmit CMOD1 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I/O TTL JTAG TMS and SWDIO. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. VDD - Power Positive supply for I/O and some logic. 82 GND - Power Ground reference for logic and I/O pins. 83 VCCPHY - Power VCC of the Ethernet PHY. 84 VCCPHY - Power VCC of the Ethernet PHY. 85 GNDPHY - Power GND of the Ethernet PHY. 74 75 76 77 78 79 80 81 June 18, 2012 633 Texas Instruments-Production Data Signal Tables Table 19-1. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type 86 GNDPHY - Power GND of the Ethernet PHY. 87 GND - Power Ground reference for logic and I/O pins. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. PB7 I/O TTL GPIO port B bit 7. TRST I TTL JTAG TRST. PB6 I/O TTL GPIO port B bit 6. C0+ I Analog C0o O TTL Analog comparator 0 output. PB5 I/O TTL GPIO port B bit 5. C1- I Analog PB4 I/O TTL C0- I Analog Analog comparator 0 negative input. 93 VDD - Power Positive supply for I/O and some logic. 94 GND - Power Ground reference for logic and I/O pins. 88 89 90 91 92 Description Analog comparator 0 positive input. Analog comparator 1 negative input. GPIO port B bit 4. PD4 I/O TTL GPIO port D bit 4. CCP0 I/O TTL Capture/Compare/PWM 0. PD5 I/O TTL GPIO port D bit 5. Capture/Compare/PWM 2. 95 96 CCP2 I/O TTL GNDA - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. 97 98 PD6 I/O TTL GPIO port D bit 6. Fault I TTL PWM Fault. PD7 I/O TTL GPIO port D bit 7. IDX0 I TTL QEI module 0 index. 99 100 a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.1.2 Signals by Signal Name Table 19-2. Signals by Signal Name a Pin Name Pin Number Pin Type Buffer Type C0+ 90 I Analog Description Analog comparator 0 positive input. C0- 92 I Analog Analog comparator 0 negative input. C0o 90 O TTL C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 24 O TTL Analog comparator 0 output. Analog comparator 1 output. 634 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description C2+ 23 I Analog Analog comparator 2 positive input. C2- 22 I Analog Analog comparator 2 negative input. C2o 23 O TTL Analog comparator 2 output. CCP0 95 I/O TTL Capture/Compare/PWM 0. CCP1 34 I/O TTL Capture/Compare/PWM 1. CCP2 96 I/O TTL Capture/Compare/PWM 2. CCP3 6 I/O TTL Capture/Compare/PWM 3. CCP4 35 I/O TTL Capture/Compare/PWM 4. CCP5 25 I/O TTL Capture/Compare/PWM 5. CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. ERBIAS 41 I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. Fault 99 I TTL GND 9 15 21 33 39 45 54 57 63 69 82 87 94 - Power Ground reference for logic and I/O pins. GNDA 4 97 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. HIB 51 O OD An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. I2C0SCL 70 I/O OD I2C module 0 clock. I2C0SDA 71 I/O OD I2C module 0 data. IDX0 100 I TTL QEI module 0 index. LDO 7 - Power LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY. PWM Fault. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). June 18, 2012 635 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description OSC0 48 I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PA0 26 I/O TTL GPIO port A bit 0. PA1 27 I/O TTL GPIO port A bit 1. PA2 28 I/O TTL GPIO port A bit 2. PA3 29 I/O TTL GPIO port A bit 3. PA4 30 I/O TTL GPIO port A bit 4. PA5 31 I/O TTL GPIO port A bit 5. PA6 34 I/O TTL GPIO port A bit 6. PA7 35 I/O TTL GPIO port A bit 7. PB0 66 I/O TTL GPIO port B bit 0. PB1 67 I/O TTL GPIO port B bit 1. PB2 70 I/O TTL GPIO port B bit 2. PB3 71 I/O TTL GPIO port B bit 3. PB4 92 I/O TTL GPIO port B bit 4. PB5 91 I/O TTL GPIO port B bit 5. PB6 90 I/O TTL GPIO port B bit 6. PB7 89 I/O TTL GPIO port B bit 7. PC0 80 I/O TTL GPIO port C bit 0. PC1 79 I/O TTL GPIO port C bit 1. PC2 78 I/O TTL GPIO port C bit 2. PC3 77 I/O TTL GPIO port C bit 3. PC4 25 I/O TTL GPIO port C bit 4. PC5 24 I/O TTL GPIO port C bit 5. PC6 23 I/O TTL GPIO port C bit 6. PC7 22 I/O TTL GPIO port C bit 7. PD0 10 I/O TTL GPIO port D bit 0. PD1 11 I/O TTL GPIO port D bit 1. PD2 12 I/O TTL GPIO port D bit 2. PD3 13 I/O TTL GPIO port D bit 3. PD4 95 I/O TTL GPIO port D bit 4. PD5 96 I/O TTL GPIO port D bit 5. PD6 99 I/O TTL GPIO port D bit 6. PD7 100 I/O TTL GPIO port D bit 7. PE0 72 I/O TTL GPIO port E bit 0. PE1 73 I/O TTL GPIO port E bit 1. PE2 74 I/O TTL GPIO port E bit 2. PE3 75 I/O TTL GPIO port E bit 3. PE4 6 I/O TTL GPIO port E bit 4. PE5 5 I/O TTL GPIO port E bit 5. 636 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description PE6 2 I/O TTL GPIO port E bit 6. PE7 1 I/O TTL GPIO port E bit 7. PF0 47 I/O TTL GPIO port F bit 0. PF1 61 I/O TTL GPIO port F bit 1. PF2 60 I/O TTL GPIO port F bit 2. PF3 59 I/O TTL GPIO port F bit 3. PG0 19 I/O TTL GPIO port G bit 0. PG1 18 I/O TTL GPIO port G bit 1. PhA0 11 I TTL QEI module 0 phase A. PhB0 47 I TTL QEI module 0 phase B. PWM0 10 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 61 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 66 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 67 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 2 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 1 O TTL PWM 5. This signal is controlled by PWM Generator 2. RST 64 I TTL System reset input. RXIN 37 I Analog RXIN of the Ethernet PHY. RXIP of the Ethernet PHY. RXIP 40 I Analog SSI0Clk 28 I/O TTL SSI module 0 clock SSI0Fss 29 I/O TTL SSI module 0 frame signal SSI0Rx 30 I TTL SSI module 0 receive SSI0Tx 31 O TTL SSI module 0 transmit SSI1Clk 72 I/O TTL SSI module 1 clock SSI1Fss 73 I/O TTL SSI module 1 frame signal SSI1Rx 74 I TTL SSI module 1 receive SSI1Tx 75 O TTL SSI module 1 transmit SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I/O TTL JTAG TMS and SWDIO. TRST 89 I TTL JTAG TRST. TXON 46 O Analog TXON of the Ethernet PHY. TXOP 43 O Analog TXOP of the Ethernet PHY. U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. June 18, 2012 637 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description U1Rx 12 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 13 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 19 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 18 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. VBAT 55 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. VCCPHY 36 83 84 - Power VCC of the Ethernet PHY. VDD 8 20 32 44 56 68 81 93 - Power Positive supply for I/O and some logic. VDD25 14 38 62 88 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDDA 3 98 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. WAKE 50 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 52 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. XTALNPHY 17 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY 16 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 638 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 19.1.3 Signals by Function, Except for GPIO Table 19-3. Signals by Function, Except for GPIO Function Analog Comparators Ethernet General-Purpose Timers Pin Name a Pin Number Pin Type Buffer Type C0+ 90 I Analog Analog comparator 0 positive input. Description C0- 92 I Analog Analog comparator 0 negative input. C0o 90 O TTL C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 24 O TTL C2+ 23 I Analog Analog comparator 2 positive input. C2- 22 I Analog Analog comparator 2 negative input. C2o 23 O TTL ERBIAS 41 I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY. RXIN 37 I Analog RXIN of the Ethernet PHY. RXIP 40 I Analog RXIP of the Ethernet PHY. TXON 46 O Analog TXON of the Ethernet PHY. TXOP 43 O Analog TXOP of the Ethernet PHY. VCCPHY 36 83 84 - Power VCC of the Ethernet PHY. XTALNPHY 17 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY 16 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. CCP0 95 I/O TTL Capture/Compare/PWM 0. CCP1 34 I/O TTL Capture/Compare/PWM 1. CCP2 96 I/O TTL Capture/Compare/PWM 2. CCP3 6 I/O TTL Capture/Compare/PWM 3. CCP4 35 I/O TTL Capture/Compare/PWM 4. CCP5 25 I/O TTL Capture/Compare/PWM 5. Analog comparator 0 output. Analog comparator 1 output. Analog comparator 2 output. June 18, 2012 639 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type HIB 51 O OD VBAT 55 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE 50 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 52 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. I2C0SCL 70 I/O OD I2C module 0 clock. I2C0SDA 71 I/O OD I2C module 0 data. SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I/O TTL JTAG TMS and SWDIO. TRST 89 I TTL JTAG TRST. Fault 99 I TTL PWM Fault. PWM0 10 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 61 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 66 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 67 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 2 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 1 O TTL PWM 5. This signal is controlled by PWM Generator 2. Hibernate I2C JTAG/SWD/SWO PWM Description An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. 640 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-3. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND 9 15 21 33 39 45 54 57 63 69 82 87 94 - Power Ground reference for logic and I/O pins. GNDA 4 97 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO 7 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). VDD 8 20 32 44 56 68 81 93 - Power Positive supply for I/O and some logic. VDD25 14 38 62 88 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDDA 3 98 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. IDX0 100 I TTL QEI module 0 index. PhA0 11 I TTL QEI module 0 phase A. PhB0 47 I TTL QEI module 0 phase B. Power QEI Description June 18, 2012 641 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Type Buffer Type SSI0Clk 28 I/O TTL SSI module 0 clock SSI0Fss 29 I/O TTL SSI module 0 frame signal SSI0Rx 30 I TTL SSI module 0 receive SSI0Tx 31 O TTL SSI module 0 transmit SSI1Clk 72 I/O TTL SSI module 1 clock SSI1Fss 73 I/O TTL SSI module 1 frame signal SSI1Rx 74 I TTL SSI module 1 receive SSI1Tx 75 O TTL SSI module 1 transmit CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 48 I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 I TTL System reset input. U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx 12 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 13 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 19 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 18 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. SSI System Control & Clocks a Pin Number UART Description a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.1.4 GPIO Pins and Alternate Functions Table 19-4. GPIO Pins and Alternate Functions IO Pin Number Multiplexed Function PA0 26 U0Rx PA1 27 U0Tx PA2 28 SSI0Clk PA3 29 SSI0Fss PA4 30 SSI0Rx PA5 31 SSI0Tx PA6 34 CCP1 PA7 35 CCP4 PB0 66 PWM2 PB1 67 PWM3 642 Multiplexed Function June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-4. GPIO Pins and Alternate Functions (continued) IO Pin Number Multiplexed Function PB2 70 I2C0SCL PB3 71 I2C0SDA PB4 92 C0- PB5 91 C1- PB6 90 C0+ PB7 89 TRST PC0 80 TCK SWCLK PC1 79 TMS SWDIO PC2 78 TDI PC3 77 TDO PC4 25 CCP5 PC5 24 C1+ C1o PC6 23 C2+ C2o PC7 22 C2- PD0 10 PWM0 PD1 11 PhA0 PD2 12 U1Rx PD3 13 U1Tx PD4 95 CCP0 PD5 96 CCP2 PD6 99 Fault PD7 100 IDX0 PE0 72 SSI1Clk PE1 73 SSI1Fss PE2 74 SSI1Rx PE3 75 SSI1Tx PE4 6 CCP3 PE5 5 PE6 2 PWM4 PE7 1 PWM5 PF0 47 PhB0 PF1 61 PWM1 PF2 60 LED1 PF3 59 LED0 PG0 19 U2Rx PG1 18 U2Tx June 18, 2012 Multiplexed Function C0o SWO 643 Texas Instruments-Production Data Signal Tables 19.2 108-Ball BGA Package Pin Tables 19.2.1 Signals by Pin Number Table 19-5. Signals by Pin Number a Pin Number Pin Name Pin Type Buffer Type A1 NC - - No connect. Leave the pin electrically unconnected/isolated. A2 NC - - No connect. Leave the pin electrically unconnected/isolated. A3 NC - - No connect. Leave the pin electrically unconnected/isolated. No connect. Leave the pin electrically unconnected/isolated. A4 NC - - GNDA - Power PB4 I/O TTL C0- I Analog PB6 I/O TTL C0+ I Analog C0o O TTL Analog comparator 0 output. PB7 I/O TTL GPIO port B bit 7. TRST I TTL JTAG TRST. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. A5 A6 A7 A8 A9 A10 Description The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GPIO port B bit 4. Analog comparator 0 negative input. GPIO port B bit 6. Analog comparator 0 positive input. PE0 I/O TTL GPIO port E bit 0. SSI1Clk I/O TTL SSI module 1 clock PE3 I/O TTL GPIO port E bit 3. SSI module 1 transmit A11 A12 SSI1Tx O TTL B1 NC - - No connect. Leave the pin electrically unconnected/isolated. B2 NC - - No connect. Leave the pin electrically unconnected/isolated. B3 NC - - No connect. Leave the pin electrically unconnected/isolated. No connect. Leave the pin electrically unconnected/isolated. B4 NC - - GNDA - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GND - Power Ground reference for logic and I/O pins. PB5 I/O TTL C1- I Analog PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I/O TTL JTAG TMS and SWDIO. B5 B6 B7 B8 B9 GPIO port B bit 5. Analog comparator 1 negative input. 644 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-5. Signals by Pin Number (continued) Pin Number B10 a Pin Name Pin Type Buffer Type Description CMOD1 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. PE2 I/O TTL GPIO port E bit 2. SSI1Rx I TTL SSI module 1 receive PE1 I/O TTL GPIO port E bit 1. SSI1Fss I/O TTL SSI module 1 frame signal PE7 I/O TTL GPIO port E bit 7. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. PE6 I/O TTL GPIO port E bit 6. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. C4 GND - Power Ground reference for logic and I/O pins. C5 GND - Power Ground reference for logic and I/O pins. VDDA - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. VDDA - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. C8 GNDPHY - Power GND of the Ethernet PHY. C9 GNDPHY - Power GND of the Ethernet PHY. C10 VCCPHY - Power VCC of the Ethernet PHY. PB2 I/O TTL GPIO port B bit 2. I2C0SCL I/O OD I2C module 0 clock. PB3 I/O TTL GPIO port B bit 3. I2C0SDA I/O OD I2C module 0 data. B11 B12 C1 C2 C3 C6 C7 C11 C12 PE4 I/O TTL GPIO port E bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. GPIO port E bit 5. D1 PE5 I/O TTL VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. D10 VCCPHY - Power VCC of the Ethernet PHY. D11 VCCPHY - Power VCC of the Ethernet PHY. D2 D3 PB1 I/O TTL GPIO port B bit 1. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. PD4 I/O TTL GPIO port D bit 4. CCP0 I/O TTL Capture/Compare/PWM 0. D12 E1 June 18, 2012 645 Texas Instruments-Production Data Signal Tables Table 19-5. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type PD5 I/O TTL GPIO port D bit 5. CCP2 I/O TTL Capture/Compare/PWM 2. LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). VDD33 - Power Positive supply for I/O and some logic. CMOD0 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. E2 E3 E10 E11 Description PB0 I/O TTL GPIO port B bit 0. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. PD7 I/O TTL GPIO port D bit 7. IDX0 I TTL QEI module 0 index. PD6 I/O TTL GPIO port D bit 6. PWM Fault. E12 F1 F2 Fault I TTL VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. F10 GND - Power Ground reference for logic and I/O pins. F11 GND - Power Ground reference for logic and I/O pins. F12 GND - Power Ground reference for logic and I/O pins. PD0 I/O TTL GPIO port D bit 0. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. F3 G1 PD1 I/O TTL GPIO port D bit 1. PhA0 I TTL QEI module 0 phase A. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. G10 VDD33 - Power Positive supply for I/O and some logic. G11 VDD33 - Power Positive supply for I/O and some logic. G12 VDD33 - Power Positive supply for I/O and some logic. PD3 I/O TTL GPIO port D bit 3. H1 U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. G2 G3 PD2 I/O TTL GPIO port D bit 2. H2 U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. H3 GND - Power Ground reference for logic and I/O pins. H10 VDD33 - Power Positive supply for I/O and some logic. H11 RST I TTL System reset input. PF1 I/O TTL GPIO port F bit 1. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. XTALNPHY O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. H12 J1 J2 646 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-5. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type J3 GND - Power Ground reference for logic and I/O pins. J10 GND - Power Ground reference for logic and I/O pins. PF2 I/O TTL GPIO port F bit 2. LED1 O TTL Ethernet LED 1. PF3 I/O TTL GPIO port F bit 3. LED0 O TTL Ethernet LED 0. PG0 I/O TTL GPIO port G bit 0. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. J11 J12 K1 Description PG1 I/O TTL GPIO port G bit 1. K2 U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. K3 ERBIAS I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. K4 GNDPHY - Power GND of the Ethernet PHY. K5 GND - Power Ground reference for logic and I/O pins. K6 GND - Power Ground reference for logic and I/O pins. K7 VDD33 - Power Positive supply for I/O and some logic. K8 VDD33 - Power Positive supply for I/O and some logic. K9 VDD33 - Power Positive supply for I/O and some logic. K10 GND - Power Ground reference for logic and I/O pins. XOSC0 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. PC4 I/O TTL GPIO port C bit 4. CCP5 I/O TTL Capture/Compare/PWM 5. PC7 I/O TTL GPIO port C bit 7. C2- I Analog K11 K12 L1 L2 L3 Analog comparator 2 negative input. PA0 I/O TTL GPIO port A bit 0. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame signal L4 PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive L5 PA6 I/O TTL GPIO port A bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. L7 RXIN I Analog RXIN of the Ethernet PHY. L8 TXON O Analog TXON of the Ethernet PHY. L9 MDIO I/O TTL MDIO of the Ethernet PHY. L10 GND - Power Ground reference for logic and I/O pins. L11 OSC0 I Analog Main oscillator crystal input or an external clock reference input. L6 June 18, 2012 647 Texas Instruments-Production Data Signal Tables Table 19-5. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type VBAT - Power PC5 I/O TTL C1+ I Analog C1o O TTL Analog comparator 1 output. PC6 I/O TTL GPIO port C bit 6. C2+ I Analog C2o O TTL Analog comparator 2 output. PA1 I/O TTL GPIO port A bit 1. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. L12 M1 M2 M3 Description Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. GPIO port C bit 5. Analog comparator 1 positive input. Analog comparator 2 positive input. PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock M4 PA5 I/O TTL GPIO port A bit 5. SSI0Tx O TTL SSI module 0 transmit PA7 I/O TTL GPIO port A bit 7. M5 M6 CCP4 I/O TTL Capture/Compare/PWM 4. M7 RXIP I Analog RXIP of the Ethernet PHY. M8 TXOP O Analog TXOP of the Ethernet PHY. PF0 I/O TTL GPIO port F bit 0. PhB0 I TTL QEI module 0 phase B. WAKE I TTL An external input that brings the processor out of Hibernate mode when asserted. OSC1 O Analog HIB O OD M9 M10 M11 M12 Main oscillator crystal output. Leave unconnected when using a single-ended clock source. An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.2.2 Signals by Signal Name Table 19-6. Signals by Signal Name a Pin Name Pin Number Pin Type Buffer Type Description C0+ A7 I Analog Analog comparator 0 positive input. C0- A6 I Analog Analog comparator 0 negative input. C0o A7 O TTL C1+ M1 I Analog Analog comparator 1 positive input. C1- B7 I Analog Analog comparator 1 negative input. C1o M1 O TTL C2+ M2 I Analog Analog comparator 2 positive input. C2- L2 I Analog Analog comparator 2 negative input. C2o M2 O TTL Analog comparator 2 output. CCP0 E1 I/O TTL Capture/Compare/PWM 0. Analog comparator 0 output. Analog comparator 1 output. 648 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-6. Signals by Signal Name (continued) Pin Name a Pin Number Pin Type Buffer Type Description CCP1 L6 I/O TTL Capture/Compare/PWM 1. CCP2 E2 I/O TTL Capture/Compare/PWM 2. CCP3 D1 I/O TTL Capture/Compare/PWM 3. CCP4 M6 I/O TTL Capture/Compare/PWM 4. CCP5 L1 I/O TTL Capture/Compare/PWM 5. CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. ERBIAS K3 I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. Fault F2 I TTL GND B6 C4 C5 F10 F11 F12 H3 J3 J10 K5 K6 K10 L10 - Power Ground reference for logic and I/O pins. GNDA A5 B5 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDPHY C8 C9 K4 - Power GND of the Ethernet PHY. HIB M12 O OD An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. I2C0SCL C11 I/O OD I2C module 0 clock. I2C0SDA C12 I/O OD I2C module 0 data. IDX0 F1 I TTL QEI module 0 index. LDO E3 - Power PWM Fault. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). LED0 J12 O TTL Ethernet LED 0. LED1 J11 O TTL Ethernet LED 1. MDIO L9 I/O TTL MDIO of the Ethernet PHY. June 18, 2012 649 Texas Instruments-Production Data Signal Tables Table 19-6. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description NC A1 A2 A3 A4 B1 B2 B3 B4 - - OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PA0 L3 I/O TTL GPIO port A bit 0. PA1 M3 I/O TTL GPIO port A bit 1. PA2 M4 I/O TTL GPIO port A bit 2. PA3 L4 I/O TTL GPIO port A bit 3. PA4 L5 I/O TTL GPIO port A bit 4. PA5 M5 I/O TTL GPIO port A bit 5. PA6 L6 I/O TTL GPIO port A bit 6. PA7 M6 I/O TTL GPIO port A bit 7. PB0 E12 I/O TTL GPIO port B bit 0. PB1 D12 I/O TTL GPIO port B bit 1. PB2 C11 I/O TTL GPIO port B bit 2. PB3 C12 I/O TTL GPIO port B bit 3. PB4 A6 I/O TTL GPIO port B bit 4. PB5 B7 I/O TTL GPIO port B bit 5. PB6 A7 I/O TTL GPIO port B bit 6. PB7 A8 I/O TTL GPIO port B bit 7. PC0 A9 I/O TTL GPIO port C bit 0. PC1 B9 I/O TTL GPIO port C bit 1. PC2 B8 I/O TTL GPIO port C bit 2. PC3 A10 I/O TTL GPIO port C bit 3. PC4 L1 I/O TTL GPIO port C bit 4. PC5 M1 I/O TTL GPIO port C bit 5. PC6 M2 I/O TTL GPIO port C bit 6. PC7 L2 I/O TTL GPIO port C bit 7. PD0 G1 I/O TTL GPIO port D bit 0. PD1 G2 I/O TTL GPIO port D bit 1. PD2 H2 I/O TTL GPIO port D bit 2. PD3 H1 I/O TTL GPIO port D bit 3. PD4 E1 I/O TTL GPIO port D bit 4. PD5 E2 I/O TTL GPIO port D bit 5. PD6 F2 I/O TTL GPIO port D bit 6. PD7 F1 I/O TTL GPIO port D bit 7. No connect. Leave the pin electrically unconnected/isolated. 650 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-6. Signals by Signal Name (continued) Pin Name a Pin Number Pin Type Buffer Type Description PE0 A11 I/O TTL GPIO port E bit 0. PE1 B12 I/O TTL GPIO port E bit 1. PE2 B11 I/O TTL GPIO port E bit 2. PE3 A12 I/O TTL GPIO port E bit 3. PE4 D1 I/O TTL GPIO port E bit 4. PE5 D2 I/O TTL GPIO port E bit 5. PE6 C2 I/O TTL GPIO port E bit 6. PE7 C1 I/O TTL GPIO port E bit 7. PF0 M9 I/O TTL GPIO port F bit 0. PF1 H12 I/O TTL GPIO port F bit 1. PF2 J11 I/O TTL GPIO port F bit 2. PF3 J12 I/O TTL GPIO port F bit 3. PG0 K1 I/O TTL GPIO port G bit 0. PG1 K2 I/O TTL GPIO port G bit 1. PhA0 G2 I TTL QEI module 0 phase A. PhB0 M9 I TTL QEI module 0 phase B. PWM0 G1 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 H12 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 E12 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 D12 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 C2 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 C1 O TTL PWM 5. This signal is controlled by PWM Generator 2. RST H11 I TTL System reset input. RXIN L7 I Analog RXIN of the Ethernet PHY. RXIP M7 I Analog RXIP of the Ethernet PHY. SSI0Clk M4 I/O TTL SSI module 0 clock SSI0Fss L4 I/O TTL SSI module 0 frame signal SSI0Rx L5 I TTL SSI module 0 receive SSI0Tx M5 O TTL SSI module 0 transmit SSI1Clk A11 I/O TTL SSI module 1 clock SSI1Fss B12 I/O TTL SSI module 1 frame signal SSI1Rx B11 I TTL SSI module 1 receive SSI1Tx A12 O TTL SSI module 1 transmit SWCLK A9 I TTL JTAG/SWD CLK. SWDIO B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I/O TTL JTAG TMS and SWDIO. TRST A8 I TTL JTAG TRST. June 18, 2012 651 Texas Instruments-Production Data Signal Tables Table 19-6. Signals by Signal Name (continued) Pin Name a Pin Number Pin Type Buffer Type Description TXON L8 O Analog TXON of the Ethernet PHY. TXOP M8 O Analog TXOP of the Ethernet PHY. U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx H2 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx H1 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx K1 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx K2 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. VBAT L12 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. VCCPHY C10 D10 D11 - Power VCC of the Ethernet PHY. VDD25 C3 D3 F3 G3 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD33 E10 G10 G11 G12 H10 K7 K8 K9 - Power Positive supply for I/O and some logic. VDDA C6 C7 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. WAKE M10 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 K11 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. XTALNPHY J1 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY J2 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 652 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 19.2.3 Signals by Function, Except for GPIO Table 19-7. Signals by Function, Except for GPIO Function Analog Comparators Ethernet General-Purpose Timers Pin Name a Pin Number Pin Type Buffer Type C0+ A7 I Analog Analog comparator 0 positive input. Description C0- A6 I Analog Analog comparator 0 negative input. C0o A7 O TTL C1+ M1 I Analog Analog comparator 1 positive input. Analog comparator 1 negative input. Analog comparator 0 output. C1- B7 I Analog C1o M1 O TTL C2+ M2 I Analog Analog comparator 2 positive input. Analog comparator 2 negative input. Analog comparator 1 output. C2- L2 I Analog C2o M2 O TTL ERBIAS K3 I Analog 12.4-k resistor (1% precision) used internally for Ethernet PHY. GNDPHY C8 C9 K4 - Power GND of the Ethernet PHY. LED0 J12 O TTL Ethernet LED 0. LED1 J11 O TTL Ethernet LED 1. MDIO L9 I/O TTL MDIO of the Ethernet PHY. RXIN L7 I Analog RXIN of the Ethernet PHY. RXIP M7 I Analog RXIP of the Ethernet PHY. TXON L8 O Analog TXON of the Ethernet PHY. TXOP M8 O Analog TXOP of the Ethernet PHY. VCCPHY C10 D10 D11 - Power VCC of the Ethernet PHY. XTALNPHY J1 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect this pin to ground when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY J2 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. CCP0 E1 I/O TTL Capture/Compare/PWM 0. CCP1 L6 I/O TTL Capture/Compare/PWM 1. CCP2 E2 I/O TTL Capture/Compare/PWM 2. CCP3 D1 I/O TTL Capture/Compare/PWM 3. CCP4 M6 I/O TTL Capture/Compare/PWM 4. CCP5 L1 I/O TTL Capture/Compare/PWM 5. Analog comparator 2 output. June 18, 2012 653 Texas Instruments-Production Data Signal Tables Table 19-7. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type HIB M12 O OD VBAT L12 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE M10 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 K11 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. I2C0SCL C11 I/O OD I2C module 0 clock. I2C0SDA C12 I/O OD I2C module 0 data. A9 I TTL JTAG/SWD CLK. SWDIO B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I/O TTL JTAG TMS and SWDIO. TRST A8 I TTL JTAG TRST. Hibernate I2C SWCLK JTAG/SWD/SWO Description An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. Fault F2 I TTL PWM Fault. PWM0 G1 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 H12 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 E12 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 D12 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 C2 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 C1 O TTL PWM 5. This signal is controlled by PWM Generator 2. PWM 654 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-7. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND B6 C4 C5 F10 F11 F12 H3 J3 J10 K5 K6 K10 L10 - Power Ground reference for logic and I/O pins. GNDA A5 B5 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO E3 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). VDD25 C3 D3 F3 G3 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD33 E10 G10 G11 G12 H10 K7 K8 K9 - Power Positive supply for I/O and some logic. VDDA C6 C7 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in "Recommended DC Operating Conditions" on page 661, regardless of system implementation. IDX0 F1 I TTL QEI module 0 index. PhA0 G2 I TTL QEI module 0 phase A. PhB0 M9 I TTL QEI module 0 phase B. Power QEI Description June 18, 2012 655 Texas Instruments-Production Data Signal Tables Table 19-7. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Type Buffer Type SSI0Clk M4 I/O TTL SSI module 0 clock SSI0Fss L4 I/O TTL SSI module 0 frame signal SSI0Rx L5 I TTL SSI module 0 receive Description SSI0Tx M5 O TTL SSI module 0 transmit SSI1Clk A11 I/O TTL SSI module 1 clock SSI1Fss B12 I/O TTL SSI module 1 frame signal SSI1Rx B11 I TTL SSI module 1 receive SSI1Tx A12 O TTL SSI module 1 transmit CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST SSI System Control & Clocks a Pin Number H11 I TTL System reset input. U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx H2 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx H1 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx K1 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx K2 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. UART a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.2.4 GPIO Pins and Alternate Functions Table 19-8. GPIO Pins and Alternate Functions IO Pin Number Multiplexed Function PA0 L3 U0Rx PA1 M3 U0Tx PA2 M4 SSI0Clk PA3 L4 SSI0Fss PA4 L5 SSI0Rx PA5 M5 SSI0Tx PA6 L6 CCP1 PA7 M6 CCP4 PB0 E12 PWM2 PB1 D12 PWM3 656 Multiplexed Function June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-8. GPIO Pins and Alternate Functions (continued) IO 19.3 Pin Number Multiplexed Function Multiplexed Function PB2 C11 I2C0SCL PB3 C12 I2C0SDA PB4 A6 C0- PB5 B7 C1- PB6 A7 C0+ PB7 A8 TRST PC0 A9 TCK SWCLK PC1 B9 TMS SWDIO PC2 B8 TDI PC3 A10 TDO C0o SWO PC4 L1 CCP5 PC5 M1 C1+ C1o PC6 M2 C2+ C2o PC7 L2 C2- PD0 G1 PWM0 PD1 G2 PhA0 PD2 H2 U1Rx PD3 H1 U1Tx PD4 E1 CCP0 PD5 E2 CCP2 PD6 F2 Fault PD7 F1 IDX0 PE0 A11 SSI1Clk PE1 B12 SSI1Fss PE2 B11 SSI1Rx PE3 A12 SSI1Tx PE4 D1 CCP3 PE5 D2 PE6 C2 PWM4 PE7 C1 PWM5 PF0 M9 PhB0 PF1 H12 PWM1 PF2 J11 LED1 PF3 J12 LED0 PG0 K1 U2Rx PG1 K2 U2Tx Connections for Unused Signals Table 19-9 on page 658 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 100-pin LQFP package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it June 18, 2012 657 Texas Instruments-Production Data Signal Tables is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. Table 19-9. Connections for Unused Signals (100-pin LQFP) Function Signal Name Pin Number Acceptable Practice Preferred Practice ERBIAS 41 Connect to GND through 12.4-k resistor. Connect to GND through 12.4-k resistor. GNDPHY 42 GND GND 85 86 Ethernet a MDIO 58 NC NC RXIN 37 NC GND RXIP 40 NC GND TXON 46 NC GND TXOP 43 NC GND VCCPHY 36 VDD VDD 83 84 a 17 NC NC a XTALNPHY GPIO Hibernate No Connects System Control XTALPPHY 16 NC GND All unused GPIOs - NC GND HIB 51 NC NC VBAT 55 NC GND WAKE 50 NC GND XOSC0 52 NC GND XOSC1 53 NC NC NC - NC NC OSC0 48 NC GND OSC1 49 NC NC RST 64 Pull up as shown in Figure Connect through a capacitor to 5-1 on page 172 GND as close to pin as possible a. Note that the Ethernet PHY is powered up by default. The PHY cannot be powered down unless a clock source is provided and the MDIO pin is pulled up through a 10-k resistor. Table 19-10 on page 659 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 108-pin BGA package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. 658 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 19-10. Connections for Unused Signals, 108-pin BGA Function Signal Name Pin Number Acceptable Practice Preferred Practice ERBIAS K3 Connect to GND through 12.4-k resistor. Connect to GND through 12.4-k resistor. GNDPHY C8 GND GND C9 K4 Ethernet a MDIO L9 NC NC RXIN L7 NC GND RXIP M7 NC GND TXON L8 NC GND TXOP M8 NC GND VCCPHY C10 VDD VDD D10 D11 a J1 NC NC a XTALNPHY GPIO Hibernate No Connects System Control XTALPPHY J2 NC GND All unused GPIOs - NC GND HIB M12 NC NC VBAT L12 NC GND WAKE M10 NC GND XOSC0 K11 NC GND XOSC1 K12 NC NC NC - NC NC OSC0 L11 NC GND OSC1 M11 NC NC RST H11 Pull up as shown in Figure Connect through a capacitor to 5-1 on page 172 GND as close to pin as possible a. Note that the Ethernet PHY is powered up by default. The PHY cannot be powered down unless a clock source is provided and the MDIO pin is pulled up through a 10-k resistor. June 18, 2012 659 Texas Instruments-Production Data Operating Characteristics 20 Operating Characteristics Table 20-1. Temperature Characteristics Characteristic Symbol Value Industrial operating temperature range TA -40 to +85 Unit C Unpowered storage temperature range TS -65 to +150 C Table 20-2. Thermal Characteristics Characteristic a Thermal resistance (junction to ambient) b Junction temperature Symbol Value JA 32 Unit TJ TA + (P * JA) C/W C a. Junction to ambient thermal resistance JA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. a Table 20-3. ESD Absolute Maximum Ratings Parameter Name VESDHBM Min Nom Max Unit - - 2.0 kV VESDCDM - - 1.0 kV VESDMM - - 100 V a. All Stellaris parts are ESD tested following the JEDEC standard. 660 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 21 Electrical Characteristics 21.1 DC Characteristics 21.1.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 21-1. Maximum Ratings a Characteristic Symbol I/O supply voltage (VDD) Value Unit Min Max VDD 0 4 V Core supply voltage (VDD25) VDD25 0 3 V Analog supply voltage (VDDA) VDDA 0 4 V Battery supply voltage (VBAT) VBAT 0 4 V Ethernet PHY supply voltage (VCCPHY) Input voltage Input voltage for a GPIO configured as an analog input VCCPHY VIN Maximum current per output pins Maximum input voltage on a non-power pin when the microcontroller is unpowered 0 4 V -0.3 5.5 V -0.3 VDD + 0.3 V I - 25 mA VNON - 300 mV a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD). 21.1.2 Recommended DC Operating Conditions For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. Table 21-2. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD I/O supply voltage 3.0 3.3 3.6 V VDD25 Core supply voltage 2.25 2.5 2.75 V VDDA Analog supply voltage 3.0 3.3 3.6 V VBAT Battery supply voltage 2.3 3.0 3.6 V Ethernet PHY supply voltage 3.0 3.3 3.6 V VCCPHY June 18, 2012 661 Texas Instruments-Production Data Electrical Characteristics Table 21-2. Recommended DC Operating Conditions (continued) Parameter Parameter Name Min Nom Max Unit VIH High-level input voltage 2.0 - 5.0 V VIL Low-level input voltage -0.3 - 1.3 V a VOH High-level output voltage 2.4 - - V VOLa Low-level output voltage - - 0.4 V 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA High-level source current, VOH=2.4 V IOH Low-level sink current, VOL=0.4 V IOL a. VOL and VOH shift to 1.2 V when using high-current GPIOs. 21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics Table 21-3. LDO Regulator Characteristics Parameter Parameter Name Min Nom Max Unit Programmable internal (logic) power supply output value 2.25 2.5 2.75 V Output voltage accuracy - 2% - % tPON Power-on time - - 100 s tON Time on - - 200 s tOFF Time off - - 100 s VSTEP Step programming incremental voltage - 50 - mV CLDO External filter capacitor size for internal power supply 1.0 - 3.0 F Min Nom Max Unit VLDOOUT 21.1.4 GPIO Module Characteristics Table 21-4. GPIO Module DC Characteristics Parameter Parameter Name RGPIOPU GPIO internal pull-up resistor 50 - 110 k RGPIOPD GPIO internal pull-down resistor 55 - 180 k - - 2 A ILKG a GPIO input leakage current a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled. 21.1.5 Power Specifications The power measurements specified in the tables that follow are run on the core processor using SRAM with the following specifications (except as noted): VDD = 3.3 V 662 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller VDD25 = 2.50 V VBAT = 3.0 V VDDA = 3.3 V VDDPHY = 3.3 V Temperature = 25C Clock Source (MOSC) =3.579545 MHz Crystal Oscillator Main oscillator (MOSC) = enabled Internal oscillator (IOSC) = disabled Table 21-5. Detailed Power Specifications Parameter Parameter Name Run mode 1 (Flash loop) Conditions VDD25 = 2.50 V 3.3 V VDD, VDDA, VDDPHY 2.5 V VDD25 3.0 V VBAT Unit Nom Max Nom Max 48 pending Nom 108 pendinga 0 pendinga mA 5 pendinga 52 pendinga 0 pendinga mA 48 pendinga 100 pendinga 0 pendinga mA 5 pendinga 45 pendinga 0 pendinga mA 5 pendinga 16 pendinga 0 pendinga mA pendinga 0.21 pendinga 0 pendinga mA a Max Code= while(1){} executed out of Flash Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (Flash loop) VDD25 = 2.50 V Code= while(1){} executed out of Flash Peripherals = All OFF IDD_RUN System Clock = 50 MHz (with PLL) Run mode 1 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_SLEEP Sleep mode VDD25 = 2.50 V Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_DEEPSLEEP Deep-Sleep mode LDO = 2.25 V 4.6 Peripherals = All OFF System Clock = IOSC30KHZ/64 June 18, 2012 663 Texas Instruments-Production Data Electrical Characteristics Table 21-5. Detailed Power Specifications (continued) Parameter Parameter Name Conditions 3.3 V VDD, VDDA, VDDPHY 3.0 V VBAT Unit Nom Max Nom Max Nom Max 0 0 0 0 16 pendinga VBAT = 3.0 V IDD_HIBERNATE Hibernate mode 2.5 V VDD25 A VDD = 0 V VDD25 = 0 V VDDA = 0 V VDDPHY = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 32 kHz a. Pending characterization completion. 21.1.6 Flash Memory Characteristics Table 21-6. Flash Memory Characteristics Parameter Min Nom Max Unit 10,000 100,000 - cycles Data retention at average operating temperature of 85C 10 - - years TPROG Word program time 20 - - s TERASE Page erase time 20 - - ms TME Mass erase time - - 250 ms PECYC TRET Parameter Name Number of guaranteed program/erase cycles a before failure a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 21.1.7 Hibernation Table 21-7. Hibernation Module DC Characteristics Parameter 21.1.8 Parameter Name Value Unit VLOWBAT Low battery detect voltage 2.35 V RWAKEPU WAKE internal pull-up resistor 200 k Ethernet Controller Table 21-8. Ethernet Controller DC Characteristics Parameter REBIAS Parameter Name Value of the pull-down resistor on the ERBIAS pin 21.2 AC Characteristics 21.2.1 Load Conditions Value Unit 12.4K 1 % Unless otherwise specified, the following conditions are true for all timing measurements. Timing measurements are for 4-mA drive strength. 664 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 21-1. Load Conditions CL = 50 pF pin GND 21.2.2 Clocks Table 21-9. Phase Locked Loop (PLL) Characteristics Min Nom Max Unit fref_crystal Parameter Crystal reference Parameter Name 3.579545 - 8.192 MHz fref_ext External clock referencea 3.579545 - 8.192 MHz a b fpll PLL frequency - 400 - MHz TREADY PLL lock time - - 0.5 ms a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. Table 21-10 on page 665 shows the actual frequency of the PLL based on the crystal frequency used (defined by the XTAL field in the RCC register). Table 21-10. Actual PLL Frequency XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0x4 3.5795 400.904 0.0023% 0x5 3.6864 398.1312 0.0047% 0x6 4.0 400 - 0x7 4.096 401.408 0.0035% 0x8 4.9152 398.1312 0.0047% 0x9 5.0 400 - 0xA 5.12 399.36 0.0016% 0xB 6.0 400 - 0xC 6.144 399.36 0.0016% 0xD 7.3728 398.1312 0.0047% 0xE 8.0 400 0.0047% 0xF 8.192 398.6773333 0.0033% Table 21-11. Clock Characteristics Parameter Parameter Name Min Nom Max Unit fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz fIOSC30KHZ Internal 30 KHz oscillator frequency 15 30 45 KHz fXOSC Hibernation module oscillator frequency - 4.194304 - MHz fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz June 18, 2012 665 Texas Instruments-Production Data Electrical Characteristics Table 21-11. Clock Characteristics (continued) Parameter Parameter Name fXOSC_EXT External clock reference for hibernation module fMOSC Main oscillator frequency tMOSC_per Main oscillator period fref_crystal_bypass Min Nom Max Unit - 32.768 - KHz 1 - 8.192 MHz 125 - 1000 ns Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8.192 MHz fref_ext_bypass External clock reference (PLL in BYPASS mode) 0 - 50 MHz fsystem_clock System clock 0 - 50 MHz Table 21-12. Crystal Characteristics Parameter Name Value Frequency Frequency tolerance Aging 8 6 4 3.5 MHz 50 50 50 50 ppm 5 5 5 5 ppm/yr Parallel Parallel Parallel Parallel - Temperature stability (-40C to 85C) 25 25 25 25 ppm Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF Motional inductance (typ) 14.3 19.1 28.6 32.7 mH Equivalent series resistance (max) 120 160 200 220 Shunt capacitance (max) 10 10 10 10 pF Oscillation mode 21.2.3 Units Load capacitance (typ) 16 16 16 16 pF Drive level (typ) 100 100 100 100 W JTAG and Boundary Scan Table 21-13. JTAG Characteristics Parameter No. Parameter Parameter Name J1 fTCK TCK operational clock frequency J2 tTCK TCK operational clock period Min Nom Max Unit 0 - 10 MHz 100 - - ns J3 tTCK_LOW TCK clock Low time - tTCK/2 - ns J4 tTCK_HIGH TCK clock High time - tTCK/2 - ns J5 tTCK_R TCK rise time 0 - 10 ns J6 tTCK_F TCK fall time 0 - 10 ns J7 tTMS_SU TMS setup time to TCK rise 20 - - ns J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns J9 tTDI_SU TDI setup time to TCK rise 25 - - ns J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns 23 35 ns 2-mA drive J11 t TDO_ZDV TCK fall to Data Valid from High-Z 4-mA drive 8-mA drive 8-mA drive with slew rate control 666 - 15 26 ns 14 25 ns 18 29 ns June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 21-13. JTAG Characteristics (continued) Parameter No. Parameter J12 TCK fall to Data Valid from Data Valid Parameter Name Min Nom Max Unit 21 35 ns 2-mA drive t TDO_DV J13 t TDO_DVZ 4-mA drive 14 25 ns 13 24 ns 8-mA drive with slew rate control 18 28 ns 2-mA drive 9 11 ns 7 9 ns 6 8 ns 7 9 ns - 8-mA drive 4-mA drive TCK fall to High-Z from Data Valid - 8-mA drive 8-mA drive with slew rate control J14 tTRST J15 tTRST_SU TRST assertion time 100 - - ns TRST setup time to TCK rise 10 - - ns Figure 21-2. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 Figure 21-3. JTAG Test Access Port (TAP) Timing TCK J7 TMS TDI J8 J8 TMS Input Valid TMS Input Valid J9 J9 J10 TDI Input Valid J11 TDO J7 J10 TDI Input Valid J12 TDO Output Valid June 18, 2012 J13 TDO Output Valid 667 Texas Instruments-Production Data Electrical Characteristics Figure 21-4. JTAG TRST Timing TCK J14 J15 TRST 21.2.4 Reset Table 21-14. Reset Characteristics Parameter No. Parameter Parameter Name Min R1 VTH Reset threshold R2 VBTH Brown-Out threshold R3 TPOR R4 TBOR R5 TIRPOR Internal reset timeout after POR R6 TIRBOR Internal reset timeout after BOR R7 TIRHWR Internal reset timeout after hardware reset (RST pin) R8 TIRSWR R9 TIRWDR R10 TVDDRISE R11 TMIN Nom Max Unit - 2.0 - V 2.85 2.9 2.95 V Power-On Reset timeout - 10 - ms Brown-Out timeout - 500 - s 6 - 11 ms 0 - 1 s 0 - 1 ms Internal reset timeout after software-initiated system reset a 2.5 - 20 s Internal reset timeout after watchdog reseta 2.5 - 20 s Supply voltage (VDD) rise time (0V-3.3V), power on reset - - 100 ms Supply voltage (VDD) rise time (0V-3.3V), waking from hibernation - - 250 s Minimum RST pulse width 2 - - s a a. 20 * t MOSC_per Figure 21-5. External Reset Timing (RST) RST R11 R7 /Reset (Internal) 668 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Figure 21-6. Power-On Reset Timing R1 VDD R3 /POR (Internal) R5 /Reset (Internal) Figure 21-7. Brown-Out Reset Timing R2 VDD R4 /BOR (Internal) R6 /Reset (Internal) Figure 21-8. Software Reset Timing SW Reset R8 /Reset (Internal) Figure 21-9. Watchdog Reset Timing WDOG Reset (Internal) R9 /Reset (Internal) June 18, 2012 669 Texas Instruments-Production Data Electrical Characteristics 21.2.5 Sleep Modes a Table 21-15. Sleep Modes AC Characteristics Parameter No Parameter Min Nom Max Unit D1 tWAKE_S Time to wake from interrupt in sleep or deep-sleep mode, not using the PLL Parameter Name - - 7 system clocks D2 tWAKE_PLL_S Time to wake from interrupt in sleep or deep-sleep mode when using the PLL - - TREADY ms a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode. 21.2.6 Hibernation Module The Hibernation Module requires special system implementation considerations since it is intended to power-down all other sections of its host device. The system power-supply distribution and interfaces to the device must be driven to 0 VDC or powered down with the same external voltage regulator controlled by HIB. The external voltage regulators controlled by HIB must have a settling time of 250 s or less. Table 21-16. Hibernation Module AC Characteristics Parameter No Parameter H1 tHIB_LOW H2 tHIB_HIGH H3 tWAKE_ASSERT H4 tWAKETOHIB Parameter Name Min Nom Max Unit Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - s Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - s /WAKE assertion time 62 - - s /WAKE assert to /HIB desassert 62 - 124 s a H5 tXOSC_SETTLE XOSC settling time 20 - - ms H6 tHIB_REG_ACCESS Access time to or from a non-volatile register in HIB module to complete 92 - - s H7 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum operational level - - 250 s a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance). Figure 21-10. Hibernation Module Timing 32.768 KHz (internal) H1 H2 HIB H4 WAKE H3 21.2.7 General-Purpose I/O (GPIO) Note: All GPIOs are 5 V-tolerant. 670 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 21-17. GPIO Characteristics Parameter Parameter Name Condition tGPIOR tGPIOF Min GPIO Rise Time (from 20% to 80% of VDD) Nom Max Unit 2-mA drive 17 26 ns 4-mA drive 9 13 ns - 6 9 ns 8-mA drive with slew rate control 8-mA drive 10 12 ns 2-mA drive 17 25 ns 4-mA drive 8 12 ns 6 10 ns 11 13 ns GPIO Fall Time (from 80% to 20% of VDD) - 8-mA drive 8-mA drive with slew rate control 21.2.8 Synchronous Serial Interface (SSI) Table 21-18. SSI Characteristics Parameter No. Parameter Parameter Name Min S1 tclk_per SSIClk cycle time S2 tclk_high SSIClk high time S3 tclk_low SSIClk low time a Nom Max Unit 2 - 65024 system clocks - 0.5 - t clk_per - 0.5 - t clk_per S4 tclkrf SSIClk rise/fall time - 6 10 ns S5 tDMd Data from master valid delay time 0 - 1 system clocks S6 tDMs Data from master setup time 1 - - system clocks S7 tDMh Data from master hold time 2 - - system clocks S8 tDSs Data from slave setup time 1 - - system clocks S9 tDSh Data from slave hold time 2 - - system clocks a. Note that the delays shown are using 8-mA drive strength. Figure 21-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S2 S4 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits June 18, 2012 671 Texas Instruments-Production Data Electrical Characteristics Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data Figure 21-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S4 S2 SSIClk (SPO=0) S3 SSIClk (SPO=1) S6 SSITx (master) S7 MSB S5 SSIRx (slave) S8 LSB S9 MSB LSB SSIFss 21.2.9 Inter-Integrated Circuit (I2C) Interface Table 21-19. I2C Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit a tSCH Start condition hold time 36 - - system clocks a tLP Clock Low period 36 - - system clocks b tSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns I1 I2 I3 672 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 21-19. I2C Characteristics (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit a tDH Data hold time 2 - - system clocks c tSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns a tHT Clock High time 24 - - system clocks a tDS Data setup time 18 - - system clocks a tSCSR Start condition setup time (for repeated start condition only) 36 - - system clocks a tSCS Stop condition setup time 24 - - system clocks I4 I5 I6 I7 I8 I9 a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above values are minimum values. b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. Specified at a nominal 50 pF load. Figure 21-14. I2C Timing I2 I5 I6 I2CSCL I1 I4 I7 I8 I3 I9 I2CSDA 21.2.10 Ethernet Controller a Table 21-20. 100BASE-TX Transmitter Characteristics Parameter Name Min Nom Max Unit Peak output amplitude 950 - 1050 mVpk Output amplitude symmetry 98 - 102 % Output overshoot - - 5 % Rise/Fall time 3 - 5 ns Rise/Fall time imbalance - - 500 ps Duty cycle distortion - - - ps Jitter - - 1.4 ns a. Measured at the line side of the transformer. a Table 21-21. 100BASE-TX Transmitter Characteristics (informative) Parameter Name Min Nom Max Unit Return loss 16 - - dB Open-circuit inductance 350 - - H a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. June 18, 2012 673 Texas Instruments-Production Data Electrical Characteristics Table 21-22. 100BASE-TX Receiver Characteristics Parameter Name Min Nom Max Unit Signal detect assertion threshold 600 700 - mVppd Signal detect de-assertion threshold 350 425 - mVppd Differential input resistance - 20 - k Jitter tolerance (pk-pk) 4 - - ns Baseline wander tracking -75 - +75 % Signal detect assertion time - - 1000 s Signal detect de-assertion time - - 4 s Unit a Table 21-23. 10BASE-T Transmitter Characteristics Parameter Name Min Nom Max Peak differential output signal 2.2 - 2.8 V Harmonic content 27 - - dB Link pulse width - 100 - ns Start-of-idle pulse width - 300 - ns 350 a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. a Table 21-24. 10BASE-T Transmitter Characteristics (informative) Parameter Name Min Nom Max Unit Output return loss 15 - - dB 29-17log(f/10) - - dB Peak common-mode output voltage - - 50 mV Common-mode rejection - - 100 mV Common-mode rejection jitter - - 1 ns Output impedance balance a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 21-25. 10BASE-T Receiver Characteristics Parameter Name Min Nom Max Unit Jitter tolerance (pk-pk) 30 - - ns Input squelched threshold 500 600 700 mVppd Differential input resistance - 20 - k 25 - - V Common-mode rejection a Table 21-26. Isolation Transformers Name Value Condition 1 CT : 1 CT +/- 5% Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz Leakage inductance 0.40 uH (max) @ 1 MHz (min) Turns ratio Inter-winding capacitance DC resistance 25 pF (max) 0.9 Ohm (max) 674 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Table 21-26. Isolation Transformers (continued) Name Insertion loss HIPOT Value Condition 0.4 dB (typ) 0-65 MHz 1500 Vrms a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO) bits in the MR19 register. a Table 21-27. Ethernet Reference Crystal Name Frequency Value Condition 25.00000 MHz Frequency tolerance 50 PPM Aging 2 PPM/yr Temperature stability (-40 to 85) 5 PPM Oscillation mode Parallel resonance, fundamental mode Parameters at 25 C 2 C; Drive level = 0.5 mW Drive level (typ) 50-100 W Shunt capacitance (max) 10 pF Motional capacitance (min) 10 fF Series resistance (max) 60 Spurious response (max) > 5 dB below main within 500 kHz a. If the internal crystal oscillator is used, select a crystal that meets these specifications. Figure 21-15. External XTLP Oscillator Characteristics Tr Tf Tclkhi Tclklo Tclkper June 18, 2012 675 Texas Instruments-Production Data Electrical Characteristics Table 21-28. External XTLP Oscillator Characteristics Parameter Name Symbol Min XTLN Input Low Voltage XTLNILV XTLPf XTLP Period XTLP Duty Cycle a XTLP Frequency b Nom Max Unit - - 0.8 - - 25.0 - - Tclkper - 40 - - XTLPDC 40 - 60 % 40 60 Rise/Fall Time Tr , Tf - - 4.0 ns Absolute Jitter TJITTER - - 0.1 ns a. IEEE 802.3 frequency tolerance 50 ppm. b. IEEE 802.3 frequency tolerance 50 ppm. 21.2.11 Analog Comparator Table 21-29. Analog Comparator Characteristics Parameter Parameter Name Min Nom Max Unit VOS Input offset voltage - 10 25 mV VCM Input common mode voltage range 0 - VDD-1.5 V CMRR Common mode rejection ratio 50 - - dB TRT Response time - - 1 s TMC Comparator mode change to Output Valid - - 10 s Table 21-30. Analog Comparator Voltage Reference Characteristics Parameter Min Nom Max Unit RHR Resolution high range Parameter Name - VDD/31 - LSB RLR Resolution low range - VDD/23 - LSB AHR Absolute accuracy high range - - 1/2 LSB ALR Absolute accuracy low range - - 1/4 LSB 676 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller A Serial Flash Loader A.1 Serial Flash Loader (R) The Stellaris serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. The serial flash loader uses a simple packet interface to provide synchronous communication with the device. The flash loader runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used. The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both the data format and communication protocol are identical for both serial interfaces. A.2 Interfaces Once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over. For example, once you start communicating using the SSI port, communications with the flash loader via the UART are disabled until the device is reset. A.2.1 UART The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. The auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device which is calculated as follows: Max Baud Rate = System Clock Frequency / 16 In order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. This is enough information for the flash loader to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. The method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the UART to match the host's baud rate. After the host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has received a synchronization pattern correctly. For example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35 ms. A.2.2 SSI The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications, with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See "Frame Formats" on page 438 in the SSI chapter for more information on formats for this transfer protocol. Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running June 18, 2012 677 Texas Instruments-Production Data Serial Flash Loader the flash loader. Since the host device is the master, the SSI on the flash loader device does not need to determine the clock as it is provided directly by the host. A.3 Packet Handling All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. A.3.1 Packet Format All packets sent and received from the device use the following byte-packed format. struct { unsigned char ucSize; unsigned char ucCheckSum; unsigned char Data[]; }; A.3.2 ucSize The first byte received holds the total size of the transfer including the size and checksum bytes. ucChecksum This holds a simple checksum of the bytes in the data buffer only. The algorithm is Data[0]+Data[1]+...+ Data[ucSize-3]. Data This is the raw data intended for the device, which is formatted in some form of command interface. There should be ucSize-2 bytes of data provided in this buffer to or from the device. Sending Packets The actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. This limitation is discussed further in the section that describes the serial flash loader command, COMMAND_SEND_DATA (see "COMMAND_SEND_DATA (0x24)" on page 680). Once the packet has been formatted correctly by the host, it should be sent out over the UART or SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly. A.3.3 Receiving Packets The flash loader sends a packet of data in the same format that it receives a packet. The flash loader may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. There is no break in the data after the first non-zero byte is sent from the flash loader. Once the device communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to indicate that the transmission was successful. The appropriate response after sending a NAK to the flash loader is to resend the command that failed and request the data again. If needed, the host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the 678 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller flash loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the flash loader. A.4 Commands The next section defines the list of commands that can be sent to the flash loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. A.4.1 COMMAND_PING (0X20) This command simply accepts the command and sets the global status to success. The format of the packet is as follows: Byte[0] = 0x03; Byte[1] = checksum(Byte[2]); Byte[2] = COMMAND_PING; The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status, the receipt of an ACK can be interpreted as a successful ping to the flash loader. A.4.2 COMMAND_GET_STATUS (0x23) This command returns the status of the last command that was issued. Typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. The command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. The last step is to ACK or NAK the received data so the flash loader knows that the data has been read. Byte[0] = 0x03 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_GET_STATUS A.4.3 COMMAND_DOWNLOAD (0x21) This command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. This command also triggers an erase of the full area to be programmed so this command takes longer than other commands. This results in a longer time to receive the ACK/NAK back from the board. This command should be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size are valid for the device running the flash loader. The format of the packet to send this command is a follows: Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] Byte[7] = = = = = = = = 11 checksum(Bytes[2:10]) COMMAND_DOWNLOAD Program Address [31:24] Program Address [23:16] Program Address [15:8] Program Address [7:0] Program Size [31:24] June 18, 2012 679 Texas Instruments-Production Data Serial Flash Loader Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0] A.4.4 COMMAND_SEND_DATA (0x24) This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands automatically increment address and continue programming from the previous location. The caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buffers of the serial interfaces. The command terminates programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK to this command, the flash loader does not increment the current address to allow retransmission of the previous data. Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_SEND_DATA Byte[3] = Data[0] Byte[4] = Data[1] Byte[5] = Data[2] Byte[6] = Data[3] Byte[7] = Data[4] Byte[8] = Data[5] Byte[9] = Data[6] Byte[10] = Data[7] A.4.5 COMMAND_RUN (0x22) This command is used to tell the flash loader to execute from the address passed as the parameter in this command. This command consists of a single 32-bit value that is interpreted as the address to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK signal back to the host device before actually executing the code at the given address. This allows the host to know that the command was received successfully and the code is now running. Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] A.4.6 = = = = = = = 7 checksum(Bytes[2:6]) COMMAND_RUN Execute Address[31:24] Execute Address[23:16] Execute Address[15:8] Execute Address[7:0] COMMAND_RESET (0x25) This command is used to tell the flash loader device to reset. This is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. Unlike the COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set up for the new code. It can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader. 680 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET The flash loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the flash loader. This allows the host to know that the command was received successfully and the part will be reset. June 18, 2012 681 Texas Instruments-Production Data Register Quick Reference B Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The Cortex-M3 Processor R0, type R/W, , reset - (see page 58) DATA DATA R1, type R/W, , reset - (see page 58) DATA DATA R2, type R/W, , reset - (see page 58) DATA DATA R3, type R/W, , reset - (see page 58) DATA DATA R4, type R/W, , reset - (see page 58) DATA DATA R5, type R/W, , reset - (see page 58) DATA DATA R6, type R/W, , reset - (see page 58) DATA DATA R7, type R/W, , reset - (see page 58) DATA DATA R8, type R/W, , reset - (see page 58) DATA DATA R9, type R/W, , reset - (see page 58) DATA DATA R10, type R/W, , reset - (see page 58) DATA DATA R11, type R/W, , reset - (see page 58) DATA DATA R12, type R/W, , reset - (see page 58) DATA DATA SP, type R/W, , reset - (see page 59) SP SP LR, type R/W, , reset 0xFFFF.FFFF (see page 60) LINK LINK PC, type R/W, , reset - (see page 61) PC PC 682 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR, type R/W, , reset 0x0100.0000 (see page 62) N Z C V Q ICI / IT THUMB ICI / IT ISRNUM PRIMASK, type R/W, , reset 0x0000.0000 (see page 66) PRIMASK FAULTMASK, type R/W, , reset 0x0000.0000 (see page 67) FAULTMASK BASEPRI, type R/W, , reset 0x0000.0000 (see page 68) BASEPRI CONTROL, type R/W, , reset 0x0000.0000 (see page 69) ASP TMPL INTEN ENABLE Cortex-M3 Peripherals System Timer (SysTick) Registers Base 0xE000.E000 STCTRL, type R/W, offset 0x010, reset 0x0000.0000 COUNT CLK_SRC STRELOAD, type R/W, offset 0x014, reset 0x0000.0000 RELOAD RELOAD STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000 CURRENT CURRENT Cortex-M3 Peripherals Nested Vectored Interrupt Controller (NVIC) Registers Base 0xE000.E000 EN0, type R/W, offset 0x100, reset 0x0000.0000 INT INT EN1, type R/W, offset 0x104, reset 0x0000.0000 INT DIS0, type R/W, offset 0x180, reset 0x0000.0000 INT INT DIS1, type R/W, offset 0x184, reset 0x0000.0000 INT PEND0, type R/W, offset 0x200, reset 0x0000.0000 INT INT PEND1, type R/W, offset 0x204, reset 0x0000.0000 INT UNPEND0, type R/W, offset 0x280, reset 0x0000.0000 INT INT June 18, 2012 683 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNPEND1, type R/W, offset 0x284, reset 0x0000.0000 INT ACTIVE0, type RO, offset 0x300, reset 0x0000.0000 INT INT ACTIVE1, type RO, offset 0x304, reset 0x0000.0000 INT PRI0, type R/W, offset 0x400, reset 0x0000.0000 INTD INTC INTB INTA PRI1, type R/W, offset 0x404, reset 0x0000.0000 INTD INTC INTB INTA PRI2, type R/W, offset 0x408, reset 0x0000.0000 INTD INTC INTB INTA PRI3, type R/W, offset 0x40C, reset 0x0000.0000 INTD INTC INTB INTA PRI4, type R/W, offset 0x410, reset 0x0000.0000 INTD INTC INTB INTA PRI5, type R/W, offset 0x414, reset 0x0000.0000 INTD INTC INTB INTA PRI6, type R/W, offset 0x418, reset 0x0000.0000 INTD INTC INTB INTA PRI7, type R/W, offset 0x41C, reset 0x0000.0000 INTD INTC INTB INTA PRI8, type R/W, offset 0x420, reset 0x0000.0000 INTD INTC INTB INTA PRI9, type R/W, offset 0x424, reset 0x0000.0000 INTD INTC INTB INTA PRI10, type R/W, offset 0x428, reset 0x0000.0000 INTD INTC INTB INTA SWTRIG, type WO, offset 0xF00, reset 0x0000.0000 INTID Cortex-M3 Peripherals System Control Block (SCB) Registers Base 0xE000.E000 CPUID, type RO, offset 0xD00, reset 0x411F.C231 IMP VAR PARTNO 684 CON REV June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISRPRE ISRPEND INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000 NMISET PENDSV UNPENDSV PENDSTSET PENDSTCLR VECPEND VECPEND RETBASE VECACT VTABLE, type R/W, offset 0xD08, reset 0x0000.0000 BASE OFFSET OFFSET APINT, type R/W, offset 0xD0C, reset 0xFA05.0000 VECTKEY PRIGROUP ENDIANESS SYSRESREQ VECTCLRACT VECTRESET SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000 SEVONPEND SLEEPDEEP SLEEPEXIT CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000 DIV0 STKALIGN BFHFNMIGN UNALIGNED MAINPEND BASETHR SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000 USAGE BUS MEM SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000 SVC SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000 TICK PENDSV DEBUG SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000 USAGE SVC BUSP MEMP USAGEP TICK PNDSV MON SVCA USGA BUS MEM BUSA MEMA INVSTAT UNDEF DERR IERR FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000 BFARV BSTKE BUSTKE IMPRE DIV0 UNALIGN PRECISE IBUS NOCP MMARV MSTKE MUSTKE INVPC HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000 DBG FORCED VECT MMADDR, type R/W, offset 0xD34, reset ADDR ADDR FAULTADDR, type R/W, offset 0xD38, reset ADDR ADDR Cortex-M3 Peripherals Memory Protection Unit (MPU) Registers Base 0xE000.E000 MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800 IREGION DREGION SEPARATE MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000 PRIVDEFEN HFNMIENA ENABLE MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000 NUMBER June 18, 2012 685 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000 ADDR ADDR VALID REGION VALID REGION VALID REGION VALID REGION MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000 ADDR ADDR MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000 ADDR ADDR MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000 ADDR ADDR MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset - (see page 185) VER CLASS MAJOR MINOR PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 187) BORIOR LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 (see page 188) VADJ RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 189) PLLLRIS BORRIS PLLLIM BORIM PLLLMIS BORMIS IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 190) MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 191) RESC, type R/W, offset 0x05C, reset - (see page 192) SW WDT BOR POR EXT RCC, type R/W, offset 0x060, reset 0x078E.3AD1 (see page 193) ACG PWRDN SYSDIV BYPASS USESYSDIV XTAL USEPWMDIV PWMDIV OSCSRC IOSCDIS MOSCDIS PLLCFG, type RO, offset 0x064, reset - (see page 197) F 686 R June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC2, type R/W, offset 0x070, reset 0x0780.2810 (see page 198) USERCC2 SYSDIV2 PWRDN2 BYPASS2 OSCSRC2 DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 200) DSDIVORIDE DSOSCSRC DID1, type RO, offset 0x004, reset - (see page 201) VER FAM PARTNO PINCOUNT TEMP PKG ROHS QUAL DC0, type RO, offset 0x008, reset 0x00FF.007F (see page 203) SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset 0x0010.30DF (see page 204) PWM MINSYSDIV MPU HIB PLL WDT SWO SWD JTAG TIMER3 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 DC2, type RO, offset 0x014, reset 0x070F.1137 (see page 206) COMP2 COMP1 I2C0 COMP0 QEI0 SSI1 SSI0 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 DC3, type RO, offset 0x018, reset 0xBF00.FFFF (see page 208) 32KHZ PWMFAULT CCP5 C2O CCP4 C2PLUS C2MINUS CCP3 C1O CCP2 CCP1 C1PLUS C1MINUS CCP0 C0O C0PLUS C0MINUS DC4, type RO, offset 0x01C, reset 0x5100.007F (see page 210) EPHY0 EMAC0 E1588 GPIOG RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 212) PWM HIB WDT SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 214) PWM HIB WDT DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 216) PWM HIB WDT RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 218) COMP2 COMP1 I2C0 COMP0 TIMER3 QEI0 SSI1 SSI0 SSI1 SSI0 SSI1 SSI0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 221) COMP2 COMP1 I2C0 COMP0 TIMER3 QEI0 DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 224) COMP2 I2C0 COMP1 COMP0 TIMER3 QEI0 RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 227) EPHY0 EMAC0 SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 229) EPHY0 EMAC0 DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 231) EPHY0 EMAC0 June 18, 2012 687 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 GPIOC GPIOB GPIOA HIBREQ RTCEN SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 233) PWM HIB WDT SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 234) COMP2 COMP1 I2C0 COMP0 TIMER3 QEI0 SSI1 SSI0 GPIOF GPIOE SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 236) EPHY0 EMAC0 GPIOG GPIOD Hibernation Module Base 0x400F.C000 HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 (see page 246) RTCC RTCC HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF (see page 247) RTCM0 RTCM0 HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF (see page 248) RTCM1 RTCM1 HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF (see page 249) RTCLD RTCLD HIBCTL, type R/W, offset 0x010, reset 0x8000.0000 (see page 250) VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 252) EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 HIBRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 253) HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 254) HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 (see page 255) HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF (see page 256) TRIM HIBDATA, type R/W, offset 0x030-0x12C, reset - (see page 257) RTD RTD Internal Memory Flash Memory Control Registers (Flash Control Offset) Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET OFFSET 688 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMT MERASE ERASE WRITE PRIS ARIS PMASK AMASK PMISC AMISC DBG1 DBG0 FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY FCRIS, type RO, offset 0x00C, reset 0x0000.0000 FCIM, type R/W, offset 0x010, reset 0x0000.0000 FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 Internal Memory Flash Memory Protection Registers (System Control Offset) Base 0x400F.E000 USECRL, type R/W, offset 0x140, reset 0x31 USEC FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW DATA DATA USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA DATA USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA DATA FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE June 18, 2012 689 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE General-Purpose Input/Outputs (GPIOs) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 297) DATA GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 298) DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 299) IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 300) IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 301) IEV GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 302) IME GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 303) RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 304) MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 305) IC GPIOAFSEL, type R/W, offset 0x420, reset - (see page 306) AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 308) DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 309) DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 310) DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 311) ODE 690 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPUR, type R/W, offset 0x510, reset - (see page 312) PUE GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 313) PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 314) SRL GPIODEN, type R/W, offset 0x51C, reset - (see page 315) DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 316) LOCK LOCK GPIOCR, type -, offset 0x524, reset - (see page 317) CR GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 319) PID4 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 320) PID5 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 321) PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 322) PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 323) PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 324) PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 325) PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 326) PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 327) CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 328) CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 329) CID2 June 18, 2012 691 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 330) CID3 General-Purpose Timers Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 344) GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 345) TAAMS TACMR TAMR TBAMS TBCMR TBMR GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 347) GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 349) TBPWML TBEVENT TBSTALL TBEN TAPWML RTCEN TAEVENT TASTALL TAEN GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 352) CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS RTCMIS CAEMIS CAMMIS TATOMIS GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 354) CBERIS GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 355) CBEMIS CBMMIS TBTOMIS GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 356) CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 358) TAILRH TAILRL GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 359) TBILRL GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 360) TAMRH TAMRL GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 361) TBMRL GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 362) TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 363) TBPSR GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 364) TAPSMR 692 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEN INTEN GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 365) TBPSMR GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 366) TARH TARL GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 367) TBRL Watchdog Timer Base 0x4000.0000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 372) WDTLoad WDTLoad WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 373) WDTValue WDTValue WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (see page 374) WDTICR, type WO, offset 0x00C, reset - (see page 375) WDTIntClr WDTIntClr WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 376) WDTRIS WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 377) WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 378) STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 379) WDTLock WDTLock WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 380) PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 381) PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 382) PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 383) PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 384) PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 385) PID1 June 18, 2012 693 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE EPS PEN BRK SIRLP SIREN UARTEN WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 386) PID2 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 387) PID3 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 388) CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 389) CID1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 390) CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 391) CID3 Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 402) OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) (see page 404) UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) (see page 404) DATA UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 406) TXFE RXFF TXFF RXFE BUSY UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 408) ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 409) DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 410) DIVFRAC UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 411) SPS WLEN FEN STP2 UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 413) RXE TXE LBE UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 415) RXIFLSEL 694 TXIFLSEL June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BEIM PEIM FEIM RTIM TXIM RXIM PERIS FERIS RTRIS TXRIS RXRIS PEMIS FEMIS RTMIS TXMIS RXMIS PEIC FEIC RTIC TXIC RXIC UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 417) OEIM UARTRIS, type RO, offset 0x03C, reset 0x0000.000F (see page 419) OERIS BERIS UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 420) OEMIS BEMIS UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 421) OEIC BEIC UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 423) PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 424) PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 425) PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 426) PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 427) PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 428) PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 429) PID2 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 430) PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 431) CID0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 432) CID1 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 433) CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 434) CID3 June 18, 2012 695 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPH SPO Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 448) SCR FRF DSS SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 450) SOD MS SSE LBM RFF RNE TNF TFE TXIM RXIM RTIM RORIM TXRIS RXRIS RTRIS RORRIS TXMIS RXMIS RTMIS RORMIS RTIC RORIC SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 452) DATA SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 453) BSY SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 455) CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 456) SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 458) SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 459) SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 460) SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 461) PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 462) PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 463) PID6 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 464) PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 465) PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 466) PID1 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 467) PID2 696 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 468) PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 469) CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 470) CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 471) CID2 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 472) CID3 Inter-Integrated Circuit (I2C) Interface I2C Master I2C 0 base: 0x4002.0000 I2CMSA, type R/W, offset 0x000, reset 0x0000.0000 SA R/S I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads) BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY ACK STOP START RUN I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes) I2CMDR, type R/W, offset 0x008, reset 0x0000.0000 DATA I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001 TPR I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000 IM I2CMRIS, type RO, offset 0x014, reset 0x0000.0000 RIS I2CMMIS, type RO, offset 0x018, reset 0x0000.0000 MIS I2CMICR, type WO, offset 0x01C, reset 0x0000.0000 IC I2CMCR, type R/W, offset 0x020, reset 0x0000.0000 SFE June 18, 2012 MFE LPBK 697 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FBR TREQ RREQ Inter-Integrated Circuit (I2C) Interface I2C Slave I2C 0 base: 0x4002.0000 I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000 OAR I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Reads) I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Writes) DA I2CSDR, type R/W, offset 0x808, reset 0x0000.0000 DATA I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000 DATAIM I2CSRIS, type RO, offset 0x810, reset 0x0000.0000 DATARIS I2CSMIS, type RO, offset 0x814, reset 0x0000.0000 DATAMIS I2CSICR, type WO, offset 0x818, reset 0x0000.0000 DATAIC Ethernet Controller Ethernet MAC Base 0x4004.8000 MACRIS/MACIACK, type RO, offset 0x000, reset 0x0000.0000 (Reads) PHYINT MDINT RXER FOV TXEMP TXER RXINT PHYINT MDINT RXER FOV TXEMP TXER RXINT RXERM FOVM TXEMPM TXERM RXINTM PRMS AMUL RXEN CRC PADEN TXEN MACRIS/MACIACK, type WO, offset 0x000, reset 0x0000.0000 (Writes) MACIM, type R/W, offset 0x004, reset 0x0000.007F PHYINTM MDINTM MACRCTL, type R/W, offset 0x008, reset 0x0000.0008 RSTFIFO BADCRC MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000 DUPLEX MACDATA, type RO, offset 0x010, reset 0x0000.0000 (Reads) RXDATA RXDATA MACDATA, type WO, offset 0x010, reset 0x0000.0000 (Writes) TXDATA TXDATA 698 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRITE START MACIA0, type R/W, offset 0x014, reset 0x0000.0000 MACOCT4 MACOCT3 MACOCT2 MACOCT1 MACIA1, type R/W, offset 0x018, reset 0x0000.0000 MACOCT6 MACOCT5 MACTHR, type R/W, offset 0x01C, reset 0x0000.003F THRESH MACMCTL, type R/W, offset 0x020, reset 0x0000.0000 REGADR MACMDV, type R/W, offset 0x024, reset 0x0000.0080 DIV MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000 MDTX MACMRXD, type R/W, offset 0x030, reset 0x0000.0000 MDRX MACNP, type RO, offset 0x034, reset 0x0000.0000 NPR MACTR, type R/W, offset 0x038, reset 0x0000.0000 NEWTX MACTS, type R/W, offset 0x03C, reset 0x0000.0000 TSEN Ethernet Controller MII Management MR0, type R/W, address 0x00, reset 0x3100 RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT MR1, type RO, address 0x01, reset 0x7849 100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD PRX LPANEGA PCSBP RXCC MR2, type RO, address 0x02, reset 0x000E OUI[21:6] MR3, type RO, address 0x03, reset 0x7237 OUI[5:0] MN RN MR4, type R/W, address 0x04, reset 0x01E1 NP RF A3 A2 A1 A0 S MR5, type RO, address 0x05, reset 0x0000 NP ACK RF A[7:0] S MR6, type RO, address 0x06, reset 0x0000 PDF LPNPA MR16, type R/W, address 0x10, reset 0x0140 RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL MR17, type R/W, address 0x11, reset 0x0000 JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT MR18, type RO, address 0x12, reset 0x0000 ANEGF DPLX RATE RXSD RX_LOCK June 18, 2012 699 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IN2 IN1 IN0 IN2 IN1 IN0 IN2 IN1 IN0 MR19, type R/W, address 0x13, reset 0x4000 TXO MR23, type R/W, address 0x17, reset 0x0010 LED1[3:0] LED0[3:0] MR24, type R/W, address 0x18, reset 0x00C0 PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD Analog Comparators Base 0x4003.C000 ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 565) ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 566) ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 567) ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 568) EN RNG VREF ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 569) OVAL ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 (see page 569) OVAL ACSTAT2, type RO, offset 0x060, reset 0x0000.0000 (see page 569) OVAL ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 570) ASRCP ISLVAL ISEN CINV ISLVAL ISEN CINV ISLVAL ISEN CINV ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 570) ASRCP ACCTL2, type R/W, offset 0x064, reset 0x0000.0000 (see page 570) ASRCP Pulse Width Modulator (PWM) Base 0x4002.8000 PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 582) GlobalSync2 GlobalSync1 GlobalSync0 Sync2 Sync1 Sync0 PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 (see page 583) PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 (see page 584) PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 585) PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv 700 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fault5 Fault4 Fault3 Fault2 Fault1 Fault0 PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 (see page 586) PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 (see page 587) IntFault IntPWM2 IntPWM1 IntPWM0 PWMRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 588) IntFault IntPWM2 IntPWM1 IntPWM0 PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 589) IntFault IntPWM2 IntPWM1 IntPWM0 PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 590) Fault PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 591) CmpBUpd CmpAUpd LoadUpd Debug Mode Enable CmpBUpd CmpAUpd LoadUpd Debug Mode Enable CmpBUpd CmpAUpd LoadUpd Debug Mode Enable PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 591) PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 591) PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 (see page 593) IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 (see page 593) PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 (see page 593) PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 (see page 595) PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 (see page 595) PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 (see page 595) PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 (see page 596) PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000 (see page 596) PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000 (see page 596) June 18, 2012 701 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 (see page 597) Load PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000 (see page 597) Load PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000 (see page 597) Load PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 (see page 598) Count PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000 (see page 598) Count PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000 (see page 598) Count PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 (see page 599) CompA PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000 (see page 599) CompA PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000 (see page 599) CompA PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 (see page 600) CompB PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 (see page 600) CompB PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 (see page 600) CompB PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 (see page 601) ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero ActCmpAD ActCmpAU ActLoad ActZero ActCmpAD ActCmpAU ActLoad ActZero ActCmpAD ActCmpAU ActLoad ActZero ActCmpAD ActCmpAU ActLoad ActZero PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 601) ActCmpBD ActCmpBU PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000 (see page 601) ActCmpBD ActCmpBU PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 (see page 604) ActCmpBD ActCmpBU PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 604) ActCmpBD ActCmpBU 702 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000 (see page 604) ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 (see page 607) Enable PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 607) Enable PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000 (see page 607) Enable PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 (see page 608) RiseDelay PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000 (see page 608) RiseDelay PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000 (see page 608) RiseDelay PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 (see page 609) FallDelay PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 609) FallDelay PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 (see page 609) FallDelay Quadrature Encoder Interface (QEI) QEI0 base: 0x4002.C000 QEICTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 616) STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable Direction Error QEISTAT, type RO, offset 0x004, reset 0x0000.0000 (see page 618) QEIPOS, type R/W, offset 0x008, reset 0x0000.0000 (see page 619) Position Position QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000 (see page 620) MaxPos MaxPos QEILOAD, type R/W, offset 0x010, reset 0x0000.0000 (see page 621) Load Load QEITIME, type RO, offset 0x014, reset 0x0000.0000 (see page 622) Time Time QEICOUNT, type RO, offset 0x018, reset 0x0000.0000 (see page 623) Count Count June 18, 2012 703 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IntError IntDir IntTimer IntIndex IntError IntDir IntTimer IntIndex IntError IntDir IntTimer IntIndex QEISPEED, type RO, offset 0x01C, reset 0x0000.0000 (see page 624) Speed Speed QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000 (see page 625) QEIRIS, type RO, offset 0x024, reset 0x0000.0000 (see page 626) QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000 (see page 627) 704 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller C Ordering and Contact Information C.1 Ordering Information LM3Snnnn-gppss-rrm Part Number nnn = Sandstorm-class parts nnnn = All other Stellaris(R) parts Shipping Medium T = Tape-and-reel Omitted = Default shipping (tray or tube) Temperature E = -40C to +105C I = -40C to +85C Revision Speed 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz 80 = 80 MHz Package BZ = 108-ball BGA QC = 100-pin LQFP QN = 48-pin LQFP QR = 64-pin LQFP Table C-1. Part Ordering Information C.2 Orderable Part Number Description LM3S6950-IBZ50-A2 Stellaris LM3S6950 Microcontroller Industrial Temperature 108-ball BGA LM3S6950-IBZ50-A2T Stellaris LM3S6950 Microcontroller Industrial Temperature 108-ball BGA Tape-and-reel LM3S6950-IQC50-A2 Stellaris LM3S6950 Microcontroller Industrial Temperature 100-pin LQFP LM3S6950-IQC50-A2T Stellaris LM3S6950 Microcontroller Industrial Temperature 100-pin LQFP Tape-and-reel (R) Part Markings The Stellaris microcontrollers are marked with an identifying number. This code contains the following information: The first line indicates the part number, for example, LM3S9B90. In the second line, the first eight characters indicate the temperature, package, speed, revision, and product status. For example in the figure below, IQC80C0X indicates an Industrial temperature (I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. The letter immediately following the revision indicates product status. An X indicates experimental and requires a waiver; an S indicates the part is fully qualified and released to production. The remaining characters contain internal tracking numbers. June 18, 2012 705 Texas Instruments-Production Data Ordering and Contact Information C.3 Kits The Stellaris Family provides the hardware and software tools that engineers need to begin development quickly. Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers before purchase Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. C.4 Support Information For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm. 706 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller D Package Information D.1 100-Pin LQFP Package D.1.1 Package Dimensions Figure D-1. Stellaris LM3S6950 100-Pin LQFP Package Dimensions Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. June 18, 2012 707 Texas Instruments-Production Data Package Information Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 100L A Max. 1.60 A1 - 0.05 Min./0.15 Max. A2 0.05 1.40 D 0.20 16.00 D1 0.05 14.00 E 0.20 16.00 E1 0.05 14.00 L +0.15/-0.10 0.60 e Basic 0.50 b +0.05 0.22 - 0-7 ddd Max. 0.08 ccc Max. 0.08 JEDEC Reference Drawing MS-026 Variation Designator BED 708 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller D.1.2 Tray Dimensions Figure D-2. 100-Pin LQFP Tray Dimensions D.1.3 Tape and Reel Dimensions Note: In the figure that follows, pin 1 is located in the top right corner of the device. June 18, 2012 709 Texas Instruments-Production Data Package Information Figure D-3. 100-Pin LQFP Tape and Reel Dimensions THIS IS A COMPUTER GENERATED UNCONTROLLED DOCUMENT PRINTED ON 06.01.2003 06.01.2003 06.01.2003 MUST NOT BE REPRODUCED WITHOUT WRITTEN PERMISSION FROM SUMICARRIER (S) PTE LTD 06.01.2003 06.01.2003 710 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller D.2 108-Ball BGA Package D.2.1 Package Dimensions Figure D-4. Stellaris LM3S6950 108-Ball BGA Package Dimensions June 18, 2012 711 Texas Instruments-Production Data Package Information Note: The following notes apply to the package drawing. Symbols MIN NOM MAX A 1.22 1.36 1.50 A1 0.29 0.34 0.39 A3 0.65 0.70 0.75 c 0.28 0.32 0.36 D 9.85 10.00 10.15 D1 E 8.80 BSC 9.85 E1 b 10.00 8.80 BSC 0.43 0.48 bbb 0.53 .20 ddd .12 e 0.80 BSC f 10.15 - 0.60 M 12 n 108 - REF: JEDEC MO-219F 712 June 18, 2012 Texas Instruments-Production Data (R) Stellaris LM3S6950 Microcontroller D.2.2 Tray Dimensions Figure D-5. 108-Ball BGA Tray Dimensions June 18, 2012 713 Texas Instruments-Production Data Package Information D.2.3 Tape and Reel Dimensions Figure D-6. 108-Ball BGA Tape and Reel Dimensions C-PAK PTE LTD 714 June 18, 2012 Texas Instruments-Production Data IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated