RF
TRIP
MODE
VDD
VREG
VIN
VIN
VIN
VIN
VIN
VIN
TPS53318
TPS53319
VFB
EN
PGOOD
VBST
ROVP
LL
LL
LL
1234567891011
22 21 20 19 18 17 16 15 14 13 12
VOUT
VREG
GND
LL
LL
LL
VVDD
VIN
EN
PGOOD
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Design
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53318
,
TPS53319
SLUSAY8E –JUNE 2012–REVISED NOVEMBER 2016
TPS5331x High-Efficiency, 8-A or 14-A, Synchronous Buck Converter
with Eco-mode Control
1
1 Features
1• Conversion Input Voltage Range: 1.5 V to 22 V
• VDD Input Voltage Range: 4.5 V to 25 V
• 91% Efficiency from 12 V to 1.5 V at 14 A
• Output Voltage Range: 0.6 V to 5.5 V
• 5-V LDO Output
• Supports Single-Rail Input
• Integrated Power MOSFETs with 8 A (TPS53318)
or 14 A (TPS53319) of Continuous Output Current
• Auto-Skip Eco-mode™ for Light-Load Efficiency
• < 110 μA Shut Down Current
• D-CAP™ Mode with Fast Transient Response
• Selectable Switching Frequency from 250 kHz to
1 MHz with External Resistor
• Selectable Auto-Skip or PWM-Only Operation
• Built-in 1% 0.6-V Reference.
• 0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable
Internal Voltage Servo Soft-Start
• Integrated Boost Switch
• Pre-Charged Start-Up Capability
• Adjustable Overcurrent Limit with Thermal
Compensation
• Overvoltage, Undervoltage, UVLO and Over-
Temperature Protection
• Supports All Ceramic Output Capacitors
• Open-Drain Power Good Indication
• Incorporates NexFET™ Power Block Technology
• 22-Pin QFN (DQP) Package with PowerPAD™
2 Applications
• Server/Storage
• Workstations and Desktops
• Telecommunications Infrastructure
3 Description
The TPS53318 and TPS53319 devices are D-CAP
mode, 8-A or 14-A synchronous switchers with
integrated MOSFETs. They are designed for ease of
use, low external component count, and space-
conscious power systems.
These devices feature accurate 1%, 0.6-V reference,
and integrated boost switch. A sample of competitive
features include: 1.5-V to 22-V wide conversion input
voltage range, very low external component count, D-
CAP™ mode control for super fast transient, auto-
skip mode operation, internal soft-start control,
selectable frequency, and no need for compensation.
The conversion input voltage ranges from 1.5 V to 22
V, the supply voltage range is from 4.5 V to 25 V, and
the output voltage range is from 0.6 V to 5.5 V.
These devices are available in 5 mm x 6 mm, 22-pin
QFN package and is specified from –40°C to 85°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS53318 LSON-CLIP (22) 6.00 mm x 5.00 mm
TPS53319
(1) For all available packages, see the Package Option
Addendum section at the end of the datasheet.
Simplified Application
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 8
7.7 TPS53319 Typical Characteristics.......................... 11
7.8 TPS53318 Typical Characteristics.......................... 12
8 Detailed Description............................................ 13
8.1 Overview................................................................. 13
8.2 Functional Block Diagram....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 19
9 Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Applications ............................................... 21
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 Device and Documentation Support................. 29
12.1 Device Support...................................................... 29
12.2 Related Links ........................................................ 29
12.3 Receiving Notification of Documentation Updates 29
12.4 Community Resources.......................................... 29
12.5 Trademarks........................................................... 29
12.6 Electrostatic Discharge Caution............................ 29
12.7 Glossary................................................................ 29
13 Mechanical, Packaging, and Orderable
Information........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2015) to Revision E Page
• Changed Pin 19 From: ground To: VIN 12 V in Figure 34.................................................................................................... 21
Changes from Revision C (December 2014) to Revision D Page
• Added recommendation for ROVP connection when ROVP function is not needed in Pin Functions table ......................... 3
• Corrected typographical error. Changed "when the VDD voltage rises above 1 V" to "when the VDD voltage rises
above 2 V" in the 5-V LDO and VREG Start-Up section. .................................................................................................... 14
• Added ROVP Pin Design Note in Redundant Overvoltage Protection (OVP) section......................................................... 17
Changes from Revision B (May 2013) to Revision C Page
• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................. 1
• Added clarity to Current Sense, Overcurrent and Short Circuit Protection section.............................................................. 16
• Added Table 2 ..................................................................................................................................................................... 17
Changes from Revision A (JUNE 2012) to Revision B Page
• Added clarity to Overvoltage and Undervoltage Protection section..................................................................................... 17
• Updated Figure 50................................................................................................................................................................ 28
Changes from Original (JUNE 2012) to Revision A Page
• Changed "< 100 μA Shut Down Current" to "< 110 μA Shut Down Current" in Features...................................................... 1
VFB
EN
PGOOD
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
GND
PowerPadTM
18
19
20
21
22
VBST
TRIP
MODE
ROVP
LL
LL
LL
LL
LL
LL
RF
VDD
VREG
VIN
VIN
VIN
VIN
VIN
VIN
3
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5 Device Comparison Table
(1) For detailed ordering information see the Package Option Addendum
section at the end of this data sheet.
ORDER NUMBER(1) OUTPUT CURRENT (A)
TPS53318DQP 8
TPS53319DQP 14
(1) I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground
6 Pin Configuration and Functions
DQP (LSON-CLIP) PACKAGE
22 PINS
(TOP VIEW)
Pin Functions
PIN I/O/P(1) DESCRIPTION
NAME NO.
EN 2 I Enable pin. Typical turn-on threshold voltage is 1.3 V. Typical turn-off threshold voltage is 1.0 V.
GND G Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
LL
6
B Output of converted power. Connect this pin to the output inductor.
7
8
9
10
11
MODE 20 I Soft-start and mode selection. Connect a resistor to select soft-start time using Table 3. The soft-start time
is detected and stored into internal register during start-up.
PGOOD 3 O Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB
goes out of the specified limits PGOOD goes low after a 2-µs delay
ROVP 5 I Redundant overvoltage protection (OVP) input. Use a resistor divider to connect this pin to VOUT.
Internally pulled down to GND with 1.5-MΩresistor. If redundant OVP is not needed, connect this pin to
GND or make it float. (See Redundant Overvoltage Protection (OVP) section)
RF 22 I Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using
Table 1. The switching frequency is detected and stored during the startup.
TRIP 21 I OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 3000 ppm/°C current is sourced
and set the OCL trip voltage as follows.
space VOCL = VTRIP/32 (VTRIP ≤2.4 V, VOCL ≤75 mV)
4
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Pin Functions (continued)
PIN I/O/P(1) DESCRIPTION
NAME NO.
VBST 4 P Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node.
Internally connected to VREG via bootstrap MOSFET switch.
VDD 19 P Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.
VFB 1 I Output feedback input. Connect this pin to VOUT through a resistor divider.
VIN
12
P Conversion power input. The conversion input voltage range is from 1.5 V to 22 V.
13
14
15
16
17
VREG 18 P 5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry.
Thermal Pad G Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings(1)
VALUE UNIT
MIN MAX
Input voltage range
VIN (main supply) –0.3 30
V
VDD –0.3 28
VBST –0.3 32
VBST (with respect to LL) –0.3 7
EN, MODE, TRIP, RF, ROVP, VFB –0.3 7
Output voltage range LL DC –2 30
V
Pulse < 20ns, E = 5 μJ –7 32
PGOOD, VREG –0.3 7
GND –0.3 0.3
Source/Sink current VBST 50 mA
Operating free-air temperature, TA–40 85
˚C
Junction temperature range, TJ–40 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
Storage temperature, Tstg –55 150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
5
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Input voltage range
VIN (main supply) 1.5 22
V
VDD 4.5 25
VBST 4.5 28
VBST (with respect to LL) 4.5 6.5
EN, MODE, TRIP, RF, ROVP, VFB –0.1 6.5
Output voltage range LL –1 27 V
PGOOD, VREG –0.1 6.5
Junction temperature range, TJ–40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC(1)
TPS53318
TPS53319 UNIT
DQP
22 PINS
RθJA Junction-to-ambient thermal resistance 27.2
°C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.1
RθJB Junction-to-board thermal resistance 5.9
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 5.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2
(1) Ensured by design. Not production tested.
7.5 Electrical Characteristics
Over recommended free-air temperature range, VVDD = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VVIN VIN pin power conversion input voltage 1.5 22 V
VVDD Supply input voltage 4.5 25.0 V
IVIN(leak) VIN pin leakage current VEN = 0 V 1 µA
IVDD VDD supply current TA= 25°C, No load, VEN = 5 V, VVFB
= 0.630 V 420 590 µA
IVDDSDN VDD shutdown current TA= 25°C, No load, VEN = 0 V 110 µA
INTERNAL REFERENCE VOLTAGE
VVFB VFB regulation voltage CCM condition(1) 0.600 V
VVFB VFB regulation voltage TA= 25°C 0.597 0.600 0.603 V0°C ≤TA≤85°C 0.5952 0.600 0.6048
–40°C ≤TA≤85°C 0.594 0.600 0.606
IVFB VFB input current VVFB = 0.630 V, TA= 25°C 0.01 0.20 µA
LDO OUTPUT
VVREG LDO output voltage 0 mA ≤IVREG ≤30 mA 4.77 5.00 5.36 V
IVREG LDO output current(1) Maximum current allowed from LDO 30 mA
VDO Low drop out voltage VVDD = 4.5 V, IVREG = 30 mA 250 mV
BOOT STRAP SWITCH
VFBST Forward voltage VVREG-VBST, IF= 10 mA, TA= 25°C 0.1 0.2 V
IVBSTLK VBST leakage current VVBST = 23 V, VSW = 17 V, TA= 25°C 0.01 1.50 µA
6
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Electrical Characteristics (continued)
Over recommended free-air temperature range, VVDD = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
(2) Not production tested. Test condition is VIN = 12 V, VOUT = 1.2 V, IOUT = 5 A using application circuit shown in Figure 45.
DUTY AND FREQUENCY CONTROL
tOFF(min) Minimum off-time TA= 25°C 150 260 400 ns
tON(min) Minimum on-time VIN = 17 V, VOUT = 0.6 V, fSW = 1
MHz,
TA= 25 °C(1) 35 ns
SOFT-START TIMING
tSS Internal soft-start time from
VOUT = 0 V to 95% of VOUT
RMODE = 39 kΩ0.7
ms
RMODE = 100 kΩ1.4
RMODE = 200 kΩ2.8
RMODE = 470 kΩ5.6
OUTPUT VOLTAGE DISCHARGE
IDSCHG Output voltage discharge current VEN = 0 V, VSW = 0.5 V 5.0 6.6 9.0 mA
POWERGOOD
VTHPG PG threshold PG in from lower 92.5% 95.0% 98.5%
PG in from higher 107.5% 110.0% 112.5%
PG hysteresis 2.5% 5.0% 7.5%
RPG PG transistor on-resistance 15 30 60 Ω
tPGDEL PG delay Delay for PG in 0.8 1 1.2 ms
LOGIC THRESHOLD AND SETTING CONDITIONS
VEN EN Voltage Enable 1.0 1.3 1.6 V
Disable 0.8 1.0 1.2
IEN EN Input current VEN = 5 V 1.0 µA
fSW Switching frequency
RRF = 0 Ωto GND, TA= 25°C(2) 200 250 300
kHz
RRF = 187 kΩto GND, TA= 25°C(2) 250 300 350
RRF = 619 kΩ, to GND, TA= 25°C(2) 350 400 450
RRF = Open, TA= 25°C(2) 450 500 550
RRF = 866 kΩto VREG, TA= 25°C(2) 540 600 660
RRF = 309 kΩto VREG, TA= 25°C(2) 670 750 820
RRF = 124 kΩto VREG, TA= 25°C(2) 770 850 930
RRF = 0 Ωto VREG, TA= 25°C(2) 880 970 1070
PROTECTION: CURRENT SENSE
ITRIP TRIP source current VTRIP = 1 V, TA= 25°C 10 µA
TCITRIP TRIP current temperature coefficient On the basis of 25°C(2) 3000 ppm/°C
VTRIP Current limit threshold
setting range TPS53318 VTRIP-GND 0.4 1.5 V
TPS53319 2.4
VOCL Current limit threshold VTRIP = 1.2 V 37.5 mV
VTRIP = 0.4 12.5
VOCLN Negative current limit threshold VTRIP = 1.2 V –37.5 mV
VTRIP = 0.4 V –12.5
IOCP Valley current limit threshold RTRIP = 66.5 kΩ, 0°C ≤TA≤125°C 4.6 5.4 6.3 A
RTRIP = 66.5 kΩ, –40°C ≤TA≤125°C 4.4 5.4 6.3
VAZCADJ Auto zero cross adjustable range Positive 3 15 mV
Negative –15 –3
7
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Electrical Characteristics (continued)
Over recommended free-air temperature range, VVDD = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PROTECTION: UVP and OVP
VOVP OVP trip threshold OVP detect 115% 120% 125%
tOVPDEL OVP propagation delay VFB delay with 50-mV overdrive 1 µs
VUVP Output UVP trip threshold UVP detect 65% 70% 75%
tUVPDEL Output UVP propagation delay 0.8 1.0 1.2 ms
tUVPEN Output UVP enable delay From enable to UVP workable 1.5 2.3 3.0 ms
UVLO
VUVVREG VREG UVLO threshold Wake up 4.00 4.20 4.33 V
Hysteresis 0.25
PROTECTION: UVP and OVP
VOVP OVP trip threshold OVP detect 115% 120% 125%
tOVPDEL OVP propagation delay VFB delay with 50-mV overdrive 1 µs
VUVP Output UVP trip threshold UVP detect 65% 70% 75%
tUVPDEL Output UVP proprogation delay 0.8 1.0 1.2 ms
tUVPEN Output UVP enable delay From enable to UVP workable 1.5 2.3 3.0 ms
UVLO
VUVVREG VREG UVLO threshold Wake up 4.00 4.20 4.33 V
Hysteresis 0.25
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature(2) 145 °C
Hysteresis(2) 10
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 300 kHz
G001
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 500 kHz
G001
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Valley OCP Threshold (A)
RTRIP = 66.5 kΩ
G001
0
20
40
60
80
100
120
140
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
OVP/UVP Trip Threshold (%)
OVP
UVP
G001
0
100
200
300
400
500
600
700
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
VDD Supply Current (µA)
VEN = 5V
VVDD = 12 V
VVFB = 0.63 V
No Load
G001
0
20
40
60
80
100
120
140
160
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
VDD Shutdown Current (µA)
VEN = 0 V
VVDD = 12 V
No Load
G001
8
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7.6 Typical Characteristics
.
.Figure 1. VDD Supply Current vs. Junction Temperature
.
.Figure 2. VDD Shutdown Current vs. Junction Temperature
.
.Figure 3. Valley OCP Threshold vs Temperature
.
.Figure 4. OVP/UVP Trip Threshold vs. Junction Temperature
.
.Figure 5. Switching Frequency vs. Output Current
.
.Figure 6. Switching Frequency vs. Output Current
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
4 8 12 16 20 24
Input Voltage (V)
Output Voltage (V)
FCCM, IOUT = 0 A
Skip Mode, IOUT = 0 A
FCCM and Skip Mode, IOUT = 14 A
fSW = 500 kHz
VIN = 12 V
G000
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 15
Output Current (A)
Efficiency (%)
Skip Mode, fSW = 500 kHz
FCCM, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCCM, fSW = 300 kHz
TPS53319
VIN = 12 V
VOUT = 1.2 V
G001
0
200
400
600
800
1000
1200
0 1 2 3 4 5 6
Output Voltage (V)
Switching Frequency (kHz)
fSET = 300 kHz
fSET = 500 kHz fSET = 750 kHz
fSET = 1 MHz
VIN = 12 V
IOUT = 5 A
G000
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 3 6 9 12 15
Output Current (A)
Output Voltage (V)
Skip Mode
FCCM
TPS53319
fSW = 500 kHz
VIN = 12 V
VOUT = 1.2 V
G001
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 750 kHz
G001
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
G001
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Typical Characteristics (continued)
.
.Figure 7. Switching Frequency vs. Output Current
.
.Figure 8. Switching Frequency vs. Output Current
.
.Figure 9. Switching Frequency vs. Output Voltage
.
.Figure 10. Output Voltage vs. Output Current
.
.Figure 11. Output Voltage vs. Input Voltage
.
.Figure 12. Efficiency vs Output Current
10
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Typical Characteristics (continued)
Figure 13. 1.2-V Output FCCM Mode Steady-State Operation Figure 14. 1.2-V Output Skip Mode Steady-State Operation
Figure 15. CCM to DCM Transition Figure 16. DCM to CCM Transition
Figure 17. Short Circuit Protection
70
74
78
82
86
90
94
98
0 2 4 6 8 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G000
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
TPS53319
G001
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7.7 TPS53319 Typical Characteristics
.
.Figure 18. Efficiency vs Output Current
.
.Figure 19. Efficiency vs Output Current
.
.Figure 20. Efficiency vs Output Current
.
.Figure 21. Efficiency vs Output Current
.
.Figure 22. Efficiency vs Output Current
.
.Figure 23. Efficiency vs Output Current
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
FCCM
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
G001
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
Skip Mode
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
G001
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53318
G000
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53318
G000
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
G001
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
G001
12
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7.8 TPS53318 Typical Characteristics
.
.Figure 24. Efficiency vs Output Current
.
.Figure 25. Efficiency vs Output Current
.
.Figure 26. Efficiency vs Output Current
.
.Figure 27. Efficiency vs Output Current
.
.Figure 28. Efficiency vs Output Current
.
.Figure 29. Efficiency vs Output Current
Shutdown VREG
VDDOK
LL
TPS53318/TPS53319
tON
One-
Shot
Control
Logic
+
+OCP
ZC
GND
LL
XCON
GND
+
1.3 V/1.0 V
EN
UVP/OVP
Logic
+
THOK 145°C/
135°C
+
4.2 V/
3.95 V
VIN
VBST
Fault
LL
GND
RF
+
+
PWM
+
OV
+20%
UV
+0.6 V –30% Delay
SS
0.6 V
VFB
TRIP
Enable
+
+
Delay
0.6 V +10/15%
0.6 V –5/10%
PGOOD
Control Logic
·On/Off time
·Minimum On/Off
·Light load
·OVP/UVP
·FCCM/Skip
UDG-12041
10 ?A
VREG
+
SS
FCCM/
Skip
Decode
MODE
VDD
Ramp
Compensation
+
LDO
+ROVP
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8 Detailed Description
8.1 Overview
The TPS53318 and TPS53319 devices are high-efficiency, single channel, synchronous buck converters suitable
for low output voltage point-of-load applications in computing and similar digital consumer applications. The
device features proprietary D-CAP™ mode control combined with an adaptive on-time architecture. This
combination is ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The
output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 1.5 V to 22 V and the VDD
bias voltage is from 4.5 V to 25 V. The D-CAP™ mode uses the equivalent series resistance (ESR) of the output
capacitor(s) to sense the device current. One advantage of this control scheme is that it does not require an
external phase compensation network. This allows a simple design with a low external component count. Eight
preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG.
Adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while
allowing the switching frequency to increase at the step-up of the load.
These devices have a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms as shown in Table 3.
8.2 Functional Block Diagram
(1) The thresholds shown in the Functional Block Diagram are typical values. Refer to the Electrical Characteristics table
for threshold tolerance specifications.
µOUT
ON
IN
V
t
V
VREG
VDD
Above 2.0 V
EN 0.6 V
VREF
VOUT
250 µs Soft-Start .
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8.3 Feature Description
8.3.1 5-V LDO and VREG Start-Up
Both the TPS53318 and TPS53319 devices provide an internal 5-V LDO function using input from VDD and
output to VREG. When the VDD voltage rises above 2 V, the internal LDO is enabled and outputs voltage to the
VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry and also provides the
supply voltage for the gate drives.
Figure 30. Power-Up Sequence Voltage Waveforms
NOTE
The 5-V LDO is not controlled by the EN pin. The LDO starts-up any time VDD rises to
approximately 2 V. (see Figure 30).
8.3.2 Adaptive On-Time D-CAP™ Control and Frequency Selection
Neither the TPS53318 nor the TPS53319 device has a dedicated oscillator to determine switching frequency.
However, the device operates with pseudo-constant frequency by feed-forwarding the input and output voltages
into the on-time one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to
the input voltage and proportional to the output voltage as shown in Equation 1.
(1)
This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 1. Maintaining open resistance sets the
switching frequency to 500 kHz.
VFB
Compensation
Ramp
PWM
tON tOFF
VREF
UDG-10209
VFB
VREF
PWM
tON tOFF
UDG-10208
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Table 1. Resistor and Switching Frequency
RESISTOR (RRF)
CONNECTIONS SWITCHING
FREQUENCY
(fSW)
(kHz)
VALUE (kΩ) CONNECT TO
0 GND 250
187 GND 300
619 GND 400
OPEN n/a 500
866 VREG 600
309 VREG 750
124 VREG 850
0 VREG 970
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts a set signal to terminate the off time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time
is extended until the current level falls below the threshold.
The waveforms shown in Figure 31 show on-time control without ramp compensation. The waveforms shown in
Figure 32 show on-time control without ramp compensation.
Figure 31. On-Time Control Without Ramp
Compensation Figure 32. On-Time Control With Ramp
Compensation
8.3.3 Ramp Signal
The TPS53318 and TPS53319 devices add a ramp signal to the 0.6-V reference in order to improve jitter
performance. As described in the previous section, the feedback voltage is compared with the reference
information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the signal-to-
noise ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jittery and
more stable. The ramp signal is controlled to start with –7 mV at the beginning of an on-cycle and becomes 0 mV
at the end of an off-cycle in steady state.
During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than
the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the
ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset.
8.3.4 Adaptive Zero Crossing
The TPS53318 and TPS53319 devices have an adaptive zero crossing circuit which performs optimization of the
zero inductor current detection at skip mode operation. This function pursues ideal low-side MOSFET turning off
timing and compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.
It prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by
too early detection. As a result, better light load efficiency is delivered.
( ) ( )
= ´ + ´ m
n
HIC dly
t 7 2 257 4 s
( ) ( )
= + ´ m
n
HIC wait
t 2 257 4 s
( )
( )
IND(ripple) IN OUT OUT
TRIP TRIP
OCP 3SW IN
DS(on)
IV V V
V R 1
I2 2 L f V
32 R 12.3 10
- ´
= + = + ´
´ ´
´´
( ) ( ) ( )
= W ´ m
TRIP TRIP TRIP
V mV R k I A
16
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8.3.5 Output Discharge Control
When the EN pin becomes low, the TPS53318 and TPS53319 devices discharge the output capacitor using the
internal MOSFET connected between the SW pin and the PGND pin while the high-side and low-side MOSFETs
are maintained in the OFF state. The typical discharge resistance is 75 Ω. The soft discharge occurs only as EN
becomes low. The discharge circuit is powered by VDD. While VDD remains high, the discharge circuit remains
active.
8.3.6 Power-Good
The TPS53318 and TPS53319 devices have power-good output that indicates high when switcher output is
within the target. The power-good function is activated after soft-start has finished. If the output voltage becomes
within +10% and –5% of the target value, internal comparators detect power-good state and the power-good
signal becomes high after a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target
value, the power-good signal becomes low after two microsecond (2-μs) internal delay. The power-good output is
an open drain output and must be pulled up externally.
The power-good MOSFET is powered through the VDD pin. VVDD must be >1 V in order to have a valid power-
good logic. It is recommended to pull PGOOD up to VREG (or a voltage divided from VREG).
8.3.7 Current Sense, Overcurrent and Short Circuit Protection
The TPS53318 and TPS53319 device offer cycle-by-cycle overcurrent limiting control. The inductor current is
monitored during the OFF state and the controller maintains the OFF state during the period in that the inductor
current is larger than the overcurrent trip level. In order to provide both good accuracy and cost effective solution,
TPS53319 device supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be
connected to GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources current (ITRIP) which
is 10 μA typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in
Equation 2.
(2)
The inductor current is monitored by the LL pin. The GND pin is used as the positive current sensing node and
the LL pin is used as the negative current sense node. The trip current, ITRIP has a 3000ppm/°C temperature
slope to compensate the temperature dependency of the RDS(on). For each device, ITRIP is also adjusted based on
the device-specific on-resistance measurement in production tests to eliminate the any OCP variation from
device to device. Duty-cycle should not be over 45% in order to provide the most accurate OCP.
As the comparison is made during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the
load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 3.
where
• RTRIP is in kΩ(3)
In an overcurrent or short-circuit condition, the current to the load exceeds the current to the output capacitor
thus the output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts
down. After a hiccup delay (16 ms plus 0.7 ms soft-start period), the controller restarts. If the overcurrent
condition remains, the procedure is repeated and the device enters hiccup mode.
where
• n = 8, 9, 10, or 11 depending on soft-start time selection (4)
(5)
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Table 2. Hiccup Timing
SELECTED SOFT-START TIME
(tSS)(ms) HICCUP WAIT TIME
(tHIC(wait))(ms) HICCUP DELAY TIME
(tHIC(delay))(ms)
0.7 2.052 14.364
1.4 3.076 21.532
2.8 5.124 35.868
5.6 9.220 64.540
For the TPS53318 device, the OCP threshold is internally clamped to 10.5 A. The recommended RTRIP value for
the TPS53318 device is less than 150 kΩ.
8.3.8 Overvoltage and Undervoltage Protection
The TPS53318 and TPS53319 devices monitor the resistor divided feedback voltage to detect over and under
voltage. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output
goes high and an internal UVP delay counter begins counting. After 1 ms, the device latches OFF both high-side
and low-side MOSFETs drivers. The controller restarts after a hiccup delay (refer to Table 2). This function is
enabled 1.5-ms after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The
output voltage decreases. Before the latch-off action for both the high-side and low-side drivers, the output
voltage must be pulled down below the UVP threshold voltage for a period of 1 ms. After the 1 ms period, the
drivers are latched off.
8.3.9 Redundant Overvoltage Protection (OVP)
The TPS53318 and TPS53319 devices have a redundant input for OVP protection. The ROVP pin senses the
voltage divided from output voltage and sends it to the OVP comparator. If this voltage is higher than 120% of
the target voltage, the overvoltage protection engages and the low-side FET is turned on. When the output
voltage is lower than the UVP threshold then the device latches off.
This redundant OVP function typically protects against a situation where the feedback loop is open or where a
VFB pin short to GND exists. The ROVP pin has an internal 1.5-MΩpull-down resistor.
ROVP PIN DESIGN NOTE
For an application that does not require a redundant OVP feature, the highly preferred
design ties the ROVP pin to GND. If the application cannot allow an ROVP pin connection
to GND, ensure that the design minimizes any potential noise injection to the ROVP pin at
all cost.
8.3.10 UVLO Protection
The TPS53318 and TPS53319 devices use VREG undervoltage lockout protection (UVLO). When the VREG
voltage is lower than 3.95 V, the device shuts off. When the VREG voltage is higher than 4.2 V, the device
restarts. This is a non-latch protection.
8.3.11 Thermal Shutdown
The TPS53318 and TPS53319 devices monitor the internal die temperature. If the temperature exceeds the
threshold value (typically 145°C), the device shuts down. When the temperature falls about 10°C below the
threshold value, the device will turn back on. This is a non-latch protection.
´
> ´
´
OUT ON
L C t
N
R7 C1 2
= £
p ´ ´
SW
0
OUT
f
1
f
2 ESR C 4
( )=´ ´ OUT
1
H s
s ESR C
R1
R2
Voltage
Divider
+
VFB
+
0.6 V
PWM Control
Logic
and
Divider
L
ESR
COUT
VC
RLOAD
IIND IOUT
UDG-12051
IC
Switching Modulator
Output
Capacitor
VOUT
VIN
VIN
LL
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8.3.12 Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 33.
Figure 33. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
(6)
For loop stability, the 0-dB frequency, ƒ0, defined below need to be lower than 1/4 of the switching frequency.
(7)
According to the equation above, the loop stability of D-CAPTM mode modulator is mainly determined by the
capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance in the
order of several 100 µF and ESR in range of 10 mΩ. These makes ƒ0on the order of 100 kHz or less, creating a
stable loop. However, ceramic capacitors have an ƒ0at more than 700 kHz, and need special care when used
with this modulator. An application circuit for ceramic capacitor is described in the External Component Selection
Using All Ceramic Output Capacitors section.
8.3.13 External Component Selection Using All Ceramic Output Capacitors
When a ceramic output capacitor is used, the stability criteria in Equation 7 cannot be satisfied. The ripple
injection approach as shown in Figure 34 is implemented to increase the ripple on the VFB pin and make the
system stable. In addition to the selections made using steps 1 through step 6 in the Detailed Design Procedure
section, the ripple injection components must be selected. The C2 value can be fixed at 1 nF. The value of C1
can be selected between 10 nF to 200 nF.
where
• N is the coefficient to account for L and COUT variation (8)
-
= ´
OUT VFB
VFB
V V
R1 R2
V
+
= + INJ _ SW INJ _ OUT
VFB
V V
V 0.6 2
( )
( )
= ´ + ´ ´
IND ripple
INJ _ OUT IND ripple OUT SW
I
V ESR I 8 C f
-
= ´
´
IN OUT
INJ _ SW
SW
V V D
VR7 C1 f
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N is also used to provide enough margin for stability. It is recommended N = 2 for VOUT ≤1.8 V and N = 4 for
VOUT ≥3.3 V or when L ≤250 nH. The higher VOUT needs a higher N value because the effective output
capacitance is reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor may
have only 8 µF of effective capacitance when biased at 5 V.
Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase
of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node
and the other coupled from the VOUT pin and they can be calculated using Equation 9 and Equation 10 when
neglecting the output voltage ripple caused by equivalent series inductance (ESL).
(9)
(10)
It is recommended that VINJ_SW to be less than 50 mV. If the calculated VINJ_SW is higher than 50 mV, then other
parameters need to be adjusted to reduce it. For example, COUT can be increased to satisfy Equation 8 with a
higher R7 value, thereby reducing VINJ_SW.
The DC voltage at the VFB pin can be calculated by Equation 11:
(11)
And the resistor divider value can be determined by Equation 12:
(12)
8.4 Device Functional Modes
8.4.1 Enable, Soft Start, and Mode Selection
When the EN pin voltage rises above the enable threshold voltage (typically 1.3 V), the controller enters its start-
up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The controller
calibrates the switching frequency setting resistance attached to the RF pin during the first 250 μs. It then stores
the switching frequency code in the internal registers. During this period, the MODE pin also senses the
resistance attached to this pin and determines the soft-start time. Switching is inhibited during this phase. In the
second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the
MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
NOTE
Enable voltage should not higher then VREG for 0.8 V.
(1) Device enters FCCM after the PGOOD pin goes high when MODE is connected to PGOOD through
the resistor RMODE.
Table 3. Soft-Start and MODE Settings
MODE SELECTION ACTION SOFT-START TIME
(tSS) (ms) RMODE (kΩ)
Auto Skip Pull down to GND
0.7 39
1.4 100
2.8 200
5.6 475
Forced CCM(1) Connect to PGOOD
0.7 39
1.4 100
2.8 200
5.6 475
( )
( )
- ´
= ´
´ ´
IN OUT OUT
OUT LL
SW IN
V V V
1
I
2 L f V
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After the soft-start period begins, the MODE pin becomes the input of an internal comparator which determines
auto skip or FCCM mode operation. If MODE voltage is higher than 1.3 V, the converter enters into FCCM mode.
Otherwise it operates in auto skip mode at light-load condition. Typically, when FCCM mode is selected, the
MODE pin connects to the PGOOD pin via the RMODE resistor, so that before PGOOD goes high, the converter
remains in auto skip mode.
8.4.2 Auto-Skip Eco-mode™ Light Load Operation
While RMODEpulls the MODE pin low , the controller automatically reduces the switching frequency at light-load
conditions to maintain high efficiency. More specifically, as the output current decreases from heavy load
condition, the inductor current is also reduced and eventually comes to the point that its rippled valley touches
zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The
synchronous MOSFET is turned off when this zero inductor current is detected. As the load current further
decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is kept almost the same
as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with
smaller load current to the level of the reference voltage. The transition point to the light-load operation IOUT(LL)
(i.e., the threshold between continuous and discontinuous conduction mode) can be calculated as shown in
Equation 13.
where
• ƒSW is the PWM switching frequency (13)
Switching frequency versus output current in the light-load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 13. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
8.4.3 Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load
range which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency.
UDG-12077
RF TRIP MODE VDD VREG VIN VIN VIN VIN VINVIN
TPS53318
TPS53319
VFB EN PGOOD VBST ROVP LL LL LL
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
C5
0.1 µF
VREG
CIN
22 µF
GND
LL LL LL
L1
0.5 µH
HCB1175B-501
VIN
12 V
R4
NI R8
120 NŸ
R6
200 NŸ
C4
1 PFC3
1 PF
CIN
22 µF
CIN
22 µF
CIN
22 µF
COUT
330 µF COUT
330 µF
R11
NI
VOUT
1.2 V
R1
10 NŸ
R2
10 NŸ
R9
0 Ÿ
R10
100 NŸ
PGOOD
EN
VIN
12 V
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS53318 and TPS53319 devices are high-efficiency, single channel, synchronous buck converters suitable
for low output voltage point-of-load applications in computing and similar digital consumer applications. The
device features proprietary D-CAP™ mode control combined with an adaptive on-time architecture. This
combination is ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The
output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 1.5 V to 22 V and the VDD
bias voltage is from 4.5 V to 25 V. The D-CAP™ mode uses the equivalent series resistance (ESR) of the output
capacitor(s) to sense the device current. One advantage of this control scheme is that it does not require an
external phase compensation network allowing for a simple design with a low external component count. Eight
preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG.
Adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while
allowing the switching frequency to increase at the step-up of the load.
9.2 Typical Applications
9.2.1 Application Using Bulk Output Capacitors, Redundant Overvoltage Protection Function (OVP)
Disabled
Figure 34. Typical Application Circuit, Overvoltage Protection Disabled
( ) ( )
( )
()
( )
IN OUT OUT
max
TRIP
IND peak SW IN
DS on max
V V V
V1
I32 R L f V
- ´
= + ´
´ ´
( )
( )
()
( ) ( )
( )
()
IN OUT OUT IN OUT OUT
max max
SW IN OUT SW IN(max)
IND ripple max max
V V V V V V
1 3
LI f V I f V
- ´ - ´
= ´ = ´
´ ´
22
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Typical Applications (continued)
9.2.1.1 Design Requirements
This design uses the parameters listed in Table 4.
Table 4. Design Specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Voltage range 5 12 18 V
IMAX
Maximum input current VIN = 5 V, IOUT = 8 A 2.5 A
No load input current VIN = 12 V, IOUT = 0 A with auto-skip
mode 1 mA
OUTPUT CHARACTERISTICS
VOUT
Output voltage 1.2
V
Output voltage regulation
Line regulation, 5 V ≤VIN ≤14 V with
FCCM 0.2%
Load regulation, VIN = 12 V, 0 A ≤IOUT
≤8 A with FCCM 0.5%
VRIPPLE Output voltage ripple VIN = 12 V, IOUT = 8 A with FCCM 10 mVPP
ILOAD Output load current 0 8 A
IOVER Output overcurrent 11
tSS Soft-start time 1 ms
SYSTEMS CHARACTERISTICS
fSW Switching frequency 500 1000 kHz
ηPeak efficiency VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A 91%
Full load efficiency VIN = 12 V, VOUT = 1.2 V, IOUT = 8 A 91.5%
TAOperating temperature 25 °C
9.2.1.2 Detailed Design Procedure
The external components selection is a simple process when using organic semiconductors or special polymer
output capacitors.
9.2.1.2.1 Step One: Select Operation Mode and Soft-Start Time
Select operation mode and soft-start time using Table 3.
9.2.1.2.2 Step Two: Select Switching Frequency
Select the switching frequency from 250 kHz to 1 MHz using Table 1.
9.2.1.2.3 Step Three: Choose the Inductor
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and helps
ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to maximum output current
ratio, the inductance can be determined by Equation 14.
(14)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak inductor
current before saturation. The peak inductor current can be estimated in Equation 15.
(15)
( )
IN OUT OUT
TRIP OCP
SW IN
V V V
1
R I 12.3
2 L f V
æ ö
- ´
æ ö
= - ´ ´
ç ÷
ç ÷
ç ÷
´ ´
è ø
è ø
( ) ´
- -
= ´
IND ripple
OUT
I ESR
V 0.6
2
R1 R2
0.6
( )
( )
´ ´ - ´ ´ ´
= = = W
´
OUT SW SW
IND ripple
V 10mV (1 D) 10mV L f L f
ESR 0.6 V I 0.6 V 60
23
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9.2.1.2.4 Step Four: Choose the Output Capacitor(s)
When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability,
capacitance and ESR should satisfy Equation 7. For jitter performance, Equation 16 is a good starting point to
determine ESR.
where
• D is the duty factor.
• The required output ripple slope is approximately 10 mV per tSW (switching period) in terms of VFB terminal
voltage. (16)
9.2.1.2.5 Step Five: Determine the Value of R1 and R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 33. R1 is
connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is from 10 kΩto 20 kΩ. Determine R1 using Equation 17.
(17)
9.2.1.2.6 Step Six: Choose the Overcurrent Setting Resistor
The overcurrent setting resistor, RTRIP, can be determined by Equation 18.
where
• RTRIP is in kΩ(18)
9.2.1.3 Application Curves
Figure 35. Start-Up Figure 36. Pre-Bias Start-Up
24
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Figure 37. Shutdown Figure 38. UVLO Start-Up
Figure 39. FCCM Load Transient Figure 40. Skip Mode Load Transeint
Figure 41. Overcurrent Protection Figure 42. Over-Temperature Protection
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TPS53319 EVM VIN = 12 V VOUT = 1.2 V
IOUT = 14 A fSW = 500 kHz TA= 25°C
No airflow
Figure 43. Thermal Signature
TPS53319 EVM VIN = 12 V VOUT = 5 V
IOUT = 14 A fSW = 500 kHz TA= 25°C
No airflow
Figure 44. Thermal Signature
UDG-12076
RF TRIP MODE VDD VREG VIN VIN VIN VIN VINVIN
TPS53318/TPS53319
VFB EN PGOOD VBST ROVP LL LL LL
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
VOUT
1.2V
C5
0.1 µF
VREG
CIN
22 µF
GND
LL LL LL
L1
0.5 ?H
HCB1175B-501
COUT
4 x 100 µF
Ceramic
R1 9.76 k?
R2
10 k?
R10
100 k?
VIN
12V
R13
NI
C6
NI
R9
0?
CIN
22 µF
CIN
22 µF
CIN
22 µF
R6
200 k?
R8
120 k?
R4
NI
C4
1 µF
C3
1 µF
VVDD
4.5 V to 25 V
R7
3.01 k?
C1
0.1 µF
C2
1 nF
EN
PGOOD
R12
10 k?
R11
9.76 k?
26
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9.2.2 Application Using Ceramic Output Capacitors, Redundant Overvoltage Protection Function (OVP)
Enabled
Figure 45. Typical Application Circuit, Redundent OVP Enabled
9.2.2.1 Design Requirements
This design uses the parameters listed in Table 4.
9.2.2.2 Detailed Design Procedure
The detailed design procedure for this design example is similar to the procedure for the previous design
example. The differences are discussed in the following two sections.
9.2.2.2.1 External Component Selection Using All Ceramic Output Capacitors
Refer to External Component Selection Using All Ceramic Output Capacitors for guidelines for this design with all
ceramic output capacitors.
9.2.2.2.2 Redundant Overvoltage Protection
The redundant overvoltage level is programmed according to the output voltage setting, it is controlled by
resistors R11 and R12 as shown in Figure 45. Connect resistor R11 between the ROVP pin and the output, and
connect resistor R12 between the ROVP pin and GND. This design recommends that the value of resistor R11
match the value of resistor R1 (or slightly higher), and that the value of resistor R2 match the value of resistor
R12.
27
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9.2.2.3 Application Curves
Figure 46. Start-Up Figure 47. Pre-Bias Start-Up
Figure 48. Shutdown Figure 49. UVLO Start-Up
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 1.5 V and 22 V (4.5 V to 25 V
biased). This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is
also critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in the
Layout section.
11 Layout
11.1 Layout Guidelines
• The power components (including input/output capacitors, inductor and TPS53318 device or TPS53319
device) should be placed on one side of the PCB (solder side). At least one inner plane should be inserted,
connected to ground, in order to shield and isolate the small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
To GND Plane
Bottom side
components and trace
Bottom side
component
and trace
GND shape
Keep VFB trace short and
away from noisy signals
VIN shape VOUT shape
LL shape
MODE
TRIP
RF
VDD
VREG
PGOOD
EN
VFB
VOUT
GND
Bottom side
components and trace
VBST
UDG-13111
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Layout Guidelines (continued)
plane(s) and shield feedback trace from power traces and components.
• Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
• Because the TPS53319 device controls output voltage referring to voltage across VOUT capacitor, the top-
side resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND
of the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors
to the VFB pin should be short and thin.
• Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as
close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
• Place the VDD and VREG decoupling capacitors as close to the device as possible. Ensure to provide GND
vias for each decoupling capacitor and make the loop as small as possible.
• For better noise filtering on VDD, a dedicated and localized decoupling support is strongly recommended.
• The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
• Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 45) from the terminal of
ceramic output capacitor. The AC coupling capacitor (C2 in Figure 45) should be placed near the device, and
R7 and C1 can be placed near the power stage.
• Use separated vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor.
Do not combine these connections.
11.2 Layout Example
Figure 50. Layout Recommendation
29
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
Reference Design: 7-V to 12-V Input, 1.2-V Output, 8-A Step-Down Converter for Powering Rails in Altera Arria V
FPGA, PMP8824
Evaluation Module: Synchronous Switcher with Integrated MOSFETs, TPS53319EVM-136
TPS53318 TINA-TI Transient Spice Model, SLUM381
12.2 Related Links
Table 5 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 5. Related Links
DEVICES PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TPS53318 Click here Click here Click here Click here Click here
TPS53319 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
Eco-mode, D-CAP, NexFET, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS53318DQPR ACTIVE LSON-CLIP DQP 22 2500 Pb-Free (RoHS
Exempt) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 53318DQP
TPS53318DQPT ACTIVE LSON-CLIP DQP 22 250 Pb-Free (RoHS
Exempt) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 53318DQP
TPS53319DQPR ACTIVE LSON-CLIP DQP 22 2500 Pb-Free (RoHS
Exempt) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 53319DQP
TPS53319DQPT ACTIVE LSON-CLIP DQP 22 250 Pb-Free (RoHS
Exempt) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 53319DQP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2016
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53318DQPR LSON-
CLIP DQP 22 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
TPS53318DQPT LSON-
CLIP DQP 22 250 180.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
TPS53319DQPR LSON-
CLIP DQP 22 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
TPS53319DQPT LSON-
CLIP DQP 22 250 180.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Jul-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53318DQPR LSON-CLIP DQP 22 2500 367.0 367.0 35.0
TPS53318DQPT LSON-CLIP DQP 22 250 210.0 185.0 35.0
TPS53319DQPR LSON-CLIP DQP 22 2500 367.0 367.0 35.0
TPS53319DQPT LSON-CLIP DQP 22 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Jul-2018
Pack Materials-Page 2
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