LM317LITPXNOPB - TEXAS INSTRUMENTS

Wideband Synthesizer with Integrated VCO

ADF4350

Rev. A

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FEATURES

Output frequency range: 137.5 MHz to 4400 MHz

Fractional-N synthesizer and integer-N synthesizer

Low phase noise VCO

Programmable divide-by-1/-2/-4/-8/-16 output

Typical rms jitter: <0.4 ps rms

Power supply: 3.0 V to 3.6 V

Logic compatibility: 1.8 V

Programmable dual-modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

Switched bandwidth fast-lock mode

Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,

GSM, PCS, DCS, DECT)

Test equipment

Wireless LANs, CATV equipment

Clock generation

GENERAL DESCRIPTION

The ADF4350 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

if used with an external loop filter and external reference

frequency.

The ADF4350 has an integrated voltage controlled oscillator

(VCO) with a fundamental output frequency ranging from

2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16

circuits allow the user to generate RF output frequencies as low

as 137.5 MHz. For applications that require isolation, the RF

output stage can be muted. The mute function is both pin- and

software-controllable. An auxiliary RF output is also available,

which can be powered down if not in use.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

MUXOUT

OUT

COM

TEMP

REF

CLK

DATA

SDV

AGND

CE DGND CP

GND

GNDVCO

SET

VCO

TUNE

REF

OUT

A+

OUT

A–

OUT

B+

OUT

B–

VCO

CORE

PHASE

COMPARATOR

SWITCH

CHARGE

PUMP

OUTPUT

STAGE

OUTPUT

STAGE

PDB

MULTIPLEXER

10-BIT R

COUNTER

÷2

DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGISTER

INTEGER

REG

N COUNTER

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

MULTIPLEXER

LOCK

DETECT

÷1/2/4/8/16

ADF4350

07325-001

Figure 1.

ADF4350

Rev. A | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description......................................................................... 11

Reference Input Section............................................................. 11

RF N Divider............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship.................... 11

INT N MODE ............................................................................. 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and LOCK Detect................................................... 12

Input Shift Registers................................................................... 12

Program Modes .......................................................................... 12

VCO.............................................................................................. 12

Output Stage................................................................................ 13

Initialization Sequence .............................................................. 21

RF Synthesizer—A Worked Example ...................................... 21

Modulus....................................................................................... 21

Reference Doubler and Reference Divider ............................. 21

12-Bit Programmable Modulus................................................ 21

Cycle Slip Reduction for Faster Lock Times........................... 22

Spurious Optimization and Fast lock ...................................... 22

Fast-Lock Timer and Register Sequences ............................... 22

Fast Lock—An Example............................................................ 22

Fast Lock—Loop Filter Topology............................................. 23

Spur Mechanisms ....................................................................... 23

Spur Consistency and Fractional Spur Optimization ........... 24

Phase Resync............................................................................... 24

Applications Information.............................................................. 25

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for a Chip Scale Package ................. 26

Output Matching........................................................................ 27

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

REVISION HISTORY

4/11—Rev. 0 to Rev. A

Changes to Typical rms Jitter in Features Section........................ 1

Changes to Specifications................................................................ 3

Changes Output Stage Section...................................................... 13

Changes to Figure 29...................................................................... 17

Changes to Fast Lock—An Example Section.............................. 22

Changes to Direct Conversion Modulator Section and

Figure 34 ......................................................................................... 25

Changes to ADuC70xx Interface Section and ADSP-BF527

Interface Section ............................................................................. 26

Changes to Output Matching Section and Table 7..................... 27

Added Table 8.................................................................................. 28

Changes to Ordering Guide .......................................................... 29

11/08—Revision 0: Initial Version

ADF4350

Rev. A | Page 3 of 32

SPECIFICATIONS

AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating

temperature range is −40°C to +85°C.

Table 1.

B Version

Parameter Min Typ Max

Unit Conditions/Comments

REFIN CHARACTERISTICS

Input Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/μs

Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21

Input Capacitance 10 pF

Input Current ±60 μA

PHASE DETECTOR

Phase Detector Frequency2 32 MHz

CHARGE PUMP

ICP Sink/Source3 With RSET = 5.1 kΩ

High Value 5 mA

Low Value 0.312 mA

RSET Range 2.7 10 kΩ

Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ 2.5 V

ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ 2.5 V

ICP vs. Temperature 2 % VCP = 2.0 V

LOGIC INPUTS

Input High Voltage, VINH 1.5 V

Input Low Voltage, VINL 0.6 V

Input Current, IINH/IINL ±1 μA

Input Capacitance, CIN 3.0 pF

LOGIC OUTPUTS

Output High Voltage, VOH DVDD − 0.4 V CMOS output chosen

Output High Current, IOH 500 μA

Output Low Voltage, VOL 0.4 V IOL = 500 μA

POWER SUPPLIES

AVDD 3.0 3.6 V

DVDD, VVCO, SDVDD, VP AVDD These voltages must equal AVDD

DIDD + AIDD4 21 27 mA

Output Dividers 6 to 24 mA Each output divide-by-2 consumes 6 mA

IVCO4 70 80 mA

IRFOUT4 21 26 mA RF output stage is programmable

Low Power Sleep Mode 7 1000 μA

RF OUTPUT CHARACTERISTICS

Maximum VCO Output Frequency 4400 MHz

Minimum VCO Output Frequency 2200 MHz Fundamental VCO mode

Minimum VCO Output Frequency

Using Dividers

137.5 MHz 2200 MHz fundamental output and divide by 16 selected

VCO Sensitivity 33 MHz/V

Frequency Pushing (Open-Loop) 1 MHz/V

Frequency Pulling (Open-Loop) 90 kHz Into 2.00 VSWR load

Harmonic Content (Second) −19 dBc Fundamental VCO output

Harmonic Content (Third) −13 dBc Fundamental VCO output

Harmonic Content (Second) −20 dBc Divided VCO output

Harmonic Content (Third) −10 dBc Divided VCO output

Minimum RF Output Power 5 −4 dBm Programmable in 3 dB steps

Maximum RF Output Power5 5 dBm

Output Power Variation ±1 dB

Minimum VCO Tuning Voltage 0.5 V

Maximum VCO Tuning Voltage 2.5 V

ADF4350

Rev. A | Page 4 of 32

B Version

Parameter Min Typ Max

Unit Conditions/Comments

NOISE CHARACTERISTICS

VCO Phase-Noise Performance6 −89 dBc/Hz 10 kHz offset from 2.2 GHz carrier

−114 dBc/Hz 100 kHz offset from 2.2 GHz carrier

−134 dBc/Hz 1 MHz offset from 2.2 GHz carrier

−148 dBc/Hz 5 MHz offset from 2.2 GHz carrier

−86 dBc/Hz 10 kHz offset from 3.3 GHz carrier

−111 dBc/Hz 100 kHz offset from 3.3 GHz carrier

−134 dBc/Hz 1 MHz offset from 3.3 GHz carrier

−145 dBc/Hz 5 MHz offset from 3.3 GHz carrier

−83 dBc/Hz 10 kHz offset from 4.4 GHz carrier

−110 dBc/Hz 100 kHz offset from 4.4 GHz carrier

−132 dBc/Hz 1 MHz offset from 4.4 GHz carrier

−145 dBc/Hz 5 MHz offset from 4.4 GHz carrier

Normalized Phase Noise Floor

(PNSYNTH)7

−220 dBc/Hz PLL Loop BW = 500 kHz

Normalized 1/f Noise (PN1_f)8 −111 dBc/Hz 10 kHz offset; normalized to 1 GHz

In-Band Phase Noise9 −97 dBc/Hz 3 kHz offset from 2113.5 MHz carrier

Integrated RMS Jitter10 0.5 ps

Spurious Signals Due to PFD Frequency −70 dBc

Level of Signal With RF Mute Enabled −40 dBm

1 AC coupling ensures AVDD/2 bias.

2 Guaranteed by design. Sample tested to ensure compliance.

3 ICP is internally modified to maintain constant loop gain over the frequency range.

4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz.

5 Using 50 Ω resistors to VVCO, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the

main output.

6 The noise of the VCO is measured in open-loop conditions.

7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.

8 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,

and at a frequency offset f is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

9 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 10 kHz; VCO frequency = 4227 MHz, output divide by two enabled. RFOUT = 2113.5 MHz; N = 169; loop BW = 40 kHz,

ICP = 313 μA; low noise mode. The noise was measured with an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.

10 fREFIN = 100 MHz; fPFD = 25 MHz; VCO frequency = 4400 MHz, RFOUT = 4400 MHz; N = 176; loop BW = 40 kHz, ICP = 313 μA; low noise mode. The noise was measured with

an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.

ADF4350

Rev. A | Page 5 of 32

TIMING CHARACTERISTICS

AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless

otherwise noted.

Table 2.

Parameter Limit (B Version) Unit Test Conditions/Comments

t1 20 ns min LE setup time

t2 10 ns min DATA to CLK setup time

t3 10 ns min DATA to CLK hold time

t4 25 ns min CLK high duration

t5 25 ns min CLK low duration

t6 10 ns min CLK to LE setup time

t7 20 ns min LE pulse width

CLK

DATA

DB31 (MSB) DB30 DB1

(CONTROL BIT C2)

DB2

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

07325-002

Figure 2. Timing Diagram

ADF4350

Rev. A | Page 6 of 32

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V

AVDD to DVDD −0.3 V to +0.3 V

VVCO to GND −0.3 V to +3.9 V

VVCO to AVDD −0.3 V to +0.3 V

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V

Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V

REFIN to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +125°C

Maximum Junction Temperature 150°C

LFCSP θJA Thermal Impedance 27.3°C/W

(Paddle-Soldered)

Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

1 GND = AGND = DGND = 0 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

This device is a high-performance RF integrated circuit with an

ESD rating of <0.5 kV and is ESD sensitive. Proper precautions

should be taken for handling and assembly.

TRANSISTOR COUNT

24202 (CMOS) and 918 (bipolar)

ESD CAUTION

ADF4350

Rev. A | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

DATA

REF

COM

SDV

ADF4350

TOP VIEW

(Not to Scale)

AGND

REF

DGND

GND

PIN 1

INDICATOR

OUT

GND

MUXOUT

SET

OUT

A+

OUT

B+

OUT

B−

OUT

A−

VCO

TUNE

GNDVCO

TEM

PDB

GNDVCO

VCO

07325-003

NOTES

1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2 DATA

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

A logic high on this pin powers up the device depending on the status of the power-down bits.

5 SW Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode.

6 VP Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to

be placed as close as possible to this pin.

7 CPOUT Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter is

connected to VTUNE to drive the internal VCO.

8 CPGND Charge Pump Ground. This is the ground return pin for CPOUT.

9 AGND Analog Ground. This is a ground return pin for AVDD.

10 AVDD Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are

to be placed as close as possible to this pin. AVDD must have the same value as DVDD.

11, 18, 21 AGNDVCO VCO Analog Ground. These are the ground return pins for the VCO.

12 RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.

13 RFOUTA− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided

down version is available.

14 RFOUTB+ Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down

version is available.

15 RFOUTB− Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a

divided down version is available.

16, 17 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to these pins. VVCO must have the same value as AVDD.

19 TEMP

Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as

possible to this pin.

20 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT

output voltage.

ADF4350

Rev. A | Page 8 of 32

Pin No. Mnemonic Description

22 RSET Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is

SET

CP R

25.5

where:

RSET = 5.1 kΩ

ICP = 5 mA

23 VCOM Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane

should be placed as close as possible to this pin.

24 VREF Reference Voltage. Decoupling capacitors to the ground plane should be placed as close as possible to this pin.

25 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.

26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.

27 DGND Digital Ground. Ground return path for DVDD.

28 DVDD Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane

should be placed as close as possible to this pin.

29 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

30 MUXOUT

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

31 SDGND Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.

32 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDD. Decoupling capacitors to

the ground plane are to be placed as close as possible to this pin.

33 EP Exposed Pad.

ADF4350

Rev. A | Page 9 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

–150

–160

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–

1k 10k 100k 1M 10M 100M

07325-028

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz

1k 10k 100k 1M 10M 100M

07325-029

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–150

–160

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–

Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz

–140

–120

–100

–80

–130

–160

–150

–110

–90

–70

–60

–50

–

1k 10k 100k 1M 10M 100M

07325-030

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz

–170

–160

–150

–140

–130

–120

–110

–100

–90

–

–80

1k 10k 100k 1M 10M 100M

07325-031

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

FUND

DIV2

DIV4

DIV8

DIV16

Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 2.2 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

–170

–160

–150

–140

–130

–120

–110

–100

–90

–

–80

PHASE NOISE (dBc/Hz)

FUND

DIV2

DIV4

DIV8

DIV16

1k 10k 100k 1M 10M 100M

07325-032

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 3.3 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

–170

–160

–150

–140

–130

–120

–110

–100

–90

–

–80

FUND

DIV2

DIV4

DIV8

DIV16

1k 10k 100k 1M 10M 100M

07325-033

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 4.4 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

ADF4350

Rev. A | Page 10 of 32

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-034

10M

Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band,

RFOUT = 904 MHz, REFIN = 100 MHz, PFD = 800 kHz, Output Divide-by-4

Selected; Loop-Filter Bandwidth = 16 kHz, Channel Spacing = 200 kHz.

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-035

10M

Figure 11. Fractional-N Spur Performance; Low Noise Mode. W-CDMA Band,

RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2

Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz.

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-036

10M

Figure 12. Fractional-N Spur Performance. Low Spur Mode, W-CDMA Band

RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2

Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-037

10M

Figure 13. Fractional-N Spur Performance. Low Noise Mode, RFOUT =

2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected;

Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz.

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-038

10M

Figure 14. Fractional-N Spur Performance. Low Spur Mode RFOUT =

2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected.

Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz (Note That

Fractional Spurs Are Removed and Only the Integer Boundary Spur Remains

in Low Spur Mode).

2.95

2.96

2.97

2.98

2.99

3.00

3.01

3.02

FREQUENCY (GHz)

CSR OFF

CSR ON

0 100 200 300

TIME (µs)

400 500 600

07325-039

Figure 15. Lock Time for 100 MHz Jump from 3070 MHz to 2970 MHz with

CSR On and Of f, PFD = 25 MHz, ICP = 313 μA, Loop Filter Bandwidth = 20 kHz

ADF4350

Rev. A | Page 11 of 32

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 16. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

during power-down.

07325-005

BUFFER

TO R COUNTER

REF

100kΩ

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 16. Reference Input Stage

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. The division ratio is determined by INT, FRAC and MOD

values, which build up this divider.

INT, FRAC, MOD, AND R COUNTER RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the

R counter, make it possible to generate output frequencies

that are spaced by fractions of the PFD frequency. See the RF

Synthesizer—A Worked Example section for more information.

The RF VCO frequency (RFOUT) equation is

RFOUT = fPFD × (INT + (FRAC/MOD)) (1)

where RFOUT is the output frequency of external voltage

controlled oscillator (VCO).

INT is the preset divide ratio of the binary 16-bit counter

(23 to 65535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).

MOD is the preset fractional modulus (2 to 4095).

FRAC is the numerator of the fractional division (0 to MOD − 1).

fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

T is the REFIN divide-by-2 bit (0 or 1).

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

MOD

REG

INT

REG

RF N DIVIDER N = INT + FRAC/MOD

FROM

VCO OUTPUT/

OUTPUT DIVIDERS TO PFD

N COUNTER

07325-006

Figure 17. RF INT Divider

INT N MODE

If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the

synthesizer operates in integer-N mode. The DB8 in Register 2

(LDF) should be set to 1 to get integer-N digital lock detect.

R COUNTER

The 10–bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the

R counter and N counter and produces an output proportional

to the phase and frequency difference between them. Figure 18

is a simplified schematic of the phase frequency detector. The

PFD includes a fixed delay element that sets the width of the

antibacklash pulse, which is typically 3 ns. This pulse ensures

there is no dead zone in the PFD transfer function, and gives a

consistent reference spur level.

CLR2

Q2D2

DOWN

HIGH

–IN

CHARGE

PUMP

DELAY

CLR1

Q1D1

07325-007

Figure 18. PFD Simplified Schematic

ADF4350

Rev. A | Page 12 of 32

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4350 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (for details,

see Figure 26). Figure 19 shows the MUXOUT section in

block diagram form.

DGND

CONTROL

MUX

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

DGND

RESERVED

THREE-STATE OUTPUT

Figure 19. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4350 digital section includes a 10–bit RF R counter,

a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit

modulus counter. Data is clocked into the 32–bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined by

the state of the three control bits (C3, C2, and C1) in the shift

in Figure 2. The truth table for these bits is shown in Table 5.

Figure 23 shows a summary of how the latches are programmed.

Table 5. C3, C2, and C1 Truth Table

Control Bits

C3 C2 C1 Register

0 0 0 Register 0 (R0)

0 0 1 Register 1 (R1)

0 1 0 Register 2 (R2)

0 1 1 Register 3 (R3)

1 0 0 Register 4 (R4)

1 0 1 Register 5 (R5)

PROGRAM MODES

Tabl e 5 and Figure 23 through Figure 29 show how the program

modes are to be set up in the ADF4350.

A number of settings in the ADF4350 are double buffered.

These include the modulus value, phase value, R counter value,

reference doubler, reference divide-by-2, and current setting.

This means that two events have to occur before the part uses

a new value of any of the double buffered settings. First, the

new value is latched into the device by writing to the appropriate

For example, any time the modulus value is updated, Register 0

(R0) must be written to, to ensure the modulus value is loaded

correctly. Divider select in Register 4 (R4) is also double buf-

fered, but only if DB13 of Register 2 (R2) is high.

VCO

The VCO core in the ADF4350 consists of three separate VCOs

each of which uses 16 overlapping bands, as shown in Figure 20,

to allow a wide frequency range to be covered without a large

VCO sensitivity (KV) and resultant poor phase noise and spu-

rious performance.

The correct VCO and band are chosen automatically by the

VCO and band select logic at power-up or whenever Register 0

(R0) is updated.

VCO and band selection take 10 PFD cycles × band select clock

divider value. The VCO VTUNE is disconnected from the output

of the loop filter and is connected to an internal reference voltage.

2.8

2.4

2.0

1.6

0.8

1.2

0.4

1800

2000

2200

2400

2600

2800

3000

3200

3400

3600

3800

4000

4200

4400

4600

07325-009

FREQUENCY (MHz)

TUNE

(V)

Figure 20. VTUNE vs. Frequency

The R counter output is used as the clock for the band select

logic. A programmable divider is provided at the R counter

output to allow division by 1 to 255 and is controlled by

Bits [BS8:BS1] in Register 4 (R4). When the required PFD

frequency is higher than 125 kHz, the divide ratio should be

set to allow enough time for correct band selection.

After band select, normal PLL action resumes. The nominal

value of KV is 33 MHz/V when the N-divider is driven from the

VCO output or this value divided by D. D is the output divider

value if the N-divider is driven from the RF divider output

(chosen by programming Bits [D12:D10] in Register 4 (R4).

The ADF4350 contains linearization circuitry to minimize

any variation of the product of ICP and KV to keep the loop

bandwidth constant.

ADF4350

Rev. A | Page 13 of 32

OUTPUT STAGE

The VCO shows variation of KV as the VTUNE varies within the

band and from band-to-band. It has been shown for wideband

applications covering a wide frequency range (and changing

output dividers) that a value of 33 MHz/V provides the most

accurate KV as this is closest to an average value. Figure 21

shows how KV varies with fundamental VCO frequency along

with an average value for the frequency band. Users may prefer

this figure when using narrowband designs.

The RFOUTA+ and RFOUTA− pins of the ADF4350 are connected

to the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 22. To allow the user to

optimize the power dissipation vs. the output power requirements,

the tail current of the differential pair is programmable by

Bits [D2:D1] in Register 4 (R4). Four current levels may be set.

These levels give output power levels of −4 dBm, −1 dBm, +2

dBm, and +5 dBm, respectively, using a 50 Ω resistor to AVDD

and ac coupling into a 50 Ω load. Alternatively, both outputs

can be combined in a 1 + 1:1 transformer or a 180° microstrip

coupler (see the Output Matching section). If the outputs are

used individually, the optimum output stage consists of a shunt

inductor to VVCO. The unused complementary output must

be terminated with a similar circuit to the used output.

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6

07325-133

VCO SENSITIVITY (MHz/V)

FREQUENCY (GHz)

An auxiliary output stage exists on Pins RFOUTB+ and RFOUTB−

providing a second set of differential outputs which can be

used to drive another circuit, or which can be powered down

if unused. The auxiliary output must be used in conjunction

with the main RF output. It cannot be used with the main

output powered down.

Another feature of the ADF4350 is that the supply current to

the RF output stage can be shut down until the part achieves

lock as measured by the digital lock detect circuitry. This is

enabled by the mute till lock detect (MTLD) bit in Register 4 (R4).

Figure 21. KV vs. Frequency

In fixed frequency applications, the ADF4350 VTUNE may

vary with ambient temperature switching from hot to cold.

In extreme cases, the drift causes VTUNE to drop to a very low

level (<0.25 V) and can cause loss of lock. This becomes an

issue only at fundamental VCO frequencies less than 2.95 GHz

and at ambient temperatures below 0°C.

VCO

OUT

A+ RF

OUT

–

BUFFER/

DIVIDE-BY-

1/2/4/8/16

07325-010

In cases such as these, if the ambient temperature decreases

below 0°C, the frequency needs to be reprogrammed (R0 updated)

to avoid VTUNE dropping to a level close to 0 V. Reprogramming

the part chooses a more suitable VCO band, and thus avoids

the low VTUNE issue. Any further temperature drops of more

than 20°C (below 0°C) also require further reprogramming.

Any increases in the ambient temperature do not require repro-

gramming.

Figure 22. Output Stage

ADF4350

Rev. A | Page 14 of 32

07325-011

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0N16 N15 N14 N13 N12 N11 N10 N9

RESERVED

16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC) CONTROL

BITS

N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 PR1 P12 P11 P10 P9

12-BIT PHASE VALUE (PHASE) 12-BIT MODULUS VALUE (MOD) CONTROL

BITS

P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)

CSR

RDIV2

REFERENCE

DOUBLER

CHARGE

PUMP

CURRENT

SETTING

10-BIT R COUNTER CONTROL

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)

CONTROL

BITS

12-BIT CLOCK DIVIDER VALUE

LDP

POLARITY

CP THREE-

STATE

COUNTER

RESET

OUTPUT

POWER

CLK

DIV

MODE

DBR 1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.

RESERVED

LDF

RESERVED

VCO POWER

DOWN

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)

CONTROL

BITS

8-BIT BAND SELECT CLOCK DIVIDER VALUE

RF OUTPUT

ENABLE

LD PIN

MODE

AUX OUTPUT

ENABLE

AUX OUTPUT

SELECT

MTLD

DIVIDER

SELECT

FEEDBACK

SELECT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000D15D140110000000000000000C3(1)C2(0)C1(1)

CONTROL

BITS

RESERVED

DBB 2

DOUBLE BUFF

RESERVED

DBR

AUX

OUTPUT

POWER

RESERVED

PRESCALER

LOW

NOISE AND

LOW SPUR

MODES MUXOUT

Figure 23. Register Summary

ADF4350

Rev. A | Page 15 of 32

07325-012

N16N15...N5N4N3N2N1 INTEGER VALUE (INT)

00...00000 NOT ALLOWED

00...00001 NOT ALLOWED

00...00010 NOT ALLOWED

.......... ...

00...10110 NOT ALLOWED

00...10111 23

00...11000 24

.......... ...

11...11101 65533

11...11110 65534

11...11111 65535

F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC)

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 4092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 ......... 1 1 4095

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0N16 N15 N14 N13 N12 N11 N10 N9

RESERVED

16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC)

CONTROL

BITS

N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)

INTmin = 75 with prescaler = 8/9

Figure 24. Register 0 (R0)

7325-013

P12 P11 .......... P2 P1 PHASE VALUE (PHASE)

0 0 .......... 0 0 0

0 0 .......... 0 1 1 (RECOMMENDED)

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 4092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 .......... 1 1 4095

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 PR1 P12 P11 P10 P9

12-BIT PHASE VALUE (PHASE) 12-BIT MODULUS VALUE (MOD)

CONTROL

BITS

P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

RESERVED

M12 M11 ..........

..........

M2 M1 INTERPOLATOR MODULUS (MOD)

00 102

00 113

.. ...

1 1 0 0 4092

1 1 0 1 4093

1 1 1 0 4094

1 1 1 1 4095

PRESCALER

P1 PRESCALER

04/5

18/9

DBR DBR

Figure 25. Register 1 (R1)

ADF4350

Rev. A | Page 16 of 32

07325-014

RD2 REFERENCE

DOUBLER

0DISABLED

1 ENABLED

RD1 REFERENCE DIVIDE BY 2

0DISABLED

1 ENABLED

CP4 CP3 CP2 CP1

ICP (mA)

5.1kΩ

00000.31

00010.63

00100.94

00111.25

01001.56

01011.88

01102.19

01112.50

10002.81

10013.13

10103.44

10113.75

11004.06

11014.38

11104.69

11115.00

R10 R9 ..........

..........

R2 R1 R DIVIDER (R)

00 011

00 102

.. ...

11 001020

11 011021

11 101022

11 111023

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)

RDIV2 DBR

REFERENCE

DOUBLER DBR

CHARGE

PUMP

CURRENT

SETTING

10-BIT R COUNTER DBR

CONTROL

BITS

LDP

POLARITY

POWER-DOWN

CP THREE-

STATE

COUNTER

RESET

LDF

MUXOUT

DOUBLE BUFF

U5 LDP

0 10ns

16ns

U4 PD POLARITY

0NEGATIVE

1 POSITIVE

U3 POWER DOWN

0DISABLED

1 ENABLED

U2 CP

THREE-STATE

0DISABLED

1 ENABLED

U1 COUNTER

RESET

0DISABLED

1 ENABLED

D1 DOUBLEBUFFER

R4 DB22-20

0DISABLED

1 ENABLED

U6 LDF

0 FRAC-N

1INT-N

RESERVED

M3 M2 M1 OUTPUT

0 0 0 THREE-STATE OUTPUT

00 1DV

01 0DGND

0 1 1 R DIVIDER OUTPUT

1 0 0 N DIVIDER OUTPUT

1 0 1 ANALOG LOCK DETECT

1 1 0 DIGITAL LOCK DETECT

1 1 1 RESERVED

L1 L2 NOISE MODE

00LOWNOISEMODE

0 1 RESERVED

1 0 RESERVED

11LOWSPURMODE

LOW

NOISE AND

LOW SPUR

MODES

Figure 26. Register 2 (R2)

07325-015

C2 C 1 CLOCK DIVIDER MODE

0 0 CLOCK DIVIDER OFF

0 1 FAST-LOCK ENABLE

1 0 RESYNC ENABLE

1 1 RESERVED

D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 4092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 .......... 1 1 4095

CSR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)

CONTROL

BITS12-BIT CLOCK DIVIDER VALUE

CLK

DIV

MODE

RESERVED

F1 CYCLE SLIP

REDUCTION

0DISABLED

1 ENABLED

RESERVED

Figure 27. Register 3 (R3)

ADF4350

Rev. A | Page 17 of 32

07325-016

BS8 BS7 ..........

..........

BS2 BS1 BAND SELECT CLOCK DIVIDER (R)

00 011

00 102

.. ...

1 1 0 0 252

1 1 0 1 253

1 1 1 0 254

11 11255

D3 RF OUT

0 DISABLED

1 ENABLED

OUTPUT

POWER

VCO POWER-

DOWN

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)

CONTROL

BITS

8-BIT BAND SELECT CLOCK DIVIDER VALUE

RF OUTPUT

ENABLE

AUX

OUTPUT

POWER

AUX OUTPUT

ENABLE

AUX OUTPUT

SELECT

MTLD

DIVIDER

SELECT

FEEDBACK

SELECT

RESERVED

D2 D1 OUTPUT POWER

00-4

01-1

10+2

11+5

D5 D4 AUX OUTPUT POWER

00-4

01-1

10+2

11+5

D6 AUX OUT

0 DISABLED

1 ENABLED

AUX OUTPUT

SELECT

FUNDAMENTAL

DIVIDED OUTPUT

D8 MUTE TILL

LOCK DETECT

0 MUTE DISABLED

1 MUTE ENABLED

D9 VCO

POWER-DOWN

0VCO POWERED UP

1 VCO POWERED DOWN

D12 D11 RF DIVIDER SELECT

00 ÷1

00 ÷2

01 ÷4

01 ÷8

D10

10 ÷160

D13 FEEDBACK

SELECT

FUNDAMENTAL

DIVIDED

DBB

Figure 28. Register 4 (R4)

07325-017

LD PIN

MODE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000D15D140110000000000000000C3(1)C2(0)C1(1)

CONTROL

BITSRESERVEDRESERVED

RESERVED

D1 5 D1 4 LOCK DETECT PIN OPERATION

00LOW

0 1 DIGITAL LOCK DETECT

10LOW

11HIGH

RESERVED

Figure 29. Register 5 (R5)

ADF4350

Rev. A | Page 18 of 32

Control Bits

With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed.

Figure 24 shows the input data format for programming this

16-Bit INT Value

These sixteen bits set the INT value, which determines the

integer part of the feedback division factor. It is used in

Equation 1 (see the INT, FRAC, MOD, and R Counter

Relationship section). All integer values from 23 to 65,535

are allowed for 4/5 prescaler. For 8/9 prescaler, the minimum

integer value is 75.

12-Bit FRAC Value

The 12 FRAC bits set the numerator of the fraction that is input

to the Σ-Δ modulator. This, along with INT, specifies the new

frequency channel that the synthesizer locks to, as shown in the

RF Synthesizer—A Worked Example section. FRAC values from

0 to MOD − 1 cover channels over a frequency range equal to

the PFD reference frequency.

Control Bits

With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed.

Figure 25 shows the input data format for programming

this register.

Prescaler Value

The dual modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division

ratio from the VCO output to the PFD input.

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating the

ADF4350 above 3 GHz, this must be set to 8/9. The prescaler

limits the INT value, where P is 4/5, NMIN is 23 and P is 8/9,

NMIN is 75.

In the ADF4350, PR1 in Register 1 sets the prescaler values.

12-Bit Phase Value

These bits control what is loaded as the phase word. The word

must be less than the MOD value programmed in Register 1.

The word is used to program the RF output phase from 0° to

360° with a resolution of 360°/MOD. See the Phase Resync

section for more information. In most applications, the phase

relationship between the RF signal and the reference is not

important. In such applications, the phase value can be used

to optimize the fractional and subfractional spur levels. See the

Spur Consistency and Fractional Spur Optimization section for

more information.

If neither the phase resync nor the spurious optimization

functions are being used, it is recommended the PHASE

word be set to 1.

12-Bit Interpolator MOD Value

This programmable register sets the fractional modulus. This

is the ratio of the PFD frequency to the channel step resolution

on the RF output. See the RF Synthesizer—A Worked Example

section for more information.

Control Bits

With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed.

Figure 26 shows the input data format for programming this

Low Noise and Low Spur Modes

The noise modes on the ADF4350 are controlled by DB30 and

DB29 in Register 2 (see Figure 26). The noise modes allow the

user to optimize a design either for improved spurious perfor-

mance or for improved phase noise performance.

When the lowest spur setting is chosen, dither is enabled. This

randomizes the fractional quantization noise so it resembles

white noise rather than spurious noise. As a result, the part is

optimized for improved spurious performance. This operation

would normally be used when the PLL closed-loop bandwidth

is wide, for fast-locking applications. Wide loop bandwidth is

seen as a loop bandwidth greater than 1/10 of the RFOUT channel

step resolution (fRES). A wide loop filter does not attenuate the

spurs to the same level as a narrow loop bandwidth.

For best noise performance, use the lowest noise setting option.

As well as disabling the dither, this setting also ensures that the

charge pump is operating in an optimum region for noise

performance. This setting is extremely useful where a narrow

loop filter bandwidth is available. The synthesizer ensures

extremely low noise and the filter attenuates the spurs. The

typical performance characteristics give the user an idea of

the trade-off in a typical W-CDMA setup for the different

noise and spur settings.

MUXOUT

The on-chip multiplexer is controlled by Bits [DB28:DB26] (see

Figure 26).

Reference Doubler

Setting DB25 to 0 feeds the REFIN signal directly to the 10–bit

R counter, disabling the doubler. Setting this bit to 1 multiplies

the REFIN frequency by a factor of 2 before feeding into the

10-bit R counter. When the doubler is disabled, the REFIN

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of REFIN become active edges at the PFD input.

ADF4350

Rev. A | Page 19 of 32

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to

the REFIN duty cycle. The phase noise degradation can be as

much as 5 dB for the REFIN duty cycles outside a 45% to 55%

range. The phase noise is insensitive to the REFIN duty cycle

in the lowest noise mode and when the doubler is disabled.

The maximum allowable REFIN frequency when the doubler

is enabled is 30 MHz.

RDIV2

Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop

between the R counter and PFD, which extends the maximum

REFIN input rate. This function allows a 50% duty cycle signal

to appear at the PFD input, which is necessary for cycle slip

reduction.

10–Bit R Counter

The 10–bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 1023 are allowed.

Double Buffer

DB13 enables or disables double buffering of Bits [DB22:DB20]

in Register 4. The Divider Select section explains how double

buffering works.

Charge Pump Current Setting

Bits [DB12:DB09] set the charge pump current setting. This

should be set to the charge pump current that the loop filter

is designed with (see Figure 26).

LDF

Setting DB8 to 1 enables integer–N digital lock detect,

when the FRAC part of the divider is 0; setting DB8 to 0

enables fractional–N digital lock detect.

Lock Detect Precision (LDP)

When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must

occur before digital lock detect is set. When this bit is programmed

to 1, 40 consecutive reference cycles of 6 ns must occur before

digital lock detect is set. This refers to fractional-N digital lock

detect (set DB8 to 0). With integer–N digital lock detect activated

(set DB8 to 1), and DB7 set to 0, then five consecutive cycles of

6 ns need to occur before digital lock detect is set. When DB7 is

set to 1, five consecutive cycles of 10 ns must occur.

Phase Detector Polarity

DB6 sets the phase detector polarity. When a passive loop filter,

or noninverting active loop filter is used, this should be set to 1.

If an active filter with an inverting characteristic is used, it

should be set to 0.

Power-Down

DB5 provides the programmable power-down mode. Setting this

bit to 1 performs a power-down. Setting this bit to 0 returns the

synthesizer to normal operation. When in software power-down

mode, the part retains all information in its registers. Only if the

supply voltages are removed are the register contents lost.

When a power-down is activated, the following events occur:

• The synthesizer counters are forced to their load state

conditions.

• The VCO is powered down.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RFOUT buffers are disabled.

• The input register remains active and capable of loading

and latching data.

Charge Pump Three-State

DB4 puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

Counter Reset

DB3 is the R counter and N counter reset bit for the ADF4350.

When this is 1, the RF synthesizer N counter and R counter are

held in reset. For normal operation, this bit should be set to 0.

ADF4350

Rev. A | Page 20 of 32

Control Bits

With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed.

Figure 27 shows the input data format for programming this

CSR Enable

Setting DB18 to 1 enables cycle slip reduction. This is a method

for improving lock times. Note that the signal at the phase fre-

quency detector (PFD) must have a 50% duty cycle for cycle slip

reduction to work. The charge pump current setting must also

be set to a minimum. See the Cycle Slip Reduction for Faster

Lock Times section for more information.

Clock Divider Mode

Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync

or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0

disables the clock divider. See Figure 27.

12-Bit Clock Divider Value

The 12-bit clock divider value sets the timeout counter for

activation of PHASE resync. See the Phase Resync section for

more information. It also sets the timeout counter for fast lock.

See the Fast-Lock Timer and Register Sequences section for

more information.

Control Bits

With Bits [C3:C1] set to 1, 0, 0, Register 4 is programmed.

Figure 28 shows the input data format for programming this

Feedback Select

DB23 selects the feedback from the VCO output to the

N counter. When set to 1, the signal is taken from the VCO

directly. When set to 0, it is taken from the output of the output

dividers. The dividers enable covering of the wide frequency band

(137.5 MHz to 4.4 GHz). When the divider is enabled and the

feedback signal is taken from the output, the RF output signals

of two separately configured PLLs are in phase. This is useful in

some applications where the positive interference of signals is

required to increase the power.

Divider Select

Bits [DB22:DB20] select the value of the output divider (see

Figure 28).

Band Select Clock Divider Value

Bits [DB19:DB12] set a divider for the band select logic

clock input. The output of the R counter, is by default, the

value used to clock the band select logic, but, if this value is

too high (>125 kHz), a divider can be switched on to divide

the R counter output to a smaller value (see Figure 28).

VCO Power-Down

DB11 powers the VCO down or up depending on the chosen value.

Mute Till Lock Detect

If DB10 is set to 1, the supply current to the RF output stage is shut

down until the part achieves lock as measured by the digital lock

detect circuitry.

AUX Output Select

DB9 sets the auxiliary RF output. The selection can be either

the output of the RF dividers or fundamental VCO frequency.

AUX Output Enable

DB8 enables or disables auxiliary RF output, depending on the

chosen value.

AUX Output Power

Bits [DB7:DB6] set the value of the auxiliary RF output power

level (see Figure 28).

RF Output Enable

DB5 enables or disables primary RF output, depending on the

chosen value.

Output Power

Bits [DB4:DB3] set the value of the primary RF output power

level (see Figure 28).

Control Bits

With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed.

Figure 29 shows the input data form for programming this

Lock Detect Pin Operation

Bits [DB23:DB22] set the operation of the lock detect pin (see

Figure 29).

ADF4350

Rev. A | Page 21 of 32

INITIALIZATION SEQUENCE

The following sequence of registers is the correct sequence for

initial power-up of the ADF4350 after the correct application of

voltages to the supply pins:

• Register 5

• Register 4

• Register 3

• Register 2

• Register 1

• Register 0

RF SYNTHESIZER—A WORKED EXAMPLE

The following is an example how to program the ADF4350

synthesizer:

RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RF divider (3)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

MOD is the modulus.

RF divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × [(1 + D)/(R × (1+T))] (4)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

T is the reference divide-by-2 bit (0 or 1).

R is the RF reference division factor.

For example, in a UMTS system, where 2112.6 MHz RF

frequency output (RFOUT) is required, a 10 MHz reference

frequency input (REFIN) is available, and a 200 kHz channel

resolution (fRESOUT) is required on the RF output. Note that

the ADF4350 operates in the frequency range of 2.2 GHz to

4.4 GHz. Therefore, the RF divider of 2 should be used (VCO

frequency = 4225.2 MHz, RFOUT = VCO frequency/RF divider =

4225.2 MHz/2 = 2112.6 MHz).

It is also important where the loop is closed. In this example,

the loop is closed (see Figure 30).

PFD

PFD VCO

DIVIDER

÷2

7325-027

OUT

Figure 30. Loop Closed Before Output Divider

Channel resolution (fRESOUT) or 200 kHz is required at the output

of the RF divider. Therefore, channel resolution at the output of

the VCO (fRES) is to be twice the fRESOUT, that is 400 kHz.

MOD = REFIN/fRES

MOD = 10 MHz/400 kHz = 25

From Equation 4,

fPFD = [10 MHz × (1 + 0)/1] = 10 MHz (5)

2112.6 MHz = 10 MHz × (INT + FRAC/25)/2 (6)

where:

INT = 422

FRAC = 13

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (fRES) required at

the RF output. For example, a GSM system with 13 MHz REFIN

sets the modulus to 65. This means the RF output resolution (fRES)

is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,

the fractional spur interval depends on the modulus values chosen

(see Table 6 ).

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important to

note that the PFD cannot operate above 32 MHz due to a limi-

tation in the speed of the Σ-Δ circuit of the N-divider.

The reference divide-by-2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency. This is necessary

for the correct operation of the cycle slip reduction (CSR)

function. See the Cycle Slip Reduction for Faster Lock Times

section for more information.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4350 allows the

user to program the modulus over a 12–bit range. This means

the user can set up the part in many different configurations for

the application, when combined with the reference doubler and

the 10-bit R counter.

For example, consider an application that requires 1.75 GHz RF

and 200 kHz channel step resolution. The system has a 13 MHz

reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This results in

the required 200 kHz resolution.

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. This 26 MHz is then fed

into the PFD programming the modulus to divide by 130. This

also results in 200 kHz resolution and offers superior phase

noise performance over the previous setup.

ADF4350

Rev. A | Page 22 of 32

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is a

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

A 13 MHz reference signal can be fed directly to the PFD, and

the modulus can be programmed to 520 when in PDC mode

(13 MHz/520 = 25 kHz).

The modulus needs to be reprogrammed to 65 for GSM 1800

operation (13 MHz/65 = 200 kHz).

It is important that the PFD frequency remain constant (13 MHz).

This allows the user to design one loop filter for both setups

without running into stability issues. It is important to remem-

ber that the ratio of the RF frequency to the PFD frequency

principally affects the loop filter design, not the actual channel

spacing.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

As outlined in the Low Noise and Low Spur Mode section, the

ADF4350 contains a number of features that allow optimization

for noise performance. However, in fast locking applications,

the loop bandwidth generally needs to be wide, and therefore,

the filter does not provide much attenuation of the spurs. If

the cycle slip reduction feature is enabled, the narrow loop

bandwidth is maintained for spur attenuation but faster lock

times are still possible.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4350 contains a cycle slip reduction feature that extends

the linear range of the PFD, allowing faster lock times without

modifications to the loop filter circuitry.

When the circuitry detects that a cycle slip is about to occur,

it turns on an extra charge pump current cell. This outputs a

constant current to the loop filter, or removes a constant

current from the loop filter (depending on whether the VCO

tuning voltage needs to increase or decrease to acquire the new

frequency). The effect is that the linear range of the PFD is

increased. Loop stability is maintained because the current

is constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4350 turns on another charge pump cell.

This continues until the ADF4350 detects the VCO frequency

has gone past the desired frequency. The extra charge pump

cells are turned off one by one until all the extra charge pump

cells have been disabled and the frequency is settled with the

original loop filter bandwidth.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB18 in the Register 3 to 1 enables cycle slip

reduction. Note that the PFD requires a 45% to 55% duty cycle

for CSR to operate correctly. If the REFIN frequency does not

have a suitable duty cycle, the RDIV2 mode ensures that the

input to the PFD has a 50% duty cycle.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these usually have a long lock time. A wider loop bandwidth

will achieve faster lock times, but a wider loop bandwidth may

lead to increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth, but with the advantage of a narrow final loop

bandwidth to keep spurs low.

FAST-LOCK TIMER AND REGISTER SEQUENCES

If the fast-lock mode is used, a timer value is to be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits [DB16:DB15] in Register 3 are set to 0, 1 (fast-lock

enable), the timer value is loaded by the 12–bit clock divider

value. The following sequence must be programmed to use

fast lock:

1. Initialization sequence (see the Initialization Sequence

section) occurs only once after powering up the part.

2. Load Register 3 by setting Bits [DB16:DB15] to 0, 1 and

the chosen fast-lock timer value [DB14:DB3]. Note that

the duration the PLL remains in wide bandwidth is equal

to the fast-lock timer/fPFD.

FAST LOCK—AN EXAMPLE

If a PLL has reference frequencies of 13 MHz and fPFD = 13 MHz

and a required lock time of 50 μs, the PLL is set to wide bandwidth

for 40 μs. This example assumes a modulus of 65 for channel

spacing of 200 kHz. This example does not account for the time

required for VCO band select.

If the time period set for the wide bandwidth is 40 μs, then

Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD

Fast-Lock Timer Value = 40 μs × 13 MHz/65 = 8

Therefore, a value of 8 must be loaded into the clock divider

value in Register 3 in Step 1 of the sequence described in the

Fast-Lock Timer and Register Sequences section.

ADF4350

Rev. A | Page 23 of 32

FAST LOCK—LOOP FILTER TOPOLOGY

To use fast-lock mode, the damping resistor in the loop filter

is reduced to ¼ of its value while in wide bandwidth mode. To

achieve the wider loop filter bandwidth, the charge pump

current increases by a factor of 16 and to maintain loop sta-

bility the damping resistor must be reduced a factor of ¼.

To enable fast lock, the SW pin is shorted to the GND pin by

settings Bits [DB16:DB15] in Register 3 to 0, 1. The following

two topologies are available:

• The damping resistor (R1) is divided into two values (R1

and R1A) that have a ratio of 1:3 (see Figure 31).

• An extra resistor (R1A) is connected directly from SW, as

shown in Figure 32. The extra resistor is calculated such

that the parallel combination of an extra resistor and the

damping resistor (R1) is reduced to ¼ of the original value

of R1 (see Figure 32).

ADF4350

C1 C2

R1A

VCO

07325-018

Figure 31. Fast-Lock Loop Filter Topology—Topology 1

ADF4350

C1 C2

R1R1A

VCO

07325-019

Figure 32. Fast-Lock Loop Filter Topology—Topology 2

SPUR MECHANISMS

This section describes the three different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4350.

Fractional Spurs

The fractional interpolator in the ADF4350 is a third-order

Σ-Δ modulator (SDM) with a modulus (MOD) that is program-

mable to any integer value from 2 to 4095. In low spur mode

(dither enabled) the minimum allowable value of MOD is 50.

The SDM is clocked at the PFD reference rate (fPFD) that allows

PLL output frequencies to be synthesized at a channel step

resolution of fPFD/MOD.

In low noise mode (dither disabled) the quantization noise from

the Σ-Δ modulator appears as fractional spurs. The interval

between spurs is fPFD/L, where L is the repeat length of the code

sequence in the digital Σ-Δ modulator. For the third-order

modulator used in the ADF4350, the repeat length depends on

the value of MOD, as listed in Tabl e 6.

Table 6. Fractional Spurs with Dither Disabled

Condition (Dither Disabled)

Repeat

Length Spur Interval

If MOD is divisible by 2, but not 3 2 × MOD Channel step/2

If MOD is divisible by 3, but not 2 3 × MOD Channel step/3

If MOD is divisible by 6 6 × MOD Channel step/6

Otherwise MOD Channel step

In low spur mode (dither enabled), the repeat length is extend-

ed to 221 cycles, regardless of the value of MOD, which makes

the quantization error spectrum look like broadband noise.

This may degrade the in-band phase noise at the PLL output

by as much as 10 dB. For lowest noise, dither disabled is a better

choice, particularly when the final loop bandwidth is low

enough to attenuate even the lowest frequency fractional spur.

Integer Boundary Spurs

Another mechanism for fractional spur creation is the inter-

actions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related (the

point of a fractional-N synthesizer) spur sidebands appear on

the VCO output spectrum at an offset frequency that corres-

ponds to the beat note or difference frequency between an

integer multiple of the reference and the VCO frequency. These

spurs are attenuated by the loop filter and are more noticeable

on channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth, there-

fore, the name integer boundary spurs.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feed-through mechanism

that bypasses the loop may cause a problem. Feed through of

low levels of on-chip reference switching noise, through the

RFIN pin back to the VCO, can result in reference spur levels as

high as –90 dBc. PCB layout needs to ensure adequate isolation

between VCO traces and the input reference to avoid a possible

feed through path on the board.

ADF4350

Rev. A | Page 24 of 32

SPUR CONSISTENCY AND FRACTIONAL SPUR

OPTIMIZATION

When a new frequency is programmed, the second sync pulse

after the LE rising edge is used to resynchronize the output

phase to the reference. The tSYNC time is to be programmed to

a value that is as least as long as the worst-case lock time. This

guarantees the phase resync occurs after the last cycle slip in the

PLL settling transient.

With dither off, the fractional spur pattern due to the quantiza-

tion noise of the SDM also depends on the particular phase

word with which the modulator is seeded.

The phase word can be varied to optimize the fractional and

subfractional spur levels on any particular frequency. Thus, a

look-up table of phase values corresponding to each frequency

can be constructed for use when programming the ADF4350.

In the example shown in Figure 33, the PFD reference is 25 MHz

and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to

400 μs by programming CLK_DIV_VALUE = 80.

PHASE

FREQUENCY

SYNC

(INTERNAL)

–100 0 100 200 1000

300 400 500 600 700 800 900

07325-020

TIME (µs)

PLL SETTLES TO

CORRECT PHASE

AFTER RESYNC

SYNC

LAST CYCLE SLIP

PLL SETTLES TO

INCORRECT PHASE

If a look-up table is not used, keep the phase word at a constant

value to ensure consistent spur levels on any particular frequency.

PHASE RESYNC

The output of a fractional-N PLL can settle to any one of the

MOD phase offsets with respect to the input reference, where

MOD is the fractional modulus. The phase resync feature in the

ADF4350 produces a consistent output phase offset with respect

to the input reference. This is necessary in applications where the

output phase and frequency are important, such as digital beam

forming. See the Phase Programmability section to program a

specific RF output phase when using phase resync.

Phase resync is enabled by setting Bits [DB16:DB15] in

timer generates sync signals at intervals of tSYNC given by the

following formula:

Figure 33. Phase Resync Example

Phase Programmability

The phase word in Register 1 controls the RF output phase. As

this word is swept from 0 to MOD, the RF output phase sweeps

over a 360° range in steps of 360°/MOD.

tSYNC = CLK_DIV_VALUE × MOD × tPFD

where:

tPFD is the PFD reference period.

CLK_DIV_VALUE is the decimal value programmed in

Bits [DB14:DB3] of Register 3 and can be any integer in the

range of 1 to 4095.

MOD is the modulus value programmed in Bits [DB14:DB3] of

ADF4350

Rev. A | Page 25 of 32

APPLICATIONS INFORMATION

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 34 shows how Analog

Devices, Inc., parts can be used to implement such a system.

The circuit block diagram shows the AD9761 TxDAC® being

used with the ADL5375. The use of dual integrated DACs, such

as the AD9788 with its specified ±0.02 dB and ±0.001 dB gain

and offset matching characteristics, ensures minimum error

contribution (over temperature) from this portion of the

signal chain.

The local oscillator (LO) is implemented using the ADF4350.

The low-pass filter was designed using ADIsimPLL™ for a channel

spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.

The LO ports of the ADL5375 can be driven differentially from

the complementary RFOUTA and RFOUTB outputs of the ADF4350.

This gives better performance than a single-ended LO driver

and eliminates the use of a balun to convert from a single-ended

LO input to the more desirable differential LO input for the

ADL5375. At LO frequencies below 3 GHz some harmonic

filtering may be necessary to ensure best single sideband

performance.

The ADL5375 accepts LO drive levels from −6 dBm to +7 dBm.

The optimum LO power can be software programmed on the

ADF4350, which allows levels from −4 dBm to +5 dBm from

each output. For more details on this circuit, consult CN-0134.

The RF output is designed to drive a 50 Ω load, but must be

ac-coupled, as shown in Figure 34. If the I and Q inputs are

driven in quadrature by 2 V p-p signals, the resulting output

power from the modulator is approximately 2 dBm.

07325-021

2700pF 1200pF

39nF

680Ω

360Ω

SPI-COMPATIBLE SERIAL BUS

ADF4350

VCO

GND

AGND DGND

OUT

B–

OUT

B+

OUT

1nF1nF

4.7kΩ

SET

DATA

CLK

REF

FREF

TUNE

CE MUXOUT

831 911 18 21 27

LOCK

DETECT

51Ω

GNDVCO

COM

19 23 24

PDB

GND

TEMP V

REF

632

SDV

10pF 0.1µF 10pF 0.1µF 10pF 0.1µF

AD9761

TxDAC

REFIO

FSADJ

MODULATED

DIGITAL

DATA

QOUTB

IOUTA

IOUTB

QOUTA

2kΩ

LOW-PASS

FILTER

LOW-PASS

FILTER

IBBP

IBBN

QBBP

QBBN

LOIP

LOIN

51Ω51Ω

ADL537 5

RFO

QUADRATURE

PHASE

SPLITTER

DSOP

OUT

A–

OUT

A+

VCO

3.9nH 3.9nH

1nF

LPF

Figure 34. Direct Conversion Modulator

ADF4350

Rev. A | Page 26 of 32

INTERFACING

The ADF4350 has a simple SPI-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When LE goes high, the 32 bits that have been clocked

into the appropriate register on each rising edge of CLK are

transferred to the appropriate latch. See Figure 2 for the timing

diagram and Table 5 for the register address table.

ADuC70xx Interface

Figure 35 shows the interface between the ADF4350 and the

ADuC70xx family of analog microcontrollers. The ADuC70xx

family is based on an AMR7 core, although the same interface

can be used with any 8051-based microcontroller. The micro-

controller is set up for SPI master mode with CPHA = 0. To

initiate the operation, the I/O port driving LE is brought low.

Each latch of the ADF4350 needs a 32-bit word. This is accom-

plished by writing four 8-bit bytes from the microcontroller to

the device. When the last byte is written, the LE input should be

brought high to complete the transfer.

On first applying power to the ADF4350, it needs six writes

(one each to R5, R4, R3, R2, R1, R0) for the output to become

active.

I/O port lines on the microcontroller are also used to control

power-down (CE input) and to detect lock (MUXOUT

configured as lock detect and polled by the port input).

When operating in the mode described, the maximum SPI

transfer rate of the ADuC7023 is 20 Mbps. This means that

the maximum rate at which the output frequency can be

changed is 833 kHz. If using a faster SPI clock just make sure

the SPI timing requirements listed in Table 2 are adhered to.

07325-022

ADuC70xx

ADF4350

CLK

DATA

MUXOUT

(LOCK DET E CT)

SCLOCK

MOSI

I/O PORTS

Figure 35. ADuC812 to ADF4350 Interface

ADSP-BF527 Interface

Figure 36 shows the interface between the ADF4351 and the

Blackfin® ADSP-BF527 digital signal processor (DSP). The

ADF4351 needs a 32-bit serial word for each latch write. The

easiest way to accomplish this using the Blackfin family is to use

the autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for 8 bits and use three memory locations for each 32-bit

word. To program each 32-bit latch, store the four 8-bit bytes,

enable the autobuffered mode, and write to the transmit register

of the DSP. This last operation initiates the autobuffer transfer.

Make sure the clock speeds are within the maximum limits

outlined in Table 2.

07325-023

ADSP-BF527

ADF4350

CLK

DATA

MUXOUT

(LOCK DET ECT)

SCK

MOSI

GPIO

I/O FLAGS

Figure 36. ADSP-BF527 to ADF4350 Interface

PCB DESIGN GUIDELINES FOR A CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-32-2) are rectangular.

The PCB pad for these is to be 0.1 mm longer than the package

land length and 0.05 mm wider than the package land width.

The land is to be centered on the pad. This ensures the solder

joint size is maximized. The bottom of the chip scale package

has a central thermal pad.

The thermal pad on the PCB is to be at least as large as the

exposed pad. On the PCB, there is to be a minimum clearance

of 0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

Thermal vias can be used on the PCB thermal pad to improve

the thermal performance of the package. If vias are used, they

are to be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter is to be between 0.3 mm and 0.33 mm, and the

via barrel is to be plated with 1 oz. of copper to plug the via.

ADF4350

Rev. A | Page 27 of 32

Table 7. Matching Components

OUTPUT MATCHING

Frequency Range (MHz) L (nH) C (nF)

137.5 to 500 100 1

500 to 1000 47 1

1000 to 2000 7.5 1

2000 to 4400 3.9 1

There are a number of ways to match the output of the ADF4350

for optimum operation; the most basic is to use a 50 Ω resistor to

VVCO. A dc bypass capacitor of 100 pF is connected in series as

shown in Figure 37. Because the resistor is not frequency

dependent, this provides a good broadband match. Placing

the output power in this circuit into a 50 Ω load typically

gives values chosen by Bit D2 and Bit D1 in Register 4 (R4).

If differential outputs are not required, the unused output can

be terminated or both outputs can be combined using a balun.

Unused terminated outputs should have the same shunt and

series components and a load resistor to GND. If the auxiliary

output is unused (disabled in software), then the RFOUTB± pins

can be left open circuit.

100pF

07325-021

RFOUT

VVCO

50Ω

OUT

A+

OUT

A–

VCO

07325-132

Figure 37. Simple ADF4350 Output Stage

A better solution is to use a shunt inductor (acting as an RF

choke) to VVCO. This gives a better match and, therefore, more

output power.

Experiments have shown the circuit shown in Figure 38

provides an excellent match to 50 Ω for the W-CDMA UMTS

Band 1 (2110 MHz to 2170 MHz). The maximum output power

in that case is about 5 dBm. Both single-ended architectures can

be examined using the EVAL-ADF4350EB1Z evaluation board.

Tabl e 7 provides a suggested range of values for the capacitor

and choke inductor for different frequency ranges.

Figure 39. ADF4350 LC Balun

A balun using discrete inductors and capacitors may be

implemented with the architecture in Figure 39.

Component L1 and Component C1 comprise the LC balun, L2

provides a dc path for RFOUTA−, and Capacitor C2 is used for dc

blocking. better solution is to use a shunt inductor (acting as an

RF choke) to VVCO. This gives a better match and, therefore,

more output power.

07325-025

OUT

VCO

50Ω

Experiments have shown the circuit shown in Figure 38

provides an excellent match to 50 Ω for the W-CDMA UMTS

Band 1 (2110 MHz to 2170 MHz). The maximum output power

in that case is about 5 dBm. Both single-ended architectures can

be examined using the EVAL-ADF4350EB1Z evaluation board.

Figure 38.Optimum ADF4350 Output Stage

S11 parameters are provided in Table 9.

Table 8. LC Balun Components

Frequency

Range (MHz) Inductor L1 (nH) Capacitor C1 (pF)

RF Choke

Inductor (nH)

DC Blocking

Capacitor (pF)

Measured Output

Power (dBm)

137 to 300 100 10 390 1000 9

300 to 460 51 5.6 180 120 10

400 to 600 30 5.6 120 120 10

600 to 900 18 4 68 120 10

860 to 1240 12 2.2 39 10 9

1200 to 1600 5.6 1.2 15 10 9

1600 to 3600 3.3 0.7 10 10 8

2800 to 3800 2.2 0.5 10 10 8

ADF4350

Rev. A | Page 28 of 32

Table 9. RFOUTA+ S-Parameters (S11)

# GHz S MA R 50

FREQ MAG ANG

0.10 0.96 −3.65

0.15 0.94 −4.41

0.20 0.93 −4.52

0.25 0.92 −4.41

0.30 0.92 −4.82

0.35 0.92 −5.25

0.40 0.91 −5.74

0.45 0.91 −6.3

0.50 0.91 −7.32

0.55 0.9 −8.22

0.60 0.9 −9.4

0.65 0.89 −10.61

0.70 0.89 −10.96

0.75 0.89 −11.68

0.80 0.89 −12.3

0.85 0.89 −12.84

0.90 0.88 −13.55

0.95 0.88 −14.13

1.00 0.87 −14.84

1.05 0.86 −15.76

1.10 0.86 −16.63

1.15 0.86 −17.51

1.20 0.85 −18.43

1.25 0.85 −19.38

1.30 0.85 −20.4

1.35 0.84 −21.61

1.40 0.83 −22.63

1.45 0.82 −22.92

1.50 0.81 −23.82

1.55 0.81 −24.82

1.60 0.8 −25.58

1.65 0.8 −26.71

1.70 0.79 −28.05

1.75 0.78 −29.63

1.80 0.75 −30.12

1.85 0.74 −29.82

1.90 0.74 −30.3

1.95 0.74 −31.36

2.00 0.74 −32.63

2.05 0.73 −33.78

2.10 0.72 −35.08

2.15 0.71 −36.83

2.20 0.69 −37.98

2.25 0.67 −38.42

# GHz S MA R 50

FREQ MAG ANG

2.30 0.65 −38.78

2.35 0.64 −39.43

2.40 0.63 −40.44

2.45 0.62 −41.55

2.50 0.61 −42.55

2.55 0.6 −43.8

2.60 0.59 −44.97

2.65 0.58 −45.93

2.70 0.57 −46.5

2.75 0.57 −47.11

2.80 0.55 −47.7

2.85 0.54 −48.54

2.90 0.52 −49.63

2.95 0.51 −50.71

3.00 0.49 −51.89

3.05 0.48 −53.42

3.10 0.47 −54.56

3.15 0.46 −55.71

3.20 0.45 −56.38

3.25 0.44 −56.99

3.30 0.43 −57.9

3.35 0.42 −58.92

3.40 0.41 −60.17

3.45 0.4 −61.49

3.50 0.38 −63.02

3.55 0.37 −64.37

3.60 0.36 −65.52

3.65 0.35 −66.53

3.70 0.34 −67.53

3.75 0.33 −69.16

3.80 0.32 −70.75

3.85 0.31 −72.04

3.90 0.3 −73.73

3.95 0.28 −75.85

4.00 0.27 −78.25

4.05 0.26 −81.03

4.10 0.26 −83.45

4.15 0.25 −85.67

4.20 0.25 −87.63

4.25 0.24 −89.61

4.30 0.23 −91.6

4.35 0.22 −93.91

4.40 0.21 −97.18

ADF4350

Rev. A | Page 29 of 32

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

011708-A

0.30

0.23

0.18

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

12° MAX

1.00

0.85

0.80 SEATING

PLANE

COPLANARITY

0.08

0.50

0.40

0.30

3.50 REF

0.50

BSC

PIN 1

INDICATOR

TOP

VIEW

5.00

BSC SQ

4.75

BSC SQ

3.25

3.10 SQ

2.95

PIN 1

INDICATOR

0.60 MAX

0.25 MIN

EXPOSED

PAD

(BOTTOM VIEW)

FORPROPERCONNECTIONOF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADF4350BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

ADF4350BCPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

ADF4350BCPZ-RL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

EVAL-ADF4350EB1Z Evaluation Board, Primary RF Output Available

EVAL-ADF4350EB2Z Evaluation Board, Primary and Auxiliary RF Outputs Available

1 Z = RoHS Compliant Part.

ADF4350

Rev. A | Page 30 of 32

NOTES

ADF4350

Rev. A | Page 31 of 32

NOTES

ADF4350

Rev. A | Page 32 of 32

NOTES

registered trademarks are the property of their respective owners.

D07325-0-4/11(A)