LT1241 Series
1
Rev B
For more information www.analog.com
BLOCK DIAGRAM
FEATURES DESCRIPTION
High Speed Current Mode
Pulse Width Modulators
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
The LT
®
1241 series devices are 8-pin, fixed frequency,
current mode, pulse width modulators. They are improved
plug compatible versions of the industry standard UC1842
series. These devices have both improved speed and
lower quiescent current. The LT1241 series is optimized
for off-line and DC/DC converter applications. They con-
tain a temperature-compensated reference, high gain
error amplifier, current sensing comparator and a high
current totem pole output stage ideally suited to driv-
ing power MOSFETs. Start-up current has been reduced
to less than 250µA. Cross-conduction current spikes in
the output stage have been eliminated, making 500kHz
operation practical. Several new features have been incor-
porated. Leading edge blanking has been added to the
current sense comparator. Trims have been added to the
oscillator circuit for both frequency and sink current, and
both of these parameters are tightly specified. The out-
put stage is clamped to a maximum VOUT of 18V in the
on state. The output and the reference output are actively
pulled low during undervoltage lockout.
n Low Start-Up Current: < 250µA
n 50ns Current Sense Delay
n Current Mode Operation: To 500kHz
n Pin Compatible with UC1842 Series
n Undervoltage Lockout with Hysteresis
n No Cross-Conduction Current
n Trimmed Bandgap Reference
n 1A Totem Pole Output
n Trimmed Oscillator Frequency and Sink Current
n Active Pull-Down on Reference and Output During
Undervoltage Lockout
n High Level Output Clamp: 18V
n Current Sense Leading Edge Blanking
n Off-Line Converters
n DC/DC Converters
+
–
+
–
1
2
FB
COMP
2.5V
2R
R
1V
1.5V
–
+
3
I
SENSE
BLANKING
1mA
5.6V
4
RT/CTOSCILLATOR
R
S
18V
7 VCC
5 GND
6 OUTPUT
8VREF
5V REF
MAIN BIAS
REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
1241 BD01
T
UV
LOCKOUT
Document Feedback
LT1241 Series
2
Rev B
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
1
2
3
4
8
7
6
5
TOP VIEW
J8 PACKAGE 8-LEAD CERDIP
VREF
VCC
OUTPUT
GND
COMP
FB
I
SENSE
RT/CT
TJMAX = 125°C, θJA = 100°C/W
OBSOLETE PACKAGE
1
2
3
4
8
7
6
5
TOP VIEW
N8 PACKAGE 8-LEAD PDIP
VREF
VCC
OUTPUT
GND
COMP
FB
I
SENSE
RT/CT
TJMAX = 100°C, θJA = 130°C/W
1
2
3
4
8
7
6
5
TOP VIEW
VREF
VCC
OUTPUT
GND
COMP
FB
I
SENSE
RT/CT
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 100°C, θJA = 150°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
OBSOLETE PACKAGE
LT124XCJ8#PBF LT124XCJ8#TRPBF 124X 8-Lead CERDIP 0°C to 100°C
LT124XCN8#PBF LT124XCN8#TRPBF 124X 8-Lead PDIP 0°C to 100°C
LT124XCS8#PBF LT124XCS8#TRPBF 124X 8-Lead Plastic SO 0°C to 100°C
LT124XIN8#PBF LT124XIN8#TRPBF 124XI 8-Lead PDIP –40°C to 125°C
LT124XIS8#PBF LT124XIS8#TRPBF 124XI 8-Lead Plastic SO –40°C to 125°C
OBSOLETE PACKAGE
LT124XMJ8#PBF LT124XMJ8#TRPBF 8-Lead CERDIP –55°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LT1241#orderinfo
Supply Voltage ..........................................................25V
Output Current ........................................................±1A*
Output Energy (Capacitive Load per Cycle) ............... 5µJ
Analog Inputs (Pins 2, 3) ............................... –0.3 to 6V
Error Amplifier Output Sink Current .......................10mA
Power Dissipation at TA ≤ 25°C ..................................1W
Operating Junction Temperature Range
LT124XC ................................................. 0°C to 100°C
LT124XI ............................................ – 40°C to 100°C
LT124XM (Obsolete) .......................... –55°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
*The 1A rating for output current is based on transient switching
requirements.
LT1241 Series
3
Rev B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Section
Output Voltage IO = 1mA, TJ = 25°C 4.925 5.000 5.075 V
Line Regulation 12V < VCC < 25V l3 20 mV
Load Regulation 1mA < IVREF < 20mA l–6 –25 mV
Temperature Stability 0.1 mV/°C
Total Output Variation Line, Load, Temp l4.87 5.13 V
Output Noise Voltage 10Hz < F < 10kHz, TJ = 25°C 50 µV
Long Term Stability TA = 125°C, 1000 Hrs 5 25 mV
Output Short-Circuit Current l–30 –90 –180 mA
Oscillator Section
Initial Accuracy RT = 10k, CT = 3.3nF, TJ = 25°C 47.5 50 52.5 kHz
RT = 13.0k, CT = 500pF, TJ = 25°C 228 248 268 kHz
Voltage Stability 12V < VCC < 25V, TJ = 25°C 1 %
Temperature Stability TMIN < TJ < TMAX – 0.05 %/°C
Amplitude TJ = 25°C (Pin 4) 1.7 V
Clock Ramp Reset Current VOSC (Pin 4) = 2V, TJ = 25°C 7.9 8.2 8.5 mA
Error Amplifier Section
Feedback Pin Input Voltage VPIN1 = 2.5V l2.42 2.50 2.58 V
Input Bias Current VFB = 2.5V l–2 µA
Open-Loop Voltage Gain 2 < VO < 4V l65 90 dB
Unity-Gain Bandwidth TJ = 25°C 0.7 1.3 2 MHz
Power Supply Rejection Ratio 12V < VCC < 25V l60 dB
Output Sink Current VPIN2 = 2.7V, VPIN1 = 1.1V l2 6 mA
Output Source Current VPIN2 = 2.3V, VPIN1 = 5V l–0.5 –0.75 mA
Error Amplifier Section
Output Voltage High Level VPIN2 = 2.3V, RL = 15k to GND l5 5.6 V
Output Voltage Low Level VPIN2 = 2.7V, RL = 15k to Pin 8 l0.2 1.1 V
Current Sense Section
Gain l2.85 3.00 3.15 V/V
Maximum Current Sense Input Threshold VPIN3 < 1.1V l0.90 1.00 1.10 V
Power Supply Rejection Ratio l70 dB
Input Bias Current l–1 10 µA
Delay to Output l50 100 ns
Blanking Time 100 ns
Blanking Override Voltage 1.5 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2 and 3)
LT1241 Series
4
Rev B
For more information www.analog.com
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Section
Output Low Level IOUT = 20mA
IOUT = 200mA
l
l
0.25
0.75
0.4
2.2
V
V
Output High Level IOUT = 20mA
IOUT = 200mA
l
l
12.0
11.75
V
V
Rise Time CL = 1nF, TJ = 25°C 50 80 ns
Fall Time CL = 1.0nF, TJ = 25°C 30 60 ns
Output Clamp Voltage IO = 1mA l18 19.5 V
Undervoltage Lockout
Start-Up Threshold
LT1241
LT1242/LT1244
LT1243/LT1245
l
l
l
9.0
15
7.8
9.6
16
8.4
10.2
17
9.0
V
V
V
Minimum Operating Voltage
LT1241/LT1243/LT1245
LT1242/LT1244
l
l
7.0
9.0
7.6
10
8.2
11
V
V
Hysteresis
LT1241
LT1242/LT1244
LT1243/LT1245
1.6
5.5
0.4
2.0
6.0
0.8
V
V
V
PWM
Maximum Duty Cycle
LT1241/LT1244/LT1245
LT1242/LT1243
TJ = 25°C
TJ = 25°C
46
94
48
96
%
%
Minimum Duty Cycle l0 %
Total Device
Start-Up Current l170 250 µA
Operating Current l7 10 mA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2 and 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Unless otherwise specified, VCC = 15V, RT = 10k, CT = 3.3nF.
Note 3: Low duty cycle pulse techniques are used during test to maintain
junction temperature close to ambient.
LT1241 Series
5
Rev B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout – LT1241
Undervoltage Lockout – LT1242,
LT1244
Undervoltage Lockout – LT1243,
LT1245
Start-Up Current Start-Up Current Supply Current
Supply Current vs Oscillator
Frequency Oscillator Frequency Oscillator Sink Current
TEMPERATURE (°C)
–50
6
V
CC
(V)
7
8
9
10
11
–25 25 75 125
LT1241 • TPC01
0 50 100
MINIMUM OPERATING VOLTAGE
START-UP THRESHOLD
TEMPERATURE (°C)
–50
9
VCC (V)
10
11
16
17
–25 25 75 125
LT1241 • TPC02
0 50 100
MINIMUM OPERATING VOLTAGE
START-UP THRESHOLD
15
TEMPERATURE (°C)
–50
6
V
CC
(V)
7
8
9
10
11
–25 25 75 125
LT1241 • TPC03
0 50 100
MINIMUM OPERATING VOLTAGE
START-UP THRESHOLD
VCC (V)
0
0
START-UP CURRENT (µA)
50
100
150
200
2 8 12
18
LT1241 • TPC04
4 10 146 16
LT1241 LT1242/4
LT1243/5
TJ = 25°C
START-UP
THRESHOLD
TEMPERATURE (°C)
–50
0
START-UP CURRENT (µA)
40
80
120
160
200
–25 25 75
125
LT1241 • TPC05
0 50 100
180
140
100
60
20
TEMPERATURE (°C)
–50
5
I
CC
(mA)
6
7
8
9
10
–25 25 75 125
LT1241 • TPC06
0 50 100
VCC = 15V
RT = 10k
CT = 3300pF
OSCILLATOR FREQUENCY (Hz)
10k
0
SUPPLY CURRENT (mA)
2
3
5
7
8
10
100k
1M
LT1241 • TPC18
9
6
4
1
LT1242, LT1243
LT1241, LT1244, LT1245
VCC = 15V
RT = 10k
CL = 15pF
TEMPERATURE (°C)
–50
40
FREQUENCY (kHz)
44
48
52
56
60
–25 25 75 125
LT1241 • TPC07
0 50 100
42
46
50
54
58 VCC = 5V
RT = 10k
CT = 3300pF
TEMPERATURE (°C)
–50
7.7
OSCILLATOR SINK CURRENT (mA)
8.7
–25 25 75 125
LT1241 • TPC08
0 50 100
7.8
8.0
8.2
8.4
8.6
8.5
7.9
8.1
8.3
VPIN4 = 2V
LT1241 Series
6
Rev B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage Reference Short-Circuit Current Feedback Pin Input Voltage
Error Amplifier Open-Loop Gain
and Phase Current Sense Clamp Voltage Current Sense Input Threshold
High Level Output Saturation
Voltage
Low Level Output Saturation
Voltage
Low Level Output Saturation
Voltage During Undervoltage
Lockout
TEMPERATURE (°C)
–50
4.95
REFERENCE VOLTAGE (V)
5.05
–25 25 75 125
LT1241 • TPC10
0 50 100
4.96
5.00
5.01
4.97
4.98
4.99
5.02
5.03
5.04 IO = 1mA
TEMPERATURE (°C)
–50
20
REFERENCE SHORT-CIRCUIT CURRENT (mA)
140
–25 25 75
125
LT1241 • TPC09
0 50 100
40
80
100
120
60
TEMPERATURE (°C)
–50
2.45
FEEDBACK PIN INPUT VOLTAGE (V)
2.55
–25 25 75
125
LT1241 • TPC11
0 50 100
2.46
2.50
2.51
2.47
2.48
2.49
2.52
2.53
2.54
FREQUENCY (Hz)
10
–20
VOL
10k 10M
40
0
20
60
80
100 1k 100k 1M
PHASE
GAIN
VCC = 15V
VO = 2.0V TO 4.0V
RL = 100k
TA = 25°C
180
–45
90
0
45
135
TEMPERATURE (°C)
–50
0.95
CURRENT SENSE CLAMP VOLTAGE (V)
1.05
–25 25 75
125
LT1241 • TPC12
0 50 100
0.96
1.00
1.01
0.97
0.98
0.99
1.02
1.03
1.04
ERROR AMP OUTPUT VOLTAGE (V)
0
0
CURRENT SENSE INPUT THRESHOLD (V)
1.2
3 6
LT1241 • TPC17
0.6
0.2
0.4
0.8
1.0
1 2 4 5
TJ = –55°C
TJ =125°C
TJ = 25°C
OUTPUT SOURCE CURRENT (mA)
0
0
OUTPUT SATURATION VOLTAGE (V)
4.0
200
LT1241 • TPC13
0.5
2.0
2.5
1.0
1.5
3.0
3.5
TJ = –55°C
TJ = 25°C
TJ = 125°C
100
OUTPUT SINK CURRENT (mA)
0
0
OUTPUT SATURATION VOLTAGE (V)
1.0
100 200
LT1241 • TPC14
TJ = –55°C
TJ = 25°C
TJ = 125°C
0.5
OUTPUT SINK CURRENT (mA)
0
0
OUTPUT SATURATION VOLTAGE (V)
4.0
5
10
LT1241 • TPC15
2.0
0.5
1.0
1.5
2.5
3.0
3.5
TJ = 125°C
TJ = –55°C
TJ = 25°C
LT1241 Series
7
Rev B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Output Deadtime vs Oscillator
Frequency – LT1242, LT1244
Output Deadtime vs Oscillator
Frequency – LT1241, LT1243,
LT1245
Timing Resistor vs Oscillator
Frequency
Output Rise and Fall Time
Output Cross-Conduction
Current Current Sense Delay
OSCILLATOR FREQUENCY (kHz)
0
0
% OF DEADTIME
10
20
30
40
50
60
100
1000
LT1241 • TPC19
5nF 2nF 1nF
100pF
500pF
OSCILLATOR FREQUENCY (kHz)
0
50
% OF DEADTIME
55
60
65
70
75
100
1000
LT1241 • TPC20
5nF 2nF
500pF
100pF
10nF 1nF
OSCILLATOR FREQUENCY (Hz)
10k
1
R
T
(kΩ)
10
100
100k 1M
LT1241 • TPC21
5nF
2nF
500pF
100pF
CT =10nF
1nF
200pF
VCC = 15V
TJ = 25°C
VCC = 15V
C
L
= 1nF
OUTPUT VOLTAGE
TIME 50ns/DIV
LT1241 • TPC22
VCC = 15V
C
L
= 1nF
OUTPUT
VOLTAGE
5V/DIV
OUTPUT CROSS-
CONDUCTION CURRENT
20mA/DIV
TIME 50ns/DIV
LT1241 • TPC23
VCC = 15V
C
L
= 1nF
OUTPUT
VOLTAGE
5V/DIV
CURRENT
SENSE INPUT
1V/DIV
TIME 50ns/DIV
LT1241 • TPC24
LT1241 Series
8
Rev B
For more information www.analog.com
PIN FUNCTIONS
COMP (Pin 1): Compensation Pin. This pin is the output of
the Error Amplifier and is made available for loop compen-
sation. It can also be used to adjust the maximum value of
the current sense clamp voltage to less than 1V. This pin
can source a minimum of 0.5mA (0.8mA typ) and sink a
minimum of 2mA (4mA typ)
FB (Pin 2): Voltage Feedback Pin. This pin is the inverting
input of the error amplifier. The output voltage is normally
fed back to this pin through a resistive divider. The non-
inverting input of the error amplifier is internally commit-
ted to a 2.5V reference point.
ISENSE (Pin 3): Current Sense Pin. This is the input to the
current sense comparator. The trip point of the compara-
tor is set by, and is proportional to, the output voltage of
the Error Amplifier
.
RT/CT (Pin 4): The oscillator frequency and the deadtime
are set by connecting a resistor (RT) from VREF to RT/CT
and a capacitor (CT) from RT/CT to GND.
The rise time of the oscillator waveform is set by the RC
time constant of RT and CT. The fall time, which is equal
to the output deadtime, is set by a combination of the RC
time constant and the oscillator sink current (8.2mA typ).
GND (Pin 5): Ground.
OUTPUT (Pin 6): This pin is the output of a high current
totem pole output stage. It is capable of driving up to
±1A of current into a capacitive load such as the gate of
a MOSFET.
VCC (Pin 7): This pin is the positive supply of the control
IC.
VREF (Pin 8): Reference. This is the reference output of
the IC. The reference output is used to supply charging
current to the external timing resistor RT. The reference
provides biasing to a large portion of the internal circuitry,
and is used to generate several internal reference lev-
els including the VFB level and the current sense clamp
voltage.
APPLICATIONS INFORMATION
LT1241 Series
9
Rev B
For more information www.analog.com
START-UP
DEVICE
MINIMUM
OPERATING
THRESHOLD
MAXIMUM
VOLTAGE
DUTY
CYCLE REPLACES
LT1241 9.6V 7.6V 50% NONE
LT1242 16V 10V 100% UC1842
LT1243 8.4V 7.6V 100% UC1843
LT1244 16V 10V 50% UC1844
LT1245 8.4V 7.6V 50% UC1845
Oscillator
The LT1241 series devices are fixed frequency current
mode pulse width modulators. The oscillator frequency
and the oscillator discharge current are both trimmed and
tightly specified to minimize the variations in frequency
and deadtime. The oscillator frequency is set by choosing
a resistor and capacitor combination, RT and CT. This RC
combination will determine both the frequency and the
maximum duty cycle. The resistor RT is connected from
VREF (Pin 8) to the RT/CT pin (Pin 4). The capacitor CT
is connected from the RT/CT pin to ground. The charg-
ing current for CT is determined by the value of RT. The
discharge current for CT is set by the difference between
the current supplied by RT and the discharge current
of the LT124X. The discharge current of the device is
trimmed to 8.2mA. For large values of RT discharge time
will be determined by the discharge current of the device
and the value of CT. As the value of RT is reduced it will
have more effect on the discharge time of CT. During an
oscillator cycle capacitor CT is charged to approximately
2.8V and discharged to approximately 1.1V. The output is
enabled during the charge time of CT and disabled, in an
off state, during the discharge time of CT. The deadtime
of the circuit is equal to the discharge time of C
T
. The
maximum duty cycle is limited by controlling the deadtime
of the oscillator. There are many combinations of RT and
CT that will yield a given oscillator frequency, however
there is only one combination that will yield a specific
deadtime at that frequency. Curves of oscillator frequency
and deadtime for various values of RT and CT appear in the
Typical Performance Characteristics section. Frequency
and deadtime can also be calculated using the following
formulas:
Oscillator Rise Time: tr = 0.583 • RC
Oscillator Discharge Time:
td=3.46 •RC
(0.0164)R –11.73
Oscillator Period: TOSC = tr + td
Oscillator Frequency:
fOSC =1
T
OSC
Maximum Duty Cycle:
LT1241, LT1244, LT1245
DMAX =tr
2T
OSC
=TOSC – td
2T
OSC
LT1242, LT1243
DMAX =tr
T
OSC
=TOSC – td
T
OSC
The above formulas will give values that will be accu-
rate to approximately ±5%, at the oscillator, over the full
operating frequency range. This is due to the fact that
the oscillator trip levels are constant versus frequency
and the discharge current and initial oscillator frequency
are trimmed. Some fine adjustment may be required to
achieve more accurate results. Once the final RT/CT com-
bination is selected the oscillator characteristics will be
repeatable from device to device. Note that there will be
some slight differences between maximum duty cycle at
the oscillator and maximum duty cycle at the output due
to the finite rise and fall times of the output.
The output switching frequency will be equal to the
oscillator frequency for LT1242 and LT1243. The output
switching frequency will be equal to one-half the oscillator
frequency for LT1241, LT1244 and LT1245. The oscilla-
tor of LT1241 series devices will run at frequencies up to
1MHz, allowing 500kHz output switching frequencies for
all devices.
APPLICATIONS INFORMATION
LT1241 Series
10
Rev B
For more information www.analog.com
Error Amplifier
The LT1241 series of devices contain a fully compensated
error amplifier with a DC gain of 90dB and a unity-gain
frequency of 1MHz. Phase margin at unity-gain is 80°.
The noninverting input is internally committed to a 2.5V
reference point derived from the 5V reference of Pin 8.
The inverting input (Pin 2) and the output (Pin 1) are made
available to the user. The output voltage in a regulator
circuit is normally fed back to the inverting input of the
error amplifier through a resistive divider.
The output of the error amplifier is made available for
external loop compensation. The output current of the
error amplifier is limited to approximately 0.8mA sourc-
ing and approximately 6mA sinking. In a current mode
PWM the peak switch current is a function of the output
voltage of the error amplifier. In the LT1241 series devices
the output of the error amplifier is offset by two diodes
(1.4V at 25°C), divided by a factor of three, and fed to
the inverting input of the current sense comparator. For
error amplifier output voltages less than 1.4V the duty
cycle of the output stage will be zero. The maximum offset
that can appear at the current sense input is limited by
a 1V clamp. This occurs when the error amplifier output
reaches 4.4V at 25°C.
The output of the error amplifier can be clamped below
4.4V in order to reduce the maximum voltage allowed
across the current sensing resistor to less than 1V. The
supply current will increase by the value of the output
source current when the output voltage of the error ampli-
fier is clamped.
Current Sense Comparator and PWM Latch
LT1241 series devices are current mode controllers.
Under normal operating conditions the output (Pin 6) is
turned on at the start of every oscillator cycle, coincident
with the rising edge of the oscillator waveform. The output
is then turned off when the current reaches a threshold
level proportional to the error voltage at the output of the
error amplifier. Once the output is turned off it is latched
off until the start of the next cycle. The peak current is
thus proportional to the error voltage and is controlled on
a cycle by cycle basis. The peak switch current is normally
sensed by placing a sense resistor in the source lead of
the output MOSFET. This resistor converts the switch cur-
rent to a voltage that can be fed into the current sense
input. For normal operating conditions the peak inductor
current, which is equal to the peak switch current, will
be equal to:
IPK =
(V
PIN1
–1.4V)
3RS
( )
During fault conditions the maximum threshold voltage at
the input of the current sense comparator is limited by the
internal 1V clamp at the inverting input. The peak switch
current will be equal to:
IPK(MAX) =1V
R
S
In certain applications, such as high power regulators, it
may be desirable to limit the maximum threshold voltage
to less than 1V in order to limit the power dissipated in
the sense resistor or to limit the short-circuit current of
the regulator circuit. This can be accomplished by clamp-
ing the output of the error amplifier. A voltage level of
approximately 1.4V at the output of the error amplifier will
give a threshold voltage of 0V. A voltage level of approxi-
mately 4.4V at the output of the error amplifier will give
a threshold level of 1V. Between 1.4V and 4.4V the thresh-
old voltage will change by a factor of one-third of the
change in the error amplifier output voltage. The threshold
voltage will be 0.333V for an error amplifier voltage of
2.4V. To reduce the maximum current sense threshold to
less than 1V the error amplifier output should be clamped
to less than 4.4V.
APPLICATIONS INFORMATION
LT1241 Series
11
Rev B
For more information www.analog.com
Blanking
A unique feature of the LT1241 series devices is the
built-in blanking circuit at the output of the current sense
comparator. A common problem with current mode
PWM circuits is erratic operation due to noise at the cur-
rent sense input. The primary cause of noise problems
is the leading edge current spike due to transformer
interwinding capacitance and diode reverse recovery
time. This current spike can prematurely trip the current
sense comparator causing an instability in the regula-
tor circuit. A filter at the current sense input is normally
required to eliminate this instability.
This filter will in turn slow down the current sense loop.
A slow current sense loop will increase the minimum
pulse width which will increase the short-circuit current
in an overload condition. The LT1241 series devices blank
(lock out) the signal at the output of the current sense
comparator for a fixed amount of time after the switch is
turned on. This effectively prevents the PWM latch from
tripping due to the leading edge current spike.
The blanking time will be a function of the voltage at the
feedback pin (Pin 2). The blanking time will be 100ns
for normal operating conditions (VFB = 2.5V). The blank-
ing time goes to zero as the feedback pin is pulled to
0V. This means that the blanking time will be minimized
during start-up and also during an output short-circuit
fault. This blanking circuit eliminates the need for an
input filter at the current sense input except in extreme
cases. Eliminating the filter allows the current sense loop
to operate with minimum delays, reducing peak currents
during fault conditions.
Undervoltage Lockout
The LT1241 series devices incorporate an undervoltage
lockout comparator which prevents the internal reference
circuitry and the output from starting up until the supply
voltage reaches the start-up threshold voltage. The qui-
escent current, below the start-up threshold, has been
reduced to less than 250µA (170µA typ.) to minimize the
power loss due to the bleed resistor used for start-up
in off-line converters. In undervoltage lockout both VREF
(Pin 8) and the output (Pin 6) are actively pulled low by
Darlington connected PNP transistors. They are designed
to sink a few milliamps of current and will pull down to
about 1V. The pull-down transistor at the reference pin
can be used to reset the external soft start capacitor. The
pull-down transistor at the output eliminates the exter-
nal pull-down resistor required, with earlier devices, to
hold the external MOSFET gate low during undervoltage
lockout.
Output
The LT1241 series devices incorporate a single high
current totem pole output stage. This output stage is
capable of driving up to ±1A of output current. Cross-
conduction current spikes in the output totem pole have
been eliminated. This device is primarily intended for driv-
ing MOSFET switches. Rise time is typically 40ns and fall
time is typically 30ns when driving a 1.0nF load. A clamp
is built into the device to prevent the output from rising
above 18V in order to protect the gate of the MOSFET
switch.
The output is actively pulled low during undervoltage
lockout by a Darlington PNP. This PNP is designed to sink
several milliamps and will pull the output down to approxi-
mately 1V. This active pull-down eliminates the need for an
external resistor which was required in older designs. The
output pin of the device connects directly to the emitter
of the upper NPN drive transistor and the collector of the
lower NPN drive transistor in the totem pole. The collector
of the lower transistor, which is n-type silicon, forms a
p-n junction with the substrate of the device. This junction
is reverse biased during normal operation.
In some applications the parasitic LC of the external
MOSFET gate can ring and pull the OUTPUT pin below
ground. If the OUTPUT pin is pulled negative by more than
a diode drop the parasitic diode formed by the collector
LT1241 Series
12
Rev B
For more information www.analog.com
APPLICATIONS INFORMATION
of the output NPN and the substrate will turn on. This
can cause erratic operation of the device. In these cases
a Schottky clamp diode is recommended from the output
to ground.
Reference
The internal reference of the LT1241 series devices is
a 5V bandgap reference, trimmed to within ±1% initial
tolerance. The reference is used to power the majority
of internal logic and the oscillator circuitry. The oscilla-
tor charging current is supplied from the reference. The
feedback pin voltage and the clamp level for the current
sense comparator are derived from the reference voltage.
The reference can supply up to 20mA of current to power
external circuitry. Note that using the reference in this
manner, as a voltage regulator, will significantly increase
power dissipation in the device which will reduce the use-
ful operating ambient temperature range.
Design/Layout Considerations
LT1241 series devices are high speed circuits capable of
generating pulsed output drive currents of up to 1A peak.
The rise and fall time for the output drive current is in the
range of 10ns to 20ns. High speed circuit techniques must
be used to insure proper operation of the device. Do not
attempt to use Proto-boards or wire-wrap techniques
to breadboard high speed switching regulator circuits.
They will not work properly.
Printed circuit layouts should include separate ground
paths for the voltage feedback network, oscillator capaci-
tor, and switch drive current. These ground paths should
be connected together directly at the ground pin (Pin 5)
of the LT124X. This will minimize noise problems due
to pulsed ground pin currents. VCC should be bypassed,
with a minimum of 0.1µF, as close to the device as pos-
sible. High current paths should be kept short and they
should be separated from the feedback voltage network
with shield traces if possible.
LT1241 Series
13
Rev B
For more information www.analog.com
TYPICAL APPLICATIONS
External Clock Synchronization
Adjustable Clamp Level with Soft-Start
Soft-Start
+
–
+
–
2
–
+
4
1
8
7
5
6
LT1241 • TA03
FB
COMP
RT/CT
VREF VIN
R
S
R2
CR1
VCLAMP ≈ 1.67
R2 + 1
R1
(
(
IPK (MAX) ≈ VCLAMP
RS WHERE: 0V ≤ VCLAMP ≤ 1.0V tSOFT-START = –ln 1 – VC C R1 R2
3 • VCLAMP R1 + R2
ISENSE
2.5V
2R
R
1V
1.5V
BLANKING
1mA
5.6V
OSCILLATOR
R
S
18V
VCC
UV
LOCKOUT
GND
OUTPUT
5V REF
MAIN BIAS REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
T
3
100k
LT1241 • TA01
5V REF
OSCILLATOR
EXTERNAL
SYNC
INPUT 0.01µF
47Ω
CT
D1
RT
RT/CT
V
REF
D1 IS REQUIRED IF THE SYNC AMPLITUDE IS LARGE
ENOUGH TO PULL THE BOTTOM OF CT MORE THAN
300mV BELOW GROUND.
8
4
++
–
+
–
1
2
–
+
3
LT1241 • TA02
R
V
REF
FB
COMP
ISENSE
C
2.5V
2R
R
1V
1.5V
1mA
5.6V
85V REF
LT1241 Series
14
Rev B
For more information www.analog.com
TYPICAL APPLICATIONS
300kHz Off-Line Power Supply
LT1241 • TA06
HOT
NEU
90VAC
TO
240VAC
R5
1M
1/2W
C2
0.1µF
250V
MP3-X2
2 4
1 3
T1
BALEN
C3
0.1µF
250V
MP3-X2
C4
4700pF
250V
Y-CAP
D5
–+
2KBPO8M
C5
4700pF
250V
Y-CAP
AC GND
C6
4700pF
250V
Y-CAP
R1
200k
1/2W
+
C14
100µF
400V
RT1
MCID404
2KBPOO5M
R3
200k
1/2W
D6
1N5245B
15V
R2
660k
1/10W
R4
660k
1/10W
C1
470pF
R5
27k
2W
D1
MUR160
30T
8
2
13T
3
6
30T
7
1
R7
510
1/10W
C7
0.22µF
MKS-2
R8
152k
C8
100pF
D7
BAV21
VCC
GND
RT/CT
VREF
COMP
C10
0.1µF
MKS-2
R9
200k
C9
0.01µF, 100V
MKS-2
2
7
1
8
4
R13
12k
C11
220pF
R10
20k
LT1241
5
OUTPUT
ISENSE
R12
1k
1/10W
6
3D4
BAT 85
R18
2Ω
1/4W
R16
2Ω
1/4W
R17
2Ω
1/4W
R11
12 Q1
MPT2N60
C12
22µF
25V
R14
39
D2
BAV21
LP = 100µH
12T
4
5
T2
D3
MUR420
C15
3.3µF
50V
R15
750Ω
1W
L1
5 1/2 TURN
AIRCORE
C16
3.3µF
50V
C13
4700pF
1kV
Y-CAP
20V
1.5A
RTN
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTANCES ARE IN OHMS, 1/4W, 5%.
2. ALL CAPACITANCES ARE IN MICROFARADS, 50V, 10%.
1212-R6103
COILTRONICS
CTX210433-1
FB
LT1241 Series
15
Rev B
For more information www.analog.com
TYPICAL APPLICATIONS
Slope Compensation at ISENSE Pin
+
–
+
–
–
+
LT1241 • TA04
RT
CT
FB
COMP
RT/CT
VREF VIN
RS
ISENSE
2
2.5V
2R
R
1V
1.5V
BLANKING
1mA
5.6V
OSCILLATOR
R
S
18V
7
VCC
UV
LOCKOUT
5
GND
6
OUTPUT
5V REF
MAIN BIAS REFERENCE PULL-DOWN
OUTPUT
PULL-DOWN
REFERENCE ENABLE
T
1
8
3
4
LT1241 Series
16
Rev B
For more information www.analog.com
OBSOLETE PACKAGE
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT1241#packaging for the most recent package drawings.
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
.005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
1 2 34
8 7 6 5
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
LT1241 Series
17
Rev B
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT1241#packaging for the most recent package drawings.
N8 REV I 0711
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ±.005
(3.302 ±0.127)
.020
(0.508)
MIN
.018 ±.003
(0.457 ±0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
1 2 34
87 65
.255 ±.015*
(6.477 ±0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LT1241 Series
18
Rev B
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT1241#packaging for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030
±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LT1241 Series
19
Rev B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REV DATE DESCRIPTION PAGE NUMBER
B 04/18 Deleted CERDIP J8 package 2
REVISION HISTORY
(Revision history begins at Rev B)
LT1241 Series
20
Rev B
ANALOG DEVICES, INC. 1992-2018
D16858-0-4/18(B)
www.analog.com
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LT1241 • TA05
FB
COMP
RT/CT
VREF
ISENSE
+
–
+
–
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2R
R
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1.5V
–
+
BLANKING
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R
S
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REFERENCE ENABLE
T
8
3
RSLOPE
TO
V
OUT
2
Rf
RT
CT
1