D−8 PW−8
1
FEATURES APPLICATIONS
1
2
3
45
6
7
8
VSS
CLASS UVLO
DET RTN
PG
VDD
ILIM
1
2
3
45
6
7
8
VSS
CLASS N/C
DET
RTN
PG
VDD
ILIM
TPS2375/77
(TOP VIEW) TPS2376
(TOP VIEW)
DESCRIPTION
TPS2375
SMAJ58A
Data to
Ethernet PHY
VDD
VSS
CLASS
DET
RTN
PG
Data to
Ethernet
PHY
1
3
6
4
5
7
8
TO DC/DC
CONVERTER
ILIM
2
RJ−45
DF01S
2 Places
Note: Class 3 PD Depicted.
PG Pullup Resistor Is Optional.
TX
Pair
RX
Pair
Spare
Pair
Spare
Pair
VDD
Input
Current
VRTN
V
Detect Classify Power Up & Inrush
Class 3
(PG-RTN)
100
kW
100 V
100 mF,
R(DET)
24.9 kW,
1 %
R(ILIM)
178 kW,
1 %
R(ICLASS)
357 W,
1 %
100 V
0.1mF,
10 %
Note: All Voltages With Respect to VSS.
Current
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
IEEE 802.3af PoE POWERED DEVICE CONTROLLERS
•VoIP Phones•Fully Supports IEEE 802.3af Specification
•WLAN Access Points•Integrated 0.58- Ω, 100-V, Low-Side Switch
•Security Cameras•15-kV System Level ESD Capable
•Internet Appliances•Supports Use of Low-Cost Silicon Rectifiers
•POS Terminals•Programmable Inrush Current Control•Fixed 450-mA Current Limit•Fixed and Adjustable UVLO Options•Open-Drain, Power-Good Reporting•Overtemperature Protection•Industrial Temperature Range: -40 °C to 85 °C•8-Pin SOIC and TSSOP Packages
These easy-to-use 8-pin integrated circuits contain all of the features needed to develop an IEEE 802.3afcompliant powered device (PD). The TPS2375 family is a second generation PDC (PD Controller) featuring100-V ratings and a true open-drain, power-good function.
In addition to the basic functions of detection, classification and undervoltage lockout (UVLO), these controllersinclude an adjustable inrush limiting feature. The TPS2375 has 802.3af compliant UVLO limits, the TPS2377 haslegacy UVLO limits, and the TPS2376 has a programmable UVLO with a dedicated input pin.
The TPS2375 family specifications incorporate a voltage offset of 1.5 V between its limits and the IEEE 802.3afspecifications to accommodate the required input diode bridges used to make the PD polarity insensitive.
Additional resources can be found on the TI Web site www.ti.com.
Figure 1. Typical Application Circuit and Startup Waveforms
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
AVAILABLE OPTIONS
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
(1)
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
UVLO THRESHOLDS (NOMINAL) PACKAGE
(1)T
A
MARKINGTYPE LOW HIGH SO-8 TSSOP-8
802.3af 30.5 V 39.3 V TPS2375D TPS2375PW 2375-40 °C to 85 °C Adjustable 1.93 V 2.49 V TPS2376D TPS2376PW 2376Legacy 30.5 V 35.1 V TPS2377D TPS2377PW 2377
(1) Add an R suffix to the device type for tape and reel.
over operating free-air temperature range (unless otherwise noted)
(1)
, voltages are referenced to V
(VSS)
TPS237x
VDD, RTN, DET, PG
(2)
-0.3 V to 100 VVoltage ILIM, UVLO -0.3 V to 10 VCLASS -0.3 V to 12 VRTN
(3)
0 to 515 mACurrent, sinking PG 0 to 5 mADET 0 to 1 mACLASS 0 to 50 mACurrent, sourcing
ILIM 0 to 1 mAHuman body model 2 kVESD Charged device model 500 VSystem level (contact/air) at RJ-45
(4)
8/15 kVT
J
Maximum junction temperature range Internally limitedT
stg
Storage temperature range -65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Green Packages 260 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Nongreen Packages 235 °C
(1) Stresses beyond those listed under “ absolute maximum ratings ” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operatingconditions ” is not implied. Exposure to absolute – maximum – rated conditions for extended periods may affect device reliability.(2) I
(RTN)
= 0(3) SOA limited to V
(RTN)
= 80 V and I
(RTN)
= 515 mA.(4) Surges applied to RJ-45 of Figure 1 between pins of RJ-45, and between pins and output voltage rails per EN61000-4-2, 1999.
POWER RATINGθ
JA
(LOW-K) θ
JA
(HIGH-K) (HIGH-K)PACKAGE
°C/W °C/W T
A
= 85 °CmW
D (SO-8) 238 150 266PW (TSSOP-8) 258.5 159 251
(1) Tested per JEDEC JESD51. High-K is a (2 signal – 2 plane) test board and low-K is a double sidedboard with minimum pad area and natural convection.
2Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
MIN MAX UNIT
VDD, PG, RTN 0 57 VInput voltage range
UVLO 0 5 VOperating current range (sinking) RTN 0 350 mAClassification resistor
(1)
CLASS 255 4420 Ω
R
(ILIM)
Inrush limit program resistor
(1)
62.5 500 k Ω
Sinking current PG 0 2 mAT
J
Operating junction temperature -40 125 °CT
A
Operating free – air temperature -40 85 °C
(1) Voltage should not be eternally applied to CLASS and ILIM.
V
(VDD)
= 48 V, R
(DET)
= 24.9 k Ω, R
(CLASS)
= 255 Ω, R
(ILIM)
= 178 k Ω, and – 40 °C≤T
J
≤125 °C, unless otherwise noted. Positivecurrents are into pins. V
(UVLO)
= 0 V for classification and V
(UVLO)
= 5 V otherwise for the TPS2376. Typical values are at 25 °C.All voltages are with respect to VSS unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DETECTION
DET open, V
(VDD)
= V
(RTN)
= 1.9 V, measureOffset current 0.3 3 µAI
(VDD)
+ I
(RTN)
DET open, V
(VDD)
= V
(RTN)
= 10.1 V, measureSleep current 4 12 µAI
(VDD)
+ I
(RTN)
DET leakage current V
(DET)
= V
(VDD)
= 57 V, measure I
(DET)
0.1 5 µA
V
(RTN)
= V
(VDD)
, V
(VDD)
= 1.4 V 53.7 56 58.3 µAR
(DET)
= 24.9 k Ω,Detection current
measure I
(VDD)
+ I
(RTN)
+
V
(VDD)
= 10.1 V 395 410 417 µAI
(DET)
CLASSIFICATION
R
(CLASS)
= 4420 Ω, 13 ≤V
(VDD)
≤21 V 2.2 2.4 2.8
R
(CLASS)
= 953 Ω, 13 ≤V
(VDD)
≤21 V 10.3 10.6 11.3
I
(CLASS)
Classification current
(1)
R
(CLASS)
= 549 Ω, 13 ≤V
(VDD)
≤21 V 17.7 18.3 19.5 mA
R
(CLASS)
= 357 Ω, 13 ≤V
(VDD)
≤21 V 27.1 28.0 29.5
R
(CLASS)
= 255 Ω, 13 ≤V
(VDD)
≤21 V 38.0 39.4 41.2
V
(CL_ON)
Classification lower threshold Regulator turns on, V
(VDD)
rising 10.2 11.3 13.0 V
V
(CU_OFF)
Regulator turns off, V
(VDD)
rising 21 21.9 23 VClassification upper thresholdV
(CU_H)
Hysteresis 0.5 0.78 1 V
Leakage current V
(CLASS)
= 0 V, V
(VDD)
= 57 V 1 µA
PASS DEVICE
r
DS(on)
On resistance I
(RTN)
= 300 mA 0.58 1.0 Ω
V
(VDD)
= V
(RTN)
= 30 V, 15Leakage current µAV
(UVLO)
= 0 V (TPS2376)
Current limit V
(RTN)
= 1 V 405 461 515 mA
I
(LIM)
Inrush limit V
(RTN)
= 2 V, R
(ILIM)
= 178 k Ω100 130 180 mA
V
(RTN)
falling, R
(ILIM)
= 178 k Ω, inrush 85% 91% 100%Inrush current termination
(2)
state →normal operation
R
(ILIM)
= 69.8 k Ω, V
(RTN-VSS)
= 5 V, 15 25Current rise time into inrush I
(RTN)
= 30 mA →300 mA, V
(VDD)
increasing µspast upper UVLO
Apply load ∞ Ω → 20 Ω, time measured to 2 2.5Current limit response time µsI
(RTN)
= 45 mA
Leakage current, ILIM V
(VDD)
= 15 V, V
(UVLO)
= 0 V 1 µA
(1) Classification is tested with exact resistor values. A 1% tolerance classification resistor assures compliance with IEEE 802.3af limits.(2) This parameter specifies the RTN current value, as a percentage of the steady state inrush current, below which it must fall to make PGassert (open-drain).
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2375 TPS2376 TPS2377
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)V
(VDD)
= 48 V, R
(DET)
= 24.9 k Ω, R
(CLASS)
= 255 Ω, R
(ILIM)
= 178 k Ω, and – 40 °C≤T
J
≤125 °C, unless otherwise noted. Positivecurrents are into pins. V
(UVLO)
= 0 V for classification and V
(UVLO)
= 5 V otherwise for the TPS2376. Typical values are at 25 °C.All voltages are with respect to VSS unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PG
Latchoff voltage threshold rising V
(RTN)
rising 9.5 10.0 10.5 V
PG deglitch Delay rising and falling PG 75 150 225 µs
I
(PG)
= 2 mA, V
(RTN)
= 34 V, 0.12 0.4
VV
(VDD)
= 38 V, V
(RTN)
fallingOutput low voltage
I
(PG)
= 2 mA, V
(RTN)
= 0 V, V
(VDD)
= 25 V, for 0.12 0.4
VTPS2376 V
(UVLO)
= 0 V
Leakage current V
(PG)
= 57 V, V
(RTN)
= 0 V 0.1 1 µA
UVLO
V
(UVLO_R)
V
(VDD)
rising 38.4 39.3 40.4
V
(UVLO_F)
TPS2375 Voltage at VDD V
(VDD)
falling 29.6 30.5 31.5 V
Hysteresis 8.3 8.8 9.1
V
(VDD)
rising 2.43 2.49 2.57
TPS2376 Voltage at UVLO V
(VDD)
falling 1.87 1.93 1.98 V
Hysteresis 0.53 0.56 0.58
V
(VDD)
rising 34.1 35.1 36.0
TPS2377 Voltage at VDD V
(VDD)
falling 29.7 30.5 31.4 V
Hysteresis 4.3 4.5 4.8
TPS2376 Input leakage, UVLO V
(UVLO)
= 0 V to 5 V -1 1 µA
THERMAL SHUTDOWN
Shutdown temperature Temperature rising 135 °C
Hysteresis 20 °C
BIAS CURRENT
Operating current I
(VDD)
240 450 µA
4Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
DEVICE INFORMATION
−
+
10V
Regulator
ThermalShutdown,
Counter,andLatch
QS
R
−
+
−
+
3
2
12V
22V
1.5V
&10V
2.5V
−
+
VDD
RTN
45mV
CLASS
DET
Current
Limit Amp.
UVLO
Comp.
EN
Delay
QS
R
5
8
6
PG
−
+
0= Inrush 0=Fault
1=Limiting
PGComparator
Detection
Comparator
Classification
Comparator
0
1
7
UVLO
’76Only
−
+
2.5V
1
ILIM
1:1
4
VSS
See
Note Current
Mirror
800 W
0.08 W
150 Sm
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
FUNCTIONAL BLOCK DIAGRAM
Note: For the TPS2376, the UVLO comparator connects to the UVLO pin and not to the UVLO divider.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS2375 TPS2376 TPS2377
Detailed Pin Description
I(LIM) +25000
R(ILIM)
(1)
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
TERMINAL FUNCTIONS
PIN NUMBERPIN NAME I/O DESCRIPTIONTPS2375/77 TPS2376
Connect a resistor from ILIM to VSS to set the start-up inrush current limit.ILIM 1 1 O The equation for calculating the resistor is shown in the detailed pindescription section for ILIM.Connect a resistor from CLASS to VSS to set the classification of theCLASS 2 2 O powered device (PD). The IEEE classification levels and correspondingresistor values are shown in Table 1 .Connect a 24.9-k Ωdetection resistor from DET to VDD for a valid PDDET 3 3 O
detection.VSS 4 4 I Return line on the source side of the TPS2375 from the PSE.Switched output side return line used as the low-side reference for theRTN 5 5 O
TPS2375 load.PG 6 6 O Open-drain, power-good output; active high.Used only on the TPS2376. Connect a resistor divider from VDD to VSS toUVLO - 7 I
implement the adjustable UVLO feature of the TPS2376.NC 7 - No connectionVDD 8 8 I Positive line from the rectified PSE provided input.
The following descriptions refer to the schematic of Figure 1 and the functional block diagram.
ILIM: A resistor from this pin to VSS sets the inrush current limit per Equation 1 :
where ILIM is the desired inrush current value, in amperes, and R
(ILIM)
is the value of the programming resistorfrom ILIM to VSS, in ohms. The practical limits on R
(ILIM)
are 62.5 k Ωto 500 k Ω. A value of 178 k Ωisrecommended for compatibility with legacy PSEs.
Inrush current limiting prevents current drawn by the bulk capacitor from causing the line voltage to sag belowthe lower UVLO threshold. Adjustable inrush current limiting allows the use of arbitrarily large capacitors and alsoaccommodates legacy systems that require low inrush currents.
The ILIM pin must not be left open or shorted to VSS.
CLASS: Classification is implemented by means of an external resistor, R
(CLASS)
, connected between CLASSand VSS. The controller draws current from the input line through R
(CLASS)
when the input voltage lies between13 V and 21 V. The classification currents specified in the electrical characteristics table include the bias currentflowing into VDD and any RTN leakage current.
Table 1. CLASSIFICATION
CLASS PD POWER (W) R
(CLASS)
(Ω) 802.3af LIMITS (mA) NOTE
0 0.44 – 12.95 4420 ± 1% 0 - 4 Default class1 0.44 – 3.84 953 ± 1% 9 - 122 3.84 – 6.49 549 ± 1% 17 - 203 6.49 – 12.95 357 ± 1% 26 - 304 - 255 ± 1% 36 - 44 Reserved for future use
The CLASS pin must not be shorted to ground.
DET: Connect a resistor, R
(DET)
, between DET and VDD. This resistor should equal 24.9 k Ω, ± 1% for mostapplications. R
(DET)
is connected across the input line when V
(VDD)
lies between 1.4 V and 11.3 V, and isdisconnected when the line voltage exceeds this range to conserve power. This voltage range has been chosento allow detection with two silicon rectifiers between the controller and the RJ-45 connector.
VSS: This is the input supply negative rail that serves as a local ground to the TPS2375.
6Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
RTN: This pin provides the switched negative power rail used by the downstream circuits. The operational andinrush current limit control current into the pin. The PG circuit monitors the RTN voltage and also uses it as thereturn for the PG pin pulldown transistor. The internal MOSFET body diode clamps VSS to RTN when voltage ispresent between VDD and RTN and the PoE input is not present.
PG: This pin goes to a high resistance state when the internal MOSFET that feeds the RTN pin is enabled, andthe device is not in inrush current limiting. In all other states except detection, the PG output is pulled to RTN bythe internal open-drain transistor. Performance is assured with at least 4 V between VDD and RTN.
PG is an open-drain output; therefore, it may require a pullup resistor or other interface.
UVLO: This pin is specific to the TPS2376; it is not internally connected on the TPS2375 and TPS2377. TheUVLO pin is used with an external resistor divider between VDD and VSS to set the upper and lower UVLOthresholds. The hysteresis, as measured as a percentage of the upper UVLO, is the same as the TPS2375.
The TPS2376 enables the output when V
(UVLO)
exceeds the upper UVLO threshold. When current begins to flow,VDD sags due to cable resistance and the dynamic resistance of the input diodes. The lower UVLO thresholdmust be below the lowest voltage that the input reaches.
The TPS2376 implements adjustable UVLO thresholds, but is otherwise functionally equivalent to the TPS2375.The TPS2375 offers fixed UVLO thresholds designed to maximize hysteresis while maintaining compatibility withthe IEEE 802.3af standard. The TPS2377 offers fixed UVLO thresholds optimized for use with legacy PoEsystems.
VDD: This is the positive input supply to the TPS2375, which is also common to downstream load circuits. Thispin provides operating power and allows the controller to monitor the line voltage to determine the mode ofoperation.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2375 TPS2376 TPS2377
TYPICAL CHARACTERISTICS
11.0
11.1
11.2
11.3
−40 −20 0 20 40 60 80 100 120
Classification Turnon Voltage − V
TA − Free-Air Temperature − °C
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7 8 9 10 11
TA = 125°C
TA = 25°C
TA = −40°C
V(VDD) − V
Current − Aµ
10
15
20
25
30
35
1 3 5 7 9 11
Specification Limits
V(PI) − V
Resistance − kΩ
0.100
0.150
0.200
0.250
0.300
0.350
22 27 32 37 42 47 52 57
VDD − V
I(VDD) − mA
TA = 125°C
TA = 25°C
TA = −40°C
0.4
0.5
0.6
0.7
0.8
0.9
−40 −20 0 20 40 60 80 100 120
Pass Device Resistance − Ω
TA − Free-Air Temperature − °C
39.2
39.3
39.4
39.5
−40 −20 0 20 40 60 80 100 120
TA − Free-Air Temperature − °C
VDD − V
30.40
30.44
30.48
30.52
30.56
30.60
−40 −20 0 20 40 60 80 100 120
TA − Free-Air Temperature − °C
VDD − V
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
Graphs over temperature are interpolations between the marked data points.
CLASSIFICATION TURNONPD DETECTION RESISTANCE VOLTAGEvs vsI
(VDD)
+ I
(RTN)
IN DETECTION V
(PI)
TEMPERATURE
Figure 2. Figure 3. Figure 4.
CLASSIFICATION TURNOFF PASS DEVICEVOLTAGE I
(VDD)
CURRENT RESISTANCEvs vs vsTEMPERATURE VDD TEMPERATURE
Figure 5. Figure 6. Figure 7.
TPS2375 TPS2375 TPS2376UVLO RISING UVLO FALLING UVLO RISINGvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 8. Figure 9. Figure 10.
8Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
425
430
435
440
−40 −20 0 20 40 60 80 100 120
TA − Free-Air Temperature − °C
I(RTN) − mA
90.5
91.0
91.5
92.0
92.5
93.0
93.5
94.0
−40 −20 0 20 40 60 80 100 120
Percent of Inrush Limit Current
TA − Free-Air Temperature − °C
100
125
150
175
200
225
250
275
300
325
350
−40 −20 0 20 40 60 80 100 120
I(ILIM) − mA
TA − Free-Air Temperature − °C
75 kΩ
125 kΩ
178 kΩ
120
140
160
180
−40 −20 0 20 40 60 80 100 120
PG Deglitch Period − sµ
TA − Free-Air Temperature − °C
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
TYPICAL CHARACTERISTICS (continued)Graphs over temperature are interpolations between the marked data points.
TPS2376 TPS2377 TPS2377UVLO FALLING UVLO RISING UVLO FALLINGvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 11. Figure 12. Figure 13.
INRUSH STATE TERMINATION
THRESHOLD INRUSH CURRENT CURRENT LIMITvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 14. Figure 15. Figure 16.
PG DEGLITCH PERIOD
vsTEMPERATURE
Figure 17.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2375 TPS2376 TPS2377
APPLICATION INFORMATION
OVERVIEW
Normal Operation
57
42
363020.514.510.12.7
Detection
Lower Limit
Detection
Upper Limit
Classification
Lower Limit
Classification
Upper Limit
Must Turn Off by −
Voltage Falling
Lower Limit −
Proper Operation
Must Turn On by−
Voltage Rising
Maximum Input
Voltage
Detect Classify Shut -
down
PI Voltage (V)
0
INTERNAL THRESHOLDS
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
The IEEE 802.3af specification defines a process for safely powering a PD over a cable, and then removingpower if a PD is disconnected. The process proceeds through three operational states: detection, classification,and operation. The intent behind the process is to leave an unterminated cable unpowered while the PSEperiodically checks for a plugged-in device; this is referred to as detection. The low power levels used duringdetection are unlikely to cause damage to devices not designed for PoE. If a valid PD signature is present, thenthe PSE may optionally inquire how much power the PD requires; this is referred to as classification. The PDmay return a default full-power signature, or one of four other choices. Knowing the power demand of each PDallows the PSE to intelligently allocate power between PDs, and also to protect itself against overload. The PSEpowers up a valid PD, and then monitors its output for overloads. The maintain power signature (MPS) ispresented by the powered PD to assure the PSE that it is there. The PSE monitors its output for the MPS to seeif the PD is removed, and turns the port off, if it loses the MPS. Loss of MPS returns the PSE to the initial state ofdetection. Figure 18 shows the operational states as a function of PD input voltage range.
The PD input is typically an RJ-45 (8-pin) connector, referred to as the power interface (PI). PD inputrequirements differ from PSE output requirements to account for voltage drops in the cable and margin. Thespecification uses a cable resistance of 20 Ωto derive the voltage limits at the PD from the PSE outputrequirements. Although the standard specifies an output power of 15.4 W at the PSE output, there is only12.95 W available at the input of the PD due to the worst case power loss in the cable.
The PSE can apply voltage either between the RX and TX pairs, or between the two spare pairs as shown inFigure 1 . The applied voltage can be of either polarity. The PSE cannot apply voltage to both paths at the sametime. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltagedrops associated with the input bridges cause a difference between the IEEE 802.3af limits at the PI and theTPS2375 specifications.
The PSE is required to current limit between 350 mA and 400 mA during normal operation, and it mustdisconnect the PD if it draws this current for more than 75 ms. The PSE may set lower output current limitsbased on the PD advertised power requirements, as discussed below.
The following discussion is intended as an aid in understanding the operation of the TPS2375, but not as asubstitute for the actual IEEE 802.3af standard. Standards change and should always be referenced whenmaking design decisions.
Figure 18. IEEE 802.3 PD Limits
In order to implement the PoE functionality as shown in Figure 18 , the TPS2375 has a number of internalcomparators with hysteresis for stable switching between the various states. Figure 19 relates the parameters inthe Electrical Characteristics section to the PoE states. The mode labeled idle between classification anddetection implies that the DET, CLASS, PG, and RTN pins are all high impedance.
10 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
Operational Mode
Detection
Classification
PD Powered
Idle
1.4V V(CL_ON) V(CU_OFF)
V(CU_H) V(UVLO_F) V(UVLO_R)
V(VDD)
DETECTION
CLASSIFICATION
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
Figure 19. Threshold Voltages
This feature of IEEE 802.3af eliminates powering and potentially damaging Ethernet devices not intended forapplication of 48 V. When a voltage in the range of 2.7 V to 10.1 V is applied to the PI, an incremental resistanceof 25 k Ωsignals the PSE that the PD is capable of accepting power. A PD that is capable of accepting power,but is not ready, may present an incorrect signature intentionally. The incremental resistance is measured byapplying two different voltages to the PI and measuring the current it draws. These two test voltages must bewithin the specified range and be at least 1 V apart. The incremental resistance equals the difference betweenthe voltages divided by the difference between the currents. The allowed range of resistance is 23.75 k Ωto26.25 k Ω.
The TPS2375 is in detection mode whenever the supply voltage is below the lower classification threshold. TheTPS2375 draws a minimum of bias power in this condition, while PG and RTN are high impedance and thecircuits associated with ILIM and CLASS are disabled. The DET pin is pulled to ground during detection. Currentflowing through R
(DET)
to VSS (Figure 1 ) produces the detection signature. For most applications, a 24.9-k Ω, 1%,resistor is recommended. R
(DET)
can be a small, low-power resistor because it only sees a stress of about 5 mW.When the input voltage rises above the 11.3 V lower classification comparator threshold, the DET pin goes to anopen-drain condition to conserve power.
The input diode bridge incremental resistance can be hundreds of ohms at the low currents seen at 2.7 V on thePI. The bridge resistance is in series with R
(DET)
and increases the total resistance seen by the PSE. This varyswith the type of diode selected by the designer, and it is not usually specified on the diode data sheet. The valueof R
(DET)
may be adjusted downwards to accommodate a particular diode type.
Once the PSE has detected a PD, it may optionally classify the PD. This process allows a PSE to determine thePD power requirements in order to allot only as much power as necessary from its fixed input power source. Thisallows the PSE to power the maximum number of PDs from a particular power budget. This step is optionalbecause some PSEs can afford to allot the full power to every powered port.
The classification process applies a voltage between 14.5 V and 20.5 V to the input of the PD, which in turndraws a fixed current set by R
(CLASS)
. The PSE measures the PD current to determine which of the five availableclasses (Table 1 ) that the PD is signalling. The total current drawn from the PSE during classification is the sumof bias currents and current through R
(CLASS)
. The TPS2375 disconnects R
(CLASS)
at voltages above theclassification range to avoid excessive power dissipation (Figure 18 and Figure 19 ).
The value of R
(CLASS)
should be chosen from the values listed in Table 1 based on the average powerrequirements of the PD. The power rating of this resistor should be chosen so that it is not overstressed for therequired 75-ms classification period, during which 10 V is applied. The PD could be in classification for extendedperiods during bench test conditions, or if an auxiliary power source with voltage within the classification range isconnected to the PD front end. Thermal protection may activate and turn classification off if it continues for morethan 75 ms, but the design must not rely on this function to protect the resistor.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS2375 TPS2376 TPS2377
UNDERVOLTAGE LOCKOUT (UVLO)
PROGRAMMABLE INRUSH CURRENT LIMIT AND FIXED OPERATIONAL CURRENT LIMIT
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
The TPS2375 incorporates an undervoltage lockout (UVLO) circuit that monitors line voltage to determine whento apply power to the downstream load and allow the PD to power up. The IEEE 802.3af specification dictates amaximum PD turnon voltage of 42 V and a minimum turnoff voltage of 30 V (Figure 19 ). The IEEE 802.3afstandard assumes an 8-V drop in the cabling based on a 20- Ωfeed resistance and a 400-mA maximum inrushlimit. Because the minimum PSE output voltage is 44 V, the PD must continue to operate properly with inputvoltages as low as 36 V. The TPS2375 UVLO limits are designed to meet the turnon, turnoff, and hysteresisrequirements.
Various legacy PSE systems in the field do not meet the minimum output voltage of 44 V. The TPS2377 UVLOlimits are designed to support these systems with a lower turnon voltage and smaller hysteresis. Although theTPS2377 works with compliant PSEs, it could potentially exhibit startup instabilities if the PSE output voltagerises slowly. The TPS2375 is recommended for applications with compliant PSEs.
In order to provide flexibility for noncompliant designs, the TPS2376 allows the designer to program the turnonthresholds with a resistor divider. The hysteresis of the TPS2376, measured as a percentage of the turnonvoltage, is similar to that of the TPS2375. To use the TPS2376, connect a resistor divider between VDD andVSS with the tap connected to the UVLO pin. The total divider resistance appears in parallel with the R
(DET)
, andthe combination of the two should equal 24.9 k Ω. The divider ratio should be chosen to obtain 2.5 V at the UVLOpin when V
(VDD)
is at the desired turnon voltage.
The TPS2375 uses the UVLO function to control the load through an onboard MOSFET switch. Figure 19graphically shows the relationships of the UVLO thresholds defined in the Electrical Characteristics section to theTPS2375 operational states.
Inrush limiting is beneficial for a number of reasons. First, it provides a mechanism to keep the inrush currentbelow the 400 mA, 50 ms, maximum inrush allowed by the standard. Second, by reducing the level of the currentlimit below the PSE operational limit, which can be as low as the classification power divided by the PSE voltage,it allows an arbitrarily large bulk capacitor to be charged. Third, some legacy PSEs may not tolerate large inrushcurrents while powering their outputs up.
The TPS2375 operational current limit protects the internal power switch from instantaneous output faults andcurrent surges. The minimum operational current limit level of 405 mA is above the maximum PSE output currentlimit of 400 mA. This current limit allows the PD to draw the maximum available power and also allows the PSEto detect fault conditions.
The TPS2375 incorporates a state machine that controls the inrush and operational current limit states. WhenV
(VDD)
is below the lower UVLO threshold, the current limit state machine is reset. In this condition, the RTN pinis high impedance, and at V
(VDD)
once the output capacitor is discharged by the downstream circuits. WhenV
(VDD)
rises above the UVLO turnon threshold, the TPS2375 enables the internal power MOSFET with thecurrent limit set to the programmed inrush value. The load capacitor charges and the RTN pin voltage falls fromV
(VDD)
to nearly V
(VSS)
. Once the inrush current falls about 10% below the programmed limit, the current limitswitches to the internal 450-mA operational level after a 150- µs delay. This switchover can be seen in theoperation of PG, which goes active (open drain) after inrush terminates as seen in Figure 1 . The internal powerMOSFET is disabled if the input voltage drops below the lower UVLO threshold.
When in the operating current-limit state, a fault on the output or a large input transient can cause the internalMOSFET to limit current. The RTN voltage rises above its normal operating level of less than 0.5 V while incurrent-limit state. If V
(RTN)
rises above 10 V for more than 150 µs, the MOSFET is latched off. The PD inputvoltage must drop below the lower UVLO threshold to clear this latch. If the RTN voltage does not exceed 10 Vwhile in current-limit state, but the condition persists long enough to overheat the TPS2375, the thermal limitcircuit activates, as described in the thermal protection section.
Practical values of R
(ILIM)
lie between 62.5 k Ωand 500 k Ω. The pin must not be left open. An inrush level of140 mA, set by an R
(ILIM)
of 178 k Ω, should be used with TPS2377 applications for compatibility with legacysystems. This same inrush current level suffices for many TPS2375 applications.
The inrush limit, the bulk capacitor size, and the downstream dc/dc converter startup method must be chosen sothat the converter input current does not exceed the inrush current limit while it is active. This can be achieved byusing the PG output to enable the downstream converter after inrush finishes, by delaying the converter startupuntil inrush finishes, or by increasing the value of the inrush current limit.
12 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
MAINTAIN POWER SIGNATURE
POWER GOOD
THERMAL PROTECTION
Ch1: VDD @ 50 V/div
CH2: RTN @ 50 V/div
Iin @ 100 mA/div
V(PI) = 44 V, R(ILIM) = 178 kW
CH3: V(PG) @ 50 V/div
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
Once a valid PD has been detected and powered, the PSE uses the maintain power signature (MPS) todetermine when to remove power from the PI. The PSE removes power from that output port if it detects loss ofMPS for 300 ms or more. A valid MPS requires the PD to draw at least 10 mA and also have an ac impedanceless than 26.25 k Ω in parallel with 0.05 µF. TI's reference designs meet the requirements necessary to maintainpower.
The TPS2375 includes a power-good circuit that can be used to signal the PD circuitry that the load capacitor isfully charged. This pin is intended for use as an enable signal for downstream circuitry. If the converter tries tostart up while inrush is active, and draws a current equal to the inrush limit, a latchup condition occurs in whichthe PD never successfully starts. Using the PG pin is the safest way to assure that there are no undesiredinteractions between the inrush limit, the converter startup characteristic, and the size of the bulk capacitor.
The PG pin goes to an open-drain state approximately 150 µs after the inrush current falls 10% below theregulated value. PG pulldown current is only assured when the voltage difference between VDD and RTNexceeds 4 V. This is not a limiting factor because the dc/dc converter should not be able to run from 4 V. The PGoutput is pulled to RTN whenever the MOSFET is disabled or is in inrush current limiting.
Referencing PG to RTN simplifies the interface to the downstream dc/dc converter or other circuit because it isreferenced to RTN, not VSS. Care must be used in interfacing the PG pin to the downstream circuits. The pullupto VDD shown in Figure 1 may not be appropriate for a particular dc/dc converter interface. The PG pin connectsto an internal open-drain, 100-V transistor capable of sinking 2 mA to a voltage below 0.4 V. The PG pin can beleft open if it is not used.
The controller may overheat after operation in current-limit state or classification for an extended period of time,or if the ambient temperature becomes excessive. The TPS2375 protects itself by disabling the RTN and CLASSpins when the internal die temperature reaches about 140 °C. It automatically restarts when the die temperaturehas fallen approximately 20 °C. If this cycle occurs eight times, then the device latches off until the supply voltagedrops below the lower classification threshold. This feature prevents the part from operating indefinitely in fault,and ensures that the PSE recognizes the fault condition when using dc MPS. Thermal protection is activewhenever the TPS2375 is not in detection.
Figure 20 shows how the TPS2375 responds when it is enabled into a short. The TPS2375 starts in the inrushcurrent-limit state when the input voltage exceeds the upper UVLO limit. A power dissipation of over 5 W heatsthe die from 25 °C to 140 °C in approximately 400 ms. The TPS2375 then shuts down until the die temperaturedrops to about 120 °C, which occurs in about 20 ms. This process repeats eight times before the TPS2375latches off. The PG pin is high because RTN is tied to VDD.
Figure 20. TPS2375 Started Into Short
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2375 TPS2376 TPS2377
POWER SYSTEM DESIGN
AUXILIARY POWER SOURCE ORING
TPS237X
SMAJ58A
R(DET)
R(CLASS)
VDDVSS
CLASS
DET
RTN
Main
DC/DC
Converter
Output
R(ILIM)
RJ−45
Option 1
ILIM
DC/DC
Converter
UCC3809
or
UCC3813
Optional
Regulator
Option 2
Option 3
A Full Wave Bridge
Gives Flexibility To
Use Supply With Either
Polarity
For Option 2,
The Capacitor Must Be
Right At The Output
To Control The
Transients.
Auxiliary
Power
Input
Use only
one option
See TI Document SLVR030 For A Typical
Application Circuit.
~
~
+
−
~
~
+
−
0.1 µF
22 µF
Inserting a Diode in This Location
With Option 2, Allows PoE To Start
With Aux Power Present.
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
The PSE is a power and current limited source, which imposes certain constraints on the PD power supplydesign. DC/DC converters have both a constant input power characteristic that causes them to draw highcurrents at low voltage, and they tend to go to a full input power mode during start-up that is often 25% or moreabove their rated power. Improper design of the power system can cause the PD to not start up with allcombinations of Ethernet lines and PSE sources.
The following guidelines should be used:1. Set the TPS2375 inrush to a moderate value as previously discussed.2. Hold the dc/dc converter off during inrush as previously discussed.3. The converter should have a softstart that keeps the peak input start-up current below 400 mA, andpreferably only a modest amount over the operating current, with a 44-V PSE source and a 20- Ωloop.4. If step 3 cannot be met, the bulk input capacitor should not discharge more than 8 V during converter startup from a 400-mA limited, 44-V source with a 20- Ωline. Start-up must be completed in less than 50 mS
Step 4 requires a balance between the converter output capacitance, load, and input bulk capacitance. Whilethere are some cases which may not require all these measures, such as a 1-W PD with minimal converteroutput capacitance, it is always a good practice to follow them.
Many PoE capable devices are designed to operate from either a wall adapter or PoE power. A local powersolution adds cost and complexity, but allows a product to be used regardless of PoE availability. Attempting tocreate solutions where the two power sources coexist in a specific controlled manner results in additionalcomplexity, and is not generally recommended. Figure 21 demonstrates three methods of diode ORing externalpower into a PD. Option 1 inserts power on the output side of the PoE power conversion. Option 2 inserts poweron the TPS2375 output. Option 3 applies power to the TPS2375 input. Each of these options has advantagesand disadvantages. The wall adapter must meet a minimum 1500-Vac dielectric withstand test voltage to the acinput power and to ground for options 2 and 3.
Figure 21. Auxiliary Power ORing
14 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
ESD
EXTERNAL COMPONENTS
Transformer
Input Diodes or Diode Bridges
data sheet
TPS2375
TPS2376
TPS2377
www.ti.com
............................................................................................................................................................ SLVS525B – APRIL 2004 – REVISED APRIL 2008
Option 1 consists of ORing power to the output of the PoE dc/dc converter. This option is preferred in caseswhere PoE is added to an existing design that uses a low-voltage wall adapter. The relatively large PDcapacitance reduces the potential for harmful transients when the adapter is plugged in. The wall adapter outputmay be grounded if the PD incorporates an isolated converter. This solution requires two separate regulators, butlow-voltage adapters are readily available. The PoE power can be given priority by setting its output voltageabove that from the auxiliary source.
Option 2 has the benefits that the adapter voltage may be lower than the TPS2375 UVLO, and that the bulkcapacitor shown can control voltage transients caused by plugging an adapter in. The capacitor size and locationare chosen to control the amount of ringing that can occur on this node, which can be affected by additionalfiltering components specific to a dc/dc converter design. The optional diode blocks the adapter voltage fromreverse biasing the input, and allows a PoE source to apply power provided that the PSE output voltage isgreater than the adapter voltage. The penalty of the diode is an additional power loss when running from PSEpower. The PSE may not be able to detect and start powering without the diode. This means that the adaptermay continue to power the PD until removed. Auxiliary voltage sources can be selected to be above or below thePoE operational voltage range. If automatic PoE precedence is desired when using the low-voltage auxiliarysource option, make sure that the TPS2375 inrush program limit is set higher than the maximum converter inputcurrent at its lowest operating voltage. It is difficult to use PG with the low-voltage auxiliary source because theconverter must operate during a condition when the TPS2375 would normally disable it. Circuits may bedesigned to force operation from one source or the other depending on the desired operation and the auxiliarysource voltage chosen. However, they are not recommended because they increase complexity and thus cost.
Option 3 inserts the power before the TPS2375. It is necessary for the adapter to meet the TPS2375 UVLOturnon requirement and to limit the maximum voltage to 57 V. This option provides a valid power-good signal andsimplifies power priority issues. The disadvantage of this method is that it is the most likely to cause transientvoltage problems. Plugging a powered adapter in applies a step input voltage to a node that has littlecapacitance to control the dv/dt and voltage ringing. If the wall mount supply applies power to the PD before thePSE, it prevents the PSE from detecting the PD. If the PSE is already powering the PD when the auxiliary sourceis plugged in, priority is given to the higher supply voltage.
The TPS2375 has been tested using the surge of EN61000-4-2 in an evaluation module (EVM) using the circuitin Figure 1 . The levels used were 8-kV contact discharge and 15-kV air discharge. Surges were applied betweenthe RJ-45 and the dc EVM outputs, and between an auxiliary power input jack and the dc outputs. No failureswere observed.
ESD requirements for a unit that incorporates the TPS2375 have much broader scope and operationalimplications than those used in TI ’ s testing. Unit level requirements should not be confused with EVM testing thatonly validated the TPS2375.
Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer per IEEE802.3 requirements, see Figure 1 . For powered devices, the isolation transformer must include a center tap onthe media (cable) side. Proper termination is required around the transformer to provide correct impedancematching and to avoid radiated and conducted emissions. Transformers must be specifically rated to work withthe Ethernet chipset, and the IEEE 802.3af standard.
The IEEE 802.3af requires the PD to accept power on either set of input pairs in either polarity. This requirementis satisfied by using two full-wave input bridge rectifiers as shown in Figure 1 . Silicon p-n diodes with a 1-A or1.5-A rating and a minimum breakdown of 100 V are recommended. Diodes exhibit large dynamic resistanceunder low-current operating conditions such as in detection. The diodes should be tested for their behavior underthis condition. The diode forward drops must be less than 1.5 V at 500 µA and at the lowest operatingtemperature.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2375 TPS2376 TPS2377
Input Capacitor
Load Capacitor
Cv
I(PD) 180
10 mA
(2)
Transient Suppressor
Layout
data sheet
TPS2375
TPS2376
TPS2377
SLVS525B – APRIL 2004 – REVISED APRIL 2008 ............................................................................................................................................................
www.ti.com
The IEEE 802.3af requires a PD input capacitance between 0.05 µF and 0.12 µF during detection. This capacitorshould be located directly adjacent to the TPS2375 as shown in Figure 1 . A 100-V, 10%, X7R ceramic capacitormeets the specification over a wide temperature range.
The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5 µF. It ispermissible to have a much larger load capacitor, and the TPS2375 can charge in excess of 470 µF beforethermal issues become a problem. However, if the load capacitor is too large, the PD design may violate IEEE802.3af requirements.
If the load capacitor is too large, there can be a problem with inadvertent power shutdown by the PSE caused byfailure to meet the MPS. This is caused by having a long input current dropout due to a drop in input voltage witha large capacitance-to-load ratio. The standard gives Equation 2 :
where C is the bulk capacitance in µF and I
(PD)
is the PD load current in mA.
A particular design may have a tendency to cause ringing at the RTN pin during startup, inadvertent hot-plugs ofthe PoE input, or plugging in a wall adapter. It is recommended that a minimum value of 1 µF be used at theoutput of the TPS2375 if downstream filtering prevents placing the larger bulk capacitor right on the output. Whenusing ORing option 2, it is recommended that a large capacitor such as a 22 µF be placed across the TPS2375output.
Voltage transients on the TPS2375 can be caused by connecting or disconnecting the PD, or by otherenvironmental conditions like ESD. The TPS2375 is specified to operate with absolute maximum voltagesV
(VDD-VSS)
and V
(RTN-VSS)
of 100 V. A transient voltage suppressor, such as the SMAJ58A, should be installedafter the bridge and across the TPS2375 input as shown in Figure 1 . Various configurations of output filters andthe insertion of local power sources across either the TPS2375 input or output have the potential to causestresses outside the absolute maximum ratings of the device. Designers should be aware of this possibility andaccount for it in their circuit designs. For example, use adequate capacitance across the output to limit themagnitude of voltage ringing caused by downstream filters. Plugging an external power source across the outputmay cause ESD-like events. Some form of protection should be considered based on a study of the specificwaveforms seen in an application circuit.
The layout of the PoE front end must use good practices for power and EMI/ESD. A basic set ofrecommendations include:1. The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45 →Ethernettransformer →diode bridges →TVS and 0.1- µF capacitor →TPS2375 →output capacitor.2. There should not be any crossovers of signals from one part of the flow to another.3. All leads should be as short as possible with wide power traces and paired signal and return.4. Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltagerails and between the input and an isolated converter output.5. The TPS2375 should be over a local ground plane or fill area referenced to VSS to aid high-speed operation.6. Large SMT component pads should be used on power dissipating devices such as the diodes and theTPS2375.
Use of added copper on local power and ground to help the PCB spread and dissipate the heat is recommended.Pin 4 of the TPS2375 has the lowest thermal resistance to the die.
16 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2375 TPS2376 TPS2377
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2375D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2375PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2376PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2377PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jun-2008
Addendum-Page 1
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jun-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2375DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2375PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2376DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2376PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2377DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2377PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2375DR SOIC D 8 2500 340.5 338.1 20.6
TPS2375PWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2376DR SOIC D 8 2500 367.0 367.0 35.0
TPS2376PWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2377DR SOIC D 8 2500 367.0 367.0 35.0
TPS2377PWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated