PLESSEY SEMICONDUCTORS 12 D M@@ 7220513 0009823 1 mm > PLESSEY Semiconductors = TT 4S-(9-05 SP8743A asomuz 8/9 SP8743B soomnz = 8/9 The SP8743 is an ECL. counter with ECL 10K compatible outputs. It divides by 8 when either contro! input isin the high VW state and by 9 when both inputs are low (or open circuit). An euack wut 1 6H INTERNAL alas GECQUPLING AC coupled input of 600mV p-p is required. cawtnox weurs Pei [2 4s[) ne Fez (fo 14E] Wc FEATURES ne []s 13[] We M@ ECL Compatible Outputs err rap ve HM ECL Compatible Control Inputs i wif 00 Nor cownecr MAC Coupled Input (Internal Sias) wer toy) we auteur {je 9[] dorrur 0G16 QUICK REFERENCE DATA Fig.1 Pin connections - top view @ = Supply Voltage: -5.2V HB EPower Consumption: 240mw Ms Temperature Range: A Grade: -55C to +125C B Grade: -30C to +70C ABSOLUTE MAXIMUM RATINGS Supply voitage -8V Output current 20mA Storage temperature range -55C to +150C Max. junction temperature +175C Max. clock I/P voltage 2.5V p-p Vee(OV) me ne ae ee Ce sooo 5 7 | I ! | I ! | aa} a4 O8 OUTPUT | CONTROL INPUTS - | oe ae -98 oureuT I I CLOCK INPUT "0 Lo jo | 4 INTERNAL BIAS va DECOUPLING 140 Fig.2 Function diagram PLESSEY SEMICONDUCTORS IlcE D me 7220513 o00078&c4 3 SP8743A & B ELECTRICAL CHARACTERISTICS ._ i _-~ Supply Voltage: Vee = -5.2 + 0.25V. Vcc = OV - Je Lf): Temperature: A Grade Tamp = -55C to +125C T a [7 So B Grade Tam = -30C to +70C Characteristi Symbol Value units | Grade Conditions Notes Bracterisiic Min. Max. | Maximum frequency fmax 450 MHz A | Input = 400 - 800mV p-p Note 4 sinewave input 500 MHz B | Input = 400 - 800mV p-p Note 4 Minimum frequency fmin 40 MHz | Both | Input = 400 - 800mV p-p Note 5 sinewave input Power supply current lee 60 mA Both | Vee = -5,2V Note 6 ECL output high voltage Vou -0.85 -0.7 Vv Both | Vee = -5.2V(25 C) ECL output low voltage Vou -1.8 -1.5 Vv Both | Vee = -5.2V(26 C) PE input high voltage VINH -0.93 Vv Both | Vee = -5.2V (25C) PE input low voltage VINL ~1.62 V Both | Vee = -5.2V(25 C) Clock to ECL output delay te 6 ns Both Note 5 Set-up time ts 1 ns Both Note 5 Release time te 2.5 ns Both Note 5 NOTES 1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range. 2. The temperature coefficients of Vox = +1.63mV/C, Voi = +0.94mV/C and of Vin= +1 2amVv/C. 3. The test configuration for dynamic testing is shown in Fig.6. 4. Tested at low and high temperature only (not at 25C) 5. Guaranteed but not tested. 6. Tested at 25C only. clock Input TLL PLAS) TRUTH TABLE FOR CONTROL INPUTS a pg a __ __ Division _ 1 | pt PE1 PE2 Ratio PE INPUTS | I j ' ' L L 9 H L 8 5 4 L H 8 equ fT H | 4 8 Fig.3 Timing diagram NOTE The set-up time ts is defined as minimum time that can elapse between LH transition of control input and the next LH clock pulse transition to ensure that the +8 mode is obtained. The retease time t- is defined as the minimum time that can elapse between a H~*L transition of a control input and the next L*H clock pulse transition to ensure that the +9 mode is obtained. : AMA = -30C > * & ame 755C to +125 Tested as = specified in 2 Table of g Electrical a Characteristics 5 a Zz Q 100 200 400 400 450 500 (NPUT FREQUENCY (MHz) Fig.4 Typical input characteristics of SP8743 141 PLESSEY SEMICONDUCTORS JceE D SP8743A & B OPERATING NOTES 4. The clock input is biased internally and is coupled to the signal source with a suitable capacitor. The input signal path is completed by an input reference decoupling capacitor which is connected to earth. . 2. If no signal is present the device will self-oscillate. If this is undesirable it may be prevented by connecting a 15k resistor from the input to Vee (i.e. Pin 1 to Pin 12). This will reduce the input sensitivity by approximately 100mV. 3. The circuit will operate down to DC but slew rate must be better than 100V/us. Me 7220513 00098eS 5 TYS-/9-O5- 4. The Q and Q outputs are compatible with ECL Ii but can be interfaced to ECL 10K as shown in Fig. 7. There is an internal circuit equivalent to a load of 2k pulldown resistor at each output. 5. The PE inputs are ECL I!I/10K compatible and include a - 4.3k internal pulldown resistor. Unused inputs can therefore be left open circuit. 6. The input impedance of the SP8743 varies as a function of frequency. See Fig. 5. Fig.5 Typical input impedance. Test conditions: supply voltage -5.2V, ambient temperature 25 C, frequencies in MHz, impedances normalised to 50 ohms, OUTPUT TO SAMPLING SCOPE INPUT FROM __s 1 GENERATOR t a 16 TO SAMPLING og 38 * SCOPE ny Fig.6 Test circuit 142 PLESSEY SEMICONDUCTORS 126 D MM 7220513 00094cb 7? SP8743A & B in CLOCK INPUT oH TYE-/P-O5- Fig.7 Typical applications circuit showing interfacing 143