IRF630N - Fairchild Semiconductor

January 2002

Rev. B

IRF630N/IRF630NS/IRF630NL

N-Channel Power MOSFETs

200V, 9.3A, 0.30Ω

Features

• Ultra Low On-Resistance

-r

DS(ON) = 0.200Ω (Typ), VGS = 10V

• Simulation Models

- Temperature Compensated PSPICE® and SABER©

Electrical Models

- Spi ce and SABER© Thermal Impedance Models

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

MOSFET Maximum Ratings TA = 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

VDSS Drain to Source Voltage 200 V

VGS Gate to Source Voltage ±20 V

Drain Current 9.3 A

Continuous (TC = 25oC, VGS = 10V)

Continuous (TC = 100oC, VGS = 10V) 6.5 A

Pulsed Figure 4 A

EAS Single Pulse Avalanche Energy (Note 1) 94 mJ

PDPower dissipation

Derate above 25oC82

0.55 W

W/oC

TJ, TSTG Operating and Storage Temperature -55 to 175 oC

RθJC Thermal Resistance Junc tion to Case TO-220, TO-262, TO-263 1.83 oC/W

RθJA Ther mal Resistance Junction to Ambient TO-220, TO-262, TO-263 62 oC/W

RθJA Thermal Resistance Junction to Ambient T O-263, 1in2 copper pad area 40 oC/W

Device Marking Device Packag e Reel Size Tape Width Quantity

630N IRF630NS TO-263A B 330mm 24mm 800 units

630N IRF630NL TO-262AA Tube N/A 50

630N IRF630N TO-220AB Tube N/A 50

TO-220

GATE

SOURCE

DRAIN

(FLANGE)

DRAIN

(FLANGE)

DRAIN

SOURCE

GATE

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

TO-262TO-263

IRF630N/IRF630NS/IRF630NL

Electrical Characte ristics TA = 25°C unless otherwise noted

Off Characteristic s

On Characteri st ics

Dynamic Characteristics

Switching Charac te ristics (VGS = 10V)

Drain-Source Diode Characteristics

Notes:

1: Starting TJ = 25°C, L = 6.5mH, IAS = 5.4A.

2: Pulse width ≤ 400µs; duty cycle ≤ 2%.`

Symbol Parameter Test Conditions Min Typ Max Units

BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 200 - - V

IDSS Zero Gate Voltage Drain Current VDS = 200V VGS = 0V - - 25 µA

VDS = 160V TC = 150o- - 250

IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

rDS(ON) Drain to Source On Resistance ID = 5.4A, VGS = 10V - 0.200 0.300 Ω

gfs Forward Transconductance VDS = 50V, ID = 5.4A (Note 2) 49 - - S

CISS Input Capacitance VDS = 25V, VGS = 0V,

f = 1MHz

- 1030 - pF

COSS Output Capacitanc e - 120 - pF

CRSS Reverse Transfer Capacitance - 50 - pF

Qg(TOT) Total Gate Charge at 20V VGS = 0V to

20V

VDD = 100V

ID = 11A

Ig = 1.0mA

59 78 nC

Qg(10) Total Gate Charge at 10V VGS = 0V to

10V -3242nC

Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 2.0 3.2 nC

Qgs Gate to Source Gate Charge - 4.0 - nC

Qgd Gate to Drain “Miller” Charge - 11 - nC

tON Turn-On Time

VDD = 100V, ID = 5.4A

VGS = 10V, RGS = 13Ω

- - 32 ns

td(ON) Turn-On Delay Time - 9 - ns

trRise Time - 12 - ns

td(OFF) Turn-Off Delay Time - 71 - ns

tfFall Time - 19 - ns

tOFF Turn-Off T ime - - 135 ns

VSD Source to Drain Diode Voltage ISD = 5.4A - - 1.3 V

trr Reverse Recovery Time ISD = 5.4A, dISD/dt = 100A/µs - - 176 ns

QRR Reverse Recovered Charge ISD = 5.4A, dISD/dt = 100A/µs - - 813 nC

IRF630N/IRF630NS/IRF630NL

Typical Characteristic

Figure 1. Normalized Power Dissipation vs

Ambient Temperature Figure 2. Maxim um Contin uous Drain Current vs

Case Temperature

Figure 3. Normalized Maximum Transient Thermal Impedance

Figure 4. Peak Current Capability

TC, CASE TEMPERATURE (oC)

POWER DISSIPAT ION MULTIPLIER

00 25 50 75 100 175

0.2

0.4

0.6

0.8

1.0

1.2

125 150 0

25 50 75 100 125 150 175

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

VGS = 10V

0.1

10-5 10-4 10-3 10-2 10-1 100101

0.01

t, RECTANGULAR PULSE DURATION (s)

ZθJC, NORM ALIZED

THERMA L IMPEDANCE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

0.5

0.2

0.1

0.05

0.01

0.02

DUTY CYCLE - DESCENDING ORDER

SINGLE PULSE

100

200

10-4 10-3 10-2 10-1 100101

10-5

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 10V

IRF630N/IRF630NS/IRF630NL

Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching

Capability

Figure 7. Transfer Characteristic s Figure 8. Sat ura tion Char acteristics

Figure 9. Normalized Drain to Source On

Resistance vs Junction Temperature Figure 10. Normalized Gate Threshold Voltage vs

Junction Temperature

Typical Characteristic (Continued)

0.1

100

110100 500

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

TJ = MAX RATED

TC = 25oC

SINGLE PULSE

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

100µs

10ms

1ms

100

0.001 0.01 0.1 1 10

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

STARTING TJ = 150oC

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

2345

ID, DRAIN CURRENT (A)

VGS, GAT E TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

TJ = 175oC

TJ = 25oC

TJ = -55oC

012345

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS =4.5V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V

VGS = 5V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-80 -40 0 40 80 120 160 200

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

VGS = 10V, ID = 9.3A

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

THRESHOLD VOLTAGE

0.6

0.8

1.0

1.2

-80 -40 0 40 80 120 160 200

IRF630N/IRF630NS/IRF630NL

Figure 11. Normalized Drain to Source

Breakdow n Voltage vs Junc tion Tem peratu re Figure 12. Capacitance vs Drain to Source

Voltage

Figure 13. Gate Charge Waveforms for Constant Gate Currents

Typical Characteristic (Continued)

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

ID = 250µA

0.9

1.0

1.1

1.2

1.3

-80 -40 0 40 80 120 160 200 10

100

1000

0.1 1 10 100 200

3000

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≅ CDS + CGD

0 5 10 15 20 25 30 35

VGS, GATE TO SOURCE VOLTAG E (V)

VDD = 100V

Qg, GATE CHARGE (nC)

ID = 9.3A

ID = 5A

WAVEFORMS IN

DESCENDING ORDER:

Test Circuits and Waveforms

Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

IRF630N/IRF630NS/IRF630NL

Figure 16. Gate Charge Test Circuit Figure 17. Gate Charg e Wavef orms

Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms

Test Circuits and Waveforms (Continued)

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10)

VGS = 10V

Qg(TOT)

VGS = 20V

VDS

VGS

Ig(REF)

Qgs Qgd

VGS

RGS

DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

IRF630N/IRF630NS/IRF630NL

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, PDM, in an

application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJM is never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

power dissipation ratings. Precise determination of PDM is

complex and influenced by many factors:

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the pa rt,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 20

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper af ter 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Displayed on the curve are RθJA values listed in the

Electrical Specifications table. The points were chosen to

depict the compromise between the copper board area, the

thermal resistance and ultimately the power dissipation,

PDM.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 20 or by calculation using

Equation 2. RθJA is defined as the natural log of the area

times a coefficient added to a constant. The area, in square

inches is the top copper area including the gate and source

pads.

(EQ. 1

)

PDM

TJM TA

–()

ZθJA

-----------------------------=

(EQ. 2

)

RθJA 26.51 19.84

0.262 Area+()

-------------------------------------+

Figure 20. Thermal Resistance vs Mounting

Pad Area

110

0.1

RθJA = 26.51+ 19.84/(0.262+Area )

RθJA (oC/W)

AREA, TOP COPPER AREA (in2)

IRF630N/IRF630NS/IRF630NL

PSPICE Ele ctrical Model

.SUBC K T IRF630N 2 1 3 ; rev May 20 01

CA 12 8 1. 6e - 9

CB 15 14 1.75e-9

CIN 6 8 9.3e - 8

DBODY 7 5 DBODYMOD

DBRE AK 5 11 D B REAK MOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 227

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTHRES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRA IN 2 5 1e- 9

LGATE 1 9 5.12e-9

LSOURCE 3 7 4.24e-9

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 M ST R O M OD

MWEA K 16 21 8 8 MWEAK MOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 1.98e-1

RGATE 9 20 1.61

RLDRAIN 2 5 10

RLGATE 1 9 51.2

RLSOURCE 3 7 42.4

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 1e-2

RVTHRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BM OD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMO D

VBAT 22 1 9 DC 1

ESL C 51 50 VA L U E={(V(5,5 1)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*19),2.5))}

.MODEL DBODYMOD D (I S = 1e-12 N=1.02 RS = 7.75e-3 TRS1 = 2.5e-3 TRS2 = 2e-5 CJO = 8.5e-10 TT = 9.6e-6 M = 0.61

XTI=5.5)

.MODEL DBREAKMOD D (RS = 4. 2TRS1 = 1e- 3TRS2 = -8.9e-6)

.MODEL DPLCAPMOD D (CJO = 1.15e- 9IS = 1e-30 N = 10 M = 0.86)

.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.61)

.MODEL MSTROMOD NMOS (VTO = 3.65 KP = 28 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMO D N M O S (VTO = 2 .8 KP = 0.05 IS = 1e-30 N = 1 0 T OX = 1 L = 1u W = 1u RG = 16.1 RS= .1)

.MODEL RBREAKMOD RES (TC1 =1.3e- 3TC2 = 2e-6)

.MODEL RDRAINMOD RES (TC1 = 1e- 2TC2 = 3.7e-5)

.MODEL RSLCMOD RES (TC1 = 4e-3 TC2 = 1e-6)

.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6 )

.MODE L RVTHRES MOD RES (T C1 = -2e-3 TC2 = -1.3e-5)

.MODEL RVTEMPMOD RES (TC1 = -3e- 3TC2 = 1.9e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.5 VOFF= -.5)

.MODEL S1B MOD VSWITCH (RON = 1 e-5 ROFF = 0.1 VON = -.5 VOFF= -7.5 )

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.2)

.MODEL S2B MOD VSWITC H (RON = 1 e-5 ROFF = 0.1 VON = 0.2 VOFF= -0 .1)

.ENDS

NO TE: For further discu ssion of the PS PICE model, co nsult A New PSPICE Sub-Cir cuit for the P ower MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURC

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

IRF630N/IRF630NS/IRF630NL

SABER Electrical Model

REV May 2001

template IRF630N n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl = 1e-12, rs = 7.75e-3, xti = 5.5, trs1 = 2.5e-3, trs2 = 2e-5, cjo = 8.5e-10, tt = 9.6e-6, m = 0.61)

dp..model dbreakmod = (rs = 4.2, trs1 = 1e-3, trs2 = -8.9e-6)

dp..mo del dplcapmod = (cjo = 1.15e-9, isl = 10e-30, nl=10, m = 0.86)

m..model mmedmod = (type=_n, vto = 3.25, kp = 5, isl = 1e-30, tox = 1)

m..model mstrongmod = (type=_n, vto = 3.65, kp = 28, isl = 1e-30, tox = 1)

m..model mweakmod = (ty pe=_n, vto = 2.8 , kp = 0.05, isl = 1e-30, tox = 1, rs=0.1)

sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.5, voff = -.5)

sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.5, voff = -7.5)

sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2)

sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1)

c.ca n12 n8 = 1.6e-9

c.cb n15 n14 = 1.75e-9

c.cin n6 n8 = 9.3e-8

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 5.12e-9

l.lsourc e n3 n7 = 4.24e-9

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.r break n17 n18 = 1, tc1 = 1. 3e-3, tc2 = 2e-6

res.rdrain n50 n16 = 1.98e-5, tc1 = 1e-2, tc2 =3.7e-5

res.rgate n9 n20 = 1.61

res.r ldrain n2 n5 = 10

res.rlgate n1 n9 = 51.2

res.rlsource n3 n7 = 42.4

res.rs lc1 n5 n51= 1e-6, tc1 = 4e-3, tc2 = -1e-6

res.r slc2 n5 n50 = 1e3

res.rs ource n8 n7 = 10e-3, tc1 = 1e-3, tc2 =1e-6

res.rv temp n18 n19 = 1, tc1 = -2e-3, tc2 = -1.3e-5

res.rvthres n22 n8 = 1, tc1 = -3e-3, tc2 = 1.9e-6

spe.ebreak n11 n7 n17 n18 = 227

spe.e ds n14 n8 n5 n8 = 1

spe.e gs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n1 3 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51) )))*((abs(v(n5,n51)*1e6*19))* * 2.5))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK

DBODY

RSOURCE

SOURC

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

IRF630N/IRF630NS/IRF630NL

SPICE Thermal Model

REV May 2001

IRF630N

CTHERM1 th 6 8.0e-4

CTHERM2 6 5 2.6e-3

CTHERM3 5 4 3.5e-3

CTHERM4 4 3 5.2e-3

CTHERM5 3 2 7.0e-3

CTHERM6 2 tl 3.3e-2

RTHERM1 th 6 1.0e-3

RTHERM2 6 5 4.5e-3

RTHERM3 5 4 4.2e-2

RTHERM4 4 3 2.5e-1

RTHERM5 3 2 3.9e-1

RTHERM6 2 tl 5.0e-1

SABER Thermal Model

SABER thermal model IRF630N

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 6 = 8.0e-4

cthe rm .cth er m 2 6 5 = 2.6e-3

cthe rm .cth er m 3 5 4 = 3.5e-3

cthe rm .cth er m 4 4 3 = 5.2e-3

cthe rm .cth er m 5 3 2 = 7.0e-3

ctherm.ctherm6 2 tl = 3.3e-2

rtherm.rtherm1 th 6 = 1.0e-3

rtherm.rtherm2 6 5 = 4.5e-3

rtherm.rtherm3 5 4 = 4.2e-2

rtherm.rtherm4 4 3 = 2.5e-1

rtherm.rtherm5 3 2 = 3.9e-1

rtherm.rtherm6 2 tl = 5.0e-1

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

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not intended to be an exhaustive list of all such trademarks.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

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systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

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

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STAR*POWER™

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

STAR*POWER is used under license

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