February 2008 Rev 7 1/32
32
VN5016AJ-E
Single channel high side driver with analog
current sense for automotive applications
Features
■Main features
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
■Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
■Protection
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shut down
– Reverse battery protection
– Electrostatic discharge protection
Application
■All types of resistive, inductive and capacitive
loads
Description
The VN5016AJ-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table). This device
integrates an analog current sense which delivers
a current proportional to the load current
(according to a known ratio) when CS_DIS is
driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Max supply voltage VCC 41V
Operating voltage range VCC 4.5 to 36V
Max On-State resistance (per ch.)
RON 16 mΩ
Current limitation (typ) ILIMH 65A
Off state supply current IS2 µA
PowerSSO-12
Table 1. Device summary
Package Order codes
Tube Tape & Reel
PowerSSO-12 VN5016AJ-E VN5016AJTR-E
www.st.com
Contents VN5016AJ-E
2/32
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 22
3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 23
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 24
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VN5016AJ-E List of tables
3/32
List of tables
Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of figures VN5016AJ-E
4/32
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6. IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. On state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. Turn - On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Turn - Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Maximum turn Off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 25
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 26
Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 26
Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VN5016AJ-E Block diagram and pin description
5/32
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Pin function
Name Function
VCC Battery connection.
OUTPUT Power output.
GND Ground connection. Must be reverse battery protected by an external
diode/resistor network.
INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
CURRENT
SENSE Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
LOGIC
UNDERVOLTAGE
OVERTEMP.
ILIM
PwCLAMP
K
IOUT
GND
INPUT
VCC
OUTPUT
CURRENT
SENSE
DRIVER
VCC
CLAMP
VDSLIM
CS_DIS
PwrLIM
Block diagram and pin description VN5016AJ-E
6/32
Figure 2. Configuration diagram (top view)
Table 3. Suggested connections for unused and N.C. pins
Connection / Pin Current Sense N.C. Output Input CS_DIS
Floating N.R.(1) XX X X
To ground Through 1KΩ
resistor XN.R.
(1)
(1) Not recommended.
Through 10KΩ
resistor
Through 10KΩ
resistor
TAB = V
cc
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
12
11
10
9
8
7
1
2
3
4
5
6
V
CC
V
CC
INPUT
CURRENT SENSE
GND
CS_DIS
VN5016AJ-E Electrical specifications
7/32
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
I
S
I
GND
V
CC
V
CC
V
SENSE
OUTPUT
I
OUT
CURRENT SENSE
I
SENSE
INPUT
I
IN
V
IN
V
OUT
GND
CS_DIS
I
CSD
V
CSD
V
F
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
-IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current 30 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC reverse CS pin current 200 mA
VCSENSE Current sense maximum voltage VCC-41
+VCC
V
V
EMAX
Maximum switching energy
(L=0.75mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC;
IOUT = IlimL(Typ.) )
304 mJ
Electrical specifications VN5016AJ-E
8/32
2.2 Thermal data
VESD
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
- INPUT
- CURRENT SENSE
- CS_DIS
- OUTPUT
- VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter Max value Unit
Rthj-case Thermal resistance junction-case 0.5 °C/W
Rthj-amb Thermal resistance junction-ambient See Figure 29 °C/W
VN5016AJ-E Electrical specifications
9/32
2.3 Electrical characteristics
8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.
.
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4.5 13 36 V
VUSD Undervoltage shutdown 3.5 4.5 V
VUSDhyst
Undervoltage Shut-down
hysteresis 0.5 V
RON On state resistance
IOUT= 5A; Tj= 25°C
IOUT= 5A; Tj= 150°C
IOUT= 5A; VCC= 5V; Tj= 25°C
16
32
20
mΩ
mΩ
mΩ
Vclamp Clamp voltage IS= 20mA 41 46 52 V
ISSupply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V;
IOUT=0A
2(1)
1.5
(1) PowerMOS leakage included.
5(1)
3
µA
mA
IL(off) Off state output current
VIN=VOUT=0V; VCC=13V;
Tj=25°C
VIN=VOUT=0V; VCC=13V;
Tj=125°C
0
0
0.01 3
5
µA
VF
Output - VCC diode
voltage IOUT= 6A; Tj= 150°C 0.7 V
Table 7. Switching (VCC=13V, Tj=25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-On delay time RL= 2.6Ω (see Figure 8)35µs
td(off) Turn-Off delay time RL= 2.6Ω (see Figure 8)50µs
(dV
OUT
/dt)
on
Turn-On voltage slope RL= 2.6Ω (see Figure 8)See Figure 20 V/µs
(dV
OUT
/dt)
off
Turn-Off voltage slope RL= 2.6Ω (see Figure 8)See Figure 22 V/µs
WON
Switching energy losses
during twon
RL= 2.6Ω (see Figure 8)1.1mJ
WOFF
Switching energy losses
during twoff
RL= 2.6Ω (see Figure 8)0.8mJ
Electrical specifications VN5016AJ-E
10/32
Table 8. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
IIL Low level input current VIN=0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN=2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
VICL Input clamp voltage IIN=1mA
IIN=-1mA
5.5
-0.7
7V
V
VCSDL CS_DIS low level voltage 0.9 V
ICSDL
Low level CS_DIS
current VCSD=0.9V 1 µA
VCSDH
CS_DIS high level
voltage 2.1 V
ICSDH
High level CS_DIS
current VCSD=2.1V 10 µA
VCSD(hyst)
CS_DIS hysteresis
voltage 0.25 V
VCSCL CS_DIS clamp voltage ICSD=1mA
ICSD=-1mA
5.5
-0.7
7V
V
Table 9. Protections and diagnostics (1)
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC=13V
5V<VCC<36V
46 65 91
91
A
A
IlimL
Short circuit current
during thermal cycling VCC=13V TR<Tj<TTSD 24 A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature
T
R
S +1 TRS +5 °C
TRS
Thermal reset of
STATUS 135 °C
THYST
Thermal hysteresis
(T
TSD
-T
R
)
7°C
VDEMAG
Turn-Off output voltage
clamp IOUT=2A; VIN=0; L=6mH
V
CC
-41
VCC-46
V
CC
-52
V
VON
Output voltage drop
limitation
IOUT=0.3A;
Tj= -40°C...+150°C
(see Figure 9)
25 mV
VN5016AJ-E Electrical specifications
11/32
Table 10. Current sense (8V<VCC<16V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K0IOUT/ISENSE
IOUT=0.25A;
VSENSE=0.5V;VCSD=0V;
Tj= -40°C...150°C
2760 5010 7240
K1IOUT/ISENSE
IOUT=4A; VSENSE=0.5V;
VCSD=0V;
Tj= -40°C...150°C
IOUT=4A; VSENSE=0.5V;
VCSD=0V;
Tj= 25°C...150°C
3510
3770
4560
4560
5690
5350
dK1/K1(1) Current sense ratio drift
IOUT=4A; VSENSE= 0.5V;
VCSD=0V;
TJ=-40 °C to 150 °C
-8 +8 %
K2IOUT/ISENSE
IOUT=10A; VSENSE=4V;
VCSD=0V;
Tj=-40°C...150°C
IOUT=10A; VSENSE=4V;
VCSD=0V;
Tj=25°C...150°C
4180
4250
4570
4570
5060
4890
dK2/K2(1) Current sense ratio drift
IOUT=10A; VSENSE= 4V;
VCSD=0V;
TJ=-40 °C to 150 °C
-4 +4 %
K3IOUT/ISENSE
IOUT=25A; VSENSE=4V;
VCSD=0V;
Tj= -40°C...150°C
IOUT=25A; VSENSE=4V;
VCSD=0V;
Tj= 25°C...150°C
4360
4380
4500
4500
4700
4620
dK3/K3(1) Current sense ratio drift
IOUT=25A; VSENSE= 4V;
VCSD=0V;
TJ=-40 °C to 150 °C
-3 +3 %
ISENSE0
Analog sense leakage
current
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V;
Tj=-40°C...150°C
VCSD=0V; VIN=5V;
Tj=-40°C...150°C
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V;
Tj=-40°C...150°C
0
0
0
1
2
1
µA
µA
µA
IOL
Openload ON state
current detection
threshold
VIN = 5V, ISENSE= 5 µA 10 45 mA
Electrical specifications VN5016AJ-E
12/32
VSENSE
Max analog sense
output voltage IOUT=15A; VCSD=0V; 5 V
VSENSEH
Analog sense output
voltage in
overtemperature
condition
VCC=13V; RSENSE=3.9KΩ9V
ISENSEH
Analog sense output
current in
overtemperature
condition
VCC=13V; VSENSE=5V 8 mA
tDSENSE1H
Delay response time
from falling edge of
CS_DIS pin
VSENSE<4V, 1.5A<Iout<25A
ISENSE= 90% of ISENSE max
(see Figure 4)
50 100 µs
tDSENSE1L
Delay response time
from rising edge of
CS_DIS pin
VSENSE<4V, 1.5A<Iout<25A
ISENSE= 10% of ISENSE max
(see Figure 4)
520µs
tDSENSE2H
Delay response time
from rising edge of
INPUT pin
VSENSE<4V, 1.5A<Iout<25A
ISENSE= 90% of ISENSE max
(see Figure 4)
270 400 µs
∆
t
DSENSE2H
Delay response time
between rising edge of
output current and rising
edge of current sense
VSENSE <4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=15A (see Figure 5)
280 µs
tDSENSE2L
Delay response time
from falling edge of
INPUT pin
VSENSE<4V, 1.5A<Iout<25A
ISENSE=10% of ISENSE max
(see Figure 4)
100 250 µs
(1) Parameter guaranteed by design; it is not tested.
Table 10. Current sense (8V<VCC<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VN5016AJ-E Electrical specifications
13/32
Figure 4. Current sense delay characteristics
Figure 5. Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
tDSENSE2H tDSENSE2L
tDSENSE1L tDSENSE1H
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
∆
t
DSENSE2H
t
t
t
Electrical specifications VN5016AJ-E
14/32
Figure 6. IOUT/ISENSE Vs. IOUT (see Ta bl e 1 0 for details)
Figure 7. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
3000
3500
4000
4500
5000
5500
6000
4 8 12 16 20 24
IOUT (A)
Iout / Isense
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
-15
-10
-5
0
5
10
15
4 7 10 13 16 19 22 25
IOUT (A)
dk/k(%)
VN5016AJ-E Electrical specifications
15/32
Figure 8. Switching characteristics
Figure 9. Output voltage drop limitation
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
Von
Iout
Vcc-Vout
Tj=150oCTj=25oC
Tj=-40oC
Von/Ron(T)
Electrical specifications VN5016AJ-E
16/32
Table 11. Truth table
Conditions Input Output Sense (VCSD=0V) (1)
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
0
Nominal
Overtemperature L
H
L
L
0
VSENSEH
Undervoltage L
H
L
L
0
0
Short circuit to GND
(Rsc ≤ 10 mΩ)
L
H
H
L
L
L
0
0 if Tj < TTSD
VSENSEH if Tj > TTSD
Short circuit to VCC
L
H
H
H
0
< Nominal
Negative output voltage clamp L L 0
VN5016AJ-E Electrical specifications
17/32
Table 12. Electrical transient requirements
ISO 7637-2:
2004(E)
Test pulse
Test levels (1) Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
III IV
1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37V +50V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 -6V -7V 1 pulse 100 ms, 0.01Ω
5b (2) +65V +87V 1 pulse 400 ms, 2 Ω
ISO 7637-2:
2004(E)
Test pulse
Test level results (1)
(1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
III IV
1C C
2a C C
3a C C
3b C C
4C C
5b (2)
(2) Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Electrical specifications VN5016AJ-E
18/32
Figure 10. Waveforms
SENSE CURRENT
INPUT
NORMAL OPERATION
UNDERVOLTAGE
VCC VUSD
VUSDhyst
INPUT
SENSE CURRENT
LOAD CURRENT
LOAD CURRENT
OVERLOAD OPERATION
INPUT
SENSE CURRENT
T
TSD
T
R
Tj
LOAD CURRENT
INPUT
LOAD VOLTAGE
SENSE CURRENT
LOAD CURRENT
<Nominal <Nominal
SHORT TO VCC
CS_DIS
CS_DIS
CS_DIS
CS_DIS
T
RS
ILIMH
ILIML
VSENSEH
thermal cycling
power
limitation
current
limitation
SHORTED LOAD NORMAL LOAD
VN5016AJ-E Electrical specifications
19/32
2.4 Electrical characteristics curves
Figure 11. Off state output current Figure 12. High level input current
Figure 13. Input clamp voltage Figure 14. Input low level
Figure 15. Input high level Figure 16. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Ilo ff (u A )
Off State
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
T
c
(
°
C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA )
Vin=2.1V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
Vicl (V)
Ii n =1 m A
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
0.5
1
1.5
2
2.5
3
3.5
4
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
0.5
1
1.5
2
2.5
3
3.5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Vhyst (V)
Electrical specifications VN5016AJ-E
20/32
Figure 17. On state resistance vs. Tcase Figure 18. On state resistance vs. VCC
Figure 19. Undervoltage shutdown Figure 20. Turn - On voltage slope
Figure 21. ILIMH vs. Tcase Figure 22. Turn - Off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
5
10
15
20
25
30
35
40
45
50
Ron (mOhm)
Io u t =5A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
5
10
15
20
25
30
35
40
Ron (mOhm)
Tc= -40°C v
Tc= 25°C
Tc= 125°C
Tc= 150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
2
4
6
8
10
12
14
16
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
100
200
300
400
500
600
700
800
900
1000
dV out/dt(on) (V /ms )
Vcc=13V
RI=2.6Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
40
45
50
55
60
65
70
75
80
Ilimh (A )
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt)off (V/ms)
Vc c=13V
Rl=2.6Ohm
VN5016AJ-E Electrical specifications
21/32
Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage
Figure 25. CS_DIS low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
0.5
1
1.5
2
2.5
3
3.5
4
Vcsdh (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
4
4.5
5
5.5
6
6.5
7
7.5
8
Vcsdcl (V)
Ic s d =1m A
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
0.5
1
1.5
2
2.5
3
3.5
4
Vcsdl (V)
Application Information VN5016AJ-E
22/32
3 Application Information
Figure 26. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max).
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
µC
+5V
V
GND
CS_DIS
INPUT
R
prot
R
prot
CURRENT SENSE
R
SENSE
R
prot
C
ext
VN5016AJ-E Application Information
23/32
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2 : diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values: Rprot =10kΩ, CEXT=10nF.
Application Information VN5016AJ-E
24/32
3.4 Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn Off current versus load inductance
Note: Values are generated with RL=0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves B and C.
VIN, IL
t
Demagnetization Demagnetization Demagnetization
1
10
100
0,1 1 10 100L (mH)
I (A)
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
A
B
C
VN5016AJ-E Package and PCB thermal data
25/32
4 Package and PCB thermal data
4.1 PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 29. Rthj-amb vs. PCB copper area in open box free air condition
30
35
40
45
50
55
60
65
0246810
RTHj_amb(°C/W)
PCB Cu heatsink area (cm^2)
Package and PCB thermal data VN5016AJ-E
26/32
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse
Equation 1: pulse calculation formula
where δ = tP/T
Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ (a)
(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
0,1
1
10
100
0,0001 0,001 0,01 0,1 1 10 100 1000
Time (s)
ZTH (°C/W)
8 cm
2
Footprint
2 cm
2
ZTHδRTH δZTHtp 1δ–()+⋅=
VN5016AJ-E Package and PCB thermal data
27/32
Table 13. Thermal parameter
Area/island (cm2)Footprint28
R1 (°C/W) 0.1
R2 (°C/W) 0.2
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1 (W.s/°C) 0.0001
C2 (W.s/°C) 0.002
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
Package information VN5016AJ-E
28/32
5 Package information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2 PowerSSO-12™ package information
Figure 32. PowerSSO-12™ package dimensions
VN5016AJ-E Package information
29/32
Table 14. PowerSSO-12™ mechanical data
Symbol
Millimeters
Min. Typ. Max.
A 1.250 1.620
A1 0.000 0.100
A2 1.100 1.650
B 0.230 0.410
C 0.190 0.250
D 4.800 5.000
E 3.800 4.000
e0.800
H 5.800 6.200
h 0.250 0.500
L 0.400 1.270
k0° 8°
X 1.900 2.500
Y 3.600 4.200
ddd 0.100
Package information VN5016AJ-E
30/32
5.3 PowerSSO-12™ packing information
Figure 33. PowerSSO-12™ tube shipment (no suffix)
Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
VN5016AJ-E Revision history
31/32
6 Revision history
Table 15. Document revision history
Date Revision Changes
30-Oct-2004 1 Initial release.
15-Jan-2005 2 Minor text changes.
11-May-2006 3 Document changed from Advance Data to maturity.
02-Feb-2007 4
Changes minor formatting.
Added Figure 27: Maximum turn Off current versus load
inductance.
Added new disclaimer.
02-Jul-2007 5
Ta bl e 4 : updated EMAX entries.
Ta bl e 1 0 : added dk1/k1, dk2/k2, dk3/k3, ∆tDSEN
SE
2H.
Added Figure 5.
Updated Figure 6.
Added Figure 7.
Ta bl e 1 2 : updated test level values III and IV for test pulse 5b and
notes.
Added Section 3.4: Maximum demagnetization energy (VCC =
13.5V).
Figure 31: Thermal fitting model of a single channel HSD in
PowerSSO-12™: added notes.
09-Jan-2007 6
Updated Table 10: Current sense (8V<VCC<16V) :
– Changed dK3/K3 values from ± 2 to ± 3 %.
– Added IOL parameter.
– Changed ∆tDSEN
SE
2H max value from 120 to 280 µs.
Updated Figure 7: Maximum current sense ratio drift vs load
current with new dK/K values.
Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 29: Rthj-amb vs. PCB copper area in open box
free air condition.
– Changed Figure 30: PowerSSO-12™ thermal impedance
junction ambient single pulse.
– Updated Table 13: Thermal parameter:
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
12-Feb-2008 7 Corrected typing error in Table 10: Current sense (8V<VCC<16V) :
changed IOL test condition from VIN = 0V to VIN = 5V.
VN5016AJ-E
32/32
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